diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/device.h | 7 | ||||
| -rw-r--r-- | include/linux/mfd/abx500/ab8500-gpio.h | 16 | ||||
| -rw-r--r-- | include/linux/mfd/abx500/ab8500.h | 279 | ||||
| -rw-r--r-- | include/linux/pinctrl/devinfo.h | 45 | ||||
| -rw-r--r-- | include/linux/pinctrl/pinconf-generic.h | 16 | ||||
| -rw-r--r-- | include/linux/pinctrl/pinctrl.h | 1 |
6 files changed, 303 insertions, 61 deletions
diff --git a/include/linux/device.h b/include/linux/device.h index 43dcda937ddf..001f6637aa47 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -21,6 +21,7 @@ #include <linux/compiler.h> #include <linux/types.h> #include <linux/mutex.h> +#include <linux/pinctrl/devinfo.h> #include <linux/pm.h> #include <linux/atomic.h> #include <linux/ratelimit.h> @@ -620,6 +621,8 @@ struct acpi_dev_node { * @pm_domain: Provide callbacks that are executed during system suspend, * hibernation, system resume and during runtime PM transitions * along with subsystem-level and driver-level callbacks. + * @pins: For device pin management. + * See Documentation/pinctrl.txt for details. * @numa_node: NUMA node this device is close to. * @dma_mask: Dma mask (if dma'ble device). * @coherent_dma_mask: Like dma_mask, but for alloc_coherent mapping as not all @@ -672,6 +675,10 @@ struct device { struct dev_pm_info power; struct dev_pm_domain *pm_domain; +#ifdef CONFIG_PINCTRL + struct dev_pin_info *pins; +#endif + #ifdef CONFIG_NUMA int numa_node; /* NUMA node this device is close to */ #endif diff --git a/include/linux/mfd/abx500/ab8500-gpio.h b/include/linux/mfd/abx500/ab8500-gpio.h index 2387c207ea86..172b2f201ae0 100644 --- a/include/linux/mfd/abx500/ab8500-gpio.h +++ b/include/linux/mfd/abx500/ab8500-gpio.h @@ -14,10 +14,20 @@ * registers. */ -struct ab8500_gpio_platform_data { +struct abx500_gpio_platform_data { int gpio_base; - u32 irq_base; - u8 config_reg[8]; +}; + +enum abx500_gpio_pull_updown { + ABX500_GPIO_PULL_DOWN = 0x0, + ABX500_GPIO_PULL_NONE = 0x1, + ABX500_GPIO_PULL_UP = 0x3, +}; + +enum abx500_gpio_vinsel { + ABX500_GPIO_VINSEL_VBAT = 0x0, + ABX500_GPIO_VINSEL_VIN_1V8 = 0x1, + ABX500_GPIO_VINSEL_VDD_BIF = 0x2, }; #endif /* _AB8500_GPIO_H */ diff --git a/include/linux/mfd/abx500/ab8500.h b/include/linux/mfd/abx500/ab8500.h index 1cb5698b4d76..fc0534483c72 100644 --- a/include/linux/mfd/abx500/ab8500.h +++ b/include/linux/mfd/abx500/ab8500.h @@ -24,7 +24,7 @@ enum ab8500_version { AB8500_VERSION_AB8500 = 0x0, AB8500_VERSION_AB8505 = 0x1, AB8500_VERSION_AB9540 = 0x2, - AB8500_VERSION_AB8540 = 0x3, + AB8500_VERSION_AB8540 = 0x4, AB8500_VERSION_UNDEFINED, }; @@ -32,6 +32,7 @@ enum ab8500_version { #define AB8500_CUTEARLY 0x00 #define AB8500_CUT1P0 0x10 #define AB8500_CUT1P1 0x11 +#define AB8500_CUT1P2 0x12 /* Only valid for AB8540 */ #define AB8500_CUT2P0 0x20 #define AB8500_CUT3P0 0x30 #define AB8500_CUT3P3 0x33 @@ -39,6 +40,7 @@ enum ab8500_version { /* * AB8500 bank addresses */ +#define AB8500_M_FSM_RANK 0x0 #define AB8500_SYS_CTRL1_BLOCK 0x1 #define AB8500_SYS_CTRL2_BLOCK 0x2 #define AB8500_REGU_CTRL1 0x3 @@ -58,6 +60,7 @@ enum ab8500_version { #define AB8500_DEVELOPMENT 0x11 #define AB8500_DEBUG 0x12 #define AB8500_PROD_TEST 0x13 +#define AB8500_STE_TEST 0x14 #define AB8500_OTP_EMUL 0x15 /* @@ -65,11 +68,11 @@ enum ab8500_version { * Values used to index into array ab8500_irq_regoffset[] defined in * drivers/mdf/ab8500-core.c */ -/* Definitions for AB8500 and AB9540 */ +/* Definitions for AB8500, AB9540 and AB8540 */ /* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */ #define AB8500_INT_MAIN_EXT_CH_NOT_OK 0 /* not 8505/9540 */ -#define AB8500_INT_UN_PLUG_TV_DET 1 /* not 8505/9540 */ -#define AB8500_INT_PLUG_TV_DET 2 /* not 8505/9540 */ +#define AB8500_INT_UN_PLUG_TV_DET 1 /* not 8505/9540/8540 */ +#define AB8500_INT_PLUG_TV_DET 2 /* not 8505/9540/8540 */ #define AB8500_INT_TEMP_WARM 3 #define AB8500_INT_PON_KEY2DB_F 4 #define AB8500_INT_PON_KEY2DB_R 5 @@ -77,18 +80,19 @@ enum ab8500_version { #define AB8500_INT_PON_KEY1DB_R 7 /* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */ #define AB8500_INT_BATT_OVV 8 -#define AB8500_INT_MAIN_CH_UNPLUG_DET 10 /* not 8505 */ -#define AB8500_INT_MAIN_CH_PLUG_DET 11 /* not 8505 */ +#define AB8500_INT_MAIN_CH_UNPLUG_DET 10 /* not 8505/8540 */ +#define AB8500_INT_MAIN_CH_PLUG_DET 11 /* not 8505/8540 */ #define AB8500_INT_VBUS_DET_F 14 #define AB8500_INT_VBUS_DET_R 15 /* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */ #define AB8500_INT_VBUS_CH_DROP_END 16 #define AB8500_INT_RTC_60S 17 #define AB8500_INT_RTC_ALARM 18 +#define AB8540_INT_BIF_INT 19 #define AB8500_INT_BAT_CTRL_INDB 20 #define AB8500_INT_CH_WD_EXP 21 #define AB8500_INT_VBUS_OVV 22 -#define AB8500_INT_MAIN_CH_DROP_END 23 /* not 8505/9540 */ +#define AB8500_INT_MAIN_CH_DROP_END 23 /* not 8505/9540/8540 */ /* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */ #define AB8500_INT_CCN_CONV_ACC 24 #define AB8500_INT_INT_AUD 25 @@ -99,7 +103,7 @@ enum ab8500_version { #define AB8500_INT_BUP_CHG_NOT_OK 30 #define AB8500_INT_BUP_CHG_OK 31 /* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */ -#define AB8500_INT_GP_HW_ADC_CONV_END 32 /* not 8505 */ +#define AB8500_INT_GP_HW_ADC_CONV_END 32 /* not 8505/8540 */ #define AB8500_INT_ACC_DETECT_1DB_F 33 #define AB8500_INT_ACC_DETECT_1DB_R 34 #define AB8500_INT_ACC_DETECT_22DB_F 35 @@ -108,23 +112,23 @@ enum ab8500_version { #define AB8500_INT_ACC_DETECT_21DB_R 38 #define AB8500_INT_GP_SW_ADC_CONV_END 39 /* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */ -#define AB8500_INT_GPIO6R 40 /* not 8505/9540 */ -#define AB8500_INT_GPIO7R 41 /* not 8505/9540 */ -#define AB8500_INT_GPIO8R 42 /* not 8505/9540 */ -#define AB8500_INT_GPIO9R 43 /* not 8505/9540 */ -#define AB8500_INT_GPIO10R 44 -#define AB8500_INT_GPIO11R 45 -#define AB8500_INT_GPIO12R 46 /* not 8505 */ -#define AB8500_INT_GPIO13R 47 +#define AB8500_INT_GPIO6R 40 /* not 8505/9540/8540 */ +#define AB8500_INT_GPIO7R 41 /* not 8505/9540/8540 */ +#define AB8500_INT_GPIO8R 42 /* not 8505/9540/8540 */ +#define AB8500_INT_GPIO9R 43 /* not 8505/9540/8540 */ +#define AB8500_INT_GPIO10R 44 /* not 8540 */ +#define AB8500_INT_GPIO11R 45 /* not 8540 */ +#define AB8500_INT_GPIO12R 46 /* not 8505/8540 */ +#define AB8500_INT_GPIO13R 47 /* not 8540 */ /* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */ -#define AB8500_INT_GPIO24R 48 /* not 8505 */ -#define AB8500_INT_GPIO25R 49 /* not 8505 */ -#define AB8500_INT_GPIO36R 50 /* not 8505/9540 */ -#define AB8500_INT_GPIO37R 51 /* not 8505/9540 */ -#define AB8500_INT_GPIO38R 52 /* not 8505/9540 */ -#define AB8500_INT_GPIO39R 53 /* not 8505/9540 */ -#define AB8500_INT_GPIO40R 54 -#define AB8500_INT_GPIO41R 55 +#define AB8500_INT_GPIO24R 48 /* not 8505/8540 */ +#define AB8500_INT_GPIO25R 49 /* not 8505/8540 */ +#define AB8500_INT_GPIO36R 50 /* not 8505/9540/8540 */ +#define AB8500_INT_GPIO37R 51 /* not 8505/9540/8540 */ +#define AB8500_INT_GPIO38R 52 /* not 8505/9540/8540 */ +#define AB8500_INT_GPIO39R 53 /* not 8505/9540/8540 */ +#define AB8500_INT_GPIO40R 54 /* not 8540 */ +#define AB8500_INT_GPIO41R 55 /* not 8540 */ /* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */ #define AB8500_INT_GPIO6F 56 /* not 8505/9540 */ #define AB8500_INT_GPIO7F 57 /* not 8505/9540 */ @@ -135,14 +139,14 @@ enum ab8500_version { #define AB8500_INT_GPIO12F 62 /* not 8505 */ #define AB8500_INT_GPIO13F 63 /* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */ -#define AB8500_INT_GPIO24F 64 /* not 8505 */ -#define AB8500_INT_GPIO25F 65 /* not 8505 */ -#define AB8500_INT_GPIO36F 66 /* not 8505/9540 */ -#define AB8500_INT_GPIO37F 67 /* not 8505/9540 */ -#define AB8500_INT_GPIO38F 68 /* not 8505/9540 */ -#define AB8500_INT_GPIO39F 69 /* not 8505/9540 */ -#define AB8500_INT_GPIO40F 70 -#define AB8500_INT_GPIO41F 71 +#define AB8500_INT_GPIO24F 64 /* not 8505/8540 */ +#define AB8500_INT_GPIO25F 65 /* not 8505/8540 */ +#define AB8500_INT_GPIO36F 66 /* not 8505/9540/8540 */ +#define AB8500_INT_GPIO37F 67 /* not 8505/9540/8540 */ +#define AB8500_INT_GPIO38F 68 /* not 8505/9540/8540 */ +#define AB8500_INT_GPIO39F 69 /* not 8505/9540/8540 */ +#define AB8500_INT_GPIO40F 70 /* not 8540 */ +#define AB8500_INT_GPIO41F 71 /* not 8540 */ /* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */ #define AB8500_INT_ADP_SOURCE_ERROR 72 #define AB8500_INT_ADP_SINK_ERROR 73 @@ -160,42 +164,44 @@ enum ab8500_version { #define AB8500_INT_SRP_DETECT 88 #define AB8500_INT_USB_CHARGER_NOT_OKR 89 #define AB8500_INT_ID_WAKEUP_R 90 +#define AB8500_INT_ID_DET_PLUGR 91 /* 8505/9540 cut2.0 */ #define AB8500_INT_ID_DET_R1R 92 #define AB8500_INT_ID_DET_R2R 93 #define AB8500_INT_ID_DET_R3R 94 #define AB8500_INT_ID_DET_R4R 95 /* ab8500_irq_regoffset[12] -> IT[Source|Latch|Mask]21 */ -#define AB8500_INT_ID_WAKEUP_F 96 -#define AB8500_INT_ID_DET_R1F 98 -#define AB8500_INT_ID_DET_R2F 99 -#define AB8500_INT_ID_DET_R3F 100 -#define AB8500_INT_ID_DET_R4F 101 -#define AB8500_INT_CHAUTORESTARTAFTSEC 102 +#define AB8500_INT_ID_WAKEUP_F 96 /* not 8505/9540 */ +#define AB8500_INT_ID_DET_PLUGF 97 /* 8505/9540 cut2.0 */ +#define AB8500_INT_ID_DET_R1F 98 /* not 8505/9540 */ +#define AB8500_INT_ID_DET_R2F 99 /* not 8505/9540 */ +#define AB8500_INT_ID_DET_R3F 100 /* not 8505/9540 */ +#define AB8500_INT_ID_DET_R4F 101 /* not 8505/9540 */ +#define AB8500_INT_CHAUTORESTARTAFTSEC 102 /* not 8505/9540 */ #define AB8500_INT_CHSTOPBYSEC 103 /* ab8500_irq_regoffset[13] -> IT[Source|Latch|Mask]22 */ #define AB8500_INT_USB_CH_TH_PROT_F 104 -#define AB8500_INT_USB_CH_TH_PROT_R 105 +#define AB8500_INT_USB_CH_TH_PROT_R 105 #define AB8500_INT_MAIN_CH_TH_PROT_F 106 /* not 8505/9540 */ #define AB8500_INT_MAIN_CH_TH_PROT_R 107 /* not 8505/9540 */ #define AB8500_INT_CHCURLIMNOHSCHIRP 109 #define AB8500_INT_CHCURLIMHSCHIRP 110 #define AB8500_INT_XTAL32K_KO 111 -/* Definitions for AB9540 */ +/* Definitions for AB9540 / AB8505 */ /* ab8500_irq_regoffset[14] -> IT[Source|Latch|Mask]13 */ -#define AB9540_INT_GPIO50R 113 -#define AB9540_INT_GPIO51R 114 /* not 8505 */ -#define AB9540_INT_GPIO52R 115 -#define AB9540_INT_GPIO53R 116 -#define AB9540_INT_GPIO54R 117 /* not 8505 */ +#define AB9540_INT_GPIO50R 113 /* not 8540 */ +#define AB9540_INT_GPIO51R 114 /* not 8505/8540 */ +#define AB9540_INT_GPIO52R 115 /* not 8540 */ +#define AB9540_INT_GPIO53R 116 /* not 8540 */ +#define AB9540_INT_GPIO54R 117 /* not 8505/8540 */ #define AB9540_INT_IEXT_CH_RF_BFN_R 118 -#define AB9540_INT_IEXT_CH_RF_BFN_F 119 /* ab8500_irq_regoffset[15] -> IT[Source|Latch|Mask]14 */ -#define AB9540_INT_GPIO50F 121 -#define AB9540_INT_GPIO51F 122 /* not 8505 */ -#define AB9540_INT_GPIO52F 123 -#define AB9540_INT_GPIO53F 124 -#define AB9540_INT_GPIO54F 125 /* not 8505 */ +#define AB9540_INT_GPIO50F 121 /* not 8540 */ +#define AB9540_INT_GPIO51F 122 /* not 8505/8540 */ +#define AB9540_INT_GPIO52F 123 /* not 8540 */ +#define AB9540_INT_GPIO53F 124 /* not 8540 */ +#define AB9540_INT_GPIO54F 125 /* not 8505/8540 */ +#define AB9540_INT_IEXT_CH_RF_BFN_F 126 /* ab8500_irq_regoffset[16] -> IT[Source|Latch|Mask]25 */ #define AB8505_INT_KEYSTUCK 128 #define AB8505_INT_IKR 129 @@ -204,6 +210,87 @@ enum ab8500_version { #define AB8505_INT_KEYDEGLITCH 132 #define AB8505_INT_MODPWRSTATUSF 134 #define AB8505_INT_MODPWRSTATUSR 135 +/* ab8500_irq_regoffset[17] -> IT[Source|Latch|Mask]6 */ +#define AB8500_INT_HOOK_DET_NEG_F 138 +#define AB8500_INT_HOOK_DET_NEG_R 139 +#define AB8500_INT_HOOK_DET_POS_F 140 +#define AB8500_INT_HOOK_DET_POS_R 141 +#define AB8500_INT_PLUG_DET_COMP_F 142 +#define AB8500_INT_PLUG_DET_COMP_R 143 +/* ab8500_irq_regoffset[18] -> IT[Source|Latch|Mask]23 */ +#define AB8505_INT_COLL 144 +#define AB8505_INT_RESERR 145 +#define AB8505_INT_FRAERR 146 +#define AB8505_INT_COMERR 147 +#define AB8505_INT_SPDSET 148 +#define AB8505_INT_DSENT 149 +#define AB8505_INT_DREC 150 +#define AB8505_INT_ACC_INT 151 +/* ab8500_irq_regoffset[19] -> IT[Source|Latch|Mask]24 */ +#define AB8505_INT_NOPINT 152 +/* ab8540_irq_regoffset[20] -> IT[Source|Latch|Mask]26 */ +#define AB8540_INT_IDPLUGDETCOMPF 160 +#define AB8540_INT_IDPLUGDETCOMPR 161 +#define AB8540_INT_FMDETCOMPLOF 162 +#define AB8540_INT_FMDETCOMPLOR 163 +#define AB8540_INT_FMDETCOMPHIF 164 +#define AB8540_INT_FMDETCOMPHIR 165 +#define AB8540_INT_ID5VDETCOMPF 166 +#define AB8540_INT_ID5VDETCOMPR 167 +/* ab8540_irq_regoffset[21] -> IT[Source|Latch|Mask]27 */ +#define AB8540_INT_GPIO43F 168 +#define AB8540_INT_GPIO43R 169 +#define AB8540_INT_GPIO44F 170 +#define AB8540_INT_GPIO44R 171 +#define AB8540_INT_KEYPOSDETCOMPF 172 +#define AB8540_INT_KEYPOSDETCOMPR 173 +#define AB8540_INT_KEYNEGDETCOMPF 174 +#define AB8540_INT_KEYNEGDETCOMPR 175 +/* ab8540_irq_regoffset[22] -> IT[Source|Latch|Mask]28 */ +#define AB8540_INT_GPIO1VBATF 176 +#define AB8540_INT_GPIO1VBATR 177 +#define AB8540_INT_GPIO2VBATF 178 +#define AB8540_INT_GPIO2VBATR 179 +#define AB8540_INT_GPIO3VBATF 180 +#define AB8540_INT_GPIO3VBATR 181 +#define AB8540_INT_GPIO4VBATF 182 +#define AB8540_INT_GPIO4VBATR 183 +/* ab8540_irq_regoffset[23] -> IT[Source|Latch|Mask]29 */ +#define AB8540_INT_SYSCLKREQ2F 184 +#define AB8540_INT_SYSCLKREQ2R 185 +#define AB8540_INT_SYSCLKREQ3F 186 +#define AB8540_INT_SYSCLKREQ3R 187 +#define AB8540_INT_SYSCLKREQ4F 188 +#define AB8540_INT_SYSCLKREQ4R 189 +#define AB8540_INT_SYSCLKREQ5F 190 +#define AB8540_INT_SYSCLKREQ5R 191 +/* ab8540_irq_regoffset[24] -> IT[Source|Latch|Mask]30 */ +#define AB8540_INT_PWMOUT1F 192 +#define AB8540_INT_PWMOUT1R 193 +#define AB8540_INT_PWMCTRL0F 194 +#define AB8540_INT_PWMCTRL0R 195 +#define AB8540_INT_PWMCTRL1F 196 +#define AB8540_INT_PWMCTRL1R 197 +#define AB8540_INT_SYSCLKREQ6F 198 +#define AB8540_INT_SYSCLKREQ6R 199 +/* ab8540_irq_regoffset[25] -> IT[Source|Latch|Mask]31 */ +#define AB8540_INT_PWMEXTVIBRA1F 200 +#define AB8540_INT_PWMEXTVIBRA1R 201 +#define AB8540_INT_PWMEXTVIBRA2F 202 +#define AB8540_INT_PWMEXTVIBRA2R 203 +#define AB8540_INT_PWMOUT2F 204 +#define AB8540_INT_PWMOUT2R 205 +#define AB8540_INT_PWMOUT3F 206 +#define AB8540_INT_PWMOUT3R 207 +/* ab8540_irq_regoffset[26] -> IT[Source|Latch|Mask]32 */ +#define AB8540_INT_ADDATA2F 208 +#define AB8540_INT_ADDATA2R 209 +#define AB8540_INT_DADATA2F 210 +#define AB8540_INT_DADATA2R 211 +#define AB8540_INT_FSYNC2F 212 +#define AB8540_INT_FSYNC2R 213 +#define AB8540_INT_BITCLK2F 214 +#define AB8540_INT_BITCLK2R 215 /* * AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the @@ -213,13 +300,24 @@ enum ab8500_version { * which is larger. */ #define AB8500_NR_IRQS 112 -#define AB8505_NR_IRQS 136 -#define AB9540_NR_IRQS 136 +#define AB8505_NR_IRQS 153 +#define AB9540_NR_IRQS 153 +#define AB8540_NR_IRQS 216 /* This is set to the roof of any AB8500 chip variant IRQ counts */ -#define AB8500_MAX_NR_IRQS AB9540_NR_IRQS +#define AB8500_MAX_NR_IRQS AB8540_NR_IRQS #define AB8500_NUM_IRQ_REGS 14 -#define AB9540_NUM_IRQ_REGS 17 +#define AB9540_NUM_IRQ_REGS 20 +#define AB8540_NUM_IRQ_REGS 27 + +/* Turn On Status Event */ +#define AB8500_POR_ON_VBAT 0x01 +#define AB8500_POW_KEY_1_ON 0x02 +#define AB8500_POW_KEY_2_ON 0x04 +#define AB8500_RTC_ALARM 0x08 +#define AB8500_MAIN_CH_DET 0x10 +#define AB8500_VBUS_DET 0x20 +#define AB8500_USB_ID_DET 0x40 /** * struct ab8500 - ab8500 internal structure @@ -287,7 +385,7 @@ struct ab8500_platform_data { struct ab8500_regulator_reg_init *regulator_reg_init; int num_regulator; struct regulator_init_data *regulator; - struct ab8500_gpio_platform_data *gpio; + struct abx500_gpio_platform_data *gpio; struct ab8500_codec_platform_data *codec; }; @@ -335,10 +433,79 @@ static inline int is_ab8500_2p0_or_earlier(struct ab8500 *ab) return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT2P0)); } +static inline int is_ab8500_3p3_or_earlier(struct ab8500 *ab) +{ + return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT3P3)); +} + /* exclude also ab8505, ab9540... */ static inline int is_ab8500_2p0(struct ab8500 *ab) { return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0)); } +static inline int is_ab8505_1p0_or_earlier(struct ab8500 *ab) +{ + return (is_ab8505(ab) && (ab->chip_id <= AB8500_CUT1P0)); +} + +static inline int is_ab8505_2p0(struct ab8500 *ab) +{ + return (is_ab8505(ab) && (ab->chip_id == AB8500_CUT2P0)); +} + +static inline int is_ab9540_1p0_or_earlier(struct ab8500 *ab) +{ + return (is_ab9540(ab) && (ab->chip_id <= AB8500_CUT1P0)); +} + +static inline int is_ab9540_2p0(struct ab8500 *ab) +{ + return (is_ab9540(ab) && (ab->chip_id == AB8500_CUT2P0)); +} + +/* + * Be careful, the marketing name for this chip is 2.1 + * but the value read from the chip is 3.0 (0x30) + */ +static inline int is_ab9540_3p0(struct ab8500 *ab) +{ + return (is_ab9540(ab) && (ab->chip_id == AB8500_CUT3P0)); +} + +static inline int is_ab8540_1p0_or_earlier(struct ab8500 *ab) +{ + return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P0); +} + +static inline int is_ab8540_1p1_or_earlier(struct ab8500 *ab) +{ + return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P1); +} + +static inline int is_ab8540_1p2_or_earlier(struct ab8500 *ab) +{ + return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P2); +} + +static inline int is_ab8540_2p0_or_earlier(struct ab8500 *ab) +{ + return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT2P0); +} + +static inline int is_ab8540_2p0(struct ab8500 *ab) +{ + return is_ab8540(ab) && (ab->chip_id == AB8500_CUT2P0); +} + +static inline int is_ab8505_2p0_earlier(struct ab8500 *ab) +{ + return (is_ab8505(ab) && (ab->chip_id < AB8500_CUT2P0)); +} + +static inline int is_ab9540_2p0_or_earlier(struct ab8500 *ab) +{ + return (is_ab9540(ab) && (ab->chip_id < AB8500_CUT2P0)); +} + #endif /* MFD_AB8500_H */ diff --git a/include/linux/pinctrl/devinfo.h b/include/linux/pinctrl/devinfo.h new file mode 100644 index 000000000000..6e5f8a985ea7 --- /dev/null +++ b/include/linux/pinctrl/devinfo.h @@ -0,0 +1,45 @@ +/* + * Per-device information from the pin control system. + * This is the stuff that get included into the device + * core. + * + * Copyright (C) 2012 ST-Ericsson SA + * Written on behalf of Linaro for ST-Ericsson + * This interface is used in the core to keep track of pins. + * + * Author: Linus Walleij <linus.walleij@linaro.org> + * + * License terms: GNU General Public License (GPL) version 2 + */ + +#ifndef PINCTRL_DEVINFO_H +#define PINCTRL_DEVINFO_H + +#ifdef CONFIG_PINCTRL + +/* The device core acts as a consumer toward pinctrl */ +#include <linux/pinctrl/consumer.h> + +/** + * struct dev_pin_info - pin state container for devices + * @p: pinctrl handle for the containing device + * @default_state: the default state for the handle, if found + */ +struct dev_pin_info { + struct pinctrl *p; + struct pinctrl_state *default_state; +}; + +extern int pinctrl_bind_pins(struct device *dev); + +#else + +/* Stubs if we're not using pinctrl */ + +static inline int pinctrl_bind_pins(struct device *dev) +{ + return 0; +} + +#endif /* CONFIG_PINCTRL */ +#endif /* PINCTRL_DEVINFO_H */ diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h index 47a1bdd88878..72474e18f1e0 100644 --- a/include/linux/pinctrl/pinconf-generic.h +++ b/include/linux/pinctrl/pinconf-generic.h @@ -46,7 +46,11 @@ * @PIN_CONFIG_DRIVE_OPEN_SOURCE: the pin will be driven with open source * (open emitter). Sending this config will enabale open drain mode, the * argument is ignored. - * @PIN_CONFIG_INPUT_SCHMITT_DISABLE: disable schmitt-trigger mode on the pin. + * @PIN_CONFIG_DRIVE_STRENGTH: the pin will output the current passed as + * argument. The argument is in mA. + * @PIN_CONFIG_INPUT_SCHMITT_ENABLE: control schmitt-trigger mode on the pin. + * If the argument != 0, schmitt-trigger mode is enabled. If it's 0, + * schmitt-trigger mode is disabled. * @PIN_CONFIG_INPUT_SCHMITT: this will configure an input pin to run in * schmitt-trigger mode. If the schmitt-trigger has adjustable hysteresis, * the threshold value is given on a custom format as argument when @@ -58,10 +62,15 @@ * @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power * supplies, the argument to this parameter (on a custom format) tells * the driver which alternative power source to use. + * @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to + * this parameter (on a custom format) tells the driver which alternative + * slew rate to use. * @PIN_CONFIG_LOW_POWER_MODE: this will configure the pin for low power * operation, if several modes of operation are supported these can be * passed in the argument on a custom form, else just use argument 1 * to indicate low power mode, argument 0 turns low power mode off. + * @PIN_CONFIG_OUTPUT: this will configure the pin in output, use argument + * 1 to indicate high level, argument 0 to indicate low level. * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if * you need to pass in custom configurations to the pin controller, use * PIN_CONFIG_END+1 as the base offset. @@ -74,11 +83,14 @@ enum pin_config_param { PIN_CONFIG_DRIVE_PUSH_PULL, PIN_CONFIG_DRIVE_OPEN_DRAIN, PIN_CONFIG_DRIVE_OPEN_SOURCE, - PIN_CONFIG_INPUT_SCHMITT_DISABLE, + PIN_CONFIG_DRIVE_STRENGTH, + PIN_CONFIG_INPUT_SCHMITT_ENABLE, PIN_CONFIG_INPUT_SCHMITT, PIN_CONFIG_INPUT_DEBOUNCE, PIN_CONFIG_POWER_SOURCE, + PIN_CONFIG_SLEW_RATE, PIN_CONFIG_LOW_POWER_MODE, + PIN_CONFIG_OUTPUT, PIN_CONFIG_END = 0x7FFF, }; diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h index 04d6700d99af..778804df293f 100644 --- a/include/linux/pinctrl/pinctrl.h +++ b/include/linux/pinctrl/pinctrl.h @@ -154,6 +154,7 @@ struct pinctrl_dev *of_pinctrl_get(struct device_node *np) #endif /* CONFIG_OF */ extern const char *pinctrl_dev_get_name(struct pinctrl_dev *pctldev); +extern const char *pinctrl_dev_get_devname(struct pinctrl_dev *pctldev); extern void *pinctrl_dev_get_drvdata(struct pinctrl_dev *pctldev); #else |