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-rw-r--r--include/video/Kbuild3
-rw-r--r--include/video/da8xx-fb.h25
-rw-r--r--include/video/display_timing.h124
-rw-r--r--include/video/edid.h7
-rw-r--r--include/video/exynos_mipi_dsim.h1
-rw-r--r--include/video/mmp_disp.h352
-rw-r--r--include/video/of_display_timing.h20
-rw-r--r--include/video/of_videomode.h18
-rw-r--r--include/video/omap-panel-tfp410.h2
-rw-r--r--include/video/omapdss.h105
-rw-r--r--include/video/omapvrfb.h68
-rw-r--r--include/video/samsung_fimd.h351
-rw-r--r--include/video/sh_mipi_dsi.h4
-rw-r--r--include/video/sh_mobile_lcdc.h1
-rw-r--r--include/video/sisfb.h189
-rw-r--r--include/video/uvesafb.h58
-rw-r--r--include/video/videomode.h48
17 files changed, 875 insertions, 501 deletions
diff --git a/include/video/Kbuild b/include/video/Kbuild
index ad3e622c5339..e69de29bb2d1 100644
--- a/include/video/Kbuild
+++ b/include/video/Kbuild
@@ -1,3 +0,0 @@
-header-y += edid.h
-header-y += sisfb.h
-header-y += uvesafb.h
diff --git a/include/video/da8xx-fb.h b/include/video/da8xx-fb.h
index 5a0e4f9efb53..f88825928dd1 100644
--- a/include/video/da8xx-fb.h
+++ b/include/video/da8xx-fb.h
@@ -12,10 +12,6 @@
#ifndef DA8XX_FB_H
#define DA8XX_FB_H
-enum panel_type {
- QVGA = 0
-};
-
enum panel_shade {
MONOCHROME = 0,
COLOR_ACTIVE,
@@ -27,13 +23,6 @@ enum raster_load_mode {
LOAD_PALETTE,
};
-struct display_panel {
- enum panel_type panel_type; /* QVGA */
- int max_bpp;
- int min_bpp;
- enum panel_shade panel_shade;
-};
-
struct da8xx_lcdc_platform_data {
const char manu_name[10];
void *controller_data;
@@ -42,7 +31,7 @@ struct da8xx_lcdc_platform_data {
};
struct lcd_ctrl_config {
- const struct display_panel *p_disp_panel;
+ enum panel_shade panel_shade;
/* AC Bias Pin Frequency */
int ac_bias;
@@ -68,18 +57,9 @@ struct lcd_ctrl_config {
/* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
unsigned char mono_8bit_mode;
- /* Invert line clock */
- unsigned char invert_line_clock;
-
- /* Invert frame clock */
- unsigned char invert_frm_clock;
-
/* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
unsigned char sync_edge;
- /* Horizontal and Vertical Sync: Control: 0=ignore */
- unsigned char sync_ctrl;
-
/* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
unsigned char raster_order;
@@ -103,5 +83,8 @@ struct lcd_sync_arg {
#define FBIPUT_HSYNC _IOW('F', 9, int)
#define FBIPUT_VSYNC _IOW('F', 10, int)
+/* Proprietary FB_SYNC_ flags */
+#define FB_SYNC_CLK_INVERT 0x40000000
+
#endif /* ifndef DA8XX_FB_H */
diff --git a/include/video/display_timing.h b/include/video/display_timing.h
new file mode 100644
index 000000000000..71e9a383a981
--- /dev/null
+++ b/include/video/display_timing.h
@@ -0,0 +1,124 @@
+/*
+ * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * description of display timings
+ *
+ * This file is released under the GPLv2
+ */
+
+#ifndef __LINUX_DISPLAY_TIMING_H
+#define __LINUX_DISPLAY_TIMING_H
+
+#include <linux/bitops.h>
+#include <linux/types.h>
+
+/* VESA display monitor timing parameters */
+#define VESA_DMT_HSYNC_LOW BIT(0)
+#define VESA_DMT_HSYNC_HIGH BIT(1)
+#define VESA_DMT_VSYNC_LOW BIT(2)
+#define VESA_DMT_VSYNC_HIGH BIT(3)
+
+/* display specific flags */
+#define DISPLAY_FLAGS_DE_LOW BIT(0) /* data enable flag */
+#define DISPLAY_FLAGS_DE_HIGH BIT(1)
+#define DISPLAY_FLAGS_PIXDATA_POSEDGE BIT(2) /* drive data on pos. edge */
+#define DISPLAY_FLAGS_PIXDATA_NEGEDGE BIT(3) /* drive data on neg. edge */
+#define DISPLAY_FLAGS_INTERLACED BIT(4)
+#define DISPLAY_FLAGS_DOUBLESCAN BIT(5)
+
+/*
+ * A single signal can be specified via a range of minimal and maximal values
+ * with a typical value, that lies somewhere inbetween.
+ */
+struct timing_entry {
+ u32 min;
+ u32 typ;
+ u32 max;
+};
+
+enum timing_entry_index {
+ TE_MIN = 0,
+ TE_TYP = 1,
+ TE_MAX = 2,
+};
+
+/*
+ * Single "mode" entry. This describes one set of signal timings a display can
+ * have in one setting. This struct can later be converted to struct videomode
+ * (see include/video/videomode.h). As each timing_entry can be defined as a
+ * range, one struct display_timing may become multiple struct videomodes.
+ *
+ * Example: hsync active high, vsync active low
+ *
+ * Active Video
+ * Video ______________________XXXXXXXXXXXXXXXXXXXXXX_____________________
+ * |<- sync ->|<- back ->|<----- active ----->|<- front ->|<- sync..
+ * | | porch | | porch |
+ *
+ * HSync _|¯¯¯¯¯¯¯¯¯¯|___________________________________________|¯¯¯¯¯¯¯¯¯
+ *
+ * VSync ¯|__________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_________
+ */
+struct display_timing {
+ struct timing_entry pixelclock;
+
+ struct timing_entry hactive; /* hor. active video */
+ struct timing_entry hfront_porch; /* hor. front porch */
+ struct timing_entry hback_porch; /* hor. back porch */
+ struct timing_entry hsync_len; /* hor. sync len */
+
+ struct timing_entry vactive; /* ver. active video */
+ struct timing_entry vfront_porch; /* ver. front porch */
+ struct timing_entry vback_porch; /* ver. back porch */
+ struct timing_entry vsync_len; /* ver. sync len */
+
+ unsigned int dmt_flags; /* VESA DMT flags */
+ unsigned int data_flags; /* video data flags */
+};
+
+/*
+ * This describes all timing settings a display provides.
+ * The native_mode is the default setting for this display.
+ * Drivers that can handle multiple videomodes should work with this struct and
+ * convert each entry to the desired end result.
+ */
+struct display_timings {
+ unsigned int num_timings;
+ unsigned int native_mode;
+
+ struct display_timing **timings;
+};
+
+/* get value specified by index from struct timing_entry */
+static inline u32 display_timing_get_value(const struct timing_entry *te,
+ enum timing_entry_index index)
+{
+ switch (index) {
+ case TE_MIN:
+ return te->min;
+ break;
+ case TE_TYP:
+ return te->typ;
+ break;
+ case TE_MAX:
+ return te->max;
+ break;
+ default:
+ return te->typ;
+ }
+}
+
+/* get one entry from struct display_timings */
+static inline struct display_timing *display_timings_get(const struct
+ display_timings *disp,
+ unsigned int index)
+{
+ if (disp->num_timings > index)
+ return disp->timings[index];
+ else
+ return NULL;
+}
+
+void display_timings_release(struct display_timings *disp);
+
+#endif
diff --git a/include/video/edid.h b/include/video/edid.h
index c5f198704912..0cb8b2a92b75 100644
--- a/include/video/edid.h
+++ b/include/video/edid.h
@@ -1,14 +1,9 @@
#ifndef __linux_video_edid_h__
#define __linux_video_edid_h__
-struct edid_info {
- unsigned char dummy[128];
-};
+#include <uapi/video/edid.h>
-#ifdef __KERNEL__
#ifdef CONFIG_X86
extern struct edid_info edid_info;
#endif
-#endif
-
#endif /* __linux_video_edid_h__ */
diff --git a/include/video/exynos_mipi_dsim.h b/include/video/exynos_mipi_dsim.h
index 83ce5e667d47..89dc88a171af 100644
--- a/include/video/exynos_mipi_dsim.h
+++ b/include/video/exynos_mipi_dsim.h
@@ -220,7 +220,6 @@ struct mipi_dsim_config {
struct mipi_dsim_device {
struct device *dev;
int id;
- struct resource *res;
struct clk *clock;
unsigned int irq;
void __iomem *reg_base;
diff --git a/include/video/mmp_disp.h b/include/video/mmp_disp.h
new file mode 100644
index 000000000000..b9dd1fbb0082
--- /dev/null
+++ b/include/video/mmp_disp.h
@@ -0,0 +1,352 @@
+/*
+ * linux/include/video/mmp_disp.h
+ * Header file for Marvell MMP Display Controller
+ *
+ * Copyright (C) 2012 Marvell Technology Group Ltd.
+ * Authors: Zhou Zhu <zzhu3@marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef _MMP_DISP_H_
+#define _MMP_DISP_H_
+#include <linux/kthread.h>
+
+enum {
+ PIXFMT_UYVY = 0,
+ PIXFMT_VYUY,
+ PIXFMT_YUYV,
+ PIXFMT_YUV422P,
+ PIXFMT_YVU422P,
+ PIXFMT_YUV420P,
+ PIXFMT_YVU420P,
+ PIXFMT_RGB565 = 0x100,
+ PIXFMT_BGR565,
+ PIXFMT_RGB1555,
+ PIXFMT_BGR1555,
+ PIXFMT_RGB888PACK,
+ PIXFMT_BGR888PACK,
+ PIXFMT_RGB888UNPACK,
+ PIXFMT_BGR888UNPACK,
+ PIXFMT_RGBA888,
+ PIXFMT_BGRA888,
+ PIXFMT_RGB666, /* for output usage */
+ PIXFMT_PSEUDOCOLOR = 0x200,
+};
+
+static inline int pixfmt_to_stride(int pix_fmt)
+{
+ switch (pix_fmt) {
+ case PIXFMT_RGB565:
+ case PIXFMT_BGR565:
+ case PIXFMT_RGB1555:
+ case PIXFMT_BGR1555:
+ case PIXFMT_UYVY:
+ case PIXFMT_VYUY:
+ case PIXFMT_YUYV:
+ return 2;
+ case PIXFMT_RGB888UNPACK:
+ case PIXFMT_BGR888UNPACK:
+ case PIXFMT_RGBA888:
+ case PIXFMT_BGRA888:
+ return 4;
+ case PIXFMT_RGB888PACK:
+ case PIXFMT_BGR888PACK:
+ return 3;
+ case PIXFMT_YUV422P:
+ case PIXFMT_YVU422P:
+ case PIXFMT_YUV420P:
+ case PIXFMT_YVU420P:
+ case PIXFMT_PSEUDOCOLOR:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+/* parameters used by path/overlay */
+/* overlay related para: win/addr */
+struct mmp_win {
+ /* position/size of window */
+ u16 xsrc;
+ u16 ysrc;
+ u16 xdst;
+ u16 ydst;
+ u16 xpos;
+ u16 ypos;
+ u16 left_crop;
+ u16 right_crop;
+ u16 up_crop;
+ u16 bottom_crop;
+ int pix_fmt;
+};
+
+struct mmp_addr {
+ /* phys address */
+ u32 phys[6];
+};
+
+/* path related para: mode */
+struct mmp_mode {
+ const char *name;
+ u32 refresh;
+ u32 xres;
+ u32 yres;
+ u32 left_margin;
+ u32 right_margin;
+ u32 upper_margin;
+ u32 lower_margin;
+ u32 hsync_len;
+ u32 vsync_len;
+ u32 hsync_invert;
+ u32 vsync_invert;
+ u32 invert_pixclock;
+ u32 pixclock_freq;
+ int pix_fmt_out;
+};
+
+/* main structures */
+struct mmp_path;
+struct mmp_overlay;
+struct mmp_panel;
+
+/* status types */
+enum {
+ MMP_OFF = 0,
+ MMP_ON,
+};
+
+static inline const char *stat_name(int stat)
+{
+ switch (stat) {
+ case MMP_OFF:
+ return "OFF";
+ case MMP_ON:
+ return "ON";
+ default:
+ return "UNKNOWNSTAT";
+ }
+}
+
+struct mmp_overlay_ops {
+ /* should be provided by driver */
+ void (*set_fetch)(struct mmp_overlay *overlay, int fetch_id);
+ void (*set_onoff)(struct mmp_overlay *overlay, int status);
+ void (*set_win)(struct mmp_overlay *overlay, struct mmp_win *win);
+ int (*set_addr)(struct mmp_overlay *overlay, struct mmp_addr *addr);
+};
+
+/* overlay describes a z-order indexed slot in each path. */
+struct mmp_overlay {
+ int id;
+ const char *name;
+ struct mmp_path *path;
+
+ /* overlay info: private data */
+ int dmafetch_id;
+ struct mmp_addr addr;
+ struct mmp_win win;
+
+ /* state */
+ int open_count;
+ int status;
+ struct mutex access_ok;
+
+ struct mmp_overlay_ops *ops;
+};
+
+/* panel type */
+enum {
+ PANELTYPE_ACTIVE = 0,
+ PANELTYPE_SMART,
+ PANELTYPE_TV,
+ PANELTYPE_DSI_CMD,
+ PANELTYPE_DSI_VIDEO,
+};
+
+struct mmp_panel {
+ /* use node to register to list */
+ struct list_head node;
+ const char *name;
+ /* path name used to connect to proper path configed */
+ const char *plat_path_name;
+ struct device *dev;
+ int panel_type;
+ void *plat_data;
+ int (*get_modelist)(struct mmp_panel *panel,
+ struct mmp_mode **modelist);
+ void (*set_mode)(struct mmp_panel *panel,
+ struct mmp_mode *mode);
+ void (*set_onoff)(struct mmp_panel *panel,
+ int status);
+};
+
+struct mmp_path_ops {
+ int (*check_status)(struct mmp_path *path);
+ struct mmp_overlay *(*get_overlay)(struct mmp_path *path,
+ int overlay_id);
+ int (*get_modelist)(struct mmp_path *path,
+ struct mmp_mode **modelist);
+
+ /* follow ops should be provided by driver */
+ void (*set_mode)(struct mmp_path *path, struct mmp_mode *mode);
+ void (*set_onoff)(struct mmp_path *path, int status);
+ /* todo: add query */
+};
+
+/* path output types */
+enum {
+ PATH_OUT_PARALLEL,
+ PATH_OUT_DSI,
+ PATH_OUT_HDMI,
+};
+
+/* path is main part of mmp-disp */
+struct mmp_path {
+ /* use node to register to list */
+ struct list_head node;
+
+ /* init data */
+ struct device *dev;
+
+ int id;
+ const char *name;
+ int output_type;
+ struct mmp_panel *panel;
+ void *plat_data;
+
+ /* dynamic use */
+ struct mmp_mode mode;
+
+ /* state */
+ int open_count;
+ int status;
+ struct mutex access_ok;
+
+ struct mmp_path_ops ops;
+
+ /* layers */
+ int overlay_num;
+ struct mmp_overlay overlays[0];
+};
+
+extern struct mmp_path *mmp_get_path(const char *name);
+static inline void mmp_path_set_mode(struct mmp_path *path,
+ struct mmp_mode *mode)
+{
+ if (path)
+ path->ops.set_mode(path, mode);
+}
+static inline void mmp_path_set_onoff(struct mmp_path *path, int status)
+{
+ if (path)
+ path->ops.set_onoff(path, status);
+}
+static inline int mmp_path_get_modelist(struct mmp_path *path,
+ struct mmp_mode **modelist)
+{
+ if (path)
+ return path->ops.get_modelist(path, modelist);
+ return 0;
+}
+static inline struct mmp_overlay *mmp_path_get_overlay(
+ struct mmp_path *path, int overlay_id)
+{
+ if (path)
+ return path->ops.get_overlay(path, overlay_id);
+ return NULL;
+}
+static inline void mmp_overlay_set_fetch(struct mmp_overlay *overlay,
+ int fetch_id)
+{
+ if (overlay)
+ overlay->ops->set_fetch(overlay, fetch_id);
+}
+static inline void mmp_overlay_set_onoff(struct mmp_overlay *overlay,
+ int status)
+{
+ if (overlay)
+ overlay->ops->set_onoff(overlay, status);
+}
+static inline void mmp_overlay_set_win(struct mmp_overlay *overlay,
+ struct mmp_win *win)
+{
+ if (overlay)
+ overlay->ops->set_win(overlay, win);
+}
+static inline int mmp_overlay_set_addr(struct mmp_overlay *overlay,
+ struct mmp_addr *addr)
+{
+ if (overlay)
+ return overlay->ops->set_addr(overlay, addr);
+ return 0;
+}
+
+/*
+ * driver data is set from each detailed ctrl driver for path usage
+ * it defined a common interface that plat driver need to implement
+ */
+struct mmp_path_info {
+ /* driver data, set when registed*/
+ const char *name;
+ struct device *dev;
+ int id;
+ int output_type;
+ int overlay_num;
+ void (*set_mode)(struct mmp_path *path, struct mmp_mode *mode);
+ void (*set_onoff)(struct mmp_path *path, int status);
+ struct mmp_overlay_ops *overlay_ops;
+ void *plat_data;
+};
+
+extern struct mmp_path *mmp_register_path(
+ struct mmp_path_info *info);
+extern void mmp_unregister_path(struct mmp_path *path);
+extern void mmp_register_panel(struct mmp_panel *panel);
+extern void mmp_unregister_panel(struct mmp_panel *panel);
+
+/* defintions for platform data */
+/* interface for buffer driver */
+struct mmp_buffer_driver_mach_info {
+ const char *name;
+ const char *path_name;
+ int overlay_id;
+ int dmafetch_id;
+ int default_pixfmt;
+};
+
+/* interface for controllers driver */
+struct mmp_mach_path_config {
+ const char *name;
+ int overlay_num;
+ int output_type;
+ u32 path_config;
+ u32 link_config;
+};
+
+struct mmp_mach_plat_info {
+ const char *name;
+ const char *clk_name;
+ int path_num;
+ struct mmp_mach_path_config *paths;
+};
+
+/* interface for panel drivers */
+struct mmp_mach_panel_info {
+ const char *name;
+ void (*plat_set_onoff)(int status);
+ const char *plat_path_name;
+};
+#endif /* _MMP_DISP_H_ */
diff --git a/include/video/of_display_timing.h b/include/video/of_display_timing.h
new file mode 100644
index 000000000000..8016eb727cf3
--- /dev/null
+++ b/include/video/of_display_timing.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * display timings of helpers
+ *
+ * This file is released under the GPLv2
+ */
+
+#ifndef __LINUX_OF_DISPLAY_TIMING_H
+#define __LINUX_OF_DISPLAY_TIMING_H
+
+struct device_node;
+struct display_timings;
+
+#define OF_USE_NATIVE_MODE -1
+
+struct display_timings *of_get_display_timings(struct device_node *np);
+int of_display_timings_exist(struct device_node *np);
+
+#endif
diff --git a/include/video/of_videomode.h b/include/video/of_videomode.h
new file mode 100644
index 000000000000..a07efcc51424
--- /dev/null
+++ b/include/video/of_videomode.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * videomode of-helpers
+ *
+ * This file is released under the GPLv2
+ */
+
+#ifndef __LINUX_OF_VIDEOMODE_H
+#define __LINUX_OF_VIDEOMODE_H
+
+struct device_node;
+struct videomode;
+
+int of_get_videomode(struct device_node *np, struct videomode *vm,
+ int index);
+
+#endif /* __LINUX_OF_VIDEOMODE_H */
diff --git a/include/video/omap-panel-tfp410.h b/include/video/omap-panel-tfp410.h
index 68c31d79c571..aef35e48bc7e 100644
--- a/include/video/omap-panel-tfp410.h
+++ b/include/video/omap-panel-tfp410.h
@@ -28,7 +28,7 @@ struct omap_dss_device;
* @power_down_gpio: gpio number for PD pin (or -1 if not available)
*/
struct tfp410_platform_data {
- u16 i2c_bus_num;
+ int i2c_bus_num;
int power_down_gpio;
};
diff --git a/include/video/omapdss.h b/include/video/omapdss.h
index 3729173b7fbc..caefa093337d 100644
--- a/include/video/omapdss.h
+++ b/include/video/omapdss.h
@@ -21,6 +21,7 @@
#include <linux/list.h>
#include <linux/kobject.h>
#include <linux/device.h>
+#include <linux/interrupt.h>
#define DISPC_IRQ_FRAMEDONE (1 << 0)
#define DISPC_IRQ_VSYNC (1 << 1)
@@ -55,6 +56,7 @@
struct omap_dss_device;
struct omap_overlay_manager;
+struct dss_lcd_mgr_config;
struct snd_aes_iec958;
struct snd_cea_861_aud_if;
@@ -158,7 +160,6 @@ enum omap_display_caps {
enum omap_dss_display_state {
OMAP_DSS_DISPLAY_DISABLED = 0,
OMAP_DSS_DISPLAY_ACTIVE,
- OMAP_DSS_DISPLAY_SUSPENDED,
};
enum omap_dss_audio_state {
@@ -314,6 +315,19 @@ int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel);
void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel);
+enum omapdss_version {
+ OMAPDSS_VER_UNKNOWN = 0,
+ OMAPDSS_VER_OMAP24xx,
+ OMAPDSS_VER_OMAP34xx_ES1, /* OMAP3430 ES1.0, 2.0 */
+ OMAPDSS_VER_OMAP34xx_ES3, /* OMAP3430 ES3.0+ */
+ OMAPDSS_VER_OMAP3630,
+ OMAPDSS_VER_AM35xx,
+ OMAPDSS_VER_OMAP4430_ES1, /* OMAP4430 ES1.0 */
+ OMAPDSS_VER_OMAP4430_ES2, /* OMAP4430 ES2.0, 2.1, 2.2 */
+ OMAPDSS_VER_OMAP4, /* All other OMAP4s */
+ OMAPDSS_VER_OMAP5,
+};
+
/* Board specific data */
struct omap_dss_board_info {
int (*get_context_loss_count)(struct device *dev);
@@ -323,6 +337,7 @@ struct omap_dss_board_info {
int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
int (*set_min_bus_tput)(struct device *dev, unsigned long r);
+ enum omapdss_version version;
};
/* Init with the board info */
@@ -607,10 +622,6 @@ struct omap_dss_device {
struct {
struct omap_video_timings timings;
- int acbi; /* ac-bias pin transitions per interrupt */
- /* Unit: line clocks */
- int acb; /* ac-bias pin frequency */
-
enum omap_dss_dsi_pixel_format dsi_pix_fmt;
enum omap_dss_dsi_mode dsi_mode;
struct omap_dss_dsi_videomode_timings dsi_vm_timings;
@@ -672,8 +683,6 @@ struct omap_dss_driver {
int (*enable)(struct omap_dss_device *display);
void (*disable)(struct omap_dss_device *display);
- int (*suspend)(struct omap_dss_device *display);
- int (*resume)(struct omap_dss_device *display);
int (*run_test)(struct omap_dss_device *display, int test);
int (*update)(struct omap_dss_device *dssdev,
@@ -731,6 +740,8 @@ struct omap_dss_driver {
};
+enum omapdss_version omapdss_get_version(void);
+
int omap_dss_register_driver(struct omap_dss_driver *);
void omap_dss_unregister_driver(struct omap_dss_driver *);
@@ -740,10 +751,19 @@ void omap_dss_put_device(struct omap_dss_device *dssdev);
struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
struct omap_dss_device *omap_dss_find_device(void *data,
int (*match)(struct omap_dss_device *dssdev, void *data));
+const char *omapdss_get_default_display_name(void);
int omap_dss_start_device(struct omap_dss_device *dssdev);
void omap_dss_stop_device(struct omap_dss_device *dssdev);
+int dss_feat_get_num_mgrs(void);
+int dss_feat_get_num_ovls(void);
+enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel);
+enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel);
+enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
+
+
+
int omap_dss_get_num_overlay_managers(void);
struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
@@ -765,9 +785,43 @@ typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
-int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
-int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
- unsigned long timeout);
+u32 dispc_read_irqstatus(void);
+void dispc_clear_irqstatus(u32 mask);
+u32 dispc_read_irqenable(void);
+void dispc_write_irqenable(u32 mask);
+
+int dispc_request_irq(irq_handler_t handler, void *dev_id);
+void dispc_free_irq(void *dev_id);
+
+int dispc_runtime_get(void);
+void dispc_runtime_put(void);
+
+void dispc_mgr_enable(enum omap_channel channel, bool enable);
+bool dispc_mgr_is_enabled(enum omap_channel channel);
+u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
+u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
+u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel);
+bool dispc_mgr_go_busy(enum omap_channel channel);
+void dispc_mgr_go(enum omap_channel channel);
+void dispc_mgr_set_lcd_config(enum omap_channel channel,
+ const struct dss_lcd_mgr_config *config);
+void dispc_mgr_set_timings(enum omap_channel channel,
+ const struct omap_video_timings *timings);
+void dispc_mgr_setup(enum omap_channel channel,
+ const struct omap_overlay_manager_info *info);
+
+int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
+ const struct omap_overlay_info *oi,
+ const struct omap_video_timings *timings,
+ int *x_predecim, int *y_predecim);
+
+int dispc_ovl_enable(enum omap_plane plane, bool enable);
+bool dispc_ovl_enabled(enum omap_plane plane);
+void dispc_ovl_set_channel_out(enum omap_plane plane,
+ enum omap_channel channel);
+int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
+ bool replication, const struct omap_video_timings *mgr_timings,
+ bool mem_to_mem);
#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
@@ -826,4 +880,35 @@ void omapdss_rfbi_set_data_lines(struct omap_dss_device *dssdev,
void omapdss_rfbi_set_interface_timings(struct omap_dss_device *dssdev,
struct rfbi_timings *timings);
+int omapdss_compat_init(void);
+void omapdss_compat_uninit(void);
+
+struct dss_mgr_ops {
+ void (*start_update)(struct omap_overlay_manager *mgr);
+ int (*enable)(struct omap_overlay_manager *mgr);
+ void (*disable)(struct omap_overlay_manager *mgr);
+ void (*set_timings)(struct omap_overlay_manager *mgr,
+ const struct omap_video_timings *timings);
+ void (*set_lcd_config)(struct omap_overlay_manager *mgr,
+ const struct dss_lcd_mgr_config *config);
+ int (*register_framedone_handler)(struct omap_overlay_manager *mgr,
+ void (*handler)(void *), void *data);
+ void (*unregister_framedone_handler)(struct omap_overlay_manager *mgr,
+ void (*handler)(void *), void *data);
+};
+
+int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops);
+void dss_uninstall_mgr_ops(void);
+
+void dss_mgr_set_timings(struct omap_overlay_manager *mgr,
+ const struct omap_video_timings *timings);
+void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr,
+ const struct dss_lcd_mgr_config *config);
+int dss_mgr_enable(struct omap_overlay_manager *mgr);
+void dss_mgr_disable(struct omap_overlay_manager *mgr);
+void dss_mgr_start_update(struct omap_overlay_manager *mgr);
+int dss_mgr_register_framedone_handler(struct omap_overlay_manager *mgr,
+ void (*handler)(void *), void *data);
+void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager *mgr,
+ void (*handler)(void *), void *data);
#endif
diff --git a/include/video/omapvrfb.h b/include/video/omapvrfb.h
new file mode 100644
index 000000000000..bb0bd89f8bc6
--- /dev/null
+++ b/include/video/omapvrfb.h
@@ -0,0 +1,68 @@
+/*
+ * VRFB Rotation Engine
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef __OMAP_VRFB_H__
+#define __OMAP_VRFB_H__
+
+#define OMAP_VRFB_LINE_LEN 2048
+
+struct vrfb {
+ u8 context;
+ void __iomem *vaddr[4];
+ unsigned long paddr[4];
+ u16 xres;
+ u16 yres;
+ u16 xoffset;
+ u16 yoffset;
+ u8 bytespp;
+ bool yuv_mode;
+};
+
+#ifdef CONFIG_OMAP2_VRFB
+extern bool omap_vrfb_supported(void);
+extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
+extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
+extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
+ u8 bytespp);
+extern u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp);
+extern u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp);
+extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
+ u16 width, u16 height,
+ unsigned bytespp, bool yuv_mode);
+extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot);
+extern void omap_vrfb_restore_context(void);
+
+#else
+static inline bool omap_vrfb_supported(void) { return false; }
+static inline int omap_vrfb_request_ctx(struct vrfb *vrfb) { return 0; }
+static inline void omap_vrfb_release_ctx(struct vrfb *vrfb) {}
+static inline void omap_vrfb_adjust_size(u16 *width, u16 *height,
+ u8 bytespp) {}
+static inline u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp)
+ { return 0; }
+static inline u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp)
+ { return 0; }
+static inline void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
+ u16 width, u16 height, unsigned bytespp, bool yuv_mode) {}
+static inline int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot)
+ { return 0; }
+static inline void omap_vrfb_restore_context(void) {}
+#endif
+#endif /* __VRFB_H */
diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h
index 7ae6c07f2ef8..b0393209679b 100644
--- a/include/video/samsung_fimd.h
+++ b/include/video/samsung_fimd.h
@@ -8,12 +8,8 @@
* S3C Platform - new-style fimd and framebuffer register definitions
*
* This is the register set for the fimd and new style framebuffer interface
- * found from the S3C2443 onwards into the S3C2416, S3C2450 and the
- * S3C64XX series such as the S3C6400 and S3C6410.
- *
- * The file does not contain the cpu specific items which are based on
- * whichever architecture is selected, it only contains the core of the
- * register set. See <mach/regs-fb.h> to get the specifics.
+ * found from the S3C2443 onwards into the S3C2416, S3C2450, the
+ * S3C64XX series such as the S3C6400 and S3C6410, and EXYNOS series.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -22,17 +18,20 @@
/* VIDCON0 */
-#define VIDCON0 (0x00)
+#define VIDCON0 0x00
#define VIDCON0_INTERLACE (1 << 29)
-#define VIDCON0_VIDOUT_MASK (0x3 << 26)
-#define VIDCON0_VIDOUT_SHIFT (26)
+#define VIDCON0_VIDOUT_MASK (0x7 << 26)
+#define VIDCON0_VIDOUT_SHIFT 26
#define VIDCON0_VIDOUT_RGB (0x0 << 26)
#define VIDCON0_VIDOUT_TV (0x1 << 26)
#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
+#define VIDCON0_VIDOUT_WB_RGB (0x4 << 26)
+#define VIDCON0_VIDOUT_WB_I80_LDI0 (0x6 << 26)
+#define VIDCON0_VIDOUT_WB_I80_LDI1 (0x7 << 26)
#define VIDCON0_L1_DATA_MASK (0x7 << 23)
-#define VIDCON0_L1_DATA_SHIFT (23)
+#define VIDCON0_L1_DATA_SHIFT 23
#define VIDCON0_L1_DATA_16BPP (0x0 << 23)
#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)
#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
@@ -41,7 +40,7 @@
#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)
#define VIDCON0_L0_DATA_MASK (0x7 << 20)
-#define VIDCON0_L0_DATA_SHIFT (20)
+#define VIDCON0_L0_DATA_SHIFT 20
#define VIDCON0_L0_DATA_16BPP (0x0 << 20)
#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)
#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
@@ -50,7 +49,7 @@
#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)
#define VIDCON0_PNRMODE_MASK (0x3 << 17)
-#define VIDCON0_PNRMODE_SHIFT (17)
+#define VIDCON0_PNRMODE_SHIFT 17
#define VIDCON0_PNRMODE_RGB (0x0 << 17)
#define VIDCON0_PNRMODE_BGR (0x1 << 17)
#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
@@ -58,14 +57,14 @@
#define VIDCON0_CLKVALUP (1 << 16)
#define VIDCON0_CLKVAL_F_MASK (0xff << 6)
-#define VIDCON0_CLKVAL_F_SHIFT (6)
-#define VIDCON0_CLKVAL_F_LIMIT (0xff)
+#define VIDCON0_CLKVAL_F_SHIFT 6
+#define VIDCON0_CLKVAL_F_LIMIT 0xff
#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)
#define VIDCON0_VLCKFREE (1 << 5)
#define VIDCON0_CLKDIR (1 << 4)
#define VIDCON0_CLKSEL_MASK (0x3 << 2)
-#define VIDCON0_CLKSEL_SHIFT (2)
+#define VIDCON0_CLKSEL_SHIFT 2
#define VIDCON0_CLKSEL_HCLK (0x0 << 2)
#define VIDCON0_CLKSEL_LCD (0x1 << 2)
#define VIDCON0_CLKSEL_27M (0x3 << 2)
@@ -73,16 +72,17 @@
#define VIDCON0_ENVID (1 << 1)
#define VIDCON0_ENVID_F (1 << 0)
-#define VIDCON1 (0x04)
+#define VIDCON1 0x04
#define VIDCON1_LINECNT_MASK (0x7ff << 16)
-#define VIDCON1_LINECNT_SHIFT (16)
+#define VIDCON1_LINECNT_SHIFT 16
#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
+#define VIDCON1_FSTATUS_EVEN (1 << 15)
#define VIDCON1_VSTATUS_MASK (0x3 << 13)
-#define VIDCON1_VSTATUS_SHIFT (13)
+#define VIDCON1_VSTATUS_SHIFT 13
#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
-#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)
+#define VIDCON1_VSTATUS_FRONTPORCH (0x3 << 13)
#define VIDCON1_VCLK_MASK (0x3 << 9)
#define VIDCON1_VCLK_HOLD (0x0 << 9)
#define VIDCON1_VCLK_RUN (0x1 << 9)
@@ -94,12 +94,12 @@
/* VIDCON2 */
-#define VIDCON2 (0x08)
+#define VIDCON2 0x08
#define VIDCON2_EN601 (1 << 23)
#define VIDCON2_TVFMTSEL_SW (1 << 14)
#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
-#define VIDCON2_TVFMTSEL1_SHIFT (12)
+#define VIDCON2_TVFMTSEL1_SHIFT 12
#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
@@ -111,82 +111,95 @@
* Might not be present in the S3C6410 documentation,
* but tests prove it's there almost for sure; shouldn't hurt in any case.
*/
-#define PRTCON (0x0c)
+#define PRTCON 0x0c
#define PRTCON_PROTECT (1 << 11)
/* VIDTCON0 */
+#define VIDTCON0 0x10
#define VIDTCON0_VBPDE_MASK (0xff << 24)
-#define VIDTCON0_VBPDE_SHIFT (24)
-#define VIDTCON0_VBPDE_LIMIT (0xff)
+#define VIDTCON0_VBPDE_SHIFT 24
+#define VIDTCON0_VBPDE_LIMIT 0xff
#define VIDTCON0_VBPDE(_x) ((_x) << 24)
#define VIDTCON0_VBPD_MASK (0xff << 16)
-#define VIDTCON0_VBPD_SHIFT (16)
-#define VIDTCON0_VBPD_LIMIT (0xff)
+#define VIDTCON0_VBPD_SHIFT 16
+#define VIDTCON0_VBPD_LIMIT 0xff
#define VIDTCON0_VBPD(_x) ((_x) << 16)
#define VIDTCON0_VFPD_MASK (0xff << 8)
-#define VIDTCON0_VFPD_SHIFT (8)
-#define VIDTCON0_VFPD_LIMIT (0xff)
+#define VIDTCON0_VFPD_SHIFT 8
+#define VIDTCON0_VFPD_LIMIT 0xff
#define VIDTCON0_VFPD(_x) ((_x) << 8)
#define VIDTCON0_VSPW_MASK (0xff << 0)
-#define VIDTCON0_VSPW_SHIFT (0)
-#define VIDTCON0_VSPW_LIMIT (0xff)
+#define VIDTCON0_VSPW_SHIFT 0
+#define VIDTCON0_VSPW_LIMIT 0xff
#define VIDTCON0_VSPW(_x) ((_x) << 0)
/* VIDTCON1 */
+#define VIDTCON1 0x14
#define VIDTCON1_VFPDE_MASK (0xff << 24)
-#define VIDTCON1_VFPDE_SHIFT (24)
-#define VIDTCON1_VFPDE_LIMIT (0xff)
+#define VIDTCON1_VFPDE_SHIFT 24
+#define VIDTCON1_VFPDE_LIMIT 0xff
#define VIDTCON1_VFPDE(_x) ((_x) << 24)
#define VIDTCON1_HBPD_MASK (0xff << 16)
-#define VIDTCON1_HBPD_SHIFT (16)
-#define VIDTCON1_HBPD_LIMIT (0xff)
+#define VIDTCON1_HBPD_SHIFT 16
+#define VIDTCON1_HBPD_LIMIT 0xff
#define VIDTCON1_HBPD(_x) ((_x) << 16)
#define VIDTCON1_HFPD_MASK (0xff << 8)
-#define VIDTCON1_HFPD_SHIFT (8)
-#define VIDTCON1_HFPD_LIMIT (0xff)
+#define VIDTCON1_HFPD_SHIFT 8
+#define VIDTCON1_HFPD_LIMIT 0xff
#define VIDTCON1_HFPD(_x) ((_x) << 8)
#define VIDTCON1_HSPW_MASK (0xff << 0)
-#define VIDTCON1_HSPW_SHIFT (0)
-#define VIDTCON1_HSPW_LIMIT (0xff)
+#define VIDTCON1_HSPW_SHIFT 0
+#define VIDTCON1_HSPW_LIMIT 0xff
#define VIDTCON1_HSPW(_x) ((_x) << 0)
-#define VIDTCON2 (0x18)
+#define VIDTCON2 0x18
#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
-#define VIDTCON2_LINEVAL_SHIFT (11)
-#define VIDTCON2_LINEVAL_LIMIT (0x7ff)
+#define VIDTCON2_LINEVAL_SHIFT 11
+#define VIDTCON2_LINEVAL_LIMIT 0x7ff
#define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11)
#define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22)
#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
-#define VIDTCON2_HOZVAL_SHIFT (0)
-#define VIDTCON2_HOZVAL_LIMIT (0x7ff)
+#define VIDTCON2_HOZVAL_SHIFT 0
+#define VIDTCON2_HOZVAL_LIMIT 0x7ff
#define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0)
/* WINCONx */
-
+#define WINCON(_win) (0x20 + ((_win) * 4))
+#define WINCONx_CSCCON_EQ601 (0x0 << 28)
+#define WINCONx_CSCCON_EQ709 (0x1 << 28)
+#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
+#define WINCONx_CSCWIDTH_SHIFT 26
+#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
+#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
+#define WINCONx_ENLOCAL (1 << 22)
+#define WINCONx_BUFSTATUS (1 << 21)
+#define WINCONx_BUFSEL (1 << 20)
+#define WINCONx_BUFAUTOEN (1 << 19)
#define WINCONx_BITSWP (1 << 18)
#define WINCONx_BYTSWP (1 << 17)
#define WINCONx_HAWSWP (1 << 16)
#define WINCONx_WSWP (1 << 15)
+#define WINCONx_YCbCr (1 << 13)
#define WINCONx_BURSTLEN_MASK (0x3 << 9)
-#define WINCONx_BURSTLEN_SHIFT (9)
+#define WINCONx_BURSTLEN_SHIFT 9
#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
-
#define WINCONx_ENWIN (1 << 0)
+
#define WINCON0_BPPMODE_MASK (0xf << 2)
-#define WINCON0_BPPMODE_SHIFT (2)
+#define WINCON0_BPPMODE_SHIFT 2
#define WINCON0_BPPMODE_1BPP (0x0 << 2)
#define WINCON0_BPPMODE_2BPP (0x1 << 2)
#define WINCON0_BPPMODE_4BPP (0x2 << 2)
@@ -196,11 +209,10 @@
#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
+#define WINCON1_LOCALSEL_CAMIF (1 << 23)
#define WINCON1_BLD_PIX (1 << 6)
-
-#define WINCON1_ALPHA_SEL (1 << 1)
#define WINCON1_BPPMODE_MASK (0xf << 2)
-#define WINCON1_BPPMODE_SHIFT (2)
+#define WINCON1_BPPMODE_SHIFT 2
#define WINCON1_BPPMODE_1BPP (0x0 << 2)
#define WINCON1_BPPMODE_2BPP (0x1 << 2)
#define WINCON1_BPPMODE_4BPP (0x2 << 2)
@@ -216,60 +228,64 @@
#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
+#define WINCON1_ALPHA_SEL (1 << 1)
/* S5PV210 */
-#define SHADOWCON (0x34)
+#define SHADOWCON 0x34
#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win)))
/* DMA channels (all windows) */
#define SHADOWCON_CHx_ENABLE(_win) (1 << (_win))
/* Local input channels (windows 0-2) */
#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win)))
+/* VIDOSDx */
+
+#define VIDOSD_BASE 0x40
#define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
-#define VIDOSDxA_TOPLEFT_X_SHIFT (11)
-#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)
+#define VIDOSDxA_TOPLEFT_X_SHIFT 11
+#define VIDOSDxA_TOPLEFT_X_LIMIT 0x7ff
#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11)
#define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
-#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)
-#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)
+#define VIDOSDxA_TOPLEFT_Y_SHIFT 0
+#define VIDOSDxA_TOPLEFT_Y_LIMIT 0x7ff
#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0)
#define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
-#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)
-#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)
+#define VIDOSDxB_BOTRIGHT_X_SHIFT 11
+#define VIDOSDxB_BOTRIGHT_X_LIMIT 0x7ff
#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11)
#define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
-#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)
-#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)
+#define VIDOSDxB_BOTRIGHT_Y_SHIFT 0
+#define VIDOSDxB_BOTRIGHT_Y_LIMIT 0x7ff
#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0)
/* For VIDOSD[1..4]C */
#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)
-#define VIDISD14C_ALPHA0_G_SHIFT (16)
-#define VIDISD14C_ALPHA0_G_LIMIT (0xf)
+#define VIDISD14C_ALPHA0_G_SHIFT 16
+#define VIDISD14C_ALPHA0_G_LIMIT 0xf
#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)
#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)
-#define VIDISD14C_ALPHA0_B_SHIFT (12)
-#define VIDISD14C_ALPHA0_B_LIMIT (0xf)
+#define VIDISD14C_ALPHA0_B_SHIFT 12
+#define VIDISD14C_ALPHA0_B_LIMIT 0xf
#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)
#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)
-#define VIDISD14C_ALPHA1_R_SHIFT (8)
-#define VIDISD14C_ALPHA1_R_LIMIT (0xf)
+#define VIDISD14C_ALPHA1_R_SHIFT 8
+#define VIDISD14C_ALPHA1_R_LIMIT 0xf
#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)
#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)
-#define VIDISD14C_ALPHA1_G_SHIFT (4)
-#define VIDISD14C_ALPHA1_G_LIMIT (0xf)
+#define VIDISD14C_ALPHA1_G_SHIFT 4
+#define VIDISD14C_ALPHA1_G_LIMIT 0xf
#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)
#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)
-#define VIDISD14C_ALPHA1_B_SHIFT (0)
-#define VIDISD14C_ALPHA1_B_LIMIT (0xf)
+#define VIDISD14C_ALPHA1_B_SHIFT 0
+#define VIDISD14C_ALPHA1_B_LIMIT 0xf
#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
/* Video buffer addresses */
@@ -281,21 +297,22 @@
#define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27)
#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
-#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)
-#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)
+#define VIDW_BUF_SIZE_OFFSET_SHIFT 13
+#define VIDW_BUF_SIZE_OFFSET_LIMIT 0x1fff
#define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13)
#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26)
#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
-#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)
-#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)
+#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT 0
+#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT 0x1fff
#define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0)
/* Interrupt controls and status */
+#define VIDINTCON0 0x130
#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
-#define VIDINTCON0_FIFOINTERVAL_SHIFT (20)
-#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f)
+#define VIDINTCON0_FIFOINTERVAL_SHIFT 20
+#define VIDINTCON0_FIFOINTERVAL_LIMIT 0x3f
#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)
#define VIDINTCON0_INT_SYSMAINCON (1 << 19)
@@ -303,7 +320,7 @@
#define VIDINTCON0_INT_I80IFDONE (1 << 17)
#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
-#define VIDINTCON0_FRAMESEL0_SHIFT (15)
+#define VIDINTCON0_FRAMESEL0_SHIFT 15
#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
@@ -318,12 +335,15 @@
#define VIDINTCON0_INT_FRAME (1 << 12)
#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
-#define VIDINTCON0_FIFIOSEL_SHIFT (5)
+#define VIDINTCON0_FIFIOSEL_SHIFT 5
#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
+#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
+#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
+#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
-#define VIDINTCON0_FIFOLEVEL_SHIFT (2)
+#define VIDINTCON0_FIFOLEVEL_SHIFT 2
#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)
#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)
#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
@@ -331,44 +351,67 @@
#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)
#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)
-#define VIDINTCON0_INT_FIFO_SHIFT (0)
+#define VIDINTCON0_INT_FIFO_SHIFT 0
#define VIDINTCON0_INT_ENABLE (1 << 0)
-#define VIDINTCON1 (0x134)
+#define VIDINTCON1 0x134
#define VIDINTCON1_INT_I180 (1 << 2)
#define VIDINTCON1_INT_FRAME (1 << 1)
#define VIDINTCON1_INT_FIFO (1 << 0)
/* Window colour-key control registers */
-#define WKEYCON (0x140) /* 6410,V210 */
+#define WKEYCON 0x140
-#define WKEYCON0 (0x00)
-#define WKEYCON1 (0x04)
+#define WKEYCON0 0x00
+#define WKEYCON1 0x04
#define WxKEYCON0_KEYBL_EN (1 << 26)
#define WxKEYCON0_KEYEN_F (1 << 25)
#define WxKEYCON0_DIRCON (1 << 24)
#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
-#define WxKEYCON0_COMPKEY_SHIFT (0)
-#define WxKEYCON0_COMPKEY_LIMIT (0xffffff)
+#define WxKEYCON0_COMPKEY_SHIFT 0
+#define WxKEYCON0_COMPKEY_LIMIT 0xffffff
#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
-#define WxKEYCON1_COLVAL_SHIFT (0)
-#define WxKEYCON1_COLVAL_LIMIT (0xffffff)
+#define WxKEYCON1_COLVAL_SHIFT 0
+#define WxKEYCON1_COLVAL_LIMIT 0xffffff
#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
+/* Dithering control */
+#define DITHMODE 0x170
+#define DITHMODE_R_POS_MASK (0x3 << 5)
+#define DITHMODE_R_POS_SHIFT 5
+#define DITHMODE_R_POS_8BIT (0x0 << 5)
+#define DITHMODE_R_POS_6BIT (0x1 << 5)
+#define DITHMODE_R_POS_5BIT (0x2 << 5)
+#define DITHMODE_G_POS_MASK (0x3 << 3)
+#define DITHMODE_G_POS_SHIFT 3
+#define DITHMODE_G_POS_8BIT (0x0 << 3)
+#define DITHMODE_G_POS_6BIT (0x1 << 3)
+#define DITHMODE_G_POS_5BIT (0x2 << 3)
+#define DITHMODE_B_POS_MASK (0x3 << 1)
+#define DITHMODE_B_POS_SHIFT 1
+#define DITHMODE_B_POS_8BIT (0x0 << 1)
+#define DITHMODE_B_POS_6BIT (0x1 << 1)
+#define DITHMODE_B_POS_5BIT (0x2 << 1)
+#define DITHMODE_DITH_EN (1 << 0)
/* Window blanking (MAP) */
-
+#define WINxMAP(_win) (0x180 + ((_win) * 4))
#define WINxMAP_MAP (1 << 24)
#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
-#define WINxMAP_MAP_COLOUR_SHIFT (0)
-#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff)
+#define WINxMAP_MAP_COLOUR_SHIFT 0
+#define WINxMAP_MAP_COLOUR_LIMIT 0xffffff
#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
+/* Winodw palette control */
+#define WPALCON 0x1A0
#define WPALCON_PAL_UPDATE (1 << 9)
+#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
+#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
+#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
#define WPALCON_W1PAL_MASK (0x7 << 3)
-#define WPALCON_W1PAL_SHIFT (3)
+#define WPALCON_W1PAL_SHIFT 3
#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
#define WPALCON_W1PAL_24BPP (0x1 << 3)
#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
@@ -376,9 +419,8 @@
#define WPALCON_W1PAL_18BPP (0x4 << 3)
#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
-
#define WPALCON_W0PAL_MASK (0x7 << 0)
-#define WPALCON_W0PAL_SHIFT (0)
+#define WPALCON_W0PAL_SHIFT 0
#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
#define WPALCON_W0PAL_24BPP (0x1 << 0)
#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
@@ -388,122 +430,11 @@
#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
/* Blending equation control */
-#define BLENDCON (0x260)
+#define BLENDCON 0x260
#define BLENDCON_NEW_MASK (1 << 0)
#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
-#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
-#define VIDCON1_FSTATUS_EVEN (1 << 15)
-
-/* Video timing controls */
-#define VIDTCON0 (0x10)
-#define VIDTCON1 (0x14)
-#define VIDTCON2 (0x18)
-
-/* Window position controls */
-
-#define WINCON(_win) (0x20 + ((_win) * 4))
-
-/* OSD1 and OSD4 do not have register D */
-
-#define VIDOSD_BASE (0x40)
-
-#define VIDINTCON0 (0x130)
-
-/* WINCONx */
-
-#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
-#define WINCONx_CSCWIDTH_SHIFT (26)
-#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
-#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
-
-#define WINCONx_ENLOCAL (1 << 22)
-#define WINCONx_BUFSTATUS (1 << 21)
-#define WINCONx_BUFSEL (1 << 20)
-#define WINCONx_BUFAUTOEN (1 << 19)
-#define WINCONx_YCbCr (1 << 13)
-
-#define WINCON1_LOCALSEL_CAMIF (1 << 23)
-
-#define WINCON2_LOCALSEL_CAMIF (1 << 23)
-#define WINCON2_BLD_PIX (1 << 6)
-
-#define WINCON2_ALPHA_SEL (1 << 1)
-#define WINCON2_BPPMODE_MASK (0xf << 2)
-#define WINCON2_BPPMODE_SHIFT (2)
-#define WINCON2_BPPMODE_1BPP (0x0 << 2)
-#define WINCON2_BPPMODE_2BPP (0x1 << 2)
-#define WINCON2_BPPMODE_4BPP (0x2 << 2)
-#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
-#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
-#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
-#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
-#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
-#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
-#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
-#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
-#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
-#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
-#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
-
-#define WINCON3_BLD_PIX (1 << 6)
-
-#define WINCON3_ALPHA_SEL (1 << 1)
-#define WINCON3_BPPMODE_MASK (0xf << 2)
-#define WINCON3_BPPMODE_SHIFT (2)
-#define WINCON3_BPPMODE_1BPP (0x0 << 2)
-#define WINCON3_BPPMODE_2BPP (0x1 << 2)
-#define WINCON3_BPPMODE_4BPP (0x2 << 2)
-#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
-#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
-#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
-#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
-#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
-#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
-#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
-#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
-#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
-#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
-
-#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
-#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
-#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
-
-#define DITHMODE (0x170)
-#define WINxMAP(_win) (0x180 + ((_win) * 4))
-
-
-#define DITHMODE_R_POS_MASK (0x3 << 5)
-#define DITHMODE_R_POS_SHIFT (5)
-#define DITHMODE_R_POS_8BIT (0x0 << 5)
-#define DITHMODE_R_POS_6BIT (0x1 << 5)
-#define DITHMODE_R_POS_5BIT (0x2 << 5)
-
-#define DITHMODE_G_POS_MASK (0x3 << 3)
-#define DITHMODE_G_POS_SHIFT (3)
-#define DITHMODE_G_POS_8BIT (0x0 << 3)
-#define DITHMODE_G_POS_6BIT (0x1 << 3)
-#define DITHMODE_G_POS_5BIT (0x2 << 3)
-
-#define DITHMODE_B_POS_MASK (0x3 << 1)
-#define DITHMODE_B_POS_SHIFT (1)
-#define DITHMODE_B_POS_8BIT (0x0 << 1)
-#define DITHMODE_B_POS_6BIT (0x1 << 1)
-#define DITHMODE_B_POS_5BIT (0x2 << 1)
-
-#define DITHMODE_DITH_EN (1 << 0)
-
-#define WPALCON (0x1A0)
-
-/* Palette control */
-/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
- * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
-#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
-#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
-#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
-
-
/* Notes on per-window bpp settings
*
* Value Win0 Win1 Win2 Win3 Win 4
@@ -526,8 +457,8 @@
*/
/* FIMD Version 8 register offset definitions */
-#define FIMD_V8_VIDTCON0 (0x20010)
-#define FIMD_V8_VIDTCON1 (0x20014)
-#define FIMD_V8_VIDTCON2 (0x20018)
-#define FIMD_V8_VIDTCON3 (0x2001C)
-#define FIMD_V8_VIDCON1 (0x20004)
+#define FIMD_V8_VIDTCON0 0x20010
+#define FIMD_V8_VIDTCON1 0x20014
+#define FIMD_V8_VIDTCON2 0x20018
+#define FIMD_V8_VIDTCON3 0x2001C
+#define FIMD_V8_VIDCON1 0x20004
diff --git a/include/video/sh_mipi_dsi.h b/include/video/sh_mipi_dsi.h
index 06c67fbc4eee..a01f197e6ac1 100644
--- a/include/video/sh_mipi_dsi.h
+++ b/include/video/sh_mipi_dsi.h
@@ -25,8 +25,6 @@ enum sh_mipi_dsi_data_fmt {
MIPI_YUV420,
};
-struct sh_mobile_lcdc_chan_cfg;
-
#define SH_MIPI_DSI_HSABM (1 << 0)
#define SH_MIPI_DSI_HBPBM (1 << 1)
#define SH_MIPI_DSI_HFPBM (1 << 2)
@@ -47,7 +45,7 @@ struct sh_mobile_lcdc_chan_cfg;
struct sh_mipi_dsi_info {
enum sh_mipi_dsi_data_fmt data_format;
- struct sh_mobile_lcdc_chan_cfg *lcd_chan;
+ int channel;
int lane;
unsigned long flags;
u32 clksrc;
diff --git a/include/video/sh_mobile_lcdc.h b/include/video/sh_mobile_lcdc.h
index ff43ffc1aab2..2605fa8adb9c 100644
--- a/include/video/sh_mobile_lcdc.h
+++ b/include/video/sh_mobile_lcdc.h
@@ -163,7 +163,6 @@ struct sh_mobile_lcdc_bl_info {
const char *name;
int max_brightness;
int (*set_brightness)(int brightness);
- int (*get_brightness)(void);
};
struct sh_mobile_lcdc_overlay_cfg {
diff --git a/include/video/sisfb.h b/include/video/sisfb.h
index 6dc5df9e43f3..6ddff93108fb 100644
--- a/include/video/sisfb.h
+++ b/include/video/sisfb.h
@@ -17,197 +17,12 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
*/
-
#ifndef _LINUX_SISFB_H_
#define _LINUX_SISFB_H_
-#include <linux/types.h>
-#include <asm/ioctl.h>
-
-/**********************************************/
-/* PUBLIC */
-/**********************************************/
-
-/* vbflags, public (others in sis.h) */
-#define CRT2_DEFAULT 0x00000001
-#define CRT2_LCD 0x00000002
-#define CRT2_TV 0x00000004
-#define CRT2_VGA 0x00000008
-#define TV_NTSC 0x00000010
-#define TV_PAL 0x00000020
-#define TV_HIVISION 0x00000040
-#define TV_YPBPR 0x00000080
-#define TV_AVIDEO 0x00000100
-#define TV_SVIDEO 0x00000200
-#define TV_SCART 0x00000400
-#define TV_PALM 0x00001000
-#define TV_PALN 0x00002000
-#define TV_NTSCJ 0x00001000
-#define TV_CHSCART 0x00008000
-#define TV_CHYPBPR525I 0x00010000
-#define CRT1_VGA 0x00000000
-#define CRT1_LCDA 0x00020000
-#define VGA2_CONNECTED 0x00040000
-#define VB_DISPTYPE_CRT1 0x00080000 /* CRT1 connected and used */
-#define VB_SINGLE_MODE 0x20000000 /* CRT1 or CRT2; determined by DISPTYPE_CRTx */
-#define VB_MIRROR_MODE 0x40000000 /* CRT1 + CRT2 identical (mirror mode) */
-#define VB_DUALVIEW_MODE 0x80000000 /* CRT1 + CRT2 independent (dual head mode) */
-
-/* Aliases: */
-#define CRT2_ENABLE (CRT2_LCD | CRT2_TV | CRT2_VGA)
-#define TV_STANDARD (TV_NTSC | TV_PAL | TV_PALM | TV_PALN | TV_NTSCJ)
-#define TV_INTERFACE (TV_AVIDEO|TV_SVIDEO|TV_SCART|TV_HIVISION|TV_YPBPR|TV_CHSCART|TV_CHYPBPR525I)
-
-/* Only if TV_YPBPR is set: */
-#define TV_YPBPR525I TV_NTSC
-#define TV_YPBPR525P TV_PAL
-#define TV_YPBPR750P TV_PALM
-#define TV_YPBPR1080I TV_PALN
-#define TV_YPBPRALL (TV_YPBPR525I | TV_YPBPR525P | TV_YPBPR750P | TV_YPBPR1080I)
-
-#define VB_DISPTYPE_DISP2 CRT2_ENABLE
-#define VB_DISPTYPE_CRT2 CRT2_ENABLE
-#define VB_DISPTYPE_DISP1 VB_DISPTYPE_CRT1
-#define VB_DISPMODE_SINGLE VB_SINGLE_MODE
-#define VB_DISPMODE_MIRROR VB_MIRROR_MODE
-#define VB_DISPMODE_DUAL VB_DUALVIEW_MODE
-#define VB_DISPLAY_MODE (SINGLE_MODE | MIRROR_MODE | DUALVIEW_MODE)
-
-/* Structure argument for SISFB_GET_INFO ioctl */
-struct sisfb_info {
- __u32 sisfb_id; /* for identifying sisfb */
-#ifndef SISFB_ID
-#define SISFB_ID 0x53495346 /* Identify myself with 'SISF' */
-#endif
- __u32 chip_id; /* PCI-ID of detected chip */
- __u32 memory; /* total video memory in KB */
- __u32 heapstart; /* heap start offset in KB */
- __u8 fbvidmode; /* current sisfb mode */
-
- __u8 sisfb_version;
- __u8 sisfb_revision;
- __u8 sisfb_patchlevel;
-
- __u8 sisfb_caps; /* sisfb capabilities */
-
- __u32 sisfb_tqlen; /* turbo queue length (in KB) */
-
- __u32 sisfb_pcibus; /* The card's PCI ID */
- __u32 sisfb_pcislot;
- __u32 sisfb_pcifunc;
-
- __u8 sisfb_lcdpdc; /* PanelDelayCompensation */
-
- __u8 sisfb_lcda; /* Detected status of LCDA for low res/text modes */
-
- __u32 sisfb_vbflags;
- __u32 sisfb_currentvbflags;
-
- __u32 sisfb_scalelcd;
- __u32 sisfb_specialtiming;
-
- __u8 sisfb_haveemi;
- __u8 sisfb_emi30,sisfb_emi31,sisfb_emi32,sisfb_emi33;
- __u8 sisfb_haveemilcd;
-
- __u8 sisfb_lcdpdca; /* PanelDelayCompensation for LCD-via-CRT1 */
-
- __u16 sisfb_tvxpos, sisfb_tvypos; /* Warning: Values + 32 ! */
-
- __u32 sisfb_heapsize; /* heap size (in KB) */
- __u32 sisfb_videooffset; /* Offset of viewport in video memory (in bytes) */
-
- __u32 sisfb_curfstn; /* currently running FSTN/DSTN mode */
- __u32 sisfb_curdstn;
-
- __u16 sisfb_pci_vendor; /* PCI vendor (SiS or XGI) */
-
- __u32 sisfb_vbflags2; /* ivideo->vbflags2 */
-
- __u8 sisfb_can_post; /* sisfb can POST this card */
- __u8 sisfb_card_posted; /* card is POSTED */
- __u8 sisfb_was_boot_device; /* This card was the boot video device (ie is primary) */
-
- __u8 reserved[183]; /* for future use */
-};
-
-#define SISFB_CMD_GETVBFLAGS 0x55AA0001 /* no arg; result[1] = vbflags */
-#define SISFB_CMD_SWITCHCRT1 0x55AA0010 /* arg[0]: 99 = query, 0 = off, 1 = on */
-/* more to come */
-
-#define SISFB_CMD_ERR_OK 0x80000000 /* command succeeded */
-#define SISFB_CMD_ERR_LOCKED 0x80000001 /* sisfb is locked */
-#define SISFB_CMD_ERR_EARLY 0x80000002 /* request before sisfb took over gfx system */
-#define SISFB_CMD_ERR_NOVB 0x80000003 /* No video bridge */
-#define SISFB_CMD_ERR_NOCRT2 0x80000004 /* can't change CRT1 status, CRT2 disabled */
-/* more to come */
-#define SISFB_CMD_ERR_UNKNOWN 0x8000ffff /* Unknown command */
-#define SISFB_CMD_ERR_OTHER 0x80010000 /* Other error */
-
-/* Argument for SISFB_CMD ioctl */
-struct sisfb_cmd {
- __u32 sisfb_cmd;
- __u32 sisfb_arg[16];
- __u32 sisfb_result[4];
-};
-
-/* Additional IOCTLs for communication sisfb <> X driver */
-/* If changing this, vgatypes.h must also be changed (for X driver) */
-
-/* ioctl for identifying and giving some info (esp. memory heap start) */
-#define SISFB_GET_INFO_SIZE _IOR(0xF3,0x00,__u32)
-#define SISFB_GET_INFO _IOR(0xF3,0x01,struct sisfb_info)
-
-/* ioctrl to get current vertical retrace status */
-#define SISFB_GET_VBRSTATUS _IOR(0xF3,0x02,__u32)
-
-/* ioctl to enable/disable panning auto-maximize (like nomax parameter) */
-#define SISFB_GET_AUTOMAXIMIZE _IOR(0xF3,0x03,__u32)
-#define SISFB_SET_AUTOMAXIMIZE _IOW(0xF3,0x03,__u32)
-
-/* ioctls to relocate TV output (x=D[31:16], y=D[15:0], + 32)*/
-#define SISFB_GET_TVPOSOFFSET _IOR(0xF3,0x04,__u32)
-#define SISFB_SET_TVPOSOFFSET _IOW(0xF3,0x04,__u32)
-
-/* ioctl for internal sisfb commands (sisfbctrl) */
-#define SISFB_COMMAND _IOWR(0xF3,0x05,struct sisfb_cmd)
-
-/* ioctl for locking sisfb (no register access during lock) */
-/* As of now, only used to avoid register access during
- * the ioctls listed above.
- */
-#define SISFB_SET_LOCK _IOW(0xF3,0x06,__u32)
-
-/* ioctls 0xF3 up to 0x3F reserved for sisfb */
-
-/****************************************************************/
-/* The following are deprecated and should not be used anymore: */
-/****************************************************************/
-/* ioctl for identifying and giving some info (esp. memory heap start) */
-#define SISFB_GET_INFO_OLD _IOR('n',0xF8,__u32)
-/* ioctrl to get current vertical retrace status */
-#define SISFB_GET_VBRSTATUS_OLD _IOR('n',0xF9,__u32)
-/* ioctl to enable/disable panning auto-maximize (like nomax parameter) */
-#define SISFB_GET_AUTOMAXIMIZE_OLD _IOR('n',0xFA,__u32)
-#define SISFB_SET_AUTOMAXIMIZE_OLD _IOW('n',0xFA,__u32)
-/****************************************************************/
-/* End of deprecated ioctl numbers */
-/****************************************************************/
-
-/* For fb memory manager (FBIO_ALLOC, FBIO_FREE) */
-struct sis_memreq {
- __u32 offset;
- __u32 size;
-};
-
-/**********************************************/
-/* PRIVATE */
-/* (for IN-KERNEL usage only) */
-/**********************************************/
-
-#ifdef __KERNEL__
#include <linux/pci.h>
+#include <uapi/video/sisfb.h>
#define UNKNOWN_VGA 0
#define SIS_300_VGA 1
@@ -220,5 +35,3 @@ extern void sis_malloc_new(struct pci_dev *pdev, struct sis_memreq *req);
extern void sis_free(u32 base);
extern void sis_free_new(struct pci_dev *pdev, u32 base);
#endif
-
-#endif
diff --git a/include/video/uvesafb.h b/include/video/uvesafb.h
index 0993a220a3e6..1a91850cb961 100644
--- a/include/video/uvesafb.h
+++ b/include/video/uvesafb.h
@@ -1,63 +1,8 @@
#ifndef _UVESAFB_H
#define _UVESAFB_H
-#include <linux/types.h>
-
-struct v86_regs {
- __u32 ebx;
- __u32 ecx;
- __u32 edx;
- __u32 esi;
- __u32 edi;
- __u32 ebp;
- __u32 eax;
- __u32 eip;
- __u32 eflags;
- __u32 esp;
- __u16 cs;
- __u16 ss;
- __u16 es;
- __u16 ds;
- __u16 fs;
- __u16 gs;
-};
-
-/* Task flags */
-#define TF_VBEIB 0x01
-#define TF_BUF_ESDI 0x02
-#define TF_BUF_ESBX 0x04
-#define TF_BUF_RET 0x08
-#define TF_EXIT 0x10
-
-struct uvesafb_task {
- __u8 flags;
- int buf_len;
- struct v86_regs regs;
-};
-
-/* Constants for the capabilities field
- * in vbe_ib */
-#define VBE_CAP_CAN_SWITCH_DAC 0x01
-#define VBE_CAP_VGACOMPAT 0x02
-
-/* The VBE Info Block */
-struct vbe_ib {
- char vbe_signature[4];
- __u16 vbe_version;
- __u32 oem_string_ptr;
- __u32 capabilities;
- __u32 mode_list_ptr;
- __u16 total_memory;
- __u16 oem_software_rev;
- __u32 oem_vendor_name_ptr;
- __u32 oem_product_name_ptr;
- __u32 oem_product_rev_ptr;
- __u8 reserved[222];
- char oem_data[256];
- char misc_data[512];
-} __attribute__ ((packed));
+#include <uapi/video/uvesafb.h>
-#ifdef __KERNEL__
/* VBE CRTC Info Block */
struct vbe_crtc_ib {
@@ -191,5 +136,4 @@ struct uvesafb_par {
struct vbe_crtc_ib crtc;
};
-#endif /* __KERNEL__ */
#endif /* _UVESAFB_H */
diff --git a/include/video/videomode.h b/include/video/videomode.h
new file mode 100644
index 000000000000..a42156234dd4
--- /dev/null
+++ b/include/video/videomode.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * generic videomode description
+ *
+ * This file is released under the GPLv2
+ */
+
+#ifndef __LINUX_VIDEOMODE_H
+#define __LINUX_VIDEOMODE_H
+
+#include <linux/types.h>
+#include <video/display_timing.h>
+
+/*
+ * Subsystem independent description of a videomode.
+ * Can be generated from struct display_timing.
+ */
+struct videomode {
+ unsigned long pixelclock; /* pixelclock in Hz */
+
+ u32 hactive;
+ u32 hfront_porch;
+ u32 hback_porch;
+ u32 hsync_len;
+
+ u32 vactive;
+ u32 vfront_porch;
+ u32 vback_porch;
+ u32 vsync_len;
+
+ unsigned int dmt_flags; /* VESA DMT flags */
+ unsigned int data_flags; /* video data flags */
+};
+
+/**
+ * videomode_from_timing - convert display timing to videomode
+ * @disp: structure with all possible timing entries
+ * @vm: return value
+ * @index: index into the list of display timings in devicetree
+ *
+ * DESCRIPTION:
+ * This function converts a struct display_timing to a struct videomode.
+ */
+int videomode_from_timing(const struct display_timings *disp,
+ struct videomode *vm, unsigned int index);
+
+#endif
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-09 16:03:47 +0000