diff options
Diffstat (limited to 'include/uapi')
| -rw-r--r-- | include/uapi/asm-generic/statfs.h | 2 | ||||
| -rw-r--r-- | include/uapi/drm/radeon_drm.h | 2 | ||||
| -rw-r--r-- | include/uapi/drm/vmwgfx_drm.h | 1 | ||||
| -rw-r--r-- | include/uapi/linux/Kbuild | 2 | ||||
| -rw-r--r-- | include/uapi/linux/genwqe/genwqe_card.h | 500 | ||||
| -rw-r--r-- | include/uapi/linux/gfs2_ondisk.h | 11 | ||||
| -rw-r--r-- | include/uapi/linux/input.h | 3 | ||||
| -rw-r--r-- | include/uapi/linux/kexec.h | 1 | ||||
| -rw-r--r-- | include/uapi/linux/pci_regs.h | 37 | ||||
| -rw-r--r-- | include/uapi/linux/perf_event.h | 2 | ||||
| -rw-r--r-- | include/uapi/linux/sched.h | 6 | ||||
| -rw-r--r-- | include/uapi/linux/zorro.h | 113 | ||||
| -rw-r--r-- | include/uapi/linux/zorro_ids.h | 552 | ||||
| -rw-r--r-- | include/uapi/sound/compress_params.h | 10 |
14 files changed, 1230 insertions, 12 deletions
diff --git a/include/uapi/asm-generic/statfs.h b/include/uapi/asm-generic/statfs.h index 0999647fca13..cb89cc730f0b 100644 --- a/include/uapi/asm-generic/statfs.h +++ b/include/uapi/asm-generic/statfs.h @@ -13,7 +13,7 @@ */ #ifndef __statfs_word #if __BITS_PER_LONG == 64 -#define __statfs_word long +#define __statfs_word __kernel_long_t #else #define __statfs_word __u32 #endif diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h index 2f3f7ea8c77b..fe421e8a431b 100644 --- a/include/uapi/drm/radeon_drm.h +++ b/include/uapi/drm/radeon_drm.h @@ -983,6 +983,8 @@ struct drm_radeon_cs { #define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17 /* CIK macrotile mode array */ #define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18 +/* query the number of render backends */ +#define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19 struct drm_radeon_info { diff --git a/include/uapi/drm/vmwgfx_drm.h b/include/uapi/drm/vmwgfx_drm.h index bcb0912afe7a..f854ca4a1372 100644 --- a/include/uapi/drm/vmwgfx_drm.h +++ b/include/uapi/drm/vmwgfx_drm.h @@ -75,6 +75,7 @@ #define DRM_VMW_PARAM_FIFO_CAPS 4 #define DRM_VMW_PARAM_MAX_FB_SIZE 5 #define DRM_VMW_PARAM_FIFO_HW_VERSION 6 +#define DRM_VMW_PARAM_MAX_SURF_MEMORY 7 /** * struct drm_vmw_getparam_arg diff --git a/include/uapi/linux/Kbuild b/include/uapi/linux/Kbuild index 33d2b8fe166d..3ce25b5d75a9 100644 --- a/include/uapi/linux/Kbuild +++ b/include/uapi/linux/Kbuild @@ -426,3 +426,5 @@ header-y += x25.h header-y += xattr.h header-y += xfrm.h header-y += hw_breakpoint.h +header-y += zorro.h +header-y += zorro_ids.h diff --git a/include/uapi/linux/genwqe/genwqe_card.h b/include/uapi/linux/genwqe/genwqe_card.h new file mode 100644 index 000000000000..795e957bb840 --- /dev/null +++ b/include/uapi/linux/genwqe/genwqe_card.h @@ -0,0 +1,500 @@ +#ifndef __GENWQE_CARD_H__ +#define __GENWQE_CARD_H__ + +/** + * IBM Accelerator Family 'GenWQE' + * + * (C) Copyright IBM Corp. 2013 + * + * Author: Frank Haverkamp <haver@linux.vnet.ibm.com> + * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com> + * Author: Michael Jung <mijung@de.ibm.com> + * Author: Michael Ruettger <michael@ibmra.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License (version 2 only) + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * User-space API for the GenWQE card. For debugging and test purposes + * the register addresses are included here too. + */ + +#include <linux/types.h> +#include <linux/ioctl.h> + +/* Basename of sysfs, debugfs and /dev interfaces */ +#define GENWQE_DEVNAME "genwqe" + +#define GENWQE_TYPE_ALTERA_230 0x00 /* GenWQE4 Stratix-IV-230 */ +#define GENWQE_TYPE_ALTERA_530 0x01 /* GenWQE4 Stratix-IV-530 */ +#define GENWQE_TYPE_ALTERA_A4 0x02 /* GenWQE5 A4 Stratix-V-A4 */ +#define GENWQE_TYPE_ALTERA_A7 0x03 /* GenWQE5 A7 Stratix-V-A7 */ + +/* MMIO Unit offsets: Each UnitID occupies a defined address range */ +#define GENWQE_UID_OFFS(uid) ((uid) << 24) +#define GENWQE_SLU_OFFS GENWQE_UID_OFFS(0) +#define GENWQE_HSU_OFFS GENWQE_UID_OFFS(1) +#define GENWQE_APP_OFFS GENWQE_UID_OFFS(2) +#define GENWQE_MAX_UNITS 3 + +/* Common offsets per UnitID */ +#define IO_EXTENDED_ERROR_POINTER 0x00000048 +#define IO_ERROR_INJECT_SELECTOR 0x00000060 +#define IO_EXTENDED_DIAG_SELECTOR 0x00000070 +#define IO_EXTENDED_DIAG_READ_MBX 0x00000078 +#define IO_EXTENDED_DIAG_MAP(ring) (0x00000500 | ((ring) << 3)) + +#define GENWQE_EXTENDED_DIAG_SELECTOR(ring, trace) (((ring) << 8) | (trace)) + +/* UnitID 0: Service Layer Unit (SLU) */ + +/* SLU: Unit Configuration Register */ +#define IO_SLU_UNITCFG 0x00000000 +#define IO_SLU_UNITCFG_TYPE_MASK 0x000000000ff00000 /* 27:20 */ + +/* SLU: Fault Isolation Register (FIR) (ac_slu_fir) */ +#define IO_SLU_FIR 0x00000008 /* read only, wr direct */ +#define IO_SLU_FIR_CLR 0x00000010 /* read and clear */ + +/* SLU: First Error Capture Register (FEC/WOF) */ +#define IO_SLU_FEC 0x00000018 + +#define IO_SLU_ERR_ACT_MASK 0x00000020 +#define IO_SLU_ERR_ATTN_MASK 0x00000028 +#define IO_SLU_FIRX1_ACT_MASK 0x00000030 +#define IO_SLU_FIRX0_ACT_MASK 0x00000038 +#define IO_SLU_SEC_LEM_DEBUG_OVR 0x00000040 +#define IO_SLU_EXTENDED_ERR_PTR 0x00000048 +#define IO_SLU_COMMON_CONFIG 0x00000060 + +#define IO_SLU_FLASH_FIR 0x00000108 +#define IO_SLU_SLC_FIR 0x00000110 +#define IO_SLU_RIU_TRAP 0x00000280 +#define IO_SLU_FLASH_FEC 0x00000308 +#define IO_SLU_SLC_FEC 0x00000310 + +/* + * The Virtual Function's Access is from offset 0x00010000 + * The Physical Function's Access is from offset 0x00050000 + * Single Shared Registers exists only at offset 0x00060000 + * + * SLC: Queue Virtual Window Window for accessing into a specific VF + * queue. When accessing the 0x10000 space using the 0x50000 address + * segment, the value indicated here is used to specify which VF + * register is decoded. This register, and the 0x50000 register space + * can only be accessed by the PF. Example, if this register is set to + * 0x2, then a read from 0x50000 is the same as a read from 0x10000 + * from VF=2. + */ + +/* SLC: Queue Segment */ +#define IO_SLC_QUEUE_SEGMENT 0x00010000 +#define IO_SLC_VF_QUEUE_SEGMENT 0x00050000 + +/* SLC: Queue Offset */ +#define IO_SLC_QUEUE_OFFSET 0x00010008 +#define IO_SLC_VF_QUEUE_OFFSET 0x00050008 + +/* SLC: Queue Configuration */ +#define IO_SLC_QUEUE_CONFIG 0x00010010 +#define IO_SLC_VF_QUEUE_CONFIG 0x00050010 + +/* SLC: Job Timout/Only accessible for the PF */ +#define IO_SLC_APPJOB_TIMEOUT 0x00010018 +#define IO_SLC_VF_APPJOB_TIMEOUT 0x00050018 +#define TIMEOUT_250MS 0x0000000f +#define HEARTBEAT_DISABLE 0x0000ff00 + +/* SLC: Queue InitSequence Register */ +#define IO_SLC_QUEUE_INITSQN 0x00010020 +#define IO_SLC_VF_QUEUE_INITSQN 0x00050020 + +/* SLC: Queue Wrap */ +#define IO_SLC_QUEUE_WRAP 0x00010028 +#define IO_SLC_VF_QUEUE_WRAP 0x00050028 + +/* SLC: Queue Status */ +#define IO_SLC_QUEUE_STATUS 0x00010100 +#define IO_SLC_VF_QUEUE_STATUS 0x00050100 + +/* SLC: Queue Working Time */ +#define IO_SLC_QUEUE_WTIME 0x00010030 +#define IO_SLC_VF_QUEUE_WTIME 0x00050030 + +/* SLC: Queue Error Counts */ +#define IO_SLC_QUEUE_ERRCNTS 0x00010038 +#define IO_SLC_VF_QUEUE_ERRCNTS 0x00050038 + +/* SLC: Queue Loast Response Word */ +#define IO_SLC_QUEUE_LRW 0x00010040 +#define IO_SLC_VF_QUEUE_LRW 0x00050040 + +/* SLC: Freerunning Timer */ +#define IO_SLC_FREE_RUNNING_TIMER 0x00010108 +#define IO_SLC_VF_FREE_RUNNING_TIMER 0x00050108 + +/* SLC: Queue Virtual Access Region */ +#define IO_PF_SLC_VIRTUAL_REGION 0x00050000 + +/* SLC: Queue Virtual Window */ +#define IO_PF_SLC_VIRTUAL_WINDOW 0x00060000 + +/* SLC: DDCB Application Job Pending [n] (n=0:63) */ +#define IO_PF_SLC_JOBPEND(n) (0x00061000 + 8*(n)) +#define IO_SLC_JOBPEND(n) IO_PF_SLC_JOBPEND(n) + +/* SLC: Parser Trap RAM [n] (n=0:31) */ +#define IO_SLU_SLC_PARSE_TRAP(n) (0x00011000 + 8*(n)) + +/* SLC: Dispatcher Trap RAM [n] (n=0:31) */ +#define IO_SLU_SLC_DISP_TRAP(n) (0x00011200 + 8*(n)) + +/* Global Fault Isolation Register (GFIR) */ +#define IO_SLC_CFGREG_GFIR 0x00020000 +#define GFIR_ERR_TRIGGER 0x0000ffff + +/* SLU: Soft Reset Register */ +#define IO_SLC_CFGREG_SOFTRESET 0x00020018 + +/* SLU: Misc Debug Register */ +#define IO_SLC_MISC_DEBUG 0x00020060 +#define IO_SLC_MISC_DEBUG_CLR 0x00020068 +#define IO_SLC_MISC_DEBUG_SET 0x00020070 + +/* Temperature Sensor Reading */ +#define IO_SLU_TEMPERATURE_SENSOR 0x00030000 +#define IO_SLU_TEMPERATURE_CONFIG 0x00030008 + +/* Voltage Margining Control */ +#define IO_SLU_VOLTAGE_CONTROL 0x00030080 +#define IO_SLU_VOLTAGE_NOMINAL 0x00000000 +#define IO_SLU_VOLTAGE_DOWN5 0x00000006 +#define IO_SLU_VOLTAGE_UP5 0x00000007 + +/* Direct LED Control Register */ +#define IO_SLU_LEDCONTROL 0x00030100 + +/* SLU: Flashbus Direct Access -A5 */ +#define IO_SLU_FLASH_DIRECTACCESS 0x00040010 + +/* SLU: Flashbus Direct Access2 -A5 */ +#define IO_SLU_FLASH_DIRECTACCESS2 0x00040020 + +/* SLU: Flashbus Command Interface -A5 */ +#define IO_SLU_FLASH_CMDINTF 0x00040030 + +/* SLU: BitStream Loaded */ +#define IO_SLU_BITSTREAM 0x00040040 + +/* This Register has a switch which will change the CAs to UR */ +#define IO_HSU_ERR_BEHAVIOR 0x01001010 + +#define IO_SLC2_SQB_TRAP 0x00062000 +#define IO_SLC2_QUEUE_MANAGER_TRAP 0x00062008 +#define IO_SLC2_FLS_MASTER_TRAP 0x00062010 + +/* UnitID 1: HSU Registers */ +#define IO_HSU_UNITCFG 0x01000000 +#define IO_HSU_FIR 0x01000008 +#define IO_HSU_FIR_CLR 0x01000010 +#define IO_HSU_FEC 0x01000018 +#define IO_HSU_ERR_ACT_MASK 0x01000020 +#define IO_HSU_ERR_ATTN_MASK 0x01000028 +#define IO_HSU_FIRX1_ACT_MASK 0x01000030 +#define IO_HSU_FIRX0_ACT_MASK 0x01000038 +#define IO_HSU_SEC_LEM_DEBUG_OVR 0x01000040 +#define IO_HSU_EXTENDED_ERR_PTR 0x01000048 +#define IO_HSU_COMMON_CONFIG 0x01000060 + +/* UnitID 2: Application Unit (APP) */ +#define IO_APP_UNITCFG 0x02000000 +#define IO_APP_FIR 0x02000008 +#define IO_APP_FIR_CLR 0x02000010 +#define IO_APP_FEC 0x02000018 +#define IO_APP_ERR_ACT_MASK 0x02000020 +#define IO_APP_ERR_ATTN_MASK 0x02000028 +#define IO_APP_FIRX1_ACT_MASK 0x02000030 +#define IO_APP_FIRX0_ACT_MASK 0x02000038 +#define IO_APP_SEC_LEM_DEBUG_OVR 0x02000040 +#define IO_APP_EXTENDED_ERR_PTR 0x02000048 +#define IO_APP_COMMON_CONFIG 0x02000060 + +#define IO_APP_DEBUG_REG_01 0x02010000 +#define IO_APP_DEBUG_REG_02 0x02010008 +#define IO_APP_DEBUG_REG_03 0x02010010 +#define IO_APP_DEBUG_REG_04 0x02010018 +#define IO_APP_DEBUG_REG_05 0x02010020 +#define IO_APP_DEBUG_REG_06 0x02010028 +#define IO_APP_DEBUG_REG_07 0x02010030 +#define IO_APP_DEBUG_REG_08 0x02010038 +#define IO_APP_DEBUG_REG_09 0x02010040 +#define IO_APP_DEBUG_REG_10 0x02010048 +#define IO_APP_DEBUG_REG_11 0x02010050 +#define IO_APP_DEBUG_REG_12 0x02010058 +#define IO_APP_DEBUG_REG_13 0x02010060 +#define IO_APP_DEBUG_REG_14 0x02010068 +#define IO_APP_DEBUG_REG_15 0x02010070 +#define IO_APP_DEBUG_REG_16 0x02010078 +#define IO_APP_DEBUG_REG_17 0x02010080 +#define IO_APP_DEBUG_REG_18 0x02010088 + +/* Read/write from/to registers */ +struct genwqe_reg_io { + __u64 num; /* register offset/address */ + __u64 val64; +}; + +/* + * All registers of our card will return values not equal this values. + * If we see IO_ILLEGAL_VALUE on any of our MMIO register reads, the + * card can be considered as unusable. It will need recovery. + */ +#define IO_ILLEGAL_VALUE 0xffffffffffffffffull + +/* + * Generic DDCB execution interface. + * + * This interface is a first prototype resulting from discussions we + * had with other teams which wanted to use the Genwqe card. It allows + * to issue a DDCB request in a generic way. The request will block + * until it finishes or time out with error. + * + * Some DDCBs require DMA addresses to be specified in the ASIV + * block. The interface provies the capability to let the kernel + * driver know where those addresses are by specifying the ATS field, + * such that it can replace the user-space addresses with appropriate + * DMA addresses or DMA addresses of a scatter gather list which is + * dynamically created. + * + * Our hardware will refuse DDCB execution if the ATS field is not as + * expected. That means the DDCB execution engine in the chip knows + * where it expects DMA addresses within the ASIV part of the DDCB and + * will check that against the ATS field definition. Any invalid or + * unknown ATS content will lead to DDCB refusal. + */ + +/* Genwqe chip Units */ +#define DDCB_ACFUNC_SLU 0x00 /* chip service layer unit */ +#define DDCB_ACFUNC_APP 0x01 /* chip application */ + +/* DDCB return codes (RETC) */ +#define DDCB_RETC_IDLE 0x0000 /* Unexecuted/DDCB created */ +#define DDCB_RETC_PENDING 0x0101 /* Pending Execution */ +#define DDCB_RETC_COMPLETE 0x0102 /* Cmd complete. No error */ +#define DDCB_RETC_FAULT 0x0104 /* App Err, recoverable */ +#define DDCB_RETC_ERROR 0x0108 /* App Err, non-recoverable */ +#define DDCB_RETC_FORCED_ERROR 0x01ff /* overwritten by driver */ + +#define DDCB_RETC_UNEXEC 0x0110 /* Unexe/Removed from queue */ +#define DDCB_RETC_TERM 0x0120 /* Terminated */ +#define DDCB_RETC_RES0 0x0140 /* Reserved */ +#define DDCB_RETC_RES1 0x0180 /* Reserved */ + +/* DDCB Command Options (CMDOPT) */ +#define DDCB_OPT_ECHO_FORCE_NO 0x0000 /* ECHO DDCB */ +#define DDCB_OPT_ECHO_FORCE_102 0x0001 /* force return code */ +#define DDCB_OPT_ECHO_FORCE_104 0x0002 +#define DDCB_OPT_ECHO_FORCE_108 0x0003 + +#define DDCB_OPT_ECHO_FORCE_110 0x0004 /* only on PF ! */ +#define DDCB_OPT_ECHO_FORCE_120 0x0005 +#define DDCB_OPT_ECHO_FORCE_140 0x0006 +#define DDCB_OPT_ECHO_FORCE_180 0x0007 + +#define DDCB_OPT_ECHO_COPY_NONE (0 << 5) +#define DDCB_OPT_ECHO_COPY_ALL (1 << 5) + +/* Definitions of Service Layer Commands */ +#define SLCMD_ECHO_SYNC 0x00 /* PF/VF */ +#define SLCMD_MOVE_FLASH 0x06 /* PF only */ +#define SLCMD_MOVE_FLASH_FLAGS_MODE 0x03 /* bit 0 and 1 used for mode */ +#define SLCMD_MOVE_FLASH_FLAGS_DLOAD 0 /* mode: download */ +#define SLCMD_MOVE_FLASH_FLAGS_EMUL 1 /* mode: emulation */ +#define SLCMD_MOVE_FLASH_FLAGS_UPLOAD 2 /* mode: upload */ +#define SLCMD_MOVE_FLASH_FLAGS_VERIFY 3 /* mode: verify */ +#define SLCMD_MOVE_FLASH_FLAG_NOTAP (1 << 2)/* just dump DDCB and exit */ +#define SLCMD_MOVE_FLASH_FLAG_POLL (1 << 3)/* wait for RETC >= 0102 */ +#define SLCMD_MOVE_FLASH_FLAG_PARTITION (1 << 4) +#define SLCMD_MOVE_FLASH_FLAG_ERASE (1 << 5) + +enum genwqe_card_state { + GENWQE_CARD_UNUSED = 0, + GENWQE_CARD_USED = 1, + GENWQE_CARD_FATAL_ERROR = 2, + GENWQE_CARD_STATE_MAX, +}; + +/* common struct for chip image exchange */ +struct genwqe_bitstream { + __u64 data_addr; /* pointer to image data */ + __u32 size; /* size of image file */ + __u32 crc; /* crc of this image */ + __u64 target_addr; /* starting address in Flash */ + __u32 partition; /* '0', '1', or 'v' */ + __u32 uid; /* 1=host/x=dram */ + + __u64 slu_id; /* informational/sim: SluID */ + __u64 app_id; /* informational/sim: AppID */ + + __u16 retc; /* returned from processing */ + __u16 attn; /* attention code from processing */ + __u32 progress; /* progress code from processing */ +}; + +/* Issuing a specific DDCB command */ +#define DDCB_LENGTH 256 /* for debug data */ +#define DDCB_ASIV_LENGTH 104 /* len of the DDCB ASIV array */ +#define DDCB_ASIV_LENGTH_ATS 96 /* ASIV in ATS architecture */ +#define DDCB_ASV_LENGTH 64 /* len of the DDCB ASV array */ +#define DDCB_FIXUPS 12 /* maximum number of fixups */ + +struct genwqe_debug_data { + char driver_version[64]; + __u64 slu_unitcfg; + __u64 app_unitcfg; + + __u8 ddcb_before[DDCB_LENGTH]; + __u8 ddcb_prev[DDCB_LENGTH]; + __u8 ddcb_finished[DDCB_LENGTH]; +}; + +/* + * Address Translation Specification (ATS) definitions + * + * Each 4 bit within the ATS 64-bit word specify the required address + * translation at the defined offset. + * + * 63 LSB + * 6666.5555.5555.5544.4444.4443.3333.3333 ... 11 + * 3210.9876.5432.1098.7654.3210.9876.5432 ... 1098.7654.3210 + * + * offset: 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 ... 0x68 0x70 0x78 + * res res res res ASIV ... + * The first 4 entries in the ATS word are reserved. The following nibbles + * each describe at an 8 byte offset the format of the required data. + */ +#define ATS_TYPE_DATA 0x0ull /* data */ +#define ATS_TYPE_FLAT_RD 0x4ull /* flat buffer read only */ +#define ATS_TYPE_FLAT_RDWR 0x5ull /* flat buffer read/write */ +#define ATS_TYPE_SGL_RD 0x6ull /* sgl read only */ +#define ATS_TYPE_SGL_RDWR 0x7ull /* sgl read/write */ + +#define ATS_SET_FLAGS(_struct, _field, _flags) \ + (((_flags) & 0xf) << (44 - (4 * (offsetof(_struct, _field) / 8)))) + +#define ATS_GET_FLAGS(_ats, _byte_offs) \ + (((_ats) >> (44 - (4 * ((_byte_offs) / 8)))) & 0xf) + +/** + * struct genwqe_ddcb_cmd - User parameter for generic DDCB commands + * + * On the way into the kernel the driver will read the whole data + * structure. On the way out the driver will not copy the ASIV data + * back to user-space. + */ +struct genwqe_ddcb_cmd { + /* START of data copied to/from driver */ + __u64 next_addr; /* chaining genwqe_ddcb_cmd */ + __u64 flags; /* reserved */ + + __u8 acfunc; /* accelerators functional unit */ + __u8 cmd; /* command to execute */ + __u8 asiv_length; /* used parameter length */ + __u8 asv_length; /* length of valid return values */ + __u16 cmdopts; /* command options */ + __u16 retc; /* return code from processing */ + + __u16 attn; /* attention code from processing */ + __u16 vcrc; /* variant crc16 */ + __u32 progress; /* progress code from processing */ + + __u64 deque_ts; /* dequeue time stamp */ + __u64 cmplt_ts; /* completion time stamp */ + __u64 disp_ts; /* SW processing start */ + + /* move to end and avoid copy-back */ + __u64 ddata_addr; /* collect debug data */ + + /* command specific values */ + __u8 asv[DDCB_ASV_LENGTH]; + + /* END of data copied from driver */ + union { + struct { + __u64 ats; + __u8 asiv[DDCB_ASIV_LENGTH_ATS]; + }; + /* used for flash update to keep it backward compatible */ + __u8 __asiv[DDCB_ASIV_LENGTH]; + }; + /* END of data copied to driver */ +}; + +#define GENWQE_IOC_CODE 0xa5 + +/* Access functions */ +#define GENWQE_READ_REG64 _IOR(GENWQE_IOC_CODE, 30, struct genwqe_reg_io) +#define GENWQE_WRITE_REG64 _IOW(GENWQE_IOC_CODE, 31, struct genwqe_reg_io) +#define GENWQE_READ_REG32 _IOR(GENWQE_IOC_CODE, 32, struct genwqe_reg_io) +#define GENWQE_WRITE_REG32 _IOW(GENWQE_IOC_CODE, 33, struct genwqe_reg_io) +#define GENWQE_READ_REG16 _IOR(GENWQE_IOC_CODE, 34, struct genwqe_reg_io) +#define GENWQE_WRITE_REG16 _IOW(GENWQE_IOC_CODE, 35, struct genwqe_reg_io) + +#define GENWQE_GET_CARD_STATE _IOR(GENWQE_IOC_CODE, 36, enum genwqe_card_state) + +/** + * struct genwqe_mem - Memory pinning/unpinning information + * @addr: virtual user space address + * @size: size of the area pin/dma-map/unmap + * direction: 0: read/1: read and write + * + * Avoid pinning and unpinning of memory pages dynamically. Instead + * the idea is to pin the whole buffer space required for DDCB + * opertionas in advance. The driver will reuse this pinning and the + * memory associated with it to setup the sglists for the DDCB + * requests without the need to allocate and free memory or map and + * unmap to get the DMA addresses. + * + * The inverse operation needs to be called after the pinning is not + * needed anymore. The pinnings else the pinnings will get removed + * after the device is closed. Note that pinnings will required + * memory. + */ +struct genwqe_mem { + __u64 addr; + __u64 size; + __u64 direction; + __u64 flags; +}; + +#define GENWQE_PIN_MEM _IOWR(GENWQE_IOC_CODE, 40, struct genwqe_mem) +#define GENWQE_UNPIN_MEM _IOWR(GENWQE_IOC_CODE, 41, struct genwqe_mem) + +/* + * Generic synchronous DDCB execution interface. + * Synchronously execute a DDCB. + * + * Return: 0 on success or negative error code. + * -EINVAL: Invalid parameters (ASIV_LEN, ASV_LEN, illegal fixups + * no mappings found/could not create mappings + * -EFAULT: illegal addresses in fixups, purging failed + * -EBADMSG: enqueing failed, retc != DDCB_RETC_COMPLETE + */ +#define GENWQE_EXECUTE_DDCB \ + _IOWR(GENWQE_IOC_CODE, 50, struct genwqe_ddcb_cmd) + +#define GENWQE_EXECUTE_RAW_DDCB \ + _IOWR(GENWQE_IOC_CODE, 51, struct genwqe_ddcb_cmd) + +/* Service Layer functions (PF only) */ +#define GENWQE_SLU_UPDATE _IOWR(GENWQE_IOC_CODE, 80, struct genwqe_bitstream) +#define GENWQE_SLU_READ _IOWR(GENWQE_IOC_CODE, 81, struct genwqe_bitstream) + +#endif /* __GENWQE_CARD_H__ */ diff --git a/include/uapi/linux/gfs2_ondisk.h b/include/uapi/linux/gfs2_ondisk.h index b2de1f9a88d6..0f24c07aed51 100644 --- a/include/uapi/linux/gfs2_ondisk.h +++ b/include/uapi/linux/gfs2_ondisk.h @@ -319,7 +319,16 @@ struct gfs2_leaf { __be32 lf_dirent_format; /* Format of the dirents */ __be64 lf_next; /* Next leaf, if overflow */ - __u8 lf_reserved[64]; + union { + __u8 lf_reserved[64]; + struct { + __be64 lf_inode; /* Dir inode number */ + __be32 lf_dist; /* Dist from inode on chain */ + __be32 lf_nsec; /* Last ins/del usecs */ + __be64 lf_sec; /* Last ins/del in secs */ + __u8 lf_reserved2[40]; + }; + }; }; /* diff --git a/include/uapi/linux/input.h b/include/uapi/linux/input.h index ecc88592ecbe..bd24470d24a2 100644 --- a/include/uapi/linux/input.h +++ b/include/uapi/linux/input.h @@ -464,7 +464,8 @@ struct input_keymap_entry { #define KEY_BRIGHTNESS_ZERO 244 /* brightness off, use ambient */ #define KEY_DISPLAY_OFF 245 /* display device to off state */ -#define KEY_WIMAX 246 +#define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */ +#define KEY_WIMAX KEY_WWAN #define KEY_RFKILL 247 /* Key that controls all radios */ #define KEY_MICMUTE 248 /* Mute / unmute the microphone */ diff --git a/include/uapi/linux/kexec.h b/include/uapi/linux/kexec.h index 104838f65bc1..d6629d49a243 100644 --- a/include/uapi/linux/kexec.h +++ b/include/uapi/linux/kexec.h @@ -18,6 +18,7 @@ */ #define KEXEC_ARCH_DEFAULT ( 0 << 16) #define KEXEC_ARCH_386 ( 3 << 16) +#define KEXEC_ARCH_68K ( 4 << 16) #define KEXEC_ARCH_X86_64 (62 << 16) #define KEXEC_ARCH_PPC (20 << 16) #define KEXEC_ARCH_PPC64 (21 << 16) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 4a98e85438a7..ab6b4e7f6657 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -518,8 +518,16 @@ #define PCI_EXP_SLTCTL_CCIE 0x0010 /* Command Completed Interrupt Enable */ #define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */ #define PCI_EXP_SLTCTL_AIC 0x00c0 /* Attention Indicator Control */ +#define PCI_EXP_SLTCTL_ATTN_IND_ON 0x0040 /* Attention Indicator on */ +#define PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 /* Attention Indicator blinking */ +#define PCI_EXP_SLTCTL_ATTN_IND_OFF 0x00c0 /* Attention Indicator off */ #define PCI_EXP_SLTCTL_PIC 0x0300 /* Power Indicator Control */ +#define PCI_EXP_SLTCTL_PWR_IND_ON 0x0100 /* Power Indicator on */ +#define PCI_EXP_SLTCTL_PWR_IND_BLINK 0x0200 /* Power Indicator blinking */ +#define PCI_EXP_SLTCTL_PWR_IND_OFF 0x0300 /* Power Indicator off */ #define PCI_EXP_SLTCTL_PCC 0x0400 /* Power Controller Control */ +#define PCI_EXP_SLTCTL_PWR_ON 0x0000 /* Power On */ +#define PCI_EXP_SLTCTL_PWR_OFF 0x0400 /* Power Off */ #define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */ #define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */ #define PCI_EXP_SLTSTA 26 /* Slot Status */ @@ -677,17 +685,34 @@ #define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */ /* Virtual Channel */ -#define PCI_VC_PORT_REG1 4 -#define PCI_VC_REG1_EVCC 0x7 /* extended VC count */ -#define PCI_VC_PORT_REG2 8 -#define PCI_VC_REG2_32_PHASE 0x2 -#define PCI_VC_REG2_64_PHASE 0x4 -#define PCI_VC_REG2_128_PHASE 0x8 +#define PCI_VC_PORT_CAP1 4 +#define PCI_VC_CAP1_EVCC 0x00000007 /* extended VC count */ +#define PCI_VC_CAP1_LPEVCC 0x00000070 /* low prio extended VC count */ +#define PCI_VC_CAP1_ARB_SIZE 0x00000c00 +#define PCI_VC_PORT_CAP2 8 +#define PCI_VC_CAP2_32_PHASE 0x00000002 +#define PCI_VC_CAP2_64_PHASE 0x00000004 +#define PCI_VC_CAP2_128_PHASE 0x00000008 +#define PCI_VC_CAP2_ARB_OFF 0xff000000 #define PCI_VC_PORT_CTRL 12 +#define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001 #define PCI_VC_PORT_STATUS 14 +#define PCI_VC_PORT_STATUS_TABLE 0x00000001 #define PCI_VC_RES_CAP 16 +#define PCI_VC_RES_CAP_32_PHASE 0x00000002 +#define PCI_VC_RES_CAP_64_PHASE 0x00000004 +#define PCI_VC_RES_CAP_128_PHASE 0x00000008 +#define PCI_VC_RES_CAP_128_PHASE_TB 0x00000010 +#define PCI_VC_RES_CAP_256_PHASE 0x00000020 +#define PCI_VC_RES_CAP_ARB_OFF 0xff000000 #define PCI_VC_RES_CTRL 20 +#define PCI_VC_RES_CTRL_LOAD_TABLE 0x00010000 +#define PCI_VC_RES_CTRL_ARB_SELECT 0x000e0000 +#define PCI_VC_RES_CTRL_ID 0x07000000 +#define PCI_VC_RES_CTRL_ENABLE 0x80000000 #define PCI_VC_RES_STATUS 26 +#define PCI_VC_RES_STATUS_TABLE 0x00000001 +#define PCI_VC_RES_STATUS_NEGO 0x00000002 #define PCI_CAP_VC_BASE_SIZEOF 0x10 #define PCI_CAP_VC_PER_VC_SIZEOF 0x0C diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h index e1802d6153ae..e244ed412745 100644 --- a/include/uapi/linux/perf_event.h +++ b/include/uapi/linux/perf_event.h @@ -679,6 +679,7 @@ enum perf_event_type { * * { u64 weight; } && PERF_SAMPLE_WEIGHT * { u64 data_src; } && PERF_SAMPLE_DATA_SRC + * { u64 transaction; } && PERF_SAMPLE_TRANSACTION * }; */ PERF_RECORD_SAMPLE = 9, @@ -724,6 +725,7 @@ enum perf_callchain_context { #define PERF_FLAG_FD_NO_GROUP (1U << 0) #define PERF_FLAG_FD_OUTPUT (1U << 1) #define PERF_FLAG_PID_CGROUP (1U << 2) /* pid=cgroup id, per-cpu mode only */ +#define PERF_FLAG_FD_CLOEXEC (1U << 3) /* O_CLOEXEC */ union perf_mem_data_src { __u64 val; diff --git a/include/uapi/linux/sched.h b/include/uapi/linux/sched.h index 5a0f945927ac..34f9d7387d13 100644 --- a/include/uapi/linux/sched.h +++ b/include/uapi/linux/sched.h @@ -39,8 +39,14 @@ #define SCHED_BATCH 3 /* SCHED_ISO: reserved but not implemented yet */ #define SCHED_IDLE 5 +#define SCHED_DEADLINE 6 + /* Can be ORed in to make sure the process is reverted back to SCHED_NORMAL on fork */ #define SCHED_RESET_ON_FORK 0x40000000 +/* + * For the sched_{set,get}attr() calls + */ +#define SCHED_FLAG_RESET_ON_FORK 0x01 #endif /* _UAPI_LINUX_SCHED_H */ diff --git a/include/uapi/linux/zorro.h b/include/uapi/linux/zorro.h new file mode 100644 index 000000000000..59d021b242ed --- /dev/null +++ b/include/uapi/linux/zorro.h @@ -0,0 +1,113 @@ +/* + * linux/zorro.h -- Amiga AutoConfig (Zorro) Bus Definitions + * + * Copyright (C) 1995--2003 Geert Uytterhoeven + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#ifndef _UAPI_LINUX_ZORRO_H +#define _UAPI_LINUX_ZORRO_H + +#include <linux/types.h> + + + /* + * Each Zorro board has a 32-bit ID of the form + * + * mmmmmmmmmmmmmmmmppppppppeeeeeeee + * + * with + * + * mmmmmmmmmmmmmmmm 16-bit Manufacturer ID (assigned by CBM (sigh)) + * pppppppp 8-bit Product ID (assigned by manufacturer) + * eeeeeeee 8-bit Extended Product ID (currently only used + * for some GVP boards) + */ + + +#define ZORRO_MANUF(id) ((id) >> 16) +#define ZORRO_PROD(id) (((id) >> 8) & 0xff) +#define ZORRO_EPC(id) ((id) & 0xff) + +#define ZORRO_ID(manuf, prod, epc) \ + ((ZORRO_MANUF_##manuf << 16) | ((prod) << 8) | (epc)) + +typedef __u32 zorro_id; + + +/* Include the ID list */ +#include <linux/zorro_ids.h> + + + /* + * GVP identifies most of its products through the 'extended product code' + * (epc). The epc has to be ANDed with the GVP_PRODMASK before the + * identification. + */ + +#define GVP_PRODMASK (0xf8) +#define GVP_SCSICLKMASK (0x01) + +enum GVP_flags { + GVP_IO = 0x01, + GVP_ACCEL = 0x02, + GVP_SCSI = 0x04, + GVP_24BITDMA = 0x08, + GVP_25BITDMA = 0x10, + GVP_NOBANK = 0x20, + GVP_14MHZ = 0x40, +}; + + +struct Node { + __be32 ln_Succ; /* Pointer to next (successor) */ + __be32 ln_Pred; /* Pointer to previous (predecessor) */ + __u8 ln_Type; + __s8 ln_Pri; /* Priority, for sorting */ + __be32 ln_Name; /* ID string, null terminated */ +} __packed; + +struct ExpansionRom { + /* -First 16 bytes of the expansion ROM */ + __u8 er_Type; /* Board type, size and flags */ + __u8 er_Product; /* Product number, assigned by manufacturer */ + __u8 er_Flags; /* Flags */ + __u8 er_Reserved03; /* Must be zero ($ff inverted) */ + __be16 er_Manufacturer; /* Unique ID, ASSIGNED BY COMMODORE-AMIGA! */ + __be32 er_SerialNumber; /* Available for use by manufacturer */ + __be16 er_InitDiagVec; /* Offset to optional "DiagArea" structure */ + __u8 er_Reserved0c; + __u8 er_Reserved0d; + __u8 er_Reserved0e; + __u8 er_Reserved0f; +} __packed; + +/* er_Type board type bits */ +#define ERT_TYPEMASK 0xc0 +#define ERT_ZORROII 0xc0 +#define ERT_ZORROIII 0x80 + +/* other bits defined in er_Type */ +#define ERTB_MEMLIST 5 /* Link RAM into free memory list */ +#define ERTF_MEMLIST (1<<5) + +struct ConfigDev { + struct Node cd_Node; + __u8 cd_Flags; /* (read/write) */ + __u8 cd_Pad; /* reserved */ + struct ExpansionRom cd_Rom; /* copy of board's expansion ROM */ + __be32 cd_BoardAddr; /* where in memory the board was placed */ + __be32 cd_BoardSize; /* size of board in bytes */ + __be16 cd_SlotAddr; /* which slot number (PRIVATE) */ + __be16 cd_SlotSize; /* number of slots (PRIVATE) */ + __be32 cd_Driver; /* pointer to node of driver */ + __be32 cd_NextCD; /* linked list of drivers to config */ + __be32 cd_Unused[4]; /* for whatever the driver wants */ +} __packed; + +#define ZORRO_NUM_AUTO 16 + +#endif /* _UAPI_LINUX_ZORRO_H */ diff --git a/include/uapi/linux/zorro_ids.h b/include/uapi/linux/zorro_ids.h new file mode 100644 index 000000000000..74bc53bcfdcf --- /dev/null +++ b/include/uapi/linux/zorro_ids.h @@ -0,0 +1,552 @@ +/* + * Zorro board IDs + * + * Please keep sorted. + */ + + +#define ZORRO_MANUF_PACIFIC_PERIPHERALS 0x00D3 +#define ZORRO_PROD_PACIFIC_PERIPHERALS_SE_2000_A500 ZORRO_ID(PACIFIC_PERIPHERALS, 0x00, 0) +#define ZORRO_PROD_PACIFIC_PERIPHERALS_SCSI ZORRO_ID(PACIFIC_PERIPHERALS, 0x0A, 0) + +#define ZORRO_MANUF_MACROSYSTEMS_USA_2 0x0100 +#define ZORRO_PROD_MACROSYSTEMS_WARP_ENGINE ZORRO_ID(MACROSYSTEMS_USA_2, 0x13, 0) + +#define ZORRO_MANUF_KUPKE_1 0x00DD +#define ZORRO_PROD_KUPKE_GOLEM_RAM_BOX_2MB ZORRO_ID(KUPKE_1, 0x00, 0) + +#define ZORRO_MANUF_MEMPHIS 0x0100 +#define ZORRO_PROD_MEMPHIS_STORMBRINGER ZORRO_ID(MEMPHIS, 0x00, 0) + +#define ZORRO_MANUF_3_STATE 0x0200 +#define ZORRO_PROD_3_STATE_MEGAMIX_2000 ZORRO_ID(3_STATE, 0x02, 0) + +#define ZORRO_MANUF_COMMODORE_BRAUNSCHWEIG 0x0201 +#define ZORRO_PROD_CBM_A2088_A2286 ZORRO_ID(COMMODORE_BRAUNSCHWEIG, 0x01, 0) +#define ZORRO_PROD_CBM_A2286 ZORRO_ID(COMMODORE_BRAUNSCHWEIG, 0x02, 0) +#define ZORRO_PROD_CBM_A4091_1 ZORRO_ID(COMMODORE_BRAUNSCHWEIG, 0x54, 0) +#define ZORRO_PROD_CBM_A2386SX_1 ZORRO_ID(COMMODORE_BRAUNSCHWEIG, 0x67, 0) + +#define ZORRO_MANUF_COMMODORE_WEST_CHESTER_1 0x0202 +#define ZORRO_PROD_CBM_A2090A ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x01, 0) +#define ZORRO_PROD_CBM_A590_A2091_1 ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x02, 0) +#define ZORRO_PROD_CBM_A590_A2091_2 ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x03, 0) +#define ZORRO_PROD_CBM_A2090B ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x04, 0) +#define ZORRO_PROD_CBM_A2060 ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x09, 0) +#define ZORRO_PROD_CBM_A590_A2052_A2058_A2091 ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x0A, 0) +#define ZORRO_PROD_CBM_A560_RAM ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x20, 0) +#define ZORRO_PROD_CBM_A2232_PROTOTYPE ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x45, 0) +#define ZORRO_PROD_CBM_A2232 ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x46, 0) +#define ZORRO_PROD_CBM_A2620 ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x50, 0) +#define ZORRO_PROD_CBM_A2630 ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x51, 0) +#define ZORRO_PROD_CBM_A4091_2 ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x54, 0) +#define ZORRO_PROD_CBM_A2065_1 ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x5A, 0) +#define ZORRO_PROD_CBM_ROMULATOR ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x60, 0) +#define ZORRO_PROD_CBM_A3000_TEST_FIXTURE ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x61, 0) +#define ZORRO_PROD_CBM_A2386SX_2 ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x67, 0) +#define ZORRO_PROD_CBM_A2065_2 ZORRO_ID(COMMODORE_WEST_CHESTER_1, 0x70, 0) + +#define ZORRO_MANUF_COMMODORE_WEST_CHESTER_2 0x0203 +#define ZORRO_PROD_CBM_A2090A_CM ZORRO_ID(COMMODORE_WEST_CHESTER_2, 0x03, 0) + +#define ZORRO_MANUF_PROGRESSIVE_PERIPHERALS_AND_SYSTEMS_2 0x02F4 +#define ZORRO_PROD_PPS_EXP8000 ZORRO_ID(PROGRESSIVE_PERIPHERALS_AND_SYSTEMS_2, 0x02, 0) + +#define ZORRO_MANUF_KOLFF_COMPUTER_SUPPLIES 0x02FF +#define ZORRO_PROD_KCS_POWER_PC_BOARD ZORRO_ID(KOLFF_COMPUTER_SUPPLIES, 0x00, 0) + +#define ZORRO_MANUF_CARDCO_1 0x03EC +#define ZORRO_PROD_CARDCO_KRONOS_2000_1 ZORRO_ID(CARDCO_1, 0x04, 0) +#define ZORRO_PROD_CARDCO_A1000_1 ZORRO_ID(CARDCO_1, 0x0C, 0) +#define ZORRO_PROD_CARDCO_ESCORT ZORRO_ID(CARDCO_1, 0x0E, 0) +#define ZORRO_PROD_CARDCO_A2410 ZORRO_ID(CARDCO_1, 0xF5, 0) + +#define ZORRO_MANUF_A_SQUARED 0x03ED +#define ZORRO_PROD_A_SQUARED_LIVE_2000 ZORRO_ID(A_SQUARED, 0x01, 0) + +#define ZORRO_MANUF_COMSPEC_COMMUNICATIONS 0x03EE +#define ZORRO_PROD_COMSPEC_COMMUNICATIONS_AX2000 ZORRO_ID(COMSPEC_COMMUNICATIONS, 0x01, 0) + +#define ZORRO_MANUF_ANAKIN_RESEARCH 0x03F1 +#define ZORRO_PROD_ANAKIN_RESEARCH_EASYL ZORRO_ID(ANAKIN_RESEARCH, 0x01, 0) + +#define ZORRO_MANUF_MICROBOTICS 0x03F2 +#define ZORRO_PROD_MICROBOTICS_STARBOARD_II ZORRO_ID(MICROBOTICS, 0x00, 0) +#define ZORRO_PROD_MICROBOTICS_STARDRIVE ZORRO_ID(MICROBOTICS, 0x02, 0) +#define ZORRO_PROD_MICROBOTICS_8_UP_A ZORRO_ID(MICROBOTICS, 0x03, 0) +#define ZORRO_PROD_MICROBOTICS_8_UP_Z ZORRO_ID(MICROBOTICS, 0x04, 0) +#define ZORRO_PROD_MICROBOTICS_DELTA_RAM ZORRO_ID(MICROBOTICS, 0x20, 0) +#define ZORRO_PROD_MICROBOTICS_8_STAR_RAM ZORRO_ID(MICROBOTICS, 0x40, 0) +#define ZORRO_PROD_MICROBOTICS_8_STAR ZORRO_ID(MICROBOTICS, 0x41, 0) +#define ZORRO_PROD_MICROBOTICS_VXL_RAM_32 ZORRO_ID(MICROBOTICS, 0x44, 0) +#define ZORRO_PROD_MICROBOTICS_VXL_68030 ZORRO_ID(MICROBOTICS, 0x45, 0) +#define ZORRO_PROD_MICROBOTICS_DELTA ZORRO_ID(MICROBOTICS, 0x60, 0) +#define ZORRO_PROD_MICROBOTICS_MBX_1200_1200Z_RAM ZORRO_ID(MICROBOTICS, 0x81, 0) +#define ZORRO_PROD_MICROBOTICS_HARDFRAME_2000_1 ZORRO_ID(MICROBOTICS, 0x96, 0) +#define ZORRO_PROD_MICROBOTICS_HARDFRAME_2000_2 ZORRO_ID(MICROBOTICS, 0x9E, 0) +#define ZORRO_PROD_MICROBOTICS_MBX_1200_1200Z ZORRO_ID(MICROBOTICS, 0xC1, 0) + +#define ZORRO_MANUF_ACCESS_ASSOCIATES_ALEGRA 0x03F4 + +#define ZORRO_MANUF_EXPANSION_TECHNOLOGIES 0x03F6 + +#define ZORRO_MANUF_ASDG 0x03FF +#define ZORRO_PROD_ASDG_MEMORY_1 ZORRO_ID(ASDG, 0x01, 0) +#define ZORRO_PROD_ASDG_MEMORY_2 ZORRO_ID(ASDG, 0x02, 0) +#define ZORRO_PROD_ASDG_EB920_LAN_ROVER ZORRO_ID(ASDG, 0xFE, 0) +#define ZORRO_PROD_ASDG_GPIB_DUALIEEE488_TWIN_X ZORRO_ID(ASDG, 0xFF, 0) + +#define ZORRO_MANUF_IMTRONICS_1 0x0404 +#define ZORRO_PROD_IMTRONICS_HURRICANE_2800_1 ZORRO_ID(IMTRONICS_1, 0x39, 0) +#define ZORRO_PROD_IMTRONICS_HURRICANE_2800_2 ZORRO_ID(IMTRONICS_1, 0x57, 0) + +#define ZORRO_MANUF_CBM_UNIVERSITY_OF_LOWELL 0x0406 +#define ZORRO_PROD_CBM_A2410 ZORRO_ID(CBM_UNIVERSITY_OF_LOWELL, 0x00, 0) + +#define ZORRO_MANUF_AMERISTAR 0x041D +#define ZORRO_PROD_AMERISTAR_A2065 ZORRO_ID(AMERISTAR, 0x01, 0) +#define ZORRO_PROD_AMERISTAR_A560 ZORRO_ID(AMERISTAR, 0x09, 0) +#define ZORRO_PROD_AMERISTAR_A4066 ZORRO_ID(AMERISTAR, 0x0A, 0) + +#define ZORRO_MANUF_SUPRA 0x0420 +#define ZORRO_PROD_SUPRA_SUPRADRIVE_4x4 ZORRO_ID(SUPRA, 0x01, 0) +#define ZORRO_PROD_SUPRA_1000_RAM ZORRO_ID(SUPRA, 0x02, 0) +#define ZORRO_PROD_SUPRA_2000_DMA ZORRO_ID(SUPRA, 0x03, 0) +#define ZORRO_PROD_SUPRA_500 ZORRO_ID(SUPRA, 0x05, 0) +#define ZORRO_PROD_SUPRA_500_SCSI ZORRO_ID(SUPRA, 0x08, 0) +#define ZORRO_PROD_SUPRA_500XP_2000_RAM ZORRO_ID(SUPRA, 0x09, 0) +#define ZORRO_PROD_SUPRA_500RX_2000_RAM ZORRO_ID(SUPRA, 0x0A, 0) +#define ZORRO_PROD_SUPRA_2400ZI ZORRO_ID(SUPRA, 0x0B, 0) +#define ZORRO_PROD_SUPRA_500XP_SUPRADRIVE_WORDSYNC ZORRO_ID(SUPRA, 0x0C, 0) +#define ZORRO_PROD_SUPRA_SUPRADRIVE_WORDSYNC_II ZORRO_ID(SUPRA, 0x0D, 0) +#define ZORRO_PROD_SUPRA_2400ZIPLUS ZORRO_ID(SUPRA, 0x10, 0) + +#define ZORRO_MANUF_COMPUTER_SYSTEMS_ASSOCIATES 0x0422 +#define ZORRO_PROD_CSA_MAGNUM ZORRO_ID(COMPUTER_SYSTEMS_ASSOCIATES, 0x11, 0) +#define ZORRO_PROD_CSA_12_GAUGE ZORRO_ID(COMPUTER_SYSTEMS_ASSOCIATES, 0x15, 0) + +#define ZORRO_MANUF_MARC_MICHAEL_GROTH 0x0439 + +#define ZORRO_MANUF_M_TECH 0x0502 +#define ZORRO_PROD_MTEC_AT500_1 ZORRO_ID(M_TECH, 0x03, 0) + +#define ZORRO_MANUF_GREAT_VALLEY_PRODUCTS_1 0x06E1 +#define ZORRO_PROD_GVP_IMPACT_SERIES_I ZORRO_ID(GREAT_VALLEY_PRODUCTS_1, 0x08, 0) + +#define ZORRO_MANUF_BYTEBOX 0x07DA +#define ZORRO_PROD_BYTEBOX_A500 ZORRO_ID(BYTEBOX, 0x00, 0) + +#define ZORRO_MANUF_DKB_POWER_COMPUTING 0x07DC +#define ZORRO_PROD_DKB_POWER_COMPUTING_SECUREKEY ZORRO_ID(DKB_POWER_COMPUTING, 0x09, 0) +#define ZORRO_PROD_DKB_POWER_COMPUTING_DKM_3128 ZORRO_ID(DKB_POWER_COMPUTING, 0x0E, 0) +#define ZORRO_PROD_DKB_POWER_COMPUTING_RAPID_FIRE ZORRO_ID(DKB_POWER_COMPUTING, 0x0F, 0) +#define ZORRO_PROD_DKB_POWER_COMPUTING_DKM_1202 ZORRO_ID(DKB_POWER_COMPUTING, 0x10, 0) +#define ZORRO_PROD_DKB_POWER_COMPUTING_COBRA_VIPER_II_68EC030 ZORRO_ID(DKB_POWER_COMPUTING, 0x12, 0) +#define ZORRO_PROD_DKB_POWER_COMPUTING_WILDFIRE_060_1 ZORRO_ID(DKB_POWER_COMPUTING, 0x17, 0) +#define ZORRO_PROD_DKB_POWER_COMPUTING_WILDFIRE_060_2 ZORRO_ID(DKB_POWER_COMPUTING, 0xFF, 0) + +#define ZORRO_MANUF_GREAT_VALLEY_PRODUCTS_2 0x07E1 +#define ZORRO_PROD_GVP_IMPACT_SERIES_I_4K ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x01, 0) +#define ZORRO_PROD_GVP_IMPACT_SERIES_I_16K_2 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x02, 0) +#define ZORRO_PROD_GVP_IMPACT_SERIES_I_16K_3 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x03, 0) +#define ZORRO_PROD_GVP_IMPACT_3001_IDE_1 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x08, 0) +#define ZORRO_PROD_GVP_IMPACT_3001_RAM ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x09, 0) +#define ZORRO_PROD_GVP_IMPACT_SERIES_II_RAM_1 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0A, 0) +#define ZORRO_PROD_GVP_EPC_BASE ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0) +#define ZORRO_PROD_GVP_GFORCE_040_1 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0x20) +#define ZORRO_PROD_GVP_GFORCE_040_SCSI_1 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0x30) +#define ZORRO_PROD_GVP_A1291 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0x40) +#define ZORRO_PROD_GVP_COMBO_030_R4 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0x60) +#define ZORRO_PROD_GVP_COMBO_030_R4_SCSI ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0x70) +#define ZORRO_PROD_GVP_PHONEPAK ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0x78) +#define ZORRO_PROD_GVP_IO_EXTENDER ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0x98) +#define ZORRO_PROD_GVP_GFORCE_030 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0xa0) +#define ZORRO_PROD_GVP_GFORCE_030_SCSI ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0xb0) +#define ZORRO_PROD_GVP_A530 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0xc0) +#define ZORRO_PROD_GVP_A530_SCSI ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0xd0) +#define ZORRO_PROD_GVP_COMBO_030_R3 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0xe0) +#define ZORRO_PROD_GVP_COMBO_030_R3_SCSI ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0xf0) +#define ZORRO_PROD_GVP_SERIES_II ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0B, 0xf8) +#define ZORRO_PROD_GVP_IMPACT_3001_IDE_2 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0D, 0) +/*#define ZORRO_PROD_GVP_A2000_030 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0D, 0)*/ +/*#define ZORRO_PROD_GVP_GFORCE_040_SCSI_2 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x0D, 0)*/ +#define ZORRO_PROD_GVP_GFORCE_040_060 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x16, 0) +#define ZORRO_PROD_GVP_IMPACT_VISION_24 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0x20, 0) +#define ZORRO_PROD_GVP_GFORCE_040_2 ZORRO_ID(GREAT_VALLEY_PRODUCTS_2, 0xFF, 0) + +#define ZORRO_MANUF_CALIFORNIA_ACCESS_SYNERGY 0x07E5 +#define ZORRO_PROD_CALIFORNIA_ACCESS_SYNERGY_MALIBU ZORRO_ID(CALIFORNIA_ACCESS_SYNERGY, 0x01, 0) + +#define ZORRO_MANUF_XETEC 0x07E6 +#define ZORRO_PROD_XETEC_FASTCARD ZORRO_ID(XETEC, 0x01, 0) +#define ZORRO_PROD_XETEC_FASTCARD_RAM ZORRO_ID(XETEC, 0x02, 0) +#define ZORRO_PROD_XETEC_FASTCARD_PLUS ZORRO_ID(XETEC, 0x03, 0) + +#define ZORRO_MANUF_PROGRESSIVE_PERIPHERALS_AND_SYSTEMS 0x07EA +#define ZORRO_PROD_PPS_MERCURY ZORRO_ID(PROGRESSIVE_PERIPHERALS_AND_SYSTEMS, 0x00, 0) +#define ZORRO_PROD_PPS_A3000_68040 ZORRO_ID(PROGRESSIVE_PERIPHERALS_AND_SYSTEMS, 0x01, 0) +#define ZORRO_PROD_PPS_A2000_68040 ZORRO_ID(PROGRESSIVE_PERIPHERALS_AND_SYSTEMS, 0x69, 0) +#define ZORRO_PROD_PPS_ZEUS ZORRO_ID(PROGRESSIVE_PERIPHERALS_AND_SYSTEMS, 0x96, 0) +#define ZORRO_PROD_PPS_A500_68040 ZORRO_ID(PROGRESSIVE_PERIPHERALS_AND_SYSTEMS, 0xBB, 0) + +#define ZORRO_MANUF_XEBEC 0x07EC + +#define ZORRO_MANUF_SPIRIT_TECHNOLOGY 0x07F2 +#define ZORRO_PROD_SPIRIT_TECHNOLOGY_INSIDER_IN1000 ZORRO_ID(SPIRIT_TECHNOLOGY, 0x01, 0) +#define ZORRO_PROD_SPIRIT_TECHNOLOGY_INSIDER_IN500 ZORRO_ID(SPIRIT_TECHNOLOGY, 0x02, 0) +#define ZORRO_PROD_SPIRIT_TECHNOLOGY_SIN500 ZORRO_ID(SPIRIT_TECHNOLOGY, 0x03, 0) +#define ZORRO_PROD_SPIRIT_TECHNOLOGY_HDA_506 ZORRO_ID(SPIRIT_TECHNOLOGY, 0x04, 0) +#define ZORRO_PROD_SPIRIT_TECHNOLOGY_AX_S ZORRO_ID(SPIRIT_TECHNOLOGY, 0x05, 0) +#define ZORRO_PROD_SPIRIT_TECHNOLOGY_OCTABYTE ZORRO_ID(SPIRIT_TECHNOLOGY, 0x06, 0) +#define ZORRO_PROD_SPIRIT_TECHNOLOGY_INMATE ZORRO_ID(SPIRIT_TECHNOLOGY, 0x08, 0) + +#define ZORRO_MANUF_SPIRIT_TECHNOLOGY_2 0x07F3 + +#define ZORRO_MANUF_BSC_ALFADATA_1 0x07FE +#define ZORRO_PROD_BSC_ALF_3_1 ZORRO_ID(BSC_ALFADATA_1, 0x03, 0) + +#define ZORRO_MANUF_BSC_ALFADATA_2 0x0801 +#define ZORRO_PROD_BSC_ALF_2_1 ZORRO_ID(BSC_ALFADATA_2, 0x01, 0) +#define ZORRO_PROD_BSC_ALF_2_2 ZORRO_ID(BSC_ALFADATA_2, 0x02, 0) +#define ZORRO_PROD_BSC_ALF_3_2 ZORRO_ID(BSC_ALFADATA_2, 0x03, 0) + +#define ZORRO_MANUF_CARDCO_2 0x0802 +#define ZORRO_PROD_CARDCO_KRONOS_2000_2 ZORRO_ID(CARDCO_2, 0x04, 0) +#define ZORRO_PROD_CARDCO_A1000_2 ZORRO_ID(CARDCO_2, 0x0C, 0) + +#define ZORRO_MANUF_JOCHHEIM 0x0804 +#define ZORRO_PROD_JOCHHEIM_RAM ZORRO_ID(JOCHHEIM, 0x01, 0) + +#define ZORRO_MANUF_CHECKPOINT_TECHNOLOGIES 0x0807 +#define ZORRO_PROD_CHECKPOINT_TECHNOLOGIES_SERIAL_SOLUTION ZORRO_ID(CHECKPOINT_TECHNOLOGIES, 0x00, 0) + +#define ZORRO_MANUF_EDOTRONIK 0x0810 +#define ZORRO_PROD_EDOTRONIK_IEEE_488 ZORRO_ID(EDOTRONIK, 0x01, 0) +#define ZORRO_PROD_EDOTRONIK_8032 ZORRO_ID(EDOTRONIK, 0x02, 0) +#define ZORRO_PROD_EDOTRONIK_MULTISERIAL ZORRO_ID(EDOTRONIK, 0x03, 0) +#define ZORRO_PROD_EDOTRONIK_VIDEODIGITIZER ZORRO_ID(EDOTRONIK, 0x04, 0) +#define ZORRO_PROD_EDOTRONIK_PARALLEL_IO ZORRO_ID(EDOTRONIK, 0x05, 0) +#define ZORRO_PROD_EDOTRONIK_PIC_PROTOYPING ZORRO_ID(EDOTRONIK, 0x06, 0) +#define ZORRO_PROD_EDOTRONIK_ADC ZORRO_ID(EDOTRONIK, 0x07, 0) +#define ZORRO_PROD_EDOTRONIK_VME ZORRO_ID(EDOTRONIK, 0x08, 0) +#define ZORRO_PROD_EDOTRONIK_DSP96000 ZORRO_ID(EDOTRONIK, 0x09, 0) + +#define ZORRO_MANUF_NES_INC 0x0813 +#define ZORRO_PROD_NES_INC_RAM ZORRO_ID(NES_INC, 0x00, 0) + +#define ZORRO_MANUF_ICD 0x0817 +#define ZORRO_PROD_ICD_ADVANTAGE_2000_SCSI ZORRO_ID(ICD, 0x01, 0) +#define ZORRO_PROD_ICD_ADVANTAGE_IDE ZORRO_ID(ICD, 0x03, 0) +#define ZORRO_PROD_ICD_ADVANTAGE_2080_RAM ZORRO_ID(ICD, 0x04, 0) + +#define ZORRO_MANUF_KUPKE_2 0x0819 +#define ZORRO_PROD_KUPKE_OMTI ZORRO_ID(KUPKE_2, 0x01, 0) +#define ZORRO_PROD_KUPKE_SCSI_II ZORRO_ID(KUPKE_2, 0x02, 0) +#define ZORRO_PROD_KUPKE_GOLEM_BOX ZORRO_ID(KUPKE_2, 0x03, 0) +#define ZORRO_PROD_KUPKE_030_882 ZORRO_ID(KUPKE_2, 0x04, 0) +#define ZORRO_PROD_KUPKE_SCSI_AT ZORRO_ID(KUPKE_2, 0x05, 0) + +#define ZORRO_MANUF_GREAT_VALLEY_PRODUCTS_3 0x081D +#define ZORRO_PROD_GVP_A2000_RAM8 ZORRO_ID(GREAT_VALLEY_PRODUCTS_3, 0x09, 0) +#define ZORRO_PROD_GVP_IMPACT_SERIES_II_RAM_2 ZORRO_ID(GREAT_VALLEY_PRODUCTS_3, 0x0A, 0) + +#define ZORRO_MANUF_INTERWORKS_NETWORK 0x081E + +#define ZORRO_MANUF_HARDITAL_SYNTHESIS 0x0820 +#define ZORRO_PROD_HARDITAL_SYNTHESIS_TQM_68030_68882 ZORRO_ID(HARDITAL_SYNTHESIS, 0x14, 0) + +#define ZORRO_MANUF_APPLIED_ENGINEERING 0x0828 +#define ZORRO_PROD_APPLIED_ENGINEERING_DL2000 ZORRO_ID(APPLIED_ENGINEERING, 0x10, 0) +#define ZORRO_PROD_APPLIED_ENGINEERING_RAM_WORKS ZORRO_ID(APPLIED_ENGINEERING, 0xE0, 0) + +#define ZORRO_MANUF_BSC_ALFADATA_3 0x082C +#define ZORRO_PROD_BSC_OKTAGON_2008 ZORRO_ID(BSC_ALFADATA_3, 0x05, 0) +#define ZORRO_PROD_BSC_TANDEM_AT_2008_508 ZORRO_ID(BSC_ALFADATA_3, 0x06, 0) +#define ZORRO_PROD_BSC_ALFA_RAM_1200 ZORRO_ID(BSC_ALFADATA_3, 0x07, 0) +#define ZORRO_PROD_BSC_OKTAGON_2008_RAM ZORRO_ID(BSC_ALFADATA_3, 0x08, 0) +#define ZORRO_PROD_BSC_MULTIFACE_I ZORRO_ID(BSC_ALFADATA_3, 0x10, 0) +#define ZORRO_PROD_BSC_MULTIFACE_II ZORRO_ID(BSC_ALFADATA_3, 0x11, 0) +#define ZORRO_PROD_BSC_MULTIFACE_III ZORRO_ID(BSC_ALFADATA_3, 0x12, 0) +#define ZORRO_PROD_BSC_FRAMEMASTER_II ZORRO_ID(BSC_ALFADATA_3, 0x20, 0) +#define ZORRO_PROD_BSC_GRAFFITI_RAM ZORRO_ID(BSC_ALFADATA_3, 0x21, 0) +#define ZORRO_PROD_BSC_GRAFFITI_REG ZORRO_ID(BSC_ALFADATA_3, 0x22, 0) +#define ZORRO_PROD_BSC_ISDN_MASTERCARD ZORRO_ID(BSC_ALFADATA_3, 0x40, 0) +#define ZORRO_PROD_BSC_ISDN_MASTERCARD_II ZORRO_ID(BSC_ALFADATA_3, 0x41, 0) + +#define ZORRO_MANUF_PHOENIX 0x0835 +#define ZORRO_PROD_PHOENIX_ST506 ZORRO_ID(PHOENIX, 0x21, 0) +#define ZORRO_PROD_PHOENIX_SCSI ZORRO_ID(PHOENIX, 0x22, 0) +#define ZORRO_PROD_PHOENIX_RAM ZORRO_ID(PHOENIX, 0xBE, 0) + +#define ZORRO_MANUF_ADVANCED_STORAGE_SYSTEMS 0x0836 +#define ZORRO_PROD_ADVANCED_STORAGE_SYSTEMS_NEXUS ZORRO_ID(ADVANCED_STORAGE_SYSTEMS, 0x01, 0) +#define ZORRO_PROD_ADVANCED_STORAGE_SYSTEMS_NEXUS_RAM ZORRO_ID(ADVANCED_STORAGE_SYSTEMS, 0x08, 0) + +#define ZORRO_MANUF_IMPULSE 0x0838 +#define ZORRO_PROD_IMPULSE_FIRECRACKER_24 ZORRO_ID(IMPULSE, 0x00, 0) + +#define ZORRO_MANUF_IVS 0x0840 +#define ZORRO_PROD_IVS_GRANDSLAM_PIC_2 ZORRO_ID(IVS, 0x02, 0) +#define ZORRO_PROD_IVS_GRANDSLAM_PIC_1 ZORRO_ID(IVS, 0x04, 0) +#define ZORRO_PROD_IVS_OVERDRIVE ZORRO_ID(IVS, 0x10, 0) +#define ZORRO_PROD_IVS_TRUMPCARD_CLASSIC ZORRO_ID(IVS, 0x30, 0) +#define ZORRO_PROD_IVS_TRUMPCARD_PRO_GRANDSLAM ZORRO_ID(IVS, 0x34, 0) +#define ZORRO_PROD_IVS_META_4 ZORRO_ID(IVS, 0x40, 0) +#define ZORRO_PROD_IVS_WAVETOOLS ZORRO_ID(IVS, 0xBF, 0) +#define ZORRO_PROD_IVS_VECTOR_1 ZORRO_ID(IVS, 0xF3, 0) +#define ZORRO_PROD_IVS_VECTOR_2 ZORRO_ID(IVS, 0xF4, 0) + +#define ZORRO_MANUF_VECTOR_1 0x0841 +#define ZORRO_PROD_VECTOR_CONNECTION_1 ZORRO_ID(VECTOR_1, 0xE3, 0) + +#define ZORRO_MANUF_XPERT_PRODEV 0x0845 +#define ZORRO_PROD_XPERT_PRODEV_VISIONA_RAM ZORRO_ID(XPERT_PRODEV, 0x01, 0) +#define ZORRO_PROD_XPERT_PRODEV_VISIONA_REG ZORRO_ID(XPERT_PRODEV, 0x02, 0) +#define ZORRO_PROD_XPERT_PRODEV_MERLIN_RAM ZORRO_ID(XPERT_PRODEV, 0x03, 0) +#define ZORRO_PROD_XPERT_PRODEV_MERLIN_REG_1 ZORRO_ID(XPERT_PRODEV, 0x04, 0) +#define ZORRO_PROD_XPERT_PRODEV_MERLIN_REG_2 ZORRO_ID(XPERT_PRODEV, 0xC9, 0) + +#define ZORRO_MANUF_HYDRA_SYSTEMS 0x0849 +#define ZORRO_PROD_HYDRA_SYSTEMS_AMIGANET ZORRO_ID(HYDRA_SYSTEMS, 0x01, 0) + +#define ZORRO_MANUF_SUNRIZE_INDUSTRIES 0x084F +#define ZORRO_PROD_SUNRIZE_INDUSTRIES_AD1012 ZORRO_ID(SUNRIZE_INDUSTRIES, 0x01, 0) +#define ZORRO_PROD_SUNRIZE_INDUSTRIES_AD516 ZORRO_ID(SUNRIZE_INDUSTRIES, 0x02, 0) +#define ZORRO_PROD_SUNRIZE_INDUSTRIES_DD512 ZORRO_ID(SUNRIZE_INDUSTRIES, 0x03, 0) + +#define ZORRO_MANUF_TRICERATOPS 0x0850 +#define ZORRO_PROD_TRICERATOPS_MULTI_IO ZORRO_ID(TRICERATOPS, 0x01, 0) + +#define ZORRO_MANUF_APPLIED_MAGIC 0x0851 +#define ZORRO_PROD_APPLIED_MAGIC_DMI_RESOLVER ZORRO_ID(APPLIED_MAGIC, 0x01, 0) +#define ZORRO_PROD_APPLIED_MAGIC_DIGITAL_BROADCASTER ZORRO_ID(APPLIED_MAGIC, 0x06, 0) + +#define ZORRO_MANUF_GFX_BASE 0x085E +#define ZORRO_PROD_GFX_BASE_GDA_1_VRAM ZORRO_ID(GFX_BASE, 0x00, 0) +#define ZORRO_PROD_GFX_BASE_GDA_1 ZORRO_ID(GFX_BASE, 0x01, 0) + +#define ZORRO_MANUF_ROCTEC 0x0860 +#define ZORRO_PROD_ROCTEC_RH_800C ZORRO_ID(ROCTEC, 0x01, 0) +#define ZORRO_PROD_ROCTEC_RH_800C_RAM ZORRO_ID(ROCTEC, 0x01, 0) + +#define ZORRO_MANUF_KATO 0x0861 +#define ZORRO_PROD_KATO_MELODY ZORRO_ID(KATO, 0x80, 0) +/* ID clash!! */ +#define ZORRO_MANUF_HELFRICH_1 0x0861 +#define ZORRO_PROD_HELFRICH_RAINBOW_II ZORRO_ID(HELFRICH_1, 0x20, 0) +#define ZORRO_PROD_HELFRICH_RAINBOW_III ZORRO_ID(HELFRICH_1, 0x21, 0) + +#define ZORRO_MANUF_ATLANTIS 0x0862 + +#define ZORRO_MANUF_PROTAR 0x0864 + +#define ZORRO_MANUF_ACS 0x0865 + +#define ZORRO_MANUF_SOFTWARE_RESULTS_ENTERPRISES 0x0866 +#define ZORRO_PROD_SOFTWARE_RESULTS_ENTERPRISES_GOLDEN_GATE_2_BUS_PLUS ZORRO_ID(SOFTWARE_RESULTS_ENTERPRISES, 0x01, 0) + +#define ZORRO_MANUF_MASOBOSHI 0x086D +#define ZORRO_PROD_MASOBOSHI_MASTER_CARD_SC201 ZORRO_ID(MASOBOSHI, 0x03, 0) +#define ZORRO_PROD_MASOBOSHI_MASTER_CARD_MC702 ZORRO_ID(MASOBOSHI, 0x04, 0) +#define ZORRO_PROD_MASOBOSHI_MVD_819 ZORRO_ID(MASOBOSHI, 0x07, 0) + +#define ZORRO_MANUF_MAINHATTAN_DATA 0x086F +#define ZORRO_PROD_MAINHATTAN_DATA_IDE ZORRO_ID(MAINHATTAN_DATA, 0x01, 0) + +#define ZORRO_MANUF_VILLAGE_TRONIC 0x0877 +#define ZORRO_PROD_VILLAGE_TRONIC_DOMINO_RAM ZORRO_ID(VILLAGE_TRONIC, 0x01, 0) +#define ZORRO_PROD_VILLAGE_TRONIC_DOMINO_REG ZORRO_ID(VILLAGE_TRONIC, 0x02, 0) +#define ZORRO_PROD_VILLAGE_TRONIC_DOMINO_16M_PROTOTYPE ZORRO_ID(VILLAGE_TRONIC, 0x03, 0) +#define ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM ZORRO_ID(VILLAGE_TRONIC, 0x0B, 0) +#define ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_REG ZORRO_ID(VILLAGE_TRONIC, 0x0C, 0) +#define ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_SEGMENTED_MODE ZORRO_ID(VILLAGE_TRONIC, 0x0D, 0) +#define ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_RAM1 ZORRO_ID(VILLAGE_TRONIC, 0x15, 0) +#define ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_RAM2 ZORRO_ID(VILLAGE_TRONIC, 0x16, 0) +#define ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_REG ZORRO_ID(VILLAGE_TRONIC, 0x17, 0) +#define ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z3 ZORRO_ID(VILLAGE_TRONIC, 0x18, 0) +#define ZORRO_PROD_VILLAGE_TRONIC_ARIADNE ZORRO_ID(VILLAGE_TRONIC, 0xC9, 0) +#define ZORRO_PROD_VILLAGE_TRONIC_ARIADNE2 ZORRO_ID(VILLAGE_TRONIC, 0xCA, 0) + +#define ZORRO_MANUF_UTILITIES_UNLIMITED 0x087B +#define ZORRO_PROD_UTILITIES_UNLIMITED_EMPLANT_DELUXE ZORRO_ID(UTILITIES_UNLIMITED, 0x15, 0) +#define ZORRO_PROD_UTILITIES_UNLIMITED_EMPLANT_DELUXE2 ZORRO_ID(UTILITIES_UNLIMITED, 0x20, 0) + +#define ZORRO_MANUF_AMITRIX 0x0880 +#define ZORRO_PROD_AMITRIX_MULTI_IO ZORRO_ID(AMITRIX, 0x01, 0) +#define ZORRO_PROD_AMITRIX_CD_RAM ZORRO_ID(AMITRIX, 0x02, 0) + +#define ZORRO_MANUF_ARMAX 0x0885 +#define ZORRO_PROD_ARMAX_OMNIBUS ZORRO_ID(ARMAX, 0x00, 0) + +#define ZORRO_MANUF_ZEUS 0x088D +#define ZORRO_PROD_ZEUS_SPIDER ZORRO_ID(ZEUS, 0x04, 0) + +#define ZORRO_MANUF_NEWTEK 0x088F +#define ZORRO_PROD_NEWTEK_VIDEOTOASTER ZORRO_ID(NEWTEK, 0x00, 0) + +#define ZORRO_MANUF_M_TECH_GERMANY 0x0890 +#define ZORRO_PROD_MTEC_AT500_2 ZORRO_ID(M_TECH_GERMANY, 0x01, 0) +#define ZORRO_PROD_MTEC_68030 ZORRO_ID(M_TECH_GERMANY, 0x03, 0) +#define ZORRO_PROD_MTEC_68020I ZORRO_ID(M_TECH_GERMANY, 0x06, 0) +#define ZORRO_PROD_MTEC_A1200_T68030_RTC ZORRO_ID(M_TECH_GERMANY, 0x20, 0) +#define ZORRO_PROD_MTEC_VIPER_MK_V_E_MATRIX_530 ZORRO_ID(M_TECH_GERMANY, 0x21, 0) +#define ZORRO_PROD_MTEC_8_MB_RAM ZORRO_ID(M_TECH_GERMANY, 0x22, 0) +#define ZORRO_PROD_MTEC_VIPER_MK_V_E_MATRIX_530_SCSI_IDE ZORRO_ID(M_TECH_GERMANY, 0x24, 0) + +#define ZORRO_MANUF_GREAT_VALLEY_PRODUCTS_4 0x0891 +#define ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM ZORRO_ID(GREAT_VALLEY_PRODUCTS_4, 0x01, 0) +#define ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_REG ZORRO_ID(GREAT_VALLEY_PRODUCTS_4, 0x02, 0) + +#define ZORRO_MANUF_APOLLO_1 0x0892 +#define ZORRO_PROD_APOLLO_A1200 ZORRO_ID(APOLLO_1, 0x01, 0) + +#define ZORRO_MANUF_HELFRICH_2 0x0893 +#define ZORRO_PROD_HELFRICH_PICCOLO_RAM ZORRO_ID(HELFRICH_2, 0x05, 0) +#define ZORRO_PROD_HELFRICH_PICCOLO_REG ZORRO_ID(HELFRICH_2, 0x06, 0) +#define ZORRO_PROD_HELFRICH_PEGGY_PLUS_MPEG ZORRO_ID(HELFRICH_2, 0x07, 0) +#define ZORRO_PROD_HELFRICH_VIDEOCRUNCHER ZORRO_ID(HELFRICH_2, 0x08, 0) +#define ZORRO_PROD_HELFRICH_SD64_RAM ZORRO_ID(HELFRICH_2, 0x0A, 0) +#define ZORRO_PROD_HELFRICH_SD64_REG ZORRO_ID(HELFRICH_2, 0x0B, 0) + +#define ZORRO_MANUF_MACROSYSTEMS_USA 0x089B +#define ZORRO_PROD_MACROSYSTEMS_WARP_ENGINE_40xx ZORRO_ID(MACROSYSTEMS_USA, 0x13, 0) + +#define ZORRO_MANUF_ELBOX_COMPUTER 0x089E +#define ZORRO_PROD_ELBOX_COMPUTER_1200_4 ZORRO_ID(ELBOX_COMPUTER, 0x06, 0) + +#define ZORRO_MANUF_HARMS_PROFESSIONAL 0x0A00 +#define ZORRO_PROD_HARMS_PROFESSIONAL_030_PLUS ZORRO_ID(HARMS_PROFESSIONAL, 0x10, 0) +#define ZORRO_PROD_HARMS_PROFESSIONAL_3500 ZORRO_ID(HARMS_PROFESSIONAL, 0xD0, 0) + +#define ZORRO_MANUF_MICRONIK 0x0A50 +#define ZORRO_PROD_MICRONIK_RCA_120 ZORRO_ID(MICRONIK, 0x0A, 0) + +#define ZORRO_MANUF_MICRONIK2 0x0F0F +#define ZORRO_PROD_MICRONIK2_Z3I ZORRO_ID(MICRONIK2, 0x01, 0) + +#define ZORRO_MANUF_MEGAMICRO 0x1000 +#define ZORRO_PROD_MEGAMICRO_SCRAM_500 ZORRO_ID(MEGAMICRO, 0x03, 0) +#define ZORRO_PROD_MEGAMICRO_SCRAM_500_RAM ZORRO_ID(MEGAMICRO, 0x04, 0) + +#define ZORRO_MANUF_IMTRONICS_2 0x1028 +#define ZORRO_PROD_IMTRONICS_HURRICANE_2800_3 ZORRO_ID(IMTRONICS_2, 0x39, 0) +#define ZORRO_PROD_IMTRONICS_HURRICANE_2800_4 ZORRO_ID(IMTRONICS_2, 0x57, 0) + +/* unofficial ID */ +#define ZORRO_MANUF_INDIVIDUAL_COMPUTERS 0x1212 +#define ZORRO_PROD_INDIVIDUAL_COMPUTERS_BUDDHA ZORRO_ID(INDIVIDUAL_COMPUTERS, 0x00, 0) +#define ZORRO_PROD_INDIVIDUAL_COMPUTERS_X_SURF ZORRO_ID(INDIVIDUAL_COMPUTERS, 0x17, 0) +#define ZORRO_PROD_INDIVIDUAL_COMPUTERS_CATWEASEL ZORRO_ID(INDIVIDUAL_COMPUTERS, 0x2A, 0) + +#define ZORRO_MANUF_KUPKE_3 0x1248 +#define ZORRO_PROD_KUPKE_GOLEM_HD_3000 ZORRO_ID(KUPKE_3, 0x01, 0) + +#define ZORRO_MANUF_ITH 0x1388 +#define ZORRO_PROD_ITH_ISDN_MASTER_II ZORRO_ID(ITH, 0x01, 0) + +#define ZORRO_MANUF_VMC 0x1389 +#define ZORRO_PROD_VMC_ISDN_BLASTER_Z2 ZORRO_ID(VMC, 0x01, 0) +#define ZORRO_PROD_VMC_HYPERCOM_4 ZORRO_ID(VMC, 0x02, 0) + +#define ZORRO_MANUF_INFORMATION 0x157C +#define ZORRO_PROD_INFORMATION_ISDN_ENGINE_I ZORRO_ID(INFORMATION, 0x64, 0) + +#define ZORRO_MANUF_VORTEX 0x2017 +#define ZORRO_PROD_VORTEX_GOLDEN_GATE_80386SX ZORRO_ID(VORTEX, 0x07, 0) +#define ZORRO_PROD_VORTEX_GOLDEN_GATE_RAM ZORRO_ID(VORTEX, 0x08, 0) +#define ZORRO_PROD_VORTEX_GOLDEN_GATE_80486 ZORRO_ID(VORTEX, 0x09, 0) + +#define ZORRO_MANUF_EXPANSION_SYSTEMS 0x2062 +#define ZORRO_PROD_EXPANSION_SYSTEMS_DATAFLYER_4000SX ZORRO_ID(EXPANSION_SYSTEMS, 0x01, 0) +#define ZORRO_PROD_EXPANSION_SYSTEMS_DATAFLYER_4000SX_RAM ZORRO_ID(EXPANSION_SYSTEMS, 0x02, 0) + +#define ZORRO_MANUF_READYSOFT 0x2100 +#define ZORRO_PROD_READYSOFT_AMAX_II_IV ZORRO_ID(READYSOFT, 0x01, 0) + +#define ZORRO_MANUF_PHASE5 0x2140 +#define ZORRO_PROD_PHASE5_BLIZZARD_RAM ZORRO_ID(PHASE5, 0x01, 0) +#define ZORRO_PROD_PHASE5_BLIZZARD ZORRO_ID(PHASE5, 0x02, 0) +#define ZORRO_PROD_PHASE5_BLIZZARD_1220_IV ZORRO_ID(PHASE5, 0x06, 0) +#define ZORRO_PROD_PHASE5_FASTLANE_Z3_RAM ZORRO_ID(PHASE5, 0x0A, 0) +#define ZORRO_PROD_PHASE5_BLIZZARD_1230_II_FASTLANE_Z3_CYBERSCSI_CYBERSTORM060 ZORRO_ID(PHASE5, 0x0B, 0) +#define ZORRO_PROD_PHASE5_BLIZZARD_1220_CYBERSTORM ZORRO_ID(PHASE5, 0x0C, 0) +#define ZORRO_PROD_PHASE5_BLIZZARD_1230 ZORRO_ID(PHASE5, 0x0D, 0) +#define ZORRO_PROD_PHASE5_BLIZZARD_1230_IV_1260 ZORRO_ID(PHASE5, 0x11, 0) +#define ZORRO_PROD_PHASE5_BLIZZARD_2060 ZORRO_ID(PHASE5, 0x18, 0) +#define ZORRO_PROD_PHASE5_CYBERSTORM_MK_II ZORRO_ID(PHASE5, 0x19, 0) +#define ZORRO_PROD_PHASE5_CYBERVISION64 ZORRO_ID(PHASE5, 0x22, 0) +#define ZORRO_PROD_PHASE5_CYBERVISION64_3D_PROTOTYPE ZORRO_ID(PHASE5, 0x32, 0) +#define ZORRO_PROD_PHASE5_CYBERVISION64_3D ZORRO_ID(PHASE5, 0x43, 0) +#define ZORRO_PROD_PHASE5_CYBERSTORM_MK_III ZORRO_ID(PHASE5, 0x64, 0) +#define ZORRO_PROD_PHASE5_BLIZZARD_603E_PLUS ZORRO_ID(PHASE5, 0x6e, 0) + +#define ZORRO_MANUF_DPS 0x2169 +#define ZORRO_PROD_DPS_PERSONAL_ANIMATION_RECORDER ZORRO_ID(DPS, 0x01, 0) + +#define ZORRO_MANUF_APOLLO_2 0x2200 +#define ZORRO_PROD_APOLLO_A620_68020_1 ZORRO_ID(APOLLO_2, 0x00, 0) +#define ZORRO_PROD_APOLLO_A620_68020_2 ZORRO_ID(APOLLO_2, 0x01, 0) + +#define ZORRO_MANUF_APOLLO_3 0x2222 +#define ZORRO_PROD_APOLLO_AT_APOLLO ZORRO_ID(APOLLO_3, 0x22, 0) +#define ZORRO_PROD_APOLLO_1230_1240_1260_2030_4040_4060 ZORRO_ID(APOLLO_3, 0x23, 0) + +#define ZORRO_MANUF_PETSOFF_LP 0x38A5 +#define ZORRO_PROD_PETSOFF_LP_DELFINA ZORRO_ID(PETSOFF_LP, 0x00, 0) +#define ZORRO_PROD_PETSOFF_LP_DELFINA_LITE ZORRO_ID(PETSOFF_LP, 0x01, 0) + +#define ZORRO_MANUF_UWE_GERLACH 0x3FF7 +#define ZORRO_PROD_UWE_GERLACH_RAM_ROM ZORRO_ID(UWE_GERLACH, 0xd4, 0) + +#define ZORRO_MANUF_ACT 0x4231 +#define ZORRO_PROD_ACT_PRELUDE ZORRO_ID(ACT, 0x01, 0) + +#define ZORRO_MANUF_MACROSYSTEMS_GERMANY 0x4754 +#define ZORRO_PROD_MACROSYSTEMS_MAESTRO ZORRO_ID(MACROSYSTEMS_GERMANY, 0x03, 0) +#define ZORRO_PROD_MACROSYSTEMS_VLAB ZORRO_ID(MACROSYSTEMS_GERMANY, 0x04, 0) +#define ZORRO_PROD_MACROSYSTEMS_MAESTRO_PRO ZORRO_ID(MACROSYSTEMS_GERMANY, 0x05, 0) +#define ZORRO_PROD_MACROSYSTEMS_RETINA ZORRO_ID(MACROSYSTEMS_GERMANY, 0x06, 0) +#define ZORRO_PROD_MACROSYSTEMS_MULTI_EVOLUTION ZORRO_ID(MACROSYSTEMS_GERMANY, 0x08, 0) +#define ZORRO_PROD_MACROSYSTEMS_TOCCATA ZORRO_ID(MACROSYSTEMS_GERMANY, 0x0C, 0) +#define ZORRO_PROD_MACROSYSTEMS_RETINA_Z3 ZORRO_ID(MACROSYSTEMS_GERMANY, 0x10, 0) +#define ZORRO_PROD_MACROSYSTEMS_VLAB_MOTION ZORRO_ID(MACROSYSTEMS_GERMANY, 0x12, 0) +#define ZORRO_PROD_MACROSYSTEMS_ALTAIS ZORRO_ID(MACROSYSTEMS_GERMANY, 0x13, 0) +#define ZORRO_PROD_MACROSYSTEMS_FALCON_040 ZORRO_ID(MACROSYSTEMS_GERMANY, 0xFD, 0) + +#define ZORRO_MANUF_COMBITEC 0x6766 + +#define ZORRO_MANUF_SKI_PERIPHERALS 0x8000 +#define ZORRO_PROD_SKI_PERIPHERALS_MAST_FIREBALL ZORRO_ID(SKI_PERIPHERALS, 0x08, 0) +#define ZORRO_PROD_SKI_PERIPHERALS_SCSI_DUAL_SERIAL ZORRO_ID(SKI_PERIPHERALS, 0x80, 0) + +#define ZORRO_MANUF_REIS_WARE_2 0xA9AD +#define ZORRO_PROD_REIS_WARE_SCAN_KING ZORRO_ID(REIS_WARE_2, 0x11, 0) + +#define ZORRO_MANUF_CAMERON 0xAA01 +#define ZORRO_PROD_CAMERON_PERSONAL_A4 ZORRO_ID(CAMERON, 0x10, 0) + +#define ZORRO_MANUF_REIS_WARE 0xAA11 +#define ZORRO_PROD_REIS_WARE_HANDYSCANNER ZORRO_ID(REIS_WARE, 0x11, 0) + +#define ZORRO_MANUF_PHOENIX_2 0xB5A8 +#define ZORRO_PROD_PHOENIX_ST506_2 ZORRO_ID(PHOENIX_2, 0x21, 0) +#define ZORRO_PROD_PHOENIX_SCSI_2 ZORRO_ID(PHOENIX_2, 0x22, 0) +#define ZORRO_PROD_PHOENIX_RAM_2 ZORRO_ID(PHOENIX_2, 0xBE, 0) + +#define ZORRO_MANUF_COMBITEC_2 0xC008 +#define ZORRO_PROD_COMBITEC_HD ZORRO_ID(COMBITEC_2, 0x2A, 0) +#define ZORRO_PROD_COMBITEC_SRAM ZORRO_ID(COMBITEC_2, 0x2B, 0) + + + /* + * Test and illegal Manufacturer IDs. + */ + +#define ZORRO_MANUF_HACKER 0x07DB +#define ZORRO_PROD_GENERAL_PROTOTYPE ZORRO_ID(HACKER, 0x00, 0) +#define ZORRO_PROD_HACKER_SCSI ZORRO_ID(HACKER, 0x01, 0) +#define ZORRO_PROD_RESOURCE_MANAGEMENT_FORCE_QUICKNET_QN2000 ZORRO_ID(HACKER, 0x02, 0) +#define ZORRO_PROD_VECTOR_CONNECTION_2 ZORRO_ID(HACKER, 0xE0, 0) +#define ZORRO_PROD_VECTOR_CONNECTION_3 ZORRO_ID(HACKER, 0xE1, 0) +#define ZORRO_PROD_VECTOR_CONNECTION_4 ZORRO_ID(HACKER, 0xE2, 0) +#define ZORRO_PROD_VECTOR_CONNECTION_5 ZORRO_ID(HACKER, 0xE3, 0) diff --git a/include/uapi/sound/compress_params.h b/include/uapi/sound/compress_params.h index 602dc6c45d1a..165e7059de75 100644 --- a/include/uapi/sound/compress_params.h +++ b/include/uapi/sound/compress_params.h @@ -57,6 +57,7 @@ #define MAX_NUM_CODECS 32 #define MAX_NUM_CODEC_DESCRIPTORS 32 #define MAX_NUM_BITRATES 32 +#define MAX_NUM_SAMPLE_RATES 32 /* Codecs are listed linearly to allow for extensibility */ #define SND_AUDIOCODEC_PCM ((__u32) 0x00000001) @@ -324,7 +325,8 @@ union snd_codec_options { /** struct snd_codec_desc - description of codec capabilities * @max_ch: Maximum number of audio channels - * @sample_rates: Sampling rates in Hz, use SNDRV_PCM_RATE_xxx for this + * @sample_rates: Sampling rates in Hz, use values like 48000 for this + * @num_sample_rates: Number of valid values in sample_rates array * @bit_rate: Indexed array containing supported bit rates * @num_bitrates: Number of valid values in bit_rate array * @rate_control: value is specified by SND_RATECONTROLMODE defines. @@ -346,7 +348,8 @@ union snd_codec_options { struct snd_codec_desc { __u32 max_ch; - __u32 sample_rates; + __u32 sample_rates[MAX_NUM_SAMPLE_RATES]; + __u32 num_sample_rates; __u32 bit_rate[MAX_NUM_BITRATES]; __u32 num_bitrates; __u32 rate_control; @@ -364,7 +367,8 @@ struct snd_codec_desc { * @ch_out: Number of output channels. In case of contradiction between * this field and the channelMode field, the channelMode field * overrides. - * @sample_rate: Audio sample rate of input data + * @sample_rate: Audio sample rate of input data in Hz, use values like 48000 + * for this. * @bit_rate: Bitrate of encoded data. May be ignored by decoders * @rate_control: Encoding rate control. See SND_RATECONTROLMODE defines. * Encoders may rely on profiles for quality levels. |