diff options
Diffstat (limited to 'include/asm-mips')
159 files changed, 4339 insertions, 7224 deletions
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h index 0b3ff9c48409..0bb7a93b7a5e 100644 --- a/include/asm-mips/addrspace.h +++ b/include/asm-mips/addrspace.h @@ -123,10 +123,10 @@ /* * 64-bit address conversions */ -#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p)) -#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p)) +#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p)) +#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p)) #define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) -#define PHYS_TO_XKPHYS(cm,a) (_CONST64_(0x8000000000000000) | \ +#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \ ((cm)<<59) | (a)) /* diff --git a/include/asm-mips/asm.h b/include/asm-mips/asm.h index 838eb3144d81..12e17581b823 100644 --- a/include/asm-mips/asm.h +++ b/include/asm-mips/asm.h @@ -21,11 +21,11 @@ #ifndef CAT #ifdef __STDC__ -#define __CAT(str1,str2) str1##str2 +#define __CAT(str1, str2) str1##str2 #else -#define __CAT(str1,str2) str1/**/str2 +#define __CAT(str1, str2) str1/**/str2 #endif -#define CAT(str1,str2) __CAT(str1,str2) +#define CAT(str1, str2) __CAT(str1, str2) #endif /* @@ -51,9 +51,9 @@ #define LEAF(symbol) \ .globl symbol; \ .align 2; \ - .type symbol,@function; \ - .ent symbol,0; \ -symbol: .frame sp,0,ra + .type symbol, @function; \ + .ent symbol, 0; \ +symbol: .frame sp, 0, ra /* * NESTED - declare nested routine entry point @@ -61,8 +61,8 @@ symbol: .frame sp,0,ra #define NESTED(symbol, framesize, rpc) \ .globl symbol; \ .align 2; \ - .type symbol,@function; \ - .ent symbol,0; \ + .type symbol, @function; \ + .ent symbol, 0; \ symbol: .frame sp, framesize, rpc /* @@ -70,7 +70,7 @@ symbol: .frame sp, framesize, rpc */ #define END(function) \ .end function; \ - .size function,.-function + .size function, .-function /* * EXPORT - export definition of symbol @@ -84,7 +84,7 @@ symbol: */ #define FEXPORT(symbol) \ .globl symbol; \ - .type symbol,@function; \ + .type symbol, @function; \ symbol: /* @@ -97,7 +97,7 @@ symbol = value #define PANIC(msg) \ .set push; \ .set reorder; \ - PTR_LA a0,8f; \ + PTR_LA a0, 8f; \ jal panic; \ 9: b 9b; \ .set pop; \ @@ -110,7 +110,7 @@ symbol = value #define PRINT(string) \ .set push; \ .set reorder; \ - PTR_LA a0,8f; \ + PTR_LA a0, 8f; \ jal printk; \ .set pop; \ TEXT(string) @@ -146,19 +146,19 @@ symbol = value #define PREF(hint,addr) \ .set push; \ .set mips4; \ - pref hint,addr; \ + pref hint, addr; \ .set pop #define PREFX(hint,addr) \ .set push; \ .set mips4; \ - prefx hint,addr; \ + prefx hint, addr; \ .set pop #else /* !CONFIG_CPU_HAS_PREFETCH */ -#define PREF(hint,addr) -#define PREFX(hint,addr) +#define PREF(hint, addr) +#define PREFX(hint, addr) #endif /* !CONFIG_CPU_HAS_PREFETCH */ @@ -166,43 +166,43 @@ symbol = value * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs. */ #if (_MIPS_ISA == _MIPS_ISA_MIPS1) -#define MOVN(rd,rs,rt) \ +#define MOVN(rd, rs, rt) \ .set push; \ .set reorder; \ - beqz rt,9f; \ - move rd,rs; \ + beqz rt, 9f; \ + move rd, rs; \ .set pop; \ 9: -#define MOVZ(rd,rs,rt) \ +#define MOVZ(rd, rs, rt) \ .set push; \ .set reorder; \ - bnez rt,9f; \ - move rd,rs; \ + bnez rt, 9f; \ + move rd, rs; \ .set pop; \ 9: #endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */ #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) -#define MOVN(rd,rs,rt) \ +#define MOVN(rd, rs, rt) \ .set push; \ .set noreorder; \ - bnezl rt,9f; \ - move rd,rs; \ + bnezl rt, 9f; \ + move rd, rs; \ .set pop; \ 9: -#define MOVZ(rd,rs,rt) \ +#define MOVZ(rd, rs, rt) \ .set push; \ .set noreorder; \ - beqzl rt,9f; \ - move rd,rs; \ + beqzl rt, 9f; \ + move rd, rs; \ .set pop; \ 9: #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */ #if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \ (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64) -#define MOVN(rd,rs,rt) \ - movn rd,rs,rt -#define MOVZ(rd,rs,rt) \ - movz rd,rs,rt +#define MOVN(rd, rs, rt) \ + movn rd, rs, rt +#define MOVZ(rd, rs, rt) \ + movz rd, rs, rt #endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */ /* @@ -396,6 +396,6 @@ symbol = value #define MTC0 dmtc0 #endif -#define SSNOP sll zero,zero,1 +#define SSNOP sll zero, zero, 1 #endif /* __ASM_ASM_H */ diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro.h index c5f20df780e9..7a881755800f 100644 --- a/include/asm-mips/asmmacro.h +++ b/include/asm-mips/asmmacro.h @@ -56,27 +56,27 @@ * Temporary until all gas have MT ASE support */ .macro DMT reg=0 - .word (0x41600bc1 | (\reg << 16)) + .word 0x41600bc1 | (\reg << 16) .endm .macro EMT reg=0 - .word (0x41600be1 | (\reg << 16)) + .word 0x41600be1 | (\reg << 16) .endm .macro DVPE reg=0 - .word (0x41600001 | (\reg << 16)) + .word 0x41600001 | (\reg << 16) .endm .macro EVPE reg=0 - .word (0x41600021 | (\reg << 16)) + .word 0x41600021 | (\reg << 16) .endm .macro MFTR rt=0, rd=0, u=0, sel=0 - .word (0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)) + .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) .endm .macro MTTR rt=0, rd=0, u=0, sel=0 - .word (0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)) + .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) .endm #endif /* _ASM_ASMMACRO_H */ diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h index 7d8003769a44..a798d6299a79 100644 --- a/include/asm-mips/atomic.h +++ b/include/asm-mips/atomic.h @@ -39,7 +39,7 @@ typedef struct { volatile int counter; } atomic_t; * * Atomically sets the value of @v to @i. */ -#define atomic_set(v,i) ((v)->counter = (i)) +#define atomic_set(v, i) ((v)->counter = (i)) /* * atomic_add - add integer to atomic variable @@ -335,8 +335,8 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) } #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) -#define atomic_dec_return(v) atomic_sub_return(1,(v)) -#define atomic_inc_return(v) atomic_add_return(1,(v)) +#define atomic_dec_return(v) atomic_sub_return(1, (v)) +#define atomic_inc_return(v) atomic_add_return(1, (v)) /* * atomic_sub_and_test - subtract value from variable and test result @@ -347,7 +347,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) * true if the result is zero, or false for all * other cases. */ -#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0) +#define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0) /* * atomic_inc_and_test - increment and test @@ -381,7 +381,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) * * Atomically increments @v by 1. */ -#define atomic_inc(v) atomic_add(1,(v)) +#define atomic_inc(v) atomic_add(1, (v)) /* * atomic_dec - decrement and test @@ -389,7 +389,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) * * Atomically decrements @v by 1. */ -#define atomic_dec(v) atomic_sub(1,(v)) +#define atomic_dec(v) atomic_sub(1, (v)) /* * atomic_add_negative - add and test if negative @@ -400,7 +400,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) * if the result is negative, or false when * result is greater than or equal to zero. */ -#define atomic_add_negative(i,v) (atomic_add_return(i, (v)) < 0) +#define atomic_add_negative(i, v) (atomic_add_return(i, (v)) < 0) #ifdef CONFIG_64BIT @@ -420,7 +420,7 @@ typedef struct { volatile long counter; } atomic64_t; * @v: pointer of type atomic64_t * @i: required value */ -#define atomic64_set(v,i) ((v)->counter = (i)) +#define atomic64_set(v, i) ((v)->counter = (i)) /* * atomic64_add - add integer to atomic variable @@ -718,8 +718,8 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0) -#define atomic64_dec_return(v) atomic64_sub_return(1,(v)) -#define atomic64_inc_return(v) atomic64_add_return(1,(v)) +#define atomic64_dec_return(v) atomic64_sub_return(1, (v)) +#define atomic64_inc_return(v) atomic64_add_return(1, (v)) /* * atomic64_sub_and_test - subtract value from variable and test result @@ -730,7 +730,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) * true if the result is zero, or false for all * other cases. */ -#define atomic64_sub_and_test(i,v) (atomic64_sub_return((i), (v)) == 0) +#define atomic64_sub_and_test(i, v) (atomic64_sub_return((i), (v)) == 0) /* * atomic64_inc_and_test - increment and test @@ -764,7 +764,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) * * Atomically increments @v by 1. */ -#define atomic64_inc(v) atomic64_add(1,(v)) +#define atomic64_inc(v) atomic64_add(1, (v)) /* * atomic64_dec - decrement and test @@ -772,7 +772,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) * * Atomically decrements @v by 1. */ -#define atomic64_dec(v) atomic64_sub(1,(v)) +#define atomic64_dec(v) atomic64_sub(1, (v)) /* * atomic64_add_negative - add and test if negative @@ -783,7 +783,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) * if the result is negative, or false when * result is greater than or equal to zero. */ -#define atomic64_add_negative(i,v) (atomic64_add_return(i, (v)) < 0) +#define atomic64_add_negative(i, v) (atomic64_add_return(i, (v)) < 0) #endif /* CONFIG_64BIT */ diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index 148bc79557f1..899357a72ac4 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -19,14 +19,14 @@ #include <asm/sgidefs.h> #include <asm/war.h> -#if (_MIPS_SZLONG == 32) +#if _MIPS_SZLONG == 32 #define SZLONG_LOG 5 #define SZLONG_MASK 31UL #define __LL "ll " #define __SC "sc " #define __INS "ins " #define __EXT "ext " -#elif (_MIPS_SZLONG == 64) +#elif _MIPS_SZLONG == 64 #define SZLONG_LOG 6 #define SZLONG_MASK 63UL #define __LL "lld " @@ -461,7 +461,7 @@ static inline int __ilog2(unsigned long x) int lz; if (sizeof(x) == 4) { - __asm__ ( + __asm__( " .set push \n" " .set mips32 \n" " clz %0, %1 \n" @@ -474,7 +474,7 @@ static inline int __ilog2(unsigned long x) BUG_ON(sizeof(x) != 8); - __asm__ ( + __asm__( " .set push \n" " .set mips64 \n" " dclz %0, %1 \n" @@ -508,7 +508,7 @@ static inline unsigned long __ffs(unsigned long word) */ static inline int fls(int word) { - __asm__ ("clz %0, %1" : "=r" (word) : "r" (word)); + __asm__("clz %0, %1" : "=r" (word) : "r" (word)); return 32 - word; } @@ -516,7 +516,7 @@ static inline int fls(int word) #if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64) static inline int fls64(__u64 word) { - __asm__ ("dclz %0, %1" : "=r" (word) : "r" (word)); + __asm__("dclz %0, %1" : "=r" (word) : "r" (word)); return 64 - word; } diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index c0f052b37b9e..b2dd9b33de8f 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -15,21 +15,19 @@ #include <asm/setup.h> /* - * The MACH_GROUP_ IDs are the equivalent to PCI vendor IDs; the remaining - * MACH_ values equivalent to product IDs. As such the numbers do not - * necessarily reflect technical relations or similarities between systems. + * The MACH_ IDs are sort of equivalent to PCI product IDs. As such the + * numbers do not necessarily reflect technical relations or similarities + * between systems. */ /* * Valid machtype values for group unknown */ -#define MACH_GROUP_UNKNOWN 0 /* whatever... */ #define MACH_UNKNOWN 0 /* whatever... */ /* * Valid machtype values for group JAZZ */ -#define MACH_GROUP_JAZZ 1 /* Jazz */ #define MACH_ACER_PICA_61 0 /* Acer PICA-61 (PICA1) */ #define MACH_MIPS_MAGNUM_4000 1 /* Mips Magnum 4000 "RC4030" */ #define MACH_OLIVETTI_M700 2 /* Olivetti M700-10 (-15 ??) */ @@ -37,7 +35,6 @@ /* * Valid machtype for group DEC */ -#define MACH_GROUP_DEC 2 /* Digital Equipment */ #define MACH_DSUNKNOWN 0 #define MACH_DS23100 1 /* DECstation 2100 or 3100 */ #define MACH_DS5100 2 /* DECsystem 5100 */ @@ -53,26 +50,22 @@ /* * Valid machtype for group ARC */ -#define MACH_GROUP_ARC 3 /* Deskstation */ #define MACH_DESKSTATION_RPC44 0 /* Deskstation rPC44 */ #define MACH_DESKSTATION_TYNE 1 /* Deskstation Tyne */ /* * Valid machtype for group SNI_RM */ -#define MACH_GROUP_SNI_RM 4 /* Siemens Nixdorf RM series */ #define MACH_SNI_RM200_PCI 0 /* RM200/RM300/RM400 PCI series */ /* * Valid machtype for group ACN */ -#define MACH_GROUP_ACN 5 #define MACH_ACN_MIPS_BOARD 0 /* ACN MIPS single board */ /* * Valid machtype for group SGI */ -#define MACH_GROUP_SGI 6 /* Silicon Graphics */ #define MACH_SGI_IP22 0 /* Indy, Indigo2, Challenge S */ #define MACH_SGI_IP27 1 /* Origin 200, Origin 2000, Onyx 2 */ #define MACH_SGI_IP28 2 /* Indigo2 Impact */ @@ -82,26 +75,22 @@ /* * Valid machtype for group COBALT */ -#define MACH_GROUP_COBALT 7 /* Cobalt servers */ #define MACH_COBALT_27 0 /* Proto "27" hardware */ /* * Valid machtype for group BAGET */ -#define MACH_GROUP_BAGET 9 /* Baget */ #define MACH_BAGET201 0 /* BT23-201 */ #define MACH_BAGET202 1 /* BT23-202 */ /* * Cosine boards. */ -#define MACH_GROUP_COSINE 10 /* CoSine Orion */ #define MACH_COSINE_ORION 0 /* * Valid machtype for group MOMENCO */ -#define MACH_GROUP_MOMENCO 12 /* Momentum Boards */ #define MACH_MOMENCO_OCELOT 0 #define MACH_MOMENCO_OCELOT_G 1 /* no more supported (may 2007) */ #define MACH_MOMENCO_OCELOT_C 2 /* no more supported (jun 2007) */ @@ -111,7 +100,6 @@ /* * Valid machtype for group PHILIPS */ -#define MACH_GROUP_PHILIPS 14 #define MACH_PHILIPS_NINO 0 /* Nino */ #define MACH_PHILIPS_VELO 1 /* Velo */ #define MACH_PHILIPS_JBS 2 /* JBS */ @@ -120,13 +108,11 @@ /* * Valid machtype for group SIBYTE */ -#define MACH_GROUP_SIBYTE 16 /* Sibyte / Broadcom */ #define MACH_SWARM 0 /* * Valid machtypes for group Toshiba */ -#define MACH_GROUP_TOSHIBA 17 /* Toshiba Reference Systems TSBREF */ #define MACH_PALLAS 0 #define MACH_TOPAS 1 #define MACH_JMR 2 @@ -138,7 +124,6 @@ /* * Valid machtype for group Alchemy */ -#define MACH_GROUP_ALCHEMY 18 /* AMD Alchemy */ #define MACH_PB1000 0 /* Au1000-based eval board */ #define MACH_PB1100 1 /* Au1100-based eval board */ #define MACH_PB1500 2 /* Au1500-based eval board */ @@ -160,7 +145,6 @@ * FIXME: MACH_GROUPs should be by _MANUFACTURER_ of * the device, not by * technical properties, so no new additions to this group. */ -#define MACH_GROUP_NEC_VR41XX 19 #define MACH_NEC_OSPREY 0 /* Osprey eval board */ #define MACH_NEC_EAGLE 1 /* NEC Eagle/Hawk board */ #define MACH_ZAO_CAPCELLA 2 /* ZAO Networks Capcella */ @@ -171,32 +155,33 @@ #define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */ #define MACH_NEC_CMBVR4133 8 /* CMB VR4133 Board */ -#define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */ #define MACH_HP_LASERJET 1 /* + * Valid machtype for group LASAT + */ +#define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */ +#define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */ + +/* * Valid machtype for group TITAN */ -#define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */ #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */ #define MACH_TITAN_EXCITE 2 /* Basler eXcite */ /* * Valid machtype for group NEC EMMA2RH */ -#define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */ #define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */ /* * Valid machtype for group LEMOTE */ -#define MACH_GROUP_LEMOTE 27 #define MACH_LEMOTE_FULONG 0 /* * Valid machtype for group PMC-MSP */ -#define MACH_GROUP_MSP 26 /* PMC-Sierra MSP boards/CPUs */ #define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */ #define MACH_MSP4200_GW 1 /* PMC-Sierra MSP4200 Gateway demo */ #define MACH_MSP4200_FPGA 2 /* PMC-Sierra MSP4200 Emulation */ @@ -205,15 +190,19 @@ #define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */ #define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */ -#define MACH_GROUP_WINDRIVER 28 /* Windriver boards */ #define MACH_WRPPMC 1 +/* + * Valid machtype for group Broadcom + */ +#define MACH_GROUP_BRCM 23 /* Broadcom */ +#define MACH_BCM47XX 1 /* Broadcom BCM47XX */ + #define CL_SIZE COMMAND_LINE_SIZE const char *get_system_type(void); extern unsigned long mips_machtype; -extern unsigned long mips_machgroup; #define BOOT_MEM_MAP_MAX 32 #define BOOT_MEM_RAM 1 diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h index eee83cbdf2b0..fe7dc2d59b69 100644 --- a/include/asm-mips/byteorder.h +++ b/include/asm-mips/byteorder.h @@ -65,9 +65,9 @@ static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x) #endif /* __GNUC__ */ -#if defined (__MIPSEB__) +#if defined(__MIPSEB__) # include <linux/byteorder/big_endian.h> -#elif defined (__MIPSEL__) +#elif defined(__MIPSEL__) # include <linux/byteorder/little_endian.h> #else # error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" diff --git a/include/asm-mips/cmpxchg.h b/include/asm-mips/cmpxchg.h index c5b4708e003b..a5ec0e5dc5b8 100644 --- a/include/asm-mips/cmpxchg.h +++ b/include/asm-mips/cmpxchg.h @@ -72,7 +72,7 @@ */ extern void __cmpxchg_called_with_bad_pointer(void); -#define __cmpxchg(ptr,old,new,barrier) \ +#define __cmpxchg(ptr, old, new, barrier) \ ({ \ __typeof__(ptr) __ptr = (ptr); \ __typeof__(*(ptr)) __old = (old); \ @@ -102,6 +102,6 @@ extern void __cmpxchg_called_with_bad_pointer(void); }) #define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_llsc_mb()) -#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new,) +#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new, ) #endif /* __ASM_CMPXCHG_H */ diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h index d95a83e3e1d7..f6bd308f047f 100644 --- a/include/asm-mips/cpu-features.h +++ b/include/asm-mips/cpu-features.h @@ -9,11 +9,14 @@ #ifndef __ASM_CPU_FEATURES_H #define __ASM_CPU_FEATURES_H - #include <asm/cpu.h> #include <asm/cpu-info.h> #include <cpu-feature-overrides.h> +#ifndef current_cpu_type +#define current_cpu_type() current_cpu_data.cputype +#endif + /* * SMP assumption: Options of CPU 0 are a superset of all processors. * This is true for all known MIPS systems. @@ -35,9 +38,6 @@ #ifndef cpu_has_tx39_cache #define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) #endif -#ifndef cpu_has_sb1_cache -#define cpu_has_sb1_cache (cpu_data[0].options & MIPS_CPU_SB1_CACHE) -#endif #ifndef cpu_has_fpu #define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) #define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h index 22fe8453fcc7..94f1c8172360 100644 --- a/include/asm-mips/cpu-info.h +++ b/include/asm-mips/cpu-info.h @@ -14,10 +14,6 @@ #include <asm/cache.h> -#ifdef CONFIG_SGI_IP27 -#include <asm/sn/types.h> -#endif - /* * Descriptor for a cache */ @@ -43,20 +39,6 @@ struct cache_desc { struct cpuinfo_mips { unsigned long udelay_val; unsigned long asid_cache; -#if defined(CONFIG_SGI_IP27) -// cpuid_t p_cpuid; /* PROM assigned cpuid */ - cnodeid_t p_nodeid; /* my node ID in compact-id-space */ - nasid_t p_nasid; /* my node ID in numa-as-id-space */ - unsigned char p_slice; /* Physical position on node board */ -#endif -#if 0 - unsigned long loops_per_sec; - unsigned long ipi_count; - unsigned long irq_attempt[NR_IRQS]; - unsigned long smp_local_irq_count; - unsigned long prof_multiplier; - unsigned long prof_counter; -#endif /* * Capability and feature descriptor structure for MIPS CPU @@ -92,4 +74,7 @@ extern struct cpuinfo_mips cpu_data[]; extern void cpu_probe(void); extern void cpu_report(void); +extern const char *__cpu_name[]; +#define cpu_name_string() __cpu_name[smp_processor_id()] + #endif /* __ASM_CPU_INFO_H */ diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index 3857358fb6de..54fc18a4e5a8 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -106,6 +106,13 @@ #define PRID_IMP_SR71000 0x0400 /* + * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM + */ + +#define PRID_IMP_BCM4710 0x4000 +#define PRID_IMP_BCM3302 0x9000 + +/* * Definitions for 7:0 on legacy processors */ @@ -150,75 +157,55 @@ #define FPIR_IMP_NONE 0x0000 -#define CPU_UNKNOWN 0 -#define CPU_R2000 1 -#define CPU_R3000 2 -#define CPU_R3000A 3 -#define CPU_R3041 4 -#define CPU_R3051 5 -#define CPU_R3052 6 -#define CPU_R3081 7 -#define CPU_R3081E 8 -#define CPU_R4000PC 9 -#define CPU_R4000SC 10 -#define CPU_R4000MC 11 -#define CPU_R4200 12 -#define CPU_R4400PC 13 -#define CPU_R4400SC 14 -#define CPU_R4400MC 15 -#define CPU_R4600 16 -#define CPU_R6000 17 -#define CPU_R6000A 18 -#define CPU_R8000 19 -#define CPU_R10000 20 -#define CPU_R12000 21 -#define CPU_R4300 22 -#define CPU_R4650 23 -#define CPU_R4700 24 -#define CPU_R5000 25 -#define CPU_R5000A 26 -#define CPU_R4640 27 -#define CPU_NEVADA 28 -#define CPU_RM7000 29 -#define CPU_R5432 30 -#define CPU_4KC 31 -#define CPU_5KC 32 -#define CPU_R4310 33 -#define CPU_SB1 34 -#define CPU_TX3912 35 -#define CPU_TX3922 36 -#define CPU_TX3927 37 -#define CPU_AU1000 38 -#define CPU_4KEC 39 -#define CPU_4KSC 40 -#define CPU_VR41XX 41 -#define CPU_R5500 42 -#define CPU_TX49XX 43 -#define CPU_AU1500 44 -#define CPU_20KC 45 -#define CPU_VR4111 46 -#define CPU_VR4121 47 -#define CPU_VR4122 48 -#define CPU_VR4131 49 -#define CPU_VR4181 50 -#define CPU_VR4181A 51 -#define CPU_AU1100 52 -#define CPU_SR71000 53 -#define CPU_RM9000 54 -#define CPU_25KF 55 -#define CPU_VR4133 56 -#define CPU_AU1550 57 -#define CPU_24K 58 -#define CPU_AU1200 59 -#define CPU_34K 60 -#define CPU_PR4450 61 -#define CPU_SB1A 62 -#define CPU_74K 63 -#define CPU_R14000 64 -#define CPU_LOONGSON1 65 -#define CPU_LOONGSON2 66 - -#define CPU_LAST 66 +enum cpu_type_enum { + CPU_UNKNOWN, + + /* + * R2000 class processors + */ + CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052, + CPU_R3081, CPU_R3081E, + + /* + * R6000 class processors + */ + CPU_R6000, CPU_R6000A, + + /* + * R4000 class processors + */ + CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310, + CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650, + CPU_R4700, CPU_R5000, CPU_R5000A, CPU_R5500, CPU_NEVADA, CPU_R5432, + CPU_R10000, CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, + CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000, + CPU_SR71000, CPU_RM9000, CPU_TX49XX, + + /* + * R8000 class processors + */ + CPU_R8000, + + /* + * TX3900 class processors + */ + CPU_TX3912, CPU_TX3922, CPU_TX3927, + + /* + * MIPS32 class processors + */ + CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_74K, CPU_AU1000, + CPU_AU1100, CPU_AU1200, CPU_AU1500, CPU_AU1550, CPU_PR4450, + CPU_BCM3302, CPU_BCM4710, + + /* + * MIPS64 class processors + */ + CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, + + CPU_LAST +}; + /* * ISA Level encodings @@ -247,24 +234,23 @@ #define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */ #define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */ #define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */ -#define MIPS_CPU_SB1_CACHE 0x00000020 /* SB1-style caches */ -#define MIPS_CPU_FPU 0x00000040 /* CPU has FPU */ -#define MIPS_CPU_32FPR 0x00000080 /* 32 dbl. prec. FP registers */ -#define MIPS_CPU_COUNTER 0x00000100 /* Cycle count/compare */ -#define MIPS_CPU_WATCH 0x00000200 /* watchpoint registers */ -#define MIPS_CPU_DIVEC 0x00000400 /* dedicated interrupt vector */ -#define MIPS_CPU_VCE 0x00000800 /* virt. coherence conflict possible */ -#define MIPS_CPU_CACHE_CDEX_P 0x00001000 /* Create_Dirty_Exclusive CACHE op */ -#define MIPS_CPU_CACHE_CDEX_S 0x00002000 /* ... same for seconary cache ... */ -#define MIPS_CPU_MCHECK 0x00004000 /* Machine check exception */ -#define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */ -#define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */ -#define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */ -#define MIPS_CPU_INCLUSIVE_CACHES 0x00040000 /* P-cache subset enforced */ -#define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ -#define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ -#define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ -#define MIPS_CPU_ULRI 0x00400000 /* CPU has ULRI feature */ +#define MIPS_CPU_FPU 0x00000020 /* CPU has FPU */ +#define MIPS_CPU_32FPR 0x00000040 /* 32 dbl. prec. FP registers */ +#define MIPS_CPU_COUNTER 0x00000080 /* Cycle count/compare */ +#define MIPS_CPU_WATCH 0x00000100 /* watchpoint registers */ +#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */ +#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */ +#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */ +#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */ +#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */ +#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */ +#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */ +#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */ +#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */ +#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */ +#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */ +#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ +#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ /* * CPU ASE encodings diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h index 223d156efb9f..fab32131e9b4 100644 --- a/include/asm-mips/delay.h +++ b/include/asm-mips/delay.h @@ -81,7 +81,7 @@ static inline void __udelay(unsigned long usecs, unsigned long lpj) #define __udelay_val cpu_data[raw_smp_processor_id()].udelay_val -#define udelay(usecs) __udelay((usecs),__udelay_val) +#define udelay(usecs) __udelay((usecs), __udelay_val) /* make sure "usecs *= ..." in udelay do not overflow. */ #if HZ >= 1000 diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h index e7d95d48177d..766f91ad5cd3 100644 --- a/include/asm-mips/elf.h +++ b/include/asm-mips/elf.h @@ -319,7 +319,7 @@ do { \ struct task_struct; extern void elf_dump_regs(elf_greg_t *, struct pt_regs *regs); -extern int dump_task_regs (struct task_struct *, elf_gregset_t *); +extern int dump_task_regs(struct task_struct *, elf_gregset_t *); extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); #define ELF_CORE_COPY_REGS(elf_regs, regs) \ diff --git a/include/asm-mips/fixmap.h b/include/asm-mips/fixmap.h index 02c8a13fc894..f27b96cfac2e 100644 --- a/include/asm-mips/fixmap.h +++ b/include/asm-mips/fixmap.h @@ -60,8 +60,8 @@ enum fixed_addresses { __end_of_fixed_addresses }; -extern void __set_fixmap (enum fixed_addresses idx, - unsigned long phys, pgprot_t flags); +extern void __set_fixmap(enum fixed_addresses idx, + unsigned long phys, pgprot_t flags); #define set_fixmap(idx, phys) \ __set_fixmap(idx, phys, PAGE_KERNEL) diff --git a/include/asm-mips/floppy.h b/include/asm-mips/floppy.h index aa1ef8b352cc..a62d0990c8ae 100644 --- a/include/asm-mips/floppy.h +++ b/include/asm-mips/floppy.h @@ -10,9 +10,11 @@ #ifndef _ASM_FLOPPY_H #define _ASM_FLOPPY_H +#include <linux/dma-mapping.h> + static inline void fd_cacheflush(char * addr, long size) { - dma_cache_wback_inv((unsigned long)addr,size); + dma_cache_sync(NULL, addr, size, DMA_BIDIRECTIONAL); } #define MAX_BUFFER_SECTORS 24 @@ -47,7 +49,7 @@ static inline void fd_cacheflush(char * addr, long size) * Actually this needs to be a bit more complicated since the so much different * hardware available with MIPS CPUs ... */ -#define CROSS_64KB(a,s) ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64) +#define CROSS_64KB(a, s) ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64) #define EXTRA_FLOPPY_PARAMS diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h index b623882bce19..3e7e30d4f418 100644 --- a/include/asm-mips/futex.h +++ b/include/asm-mips/futex.h @@ -75,7 +75,7 @@ } static inline int -futex_atomic_op_inuser (int encoded_op, int __user *uaddr) +futex_atomic_op_inuser(int encoded_op, int __user *uaddr) { int op = (encoded_op >> 28) & 7; int cmp = (encoded_op >> 24) & 15; diff --git a/include/asm-mips/arc/hinv.h b/include/asm-mips/fw/arc/hinv.h index ee792bf04002..e6ff4add04e2 100644 --- a/include/asm-mips/arc/hinv.h +++ b/include/asm-mips/fw/arc/hinv.h @@ -4,7 +4,8 @@ #ifndef _ASM_ARC_HINV_H #define _ASM_ARC_HINV_H -#include <asm/arc/types.h> +#include <asm/sgidefs.h> +#include <asm/fw/arc/types.h> /* configuration query defines */ typedef enum configclass { @@ -110,7 +111,7 @@ union key_u { ULONG FullKey; }; -#if _MIPS_SIM == _ABI64 +#if _MIPS_SIM == _MIPS_SIM_ABI64 #define SGI_ARCS_VERS 64 /* sgi 64-bit version */ #define SGI_ARCS_REV 0 /* rev .00 */ #else diff --git a/include/asm-mips/arc/types.h b/include/asm-mips/fw/arc/types.h index b9adcd6f0860..b9adcd6f0860 100644 --- a/include/asm-mips/arc/types.h +++ b/include/asm-mips/fw/arc/types.h diff --git a/include/asm-mips/fw/cfe/cfe_api.h b/include/asm-mips/fw/cfe/cfe_api.h new file mode 100644 index 000000000000..41cf050b6810 --- /dev/null +++ b/include/asm-mips/fw/cfe/cfe_api.h @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2000, 2001, 2002 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* ********************************************************************* + * + * Broadcom Common Firmware Environment (CFE) + * + * Device function prototypes File: cfe_api.h + * + * This file contains declarations for doing callbacks to + * cfe from an application. It should be the only header + * needed by the application to use this library + * + * Authors: Mitch Lichtenberg, Chris Demetriou + * + ********************************************************************* */ + +#ifndef CFE_API_H +#define CFE_API_H + +/* + * Apply customizations here for different OSes. These need to: + * * typedef uint64_t, int64_t, intptr_t, uintptr_t. + * * define cfe_strlen() if use of an existing function is desired. + * * define CFE_API_IMPL_NAMESPACE if API functions are to use + * names in the implementation namespace. + * Also, optionally, if the build environment does not do so automatically, + * CFE_API_* can be defined here as desired. + */ +/* Begin customization. */ +#include <linux/types.h> +#include <linux/string.h> + +typedef long intptr_t; + +#define cfe_strlen strlen + +#define CFE_API_ALL +#define CFE_API_STRLEN_CUSTOM +/* End customization. */ + + +/* ********************************************************************* + * Constants + ********************************************************************* */ + +/* Seal indicating CFE's presence, passed to user program. */ +#define CFE_EPTSEAL 0x43464531 + +#define CFE_MI_RESERVED 0 /* memory is reserved, do not use */ +#define CFE_MI_AVAILABLE 1 /* memory is available */ + +#define CFE_FLG_WARMSTART 0x00000001 +#define CFE_FLG_FULL_ARENA 0x00000001 +#define CFE_FLG_ENV_PERMANENT 0x00000001 + +#define CFE_CPU_CMD_START 1 +#define CFE_CPU_CMD_STOP 0 + +#define CFE_STDHANDLE_CONSOLE 0 + +#define CFE_DEV_NETWORK 1 +#define CFE_DEV_DISK 2 +#define CFE_DEV_FLASH 3 +#define CFE_DEV_SERIAL 4 +#define CFE_DEV_CPU 5 +#define CFE_DEV_NVRAM 6 +#define CFE_DEV_CLOCK 7 +#define CFE_DEV_OTHER 8 +#define CFE_DEV_MASK 0x0F + +#define CFE_CACHE_FLUSH_D 1 +#define CFE_CACHE_INVAL_I 2 +#define CFE_CACHE_INVAL_D 4 +#define CFE_CACHE_INVAL_L2 8 + +#define CFE_FWI_64BIT 0x00000001 +#define CFE_FWI_32BIT 0x00000002 +#define CFE_FWI_RELOC 0x00000004 +#define CFE_FWI_UNCACHED 0x00000008 +#define CFE_FWI_MULTICPU 0x00000010 +#define CFE_FWI_FUNCSIM 0x00000020 +#define CFE_FWI_RTLSIM 0x00000040 + +typedef struct { + int64_t fwi_version; /* major, minor, eco version */ + int64_t fwi_totalmem; /* total installed mem */ + int64_t fwi_flags; /* various flags */ + int64_t fwi_boardid; /* board ID */ + int64_t fwi_bootarea_va; /* VA of boot area */ + int64_t fwi_bootarea_pa; /* PA of boot area */ + int64_t fwi_bootarea_size; /* size of boot area */ +} cfe_fwinfo_t; + + +/* + * cfe_strlen is handled specially: If already defined, it has been + * overridden in this environment with a standard strlen-like function. + */ +#ifdef cfe_strlen +# define CFE_API_STRLEN_CUSTOM +#else +# ifdef CFE_API_IMPL_NAMESPACE +# define cfe_strlen(a) __cfe_strlen(a) +# endif +int cfe_strlen(char *name); +#endif + +/* + * Defines and prototypes for functions which take no arguments. + */ +#ifdef CFE_API_IMPL_NAMESPACE +int64_t __cfe_getticks(void); +#define cfe_getticks() __cfe_getticks() +#else +int64_t cfe_getticks(void); +#endif + +/* + * Defines and prototypes for the rest of the functions. + */ +#ifdef CFE_API_IMPL_NAMESPACE +#define cfe_close(a) __cfe_close(a) +#define cfe_cpu_start(a, b, c, d, e) __cfe_cpu_start(a, b, c, d, e) +#define cfe_cpu_stop(a) __cfe_cpu_stop(a) +#define cfe_enumenv(a, b, d, e, f) __cfe_enumenv(a, b, d, e, f) +#define cfe_enummem(a, b, c, d, e) __cfe_enummem(a, b, c, d, e) +#define cfe_exit(a, b) __cfe_exit(a, b) +#define cfe_flushcache(a) __cfe_cacheflush(a) +#define cfe_getdevinfo(a) __cfe_getdevinfo(a) +#define cfe_getenv(a, b, c) __cfe_getenv(a, b, c) +#define cfe_getfwinfo(a) __cfe_getfwinfo(a) +#define cfe_getstdhandle(a) __cfe_getstdhandle(a) +#define cfe_init(a, b) __cfe_init(a, b) +#define cfe_inpstat(a) __cfe_inpstat(a) +#define cfe_ioctl(a, b, c, d, e, f) __cfe_ioctl(a, b, c, d, e, f) +#define cfe_open(a) __cfe_open(a) +#define cfe_read(a, b, c) __cfe_read(a, b, c) +#define cfe_readblk(a, b, c, d) __cfe_readblk(a, b, c, d) +#define cfe_setenv(a, b) __cfe_setenv(a, b) +#define cfe_write(a, b, c) __cfe_write(a, b, c) +#define cfe_writeblk(a, b, c, d __cfe_writeblk(a, b, c, d) +#endif /* CFE_API_IMPL_NAMESPACE */ + +int cfe_close(int handle); +int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1); +int cfe_cpu_stop(int cpu); +int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen); +int cfe_enummem(int idx, int flags, uint64_t * start, uint64_t * length, + uint64_t * type); +int cfe_exit(int warm, int status); +int cfe_flushcache(int flg); +int cfe_getdevinfo(char *name); +int cfe_getenv(char *name, char *dest, int destlen); +int cfe_getfwinfo(cfe_fwinfo_t * info); +int cfe_getstdhandle(int flg); +int cfe_init(uint64_t handle, uint64_t ept); +int cfe_inpstat(int handle); +int cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer, + int length, int *retlen, uint64_t offset); +int cfe_open(char *name); +int cfe_read(int handle, unsigned char *buffer, int length); +int cfe_readblk(int handle, int64_t offset, unsigned char *buffer, + int length); +int cfe_setenv(char *name, char *val); +int cfe_write(int handle, unsigned char *buffer, int length); +int cfe_writeblk(int handle, int64_t offset, unsigned char *buffer, + int length); + +#endif /* CFE_API_H */ diff --git a/include/asm-mips/fw/cfe/cfe_error.h b/include/asm-mips/fw/cfe/cfe_error.h new file mode 100644 index 000000000000..975f00002cbe --- /dev/null +++ b/include/asm-mips/fw/cfe/cfe_error.h @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2000, 2001, 2002 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* ********************************************************************* + * + * Broadcom Common Firmware Environment (CFE) + * + * Error codes File: cfe_error.h + * + * CFE's global error code list is here. + * + * Author: Mitch Lichtenberg + * + ********************************************************************* */ + + +#define CFE_OK 0 +#define CFE_ERR -1 /* generic error */ +#define CFE_ERR_INV_COMMAND -2 +#define CFE_ERR_EOF -3 +#define CFE_ERR_IOERR -4 +#define CFE_ERR_NOMEM -5 +#define CFE_ERR_DEVNOTFOUND -6 +#define CFE_ERR_DEVOPEN -7 +#define CFE_ERR_INV_PARAM -8 +#define CFE_ERR_ENVNOTFOUND -9 +#define CFE_ERR_ENVREADONLY -10 + +#define CFE_ERR_NOTELF -11 +#define CFE_ERR_NOT32BIT -12 +#define CFE_ERR_WRONGENDIAN -13 +#define CFE_ERR_BADELFVERS -14 +#define CFE_ERR_NOTMIPS -15 +#define CFE_ERR_BADELFFMT -16 +#define CFE_ERR_BADADDR -17 + +#define CFE_ERR_FILENOTFOUND -18 +#define CFE_ERR_UNSUPPORTED -19 + +#define CFE_ERR_HOSTUNKNOWN -20 + +#define CFE_ERR_TIMEOUT -21 + +#define CFE_ERR_PROTOCOLERR -22 + +#define CFE_ERR_NETDOWN -23 +#define CFE_ERR_NONAMESERVER -24 + +#define CFE_ERR_NOHANDLES -25 +#define CFE_ERR_ALREADYBOUND -26 + +#define CFE_ERR_CANNOTSET -27 +#define CFE_ERR_NOMORE -28 +#define CFE_ERR_BADFILESYS -29 +#define CFE_ERR_FSNOTAVAIL -30 + +#define CFE_ERR_INVBOOTBLOCK -31 +#define CFE_ERR_WRONGDEVTYPE -32 +#define CFE_ERR_BBCHECKSUM -33 +#define CFE_ERR_BOOTPROGCHKSUM -34 + +#define CFE_ERR_LDRNOTAVAIL -35 + +#define CFE_ERR_NOTREADY -36 + +#define CFE_ERR_GETMEM -37 +#define CFE_ERR_SETMEM -38 + +#define CFE_ERR_NOTCONN -39 +#define CFE_ERR_ADDRINUSE -40 diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index 6a5fa32f615b..2de638f84c86 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h @@ -10,11 +10,12 @@ #ifndef _ASM_HAZARDS_H #define _ASM_HAZARDS_H - #ifdef __ASSEMBLY__ #define ASMMACRO(name, code...) .macro name; code; .endm #else +#include <asm/cpu-features.h> + #define ASMMACRO(name, code...) \ __asm__(".macro " #name "; " #code "; .endm"); \ \ @@ -86,6 +87,57 @@ do { \ : "=r" (tmp)); \ } while (0) +#elif defined(CONFIG_CPU_MIPSR1) + +/* + * These are slightly complicated by the fact that we guarantee R1 kernels to + * run fine on R2 processors. + */ +ASMMACRO(mtc0_tlbw_hazard, + _ssnop; _ssnop; _ehb + ) +ASMMACRO(tlbw_use_hazard, + _ssnop; _ssnop; _ssnop; _ehb + ) +ASMMACRO(tlb_probe_hazard, + _ssnop; _ssnop; _ssnop; _ehb + ) +ASMMACRO(irq_enable_hazard, + _ssnop; _ssnop; _ssnop; _ehb + ) +ASMMACRO(irq_disable_hazard, + _ssnop; _ssnop; _ssnop; _ehb + ) +ASMMACRO(back_to_back_c0_hazard, + _ssnop; _ssnop; _ssnop; _ehb + ) +/* + * gcc has a tradition of misscompiling the previous construct using the + * address of a label as argument to inline assembler. Gas otoh has the + * annoying difference between la and dla which are only usable for 32-bit + * rsp. 64-bit code, so can't be used without conditional compilation. + * The alterantive is switching the assembler to 64-bit code which happens + * to work right even for 32-bit code ... + */ +#define __instruction_hazard() \ +do { \ + unsigned long tmp; \ + \ + __asm__ __volatile__( \ + " .set mips64r2 \n" \ + " dla %0, 1f \n" \ + " jr.hb %0 \n" \ + " .set mips0 \n" \ + "1: \n" \ + : "=r" (tmp)); \ +} while (0) + +#define instruction_hazard() \ +do { \ + if (cpu_has_mips_r2) \ + __instruction_hazard(); \ +} while (0) + #elif defined(CONFIG_CPU_R10000) /* @@ -193,7 +245,7 @@ ASMMACRO(enable_fpu_hazard, .set mips64; .set noreorder; _ssnop; - bnezl $0,.+4; + bnezl $0, .+4; _ssnop; .set pop ) diff --git a/include/asm-mips/hw_irq.h b/include/asm-mips/hw_irq.h index 458d9fdc76bf..aca05a43a97b 100644 --- a/include/asm-mips/hw_irq.h +++ b/include/asm-mips/hw_irq.h @@ -8,15 +8,8 @@ #ifndef __ASM_HW_IRQ_H #define __ASM_HW_IRQ_H -#include <linux/profile.h> #include <asm/atomic.h> -extern void disable_8259A_irq(unsigned int irq); -extern void enable_8259A_irq(unsigned int irq); -extern int i8259A_irq_pending(unsigned int irq); -extern void make_8259A_irq(unsigned int irq); -extern void init_8259A(int aeoi); - extern atomic_t irq_err_count; /* diff --git a/include/asm-mips/i8253.h b/include/asm-mips/i8253.h new file mode 100644 index 000000000000..8f689d7df6b1 --- /dev/null +++ b/include/asm-mips/i8253.h @@ -0,0 +1,30 @@ +/* + * Machine specific IO port address definition for generic. + * Written by Osamu Tomita <tomita@cinet.co.jp> + */ +#ifndef _MACH_IO_PORTS_H +#define _MACH_IO_PORTS_H + +/* i8253A PIT registers */ +#define PIT_MODE 0x43 +#define PIT_CH0 0x40 +#define PIT_CH2 0x42 + +/* i8259A PIC registers */ +#define PIC_MASTER_CMD 0x20 +#define PIC_MASTER_IMR 0x21 +#define PIC_MASTER_ISR PIC_MASTER_CMD +#define PIC_MASTER_POLL PIC_MASTER_ISR +#define PIC_MASTER_OCW3 PIC_MASTER_ISR +#define PIC_SLAVE_CMD 0xa0 +#define PIC_SLAVE_IMR 0xa1 + +/* i8259A PIC related value */ +#define PIC_CASCADE_IR 2 +#define MASTER_ICW4_DEFAULT 0x01 +#define SLAVE_ICW4_DEFAULT 0x01 +#define PIC_ICW4_AEOI 2 + +extern void setup_pit_timer(void); + +#endif /* !_MACH_IO_PORTS_H */ diff --git a/include/asm-mips/i8259.h b/include/asm-mips/i8259.h index e88a01607fea..8572a2d90484 100644 --- a/include/asm-mips/i8259.h +++ b/include/asm-mips/i8259.h @@ -37,9 +37,8 @@ extern spinlock_t i8259A_lock; -extern void init_8259A(int auto_eoi); -extern void enable_8259A_irq(unsigned int irq); -extern void disable_8259A_irq(unsigned int irq); +extern int i8259A_irq_pending(unsigned int irq); +extern void make_8259A_irq(unsigned int irq); extern void init_i8259_irqs(void); diff --git a/include/asm-mips/inventory.h b/include/asm-mips/inventory.h index 92d90f75a636..cc88aed23f0f 100644 --- a/include/asm-mips/inventory.h +++ b/include/asm-mips/inventory.h @@ -17,8 +17,8 @@ typedef struct inventory_s { extern int inventory_items; -extern void add_to_inventory (int class, int type, int controller, int unit, int state); -extern int dump_inventory_to_user (void __user *userbuf, int size); +extern void add_to_inventory(int class, int type, int controller, int unit, int state); +extern int dump_inventory_to_user(void __user *userbuf, int size); extern int __init init_inventory(void); #endif /* __ASM_INVENTORY_H */ diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index 7ba92890ea13..2cd8323c8586 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -40,11 +40,11 @@ * hardware. An example use would be for flash memory that's used for * execute in place. */ -# define __raw_ioswabb(a,x) (x) -# define __raw_ioswabw(a,x) (x) -# define __raw_ioswabl(a,x) (x) -# define __raw_ioswabq(a,x) (x) -# define ____raw_ioswabq(a,x) (x) +# define __raw_ioswabb(a, x) (x) +# define __raw_ioswabw(a, x) (x) +# define __raw_ioswabl(a, x) (x) +# define __raw_ioswabq(a, x) (x) +# define ____raw_ioswabq(a, x) (x) /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */ @@ -561,9 +561,9 @@ extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); -#define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start,size) -#define dma_cache_wback(start, size) _dma_cache_wback(start,size) -#define dma_cache_inv(start, size) _dma_cache_inv(start,size) +#define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size) +#define dma_cache_wback(start, size) _dma_cache_wback(start, size) +#define dma_cache_inv(start, size) _dma_cache_inv(start, size) #else /* Sane hardware */ @@ -587,7 +587,7 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); #define __CSR_32_ADJUST 0 #endif -#define csr_out32(v,a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) +#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST)) /* diff --git a/include/asm-mips/ioctl.h b/include/asm-mips/ioctl.h index 2036fcb9f117..85067e248a83 100644 --- a/include/asm-mips/ioctl.h +++ b/include/asm-mips/ioctl.h @@ -54,7 +54,7 @@ #define _IOC_IN 0x80000000 #define _IOC_INOUT (IOC_IN|IOC_OUT) -#define _IOC(dir,type,nr,size) \ +#define _IOC(dir, type, nr, size) \ (((dir) << _IOC_DIRSHIFT) | \ ((type) << _IOC_TYPESHIFT) | \ ((nr) << _IOC_NRSHIFT) | \ @@ -68,13 +68,13 @@ extern unsigned int __invalid_size_argument_for_IOC; sizeof(t) : __invalid_size_argument_for_IOC) /* used to create numbers */ -#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0) -#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size))) -#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) -#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) -#define _IOR_BAD(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size)) -#define _IOW_BAD(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size)) -#define _IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size)) +#define _IO(type, nr) _IOC(_IOC_NONE, (type), (nr), 0) +#define _IOR(type, nr, size) _IOC(_IOC_READ, (type), (nr), (_IOC_TYPECHECK(size))) +#define _IOW(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size))) +#define _IOWR(type, nr, size) _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size))) +#define _IOR_BAD(type, nr, size) _IOC(_IOC_READ, (type), (nr), sizeof(size)) +#define _IOW_BAD(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), sizeof(size)) +#define _IOWR_BAD(type, nr, size) _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), sizeof(size)) /* used to decode them.. */ diff --git a/include/asm-mips/ioctls.h b/include/asm-mips/ioctls.h index 5097cbf183a9..3f04a995ec54 100644 --- a/include/asm-mips/ioctls.h +++ b/include/asm-mips/ioctls.h @@ -77,12 +77,12 @@ #define TIOCSBRK 0x5427 /* BSD compatibility */ #define TIOCCBRK 0x5428 /* BSD compatibility */ #define TIOCGSID 0x7416 /* Return the session ID of FD */ -#define TCGETS2 _IOR('T',0x2A, struct termios2) -#define TCSETS2 _IOW('T',0x2B, struct termios2) -#define TCSETSW2 _IOW('T',0x2C, struct termios2) -#define TCSETSF2 _IOW('T',0x2D, struct termios2) -#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ -#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ +#define TCGETS2 _IOR('T', 0x2A, struct termios2) +#define TCSETS2 _IOW('T', 0x2B, struct termios2) +#define TCSETSW2 _IOW('T', 0x2C, struct termios2) +#define TCSETSF2 _IOW('T', 0x2D, struct termios2) +#define TIOCGPTN _IOR('T', 0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ +#define TIOCSPTLCK _IOW('T', 0x31, int) /* Lock/unlock Pty */ /* I hope the range from 0x5480 on is free ... */ #define TIOCSCTTY 0x5480 /* become controlling tty */ diff --git a/include/asm-mips/ip32/machine.h b/include/asm-mips/ip32/machine.h deleted file mode 100644 index 1b631b8da6f8..000000000000 --- a/include/asm-mips/ip32/machine.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * machine.h -- Machine/group probing for ip32 - * - * Copyright (C) 2001 Keith M Wesolowski - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ -#ifndef _ASM_IP32_MACHINE_H -#define _ASM_IP32_MACHINE_H - - -#ifdef CONFIG_SGI_IP32 - -#define SGI_MACH_O2 0x3201 - -#endif /* CONFIG_SGI_IP32 */ - -#endif /* _ASM_SGI_MACHINE_H */ diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h index 2cb52cf8bd4e..a58f0eecc68f 100644 --- a/include/asm-mips/irq.h +++ b/include/asm-mips/irq.h @@ -46,6 +46,38 @@ static inline void smtc_im_ack_irq(unsigned int irq) #endif /* CONFIG_MIPS_MT_SMTC */ +#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF +#include <linux/cpumask.h> + +extern void plat_set_irq_affinity(unsigned int irq, cpumask_t affinity); +extern void smtc_forward_irq(unsigned int irq); + +/* + * IRQ affinity hook invoked at the beginning of interrupt dispatch + * if option is enabled. + * + * Up through Linux 2.6.22 (at least) cpumask operations are very + * inefficient on MIPS. Initial prototypes of SMTC IRQ affinity + * used a "fast path" per-IRQ-descriptor cache of affinity information + * to reduce latency. As there is a project afoot to optimize the + * cpumask implementations, this version is optimistically assuming + * that cpumask.h macro overhead is reasonable during interrupt dispatch. + */ +#define IRQ_AFFINITY_HOOK(irq) \ +do { \ + if (!cpu_isset(smp_processor_id(), irq_desc[irq].affinity)) { \ + smtc_forward_irq(irq); \ + irq_exit(); \ + return; \ + } \ +} while (0) + +#else /* Not doing SMTC affinity */ + +#define IRQ_AFFINITY_HOOK(irq) do { } while (0) + +#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ + #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP /* @@ -56,13 +88,27 @@ static inline void smtc_im_ack_irq(unsigned int irq) */ #define __DO_IRQ_SMTC_HOOK(irq) \ do { \ + IRQ_AFFINITY_HOOK(irq); \ if (irq_hwmask[irq] & 0x0000ff00) \ write_c0_tccontext(read_c0_tccontext() & \ - ~(irq_hwmask[irq] & 0x0000ff00)); \ + ~(irq_hwmask[irq] & 0x0000ff00)); \ +} while (0) + +#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) \ +do { \ + if (irq_hwmask[irq] & 0x0000ff00) \ + write_c0_tccontext(read_c0_tccontext() & \ + ~(irq_hwmask[irq] & 0x0000ff00)); \ } while (0) + #else -#define __DO_IRQ_SMTC_HOOK(irq) do { } while (0) +#define __DO_IRQ_SMTC_HOOK(irq) \ +do { \ + IRQ_AFFINITY_HOOK(irq); \ +} while (0) +#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) do { } while (0) + #endif /* @@ -81,6 +127,23 @@ do { \ irq_exit(); \ } while (0) +#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF +/* + * To avoid inefficient and in some cases pathological re-checking of + * IRQ affinity, we have this variant that skips the affinity check. + */ + + +#define do_IRQ_no_affinity(irq) \ +do { \ + irq_enter(); \ + __NO_AFFINITY_IRQ_SMTC_HOOK(irq); \ + generic_handle_irq(irq); \ + irq_exit(); \ +} while (0) + +#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ + extern void arch_init_irq(void); extern void spurious_interrupt(void); diff --git a/include/asm-mips/irq_gt641xx.h b/include/asm-mips/irq_gt641xx.h new file mode 100644 index 000000000000..f9a7c3ac2e66 --- /dev/null +++ b/include/asm-mips/irq_gt641xx.h @@ -0,0 +1,60 @@ +/* + * Galileo/Marvell GT641xx IRQ definitions. + * + * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef _ASM_IRQ_GT641XX_H +#define _ASM_IRQ_GT641XX_H + +#ifndef GT641XX_IRQ_BASE +#define GT641XX_IRQ_BASE 8 +#endif + +#define GT641XX_MEMORY_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 1) +#define GT641XX_DMA_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 2) +#define GT641XX_CPU_ACCESS_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 3) +#define GT641XX_DMA0_IRQ (GT641XX_IRQ_BASE + 4) +#define GT641XX_DMA1_IRQ (GT641XX_IRQ_BASE + 5) +#define GT641XX_DMA2_IRQ (GT641XX_IRQ_BASE + 6) +#define GT641XX_DMA3_IRQ (GT641XX_IRQ_BASE + 7) +#define GT641XX_TIMER0_IRQ (GT641XX_IRQ_BASE + 8) +#define GT641XX_TIMER1_IRQ (GT641XX_IRQ_BASE + 9) +#define GT641XX_TIMER2_IRQ (GT641XX_IRQ_BASE + 10) +#define GT641XX_TIMER3_IRQ (GT641XX_IRQ_BASE + 11) +#define GT641XX_PCI_0_MASTER_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 12) +#define GT641XX_PCI_0_SLAVE_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 13) +#define GT641XX_PCI_0_MASTER_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 14) +#define GT641XX_PCI_0_SLAVE_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 15) +#define GT641XX_PCI_0_ADDRESS_ERROR_IRQ (GT641XX_IRQ_BASE + 16) +#define GT641XX_MEMORY_ERROR_IRQ (GT641XX_IRQ_BASE + 17) +#define GT641XX_PCI_0_MASTER_ABORT_IRQ (GT641XX_IRQ_BASE + 18) +#define GT641XX_PCI_0_TARGET_ABORT_IRQ (GT641XX_IRQ_BASE + 19) +#define GT641XX_PCI_0_RETRY_TIMEOUT_IRQ (GT641XX_IRQ_BASE + 20) +#define GT641XX_CPU_INT0_IRQ (GT641XX_IRQ_BASE + 21) +#define GT641XX_CPU_INT1_IRQ (GT641XX_IRQ_BASE + 22) +#define GT641XX_CPU_INT2_IRQ (GT641XX_IRQ_BASE + 23) +#define GT641XX_CPU_INT3_IRQ (GT641XX_IRQ_BASE + 24) +#define GT641XX_CPU_INT4_IRQ (GT641XX_IRQ_BASE + 25) +#define GT641XX_PCI_INT0_IRQ (GT641XX_IRQ_BASE + 26) +#define GT641XX_PCI_INT1_IRQ (GT641XX_IRQ_BASE + 27) +#define GT641XX_PCI_INT2_IRQ (GT641XX_IRQ_BASE + 28) +#define GT641XX_PCI_INT3_IRQ (GT641XX_IRQ_BASE + 29) + +extern void gt641xx_irq_dispatch(void); +extern void gt641xx_irq_init(void); + +#endif /* _ASM_IRQ_GT641XX_H */ diff --git a/include/asm-mips/irqflags.h b/include/asm-mips/irqflags.h index e459fa05db83..881e8866501d 100644 --- a/include/asm-mips/irqflags.h +++ b/include/asm-mips/irqflags.h @@ -16,7 +16,7 @@ #include <linux/compiler.h> #include <asm/hazards.h> -__asm__ ( +__asm__( " .macro raw_local_irq_enable \n" " .set push \n" " .set reorder \n" @@ -65,7 +65,7 @@ static inline void raw_local_irq_enable(void) * * Workaround: mask EXL bit of the result or place a nop before mfc0. */ -__asm__ ( +__asm__( " .macro raw_local_irq_disable\n" " .set push \n" " .set noat \n" @@ -96,7 +96,7 @@ static inline void raw_local_irq_disable(void) : "memory"); } -__asm__ ( +__asm__( " .macro raw_local_save_flags flags \n" " .set push \n" " .set reorder \n" @@ -113,7 +113,7 @@ __asm__ __volatile__( \ "raw_local_save_flags %0" \ : "=r" (x)) -__asm__ ( +__asm__( " .macro raw_local_irq_save result \n" " .set push \n" " .set reorder \n" @@ -145,7 +145,7 @@ __asm__ __volatile__( \ : /* no inputs */ \ : "memory") -__asm__ ( +__asm__( " .macro raw_local_irq_restore flags \n" " .set push \n" " .set noreorder \n" diff --git a/include/asm-mips/jazz.h b/include/asm-mips/jazz.h index 81cbf004fd13..83f449dec95e 100644 --- a/include/asm-mips/jazz.h +++ b/include/asm-mips/jazz.h @@ -185,37 +185,25 @@ typedef struct { #define JAZZ_IO_IRQ_ENABLE 0xe0010002 /* - * JAZZ interrupt enable bits - */ -#define JAZZ_IE_PARALLEL (1 << 0) -#define JAZZ_IE_FLOPPY (1 << 1) -#define JAZZ_IE_SOUND (1 << 2) -#define JAZZ_IE_VIDEO (1 << 3) -#define JAZZ_IE_ETHERNET (1 << 4) -#define JAZZ_IE_SCSI (1 << 5) -#define JAZZ_IE_KEYBOARD (1 << 6) -#define JAZZ_IE_MOUSE (1 << 7) -#define JAZZ_IE_SERIAL1 (1 << 8) -#define JAZZ_IE_SERIAL2 (1 << 9) - -/* * JAZZ Interrupt Level definitions * * This is somewhat broken. For reasons which nobody can remember anymore * we remap the Jazz interrupts to the usual ISA style interrupt numbers. */ -#define JAZZ_PARALLEL_IRQ 16 -#define JAZZ_FLOPPY_IRQ 17 -#define JAZZ_SOUND_IRQ 18 -#define JAZZ_VIDEO_IRQ 19 -#define JAZZ_ETHERNET_IRQ 20 -#define JAZZ_SCSI_IRQ 21 -#define JAZZ_KEYBOARD_IRQ 22 -#define JAZZ_MOUSE_IRQ 23 -#define JAZZ_SERIAL1_IRQ 24 -#define JAZZ_SERIAL2_IRQ 25 - -#define JAZZ_TIMER_IRQ 31 +#define JAZZ_IRQ_START 24 +#define JAZZ_IRQ_END (24 + 9) +#define JAZZ_PARALLEL_IRQ (JAZZ_IRQ_START + 0) +#define JAZZ_FLOPPY_IRQ (JAZZ_IRQ_START + 1) +#define JAZZ_SOUND_IRQ (JAZZ_IRQ_START + 2) +#define JAZZ_VIDEO_IRQ (JAZZ_IRQ_START + 3) +#define JAZZ_ETHERNET_IRQ (JAZZ_IRQ_START + 4) +#define JAZZ_SCSI_IRQ (JAZZ_IRQ_START + 5) +#define JAZZ_KEYBOARD_IRQ (JAZZ_IRQ_START + 6) +#define JAZZ_MOUSE_IRQ (JAZZ_IRQ_START + 7) +#define JAZZ_SERIAL1_IRQ (JAZZ_IRQ_START + 8) +#define JAZZ_SERIAL2_IRQ (JAZZ_IRQ_START + 9) + +#define JAZZ_TIMER_IRQ (MIPS_CPU_IRQ_BASE+6) /* diff --git a/include/asm-mips/jazzdma.h b/include/asm-mips/jazzdma.h index 0a205b77e505..8bb37bba68f0 100644 --- a/include/asm-mips/jazzdma.h +++ b/include/asm-mips/jazzdma.h @@ -7,7 +7,6 @@ /* * Prototypes and macros */ -extern void vdma_init(void); extern unsigned long vdma_alloc(unsigned long paddr, unsigned long size); extern int vdma_free(unsigned long laddr); extern int vdma_remap(unsigned long laddr, unsigned long paddr, diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h index 4be2f25f70dd..211bcf47fffb 100644 --- a/include/asm-mips/jmr3927/tx3927.h +++ b/include/asm-mips/jmr3927/tx3927.h @@ -53,23 +53,23 @@ struct tx3927_dma_reg { #include <asm/byteorder.h> #ifdef __BIG_ENDIAN -#define endian_def_s2(e1,e2) \ - volatile unsigned short e1,e2 -#define endian_def_sb2(e1,e2,e3) \ - volatile unsigned short e1;volatile unsigned char e2,e3 -#define endian_def_b2s(e1,e2,e3) \ - volatile unsigned char e1,e2;volatile unsigned short e3 -#define endian_def_b4(e1,e2,e3,e4) \ - volatile unsigned char e1,e2,e3,e4 +#define endian_def_s2(e1, e2) \ + volatile unsigned short e1, e2 +#define endian_def_sb2(e1, e2, e3) \ + volatile unsigned short e1;volatile unsigned char e2, e3 +#define endian_def_b2s(e1, e2, e3) \ + volatile unsigned char e1, e2;volatile unsigned short e3 +#define endian_def_b4(e1, e2, e3, e4) \ + volatile unsigned char e1, e2, e3, e4 #else -#define endian_def_s2(e1,e2) \ - volatile unsigned short e2,e1 -#define endian_def_sb2(e1,e2,e3) \ - volatile unsigned char e3,e2;volatile unsigned short e1 -#define endian_def_b2s(e1,e2,e3) \ - volatile unsigned short e3;volatile unsigned char e2,e1 -#define endian_def_b4(e1,e2,e3,e4) \ - volatile unsigned char e4,e3,e2,e1 +#define endian_def_s2(e1, e2) \ + volatile unsigned short e2, e1 +#define endian_def_sb2(e1, e2, e3) \ + volatile unsigned char e3, e2;volatile unsigned short e1 +#define endian_def_b2s(e1, e2, e3) \ + volatile unsigned short e3;volatile unsigned char e2, e1 +#define endian_def_b4(e1, e2, e3, e4) \ + volatile unsigned char e4, e3, e2, e1 #endif struct tx3927_pcic_reg { diff --git a/include/asm-mips/lasat/ds1603.h b/include/asm-mips/lasat/ds1603.h new file mode 100644 index 000000000000..edcd7544b358 --- /dev/null +++ b/include/asm-mips/lasat/ds1603.h @@ -0,0 +1,18 @@ +#include <asm/addrspace.h> + +/* Lasat 100 */ +#define DS1603_REG_100 (KSEG1ADDR(0x1c810000)) +#define DS1603_RST_100 (1 << 2) +#define DS1603_CLK_100 (1 << 0) +#define DS1603_DATA_SHIFT_100 1 +#define DS1603_DATA_100 (1 << DS1603_DATA_SHIFT_100) + +/* Lasat 200 */ +#define DS1603_REG_200 (KSEG1ADDR(0x11000000)) +#define DS1603_RST_200 (1 << 3) +#define DS1603_CLK_200 (1 << 4) +#define DS1603_DATA_200 (1 << 5) + +#define DS1603_DATA_REG_200 (DS1603_REG_200 + 0x10000) +#define DS1603_DATA_READ_SHIFT_200 9 +#define DS1603_DATA_READ_200 (1 << DS1603_DATA_READ_SHIFT_200) diff --git a/include/asm-mips/lasat/eeprom.h b/include/asm-mips/lasat/eeprom.h new file mode 100644 index 000000000000..3dac203697fa --- /dev/null +++ b/include/asm-mips/lasat/eeprom.h @@ -0,0 +1,17 @@ +#include <asm/addrspace.h> + +/* lasat 100 */ +#define AT93C_REG_100 KSEG1ADDR(0x1c810000) +#define AT93C_RDATA_REG_100 AT93C_REG_100 +#define AT93C_RDATA_SHIFT_100 4 +#define AT93C_WDATA_SHIFT_100 4 +#define AT93C_CS_M_100 (1 << 5) +#define AT93C_CLK_M_100 (1 << 3) + +/* lasat 200 */ +#define AT93C_REG_200 KSEG1ADDR(0x11000000) +#define AT93C_RDATA_REG_200 (AT93C_REG_200+0x10000) +#define AT93C_RDATA_SHIFT_200 8 +#define AT93C_WDATA_SHIFT_200 2 +#define AT93C_CS_M_200 (1 << 0) +#define AT93C_CLK_M_200 (1 << 1) diff --git a/include/asm-mips/lasat/head.h b/include/asm-mips/lasat/head.h new file mode 100644 index 000000000000..f5589f31a197 --- /dev/null +++ b/include/asm-mips/lasat/head.h @@ -0,0 +1,22 @@ +/* + * Image header stuff + */ +#ifndef _HEAD_H +#define _HEAD_H + +#define LASAT_K_MAGIC0_VAL 0xfedeabba +#define LASAT_K_MAGIC1_VAL 0x00bedead + +#ifndef _LANGUAGE_ASSEMBLY +#include <linux/types.h> +struct bootloader_header { + u32 magic[2]; + u32 version; + u32 image_start; + u32 image_size; + u32 kernel_start; + u32 kernel_entry; +}; +#endif + +#endif /* _HEAD_H */ diff --git a/include/asm-mips/lasat/lasat.h b/include/asm-mips/lasat/lasat.h new file mode 100644 index 000000000000..ea04d9262edc --- /dev/null +++ b/include/asm-mips/lasat/lasat.h @@ -0,0 +1,256 @@ +/* + * lasat.h + * + * Thomas Horsten <thh@lasat.com> + * Copyright (C) 2000 LASAT Networks A/S. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Configuration for LASAT boards, loads the appropriate include files. + */ +#ifndef _LASAT_H +#define _LASAT_H + +#ifndef _LANGUAGE_ASSEMBLY + +extern struct lasat_misc { + volatile u32 *reset_reg; + volatile u32 *flash_wp_reg; + u32 flash_wp_bit; +} *lasat_misc; + +enum lasat_mtdparts { + LASAT_MTD_BOOTLOADER, + LASAT_MTD_SERVICE, + LASAT_MTD_NORMAL, + LASAT_MTD_CONFIG, + LASAT_MTD_FS, + LASAT_MTD_LAST +}; + +/* + * The format of the data record in the EEPROM. + * See Documentation/LASAT/eeprom.txt for a detailed description + * of the fields in this struct, and the LASAT Hardware Configuration + * field specification for a detailed description of the config + * field. + */ +#include <linux/types.h> + +#define LASAT_EEPROM_VERSION 7 +struct lasat_eeprom_struct { + unsigned int version; + unsigned int cfg[3]; + unsigned char hwaddr[6]; + unsigned char print_partno[12]; + unsigned char term0; + unsigned char print_serial[14]; + unsigned char term1; + unsigned char prod_partno[12]; + unsigned char term2; + unsigned char prod_serial[14]; + unsigned char term3; + unsigned char passwd_hash[16]; + unsigned char pwdnull; + unsigned char vendid; + unsigned char ts_ref; + unsigned char ts_signoff; + unsigned char reserved[11]; + unsigned char debugaccess; + unsigned short prid; + unsigned int serviceflag; + unsigned int ipaddr; + unsigned int netmask; + unsigned int crc32; +}; + +struct lasat_eeprom_struct_pre7 { + unsigned int version; + unsigned int flags[3]; + unsigned char hwaddr0[6]; + unsigned char hwaddr1[6]; + unsigned char print_partno[9]; + unsigned char term0; + unsigned char print_serial[14]; + unsigned char term1; + unsigned char prod_partno[9]; + unsigned char term2; + unsigned char prod_serial[14]; + unsigned char term3; + unsigned char passwd_hash[24]; + unsigned char pwdnull; + unsigned char vendor; + unsigned char ts_ref; + unsigned char ts_signoff; + unsigned char reserved[6]; + unsigned int writecount; + unsigned int ipaddr; + unsigned int netmask; + unsigned int crc32; +}; + +/* Configuration descriptor encoding - see the doc for details */ + +#define LASAT_W0_DSCTYPE(v) (((v)) & 0xf) +#define LASAT_W0_BMID(v) (((v) >> 0x04) & 0xf) +#define LASAT_W0_CPUTYPE(v) (((v) >> 0x08) & 0xf) +#define LASAT_W0_BUSSPEED(v) (((v) >> 0x0c) & 0xf) +#define LASAT_W0_CPUCLK(v) (((v) >> 0x10) & 0xf) +#define LASAT_W0_SDRAMBANKSZ(v) (((v) >> 0x14) & 0xf) +#define LASAT_W0_SDRAMBANKS(v) (((v) >> 0x18) & 0xf) +#define LASAT_W0_L2CACHE(v) (((v) >> 0x1c) & 0xf) + +#define LASAT_W1_EDHAC(v) (((v)) & 0xf) +#define LASAT_W1_HIFN(v) (((v) >> 0x04) & 0x1) +#define LASAT_W1_ISDN(v) (((v) >> 0x05) & 0x1) +#define LASAT_W1_IDE(v) (((v) >> 0x06) & 0x1) +#define LASAT_W1_HDLC(v) (((v) >> 0x07) & 0x1) +#define LASAT_W1_USVERSION(v) (((v) >> 0x08) & 0x1) +#define LASAT_W1_4MACS(v) (((v) >> 0x09) & 0x1) +#define LASAT_W1_EXTSERIAL(v) (((v) >> 0x0a) & 0x1) +#define LASAT_W1_FLASHSIZE(v) (((v) >> 0x0c) & 0xf) +#define LASAT_W1_PCISLOTS(v) (((v) >> 0x10) & 0xf) +#define LASAT_W1_PCI1OPT(v) (((v) >> 0x14) & 0xf) +#define LASAT_W1_PCI2OPT(v) (((v) >> 0x18) & 0xf) +#define LASAT_W1_PCI3OPT(v) (((v) >> 0x1c) & 0xf) + +/* Routines specific to LASAT boards */ + +#define LASAT_BMID_MASQUERADE2 0 +#define LASAT_BMID_MASQUERADEPRO 1 +#define LASAT_BMID_SAFEPIPE25 2 +#define LASAT_BMID_SAFEPIPE50 3 +#define LASAT_BMID_SAFEPIPE100 4 +#define LASAT_BMID_SAFEPIPE5000 5 +#define LASAT_BMID_SAFEPIPE7000 6 +#define LASAT_BMID_SAFEPIPE1000 7 +#if 0 +#define LASAT_BMID_SAFEPIPE30 7 +#define LASAT_BMID_SAFEPIPE5100 8 +#define LASAT_BMID_SAFEPIPE7100 9 +#endif +#define LASAT_BMID_UNKNOWN 0xf +#define LASAT_MAX_BMID_NAMES 9 /* no larger than 15! */ + +#define LASAT_HAS_EDHAC (1 << 0) +#define LASAT_EDHAC_FAST (1 << 1) +#define LASAT_HAS_EADI (1 << 2) +#define LASAT_HAS_HIFN (1 << 3) +#define LASAT_HAS_ISDN (1 << 4) +#define LASAT_HAS_LEASEDLINE_IF (1 << 5) +#define LASAT_HAS_HDC (1 << 6) + +#define LASAT_PRID_MASQUERADE2 0 +#define LASAT_PRID_MASQUERADEPRO 1 +#define LASAT_PRID_SAFEPIPE25 2 +#define LASAT_PRID_SAFEPIPE50 3 +#define LASAT_PRID_SAFEPIPE100 4 +#define LASAT_PRID_SAFEPIPE5000 5 +#define LASAT_PRID_SAFEPIPE7000 6 +#define LASAT_PRID_SAFEPIPE30 7 +#define LASAT_PRID_SAFEPIPE5100 8 +#define LASAT_PRID_SAFEPIPE7100 9 + +#define LASAT_PRID_SAFEPIPE1110 10 +#define LASAT_PRID_SAFEPIPE3020 11 +#define LASAT_PRID_SAFEPIPE3030 12 +#define LASAT_PRID_SAFEPIPE5020 13 +#define LASAT_PRID_SAFEPIPE5030 14 +#define LASAT_PRID_SAFEPIPE1120 15 +#define LASAT_PRID_SAFEPIPE1130 16 +#define LASAT_PRID_SAFEPIPE6010 17 +#define LASAT_PRID_SAFEPIPE6110 18 +#define LASAT_PRID_SAFEPIPE6210 19 +#define LASAT_PRID_SAFEPIPE1020 20 +#define LASAT_PRID_SAFEPIPE1040 21 +#define LASAT_PRID_SAFEPIPE1060 22 + +struct lasat_info { + unsigned int li_cpu_hz; + unsigned int li_bus_hz; + unsigned int li_bmid; + unsigned int li_memsize; + unsigned int li_flash_size; + unsigned int li_prid; + unsigned char li_bmstr[16]; + unsigned char li_namestr[32]; + unsigned char li_typestr[16]; + /* Info on the Flash layout */ + unsigned int li_flash_base; + unsigned long li_flashpart_base[LASAT_MTD_LAST]; + unsigned long li_flashpart_size[LASAT_MTD_LAST]; + struct lasat_eeprom_struct li_eeprom_info; + unsigned int li_eeprom_upgrade_version; + unsigned int li_debugaccess; +}; + +extern struct lasat_info lasat_board_info; + +static inline unsigned long lasat_flash_partition_start(int partno) +{ + if (partno < 0 || partno >= LASAT_MTD_LAST) + return 0; + + return lasat_board_info.li_flashpart_base[partno]; +} + +static inline unsigned long lasat_flash_partition_size(int partno) +{ + if (partno < 0 || partno >= LASAT_MTD_LAST) + return 0; + + return lasat_board_info.li_flashpart_size[partno]; +} + +/* Called from setup() to initialize the global board_info struct */ +extern int lasat_init_board_info(void); + +/* Write the modified EEPROM info struct */ +extern void lasat_write_eeprom_info(void); + +#define N_MACHTYPES 2 +/* for calibration of delays */ + +/* the lasat_ndelay function is necessary because it is used at an + * early stage of the boot process where ndelay is not calibrated. + * It is used for the bit-banging rtc and eeprom drivers */ + +#include <linux/delay.h> + +/* calculating with the slowest board with 100 MHz clock */ +#define LASAT_100_DIVIDER 20 +/* All 200's run at 250 MHz clock */ +#define LASAT_200_DIVIDER 8 + +extern unsigned int lasat_ndelay_divider; + +static inline void lasat_ndelay(unsigned int ns) +{ + __delay(ns / lasat_ndelay_divider); +} + +#endif /* !defined (_LANGUAGE_ASSEMBLY) */ + +#define LASAT_SERVICEMODE_MAGIC_1 0xdeadbeef +#define LASAT_SERVICEMODE_MAGIC_2 0xfedeabba + +/* Lasat 100 boards */ +#define LASAT_GT_BASE (KSEG1ADDR(0x14000000)) + +/* Lasat 200 boards */ +#define Vrc5074_PHYS_BASE 0x1fa00000 +#define Vrc5074_BASE (KSEG1ADDR(Vrc5074_PHYS_BASE)) +#define PCI_WINDOW1 0x1a000000 + +#endif /* _LASAT_H */ diff --git a/include/asm-mips/lasat/lasatint.h b/include/asm-mips/lasat/lasatint.h new file mode 100644 index 000000000000..065474feeccc --- /dev/null +++ b/include/asm-mips/lasat/lasatint.h @@ -0,0 +1,12 @@ +#define LASATINT_END 16 + +/* lasat 100 */ +#define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000)) +#define LASAT_INT_MASK_REG_100 (KSEG1ADDR(0x1c890000)) +#define LASATINT_MASK_SHIFT_100 0 + +/* lasat 200 */ +#define LASAT_INT_STATUS_REG_200 (KSEG1ADDR(0x1104003c)) +#define LASAT_INT_MASK_REG_200 (KSEG1ADDR(0x1104003c)) +#define LASATINT_MASK_SHIFT_200 16 + diff --git a/include/asm-mips/lasat/picvue.h b/include/asm-mips/lasat/picvue.h new file mode 100644 index 000000000000..42a492edc40e --- /dev/null +++ b/include/asm-mips/lasat/picvue.h @@ -0,0 +1,15 @@ +/* Lasat 100 */ +#define PVC_REG_100 KSEG1ADDR(0x1c820000) +#define PVC_DATA_SHIFT_100 0 +#define PVC_DATA_M_100 0xFF +#define PVC_E_100 (1 << 8) +#define PVC_RW_100 (1 << 9) +#define PVC_RS_100 (1 << 10) + +/* Lasat 200 */ +#define PVC_REG_200 KSEG1ADDR(0x11000000) +#define PVC_DATA_SHIFT_200 24 +#define PVC_DATA_M_200 (0xFF << PVC_DATA_SHIFT_200) +#define PVC_E_200 (1 << 16) +#define PVC_RW_200 (1 << 17) +#define PVC_RS_200 (1 << 18) diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h new file mode 100644 index 000000000000..bafe68b10614 --- /dev/null +++ b/include/asm-mips/lasat/serial.h @@ -0,0 +1,13 @@ +#include <asm/lasat/lasat.h> + +/* Lasat 100 boards serial configuration */ +#define LASAT_BASE_BAUD_100 (7372800 / 16) +#define LASAT_UART_REGS_BASE_100 0x1c8b0000 +#define LASAT_UART_REGS_SHIFT_100 2 +#define LASATINT_UART_100 8 + +/* * LASAT 200 boards serial configuration */ +#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12) +#define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300) +#define LASAT_UART_REGS_SHIFT_200 3 +#define LASATINT_UART_200 13 diff --git a/include/asm-mips/linkage.h b/include/asm-mips/linkage.h index b6185d3cfe68..e9a940d1b0c6 100644 --- a/include/asm-mips/linkage.h +++ b/include/asm-mips/linkage.h @@ -5,4 +5,6 @@ #include <asm/asm.h> #endif +#define __weak __attribute__((weak)) + #endif diff --git a/include/asm-mips/local.h b/include/asm-mips/local.h index f9a5ce5c9af1..f96fd59e0845 100644 --- a/include/asm-mips/local.h +++ b/include/asm-mips/local.h @@ -15,10 +15,10 @@ typedef struct #define LOCAL_INIT(i) { ATOMIC_LONG_INIT(i) } #define local_read(l) atomic_long_read(&(l)->a) -#define local_set(l,i) atomic_long_set(&(l)->a, (i)) +#define local_set(l, i) atomic_long_set(&(l)->a, (i)) -#define local_add(i,l) atomic_long_add((i),(&(l)->a)) -#define local_sub(i,l) atomic_long_sub((i),(&(l)->a)) +#define local_add(i, l) atomic_long_add((i), (&(l)->a)) +#define local_sub(i, l) atomic_long_sub((i), (&(l)->a)) #define local_inc(l) atomic_long_inc(&(l)->a) #define local_dec(l) atomic_long_dec(&(l)->a) @@ -117,7 +117,7 @@ static __inline__ long local_sub_return(long i, local_t * l) #define local_cmpxchg(l, o, n) \ ((long)cmpxchg_local(&((l)->a.counter), (o), (n))) -#define local_xchg(l, n) (xchg_local(&((l)->a.counter),(n))) +#define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n))) /** * local_add_unless - add unless the number is a given value @@ -138,8 +138,8 @@ static __inline__ long local_sub_return(long i, local_t * l) }) #define local_inc_not_zero(l) local_add_unless((l), 1, 0) -#define local_dec_return(l) local_sub_return(1,(l)) -#define local_inc_return(l) local_add_return(1,(l)) +#define local_dec_return(l) local_sub_return(1, (l)) +#define local_inc_return(l) local_add_return(1, (l)) /* * local_sub_and_test - subtract value from variable and test result @@ -150,7 +150,7 @@ static __inline__ long local_sub_return(long i, local_t * l) * true if the result is zero, or false for all * other cases. */ -#define local_sub_and_test(i,l) (local_sub_return((i), (l)) == 0) +#define local_sub_and_test(i, l) (local_sub_return((i), (l)) == 0) /* * local_inc_and_test - increment and test @@ -181,7 +181,7 @@ static __inline__ long local_sub_return(long i, local_t * l) * if the result is negative, or false when * result is greater than or equal to zero. */ -#define local_add_negative(i,l) (local_add_return(i, (l)) < 0) +#define local_add_negative(i, l) (local_add_return(i, (l)) < 0) /* Use these for per-cpu local_t variables: on some archs they are * much more efficient than these naive implementations. Note they take @@ -190,8 +190,8 @@ static __inline__ long local_sub_return(long i, local_t * l) #define __local_inc(l) ((l)->a.counter++) #define __local_dec(l) ((l)->a.counter++) -#define __local_add(i,l) ((l)->a.counter+=(i)) -#define __local_sub(i,l) ((l)->a.counter-=(i)) +#define __local_add(i, l) ((l)->a.counter+=(i)) +#define __local_sub(i, l) ((l)->a.counter-=(i)) /* Need to disable preemption for the cpu local counters otherwise we could still access a variable of a previous CPU in a non atomic way. */ diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index 58fca8a5a9a6..10f613f23c33 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h @@ -951,25 +951,25 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; /* Programmable Counters 0 and 1 */ #define SYS_BASE 0xB1900000 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) - #define SYS_CNTRL_E1S (1<<23) - #define SYS_CNTRL_T1S (1<<20) - #define SYS_CNTRL_M21 (1<<19) - #define SYS_CNTRL_M11 (1<<18) - #define SYS_CNTRL_M01 (1<<17) - #define SYS_CNTRL_C1S (1<<16) - #define SYS_CNTRL_BP (1<<14) - #define SYS_CNTRL_EN1 (1<<13) - #define SYS_CNTRL_BT1 (1<<12) - #define SYS_CNTRL_EN0 (1<<11) - #define SYS_CNTRL_BT0 (1<<10) - #define SYS_CNTRL_E0 (1<<8) - #define SYS_CNTRL_E0S (1<<7) - #define SYS_CNTRL_32S (1<<5) - #define SYS_CNTRL_T0S (1<<4) - #define SYS_CNTRL_M20 (1<<3) - #define SYS_CNTRL_M10 (1<<2) - #define SYS_CNTRL_M00 (1<<1) - #define SYS_CNTRL_C0S (1<<0) +# define SYS_CNTRL_E1S (1<<23) +# define SYS_CNTRL_T1S (1<<20) +# define SYS_CNTRL_M21 (1<<19) +# define SYS_CNTRL_M11 (1<<18) +# define SYS_CNTRL_M01 (1<<17) +# define SYS_CNTRL_C1S (1<<16) +# define SYS_CNTRL_BP (1<<14) +# define SYS_CNTRL_EN1 (1<<13) +# define SYS_CNTRL_BT1 (1<<12) +# define SYS_CNTRL_EN0 (1<<11) +# define SYS_CNTRL_BT0 (1<<10) +# define SYS_CNTRL_E0 (1<<8) +# define SYS_CNTRL_E0S (1<<7) +# define SYS_CNTRL_32S (1<<5) +# define SYS_CNTRL_T0S (1<<4) +# define SYS_CNTRL_M20 (1<<3) +# define SYS_CNTRL_M10 (1<<2) +# define SYS_CNTRL_M00 (1<<1) +# define SYS_CNTRL_C0S (1<<0) /* Programmable Counter 0 Registers */ #define SYS_TOYTRIM (SYS_BASE + 0) @@ -989,34 +989,34 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; /* I2S Controller */ #define I2S_DATA 0xB1000000 - #define I2S_DATA_MASK (0xffffff) +# define I2S_DATA_MASK (0xffffff) #define I2S_CONFIG 0xB1000004 - #define I2S_CONFIG_XU (1<<25) - #define I2S_CONFIG_XO (1<<24) - #define I2S_CONFIG_RU (1<<23) - #define I2S_CONFIG_RO (1<<22) - #define I2S_CONFIG_TR (1<<21) - #define I2S_CONFIG_TE (1<<20) - #define I2S_CONFIG_TF (1<<19) - #define I2S_CONFIG_RR (1<<18) - #define I2S_CONFIG_RE (1<<17) - #define I2S_CONFIG_RF (1<<16) - #define I2S_CONFIG_PD (1<<11) - #define I2S_CONFIG_LB (1<<10) - #define I2S_CONFIG_IC (1<<9) - #define I2S_CONFIG_FM_BIT 7 - #define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) - #define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) - #define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) - #define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) - #define I2S_CONFIG_TN (1<<6) - #define I2S_CONFIG_RN (1<<5) - #define I2S_CONFIG_SZ_BIT 0 - #define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) +# define I2S_CONFIG_XU (1<<25) +# define I2S_CONFIG_XO (1<<24) +# define I2S_CONFIG_RU (1<<23) +# define I2S_CONFIG_RO (1<<22) +# define I2S_CONFIG_TR (1<<21) +# define I2S_CONFIG_TE (1<<20) +# define I2S_CONFIG_TF (1<<19) +# define I2S_CONFIG_RR (1<<18) +# define I2S_CONFIG_RE (1<<17) +# define I2S_CONFIG_RF (1<<16) +# define I2S_CONFIG_PD (1<<11) +# define I2S_CONFIG_LB (1<<10) +# define I2S_CONFIG_IC (1<<9) +# define I2S_CONFIG_FM_BIT 7 +# define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) +# define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) +# define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) +# define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) +# define I2S_CONFIG_TN (1<<6) +# define I2S_CONFIG_RN (1<<5) +# define I2S_CONFIG_SZ_BIT 0 +# define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) #define I2S_CONTROL 0xB1000008 - #define I2S_CONTROL_D (1<<1) - #define I2S_CONTROL_CE (1<<0) +# define I2S_CONTROL_D (1<<1) +# define I2S_CONTROL_CE (1<<0) /* USB Host Controller */ #ifndef USB_OHCI_LEN @@ -1034,38 +1034,38 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define USBD_EP5RD 0xB0200014 #define USBD_INTEN 0xB0200018 #define USBD_INTSTAT 0xB020001C - #define USBDEV_INT_SOF (1<<12) - #define USBDEV_INT_HF_BIT 6 - #define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) - #define USBDEV_INT_CMPLT_BIT 0 - #define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) +# define USBDEV_INT_SOF (1<<12) +# define USBDEV_INT_HF_BIT 6 +# define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) +# define USBDEV_INT_CMPLT_BIT 0 +# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) #define USBD_CONFIG 0xB0200020 #define USBD_EP0CS 0xB0200024 #define USBD_EP2CS 0xB0200028 #define USBD_EP3CS 0xB020002C #define USBD_EP4CS 0xB0200030 #define USBD_EP5CS 0xB0200034 - #define USBDEV_CS_SU (1<<14) - #define USBDEV_CS_NAK (1<<13) - #define USBDEV_CS_ACK (1<<12) - #define USBDEV_CS_BUSY (1<<11) - #define USBDEV_CS_TSIZE_BIT 1 - #define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) - #define USBDEV_CS_STALL (1<<0) +# define USBDEV_CS_SU (1<<14) +# define USBDEV_CS_NAK (1<<13) +# define USBDEV_CS_ACK (1<<12) +# define USBDEV_CS_BUSY (1<<11) +# define USBDEV_CS_TSIZE_BIT 1 +# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) +# define USBDEV_CS_STALL (1<<0) #define USBD_EP0RDSTAT 0xB0200040 #define USBD_EP0WRSTAT 0xB0200044 #define USBD_EP2WRSTAT 0xB0200048 #define USBD_EP3WRSTAT 0xB020004C #define USBD_EP4RDSTAT 0xB0200050 #define USBD_EP5RDSTAT 0xB0200054 - #define USBDEV_FSTAT_FLUSH (1<<6) - #define USBDEV_FSTAT_UF (1<<5) - #define USBDEV_FSTAT_OF (1<<4) - #define USBDEV_FSTAT_FCNT_BIT 0 - #define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) +# define USBDEV_FSTAT_FLUSH (1<<6) +# define USBDEV_FSTAT_UF (1<<5) +# define USBDEV_FSTAT_OF (1<<4) +# define USBDEV_FSTAT_FCNT_BIT 0 +# define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) #define USBD_ENABLE 0xB0200058 - #define USBDEV_ENABLE (1<<1) - #define USBDEV_CE (1<<0) +# define USBDEV_ENABLE (1<<1) +# define USBDEV_CE (1<<0) #endif /* !CONFIG_SOC_AU1200 */ @@ -1073,55 +1073,55 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; /* 4 byte offsets from AU1000_ETH_BASE */ #define MAC_CONTROL 0x0 - #define MAC_RX_ENABLE (1<<2) - #define MAC_TX_ENABLE (1<<3) - #define MAC_DEF_CHECK (1<<5) - #define MAC_SET_BL(X) (((X)&0x3)<<6) - #define MAC_AUTO_PAD (1<<8) - #define MAC_DISABLE_RETRY (1<<10) - #define MAC_DISABLE_BCAST (1<<11) - #define MAC_LATE_COL (1<<12) - #define MAC_HASH_MODE (1<<13) - #define MAC_HASH_ONLY (1<<15) - #define MAC_PASS_ALL (1<<16) - #define MAC_INVERSE_FILTER (1<<17) - #define MAC_PROMISCUOUS (1<<18) - #define MAC_PASS_ALL_MULTI (1<<19) - #define MAC_FULL_DUPLEX (1<<20) - #define MAC_NORMAL_MODE 0 - #define MAC_INT_LOOPBACK (1<<21) - #define MAC_EXT_LOOPBACK (1<<22) - #define MAC_DISABLE_RX_OWN (1<<23) - #define MAC_BIG_ENDIAN (1<<30) - #define MAC_RX_ALL (1<<31) +# define MAC_RX_ENABLE (1<<2) +# define MAC_TX_ENABLE (1<<3) +# define MAC_DEF_CHECK (1<<5) +# define MAC_SET_BL(X) (((X)&0x3)<<6) +# define MAC_AUTO_PAD (1<<8) +# define MAC_DISABLE_RETRY (1<<10) +# define MAC_DISABLE_BCAST (1<<11) +# define MAC_LATE_COL (1<<12) +# define MAC_HASH_MODE (1<<13) +# define MAC_HASH_ONLY (1<<15) +# define MAC_PASS_ALL (1<<16) +# define MAC_INVERSE_FILTER (1<<17) +# define MAC_PROMISCUOUS (1<<18) +# define MAC_PASS_ALL_MULTI (1<<19) +# define MAC_FULL_DUPLEX (1<<20) +# define MAC_NORMAL_MODE 0 +# define MAC_INT_LOOPBACK (1<<21) +# define MAC_EXT_LOOPBACK (1<<22) +# define MAC_DISABLE_RX_OWN (1<<23) +# define MAC_BIG_ENDIAN (1<<30) +# define MAC_RX_ALL (1<<31) #define MAC_ADDRESS_HIGH 0x4 #define MAC_ADDRESS_LOW 0x8 #define MAC_MCAST_HIGH 0xC #define MAC_MCAST_LOW 0x10 #define MAC_MII_CNTRL 0x14 - #define MAC_MII_BUSY (1<<0) - #define MAC_MII_READ 0 - #define MAC_MII_WRITE (1<<1) - #define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6) - #define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11) +# define MAC_MII_BUSY (1<<0) +# define MAC_MII_READ 0 +# define MAC_MII_WRITE (1<<1) +# define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6) +# define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11) #define MAC_MII_DATA 0x18 #define MAC_FLOW_CNTRL 0x1C - #define MAC_FLOW_CNTRL_BUSY (1<<0) - #define MAC_FLOW_CNTRL_ENABLE (1<<1) - #define MAC_PASS_CONTROL (1<<2) - #define MAC_SET_PAUSE(X) (((X)&0xffff)<<16) +# define MAC_FLOW_CNTRL_BUSY (1<<0) +# define MAC_FLOW_CNTRL_ENABLE (1<<1) +# define MAC_PASS_CONTROL (1<<2) +# define MAC_SET_PAUSE(X) (((X)&0xffff)<<16) #define MAC_VLAN1_TAG 0x20 #define MAC_VLAN2_TAG 0x24 /* Ethernet Controller Enable */ - #define MAC_EN_CLOCK_ENABLE (1<<0) - #define MAC_EN_RESET0 (1<<1) - #define MAC_EN_TOSS (0<<2) - #define MAC_EN_CACHEABLE (1<<3) - #define MAC_EN_RESET1 (1<<4) - #define MAC_EN_RESET2 (1<<5) - #define MAC_DMA_RESET (1<<6) +# define MAC_EN_CLOCK_ENABLE (1<<0) +# define MAC_EN_RESET0 (1<<1) +# define MAC_EN_TOSS (0<<2) +# define MAC_EN_CACHEABLE (1<<3) +# define MAC_EN_RESET1 (1<<4) +# define MAC_EN_RESET2 (1<<5) +# define MAC_DMA_RESET (1<<6) /* Ethernet Controller DMA Channels */ @@ -1129,22 +1129,22 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define MAC1_TX_DMA_ADDR 0xB4004200 /* offsets from MAC_TX_RING_ADDR address */ #define MAC_TX_BUFF0_STATUS 0x0 - #define TX_FRAME_ABORTED (1<<0) - #define TX_JAB_TIMEOUT (1<<1) - #define TX_NO_CARRIER (1<<2) - #define TX_LOSS_CARRIER (1<<3) - #define TX_EXC_DEF (1<<4) - #define TX_LATE_COLL_ABORT (1<<5) - #define TX_EXC_COLL (1<<6) - #define TX_UNDERRUN (1<<7) - #define TX_DEFERRED (1<<8) - #define TX_LATE_COLL (1<<9) - #define TX_COLL_CNT_MASK (0xF<<10) - #define TX_PKT_RETRY (1<<31) +# define TX_FRAME_ABORTED (1<<0) +# define TX_JAB_TIMEOUT (1<<1) +# define TX_NO_CARRIER (1<<2) +# define TX_LOSS_CARRIER (1<<3) +# define TX_EXC_DEF (1<<4) +# define TX_LATE_COLL_ABORT (1<<5) +# define TX_EXC_COLL (1<<6) +# define TX_UNDERRUN (1<<7) +# define TX_DEFERRED (1<<8) +# define TX_LATE_COLL (1<<9) +# define TX_COLL_CNT_MASK (0xF<<10) +# define TX_PKT_RETRY (1<<31) #define MAC_TX_BUFF0_ADDR 0x4 - #define TX_DMA_ENABLE (1<<0) - #define TX_T_DONE (1<<1) - #define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) +# define TX_DMA_ENABLE (1<<0) +# define TX_T_DONE (1<<1) +# define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) #define MAC_TX_BUFF0_LEN 0x8 #define MAC_TX_BUFF1_STATUS 0x10 #define MAC_TX_BUFF1_ADDR 0x14 @@ -1160,34 +1160,34 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define MAC1_RX_DMA_ADDR 0xB4004300 /* offsets from MAC_RX_RING_ADDR */ #define MAC_RX_BUFF0_STATUS 0x0 - #define RX_FRAME_LEN_MASK 0x3fff - #define RX_WDOG_TIMER (1<<14) - #define RX_RUNT (1<<15) - #define RX_OVERLEN (1<<16) - #define RX_COLL (1<<17) - #define RX_ETHER (1<<18) - #define RX_MII_ERROR (1<<19) - #define RX_DRIBBLING (1<<20) - #define RX_CRC_ERROR (1<<21) - #define RX_VLAN1 (1<<22) - #define RX_VLAN2 (1<<23) - #define RX_LEN_ERROR (1<<24) - #define RX_CNTRL_FRAME (1<<25) - #define RX_U_CNTRL_FRAME (1<<26) - #define RX_MCAST_FRAME (1<<27) - #define RX_BCAST_FRAME (1<<28) - #define RX_FILTER_FAIL (1<<29) - #define RX_PACKET_FILTER (1<<30) - #define RX_MISSED_FRAME (1<<31) - - #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ +# define RX_FRAME_LEN_MASK 0x3fff +# define RX_WDOG_TIMER (1<<14) +# define RX_RUNT (1<<15) +# define RX_OVERLEN (1<<16) +# define RX_COLL (1<<17) +# define RX_ETHER (1<<18) +# define RX_MII_ERROR (1<<19) +# define RX_DRIBBLING (1<<20) +# define RX_CRC_ERROR (1<<21) +# define RX_VLAN1 (1<<22) +# define RX_VLAN2 (1<<23) +# define RX_LEN_ERROR (1<<24) +# define RX_CNTRL_FRAME (1<<25) +# define RX_U_CNTRL_FRAME (1<<26) +# define RX_MCAST_FRAME (1<<27) +# define RX_BCAST_FRAME (1<<28) +# define RX_FILTER_FAIL (1<<29) +# define RX_PACKET_FILTER (1<<30) +# define RX_MISSED_FRAME (1<<31) + +# define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) #define MAC_RX_BUFF0_ADDR 0x4 - #define RX_DMA_ENABLE (1<<0) - #define RX_T_DONE (1<<1) - #define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) - #define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0) +# define RX_DMA_ENABLE (1<<0) +# define RX_T_DONE (1<<1) +# define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) +# define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0) #define MAC_RX_BUFF1_STATUS 0x10 #define MAC_RX_BUFF1_ADDR 0x14 #define MAC_RX_BUFF2_STATUS 0x20 @@ -1298,44 +1298,44 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; /* SSIO */ #define SSI0_STATUS 0xB1600000 - #define SSI_STATUS_BF (1<<4) - #define SSI_STATUS_OF (1<<3) - #define SSI_STATUS_UF (1<<2) - #define SSI_STATUS_D (1<<1) - #define SSI_STATUS_B (1<<0) +# define SSI_STATUS_BF (1<<4) +# define SSI_STATUS_OF (1<<3) +# define SSI_STATUS_UF (1<<2) +# define SSI_STATUS_D (1<<1) +# define SSI_STATUS_B (1<<0) #define SSI0_INT 0xB1600004 - #define SSI_INT_OI (1<<3) - #define SSI_INT_UI (1<<2) - #define SSI_INT_DI (1<<1) +# define SSI_INT_OI (1<<3) +# define SSI_INT_UI (1<<2) +# define SSI_INT_DI (1<<1) #define SSI0_INT_ENABLE 0xB1600008 - #define SSI_INTE_OIE (1<<3) - #define SSI_INTE_UIE (1<<2) - #define SSI_INTE_DIE (1<<1) +# define SSI_INTE_OIE (1<<3) +# define SSI_INTE_UIE (1<<2) +# define SSI_INTE_DIE (1<<1) #define SSI0_CONFIG 0xB1600020 - #define SSI_CONFIG_AO (1<<24) - #define SSI_CONFIG_DO (1<<23) - #define SSI_CONFIG_ALEN_BIT 20 - #define SSI_CONFIG_ALEN_MASK (0x7<<20) - #define SSI_CONFIG_DLEN_BIT 16 - #define SSI_CONFIG_DLEN_MASK (0x7<<16) - #define SSI_CONFIG_DD (1<<11) - #define SSI_CONFIG_AD (1<<10) - #define SSI_CONFIG_BM_BIT 8 - #define SSI_CONFIG_BM_MASK (0x3<<8) - #define SSI_CONFIG_CE (1<<7) - #define SSI_CONFIG_DP (1<<6) - #define SSI_CONFIG_DL (1<<5) - #define SSI_CONFIG_EP (1<<4) +# define SSI_CONFIG_AO (1<<24) +# define SSI_CONFIG_DO (1<<23) +# define SSI_CONFIG_ALEN_BIT 20 +# define SSI_CONFIG_ALEN_MASK (0x7<<20) +# define SSI_CONFIG_DLEN_BIT 16 +# define SSI_CONFIG_DLEN_MASK (0x7<<16) +# define SSI_CONFIG_DD (1<<11) +# define SSI_CONFIG_AD (1<<10) +# define SSI_CONFIG_BM_BIT 8 +# define SSI_CONFIG_BM_MASK (0x3<<8) +# define SSI_CONFIG_CE (1<<7) +# define SSI_CONFIG_DP (1<<6) +# define SSI_CONFIG_DL (1<<5) +# define SSI_CONFIG_EP (1<<4) #define SSI0_ADATA 0xB1600024 - #define SSI_AD_D (1<<24) - #define SSI_AD_ADDR_BIT 16 - #define SSI_AD_ADDR_MASK (0xff<<16) - #define SSI_AD_DATA_BIT 0 - #define SSI_AD_DATA_MASK (0xfff<<0) +# define SSI_AD_D (1<<24) +# define SSI_AD_ADDR_BIT 16 +# define SSI_AD_ADDR_MASK (0xff<<16) +# define SSI_AD_DATA_BIT 0 +# define SSI_AD_DATA_MASK (0xfff<<0) #define SSI0_CLKDIV 0xB1600028 #define SSI0_CONTROL 0xB1600100 - #define SSI_CONTROL_CD (1<<1) - #define SSI_CONTROL_E (1<<0) +# define SSI_CONTROL_CD (1<<1) +# define SSI_CONTROL_E (1<<0) /* SSI1 */ #define SSI1_STATUS 0xB1680000 @@ -1401,75 +1401,75 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define IR_RING_ADDR_CMPR (IRDA_BASE+0x14) #define IR_INT_CLEAR (IRDA_BASE+0x18) #define IR_CONFIG_1 (IRDA_BASE+0x20) - #define IR_RX_INVERT_LED (1<<0) - #define IR_TX_INVERT_LED (1<<1) - #define IR_ST (1<<2) - #define IR_SF (1<<3) - #define IR_SIR (1<<4) - #define IR_MIR (1<<5) - #define IR_FIR (1<<6) - #define IR_16CRC (1<<7) - #define IR_TD (1<<8) - #define IR_RX_ALL (1<<9) - #define IR_DMA_ENABLE (1<<10) - #define IR_RX_ENABLE (1<<11) - #define IR_TX_ENABLE (1<<12) - #define IR_LOOPBACK (1<<14) - #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ +# define IR_RX_INVERT_LED (1<<0) +# define IR_TX_INVERT_LED (1<<1) +# define IR_ST (1<<2) +# define IR_SF (1<<3) +# define IR_SIR (1<<4) +# define IR_MIR (1<<5) +# define IR_FIR (1<<6) +# define IR_16CRC (1<<7) +# define IR_TD (1<<8) +# define IR_RX_ALL (1<<9) +# define IR_DMA_ENABLE (1<<10) +# define IR_RX_ENABLE (1<<11) +# define IR_TX_ENABLE (1<<12) +# define IR_LOOPBACK (1<<14) +# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) #define IR_SIR_FLAGS (IRDA_BASE+0x24) #define IR_ENABLE (IRDA_BASE+0x28) - #define IR_RX_STATUS (1<<9) - #define IR_TX_STATUS (1<<10) +# define IR_RX_STATUS (1<<9) +# define IR_TX_STATUS (1<<10) #define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C) #define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30) #define IR_MAX_PKT_LEN (IRDA_BASE+0x34) #define IR_RX_BYTE_CNT (IRDA_BASE+0x38) #define IR_CONFIG_2 (IRDA_BASE+0x3C) - #define IR_MODE_INV (1<<0) - #define IR_ONE_PIN (1<<1) +# define IR_MODE_INV (1<<0) +# define IR_ONE_PIN (1<<1) #define IR_INTERFACE_CONFIG (IRDA_BASE+0x40) /* GPIO */ #define SYS_PINFUNC 0xB190002C - #define SYS_PF_USB (1<<15) /* 2nd USB device/host */ - #define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ - #define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ - #define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ - #define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ - #define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ - #define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ - #define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ - #define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ - #define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ - #define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ - #define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ - #define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ - #define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ - #define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ - #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ +# define SYS_PF_USB (1<<15) /* 2nd USB device/host */ +# define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ +# define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ +# define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ +# define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ +# define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ +# define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ +# define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ +# define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ +# define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ +# define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ +# define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ +# define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ +# define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ +# define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ +# define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ /* Au1100 Only */ - #define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */ - #define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */ - #define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */ - #define SYS_PF_EX0 (1<<9) /* gpio2/clock */ +# define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */ +# define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */ +# define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */ +# define SYS_PF_EX0 (1<<9) /* gpio2/clock */ /* Au1550 Only. Redefines lots of pins */ - #define SYS_PF_PSC2_MASK (7 << 17) - #define SYS_PF_PSC2_AC97 (0) - #define SYS_PF_PSC2_SPI (0) - #define SYS_PF_PSC2_I2S (1 << 17) - #define SYS_PF_PSC2_SMBUS (3 << 17) - #define SYS_PF_PSC2_GPIO (7 << 17) - #define SYS_PF_PSC3_MASK (7 << 20) - #define SYS_PF_PSC3_AC97 (0) - #define SYS_PF_PSC3_SPI (0) - #define SYS_PF_PSC3_I2S (1 << 20) - #define SYS_PF_PSC3_SMBUS (3 << 20) - #define SYS_PF_PSC3_GPIO (7 << 20) - #define SYS_PF_PSC1_S1 (1 << 1) - #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) +# define SYS_PF_PSC2_MASK (7 << 17) +# define SYS_PF_PSC2_AC97 (0) +# define SYS_PF_PSC2_SPI (0) +# define SYS_PF_PSC2_I2S (1 << 17) +# define SYS_PF_PSC2_SMBUS (3 << 17) +# define SYS_PF_PSC2_GPIO (7 << 17) +# define SYS_PF_PSC3_MASK (7 << 20) +# define SYS_PF_PSC3_AC97 (0) +# define SYS_PF_PSC3_SPI (0) +# define SYS_PF_PSC3_I2S (1 << 20) +# define SYS_PF_PSC3_SMBUS (3 << 20) +# define SYS_PF_PSC3_GPIO (7 << 20) +# define SYS_PF_PSC1_S1 (1 << 1) +# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) /* Au1200 Only */ #ifdef CONFIG_SOC_AU1200 @@ -1530,104 +1530,104 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; /* Clock Controller */ #define SYS_FREQCTRL0 0xB1900020 - #define SYS_FC_FRDIV2_BIT 22 - #define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) - #define SYS_FC_FE2 (1<<21) - #define SYS_FC_FS2 (1<<20) - #define SYS_FC_FRDIV1_BIT 12 - #define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) - #define SYS_FC_FE1 (1<<11) - #define SYS_FC_FS1 (1<<10) - #define SYS_FC_FRDIV0_BIT 2 - #define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) - #define SYS_FC_FE0 (1<<1) - #define SYS_FC_FS0 (1<<0) +# define SYS_FC_FRDIV2_BIT 22 +# define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) +# define SYS_FC_FE2 (1<<21) +# define SYS_FC_FS2 (1<<20) +# define SYS_FC_FRDIV1_BIT 12 +# define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) +# define SYS_FC_FE1 (1<<11) +# define SYS_FC_FS1 (1<<10) +# define SYS_FC_FRDIV0_BIT 2 +# define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) +# define SYS_FC_FE0 (1<<1) +# define SYS_FC_FS0 (1<<0) #define SYS_FREQCTRL1 0xB1900024 - #define SYS_FC_FRDIV5_BIT 22 - #define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) - #define SYS_FC_FE5 (1<<21) - #define SYS_FC_FS5 (1<<20) - #define SYS_FC_FRDIV4_BIT 12 - #define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) - #define SYS_FC_FE4 (1<<11) - #define SYS_FC_FS4 (1<<10) - #define SYS_FC_FRDIV3_BIT 2 - #define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) - #define SYS_FC_FE3 (1<<1) - #define SYS_FC_FS3 (1<<0) +# define SYS_FC_FRDIV5_BIT 22 +# define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) +# define SYS_FC_FE5 (1<<21) +# define SYS_FC_FS5 (1<<20) +# define SYS_FC_FRDIV4_BIT 12 +# define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) +# define SYS_FC_FE4 (1<<11) +# define SYS_FC_FS4 (1<<10) +# define SYS_FC_FRDIV3_BIT 2 +# define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) +# define SYS_FC_FE3 (1<<1) +# define SYS_FC_FS3 (1<<0) #define SYS_CLKSRC 0xB1900028 - #define SYS_CS_ME1_BIT 27 - #define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT) - #define SYS_CS_DE1 (1<<26) - #define SYS_CS_CE1 (1<<25) - #define SYS_CS_ME0_BIT 22 - #define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT) - #define SYS_CS_DE0 (1<<21) - #define SYS_CS_CE0 (1<<20) - #define SYS_CS_MI2_BIT 17 - #define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT) - #define SYS_CS_DI2 (1<<16) - #define SYS_CS_CI2 (1<<15) +# define SYS_CS_ME1_BIT 27 +# define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT) +# define SYS_CS_DE1 (1<<26) +# define SYS_CS_CE1 (1<<25) +# define SYS_CS_ME0_BIT 22 +# define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT) +# define SYS_CS_DE0 (1<<21) +# define SYS_CS_CE0 (1<<20) +# define SYS_CS_MI2_BIT 17 +# define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT) +# define SYS_CS_DI2 (1<<16) +# define SYS_CS_CI2 (1<<15) #ifdef CONFIG_SOC_AU1100 - #define SYS_CS_ML_BIT 7 - #define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT) - #define SYS_CS_DL (1<<6) - #define SYS_CS_CL (1<<5) +# define SYS_CS_ML_BIT 7 +# define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT) +# define SYS_CS_DL (1<<6) +# define SYS_CS_CL (1<<5) #else - #define SYS_CS_MUH_BIT 12 - #define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT) - #define SYS_CS_DUH (1<<11) - #define SYS_CS_CUH (1<<10) - #define SYS_CS_MUD_BIT 7 - #define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT) - #define SYS_CS_DUD (1<<6) - #define SYS_CS_CUD (1<<5) +# define SYS_CS_MUH_BIT 12 +# define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT) +# define SYS_CS_DUH (1<<11) +# define SYS_CS_CUH (1<<10) +# define SYS_CS_MUD_BIT 7 +# define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT) +# define SYS_CS_DUD (1<<6) +# define SYS_CS_CUD (1<<5) #endif - #define SYS_CS_MIR_BIT 2 - #define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT) - #define SYS_CS_DIR (1<<1) - #define SYS_CS_CIR (1<<0) - - #define SYS_CS_MUX_AUX 0x1 - #define SYS_CS_MUX_FQ0 0x2 - #define SYS_CS_MUX_FQ1 0x3 - #define SYS_CS_MUX_FQ2 0x4 - #define SYS_CS_MUX_FQ3 0x5 - #define SYS_CS_MUX_FQ4 0x6 - #define SYS_CS_MUX_FQ5 0x7 +# define SYS_CS_MIR_BIT 2 +# define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT) +# define SYS_CS_DIR (1<<1) +# define SYS_CS_CIR (1<<0) + +# define SYS_CS_MUX_AUX 0x1 +# define SYS_CS_MUX_FQ0 0x2 +# define SYS_CS_MUX_FQ1 0x3 +# define SYS_CS_MUX_FQ2 0x4 +# define SYS_CS_MUX_FQ3 0x5 +# define SYS_CS_MUX_FQ4 0x6 +# define SYS_CS_MUX_FQ5 0x7 #define SYS_CPUPLL 0xB1900060 #define SYS_AUXPLL 0xB1900064 /* AC97 Controller */ #define AC97C_CONFIG 0xB0000000 - #define AC97C_RECV_SLOTS_BIT 13 - #define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) - #define AC97C_XMIT_SLOTS_BIT 3 - #define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) - #define AC97C_SG (1<<2) - #define AC97C_SYNC (1<<1) - #define AC97C_RESET (1<<0) +# define AC97C_RECV_SLOTS_BIT 13 +# define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) +# define AC97C_XMIT_SLOTS_BIT 3 +# define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) +# define AC97C_SG (1<<2) +# define AC97C_SYNC (1<<1) +# define AC97C_RESET (1<<0) #define AC97C_STATUS 0xB0000004 - #define AC97C_XU (1<<11) - #define AC97C_XO (1<<10) - #define AC97C_RU (1<<9) - #define AC97C_RO (1<<8) - #define AC97C_READY (1<<7) - #define AC97C_CP (1<<6) - #define AC97C_TR (1<<5) - #define AC97C_TE (1<<4) - #define AC97C_TF (1<<3) - #define AC97C_RR (1<<2) - #define AC97C_RE (1<<1) - #define AC97C_RF (1<<0) +# define AC97C_XU (1<<11) +# define AC97C_XO (1<<10) +# define AC97C_RU (1<<9) +# define AC97C_RO (1<<8) +# define AC97C_READY (1<<7) +# define AC97C_CP (1<<6) +# define AC97C_TR (1<<5) +# define AC97C_TE (1<<4) +# define AC97C_TF (1<<3) +# define AC97C_RR (1<<2) +# define AC97C_RE (1<<1) +# define AC97C_RF (1<<0) #define AC97C_DATA 0xB0000008 #define AC97C_CMD 0xB000000C - #define AC97C_WD_BIT 16 - #define AC97C_READ (1<<7) - #define AC97C_INDEX_MASK 0x7f +# define AC97C_WD_BIT 16 +# define AC97C_READ (1<<7) +# define AC97C_INDEX_MASK 0x7f #define AC97C_CNTRL 0xB0000010 - #define AC97C_RS (1<<1) - #define AC97C_CE (1<<0) +# define AC97C_RS (1<<1) +# define AC97C_CE (1<<0) /* Secure Digital (SD) Controller */ @@ -1636,12 +1636,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define SD1_XMIT_FIFO 0xB0680000 #define SD1_RECV_FIFO 0xB0680004 -#if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) +#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) /* Au1500 PCI Controller */ #define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) - #define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27)) +# define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27)) #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) diff --git a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h index eeb0c3115b6a..93d507cea518 100644 --- a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h +++ b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h @@ -199,7 +199,7 @@ typedef volatile struct au1xxx_ddma_desc { #define DSCR_CMD0_ALWAYS 31 #define DSCR_NDEV_IDS 32 /* THis macro is used to find/create custom device types */ -#define DSCR_DEV2CUSTOM_ID(x,d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF)) +#define DSCR_DEV2CUSTOM_ID(x, d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF)) #define DSCR_CUSTOM2DEV_ID(x) ((x)&0xFF) @@ -373,14 +373,14 @@ void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp); Some compatibilty macros -- Needed to make changes to API without breaking existing drivers */ -#define au1xxx_dbdma_put_source(chanid,buf,nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE) -#define au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags) -#define put_source_flags(chanid,buf,nbytes,flags) au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags) +#define au1xxx_dbdma_put_source(chanid, buf, nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE) +#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags) +#define put_source_flags(chanid, buf, nbytes, flags) au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) -#define au1xxx_dbdma_put_dest(chanid,buf,nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE) -#define au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags) -#define put_dest_flags(chanid,buf,nbytes,flags) au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags) +#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE) +#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags) +#define put_dest_flags(chanid, buf, nbytes, flags) au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) /* * Flags for the put_source/put_dest functions. diff --git a/include/asm-mips/mach-au1x00/au1xxx_ide.h b/include/asm-mips/mach-au1x00/au1xxx_ide.h index 4663e8b415c9..aef0edbfe4c6 100644 --- a/include/asm-mips/mach-au1x00/au1xxx_ide.h +++ b/include/asm-mips/mach-au1x00/au1xxx_ide.h @@ -136,7 +136,7 @@ void auide_outl(u32 addr, unsigned long port); void auide_outsw(unsigned long port, void *addr, u32 count); void auide_outsl(unsigned long port, void *addr, u32 count); static void auide_tune_drive(ide_drive_t *drive, byte pio); -static int auide_tune_chipset (ide_drive_t *drive, u8 speed); +static int auide_tune_chipset(ide_drive_t *drive, u8 speed); static int auide_ddma_init( _auide_hwif *auide ); static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif); int __init auide_probe(void); diff --git a/include/asm-mips/mach-au1x00/war.h b/include/asm-mips/mach-au1x00/war.h new file mode 100644 index 000000000000..dd57d03d68ba --- /dev/null +++ b/include/asm-mips/mach-au1x00/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_AU1X00_WAR_H +#define __ASM_MIPS_MACH_AU1X00_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_AU1X00_WAR_H */ diff --git a/include/asm-mips/mach-bcm47xx/bcm47xx.h b/include/asm-mips/mach-bcm47xx/bcm47xx.h new file mode 100644 index 000000000000..d008f47a28bd --- /dev/null +++ b/include/asm-mips/mach-bcm47xx/bcm47xx.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef __ASM_BCM47XX_H +#define __ASM_BCM47XX_H + +/* SSB bus */ +extern struct ssb_bus ssb_bcm47xx; + +#endif /* __ASM_BCM47XX_H */ diff --git a/include/asm-mips/mach-bcm47xx/gpio.h b/include/asm-mips/mach-bcm47xx/gpio.h new file mode 100644 index 000000000000..cfc8f4d618ce --- /dev/null +++ b/include/asm-mips/mach-bcm47xx/gpio.h @@ -0,0 +1,59 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net> + */ + +#ifndef __BCM47XX_GPIO_H +#define __BCM47XX_GPIO_H + +#define BCM47XX_EXTIF_GPIO_LINES 5 +#define BCM47XX_CHIPCO_GPIO_LINES 16 + +extern int bcm47xx_gpio_to_irq(unsigned gpio); +extern int bcm47xx_gpio_get_value(unsigned gpio); +extern void bcm47xx_gpio_set_value(unsigned gpio, int value); +extern int bcm47xx_gpio_direction_input(unsigned gpio); +extern int bcm47xx_gpio_direction_output(unsigned gpio, int value); + +static inline int gpio_request(unsigned gpio, const char *label) +{ + return 0; +} + +static inline void gpio_free(unsigned gpio) +{ +} + +static inline int gpio_to_irq(unsigned gpio) +{ + return bcm47xx_gpio_to_irq(gpio); +} + +static inline int gpio_get_value(unsigned gpio) +{ + return bcm47xx_gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + bcm47xx_gpio_set_value(gpio, value); +} + +static inline int gpio_direction_input(unsigned gpio) +{ + return bcm47xx_gpio_direction_input(gpio); +} + +static inline int gpio_direction_output(unsigned gpio, int value) +{ + return bcm47xx_gpio_direction_output(gpio, value); +} + + +/* cansleep wrappers */ +#include <asm-generic/gpio.h> + +#endif /* __BCM47XX_GPIO_H */ diff --git a/include/asm-mips/mach-bcm47xx/war.h b/include/asm-mips/mach-bcm47xx/war.h new file mode 100644 index 000000000000..4a2b7986b582 --- /dev/null +++ b/include/asm-mips/mach-bcm47xx/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_BCM947XX_WAR_H +#define __ASM_MIPS_MACH_BCM947XX_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_BCM947XX_WAR_H */ diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h index 9c9d2b998ca4..a79e7caf3a86 100644 --- a/include/asm-mips/mach-cobalt/cobalt.h +++ b/include/asm-mips/mach-cobalt/cobalt.h @@ -12,71 +12,16 @@ #ifndef __ASM_COBALT_H #define __ASM_COBALT_H -#include <irq.h> - -/* - * i8259 legacy interrupts used on Cobalt: - * - * 8 - RTC - * 9 - PCI - * 14 - IDE0 - * 15 - IDE1 - */ -#define COBALT_QUBE_SLOT_IRQ 9 - -/* - * CPU IRQs are 16 ... 23 - */ -#define COBALT_CPU_IRQ MIPS_CPU_IRQ_BASE - -#define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2) -#define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3) -#define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3) -#define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4) -#define COBALT_ETH1_IRQ (COBALT_CPU_IRQ + 4) -#define COBALT_SERIAL_IRQ (COBALT_CPU_IRQ + 5) -#define COBALT_SCSI_IRQ (COBALT_CPU_IRQ + 5) -#define COBALT_VIA_IRQ (COBALT_CPU_IRQ + 6) /* Chained to VIA ISA bridge */ - /* - * PCI configuration space manifest constants. These are wired into - * the board layout according to the PCI spec to enable the software - * to probe the hardware configuration space in a well defined manner. - * - * The PCI_DEVSHFT() macro transforms these values into numbers - * suitable for passing as the dev parameter to the various - * pcibios_read/write_config routines. + * The Cobalt board ID information. */ -#define COBALT_PCICONF_CPU 0x06 -#define COBALT_PCICONF_ETH0 0x07 -#define COBALT_PCICONF_RAQSCSI 0x08 -#define COBALT_PCICONF_VIA 0x09 -#define COBALT_PCICONF_PCISLOT 0x0A -#define COBALT_PCICONF_ETH1 0x0C - +extern int cobalt_board_id; -/* - * The Cobalt board id information. The boards have an ID number wired - * into the VIA that is available in the high nibble of register 94. - * This register is available in the VIA configuration space through the - * interface routines qube_pcibios_read/write_config. See cobalt/pci.c - */ -#define VIA_COBALT_BRD_ID_REG 0x94 -#define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char) (reg) >> 4) #define COBALT_BRD_ID_QUBE1 0x3 #define COBALT_BRD_ID_RAQ1 0x4 #define COBALT_BRD_ID_QUBE2 0x5 #define COBALT_BRD_ID_RAQ2 0x6 -extern int cobalt_board_id; - -#define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000)) -# define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */ -# define COBALT_LED_BAR_RIGHT (1 << 1) /* Qube */ -# define COBALT_LED_WEB (1 << 2) /* RaQ */ -# define COBALT_LED_POWER_OFF (1 << 3) /* RaQ */ -# define COBALT_LED_RESET 0x0f - #define COBALT_KEY_PORT ((~*(volatile unsigned int *) CKSEG1ADDR(0x1d000000) >> 24) & COBALT_KEY_MASK) # define COBALT_KEY_CLEAR (1 << 1) # define COBALT_KEY_LEFT (1 << 2) @@ -87,6 +32,4 @@ extern int cobalt_board_id; # define COBALT_KEY_SELECT (1 << 7) # define COBALT_KEY_MASK 0xfe -#define COBALT_UART ((volatile unsigned char *) CKSEG1ADDR(0x1c800000)) - #endif /* __ASM_COBALT_H */ diff --git a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h index d38f069d9e95..b3314cf53194 100644 --- a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h +++ b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h @@ -14,7 +14,6 @@ #define cpu_has_3k_cache 0 #define cpu_has_4k_cache 1 #define cpu_has_tx39_cache 0 -#define cpu_has_sb1_cache 0 #define cpu_has_fpu 1 #define cpu_has_32fpr 1 #define cpu_has_counter 1 diff --git a/include/asm-mips/mach-cobalt/irq.h b/include/asm-mips/mach-cobalt/irq.h new file mode 100644 index 000000000000..179d0e850b59 --- /dev/null +++ b/include/asm-mips/mach-cobalt/irq.h @@ -0,0 +1,58 @@ +/* + * Cobalt IRQ definitions. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1997 Cobalt Microserver + * Copyright (C) 1997, 2003 Ralf Baechle + * Copyright (C) 2001-2003 Liam Davies (ldavies@agile.tv) + * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> + */ +#ifndef _ASM_COBALT_IRQ_H +#define _ASM_COBALT_IRQ_H + +/* + * i8259 interrupts used on Cobalt: + * + * 8 - RTC + * 9 - PCI slot + * 14 - IDE0 + * 15 - IDE1(no connector on board) + */ +#define I8259A_IRQ_BASE 0 + +#define PCISLOT_IRQ (I8259A_IRQ_BASE + 9) + +/* + * CPU interrupts used on Cobalt: + * + * 0 - Software interrupt 0 (unused) + * 1 - Software interrupt 0 (unused) + * 2 - cascade GT64111 + * 3 - ethernet or SCSI host controller + * 4 - ethernet + * 5 - 16550 UART + * 6 - cascade i8259 + * 7 - CP0 counter (unused) + */ +#define MIPS_CPU_IRQ_BASE 16 + +#define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2) +#define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3) +#define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3) +#define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4) +#define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4) +#define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5) +#define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5) +#define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6) + + +#define GT641XX_IRQ_BASE 24 + +#include <asm/irq_gt641xx.h> + +#define NR_IRQS (GT641XX_PCI_INT3_IRQ + 1) + +#endif /* _ASM_COBALT_IRQ_H */ diff --git a/include/asm-mips/mach-cobalt/war.h b/include/asm-mips/mach-cobalt/war.h new file mode 100644 index 000000000000..97884fd18ac0 --- /dev/null +++ b/include/asm-mips/mach-cobalt/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_COBALT_WAR_H +#define __ASM_MIPS_MACH_COBALT_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_COBALT_WAR_H */ diff --git a/include/asm-mips/mach-dec/war.h b/include/asm-mips/mach-dec/war.h new file mode 100644 index 000000000000..ca5e2ef909ad --- /dev/null +++ b/include/asm-mips/mach-dec/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_DEC_WAR_H +#define __ASM_MIPS_MACH_DEC_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_DEC_WAR_H */ diff --git a/include/asm-mips/mach-emma2rh/war.h b/include/asm-mips/mach-emma2rh/war.h new file mode 100644 index 000000000000..b660a4c30e6a --- /dev/null +++ b/include/asm-mips/mach-emma2rh/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_EMMA2RH_WAR_H +#define __ASM_MIPS_MACH_EMMA2RH_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_EMMA2RH_WAR_H */ diff --git a/include/asm-mips/mach-excite/cpu-feature-overrides.h b/include/asm-mips/mach-excite/cpu-feature-overrides.h index 07f4322c235d..107104c3cd12 100644 --- a/include/asm-mips/mach-excite/cpu-feature-overrides.h +++ b/include/asm-mips/mach-excite/cpu-feature-overrides.h @@ -34,6 +34,11 @@ #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 +#define cpu_has_mips32r1 0 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + #define cpu_has_inclusive_pcaches 0 #define cpu_dcache_line_size() 32 diff --git a/include/asm-mips/mach-excite/war.h b/include/asm-mips/mach-excite/war.h new file mode 100644 index 000000000000..1f82180c1598 --- /dev/null +++ b/include/asm-mips/mach-excite/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_EXCITE_WAR_H +#define __ASM_MIPS_MACH_EXCITE_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 1 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_EXCITE_WAR_H */ diff --git a/include/asm-mips/mach-generic/mangle-port.h b/include/asm-mips/mach-generic/mangle-port.h index 6e1b0c075de7..f49dc990214b 100644 --- a/include/asm-mips/mach-generic/mangle-port.h +++ b/include/asm-mips/mach-generic/mangle-port.h @@ -27,25 +27,25 @@ */ #if defined(CONFIG_SWAP_IO_SPACE) -# define ioswabb(a,x) (x) -# define __mem_ioswabb(a,x) (x) -# define ioswabw(a,x) le16_to_cpu(x) -# define __mem_ioswabw(a,x) (x) -# define ioswabl(a,x) le32_to_cpu(x) -# define __mem_ioswabl(a,x) (x) -# define ioswabq(a,x) le64_to_cpu(x) -# define __mem_ioswabq(a,x) (x) +# define ioswabb(a, x) (x) +# define __mem_ioswabb(a, x) (x) +# define ioswabw(a, x) le16_to_cpu(x) +# define __mem_ioswabw(a, x) (x) +# define ioswabl(a, x) le32_to_cpu(x) +# define __mem_ioswabl(a, x) (x) +# define ioswabq(a, x) le64_to_cpu(x) +# define __mem_ioswabq(a, x) (x) #else -# define ioswabb(a,x) (x) -# define __mem_ioswabb(a,x) (x) -# define ioswabw(a,x) (x) -# define __mem_ioswabw(a,x) cpu_to_le16(x) -# define ioswabl(a,x) (x) -# define __mem_ioswabl(a,x) cpu_to_le32(x) -# define ioswabq(a,x) (x) -# define __mem_ioswabq(a,x) cpu_to_le32(x) +# define ioswabb(a, x) (x) +# define __mem_ioswabb(a, x) (x) +# define ioswabw(a, x) (x) +# define __mem_ioswabw(a, x) cpu_to_le16(x) +# define ioswabl(a, x) (x) +# define __mem_ioswabl(a, x) cpu_to_le32(x) +# define ioswabq(a, x) (x) +# define __mem_ioswabq(a, x) cpu_to_le32(x) #endif diff --git a/include/asm-mips/mach-ip22/war.h b/include/asm-mips/mach-ip22/war.h new file mode 100644 index 000000000000..a44fa9656a82 --- /dev/null +++ b/include/asm-mips/mach-ip22/war.h @@ -0,0 +1,29 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_IP22_WAR_H +#define __ASM_MIPS_MACH_IP22_WAR_H + +/* + * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors. + */ + +#define R4600_V1_INDEX_ICACHEOP_WAR 1 +#define R4600_V1_HIT_CACHEOP_WAR 1 +#define R4600_V2_HIT_CACHEOP_WAR 1 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_IP22_WAR_H */ diff --git a/include/asm-mips/mach-ip27/irq.h b/include/asm-mips/mach-ip27/irq.h index 25f0c3f39adf..cf4384bfa846 100644 --- a/include/asm-mips/mach-ip27/irq.h +++ b/include/asm-mips/mach-ip27/irq.h @@ -17,4 +17,6 @@ */ #define NR_IRQS 256 +#include_next <irq.h> + #endif /* __ASM_MACH_IP27_IRQ_H */ diff --git a/include/asm-mips/mach-ip27/mangle-port.h b/include/asm-mips/mach-ip27/mangle-port.h index d615312a451a..f6e4912ea062 100644 --- a/include/asm-mips/mach-ip27/mangle-port.h +++ b/include/asm-mips/mach-ip27/mangle-port.h @@ -13,13 +13,13 @@ #define __swizzle_addr_l(port) (port) #define __swizzle_addr_q(port) (port) -# define ioswabb(a,x) (x) -# define __mem_ioswabb(a,x) (x) -# define ioswabw(a,x) (x) -# define __mem_ioswabw(a,x) cpu_to_le16(x) -# define ioswabl(a,x) (x) -# define __mem_ioswabl(a,x) cpu_to_le32(x) -# define ioswabq(a,x) (x) -# define __mem_ioswabq(a,x) cpu_to_le32(x) +# define ioswabb(a, x) (x) +# define __mem_ioswabb(a, x) (x) +# define ioswabw(a, x) (x) +# define __mem_ioswabw(a, x) cpu_to_le16(x) +# define ioswabl(a, x) (x) +# define __mem_ioswabl(a, x) cpu_to_le32(x) +# define ioswabq(a, x) (x) +# define __mem_ioswabq(a, x) cpu_to_le32(x) #endif /* __ASM_MACH_IP27_MANGLE_PORT_H */ diff --git a/include/asm-mips/mach-ip27/topology.h b/include/asm-mips/mach-ip27/topology.h index 61d9be3f3175..372291f53fb9 100644 --- a/include/asm-mips/mach-ip27/topology.h +++ b/include/asm-mips/mach-ip27/topology.h @@ -2,9 +2,27 @@ #define _ASM_MACH_TOPOLOGY_H 1 #include <asm/sn/hub.h> +#include <asm/sn/types.h> #include <asm/mmzone.h> -#define cpu_to_node(cpu) (cpu_data[(cpu)].p_nodeid) +struct cpuinfo_ip27 { +// cpuid_t p_cpuid; /* PROM assigned cpuid */ + cnodeid_t p_nodeid; /* my node ID in compact-id-space */ + nasid_t p_nasid; /* my node ID in numa-as-id-space */ + unsigned char p_slice; /* Physical position on node board */ +#if 0 + unsigned long loops_per_sec; + unsigned long ipi_count; + unsigned long irq_attempt[NR_IRQS]; + unsigned long smp_local_irq_count; + unsigned long prof_multiplier; + unsigned long prof_counter; +#endif +}; + +extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS]; + +#define cpu_to_node(cpu) (sn_cpu_info[(cpu)].p_nodeid) #define parent_node(node) (node) #define node_to_cpumask(node) (hub_data(node)->h_cpus) #define node_to_first_cpu(node) (first_cpu(node_to_cpumask(node))) diff --git a/include/asm-mips/mach-ip27/war.h b/include/asm-mips/mach-ip27/war.h new file mode 100644 index 000000000000..e2ddcc9b1fff --- /dev/null +++ b/include/asm-mips/mach-ip27/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_IP27_WAR_H +#define __ASM_MIPS_MACH_IP27_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 1 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_IP27_WAR_H */ diff --git a/include/asm-mips/mach-ip32/kmalloc.h b/include/asm-mips/mach-ip32/kmalloc.h index f6198a21fba1..b1e0be60f720 100644 --- a/include/asm-mips/mach-ip32/kmalloc.h +++ b/include/asm-mips/mach-ip32/kmalloc.h @@ -2,7 +2,7 @@ #define __ASM_MACH_IP32_KMALLOC_H -#if defined(CONFIG_CPU_R5000) || defined (CONFIG_CPU_RM7000) +#if defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_RM7000) #define ARCH_KMALLOC_MINALIGN 32 #else #define ARCH_KMALLOC_MINALIGN 128 diff --git a/include/asm-mips/mach-ip32/mangle-port.h b/include/asm-mips/mach-ip32/mangle-port.h index 81320eb55324..f1d0f1756a9f 100644 --- a/include/asm-mips/mach-ip32/mangle-port.h +++ b/include/asm-mips/mach-ip32/mangle-port.h @@ -14,13 +14,13 @@ #define __swizzle_addr_l(port) (port) #define __swizzle_addr_q(port) (port) -# define ioswabb(a,x) (x) -# define __mem_ioswabb(a,x) (x) -# define ioswabw(a,x) (x) -# define __mem_ioswabw(a,x) cpu_to_le16(x) -# define ioswabl(a,x) (x) -# define __mem_ioswabl(a,x) cpu_to_le32(x) -# define ioswabq(a,x) (x) -# define __mem_ioswabq(a,x) cpu_to_le32(x) +# define ioswabb(a, x) (x) +# define __mem_ioswabb(a, x) (x) +# define ioswabw(a, x) (x) +# define __mem_ioswabw(a, x) cpu_to_le16(x) +# define ioswabl(a, x) (x) +# define __mem_ioswabl(a, x) cpu_to_le32(x) +# define ioswabq(a, x) (x) +# define __mem_ioswabq(a, x) cpu_to_le32(x) #endif /* __ASM_MACH_IP32_MANGLE_PORT_H */ diff --git a/include/asm-mips/mach-ip32/war.h b/include/asm-mips/mach-ip32/war.h new file mode 100644 index 000000000000..d194056dcd7a --- /dev/null +++ b/include/asm-mips/mach-ip32/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_IP32_WAR_H +#define __ASM_MIPS_MACH_IP32_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_IP32_WAR_H */ diff --git a/include/asm-mips/mach-jazz/mc146818rtc.h b/include/asm-mips/mach-jazz/mc146818rtc.h index f44fdba1998b..987f727afe25 100644 --- a/include/asm-mips/mach-jazz/mc146818rtc.h +++ b/include/asm-mips/mach-jazz/mc146818rtc.h @@ -4,12 +4,15 @@ * for more details. * * Copyright (C) 1998, 2001, 03 by Ralf Baechle + * Copyright (C) 2007 Thomas Bogendoerfer * * RTC routines for Jazz style attached Dallas chip. */ #ifndef __ASM_MACH_JAZZ_MC146818RTC_H #define __ASM_MACH_JAZZ_MC146818RTC_H +#include <linux/delay.h> + #include <asm/io.h> #include <asm/jazz.h> @@ -19,16 +22,17 @@ static inline unsigned char CMOS_READ(unsigned long addr) { outb_p(addr, RTC_PORT(0)); - - return *(char *)JAZZ_RTC_BASE; + return *(volatile char *)JAZZ_RTC_BASE; } static inline void CMOS_WRITE(unsigned char data, unsigned long addr) { outb_p(addr, RTC_PORT(0)); - *(char *)JAZZ_RTC_BASE = data; + *(volatile char *)JAZZ_RTC_BASE = data; } #define RTC_ALWAYS_BCD 0 +#define mc146818_decode_year(year) ((year) + 1980) + #endif /* __ASM_MACH_JAZZ_MC146818RTC_H */ diff --git a/include/asm-mips/mach-jazz/war.h b/include/asm-mips/mach-jazz/war.h new file mode 100644 index 000000000000..6158ee861bfd --- /dev/null +++ b/include/asm-mips/mach-jazz/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_JAZZ_WAR_H +#define __ASM_MIPS_MACH_JAZZ_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_JAZZ_WAR_H */ diff --git a/include/asm-mips/mach-jmr3927/mangle-port.h b/include/asm-mips/mach-jmr3927/mangle-port.h index 501a202631b5..11bffcd1043b 100644 --- a/include/asm-mips/mach-jmr3927/mangle-port.h +++ b/include/asm-mips/mach-jmr3927/mangle-port.h @@ -6,13 +6,13 @@ extern unsigned long __swizzle_addr_b(unsigned long port); #define __swizzle_addr_l(port) (port) #define __swizzle_addr_q(port) (port) -#define ioswabb(a,x) (x) -#define __mem_ioswabb(a,x) (x) -#define ioswabw(a,x) le16_to_cpu(x) -#define __mem_ioswabw(a,x) (x) -#define ioswabl(a,x) le32_to_cpu(x) -#define __mem_ioswabl(a,x) (x) -#define ioswabq(a,x) le64_to_cpu(x) -#define __mem_ioswabq(a,x) (x) +#define ioswabb(a, x) (x) +#define __mem_ioswabb(a, x) (x) +#define ioswabw(a, x) le16_to_cpu(x) +#define __mem_ioswabw(a, x) (x) +#define ioswabl(a, x) le32_to_cpu(x) +#define __mem_ioswabl(a, x) (x) +#define ioswabq(a, x) le64_to_cpu(x) +#define __mem_ioswabq(a, x) (x) #endif /* __ASM_MACH_JMR3927_MANGLE_PORT_H */ diff --git a/include/asm-mips/mach-jmr3927/war.h b/include/asm-mips/mach-jmr3927/war.h new file mode 100644 index 000000000000..1ff55fb3fbcb --- /dev/null +++ b/include/asm-mips/mach-jmr3927/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_JMR3927_WAR_H +#define __ASM_MIPS_MACH_JMR3927_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_JMR3927_WAR_H */ diff --git a/include/asm-mips/mach-lasat/mach-gt64120.h b/include/asm-mips/mach-lasat/mach-gt64120.h new file mode 100644 index 000000000000..1a9ad45cc135 --- /dev/null +++ b/include/asm-mips/mach-lasat/mach-gt64120.h @@ -0,0 +1,27 @@ +/* + * This is a direct copy of the ev96100.h file, with a global + * search and replace. The numbers are the same. + * + * The reason I'm duplicating this is so that the 64120/96100 + * defines won't be confusing in the source code. + */ +#ifndef _ASM_GT64120_LASAT_GT64120_DEP_H +#define _ASM_GT64120_LASAT_GT64120_DEP_H + +/* + * GT64120 config space base address on Lasat 100 + */ +#define GT64120_BASE (KSEG1ADDR(0x14000000)) + +/* + * PCI Bus allocation + * + * (Guessing ...) + */ +#define GT_PCI_MEM_BASE 0x12000000UL +#define GT_PCI_MEM_SIZE 0x02000000UL +#define GT_PCI_IO_BASE 0x10000000UL +#define GT_PCI_IO_SIZE 0x02000000UL +#define GT_ISA_IO_BASE PCI_IO_BASE + +#endif /* _ASM_GT64120_LASAT_GT64120_DEP_H */ diff --git a/include/asm-mips/mach-lasat/war.h b/include/asm-mips/mach-lasat/war.h new file mode 100644 index 000000000000..bb1e0325c9be --- /dev/null +++ b/include/asm-mips/mach-lasat/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_LASAT_WAR_H +#define __ASM_MIPS_MACH_LASAT_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_LASAT_WAR_H */ diff --git a/include/asm-mips/mach-lemote/war.h b/include/asm-mips/mach-lemote/war.h new file mode 100644 index 000000000000..05f89e0f2a11 --- /dev/null +++ b/include/asm-mips/mach-lemote/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_LEMOTE_WAR_H +#define __ASM_MIPS_MACH_LEMOTE_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_LEMOTE_WAR_H */ diff --git a/include/asm-mips/mach-mips/mach-gt64120.h b/include/asm-mips/mach-mips/mach-gt64120.h index 511f7cf3a6be..0f863148f3b6 100644 --- a/include/asm-mips/mach-mips/mach-gt64120.h +++ b/include/asm-mips/mach-mips/mach-gt64120.h @@ -16,13 +16,4 @@ extern unsigned long _pcictrl_gt64120; */ #define GT64120_BASE _pcictrl_gt64120 -/* - * PCI Bus allocation - */ -#define GT_PCI_MEM_BASE 0x12000000UL -#define GT_PCI_MEM_SIZE 0x02000000UL -#define GT_PCI_IO_BASE 0x10000000UL -#define GT_PCI_IO_SIZE 0x02000000UL -#define GT_ISA_IO_BASE PCI_IO_BASE - #endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */ diff --git a/include/asm-mips/mach-mips/war.h b/include/asm-mips/mach-mips/war.h new file mode 100644 index 000000000000..7c6931d5f45f --- /dev/null +++ b/include/asm-mips/mach-mips/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_MIPS_WAR_H +#define __ASM_MIPS_MACH_MIPS_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 1 +#define MIPS_CACHE_SYNC_WAR 1 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */ diff --git a/include/asm-mips/mach-mipssim/war.h b/include/asm-mips/mach-mipssim/war.h new file mode 100644 index 000000000000..c8a74a3515e0 --- /dev/null +++ b/include/asm-mips/mach-mipssim/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_MIPSSIM_WAR_H +#define __ASM_MIPS_MACH_MIPSSIM_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_MIPSSIM_WAR_H */ diff --git a/include/asm-mips/mach-pb1x00/pb1000.h b/include/asm-mips/mach-pb1x00/pb1000.h index 50c1e413a688..b52e0e7ee3fb 100644 --- a/include/asm-mips/mach-pb1x00/pb1000.h +++ b/include/asm-mips/mach-pb1x00/pb1000.h @@ -32,38 +32,38 @@ #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) #define PB1000_PCR 0xBE000000 - #define PCR_SLOT_0_VPP0 (1<<0) - #define PCR_SLOT_0_VPP1 (1<<1) - #define PCR_SLOT_0_VCC0 (1<<2) - #define PCR_SLOT_0_VCC1 (1<<3) - #define PCR_SLOT_0_RST (1<<4) - - #define PCR_SLOT_1_VPP0 (1<<8) - #define PCR_SLOT_1_VPP1 (1<<9) - #define PCR_SLOT_1_VCC0 (1<<10) - #define PCR_SLOT_1_VCC1 (1<<11) - #define PCR_SLOT_1_RST (1<<12) +# define PCR_SLOT_0_VPP0 (1<<0) +# define PCR_SLOT_0_VPP1 (1<<1) +# define PCR_SLOT_0_VCC0 (1<<2) +# define PCR_SLOT_0_VCC1 (1<<3) +# define PCR_SLOT_0_RST (1<<4) + +# define PCR_SLOT_1_VPP0 (1<<8) +# define PCR_SLOT_1_VPP1 (1<<9) +# define PCR_SLOT_1_VCC0 (1<<10) +# define PCR_SLOT_1_VCC1 (1<<11) +# define PCR_SLOT_1_RST (1<<12) #define PB1000_MDR 0xBE000004 - #define MDR_PI (1<<5) /* pcmcia int latch */ - #define MDR_EPI (1<<14) /* enable pcmcia int */ - #define MDR_CPI (1<<15) /* clear pcmcia int */ +# define MDR_PI (1<<5) /* pcmcia int latch */ +# define MDR_EPI (1<<14) /* enable pcmcia int */ +# define MDR_CPI (1<<15) /* clear pcmcia int */ #define PB1000_ACR1 0xBE000008 - #define ACR1_SLOT_0_CD1 (1<<0) /* card detect 1 */ - #define ACR1_SLOT_0_CD2 (1<<1) /* card detect 2 */ - #define ACR1_SLOT_0_READY (1<<2) /* ready */ - #define ACR1_SLOT_0_STATUS (1<<3) /* status change */ - #define ACR1_SLOT_0_VS1 (1<<4) /* voltage sense 1 */ - #define ACR1_SLOT_0_VS2 (1<<5) /* voltage sense 2 */ - #define ACR1_SLOT_0_INPACK (1<<6) /* inpack pin status */ - #define ACR1_SLOT_1_CD1 (1<<8) /* card detect 1 */ - #define ACR1_SLOT_1_CD2 (1<<9) /* card detect 2 */ - #define ACR1_SLOT_1_READY (1<<10) /* ready */ - #define ACR1_SLOT_1_STATUS (1<<11) /* status change */ - #define ACR1_SLOT_1_VS1 (1<<12) /* voltage sense 1 */ - #define ACR1_SLOT_1_VS2 (1<<13) /* voltage sense 2 */ - #define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */ +# define ACR1_SLOT_0_CD1 (1<<0) /* card detect 1 */ +# define ACR1_SLOT_0_CD2 (1<<1) /* card detect 2 */ +# define ACR1_SLOT_0_READY (1<<2) /* ready */ +# define ACR1_SLOT_0_STATUS (1<<3) /* status change */ +# define ACR1_SLOT_0_VS1 (1<<4) /* voltage sense 1 */ +# define ACR1_SLOT_0_VS2 (1<<5) /* voltage sense 2 */ +# define ACR1_SLOT_0_INPACK (1<<6) /* inpack pin status */ +# define ACR1_SLOT_1_CD1 (1<<8) /* card detect 1 */ +# define ACR1_SLOT_1_CD2 (1<<9) /* card detect 2 */ +# define ACR1_SLOT_1_READY (1<<10) /* ready */ +# define ACR1_SLOT_1_STATUS (1<<11) /* status change */ +# define ACR1_SLOT_1_VS1 (1<<12) /* voltage sense 1 */ +# define ACR1_SLOT_1_VS2 (1<<13) /* voltage sense 2 */ +# define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */ #define CPLD_AUX0 0xBE00000C #define CPLD_AUX1 0xBE000010 diff --git a/include/asm-mips/mach-pb1x00/pb1100.h b/include/asm-mips/mach-pb1x00/pb1100.h index 4c5a1cd01841..63aa3926b297 100644 --- a/include/asm-mips/mach-pb1x00/pb1100.h +++ b/include/asm-mips/mach-pb1x00/pb1100.h @@ -29,44 +29,44 @@ #define PB1100_IDENT 0xAE000000 #define BOARD_STATUS_REG 0xAE000004 - #define PB1100_ROM_SEL (1<<15) - #define PB1100_ROM_SIZ (1<<14) - #define PB1100_SWAP_BOOT (1<<13) - #define PB1100_FLASH_WP (1<<12) - #define PB1100_ROM_H_STS (1<<11) - #define PB1100_ROM_L_STS (1<<10) - #define PB1100_FLASH_H_STS (1<<9) - #define PB1100_FLASH_L_STS (1<<8) - #define PB1100_SRAM_SIZ (1<<7) - #define PB1100_TSC_BUSY (1<<6) - #define PB1100_PCMCIA_VS_MASK (3<<4) - #define PB1100_RS232_CD (1<<3) - #define PB1100_RS232_CTS (1<<2) - #define PB1100_RS232_DSR (1<<1) - #define PB1100_RS232_RI (1<<0) +# define PB1100_ROM_SEL (1<<15) +# define PB1100_ROM_SIZ (1<<14) +# define PB1100_SWAP_BOOT (1<<13) +# define PB1100_FLASH_WP (1<<12) +# define PB1100_ROM_H_STS (1<<11) +# define PB1100_ROM_L_STS (1<<10) +# define PB1100_FLASH_H_STS (1<<9) +# define PB1100_FLASH_L_STS (1<<8) +# define PB1100_SRAM_SIZ (1<<7) +# define PB1100_TSC_BUSY (1<<6) +# define PB1100_PCMCIA_VS_MASK (3<<4) +# define PB1100_RS232_CD (1<<3) +# define PB1100_RS232_CTS (1<<2) +# define PB1100_RS232_DSR (1<<1) +# define PB1100_RS232_RI (1<<0) #define PB1100_IRDA_RS232 0xAE00000C - #define PB1100_IRDA_FULL (0<<14) /* full power */ - #define PB1100_IRDA_SHUTDOWN (1<<14) - #define PB1100_IRDA_TT (2<<14) /* 2/3 power */ - #define PB1100_IRDA_OT (3<<14) /* 1/3 power */ - #define PB1100_IRDA_FIR (1<<13) +# define PB1100_IRDA_FULL (0<<14) /* full power */ +# define PB1100_IRDA_SHUTDOWN (1<<14) +# define PB1100_IRDA_TT (2<<14) /* 2/3 power */ +# define PB1100_IRDA_OT (3<<14) /* 1/3 power */ +# define PB1100_IRDA_FIR (1<<13) #define PCMCIA_BOARD_REG 0xAE000010 - #define PB1100_SD_WP1_RO (1<<15) /* read only */ - #define PB1100_SD_WP0_RO (1<<14) /* read only */ - #define PB1100_SD_PWR1 (1<<11) /* applies power to SD1 */ - #define PB1100_SD_PWR0 (1<<10) /* applies power to SD0 */ - #define PB1100_SEL_SD_CONN1 (1<<9) - #define PB1100_SEL_SD_CONN0 (1<<8) - #define PC_DEASSERT_RST (1<<7) - #define PC_DRV_EN (1<<4) +# define PB1100_SD_WP1_RO (1<<15) /* read only */ +# define PB1100_SD_WP0_RO (1<<14) /* read only */ +# define PB1100_SD_PWR1 (1<<11) /* applies power to SD1 */ +# define PB1100_SD_PWR0 (1<<10) /* applies power to SD0 */ +# define PB1100_SEL_SD_CONN1 (1<<9) +# define PB1100_SEL_SD_CONN0 (1<<8) +# define PC_DEASSERT_RST (1<<7) +# define PC_DRV_EN (1<<4) #define PB1100_G_CONTROL 0xAE000014 /* graphics control */ #define PB1100_RST_VDDI 0xAE00001C - #define PB1100_SOFT_RESET (1<<15) /* clear to reset the board */ - #define PB1100_VDDI_MASK (0x1F) +# define PB1100_SOFT_RESET (1<<15) /* clear to reset the board */ +# define PB1100_VDDI_MASK (0x1F) #define PB1100_LEDS 0xAE000018 diff --git a/include/asm-mips/mach-pnx8550/kernel-entry-init.h b/include/asm-mips/mach-pnx8550/kernel-entry-init.h index 57102fa9da51..bdde00c9199b 100644 --- a/include/asm-mips/mach-pnx8550/kernel-entry-init.h +++ b/include/asm-mips/mach-pnx8550/kernel-entry-init.h @@ -44,7 +44,7 @@ cache_begin: li t0, (1<<28) mfc0 t0, CP0_CONFIG, 7 HAZARD_CP0 - and t0,~((1<<19) | (1<<20)) /* TLB/MAP cleared */ + and t0, ~((1<<19) | (1<<20)) /* TLB/MAP cleared */ mtc0 t0, CP0_CONFIG, 7 HAZARD_CP0 @@ -200,10 +200,10 @@ pr4450_instr_cache_invalidated: icache_invd_loop: /* 9 == register t1 */ - .word (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ - (0 * ICACHE_SET_SIZE)) /* invalidate inst cache WAY0 */ - .word (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ - (1 * ICACHE_SET_SIZE)) /* invalidate inst cache WAY1 */ + .word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ + (0 * ICACHE_SET_SIZE) /* invalidate inst cache WAY0 */ + .word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ + (1 * ICACHE_SET_SIZE) /* invalidate inst cache WAY1 */ addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */ bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */ @@ -235,14 +235,14 @@ pr4450_instr_cache_invalidated: dcache_wbinvd_loop: /* 9 == register t1 */ - .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ - (0 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY0 */ - .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ - (1 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY1 */ - .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ - (2 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY2 */ - .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ - (3 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY3 */ + .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ + (0 * DCACHE_SET_SIZE) /* writeback/invalidate WAY0 */ + .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ + (1 * DCACHE_SET_SIZE) /* writeback/invalidate WAY1 */ + .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ + (2 * DCACHE_SET_SIZE) /* writeback/invalidate WAY2 */ + .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ + (3 * DCACHE_SET_SIZE) /* writeback/invalidate WAY3 */ addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */ bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */ diff --git a/include/asm-mips/mach-pnx8550/uart.h b/include/asm-mips/mach-pnx8550/uart.h index 814a7a15ab49..ad7608d44874 100644 --- a/include/asm-mips/mach-pnx8550/uart.h +++ b/include/asm-mips/mach-pnx8550/uart.h @@ -15,7 +15,7 @@ /* early macros needed for prom/kgdb */ -#define ip3106_lcr(base,port) *(volatile u32 *)(base+(port*0x1000) + 0x000) +#define ip3106_lcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x000) #define ip3106_mcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x004) #define ip3106_baud(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x008) #define ip3106_cfg(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x00C) diff --git a/include/asm-mips/mach-pnx8550/war.h b/include/asm-mips/mach-pnx8550/war.h new file mode 100644 index 000000000000..d0458dd082f9 --- /dev/null +++ b/include/asm-mips/mach-pnx8550/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_PNX8550_WAR_H +#define __ASM_MIPS_MACH_PNX8550_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */ diff --git a/include/asm-mips/mach-qemu/war.h b/include/asm-mips/mach-qemu/war.h new file mode 100644 index 000000000000..0eaf0c548a47 --- /dev/null +++ b/include/asm-mips/mach-qemu/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_QEMU_WAR_H +#define __ASM_MIPS_MACH_QEMU_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_QEMU_WAR_H */ diff --git a/include/asm-mips/mach-rm/war.h b/include/asm-mips/mach-rm/war.h new file mode 100644 index 000000000000..948d3129a114 --- /dev/null +++ b/include/asm-mips/mach-rm/war.h @@ -0,0 +1,29 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_RM_WAR_H +#define __ASM_MIPS_MACH_RM_WAR_H + +/* + * The RM200C seems to have been shipped only with V2.0 R4600s + */ + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 1 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_RM_WAR_H */ diff --git a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h index 63d5bf649af1..1c1f92415b9a 100644 --- a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h +++ b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h @@ -9,7 +9,7 @@ #define __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H /* - * Sibyte are MIPS64 processors weired to a specific configuration + * Sibyte are MIPS64 processors wired to a specific configuration */ #define cpu_has_watch 1 #define cpu_has_mips16 0 @@ -33,6 +33,11 @@ #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 1 +#define cpu_has_mips64r2 0 + #define cpu_has_inclusive_pcaches 0 #define cpu_dcache_line_size() 32 diff --git a/include/asm-mips/mach-sibyte/war.h b/include/asm-mips/mach-sibyte/war.h new file mode 100644 index 000000000000..7950ef4f032c --- /dev/null +++ b/include/asm-mips/mach-sibyte/war.h @@ -0,0 +1,37 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H +#define __ASM_MIPS_MACH_SIBYTE_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 + +#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \ + defined(CONFIG_SB1_PASS_2_WORKAROUNDS) + +#define BCM1250_M3_WAR 1 +#define SIBYTE_1956_WAR 1 + +#else + +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 + +#endif + +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */ diff --git a/include/asm-mips/mach-tx49xx/war.h b/include/asm-mips/mach-tx49xx/war.h new file mode 100644 index 000000000000..39b5d1177c57 --- /dev/null +++ b/include/asm-mips/mach-tx49xx/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_TX49XX_WAR_H +#define __ASM_MIPS_MACH_TX49XX_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 1 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */ diff --git a/include/asm-mips/mach-vr41xx/war.h b/include/asm-mips/mach-vr41xx/war.h new file mode 100644 index 000000000000..56a38926412a --- /dev/null +++ b/include/asm-mips/mach-vr41xx/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_VR41XX_WAR_H +#define __ASM_MIPS_MACH_VR41XX_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_VR41XX_WAR_H */ diff --git a/include/asm-mips/mach-wrppmc/mach-gt64120.h b/include/asm-mips/mach-wrppmc/mach-gt64120.h index ba9205a04582..00d8bf6164a9 100644 --- a/include/asm-mips/mach-wrppmc/mach-gt64120.h +++ b/include/asm-mips/mach-wrppmc/mach-gt64120.h @@ -43,7 +43,6 @@ #define GT_PCI_MEM_SIZE 0x02000000UL #define GT_PCI_IO_BASE 0x11000000UL #define GT_PCI_IO_SIZE 0x02000000UL -#define GT_ISA_IO_BASE PCI_IO_BASE /* * PCI interrupts will come in on either the INTA or INTD interrups lines, diff --git a/include/asm-mips/mach-wrppmc/war.h b/include/asm-mips/mach-wrppmc/war.h new file mode 100644 index 000000000000..ac48629bb1ce --- /dev/null +++ b/include/asm-mips/mach-wrppmc/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_WRPPMC_WAR_H +#define __ASM_MIPS_MACH_WRPPMC_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_WRPPMC_WAR_H */ diff --git a/include/asm-mips/mach-yosemite/war.h b/include/asm-mips/mach-yosemite/war.h new file mode 100644 index 000000000000..e5c6d53efc86 --- /dev/null +++ b/include/asm-mips/mach-yosemite/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_YOSEMITE_WAR_H +#define __ASM_MIPS_MACH_YOSEMITE_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 1 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_YOSEMITE_WAR_H */ diff --git a/include/asm-mips/mc146818-time.h b/include/asm-mips/mc146818-time.h index 41ac8d363c67..cdc379a0a94e 100644 --- a/include/asm-mips/mc146818-time.h +++ b/include/asm-mips/mc146818-time.h @@ -63,8 +63,8 @@ static inline int mc146818_set_rtc_mmss(unsigned long nowtime) BIN_TO_BCD(real_seconds); BIN_TO_BCD(real_minutes); } - CMOS_WRITE(real_seconds,RTC_SECONDS); - CMOS_WRITE(real_minutes,RTC_MINUTES); + CMOS_WRITE(real_seconds, RTC_SECONDS); + CMOS_WRITE(real_minutes, RTC_MINUTES); } else { printk(KERN_WARNING "set_rtc_mmss: can't update from %d to %d\n", diff --git a/include/asm-mips/mips-boards/bonito64.h b/include/asm-mips/mips-boards/bonito64.h index dc3fc32eedd8..a0f04bb99c99 100644 --- a/include/asm-mips/mips-boards/bonito64.h +++ b/include/asm-mips/mips-boards/bonito64.h @@ -387,7 +387,7 @@ extern unsigned long _pcictrl_bonito_pcicfg; #define BONITO_PCIMAP_PCIMAP_LO2 0x0003f000 #define BONITO_PCIMAP_PCIMAP_LO2_SHIFT 12 #define BONITO_PCIMAP_PCIMAP_2 0x00040000 -#define BONITO_PCIMAP_WIN(WIN,ADDR) ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) +#define BONITO_PCIMAP_WIN(WIN, ADDR) ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) #define BONITO_PCIMAP_WINSIZE (1<<26) #define BONITO_PCIMAP_WINOFFSET(ADDR) ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1)) @@ -412,19 +412,19 @@ extern unsigned long _pcictrl_bonito_pcicfg; #define BONITO_PCIMEMBASECFG_ASHIFT 23 #define BONITO_PCIMEMBASECFG_AMASK 0x007fffff -#define BONITO_PCIMEMBASECFGSIZE(WIN,SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) -#define BONITO_PCIMEMBASECFGBASE(WIN,BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) +#define BONITO_PCIMEMBASECFGSIZE(WIN, SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) +#define BONITO_PCIMEMBASECFGBASE(WIN, BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) -#define BONITO_PCIMEMBASECFG_SIZE(WIN,CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK) +#define BONITO_PCIMEMBASECFG_SIZE(WIN, CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK) -#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) -#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) -#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) +#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) +#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) +#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) -#define BONITO_PCITOPHYS(WIN,ADDR,CFG) ( \ - (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG)))) | \ - (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG)) \ +#define BONITO_PCITOPHYS(WIN, ADDR, CFG) ( \ + (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)))) | \ + (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG)) \ ) /* PCICmd */ diff --git a/include/asm-mips/mips-boards/malta.h b/include/asm-mips/mips-boards/malta.h index eec91001bb65..93bf4e51b8a4 100644 --- a/include/asm-mips/mips-boards/malta.h +++ b/include/asm-mips/mips-boards/malta.h @@ -72,7 +72,7 @@ static inline unsigned long get_msc_port_base(unsigned long reg) #define SMSC_CONFIG_ACTIVATE_ENABLE 1 -#define SMSC_WRITE(x,a) outb(x,a) +#define SMSC_WRITE(x, a) outb(x, a) #define MALTA_JMPRS_REG 0x1f000210 diff --git a/include/asm-mips/mipsmtregs.h b/include/asm-mips/mipsmtregs.h index 294bca12cd3f..5a2f8a3a6a1f 100644 --- a/include/asm-mips/mipsmtregs.h +++ b/include/asm-mips/mipsmtregs.h @@ -41,27 +41,27 @@ * Macros for use in assembly language code */ -#define CP0_MVPCONTROL $0,1 -#define CP0_MVPCONF0 $0,2 -#define CP0_MVPCONF1 $0,3 -#define CP0_VPECONTROL $1,1 -#define CP0_VPECONF0 $1,2 -#define CP0_VPECONF1 $1,3 -#define CP0_YQMASK $1,4 -#define CP0_VPESCHEDULE $1,5 -#define CP0_VPESCHEFBK $1,6 -#define CP0_TCSTATUS $2,1 -#define CP0_TCBIND $2,2 -#define CP0_TCRESTART $2,3 -#define CP0_TCHALT $2,4 -#define CP0_TCCONTEXT $2,5 -#define CP0_TCSCHEDULE $2,6 -#define CP0_TCSCHEFBK $2,7 -#define CP0_SRSCONF0 $6,1 -#define CP0_SRSCONF1 $6,2 -#define CP0_SRSCONF2 $6,3 -#define CP0_SRSCONF3 $6,4 -#define CP0_SRSCONF4 $6,5 +#define CP0_MVPCONTROL $0, 1 +#define CP0_MVPCONF0 $0, 2 +#define CP0_MVPCONF1 $0, 3 +#define CP0_VPECONTROL $1, 1 +#define CP0_VPECONF0 $1, 2 +#define CP0_VPECONF1 $1, 3 +#define CP0_YQMASK $1, 4 +#define CP0_VPESCHEDULE $1, 5 +#define CP0_VPESCHEFBK $1, 6 +#define CP0_TCSTATUS $2, 1 +#define CP0_TCBIND $2, 2 +#define CP0_TCRESTART $2, 3 +#define CP0_TCHALT $2, 4 +#define CP0_TCCONTEXT $2, 5 +#define CP0_TCSCHEDULE $2, 6 +#define CP0_TCSCHEFBK $2, 7 +#define CP0_SRSCONF0 $6, 1 +#define CP0_SRSCONF1 $6, 2 +#define CP0_SRSCONF2 $6, 3 +#define CP0_SRSCONF3 $6, 4 +#define CP0_SRSCONF4 $6, 5 #endif @@ -291,7 +291,7 @@ static inline void ehb(void) __res; \ }) -#define mftr(rt,u,sel) \ +#define mftr(rt, u, sel) \ ({ \ unsigned long __res; \ \ @@ -315,7 +315,7 @@ do { \ : : "r" (v)); \ } while (0) -#define mttc0(rd,sel,v) \ +#define mttc0(rd, sel, v) \ ({ \ __asm__ __volatile__( \ " .set push \n" \ @@ -330,7 +330,7 @@ do { \ }) -#define mttr(rd,u,sel,v) \ +#define mttr(rd, u, sel, v) \ ({ \ __asm__ __volatile__( \ "mttr %0," #rd ", " #u ", " #sel \ @@ -362,7 +362,7 @@ do { \ #define write_vpe_c0_config1(val) mttc0(16, 1, val) #define read_vpe_c0_config7() mftc0(16, 7) #define write_vpe_c0_config7(val) mttc0(16, 7, val) -#define read_vpe_c0_ebase() mftc0(15,1) +#define read_vpe_c0_ebase() mftc0(15, 1) #define write_vpe_c0_ebase(val) mttc0(15, 1, val) #define write_vpe_c0_compare(val) mttc0(11, 0, val) #define read_vpe_c0_badvaddr() mftc0(8, 0) @@ -372,15 +372,15 @@ do { \ /* TC */ #define read_tc_c0_tcstatus() mftc0(2, 1) -#define write_tc_c0_tcstatus(val) mttc0(2,1,val) +#define write_tc_c0_tcstatus(val) mttc0(2, 1, val) #define read_tc_c0_tcbind() mftc0(2, 2) -#define write_tc_c0_tcbind(val) mttc0(2,2,val) +#define write_tc_c0_tcbind(val) mttc0(2, 2, val) #define read_tc_c0_tcrestart() mftc0(2, 3) -#define write_tc_c0_tcrestart(val) mttc0(2,3,val) +#define write_tc_c0_tcrestart(val) mttc0(2, 3, val) #define read_tc_c0_tchalt() mftc0(2, 4) -#define write_tc_c0_tchalt(val) mttc0(2,4,val) +#define write_tc_c0_tchalt(val) mttc0(2, 4, val) #define read_tc_c0_tccontext() mftc0(2, 5) -#define write_tc_c0_tccontext(val) mttc0(2,5,val) +#define write_tc_c0_tccontext(val) mttc0(2, 5, val) /* GPR */ #define read_tc_gpr_sp() mftgpr(29) diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 18f47f1e8cd5..aa17f658f73c 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -981,7 +981,7 @@ do { \ #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) /* MIPSR2 */ -#define read_c0_hwrena() __read_32bit_c0_register($7,0) +#define read_c0_hwrena() __read_32bit_c0_register($7, 0) #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) #define read_c0_intctl() __read_32bit_c0_register($12, 1) @@ -993,7 +993,7 @@ do { \ #define read_c0_srsmap() __read_32bit_c0_register($12, 3) #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) -#define read_c0_ebase() __read_32bit_c0_register($15,1) +#define read_c0_ebase() __read_32bit_c0_register($15, 1) #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) /* diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h index 65024ffd7879..0c4f245eaeb2 100644 --- a/include/asm-mips/mmu_context.h +++ b/include/asm-mips/mmu_context.h @@ -107,7 +107,7 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) #else /* CONFIG_MIPS_MT_SMTC */ -#define get_new_mmu_context(mm,cpu) smtc_get_new_mmu_context((mm),(cpu)) +#define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu)) #endif /* CONFIG_MIPS_MT_SMTC */ @@ -120,7 +120,7 @@ init_new_context(struct task_struct *tsk, struct mm_struct *mm) { int i; - for (i = 0; i < num_online_cpus(); i++) + for_each_online_cpu(i) cpu_context(i, mm) = 0; return 0; @@ -191,7 +191,7 @@ static inline void destroy_context(struct mm_struct *mm) { } -#define deactivate_mm(tsk,mm) do { } while (0) +#define deactivate_mm(tsk, mm) do { } while (0) /* * After we have set current->mm to a new value, this activates @@ -284,7 +284,7 @@ drop_mmu_context(struct mm_struct *mm, unsigned cpu) int i; /* SMTC shares the TLB (and ASIDs) across VPEs */ - for (i = 0; i < num_online_cpus(); i++) { + for_each_online_cpu(i) { if((smtc_status & SMTC_TLB_SHARED) || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id)) cpu_context(i, mm) = 0; diff --git a/include/asm-mips/nile4.h b/include/asm-mips/nile4.h new file mode 100644 index 000000000000..c3ca959aa4d9 --- /dev/null +++ b/include/asm-mips/nile4.h @@ -0,0 +1,310 @@ +/* + * asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions + * + * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> + * Sony Software Development Center Europe (SDCE), Brussels + * + * This file is based on the following documentation: + * + * NEC Vrc 5074 System Controller Data Sheet, June 1998 + */ + +#ifndef _ASM_NILE4_H +#define _ASM_NILE4_H + +#define NILE4_BASE 0xbfa00000 +#define NILE4_SIZE 0x00200000 /* 2 MB */ + + + /* + * Physical Device Address Registers (PDARs) + */ + +#define NILE4_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */ +#define NILE4_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */ +#define NILE4_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */ +#define NILE4_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */ +#define NILE4_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */ +#define NILE4_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */ +#define NILE4_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */ +#define NILE4_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */ +#define NILE4_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */ +#define NILE4_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */ +#define NILE4_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */ +#define NILE4_INTCS 0x0070 /* Controller Internal Registers and Devices */ + /* [R/W] */ +#define NILE4_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */ + + + /* + * CPU Interface Registers + */ + +#define NILE4_CPUSTAT 0x0080 /* CPU Status [R/W] */ +#define NILE4_INTCTRL 0x0088 /* Interrupt Control [R/W] */ +#define NILE4_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */ +#define NILE4_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */ + /* Enable [R/W] */ +#define NILE4_INTCLR 0x00A0 /* Interrupt Clear [R/W] */ +#define NILE4_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */ + + + /* + * Memory-Interface Registers + */ + +#define NILE4_MEMCTRL 0x00C0 /* Memory Control */ +#define NILE4_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */ +#define NILE4_CHKERR 0x00D0 /* Memory Check Error Status [R] */ + + + /* + * PCI-Bus Registers + */ + +#define NILE4_PCICTRL 0x00E0 /* PCI Control [R/W] */ +#define NILE4_PCIARB 0x00E8 /* PCI Arbiter [R/W] */ +#define NILE4_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */ +#define NILE4_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */ +#define NILE4_PCIERR 0x00B8 /* PCI Error [R/W] */ + + + /* + * Local-Bus Registers + */ + +#define NILE4_LCNFG 0x0100 /* Local Bus Configuration [R/W] */ +#define NILE4_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */ +#define NILE4_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */ +#define NILE4_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */ +#define NILE4_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */ +#define NILE4_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */ +#define NILE4_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */ +#define NILE4_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */ +#define NILE4_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */ + /* Enables [R/W] */ +#define NILE4_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */ +#define NILE4_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */ + + + /* + * DMA Registers + */ + +#define NILE4_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */ +#define NILE4_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */ +#define NILE4_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */ +#define NILE4_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */ +#define NILE4_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */ +#define NILE4_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */ + + + /* + * Timer Registers + */ + +#define NILE4_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */ +#define NILE4_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */ +#define NILE4_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */ +#define NILE4_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */ +#define NILE4_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */ +#define NILE4_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */ +#define NILE4_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */ +#define NILE4_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */ + + + /* + * PCI Configuration Space Registers + */ + +#define NILE4_PCI_BASE 0x0200 + +#define NILE4_VID 0x0200 /* PCI Vendor ID [R] */ +#define NILE4_DID 0x0202 /* PCI Device ID [R] */ +#define NILE4_PCICMD 0x0204 /* PCI Command [R/W] */ +#define NILE4_PCISTS 0x0206 /* PCI Status [R/W] */ +#define NILE4_REVID 0x0208 /* PCI Revision ID [R] */ +#define NILE4_CLASS 0x0209 /* PCI Class Code [R] */ +#define NILE4_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */ +#define NILE4_MLTIM 0x020D /* PCI Latency Timer [R/W] */ +#define NILE4_HTYPE 0x020E /* PCI Header Type [R] */ +#define NILE4_BIST 0x020F /* BIST [R] (unimplemented) */ +#define NILE4_BARC 0x0210 /* PCI Base Address Register Control [R/W] */ +#define NILE4_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */ +#define NILE4_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */ +#define NILE4_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */ + /* (unimplemented) */ +#define NILE4_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */ +#define NILE4_SSID 0x022E /* PCI Sub-System ID [R/W] */ +#define NILE4_ROM 0x0230 /* Expansion ROM Base Address [R] */ + /* (unimplemented) */ +#define NILE4_INTLIN 0x023C /* PCI Interrupt Line [R/W] */ +#define NILE4_INTPIN 0x023D /* PCI Interrupt Pin [R] */ +#define NILE4_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */ +#define NILE4_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */ +#define NILE4_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */ +#define NILE4_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */ +#define NILE4_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */ +#define NILE4_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */ +#define NILE4_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */ +#define NILE4_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */ +#define NILE4_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */ +#define NILE4_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */ + + + /* + * Serial-Port Registers + */ + +#define NILE4_UART_BASE 0x0300 + +#define NILE4_UARTRBR 0x0300 /* UART Receiver Data Buffer [R] */ +#define NILE4_UARTTHR 0x0300 /* UART Transmitter Data Holding [W] */ +#define NILE4_UARTIER 0x0308 /* UART Interrupt Enable [R/W] */ +#define NILE4_UARTDLL 0x0300 /* UART Divisor Latch LSB [R/W] */ +#define NILE4_UARTDLM 0x0308 /* UART Divisor Latch MSB [R/W] */ +#define NILE4_UARTIIR 0x0310 /* UART Interrupt ID [R] */ +#define NILE4_UARTFCR 0x0310 /* UART FIFO Control [W] */ +#define NILE4_UARTLCR 0x0318 /* UART Line Control [R/W] */ +#define NILE4_UARTMCR 0x0320 /* UART Modem Control [R/W] */ +#define NILE4_UARTLSR 0x0328 /* UART Line Status [R/W] */ +#define NILE4_UARTMSR 0x0330 /* UART Modem Status [R/W] */ +#define NILE4_UARTSCR 0x0338 /* UART Scratch [R/W] */ + +#define NILE4_UART_BASE_BAUD 520833 /* 100 MHz / 12 / 16 */ + + + /* + * Interrupt Lines + */ + +#define NILE4_INT_CPCE 0 /* CPU-Interface Parity-Error Interrupt */ +#define NILE4_INT_CNTD 1 /* CPU No-Target Decode Interrupt */ +#define NILE4_INT_MCE 2 /* Memory-Check Error Interrupt */ +#define NILE4_INT_DMA 3 /* DMA Controller Interrupt */ +#define NILE4_INT_UART 4 /* UART Interrupt */ +#define NILE4_INT_WDOG 5 /* Watchdog Timer Interrupt */ +#define NILE4_INT_GPT 6 /* General-Purpose Timer Interrupt */ +#define NILE4_INT_LBRTD 7 /* Local-Bus Ready Timer Interrupt */ +#define NILE4_INT_INTA 8 /* PCI Interrupt Signal INTA# */ +#define NILE4_INT_INTB 9 /* PCI Interrupt Signal INTB# */ +#define NILE4_INT_INTC 10 /* PCI Interrupt Signal INTC# */ +#define NILE4_INT_INTD 11 /* PCI Interrupt Signal INTD# */ +#define NILE4_INT_INTE 12 /* PCI Interrupt Signal INTE# (ISA cascade) */ +#define NILE4_INT_RESV 13 /* Reserved */ +#define NILE4_INT_PCIS 14 /* PCI SERR# Interrupt */ +#define NILE4_INT_PCIE 15 /* PCI Internal Error Interrupt */ + + + /* + * Nile 4 Register Access + */ + +static inline void nile4_sync(void) +{ + volatile u32 *p = (volatile u32 *)0xbfc00000; + (void)(*p); +} + +static inline void nile4_out32(u32 offset, u32 val) +{ + *(volatile u32 *)(NILE4_BASE+offset) = val; + nile4_sync(); +} + +static inline u32 nile4_in32(u32 offset) +{ + u32 val = *(volatile u32 *)(NILE4_BASE+offset); + nile4_sync(); + return val; +} + +static inline void nile4_out16(u32 offset, u16 val) +{ + *(volatile u16 *)(NILE4_BASE+offset) = val; + nile4_sync(); +} + +static inline u16 nile4_in16(u32 offset) +{ + u16 val = *(volatile u16 *)(NILE4_BASE+offset); + nile4_sync(); + return val; +} + +static inline void nile4_out8(u32 offset, u8 val) +{ + *(volatile u8 *)(NILE4_BASE+offset) = val; + nile4_sync(); +} + +static inline u8 nile4_in8(u32 offset) +{ + u8 val = *(volatile u8 *)(NILE4_BASE+offset); + nile4_sync(); + return val; +} + + + /* + * Physical Device Address Registers + */ + +extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width, + int on_memory_bus, int visible); + + + /* + * PCI Master Registers + */ + +#define NILE4_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */ +#define NILE4_PCICMD_IO 1 /* PCI I/O Space */ +#define NILE4_PCICMD_MEM 3 /* PCI Memory Space */ +#define NILE4_PCICMD_CFG 5 /* PCI Configuration Space */ + + + /* + * PCI Address Spaces + * + * Note that these are multiplexed using PCIINIT[01]! + */ + +#define NILE4_PCI_IO_BASE 0xa6000000 +#define NILE4_PCI_MEM_BASE 0xa8000000 +#define NILE4_PCI_CFG_BASE NILE4_PCI_MEM_BASE +#define NILE4_PCI_IACK_BASE NILE4_PCI_IO_BASE + + +extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr); + + + /* + * Interrupt Programming + */ + +#define NUM_I8259_INTERRUPTS 16 +#define NUM_NILE4_INTERRUPTS 16 + +#define IRQ_I8259_CASCADE NILE4_INT_INTE +#define is_i8259_irq(irq) ((irq) < NUM_I8259_INTERRUPTS) +#define nile4_to_irq(n) ((n)+NUM_I8259_INTERRUPTS) +#define irq_to_nile4(n) ((n)-NUM_I8259_INTERRUPTS) + +extern void nile4_map_irq(int nile4_irq, int cpu_irq); +extern void nile4_map_irq_all(int cpu_irq); +extern void nile4_enable_irq(unsigned int nile4_irq); +extern void nile4_disable_irq(unsigned int nile4_irq); +extern void nile4_disable_irq_all(void); +extern u16 nile4_get_irq_stat(int cpu_irq); +extern void nile4_enable_irq_output(int cpu_irq); +extern void nile4_disable_irq_output(int cpu_irq); +extern void nile4_set_pci_irq_polarity(int pci_irq, int high); +extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level); +extern void nile4_clear_irq(int nile4_irq); +extern void nile4_clear_irq_mask(u32 mask); +extern u8 nile4_i8259_iack(void); +extern void nile4_dump_irq_status(void); /* Debug */ + +#endif + diff --git a/include/asm-mips/paccess.h b/include/asm-mips/paccess.h index 8c08fa904b2c..c2394f8b0fe1 100644 --- a/include/asm-mips/paccess.h +++ b/include/asm-mips/paccess.h @@ -25,13 +25,13 @@ extern asmlinkage void handle_ibe(void); extern asmlinkage void handle_dbe(void); -#define put_dbe(x,ptr) __put_dbe((x),(ptr),sizeof(*(ptr))) -#define get_dbe(x,ptr) __get_dbe((x),(ptr),sizeof(*(ptr))) +#define put_dbe(x, ptr) __put_dbe((x), (ptr), sizeof(*(ptr))) +#define get_dbe(x, ptr) __get_dbe((x), (ptr), sizeof(*(ptr))) struct __large_pstruct { unsigned long buf[100]; }; #define __mp(x) (*(struct __large_pstruct *)(x)) -#define __get_dbe(x,ptr,size) \ +#define __get_dbe(x, ptr, size) \ ({ \ long __gu_err; \ __typeof__(*(ptr)) __gu_val; \ @@ -70,7 +70,7 @@ struct __large_pstruct { unsigned long buf[100]; }; extern void __get_dbe_unknown(void); -#define __put_dbe(x,ptr,size) \ +#define __put_dbe(x, ptr, size) \ ({ \ long __pu_err; \ __typeof__(*(ptr)) __pu_val; \ diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h index e3301e54d559..d2ea983bec06 100644 --- a/include/asm-mips/page.h +++ b/include/asm-mips/page.h @@ -153,7 +153,7 @@ typedef struct { unsigned long pgprot; } pgprot_t; ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET) #endif #define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET)) -#define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x),0)) +#define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x), 0)) #define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) diff --git a/include/asm-mips/parport.h b/include/asm-mips/parport.h index a742e04e82de..f52656826cce 100644 --- a/include/asm-mips/parport.h +++ b/include/asm-mips/parport.h @@ -6,10 +6,10 @@ #ifndef _ASM_PARPORT_H #define _ASM_PARPORT_H -static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma); -static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma) +static int __devinit parport_pc_find_isa_ports(int autoirq, int autodma); +static int __devinit parport_pc_find_nonpci_ports(int autoirq, int autodma) { - return parport_pc_find_isa_ports (autoirq, autodma); + return parport_pc_find_isa_ports(autoirq, autodma); } #endif /* _ASM_PARPORT_H */ diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h index 4fcc185cb2d1..301ff2f28012 100644 --- a/include/asm-mips/pci.h +++ b/include/asm-mips/pci.h @@ -150,8 +150,6 @@ pcibios_select_root(struct pci_dev *pdev, struct resource *res) return root; } -#ifdef CONFIG_PCI_DOMAINS - #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index static inline int pci_proc_domain(struct pci_bus *bus) @@ -160,8 +158,6 @@ static inline int pci_proc_domain(struct pci_bus *bus) return hose->need_domain_info; } -#endif /* CONFIG_PCI_DOMAINS */ - #endif /* __KERNEL__ */ /* implement the pci_ DMA API in terms of the generic device dma_ one */ diff --git a/include/asm-mips/pci/bridge.h b/include/asm-mips/pci/bridge.h index 0c45e7598f3f..b84feebf2cef 100644 --- a/include/asm-mips/pci/bridge.h +++ b/include/asm-mips/pci/bridge.h @@ -360,7 +360,7 @@ typedef struct bridge_err_cmdword_s { #define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100 /* Type 0 Cfg Func Offset (1..7) */ #define BRIDGE_TYPE0_CFG_DEV(s) (BRIDGE_TYPE0_CFG_DEV0+\ (s)*BRIDGE_TYPE0_CFG_SLOT_OFF) -#define BRIDGE_TYPE0_CFG_DEVF(s,f) (BRIDGE_TYPE0_CFG_DEV0+\ +#define BRIDGE_TYPE0_CFG_DEVF(s, f) (BRIDGE_TYPE0_CFG_DEV0+\ (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\ (f)*BRIDGE_TYPE0_CFG_FUNC_OFF) diff --git a/include/asm-mips/pgalloc.h b/include/asm-mips/pgalloc.h index 9fb57c035213..81b72122207a 100644 --- a/include/asm-mips/pgalloc.h +++ b/include/asm-mips/pgalloc.h @@ -95,7 +95,7 @@ static inline void pte_free(struct page *pte) __free_pages(pte, PTE_ORDER); } -#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) +#define __pte_free_tlb(tlb, pte) tlb_remove_page((tlb), (pte)) #ifdef CONFIG_32BIT @@ -104,7 +104,7 @@ static inline void pte_free(struct page *pte) * inside the pgd, so has no extra memory associated with it. */ #define pmd_free(x) do { } while (0) -#define __pmd_free_tlb(tlb,x) do { } while (0) +#define __pmd_free_tlb(tlb, x) do { } while (0) #endif @@ -125,7 +125,7 @@ static inline void pmd_free(pmd_t *pmd) free_pages((unsigned long)pmd, PMD_ORDER); } -#define __pmd_free_tlb(tlb,x) pmd_free(x) +#define __pmd_free_tlb(tlb, x) pmd_free(x) #endif diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h index 59c865deb0c7..a0947092d0e0 100644 --- a/include/asm-mips/pgtable-32.h +++ b/include/asm-mips/pgtable-32.h @@ -140,7 +140,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot) #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) /* to find an entry in a page-table-directory */ -#define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr)) +#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr)) /* Find an entry in the third-level page table.. */ #define __pte_offset(address) \ diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h index 49f5a1a2dfcd..943515f0ef87 100644 --- a/include/asm-mips/pgtable-64.h +++ b/include/asm-mips/pgtable-64.h @@ -104,7 +104,7 @@ #define VMALLOC_START MAP_BASE #define VMALLOC_END \ (VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE) -#if defined(CONFIG_MODULES) && !defined(CONFIG_BUILD_ELF64) && \ +#if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \ VMALLOC_START != CKSSEG /* Load modules into 32bit-compatible segment. */ #define MODULE_START CKSSEG @@ -193,7 +193,7 @@ static inline void pud_clear(pud_t *pudp) #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) /* to find an entry in a page-table-directory */ -#define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr)) +#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr)) static inline unsigned long pud_page_vaddr(pud_t pud) { @@ -237,7 +237,7 @@ static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) #define __swp_type(x) (((x).val >> 32) & 0xff) #define __swp_offset(x) ((x).val >> 40) -#define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) }) +#define __swp_entry(type, offset) ((swp_entry_t) { pte_val(mk_swap_pte((type), (offset))) }) #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h index d2ee28156743..17a7703a2969 100644 --- a/include/asm-mips/pgtable.h +++ b/include/asm-mips/pgtable.h @@ -103,7 +103,7 @@ static inline void set_pte(pte_t *ptep, pte_t pte) } } } -#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) +#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval) static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { @@ -140,7 +140,7 @@ static inline void set_pte(pte_t *ptep, pte_t pteval) } #endif } -#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) +#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval) static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { diff --git a/include/asm-mips/prctl.h b/include/asm-mips/prctl.h index 4aaaff670361..8121a9a75bfd 100644 --- a/include/asm-mips/prctl.h +++ b/include/asm-mips/prctl.h @@ -36,6 +36,6 @@ struct prda { #define t_sys prda_sys -ptrdiff_t prctl (int op, int v1, int v2); +ptrdiff_t prctl(int op, int v1, int v2); #endif diff --git a/include/asm-mips/qemu.h b/include/asm-mips/qemu.h index 531caf44560c..487ced4a40de 100644 --- a/include/asm-mips/qemu.h +++ b/include/asm-mips/qemu.h @@ -12,7 +12,7 @@ * Interrupt numbers */ #define Q_PIC_IRQ_BASE 0 -#define Q_COUNT_COMPARE_IRQ 16 +#define Q_COUNT_COMPARE_IRQ 23 /* * Qemu clock rate. Unlike on real MIPS this has no relation to the diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h index 3c8e3c8d1a9a..2b8466ffd3ca 100644 --- a/include/asm-mips/r4kcache.h +++ b/include/asm-mips/r4kcache.h @@ -354,7 +354,7 @@ static inline void blast_##pfx##cache##lsize(void) \ \ for (ws = 0; ws < ws_end; ws += ws_inc) \ for (addr = start; addr < end; addr += lsize * 32) \ - cache##lsize##_unroll32(addr|ws,indexop); \ + cache##lsize##_unroll32(addr|ws, indexop); \ \ __##pfx##flush_epilogue \ } \ @@ -367,7 +367,7 @@ static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \ __##pfx##flush_prologue \ \ do { \ - cache##lsize##_unroll32(start,hitop); \ + cache##lsize##_unroll32(start, hitop); \ start += lsize * 32; \ } while (start < end); \ \ @@ -388,7 +388,7 @@ static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \ for (ws = 0; ws < ws_end; ws += ws_inc) \ for (addr = start; addr < end; addr += lsize * 32) \ - cache##lsize##_unroll32(addr|ws,indexop); \ + cache##lsize##_unroll32(addr|ws, indexop); \ \ __##pfx##flush_epilogue \ } diff --git a/include/asm-mips/semaphore.h b/include/asm-mips/semaphore.h index 3d6aa7c7ea81..080daa77f867 100644 --- a/include/asm-mips/semaphore.h +++ b/include/asm-mips/semaphore.h @@ -46,23 +46,23 @@ struct semaphore { } #define __DECLARE_SEMAPHORE_GENERIC(name, count) \ - struct semaphore name = __SEMAPHORE_INITIALIZER(name,count) + struct semaphore name = __SEMAPHORE_INITIALIZER(name, count) #define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name, 1) #define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name, 0) -static inline void sema_init (struct semaphore *sem, int val) +static inline void sema_init(struct semaphore *sem, int val) { atomic_set(&sem->count, val); init_waitqueue_head(&sem->wait); } -static inline void init_MUTEX (struct semaphore *sem) +static inline void init_MUTEX(struct semaphore *sem) { sema_init(sem, 1); } -static inline void init_MUTEX_LOCKED (struct semaphore *sem) +static inline void init_MUTEX_LOCKED(struct semaphore *sem) { sema_init(sem, 0); } diff --git a/include/asm-mips/sgiarcs.h b/include/asm-mips/sgiarcs.h index 439bce7daa3a..721327f88601 100644 --- a/include/asm-mips/sgiarcs.h +++ b/include/asm-mips/sgiarcs.h @@ -13,7 +13,7 @@ #define _ASM_SGIARCS_H #include <asm/types.h> -#include <asm/arc/types.h> +#include <asm/fw/arc/types.h> /* Various ARCS error codes. */ #define PROM_ESUCCESS 0x00 @@ -369,8 +369,8 @@ struct linux_smonblock { #if defined(CONFIG_64BIT) && defined(CONFIG_ARC32) #define __arc_clobbers \ - "$2","$3" /* ... */, "$8","$9","$10","$11", \ - "$12","$13","$14","$15","$16","$24","$25","$31" + "$2", "$3" /* ... */, "$8", "$9", "$10", "$11", \ + "$12", "$13", "$14", "$15", "$16", "$24", "$25", "$31" #define ARC_CALL0(dest) \ ({ long __res; \ @@ -382,11 +382,11 @@ struct linux_smonblock { "move\t%0, $2" \ : "=r" (__res), "=r" (__vec) \ : "1" (__vec) \ - : __arc_clobbers, "$4","$5","$6","$7"); \ + : __arc_clobbers, "$4", "$5", "$6", "$7"); \ (unsigned long) __res; \ }) -#define ARC_CALL1(dest,a1) \ +#define ARC_CALL1(dest, a1) \ ({ long __res; \ register signed int __a1 __asm__("$4") = (int) (long) (a1); \ long __vec = (long) romvec->dest; \ @@ -397,11 +397,11 @@ struct linux_smonblock { "move\t%0, $2" \ : "=r" (__res), "=r" (__vec) \ : "1" (__vec), "r" (__a1) \ - : __arc_clobbers, "$5","$6","$7"); \ + : __arc_clobbers, "$5", "$6", "$7"); \ (unsigned long) __res; \ }) -#define ARC_CALL2(dest,a1,a2) \ +#define ARC_CALL2(dest, a1, a2) \ ({ long __res; \ register signed int __a1 __asm__("$4") = (int) (long) (a1); \ register signed int __a2 __asm__("$5") = (int) (long) (a2); \ @@ -413,11 +413,11 @@ struct linux_smonblock { "move\t%0, $2" \ : "=r" (__res), "=r" (__vec) \ : "1" (__vec), "r" (__a1), "r" (__a2) \ - : __arc_clobbers, "$6","$7"); \ + : __arc_clobbers, "$6", "$7"); \ __res; \ }) -#define ARC_CALL3(dest,a1,a2,a3) \ +#define ARC_CALL3(dest, a1, a2, a3) \ ({ long __res; \ register signed int __a1 __asm__("$4") = (int) (long) (a1); \ register signed int __a2 __asm__("$5") = (int) (long) (a2); \ @@ -434,7 +434,7 @@ struct linux_smonblock { __res; \ }) -#define ARC_CALL4(dest,a1,a2,a3,a4) \ +#define ARC_CALL4(dest, a1, a2, a3, a4) \ ({ long __res; \ register signed int __a1 __asm__("$4") = (int) (long) (a1); \ register signed int __a2 __asm__("$5") = (int) (long) (a2); \ @@ -453,7 +453,7 @@ struct linux_smonblock { __res; \ }) -#define ARC_CALL5(dest,a1,a2,a3,a4,a5) \ +#define ARC_CALL5(dest, a1, a2, a3, a4, a5) \ ({ long __res; \ register signed int __a1 __asm__("$4") = (int) (long) (a1); \ register signed int __a2 __asm__("$5") = (int) (long) (a2); \ @@ -468,8 +468,8 @@ struct linux_smonblock { "daddu\t$29, 32\n\t" \ "move\t%0, $2" \ : "=r" (__res), "=r" (__vec) \ - : "1" (__vec), \ - "r" (__a1), "r" (__a2), "r" (__a3), "r" (__a4), \ + : "1" (__vec), \ + "r" (__a1), "r" (__a2), "r" (__a3), "r" (__a4), \ "r" (__a5) \ : __arc_clobbers); \ __res; \ @@ -488,7 +488,7 @@ struct linux_smonblock { __res; \ }) -#define ARC_CALL1(dest,a1) \ +#define ARC_CALL1(dest, a1) \ ({ long __res; \ long __a1 = (long) (a1); \ long (*__vec)(long) = (void *) romvec->dest; \ @@ -497,7 +497,7 @@ struct linux_smonblock { __res; \ }) -#define ARC_CALL2(dest,a1,a2) \ +#define ARC_CALL2(dest, a1, a2) \ ({ long __res; \ long __a1 = (long) (a1); \ long __a2 = (long) (a2); \ @@ -507,7 +507,7 @@ struct linux_smonblock { __res; \ }) -#define ARC_CALL3(dest,a1,a2,a3) \ +#define ARC_CALL3(dest, a1, a2, a3) \ ({ long __res; \ long __a1 = (long) (a1); \ long __a2 = (long) (a2); \ @@ -518,7 +518,7 @@ struct linux_smonblock { __res; \ }) -#define ARC_CALL4(dest,a1,a2,a3,a4) \ +#define ARC_CALL4(dest, a1, a2, a3, a4) \ ({ long __res; \ long __a1 = (long) (a1); \ long __a2 = (long) (a2); \ @@ -530,7 +530,7 @@ struct linux_smonblock { __res; \ }) -#define ARC_CALL5(dest,a1,a2,a3,a4,a5) \ +#define ARC_CALL5(dest, a1, a2, a3, a4, a5) \ ({ long __res; \ long __a1 = (long) (a1); \ long __a2 = (long) (a2); \ diff --git a/include/asm-mips/sibyte/bcm1480_int.h b/include/asm-mips/sibyte/bcm1480_int.h index c0d5206020fd..6109557c14e9 100644 --- a/include/asm-mips/sibyte/bcm1480_int.h +++ b/include/asm-mips/sibyte/bcm1480_int.h @@ -157,7 +157,7 @@ * Mask values for each interrupt */ -#define _BCM1480_INT_MASK(w,n) _SB_MAKEMASK(w,((n) & 0x3F)) +#define _BCM1480_INT_MASK(w, n) _SB_MAKEMASK(w, ((n) & 0x3F)) #define _BCM1480_INT_MASK1(n) _SB_MAKEMASK1(((n) & 0x3F)) #define _BCM1480_INT_OFFSET(n) (((n) & 0x40) << 6) @@ -196,7 +196,7 @@ #define M_BCM1480_INT_PMI_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH) #define M_BCM1480_INT_PMO_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW) #define M_BCM1480_INT_PMO_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH) -#define M_BCM1480_INT_MBOX_ALL _BCM1480_INT_MASK(8,K_BCM1480_INT_MBOX_0_0) +#define M_BCM1480_INT_MBOX_ALL _BCM1480_INT_MASK(8, K_BCM1480_INT_MBOX_0_0) #define M_BCM1480_INT_MBOX_0_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0) #define M_BCM1480_INT_MBOX_0_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1) #define M_BCM1480_INT_MBOX_0_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2) @@ -269,9 +269,9 @@ */ #define S_BCM1480_INT_HT_INTMSG 0 -#define M_BCM1480_INT_HT_INTMSG _SB_MAKEMASK(3,S_BCM1480_INT_HT_INTMSG) -#define V_BCM1480_INT_HT_INTMSG(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_INTMSG) -#define G_BCM1480_INT_HT_INTMSG(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_INTMSG,M_BCM1480_INT_HT_INTMSG) +#define M_BCM1480_INT_HT_INTMSG _SB_MAKEMASK(3, S_BCM1480_INT_HT_INTMSG) +#define V_BCM1480_INT_HT_INTMSG(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTMSG) +#define G_BCM1480_INT_HT_INTMSG(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_INTMSG, M_BCM1480_INT_HT_INTMSG) #define K_BCM1480_INT_HT_INTMSG_FIXED 0 #define K_BCM1480_INT_HT_INTMSG_ARBITRATED 1 @@ -291,14 +291,14 @@ #define V_BCM1480_INT_HT_LOGICALDEST M_BCM1480_INT_HT_DESTMODE #define S_BCM1480_INT_HT_INTDEST 5 -#define M_BCM1480_INT_HT_INTDEST _SB_MAKEMASK(8,S_BCM1480_INT_HT_INTDEST) -#define V_BCM1480_INT_HT_INTDEST(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_INTDEST) -#define G_BCM1480_INT_HT_INTDEST(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_INTDEST,M_BCM1480_INT_HT_INTDEST) +#define M_BCM1480_INT_HT_INTDEST _SB_MAKEMASK(8, S_BCM1480_INT_HT_INTDEST) +#define V_BCM1480_INT_HT_INTDEST(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTDEST) +#define G_BCM1480_INT_HT_INTDEST(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_INTDEST, M_BCM1480_INT_HT_INTDEST) #define S_BCM1480_INT_HT_VECTOR 13 -#define M_BCM1480_INT_HT_VECTOR _SB_MAKEMASK(8,S_BCM1480_INT_HT_VECTOR) -#define V_BCM1480_INT_HT_VECTOR(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_VECTOR) -#define G_BCM1480_INT_HT_VECTOR(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_VECTOR,M_BCM1480_INT_HT_VECTOR) +#define M_BCM1480_INT_HT_VECTOR _SB_MAKEMASK(8, S_BCM1480_INT_HT_VECTOR) +#define V_BCM1480_INT_HT_VECTOR(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_VECTOR) +#define G_BCM1480_INT_HT_VECTOR(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_VECTOR, M_BCM1480_INT_HT_VECTOR) /* * Vector prefix (Table 4-7) diff --git a/include/asm-mips/sibyte/bcm1480_l2c.h b/include/asm-mips/sibyte/bcm1480_l2c.h index 886b099565e6..fd75817f7ac4 100644 --- a/include/asm-mips/sibyte/bcm1480_l2c.h +++ b/include/asm-mips/sibyte/bcm1480_l2c.h @@ -40,22 +40,22 @@ */ #define S_BCM1480_L2C_MGMT_INDEX 5 -#define M_BCM1480_L2C_MGMT_INDEX _SB_MAKEMASK(12,S_BCM1480_L2C_MGMT_INDEX) -#define V_BCM1480_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_INDEX) -#define G_BCM1480_L2C_MGMT_INDEX(x) _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_INDEX,M_BCM1480_L2C_MGMT_INDEX) +#define M_BCM1480_L2C_MGMT_INDEX _SB_MAKEMASK(12, S_BCM1480_L2C_MGMT_INDEX) +#define V_BCM1480_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_INDEX) +#define G_BCM1480_L2C_MGMT_INDEX(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_INDEX, M_BCM1480_L2C_MGMT_INDEX) #define S_BCM1480_L2C_MGMT_WAY 17 -#define M_BCM1480_L2C_MGMT_WAY _SB_MAKEMASK(3,S_BCM1480_L2C_MGMT_WAY) -#define V_BCM1480_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_WAY) -#define G_BCM1480_L2C_MGMT_WAY(x) _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_WAY,M_BCM1480_L2C_MGMT_WAY) +#define M_BCM1480_L2C_MGMT_WAY _SB_MAKEMASK(3, S_BCM1480_L2C_MGMT_WAY) +#define V_BCM1480_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_WAY) +#define G_BCM1480_L2C_MGMT_WAY(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_WAY, M_BCM1480_L2C_MGMT_WAY) #define M_BCM1480_L2C_MGMT_DIRTY _SB_MAKEMASK1(20) #define M_BCM1480_L2C_MGMT_VALID _SB_MAKEMASK1(21) #define S_BCM1480_L2C_MGMT_ECC_DIAG 22 -#define M_BCM1480_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2,S_BCM1480_L2C_MGMT_ECC_DIAG) -#define V_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_ECC_DIAG) -#define G_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_ECC_DIAG,M_BCM1480_L2C_MGMT_ECC_DIAG) +#define M_BCM1480_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2, S_BCM1480_L2C_MGMT_ECC_DIAG) +#define V_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG) +#define G_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG, M_BCM1480_L2C_MGMT_ECC_DIAG) #define A_BCM1480_L2C_MGMT_TAG_BASE 0x00D0000000 @@ -68,36 +68,36 @@ */ #define S_BCM1480_L2C_TAG_MBZ 0 -#define M_BCM1480_L2C_TAG_MBZ _SB_MAKEMASK(5,S_BCM1480_L2C_TAG_MBZ) +#define M_BCM1480_L2C_TAG_MBZ _SB_MAKEMASK(5, S_BCM1480_L2C_TAG_MBZ) #define S_BCM1480_L2C_TAG_INDEX 5 -#define M_BCM1480_L2C_TAG_INDEX _SB_MAKEMASK(12,S_BCM1480_L2C_TAG_INDEX) -#define V_BCM1480_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_INDEX) -#define G_BCM1480_L2C_TAG_INDEX(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_INDEX,M_BCM1480_L2C_TAG_INDEX) +#define M_BCM1480_L2C_TAG_INDEX _SB_MAKEMASK(12, S_BCM1480_L2C_TAG_INDEX) +#define V_BCM1480_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_INDEX) +#define G_BCM1480_L2C_TAG_INDEX(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_INDEX, M_BCM1480_L2C_TAG_INDEX) /* Note that index bit 16 is also tag bit 40 */ #define S_BCM1480_L2C_TAG_TAG 17 -#define M_BCM1480_L2C_TAG_TAG _SB_MAKEMASK(23,S_BCM1480_L2C_TAG_TAG) -#define V_BCM1480_L2C_TAG_TAG(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_TAG) -#define G_BCM1480_L2C_TAG_TAG(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_TAG,M_BCM1480_L2C_TAG_TAG) +#define M_BCM1480_L2C_TAG_TAG _SB_MAKEMASK(23, S_BCM1480_L2C_TAG_TAG) +#define V_BCM1480_L2C_TAG_TAG(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_TAG) +#define G_BCM1480_L2C_TAG_TAG(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_TAG, M_BCM1480_L2C_TAG_TAG) #define S_BCM1480_L2C_TAG_ECC 40 -#define M_BCM1480_L2C_TAG_ECC _SB_MAKEMASK(6,S_BCM1480_L2C_TAG_ECC) -#define V_BCM1480_L2C_TAG_ECC(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_ECC) -#define G_BCM1480_L2C_TAG_ECC(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_ECC,M_BCM1480_L2C_TAG_ECC) +#define M_BCM1480_L2C_TAG_ECC _SB_MAKEMASK(6, S_BCM1480_L2C_TAG_ECC) +#define V_BCM1480_L2C_TAG_ECC(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_ECC) +#define G_BCM1480_L2C_TAG_ECC(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_ECC, M_BCM1480_L2C_TAG_ECC) #define S_BCM1480_L2C_TAG_WAY 46 -#define M_BCM1480_L2C_TAG_WAY _SB_MAKEMASK(3,S_BCM1480_L2C_TAG_WAY) -#define V_BCM1480_L2C_TAG_WAY(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_WAY) -#define G_BCM1480_L2C_TAG_WAY(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_WAY,M_BCM1480_L2C_TAG_WAY) +#define M_BCM1480_L2C_TAG_WAY _SB_MAKEMASK(3, S_BCM1480_L2C_TAG_WAY) +#define V_BCM1480_L2C_TAG_WAY(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_WAY) +#define G_BCM1480_L2C_TAG_WAY(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_WAY, M_BCM1480_L2C_TAG_WAY) #define M_BCM1480_L2C_TAG_DIRTY _SB_MAKEMASK1(49) #define M_BCM1480_L2C_TAG_VALID _SB_MAKEMASK1(50) #define S_BCM1480_L2C_DATA_ECC 51 -#define M_BCM1480_L2C_DATA_ECC _SB_MAKEMASK(10,S_BCM1480_L2C_DATA_ECC) -#define V_BCM1480_L2C_DATA_ECC(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_DATA_ECC) -#define G_BCM1480_L2C_DATA_ECC(x) _SB_GETVALUE(x,S_BCM1480_L2C_DATA_ECC,M_BCM1480_L2C_DATA_ECC) +#define M_BCM1480_L2C_DATA_ECC _SB_MAKEMASK(10, S_BCM1480_L2C_DATA_ECC) +#define V_BCM1480_L2C_DATA_ECC(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_DATA_ECC) +#define G_BCM1480_L2C_DATA_ECC(x) _SB_GETVALUE(x, S_BCM1480_L2C_DATA_ECC, M_BCM1480_L2C_DATA_ECC) /* @@ -105,24 +105,24 @@ */ #define S_BCM1480_L2C_MISC0_WAY_REMOTE 0 -#define M_BCM1480_L2C_MISC0_WAY_REMOTE _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_REMOTE) -#define G_BCM1480_L2C_MISC0_WAY_REMOTE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_REMOTE,M_BCM1480_L2C_MISC0_WAY_REMOTE) +#define M_BCM1480_L2C_MISC0_WAY_REMOTE _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_REMOTE) +#define G_BCM1480_L2C_MISC0_WAY_REMOTE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_REMOTE, M_BCM1480_L2C_MISC0_WAY_REMOTE) #define S_BCM1480_L2C_MISC0_WAY_LOCAL 8 -#define M_BCM1480_L2C_MISC0_WAY_LOCAL _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_LOCAL) -#define G_BCM1480_L2C_MISC0_WAY_LOCAL(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_LOCAL,M_BCM1480_L2C_MISC0_WAY_LOCAL) +#define M_BCM1480_L2C_MISC0_WAY_LOCAL _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_LOCAL) +#define G_BCM1480_L2C_MISC0_WAY_LOCAL(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_LOCAL, M_BCM1480_L2C_MISC0_WAY_LOCAL) #define S_BCM1480_L2C_MISC0_WAY_ENABLE 16 -#define M_BCM1480_L2C_MISC0_WAY_ENABLE _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_ENABLE) -#define G_BCM1480_L2C_MISC0_WAY_ENABLE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_ENABLE,M_BCM1480_L2C_MISC0_WAY_ENABLE) +#define M_BCM1480_L2C_MISC0_WAY_ENABLE _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_ENABLE) +#define G_BCM1480_L2C_MISC0_WAY_ENABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_ENABLE, M_BCM1480_L2C_MISC0_WAY_ENABLE) #define S_BCM1480_L2C_MISC0_CACHE_DISABLE 24 -#define M_BCM1480_L2C_MISC0_CACHE_DISABLE _SB_MAKEMASK(2,S_BCM1480_L2C_MISC0_CACHE_DISABLE) -#define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_CACHE_DISABLE,M_BCM1480_L2C_MISC0_CACHE_DISABLE) +#define M_BCM1480_L2C_MISC0_CACHE_DISABLE _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_DISABLE) +#define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_DISABLE, M_BCM1480_L2C_MISC0_CACHE_DISABLE) #define S_BCM1480_L2C_MISC0_CACHE_QUAD 26 -#define M_BCM1480_L2C_MISC0_CACHE_QUAD _SB_MAKEMASK(2,S_BCM1480_L2C_MISC0_CACHE_QUAD) -#define G_BCM1480_L2C_MISC0_CACHE_QUAD(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_CACHE_QUAD,M_BCM1480_L2C_MISC0_CACHE_QUAD) +#define M_BCM1480_L2C_MISC0_CACHE_QUAD _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_QUAD) +#define G_BCM1480_L2C_MISC0_CACHE_QUAD(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_QUAD, M_BCM1480_L2C_MISC0_CACHE_QUAD) #define S_BCM1480_L2C_MISC0_MC_PRIORITY 30 #define M_BCM1480_L2C_MISC0_MC_PRIORITY _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY) @@ -136,24 +136,24 @@ */ #define S_BCM1480_L2C_MISC1_WAY_AGENT_0 0 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_0 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_0) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_0,M_BCM1480_L2C_MISC1_WAY_AGENT_0) +#define M_BCM1480_L2C_MISC1_WAY_AGENT_0 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_0) +#define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_0, M_BCM1480_L2C_MISC1_WAY_AGENT_0) #define S_BCM1480_L2C_MISC1_WAY_AGENT_1 8 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_1 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_1) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_1,M_BCM1480_L2C_MISC1_WAY_AGENT_1) +#define M_BCM1480_L2C_MISC1_WAY_AGENT_1 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_1) +#define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_1, M_BCM1480_L2C_MISC1_WAY_AGENT_1) #define S_BCM1480_L2C_MISC1_WAY_AGENT_2 16 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_2 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_2) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_2,M_BCM1480_L2C_MISC1_WAY_AGENT_2) +#define M_BCM1480_L2C_MISC1_WAY_AGENT_2 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_2) +#define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_2, M_BCM1480_L2C_MISC1_WAY_AGENT_2) #define S_BCM1480_L2C_MISC1_WAY_AGENT_3 24 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_3 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_3) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_3,M_BCM1480_L2C_MISC1_WAY_AGENT_3) +#define M_BCM1480_L2C_MISC1_WAY_AGENT_3 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_3) +#define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_3, M_BCM1480_L2C_MISC1_WAY_AGENT_3) #define S_BCM1480_L2C_MISC1_WAY_AGENT_4 32 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_4 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_4) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_4,M_BCM1480_L2C_MISC1_WAY_AGENT_4) +#define M_BCM1480_L2C_MISC1_WAY_AGENT_4 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_4) +#define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_4, M_BCM1480_L2C_MISC1_WAY_AGENT_4) /* @@ -161,16 +161,16 @@ */ #define S_BCM1480_L2C_MISC2_WAY_AGENT_8 0 -#define M_BCM1480_L2C_MISC2_WAY_AGENT_8 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_8) -#define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_8,M_BCM1480_L2C_MISC2_WAY_AGENT_8) +#define M_BCM1480_L2C_MISC2_WAY_AGENT_8 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_8) +#define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_8, M_BCM1480_L2C_MISC2_WAY_AGENT_8) #define S_BCM1480_L2C_MISC2_WAY_AGENT_9 8 -#define M_BCM1480_L2C_MISC2_WAY_AGENT_9 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_9) -#define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_9,M_BCM1480_L2C_MISC2_WAY_AGENT_9) +#define M_BCM1480_L2C_MISC2_WAY_AGENT_9 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_9) +#define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_9, M_BCM1480_L2C_MISC2_WAY_AGENT_9) #define S_BCM1480_L2C_MISC2_WAY_AGENT_A 16 -#define M_BCM1480_L2C_MISC2_WAY_AGENT_A _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_A) -#define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_A,M_BCM1480_L2C_MISC2_WAY_AGENT_A) +#define M_BCM1480_L2C_MISC2_WAY_AGENT_A _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_A) +#define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_A, M_BCM1480_L2C_MISC2_WAY_AGENT_A) #endif /* _BCM1480_L2C_H */ diff --git a/include/asm-mips/sibyte/bcm1480_mc.h b/include/asm-mips/sibyte/bcm1480_mc.h index a6a437451da4..f26a41a82b59 100644 --- a/include/asm-mips/sibyte/bcm1480_mc.h +++ b/include/asm-mips/sibyte/bcm1480_mc.h @@ -40,27 +40,27 @@ */ #define S_BCM1480_MC_INTLV0 0 -#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0) -#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0) -#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0) +#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0) +#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0) +#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0) #define V_BCM1480_MC_INTLV0_DEFAULT V_BCM1480_MC_INTLV0(0) #define S_BCM1480_MC_INTLV1 8 -#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1) -#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1) -#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1) +#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1) +#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1) +#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1) #define V_BCM1480_MC_INTLV1_DEFAULT V_BCM1480_MC_INTLV1(0) #define S_BCM1480_MC_INTLV2 16 -#define M_BCM1480_MC_INTLV2 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV2) -#define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV2) -#define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV2,M_BCM1480_MC_INTLV2) +#define M_BCM1480_MC_INTLV2 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV2) +#define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV2) +#define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV2, M_BCM1480_MC_INTLV2) #define V_BCM1480_MC_INTLV2_DEFAULT V_BCM1480_MC_INTLV2(0) #define S_BCM1480_MC_CS_MODE 32 -#define M_BCM1480_MC_CS_MODE _SB_MAKEMASK(8,S_BCM1480_MC_CS_MODE) -#define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS_MODE) -#define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_CS_MODE,M_BCM1480_MC_CS_MODE) +#define M_BCM1480_MC_CS_MODE _SB_MAKEMASK(8, S_BCM1480_MC_CS_MODE) +#define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS_MODE) +#define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_CS_MODE, M_BCM1480_MC_CS_MODE) #define V_BCM1480_MC_CS_MODE_DEFAULT V_BCM1480_MC_CS_MODE(0) #define V_BCM1480_MC_CONFIG_DEFAULT (V_BCM1480_MC_INTLV0_DEFAULT | \ @@ -81,131 +81,131 @@ */ #define S_BCM1480_MC_CS0_START 0 -#define M_BCM1480_MC_CS0_START _SB_MAKEMASK(12,S_BCM1480_MC_CS0_START) -#define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_START) -#define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0_START,M_BCM1480_MC_CS0_START) +#define M_BCM1480_MC_CS0_START _SB_MAKEMASK(12, S_BCM1480_MC_CS0_START) +#define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_START) +#define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_START, M_BCM1480_MC_CS0_START) #define S_BCM1480_MC_CS1_START 16 -#define M_BCM1480_MC_CS1_START _SB_MAKEMASK(12,S_BCM1480_MC_CS1_START) -#define V_BCM1480_MC_CS1_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_START) -#define G_BCM1480_MC_CS1_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS1_START,M_BCM1480_MC_CS1_START) +#define M_BCM1480_MC_CS1_START _SB_MAKEMASK(12, S_BCM1480_MC_CS1_START) +#define V_BCM1480_MC_CS1_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_START) +#define G_BCM1480_MC_CS1_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS1_START, M_BCM1480_MC_CS1_START) #define S_BCM1480_MC_CS2_START 32 -#define M_BCM1480_MC_CS2_START _SB_MAKEMASK(12,S_BCM1480_MC_CS2_START) -#define V_BCM1480_MC_CS2_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_START) -#define G_BCM1480_MC_CS2_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS2_START,M_BCM1480_MC_CS2_START) +#define M_BCM1480_MC_CS2_START _SB_MAKEMASK(12, S_BCM1480_MC_CS2_START) +#define V_BCM1480_MC_CS2_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_START) +#define G_BCM1480_MC_CS2_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS2_START, M_BCM1480_MC_CS2_START) #define S_BCM1480_MC_CS3_START 48 -#define M_BCM1480_MC_CS3_START _SB_MAKEMASK(12,S_BCM1480_MC_CS3_START) -#define V_BCM1480_MC_CS3_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_START) -#define G_BCM1480_MC_CS3_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS3_START,M_BCM1480_MC_CS3_START) +#define M_BCM1480_MC_CS3_START _SB_MAKEMASK(12, S_BCM1480_MC_CS3_START) +#define V_BCM1480_MC_CS3_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_START) +#define G_BCM1480_MC_CS3_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS3_START, M_BCM1480_MC_CS3_START) /* * Chip Select End Address Register (Table 83) */ #define S_BCM1480_MC_CS0_END 0 -#define M_BCM1480_MC_CS0_END _SB_MAKEMASK(12,S_BCM1480_MC_CS0_END) -#define V_BCM1480_MC_CS0_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_END) -#define G_BCM1480_MC_CS0_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0_END,M_BCM1480_MC_CS0_END) +#define M_BCM1480_MC_CS0_END _SB_MAKEMASK(12, S_BCM1480_MC_CS0_END) +#define V_BCM1480_MC_CS0_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_END) +#define G_BCM1480_MC_CS0_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_END, M_BCM1480_MC_CS0_END) #define S_BCM1480_MC_CS1_END 16 -#define M_BCM1480_MC_CS1_END _SB_MAKEMASK(12,S_BCM1480_MC_CS1_END) -#define V_BCM1480_MC_CS1_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_END) -#define G_BCM1480_MC_CS1_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS1_END,M_BCM1480_MC_CS1_END) +#define M_BCM1480_MC_CS1_END _SB_MAKEMASK(12, S_BCM1480_MC_CS1_END) +#define V_BCM1480_MC_CS1_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_END) +#define G_BCM1480_MC_CS1_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS1_END, M_BCM1480_MC_CS1_END) #define S_BCM1480_MC_CS2_END 32 -#define M_BCM1480_MC_CS2_END _SB_MAKEMASK(12,S_BCM1480_MC_CS2_END) -#define V_BCM1480_MC_CS2_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_END) -#define G_BCM1480_MC_CS2_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS2_END,M_BCM1480_MC_CS2_END) +#define M_BCM1480_MC_CS2_END _SB_MAKEMASK(12, S_BCM1480_MC_CS2_END) +#define V_BCM1480_MC_CS2_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_END) +#define G_BCM1480_MC_CS2_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS2_END, M_BCM1480_MC_CS2_END) #define S_BCM1480_MC_CS3_END 48 -#define M_BCM1480_MC_CS3_END _SB_MAKEMASK(12,S_BCM1480_MC_CS3_END) -#define V_BCM1480_MC_CS3_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_END) -#define G_BCM1480_MC_CS3_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS3_END,M_BCM1480_MC_CS3_END) +#define M_BCM1480_MC_CS3_END _SB_MAKEMASK(12, S_BCM1480_MC_CS3_END) +#define V_BCM1480_MC_CS3_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_END) +#define G_BCM1480_MC_CS3_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS3_END, M_BCM1480_MC_CS3_END) /* * Row Address Bit Select Register 0 (Table 84) */ #define S_BCM1480_MC_ROW00 0 -#define M_BCM1480_MC_ROW00 _SB_MAKEMASK(6,S_BCM1480_MC_ROW00) -#define V_BCM1480_MC_ROW00(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW00) -#define G_BCM1480_MC_ROW00(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW00,M_BCM1480_MC_ROW00) +#define M_BCM1480_MC_ROW00 _SB_MAKEMASK(6, S_BCM1480_MC_ROW00) +#define V_BCM1480_MC_ROW00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW00) +#define G_BCM1480_MC_ROW00(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW00, M_BCM1480_MC_ROW00) #define S_BCM1480_MC_ROW01 8 -#define M_BCM1480_MC_ROW01 _SB_MAKEMASK(6,S_BCM1480_MC_ROW01) -#define V_BCM1480_MC_ROW01(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW01) -#define G_BCM1480_MC_ROW01(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW01,M_BCM1480_MC_ROW01) +#define M_BCM1480_MC_ROW01 _SB_MAKEMASK(6, S_BCM1480_MC_ROW01) +#define V_BCM1480_MC_ROW01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW01) +#define G_BCM1480_MC_ROW01(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW01, M_BCM1480_MC_ROW01) #define S_BCM1480_MC_ROW02 16 -#define M_BCM1480_MC_ROW02 _SB_MAKEMASK(6,S_BCM1480_MC_ROW02) -#define V_BCM1480_MC_ROW02(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW02) -#define G_BCM1480_MC_ROW02(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW02,M_BCM1480_MC_ROW02) +#define M_BCM1480_MC_ROW02 _SB_MAKEMASK(6, S_BCM1480_MC_ROW02) +#define V_BCM1480_MC_ROW02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW02) +#define G_BCM1480_MC_ROW02(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW02, M_BCM1480_MC_ROW02) #define S_BCM1480_MC_ROW03 24 -#define M_BCM1480_MC_ROW03 _SB_MAKEMASK(6,S_BCM1480_MC_ROW03) -#define V_BCM1480_MC_ROW03(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW03) -#define G_BCM1480_MC_ROW03(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW03,M_BCM1480_MC_ROW03) +#define M_BCM1480_MC_ROW03 _SB_MAKEMASK(6, S_BCM1480_MC_ROW03) +#define V_BCM1480_MC_ROW03(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW03) +#define G_BCM1480_MC_ROW03(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW03, M_BCM1480_MC_ROW03) #define S_BCM1480_MC_ROW04 32 -#define M_BCM1480_MC_ROW04 _SB_MAKEMASK(6,S_BCM1480_MC_ROW04) -#define V_BCM1480_MC_ROW04(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW04) -#define G_BCM1480_MC_ROW04(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW04,M_BCM1480_MC_ROW04) +#define M_BCM1480_MC_ROW04 _SB_MAKEMASK(6, S_BCM1480_MC_ROW04) +#define V_BCM1480_MC_ROW04(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW04) +#define G_BCM1480_MC_ROW04(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW04, M_BCM1480_MC_ROW04) #define S_BCM1480_MC_ROW05 40 -#define M_BCM1480_MC_ROW05 _SB_MAKEMASK(6,S_BCM1480_MC_ROW05) -#define V_BCM1480_MC_ROW05(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW05) -#define G_BCM1480_MC_ROW05(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW05,M_BCM1480_MC_ROW05) +#define M_BCM1480_MC_ROW05 _SB_MAKEMASK(6, S_BCM1480_MC_ROW05) +#define V_BCM1480_MC_ROW05(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW05) +#define G_BCM1480_MC_ROW05(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW05, M_BCM1480_MC_ROW05) #define S_BCM1480_MC_ROW06 48 -#define M_BCM1480_MC_ROW06 _SB_MAKEMASK(6,S_BCM1480_MC_ROW06) -#define V_BCM1480_MC_ROW06(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW06) -#define G_BCM1480_MC_ROW06(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW06,M_BCM1480_MC_ROW06) +#define M_BCM1480_MC_ROW06 _SB_MAKEMASK(6, S_BCM1480_MC_ROW06) +#define V_BCM1480_MC_ROW06(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW06) +#define G_BCM1480_MC_ROW06(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW06, M_BCM1480_MC_ROW06) #define S_BCM1480_MC_ROW07 56 -#define M_BCM1480_MC_ROW07 _SB_MAKEMASK(6,S_BCM1480_MC_ROW07) -#define V_BCM1480_MC_ROW07(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW07) -#define G_BCM1480_MC_ROW07(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW07,M_BCM1480_MC_ROW07) +#define M_BCM1480_MC_ROW07 _SB_MAKEMASK(6, S_BCM1480_MC_ROW07) +#define V_BCM1480_MC_ROW07(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW07) +#define G_BCM1480_MC_ROW07(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW07, M_BCM1480_MC_ROW07) /* * Row Address Bit Select Register 1 (Table 85) */ #define S_BCM1480_MC_ROW08 0 -#define M_BCM1480_MC_ROW08 _SB_MAKEMASK(6,S_BCM1480_MC_ROW08) -#define V_BCM1480_MC_ROW08(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW08) -#define G_BCM1480_MC_ROW08(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW08,M_BCM1480_MC_ROW08) +#define M_BCM1480_MC_ROW08 _SB_MAKEMASK(6, S_BCM1480_MC_ROW08) +#define V_BCM1480_MC_ROW08(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW08) +#define G_BCM1480_MC_ROW08(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW08, M_BCM1480_MC_ROW08) #define S_BCM1480_MC_ROW09 8 -#define M_BCM1480_MC_ROW09 _SB_MAKEMASK(6,S_BCM1480_MC_ROW09) -#define V_BCM1480_MC_ROW09(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW09) -#define G_BCM1480_MC_ROW09(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW09,M_BCM1480_MC_ROW09) +#define M_BCM1480_MC_ROW09 _SB_MAKEMASK(6, S_BCM1480_MC_ROW09) +#define V_BCM1480_MC_ROW09(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW09) +#define G_BCM1480_MC_ROW09(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW09, M_BCM1480_MC_ROW09) #define S_BCM1480_MC_ROW10 16 -#define M_BCM1480_MC_ROW10 _SB_MAKEMASK(6,S_BCM1480_MC_ROW10) -#define V_BCM1480_MC_ROW10(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW10) -#define G_BCM1480_MC_ROW10(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW10,M_BCM1480_MC_ROW10) +#define M_BCM1480_MC_ROW10 _SB_MAKEMASK(6, S_BCM1480_MC_ROW10) +#define V_BCM1480_MC_ROW10(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW10) +#define G_BCM1480_MC_ROW10(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW10, M_BCM1480_MC_ROW10) #define S_BCM1480_MC_ROW11 24 -#define M_BCM1480_MC_ROW11 _SB_MAKEMASK(6,S_BCM1480_MC_ROW11) -#define V_BCM1480_MC_ROW11(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW11) -#define G_BCM1480_MC_ROW11(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW11,M_BCM1480_MC_ROW11) +#define M_BCM1480_MC_ROW11 _SB_MAKEMASK(6, S_BCM1480_MC_ROW11) +#define V_BCM1480_MC_ROW11(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW11) +#define G_BCM1480_MC_ROW11(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW11, M_BCM1480_MC_ROW11) #define S_BCM1480_MC_ROW12 32 -#define M_BCM1480_MC_ROW12 _SB_MAKEMASK(6,S_BCM1480_MC_ROW12) -#define V_BCM1480_MC_ROW12(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW12) -#define G_BCM1480_MC_ROW12(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW12,M_BCM1480_MC_ROW12) +#define M_BCM1480_MC_ROW12 _SB_MAKEMASK(6, S_BCM1480_MC_ROW12) +#define V_BCM1480_MC_ROW12(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW12) +#define G_BCM1480_MC_ROW12(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW12, M_BCM1480_MC_ROW12) #define S_BCM1480_MC_ROW13 40 -#define M_BCM1480_MC_ROW13 _SB_MAKEMASK(6,S_BCM1480_MC_ROW13) -#define V_BCM1480_MC_ROW13(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW13) -#define G_BCM1480_MC_ROW13(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW13,M_BCM1480_MC_ROW13) +#define M_BCM1480_MC_ROW13 _SB_MAKEMASK(6, S_BCM1480_MC_ROW13) +#define V_BCM1480_MC_ROW13(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW13) +#define G_BCM1480_MC_ROW13(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW13, M_BCM1480_MC_ROW13) #define S_BCM1480_MC_ROW14 48 -#define M_BCM1480_MC_ROW14 _SB_MAKEMASK(6,S_BCM1480_MC_ROW14) -#define V_BCM1480_MC_ROW14(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW14) -#define G_BCM1480_MC_ROW14(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW14,M_BCM1480_MC_ROW14) +#define M_BCM1480_MC_ROW14 _SB_MAKEMASK(6, S_BCM1480_MC_ROW14) +#define V_BCM1480_MC_ROW14(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW14) +#define G_BCM1480_MC_ROW14(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW14, M_BCM1480_MC_ROW14) #define K_BCM1480_MC_ROWX_BIT_SPACING 8 @@ -214,80 +214,80 @@ */ #define S_BCM1480_MC_COL00 0 -#define M_BCM1480_MC_COL00 _SB_MAKEMASK(6,S_BCM1480_MC_COL00) -#define V_BCM1480_MC_COL00(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL00) -#define G_BCM1480_MC_COL00(x) _SB_GETVALUE(x,S_BCM1480_MC_COL00,M_BCM1480_MC_COL00) +#define M_BCM1480_MC_COL00 _SB_MAKEMASK(6, S_BCM1480_MC_COL00) +#define V_BCM1480_MC_COL00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL00) +#define G_BCM1480_MC_COL00(x) _SB_GETVALUE(x, S_BCM1480_MC_COL00, M_BCM1480_MC_COL00) #define S_BCM1480_MC_COL01 8 -#define M_BCM1480_MC_COL01 _SB_MAKEMASK(6,S_BCM1480_MC_COL01) -#define V_BCM1480_MC_COL01(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL01) -#define G_BCM1480_MC_COL01(x) _SB_GETVALUE(x,S_BCM1480_MC_COL01,M_BCM1480_MC_COL01) +#define M_BCM1480_MC_COL01 _SB_MAKEMASK(6, S_BCM1480_MC_COL01) +#define V_BCM1480_MC_COL01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL01) +#define G_BCM1480_MC_COL01(x) _SB_GETVALUE(x, S_BCM1480_MC_COL01, M_BCM1480_MC_COL01) #define S_BCM1480_MC_COL02 16 -#define M_BCM1480_MC_COL02 _SB_MAKEMASK(6,S_BCM1480_MC_COL02) -#define V_BCM1480_MC_COL02(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL02) -#define G_BCM1480_MC_COL02(x) _SB_GETVALUE(x,S_BCM1480_MC_COL02,M_BCM1480_MC_COL02) +#define M_BCM1480_MC_COL02 _SB_MAKEMASK(6, S_BCM1480_MC_COL02) +#define V_BCM1480_MC_COL02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL02) +#define G_BCM1480_MC_COL02(x) _SB_GETVALUE(x, S_BCM1480_MC_COL02, M_BCM1480_MC_COL02) #define S_BCM1480_MC_COL03 24 -#define M_BCM1480_MC_COL03 _SB_MAKEMASK(6,S_BCM1480_MC_COL03) -#define V_BCM1480_MC_COL03(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL03) -#define G_BCM1480_MC_COL03(x) _SB_GETVALUE(x,S_BCM1480_MC_COL03,M_BCM1480_MC_COL03) +#define M_BCM1480_MC_COL03 _SB_MAKEMASK(6, S_BCM1480_MC_COL03) +#define V_BCM1480_MC_COL03(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL03) +#define G_BCM1480_MC_COL03(x) _SB_GETVALUE(x, S_BCM1480_MC_COL03, M_BCM1480_MC_COL03) #define S_BCM1480_MC_COL04 32 -#define M_BCM1480_MC_COL04 _SB_MAKEMASK(6,S_BCM1480_MC_COL04) -#define V_BCM1480_MC_COL04(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL04) -#define G_BCM1480_MC_COL04(x) _SB_GETVALUE(x,S_BCM1480_MC_COL04,M_BCM1480_MC_COL04) +#define M_BCM1480_MC_COL04 _SB_MAKEMASK(6, S_BCM1480_MC_COL04) +#define V_BCM1480_MC_COL04(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL04) +#define G_BCM1480_MC_COL04(x) _SB_GETVALUE(x, S_BCM1480_MC_COL04, M_BCM1480_MC_COL04) #define S_BCM1480_MC_COL05 40 -#define M_BCM1480_MC_COL05 _SB_MAKEMASK(6,S_BCM1480_MC_COL05) -#define V_BCM1480_MC_COL05(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL05) -#define G_BCM1480_MC_COL05(x) _SB_GETVALUE(x,S_BCM1480_MC_COL05,M_BCM1480_MC_COL05) +#define M_BCM1480_MC_COL05 _SB_MAKEMASK(6, S_BCM1480_MC_COL05) +#define V_BCM1480_MC_COL05(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL05) +#define G_BCM1480_MC_COL05(x) _SB_GETVALUE(x, S_BCM1480_MC_COL05, M_BCM1480_MC_COL05) #define S_BCM1480_MC_COL06 48 -#define M_BCM1480_MC_COL06 _SB_MAKEMASK(6,S_BCM1480_MC_COL06) -#define V_BCM1480_MC_COL06(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL06) -#define G_BCM1480_MC_COL06(x) _SB_GETVALUE(x,S_BCM1480_MC_COL06,M_BCM1480_MC_COL06) +#define M_BCM1480_MC_COL06 _SB_MAKEMASK(6, S_BCM1480_MC_COL06) +#define V_BCM1480_MC_COL06(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL06) +#define G_BCM1480_MC_COL06(x) _SB_GETVALUE(x, S_BCM1480_MC_COL06, M_BCM1480_MC_COL06) #define S_BCM1480_MC_COL07 56 -#define M_BCM1480_MC_COL07 _SB_MAKEMASK(6,S_BCM1480_MC_COL07) -#define V_BCM1480_MC_COL07(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL07) -#define G_BCM1480_MC_COL07(x) _SB_GETVALUE(x,S_BCM1480_MC_COL07,M_BCM1480_MC_COL07) +#define M_BCM1480_MC_COL07 _SB_MAKEMASK(6, S_BCM1480_MC_COL07) +#define V_BCM1480_MC_COL07(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL07) +#define G_BCM1480_MC_COL07(x) _SB_GETVALUE(x, S_BCM1480_MC_COL07, M_BCM1480_MC_COL07) /* * Column Address Bit Select Register 1 (Table 87) */ #define S_BCM1480_MC_COL08 0 -#define M_BCM1480_MC_COL08 _SB_MAKEMASK(6,S_BCM1480_MC_COL08) -#define V_BCM1480_MC_COL08(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL08) -#define G_BCM1480_MC_COL08(x) _SB_GETVALUE(x,S_BCM1480_MC_COL08,M_BCM1480_MC_COL08) +#define M_BCM1480_MC_COL08 _SB_MAKEMASK(6, S_BCM1480_MC_COL08) +#define V_BCM1480_MC_COL08(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL08) +#define G_BCM1480_MC_COL08(x) _SB_GETVALUE(x, S_BCM1480_MC_COL08, M_BCM1480_MC_COL08) #define S_BCM1480_MC_COL09 8 -#define M_BCM1480_MC_COL09 _SB_MAKEMASK(6,S_BCM1480_MC_COL09) -#define V_BCM1480_MC_COL09(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL09) -#define G_BCM1480_MC_COL09(x) _SB_GETVALUE(x,S_BCM1480_MC_COL09,M_BCM1480_MC_COL09) +#define M_BCM1480_MC_COL09 _SB_MAKEMASK(6, S_BCM1480_MC_COL09) +#define V_BCM1480_MC_COL09(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL09) +#define G_BCM1480_MC_COL09(x) _SB_GETVALUE(x, S_BCM1480_MC_COL09, M_BCM1480_MC_COL09) #define S_BCM1480_MC_COL10 16 /* not a valid position, must be prog as 0 */ #define S_BCM1480_MC_COL11 24 -#define M_BCM1480_MC_COL11 _SB_MAKEMASK(6,S_BCM1480_MC_COL11) -#define V_BCM1480_MC_COL11(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL11) -#define G_BCM1480_MC_COL11(x) _SB_GETVALUE(x,S_BCM1480_MC_COL11,M_BCM1480_MC_COL11) +#define M_BCM1480_MC_COL11 _SB_MAKEMASK(6, S_BCM1480_MC_COL11) +#define V_BCM1480_MC_COL11(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL11) +#define G_BCM1480_MC_COL11(x) _SB_GETVALUE(x, S_BCM1480_MC_COL11, M_BCM1480_MC_COL11) #define S_BCM1480_MC_COL12 32 -#define M_BCM1480_MC_COL12 _SB_MAKEMASK(6,S_BCM1480_MC_COL12) -#define V_BCM1480_MC_COL12(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL12) -#define G_BCM1480_MC_COL12(x) _SB_GETVALUE(x,S_BCM1480_MC_COL12,M_BCM1480_MC_COL12) +#define M_BCM1480_MC_COL12 _SB_MAKEMASK(6, S_BCM1480_MC_COL12) +#define V_BCM1480_MC_COL12(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL12) +#define G_BCM1480_MC_COL12(x) _SB_GETVALUE(x, S_BCM1480_MC_COL12, M_BCM1480_MC_COL12) #define S_BCM1480_MC_COL13 40 -#define M_BCM1480_MC_COL13 _SB_MAKEMASK(6,S_BCM1480_MC_COL13) -#define V_BCM1480_MC_COL13(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL13) -#define G_BCM1480_MC_COL13(x) _SB_GETVALUE(x,S_BCM1480_MC_COL13,M_BCM1480_MC_COL13) +#define M_BCM1480_MC_COL13 _SB_MAKEMASK(6, S_BCM1480_MC_COL13) +#define V_BCM1480_MC_COL13(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL13) +#define G_BCM1480_MC_COL13(x) _SB_GETVALUE(x, S_BCM1480_MC_COL13, M_BCM1480_MC_COL13) #define S_BCM1480_MC_COL14 48 -#define M_BCM1480_MC_COL14 _SB_MAKEMASK(6,S_BCM1480_MC_COL14) -#define V_BCM1480_MC_COL14(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL14) -#define G_BCM1480_MC_COL14(x) _SB_GETVALUE(x,S_BCM1480_MC_COL14,M_BCM1480_MC_COL14) +#define M_BCM1480_MC_COL14 _SB_MAKEMASK(6, S_BCM1480_MC_COL14) +#define V_BCM1480_MC_COL14(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL14) +#define G_BCM1480_MC_COL14(x) _SB_GETVALUE(x, S_BCM1480_MC_COL14, M_BCM1480_MC_COL14) #define K_BCM1480_MC_COLX_BIT_SPACING 8 @@ -296,38 +296,38 @@ */ #define S_BCM1480_MC_CS01_BANK0 0 -#define M_BCM1480_MC_CS01_BANK0 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK0) -#define V_BCM1480_MC_CS01_BANK0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK0) -#define G_BCM1480_MC_CS01_BANK0(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK0,M_BCM1480_MC_CS01_BANK0) +#define M_BCM1480_MC_CS01_BANK0 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK0) +#define V_BCM1480_MC_CS01_BANK0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK0) +#define G_BCM1480_MC_CS01_BANK0(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK0, M_BCM1480_MC_CS01_BANK0) #define S_BCM1480_MC_CS01_BANK1 8 -#define M_BCM1480_MC_CS01_BANK1 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK1) -#define V_BCM1480_MC_CS01_BANK1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK1) -#define G_BCM1480_MC_CS01_BANK1(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK1,M_BCM1480_MC_CS01_BANK1) +#define M_BCM1480_MC_CS01_BANK1 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK1) +#define V_BCM1480_MC_CS01_BANK1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK1) +#define G_BCM1480_MC_CS01_BANK1(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK1, M_BCM1480_MC_CS01_BANK1) #define S_BCM1480_MC_CS01_BANK2 16 -#define M_BCM1480_MC_CS01_BANK2 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK2) -#define V_BCM1480_MC_CS01_BANK2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK2) -#define G_BCM1480_MC_CS01_BANK2(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK2,M_BCM1480_MC_CS01_BANK2) +#define M_BCM1480_MC_CS01_BANK2 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK2) +#define V_BCM1480_MC_CS01_BANK2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK2) +#define G_BCM1480_MC_CS01_BANK2(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK2, M_BCM1480_MC_CS01_BANK2) /* * CS2 and CS3 Bank Address Bit Select Register (Table 89) */ #define S_BCM1480_MC_CS23_BANK0 0 -#define M_BCM1480_MC_CS23_BANK0 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK0) -#define V_BCM1480_MC_CS23_BANK0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK0) -#define G_BCM1480_MC_CS23_BANK0(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK0,M_BCM1480_MC_CS23_BANK0) +#define M_BCM1480_MC_CS23_BANK0 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK0) +#define V_BCM1480_MC_CS23_BANK0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK0) +#define G_BCM1480_MC_CS23_BANK0(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK0, M_BCM1480_MC_CS23_BANK0) #define S_BCM1480_MC_CS23_BANK1 8 -#define M_BCM1480_MC_CS23_BANK1 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK1) -#define V_BCM1480_MC_CS23_BANK1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK1) -#define G_BCM1480_MC_CS23_BANK1(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK1,M_BCM1480_MC_CS23_BANK1) +#define M_BCM1480_MC_CS23_BANK1 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK1) +#define V_BCM1480_MC_CS23_BANK1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK1) +#define G_BCM1480_MC_CS23_BANK1(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK1, M_BCM1480_MC_CS23_BANK1) #define S_BCM1480_MC_CS23_BANK2 16 -#define M_BCM1480_MC_CS23_BANK2 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK2) -#define V_BCM1480_MC_CS23_BANK2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK2) -#define G_BCM1480_MC_CS23_BANK2(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK2,M_BCM1480_MC_CS23_BANK2) +#define M_BCM1480_MC_CS23_BANK2 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK2) +#define V_BCM1480_MC_CS23_BANK2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK2) +#define G_BCM1480_MC_CS23_BANK2(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK2, M_BCM1480_MC_CS23_BANK2) #define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING 8 @@ -336,9 +336,9 @@ */ #define S_BCM1480_MC_COMMAND 0 -#define M_BCM1480_MC_COMMAND _SB_MAKEMASK(4,S_BCM1480_MC_COMMAND) -#define V_BCM1480_MC_COMMAND(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COMMAND) -#define G_BCM1480_MC_COMMAND(x) _SB_GETVALUE(x,S_BCM1480_MC_COMMAND,M_BCM1480_MC_COMMAND) +#define M_BCM1480_MC_COMMAND _SB_MAKEMASK(4, S_BCM1480_MC_COMMAND) +#define V_BCM1480_MC_COMMAND(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COMMAND) +#define G_BCM1480_MC_COMMAND(x) _SB_GETVALUE(x, S_BCM1480_MC_COMMAND, M_BCM1480_MC_COMMAND) #define K_BCM1480_MC_COMMAND_EMRS 0 #define K_BCM1480_MC_COMMAND_MRS 1 @@ -382,9 +382,9 @@ #define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10) #define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11) -#define M_BCM1480_MC_CS _SB_MAKEMASK(8,S_BCM1480_MC_CS0) -#define V_BCM1480_MC_CS(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0) -#define G_BCM1480_MC_CS(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0,M_BCM1480_MC_CS0) +#define M_BCM1480_MC_CS _SB_MAKEMASK(8, S_BCM1480_MC_CS0) +#define V_BCM1480_MC_CS(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0) +#define G_BCM1480_MC_CS(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0, M_BCM1480_MC_CS0) #define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16) @@ -393,21 +393,21 @@ */ #define S_BCM1480_MC_EMODE 0 -#define M_BCM1480_MC_EMODE _SB_MAKEMASK(15,S_BCM1480_MC_EMODE) -#define V_BCM1480_MC_EMODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_EMODE) -#define G_BCM1480_MC_EMODE(x) _SB_GETVALUE(x,S_BCM1480_MC_EMODE,M_BCM1480_MC_EMODE) +#define M_BCM1480_MC_EMODE _SB_MAKEMASK(15, S_BCM1480_MC_EMODE) +#define V_BCM1480_MC_EMODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_EMODE) +#define G_BCM1480_MC_EMODE(x) _SB_GETVALUE(x, S_BCM1480_MC_EMODE, M_BCM1480_MC_EMODE) #define V_BCM1480_MC_EMODE_DEFAULT V_BCM1480_MC_EMODE(0) #define S_BCM1480_MC_MODE 16 -#define M_BCM1480_MC_MODE _SB_MAKEMASK(15,S_BCM1480_MC_MODE) -#define V_BCM1480_MC_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_MODE) -#define G_BCM1480_MC_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_MODE,M_BCM1480_MC_MODE) +#define M_BCM1480_MC_MODE _SB_MAKEMASK(15, S_BCM1480_MC_MODE) +#define V_BCM1480_MC_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_MODE) +#define G_BCM1480_MC_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_MODE, M_BCM1480_MC_MODE) #define V_BCM1480_MC_MODE_DEFAULT V_BCM1480_MC_MODE(0) #define S_BCM1480_MC_DRAM_TYPE 32 -#define M_BCM1480_MC_DRAM_TYPE _SB_MAKEMASK(4,S_BCM1480_MC_DRAM_TYPE) -#define V_BCM1480_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DRAM_TYPE) -#define G_BCM1480_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_BCM1480_MC_DRAM_TYPE,M_BCM1480_MC_DRAM_TYPE) +#define M_BCM1480_MC_DRAM_TYPE _SB_MAKEMASK(4, S_BCM1480_MC_DRAM_TYPE) +#define V_BCM1480_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DRAM_TYPE) +#define G_BCM1480_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_BCM1480_MC_DRAM_TYPE, M_BCM1480_MC_DRAM_TYPE) #define K_BCM1480_MC_DRAM_TYPE_JEDEC 0 #define K_BCM1480_MC_DRAM_TYPE_FCRAM 1 @@ -431,9 +431,9 @@ #define M_BCM1480_MC_ECC_DISABLE _SB_MAKEMASK1(39) #define S_BCM1480_MC_PG_POLICY 40 -#define M_BCM1480_MC_PG_POLICY _SB_MAKEMASK(2,S_BCM1480_MC_PG_POLICY) -#define V_BCM1480_MC_PG_POLICY(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PG_POLICY) -#define G_BCM1480_MC_PG_POLICY(x) _SB_GETVALUE(x,S_BCM1480_MC_PG_POLICY,M_BCM1480_MC_PG_POLICY) +#define M_BCM1480_MC_PG_POLICY _SB_MAKEMASK(2, S_BCM1480_MC_PG_POLICY) +#define V_BCM1480_MC_PG_POLICY(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PG_POLICY) +#define G_BCM1480_MC_PG_POLICY(x) _SB_GETVALUE(x, S_BCM1480_MC_PG_POLICY, M_BCM1480_MC_PG_POLICY) #define K_BCM1480_MC_PG_POLICY_CLOSED 0 #define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1 @@ -454,16 +454,16 @@ */ #define S_BCM1480_MC_CLK_RATIO 0 -#define M_BCM1480_MC_CLK_RATIO _SB_MAKEMASK(6,S_BCM1480_MC_CLK_RATIO) -#define V_BCM1480_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CLK_RATIO) -#define G_BCM1480_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_BCM1480_MC_CLK_RATIO,M_BCM1480_MC_CLK_RATIO) +#define M_BCM1480_MC_CLK_RATIO _SB_MAKEMASK(6, S_BCM1480_MC_CLK_RATIO) +#define V_BCM1480_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CLK_RATIO) +#define G_BCM1480_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_BCM1480_MC_CLK_RATIO, M_BCM1480_MC_CLK_RATIO) #define V_BCM1480_MC_CLK_RATIO_DEFAULT V_BCM1480_MC_CLK_RATIO(10) #define S_BCM1480_MC_REF_RATE 8 -#define M_BCM1480_MC_REF_RATE _SB_MAKEMASK(8,S_BCM1480_MC_REF_RATE) -#define V_BCM1480_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_REF_RATE) -#define G_BCM1480_MC_REF_RATE(x) _SB_GETVALUE(x,S_BCM1480_MC_REF_RATE,M_BCM1480_MC_REF_RATE) +#define M_BCM1480_MC_REF_RATE _SB_MAKEMASK(8, S_BCM1480_MC_REF_RATE) +#define V_BCM1480_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_REF_RATE) +#define G_BCM1480_MC_REF_RATE(x) _SB_GETVALUE(x, S_BCM1480_MC_REF_RATE, M_BCM1480_MC_REF_RATE) #define K_BCM1480_MC_REF_RATE_100MHz 0x31 #define K_BCM1480_MC_REF_RATE_200MHz 0x62 @@ -519,20 +519,20 @@ #define M_BCM1480_MC_CS_ODD_ODT_EN _SB_MAKEMASK1(32) #define S_BCM1480_MC_ODT0 0 -#define M_BCM1480_MC_ODT0 _SB_MAKEMASK(8,S_BCM1480_MC_ODT0) -#define V_BCM1480_MC_ODT0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT0) +#define M_BCM1480_MC_ODT0 _SB_MAKEMASK(8, S_BCM1480_MC_ODT0) +#define V_BCM1480_MC_ODT0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT0) #define S_BCM1480_MC_ODT2 8 -#define M_BCM1480_MC_ODT2 _SB_MAKEMASK(8,S_BCM1480_MC_ODT2) -#define V_BCM1480_MC_ODT2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT2) +#define M_BCM1480_MC_ODT2 _SB_MAKEMASK(8, S_BCM1480_MC_ODT2) +#define V_BCM1480_MC_ODT2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT2) #define S_BCM1480_MC_ODT4 16 -#define M_BCM1480_MC_ODT4 _SB_MAKEMASK(8,S_BCM1480_MC_ODT4) -#define V_BCM1480_MC_ODT4(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT4) +#define M_BCM1480_MC_ODT4 _SB_MAKEMASK(8, S_BCM1480_MC_ODT4) +#define V_BCM1480_MC_ODT4(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT4) #define S_BCM1480_MC_ODT6 24 -#define M_BCM1480_MC_ODT6 _SB_MAKEMASK(8,S_BCM1480_MC_ODT6) -#define V_BCM1480_MC_ODT6(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT6) +#define M_BCM1480_MC_ODT6 _SB_MAKEMASK(8, S_BCM1480_MC_ODT6) +#define V_BCM1480_MC_ODT6(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT6) #endif /* @@ -540,70 +540,70 @@ */ #define S_BCM1480_MC_ADDR_COARSE_ADJ 0 -#define M_BCM1480_MC_ADDR_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_ADDR_COARSE_ADJ) -#define V_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ) -#define G_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ,M_BCM1480_MC_ADDR_COARSE_ADJ) +#define M_BCM1480_MC_ADDR_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_ADDR_COARSE_ADJ) +#define V_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ) +#define G_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ, M_BCM1480_MC_ADDR_COARSE_ADJ) #define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_ADDR_FREQ_RANGE 8 -#define M_BCM1480_MC_ADDR_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FREQ_RANGE) -#define V_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE) -#define G_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE,M_BCM1480_MC_ADDR_FREQ_RANGE) +#define M_BCM1480_MC_ADDR_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FREQ_RANGE) +#define V_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE) +#define G_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE, M_BCM1480_MC_ADDR_FREQ_RANGE) #define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT V_BCM1480_MC_ADDR_FREQ_RANGE(0x4) #endif #define S_BCM1480_MC_ADDR_FINE_ADJ 8 -#define M_BCM1480_MC_ADDR_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FINE_ADJ) -#define V_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ) -#define G_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ,M_BCM1480_MC_ADDR_FINE_ADJ) +#define M_BCM1480_MC_ADDR_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FINE_ADJ) +#define V_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ) +#define G_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ, M_BCM1480_MC_ADDR_FINE_ADJ) #define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT V_BCM1480_MC_ADDR_FINE_ADJ(0x8) #define S_BCM1480_MC_DQI_COARSE_ADJ 16 -#define M_BCM1480_MC_DQI_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_DQI_COARSE_ADJ) -#define V_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ) -#define G_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ,M_BCM1480_MC_DQI_COARSE_ADJ) +#define M_BCM1480_MC_DQI_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_DQI_COARSE_ADJ) +#define V_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ) +#define G_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ, M_BCM1480_MC_DQI_COARSE_ADJ) #define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_DQI_FREQ_RANGE 24 -#define M_BCM1480_MC_DQI_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FREQ_RANGE) -#define V_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE) -#define G_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE,M_BCM1480_MC_DQI_FREQ_RANGE) +#define M_BCM1480_MC_DQI_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FREQ_RANGE) +#define V_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE) +#define G_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE, M_BCM1480_MC_DQI_FREQ_RANGE) #define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQI_FREQ_RANGE(0x4) #endif #define S_BCM1480_MC_DQI_FINE_ADJ 24 -#define M_BCM1480_MC_DQI_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FINE_ADJ) -#define V_BCM1480_MC_DQI_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ) -#define G_BCM1480_MC_DQI_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ,M_BCM1480_MC_DQI_FINE_ADJ) +#define M_BCM1480_MC_DQI_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FINE_ADJ) +#define V_BCM1480_MC_DQI_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ) +#define G_BCM1480_MC_DQI_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ, M_BCM1480_MC_DQI_FINE_ADJ) #define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT V_BCM1480_MC_DQI_FINE_ADJ(0x8) #define S_BCM1480_MC_DQO_COARSE_ADJ 32 -#define M_BCM1480_MC_DQO_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_DQO_COARSE_ADJ) -#define V_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ) -#define G_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ,M_BCM1480_MC_DQO_COARSE_ADJ) +#define M_BCM1480_MC_DQO_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_DQO_COARSE_ADJ) +#define V_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ) +#define G_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ, M_BCM1480_MC_DQO_COARSE_ADJ) #define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_DQO_FREQ_RANGE 40 -#define M_BCM1480_MC_DQO_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FREQ_RANGE) -#define V_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE) -#define G_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE,M_BCM1480_MC_DQO_FREQ_RANGE) +#define M_BCM1480_MC_DQO_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FREQ_RANGE) +#define V_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE) +#define G_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE, M_BCM1480_MC_DQO_FREQ_RANGE) #define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQO_FREQ_RANGE(0x4) #endif #define S_BCM1480_MC_DQO_FINE_ADJ 40 -#define M_BCM1480_MC_DQO_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FINE_ADJ) -#define V_BCM1480_MC_DQO_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ) -#define G_BCM1480_MC_DQO_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ,M_BCM1480_MC_DQO_FINE_ADJ) +#define M_BCM1480_MC_DQO_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FINE_ADJ) +#define V_BCM1480_MC_DQO_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ) +#define G_BCM1480_MC_DQO_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ, M_BCM1480_MC_DQO_FINE_ADJ) #define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT V_BCM1480_MC_DQO_FINE_ADJ(0x8) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_DLL_PDSEL 44 -#define M_BCM1480_MC_DLL_PDSEL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_PDSEL) -#define V_BCM1480_MC_DLL_PDSEL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_PDSEL) -#define G_BCM1480_MC_DLL_PDSEL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_PDSEL,M_BCM1480_MC_DLL_PDSEL) +#define M_BCM1480_MC_DLL_PDSEL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_PDSEL) +#define V_BCM1480_MC_DLL_PDSEL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_PDSEL) +#define G_BCM1480_MC_DLL_PDSEL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_PDSEL, M_BCM1480_MC_DLL_PDSEL) #define V_BCM1480_MC_DLL_DEFAULT_PDSEL V_BCM1480_MC_DLL_PDSEL(0x0) #define M_BCM1480_MC_DLL_REGBYPASS _SB_MAKEMASK1(46) @@ -611,38 +611,38 @@ #endif #define S_BCM1480_MC_DLL_DEFAULT 48 -#define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6,S_BCM1480_MC_DLL_DEFAULT) -#define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_DEFAULT) -#define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_DEFAULT,M_BCM1480_MC_DLL_DEFAULT) +#define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6, S_BCM1480_MC_DLL_DEFAULT) +#define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_DEFAULT) +#define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_DEFAULT, M_BCM1480_MC_DLL_DEFAULT) #define V_BCM1480_MC_DLL_DEFAULT_DEFAULT V_BCM1480_MC_DLL_DEFAULT(0x10) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_DLL_REGCTRL 54 -#define M_BCM1480_MC_DLL_REGCTRL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_REGCTRL) -#define V_BCM1480_MC_DLL_REGCTRL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_REGCTRL) -#define G_BCM1480_MC_DLL_REGCTRL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_REGCTRL,M_BCM1480_MC_DLL_REGCTRL) +#define M_BCM1480_MC_DLL_REGCTRL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_REGCTRL) +#define V_BCM1480_MC_DLL_REGCTRL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_REGCTRL) +#define G_BCM1480_MC_DLL_REGCTRL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_REGCTRL, M_BCM1480_MC_DLL_REGCTRL) #define V_BCM1480_MC_DLL_DEFAULT_REGCTRL V_BCM1480_MC_DLL_REGCTRL(0x0) #endif #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_DLL_FREQ_RANGE 56 -#define M_BCM1480_MC_DLL_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DLL_FREQ_RANGE) -#define V_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE) -#define G_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE,M_BCM1480_MC_DLL_FREQ_RANGE) +#define M_BCM1480_MC_DLL_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DLL_FREQ_RANGE) +#define V_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE) +#define G_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE, M_BCM1480_MC_DLL_FREQ_RANGE) #define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT V_BCM1480_MC_DLL_FREQ_RANGE(0x4) #endif #define S_BCM1480_MC_DLL_STEP_SIZE 56 -#define M_BCM1480_MC_DLL_STEP_SIZE _SB_MAKEMASK(4,S_BCM1480_MC_DLL_STEP_SIZE) -#define V_BCM1480_MC_DLL_STEP_SIZE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE) -#define G_BCM1480_MC_DLL_STEP_SIZE(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE,M_BCM1480_MC_DLL_STEP_SIZE) +#define M_BCM1480_MC_DLL_STEP_SIZE _SB_MAKEMASK(4, S_BCM1480_MC_DLL_STEP_SIZE) +#define V_BCM1480_MC_DLL_STEP_SIZE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE) +#define G_BCM1480_MC_DLL_STEP_SIZE(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE, M_BCM1480_MC_DLL_STEP_SIZE) #define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT V_BCM1480_MC_DLL_STEP_SIZE(0x8) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_DLL_BGCTRL 60 -#define M_BCM1480_MC_DLL_BGCTRL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_BGCTRL) -#define V_BCM1480_MC_DLL_BGCTRL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_BGCTRL) -#define G_BCM1480_MC_DLL_BGCTRL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_BGCTRL,M_BCM1480_MC_DLL_BGCTRL) +#define M_BCM1480_MC_DLL_BGCTRL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_BGCTRL) +#define V_BCM1480_MC_DLL_BGCTRL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_BGCTRL) +#define G_BCM1480_MC_DLL_BGCTRL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_BGCTRL, M_BCM1480_MC_DLL_BGCTRL) #define V_BCM1480_MC_DLL_DEFAULT_BGCTRL V_BCM1480_MC_DLL_BGCTRL(0x0) #endif @@ -653,37 +653,37 @@ */ #define S_BCM1480_MC_RTT_BYP_PULLDOWN 0 -#define M_BCM1480_MC_RTT_BYP_PULLDOWN _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLDOWN) -#define V_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN) -#define G_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN,M_BCM1480_MC_RTT_BYP_PULLDOWN) +#define M_BCM1480_MC_RTT_BYP_PULLDOWN _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLDOWN) +#define V_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN) +#define G_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN, M_BCM1480_MC_RTT_BYP_PULLDOWN) #define S_BCM1480_MC_RTT_BYP_PULLUP 6 -#define M_BCM1480_MC_RTT_BYP_PULLUP _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLUP) -#define V_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP) -#define G_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP,M_BCM1480_MC_RTT_BYP_PULLUP) +#define M_BCM1480_MC_RTT_BYP_PULLUP _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLUP) +#define V_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP) +#define G_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP, M_BCM1480_MC_RTT_BYP_PULLUP) #define M_BCM1480_MC_RTT_BYPASS _SB_MAKEMASK1(8) #define M_BCM1480_MC_RTT_COMP_MOV_AVG _SB_MAKEMASK1(9) #define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN 10 -#define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) -#define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) -#define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN,M_BCM1480_MC_PVT_BYP_C1_PULLDOWN) +#define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) +#define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) +#define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN, M_BCM1480_MC_PVT_BYP_C1_PULLDOWN) #define S_BCM1480_MC_PVT_BYP_C1_PULLUP 15 -#define M_BCM1480_MC_PVT_BYP_C1_PULLUP _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLUP) -#define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP) -#define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP,M_BCM1480_MC_PVT_BYP_C1_PULLUP) +#define M_BCM1480_MC_PVT_BYP_C1_PULLUP _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLUP) +#define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP) +#define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP, M_BCM1480_MC_PVT_BYP_C1_PULLUP) #define S_BCM1480_MC_PVT_BYP_C2_PULLDOWN 20 -#define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) -#define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) -#define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN,M_BCM1480_MC_PVT_BYP_C2_PULLDOWN) +#define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) +#define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) +#define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN, M_BCM1480_MC_PVT_BYP_C2_PULLDOWN) #define S_BCM1480_MC_PVT_BYP_C2_PULLUP 25 -#define M_BCM1480_MC_PVT_BYP_C2_PULLUP _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLUP) -#define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP) -#define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP,M_BCM1480_MC_PVT_BYP_C2_PULLUP) +#define M_BCM1480_MC_PVT_BYP_C2_PULLUP _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLUP) +#define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP) +#define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP, M_BCM1480_MC_PVT_BYP_C2_PULLUP) #define M_BCM1480_MC_PVT_BYPASS _SB_MAKEMASK1(30) #define M_BCM1480_MC_PVT_COMP_MOV_AVG _SB_MAKEMASK1(31) @@ -703,111 +703,111 @@ */ #define S_BCM1480_MC_DATA_INVERT 0 -#define M_DATA_ECC_INVERT _SB_MAKEMASK(64,S_BCM1480_MC_ECC_INVERT) +#define M_DATA_ECC_INVERT _SB_MAKEMASK(64, S_BCM1480_MC_ECC_INVERT) /* * ECC Test ECC Register (Table 96) */ #define S_BCM1480_MC_ECC_INVERT 0 -#define M_BCM1480_MC_ECC_INVERT _SB_MAKEMASK(8,S_BCM1480_MC_ECC_INVERT) +#define M_BCM1480_MC_ECC_INVERT _SB_MAKEMASK(8, S_BCM1480_MC_ECC_INVERT) /* * SDRAM Timing Register (Table 97) */ #define S_BCM1480_MC_tRCD 0 -#define M_BCM1480_MC_tRCD _SB_MAKEMASK(4,S_BCM1480_MC_tRCD) -#define V_BCM1480_MC_tRCD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCD) -#define G_BCM1480_MC_tRCD(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCD,M_BCM1480_MC_tRCD) +#define M_BCM1480_MC_tRCD _SB_MAKEMASK(4, S_BCM1480_MC_tRCD) +#define V_BCM1480_MC_tRCD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCD) +#define G_BCM1480_MC_tRCD(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCD, M_BCM1480_MC_tRCD) #define K_BCM1480_MC_tRCD_DEFAULT 3 #define V_BCM1480_MC_tRCD_DEFAULT V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT) #define S_BCM1480_MC_tCL 4 -#define M_BCM1480_MC_tCL _SB_MAKEMASK(4,S_BCM1480_MC_tCL) -#define V_BCM1480_MC_tCL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tCL) -#define G_BCM1480_MC_tCL(x) _SB_GETVALUE(x,S_BCM1480_MC_tCL,M_BCM1480_MC_tCL) +#define M_BCM1480_MC_tCL _SB_MAKEMASK(4, S_BCM1480_MC_tCL) +#define V_BCM1480_MC_tCL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tCL) +#define G_BCM1480_MC_tCL(x) _SB_GETVALUE(x, S_BCM1480_MC_tCL, M_BCM1480_MC_tCL) #define K_BCM1480_MC_tCL_DEFAULT 2 #define V_BCM1480_MC_tCL_DEFAULT V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT) #define M_BCM1480_MC_tCrDh _SB_MAKEMASK1(8) #define S_BCM1480_MC_tWR 9 -#define M_BCM1480_MC_tWR _SB_MAKEMASK(3,S_BCM1480_MC_tWR) -#define V_BCM1480_MC_tWR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tWR) -#define G_BCM1480_MC_tWR(x) _SB_GETVALUE(x,S_BCM1480_MC_tWR,M_BCM1480_MC_tWR) +#define M_BCM1480_MC_tWR _SB_MAKEMASK(3, S_BCM1480_MC_tWR) +#define V_BCM1480_MC_tWR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tWR) +#define G_BCM1480_MC_tWR(x) _SB_GETVALUE(x, S_BCM1480_MC_tWR, M_BCM1480_MC_tWR) #define K_BCM1480_MC_tWR_DEFAULT 2 #define V_BCM1480_MC_tWR_DEFAULT V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT) #define S_BCM1480_MC_tCwD 12 -#define M_BCM1480_MC_tCwD _SB_MAKEMASK(4,S_BCM1480_MC_tCwD) -#define V_BCM1480_MC_tCwD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tCwD) -#define G_BCM1480_MC_tCwD(x) _SB_GETVALUE(x,S_BCM1480_MC_tCwD,M_BCM1480_MC_tCwD) +#define M_BCM1480_MC_tCwD _SB_MAKEMASK(4, S_BCM1480_MC_tCwD) +#define V_BCM1480_MC_tCwD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tCwD) +#define G_BCM1480_MC_tCwD(x) _SB_GETVALUE(x, S_BCM1480_MC_tCwD, M_BCM1480_MC_tCwD) #define K_BCM1480_MC_tCwD_DEFAULT 1 #define V_BCM1480_MC_tCwD_DEFAULT V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT) #define S_BCM1480_MC_tRP 16 -#define M_BCM1480_MC_tRP _SB_MAKEMASK(4,S_BCM1480_MC_tRP) -#define V_BCM1480_MC_tRP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRP) -#define G_BCM1480_MC_tRP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRP,M_BCM1480_MC_tRP) +#define M_BCM1480_MC_tRP _SB_MAKEMASK(4, S_BCM1480_MC_tRP) +#define V_BCM1480_MC_tRP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRP) +#define G_BCM1480_MC_tRP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRP, M_BCM1480_MC_tRP) #define K_BCM1480_MC_tRP_DEFAULT 4 #define V_BCM1480_MC_tRP_DEFAULT V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT) #define S_BCM1480_MC_tRRD 20 -#define M_BCM1480_MC_tRRD _SB_MAKEMASK(4,S_BCM1480_MC_tRRD) -#define V_BCM1480_MC_tRRD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRRD) -#define G_BCM1480_MC_tRRD(x) _SB_GETVALUE(x,S_BCM1480_MC_tRRD,M_BCM1480_MC_tRRD) +#define M_BCM1480_MC_tRRD _SB_MAKEMASK(4, S_BCM1480_MC_tRRD) +#define V_BCM1480_MC_tRRD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRRD) +#define G_BCM1480_MC_tRRD(x) _SB_GETVALUE(x, S_BCM1480_MC_tRRD, M_BCM1480_MC_tRRD) #define K_BCM1480_MC_tRRD_DEFAULT 2 #define V_BCM1480_MC_tRRD_DEFAULT V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT) #define S_BCM1480_MC_tRCw 24 -#define M_BCM1480_MC_tRCw _SB_MAKEMASK(5,S_BCM1480_MC_tRCw) -#define V_BCM1480_MC_tRCw(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCw) -#define G_BCM1480_MC_tRCw(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCw,M_BCM1480_MC_tRCw) +#define M_BCM1480_MC_tRCw _SB_MAKEMASK(5, S_BCM1480_MC_tRCw) +#define V_BCM1480_MC_tRCw(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCw) +#define G_BCM1480_MC_tRCw(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCw, M_BCM1480_MC_tRCw) #define K_BCM1480_MC_tRCw_DEFAULT 10 #define V_BCM1480_MC_tRCw_DEFAULT V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT) #define S_BCM1480_MC_tRCr 32 -#define M_BCM1480_MC_tRCr _SB_MAKEMASK(5,S_BCM1480_MC_tRCr) -#define V_BCM1480_MC_tRCr(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCr) -#define G_BCM1480_MC_tRCr(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCr,M_BCM1480_MC_tRCr) +#define M_BCM1480_MC_tRCr _SB_MAKEMASK(5, S_BCM1480_MC_tRCr) +#define V_BCM1480_MC_tRCr(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCr) +#define G_BCM1480_MC_tRCr(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCr, M_BCM1480_MC_tRCr) #define K_BCM1480_MC_tRCr_DEFAULT 9 #define V_BCM1480_MC_tRCr_DEFAULT V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_tFAW 40 -#define M_BCM1480_MC_tFAW _SB_MAKEMASK(6,S_BCM1480_MC_tFAW) -#define V_BCM1480_MC_tFAW(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tFAW) -#define G_BCM1480_MC_tFAW(x) _SB_GETVALUE(x,S_BCM1480_MC_tFAW,M_BCM1480_MC_tFAW) +#define M_BCM1480_MC_tFAW _SB_MAKEMASK(6, S_BCM1480_MC_tFAW) +#define V_BCM1480_MC_tFAW(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tFAW) +#define G_BCM1480_MC_tFAW(x) _SB_GETVALUE(x, S_BCM1480_MC_tFAW, M_BCM1480_MC_tFAW) #define K_BCM1480_MC_tFAW_DEFAULT 0 #define V_BCM1480_MC_tFAW_DEFAULT V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT) #endif #define S_BCM1480_MC_tRFC 48 -#define M_BCM1480_MC_tRFC _SB_MAKEMASK(7,S_BCM1480_MC_tRFC) -#define V_BCM1480_MC_tRFC(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRFC) -#define G_BCM1480_MC_tRFC(x) _SB_GETVALUE(x,S_BCM1480_MC_tRFC,M_BCM1480_MC_tRFC) +#define M_BCM1480_MC_tRFC _SB_MAKEMASK(7, S_BCM1480_MC_tRFC) +#define V_BCM1480_MC_tRFC(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRFC) +#define G_BCM1480_MC_tRFC(x) _SB_GETVALUE(x, S_BCM1480_MC_tRFC, M_BCM1480_MC_tRFC) #define K_BCM1480_MC_tRFC_DEFAULT 12 #define V_BCM1480_MC_tRFC_DEFAULT V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT) #define S_BCM1480_MC_tFIFO 56 -#define M_BCM1480_MC_tFIFO _SB_MAKEMASK(2,S_BCM1480_MC_tFIFO) -#define V_BCM1480_MC_tFIFO(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tFIFO) -#define G_BCM1480_MC_tFIFO(x) _SB_GETVALUE(x,S_BCM1480_MC_tFIFO,M_BCM1480_MC_tFIFO) +#define M_BCM1480_MC_tFIFO _SB_MAKEMASK(2, S_BCM1480_MC_tFIFO) +#define V_BCM1480_MC_tFIFO(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tFIFO) +#define G_BCM1480_MC_tFIFO(x) _SB_GETVALUE(x, S_BCM1480_MC_tFIFO, M_BCM1480_MC_tFIFO) #define K_BCM1480_MC_tFIFO_DEFAULT 0 #define V_BCM1480_MC_tFIFO_DEFAULT V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT) #define S_BCM1480_MC_tW2R 58 -#define M_BCM1480_MC_tW2R _SB_MAKEMASK(2,S_BCM1480_MC_tW2R) -#define V_BCM1480_MC_tW2R(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tW2R) -#define G_BCM1480_MC_tW2R(x) _SB_GETVALUE(x,S_BCM1480_MC_tW2R,M_BCM1480_MC_tW2R) +#define M_BCM1480_MC_tW2R _SB_MAKEMASK(2, S_BCM1480_MC_tW2R) +#define V_BCM1480_MC_tW2R(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tW2R) +#define G_BCM1480_MC_tW2R(x) _SB_GETVALUE(x, S_BCM1480_MC_tW2R, M_BCM1480_MC_tW2R) #define K_BCM1480_MC_tW2R_DEFAULT 1 #define V_BCM1480_MC_tW2R_DEFAULT V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT) #define S_BCM1480_MC_tR2W 60 -#define M_BCM1480_MC_tR2W _SB_MAKEMASK(2,S_BCM1480_MC_tR2W) -#define V_BCM1480_MC_tR2W(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tR2W) -#define G_BCM1480_MC_tR2W(x) _SB_GETVALUE(x,S_BCM1480_MC_tR2W,M_BCM1480_MC_tR2W) +#define M_BCM1480_MC_tR2W _SB_MAKEMASK(2, S_BCM1480_MC_tR2W) +#define V_BCM1480_MC_tR2W(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tR2W) +#define G_BCM1480_MC_tR2W(x) _SB_GETVALUE(x, S_BCM1480_MC_tR2W, M_BCM1480_MC_tR2W) #define K_BCM1480_MC_tR2W_DEFAULT 0 #define V_BCM1480_MC_tR2W_DEFAULT V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT) @@ -835,30 +835,30 @@ #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_tAL 0 -#define M_BCM1480_MC_tAL _SB_MAKEMASK(4,S_BCM1480_MC_tAL) -#define V_BCM1480_MC_tAL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tAL) -#define G_BCM1480_MC_tAL(x) _SB_GETVALUE(x,S_BCM1480_MC_tAL,M_BCM1480_MC_tAL) +#define M_BCM1480_MC_tAL _SB_MAKEMASK(4, S_BCM1480_MC_tAL) +#define V_BCM1480_MC_tAL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tAL) +#define G_BCM1480_MC_tAL(x) _SB_GETVALUE(x, S_BCM1480_MC_tAL, M_BCM1480_MC_tAL) #define K_BCM1480_MC_tAL_DEFAULT 0 #define V_BCM1480_MC_tAL_DEFAULT V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT) #define S_BCM1480_MC_tRTP 4 -#define M_BCM1480_MC_tRTP _SB_MAKEMASK(3,S_BCM1480_MC_tRTP) -#define V_BCM1480_MC_tRTP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRTP) -#define G_BCM1480_MC_tRTP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRTP,M_BCM1480_MC_tRTP) +#define M_BCM1480_MC_tRTP _SB_MAKEMASK(3, S_BCM1480_MC_tRTP) +#define V_BCM1480_MC_tRTP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRTP) +#define G_BCM1480_MC_tRTP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRTP, M_BCM1480_MC_tRTP) #define K_BCM1480_MC_tRTP_DEFAULT 2 #define V_BCM1480_MC_tRTP_DEFAULT V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT) #define S_BCM1480_MC_tW2W 8 -#define M_BCM1480_MC_tW2W _SB_MAKEMASK(2,S_BCM1480_MC_tW2W) -#define V_BCM1480_MC_tW2W(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tW2W) -#define G_BCM1480_MC_tW2W(x) _SB_GETVALUE(x,S_BCM1480_MC_tW2W,M_BCM1480_MC_tW2W) +#define M_BCM1480_MC_tW2W _SB_MAKEMASK(2, S_BCM1480_MC_tW2W) +#define V_BCM1480_MC_tW2W(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tW2W) +#define G_BCM1480_MC_tW2W(x) _SB_GETVALUE(x, S_BCM1480_MC_tW2W, M_BCM1480_MC_tW2W) #define K_BCM1480_MC_tW2W_DEFAULT 0 #define V_BCM1480_MC_tW2W_DEFAULT V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT) #define S_BCM1480_MC_tRAP 12 -#define M_BCM1480_MC_tRAP _SB_MAKEMASK(4,S_BCM1480_MC_tRAP) -#define V_BCM1480_MC_tRAP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRAP) -#define G_BCM1480_MC_tRAP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRAP,M_BCM1480_MC_tRAP) +#define M_BCM1480_MC_tRAP _SB_MAKEMASK(4, S_BCM1480_MC_tRAP) +#define V_BCM1480_MC_tRAP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRAP) +#define G_BCM1480_MC_tRAP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRAP, M_BCM1480_MC_tRAP) #define K_BCM1480_MC_tRAP_DEFAULT 0 #define V_BCM1480_MC_tRAP_DEFAULT V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT) @@ -875,30 +875,30 @@ */ #define S_BCM1480_MC_BLK_SET_MARK 8 -#define M_BCM1480_MC_BLK_SET_MARK _SB_MAKEMASK(4,S_BCM1480_MC_BLK_SET_MARK) -#define V_BCM1480_MC_BLK_SET_MARK(x) _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_SET_MARK) -#define G_BCM1480_MC_BLK_SET_MARK(x) _SB_GETVALUE(x,S_BCM1480_MC_BLK_SET_MARK,M_BCM1480_MC_BLK_SET_MARK) +#define M_BCM1480_MC_BLK_SET_MARK _SB_MAKEMASK(4, S_BCM1480_MC_BLK_SET_MARK) +#define V_BCM1480_MC_BLK_SET_MARK(x) _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_SET_MARK) +#define G_BCM1480_MC_BLK_SET_MARK(x) _SB_GETVALUE(x, S_BCM1480_MC_BLK_SET_MARK, M_BCM1480_MC_BLK_SET_MARK) #define S_BCM1480_MC_BLK_CLR_MARK 12 -#define M_BCM1480_MC_BLK_CLR_MARK _SB_MAKEMASK(4,S_BCM1480_MC_BLK_CLR_MARK) -#define V_BCM1480_MC_BLK_CLR_MARK(x) _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_CLR_MARK) -#define G_BCM1480_MC_BLK_CLR_MARK(x) _SB_GETVALUE(x,S_BCM1480_MC_BLK_CLR_MARK,M_BCM1480_MC_BLK_CLR_MARK) +#define M_BCM1480_MC_BLK_CLR_MARK _SB_MAKEMASK(4, S_BCM1480_MC_BLK_CLR_MARK) +#define V_BCM1480_MC_BLK_CLR_MARK(x) _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_CLR_MARK) +#define G_BCM1480_MC_BLK_CLR_MARK(x) _SB_GETVALUE(x, S_BCM1480_MC_BLK_CLR_MARK, M_BCM1480_MC_BLK_CLR_MARK) #define M_BCM1480_MC_PKT_PRIORITY _SB_MAKEMASK1(16) #define S_BCM1480_MC_MAX_AGE 20 -#define M_BCM1480_MC_MAX_AGE _SB_MAKEMASK(4,S_BCM1480_MC_MAX_AGE) -#define V_BCM1480_MC_MAX_AGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_MAX_AGE) -#define G_BCM1480_MC_MAX_AGE(x) _SB_GETVALUE(x,S_BCM1480_MC_MAX_AGE,M_BCM1480_MC_MAX_AGE) +#define M_BCM1480_MC_MAX_AGE _SB_MAKEMASK(4, S_BCM1480_MC_MAX_AGE) +#define V_BCM1480_MC_MAX_AGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_MAX_AGE) +#define G_BCM1480_MC_MAX_AGE(x) _SB_GETVALUE(x, S_BCM1480_MC_MAX_AGE, M_BCM1480_MC_MAX_AGE) #define M_BCM1480_MC_BERR_DISABLE _SB_MAKEMASK1(29) #define M_BCM1480_MC_FORCE_SEQ _SB_MAKEMASK1(30) #define M_BCM1480_MC_VGEN _SB_MAKEMASK1(32) #define S_BCM1480_MC_SLEW 33 -#define M_BCM1480_MC_SLEW _SB_MAKEMASK(2,S_BCM1480_MC_SLEW) -#define V_BCM1480_MC_SLEW(x) _SB_MAKEVALUE(x,S_BCM1480_MC_SLEW) -#define G_BCM1480_MC_SLEW(x) _SB_GETVALUE(x,S_BCM1480_MC_SLEW,M_BCM1480_MC_SLEW) +#define M_BCM1480_MC_SLEW _SB_MAKEMASK(2, S_BCM1480_MC_SLEW) +#define V_BCM1480_MC_SLEW(x) _SB_MAKEVALUE(x, S_BCM1480_MC_SLEW) +#define G_BCM1480_MC_SLEW(x) _SB_GETVALUE(x, S_BCM1480_MC_SLEW, M_BCM1480_MC_SLEW) #define M_BCM1480_MC_SSTL_VOLTAGE _SB_MAKEMASK1(35) @@ -907,19 +907,19 @@ */ #define S_BCM1480_MC_INTLV0 0 -#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0) -#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0) -#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0) +#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0) +#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0) +#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0) #define S_BCM1480_MC_INTLV1 8 -#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1) -#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1) -#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1) +#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1) +#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1) +#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1) #define S_BCM1480_MC_INTLV_MODE 16 -#define M_BCM1480_MC_INTLV_MODE _SB_MAKEMASK(3,S_BCM1480_MC_INTLV_MODE) -#define V_BCM1480_MC_INTLV_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV_MODE) -#define G_BCM1480_MC_INTLV_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV_MODE,M_BCM1480_MC_INTLV_MODE) +#define M_BCM1480_MC_INTLV_MODE _SB_MAKEMASK(3, S_BCM1480_MC_INTLV_MODE) +#define V_BCM1480_MC_INTLV_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV_MODE) +#define G_BCM1480_MC_INTLV_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV_MODE, M_BCM1480_MC_INTLV_MODE) #define K_BCM1480_MC_INTLV_MODE_NONE 0x0 #define K_BCM1480_MC_INTLV_MODE_01 0x1 @@ -938,9 +938,9 @@ */ #define S_BCM1480_MC_ECC_ERR_ADDR 0 -#define M_BCM1480_MC_ECC_ERR_ADDR _SB_MAKEMASK(37,S_BCM1480_MC_ECC_ERR_ADDR) -#define V_BCM1480_MC_ECC_ERR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR) -#define G_BCM1480_MC_ECC_ERR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR,M_BCM1480_MC_ECC_ERR_ADDR) +#define M_BCM1480_MC_ECC_ERR_ADDR _SB_MAKEMASK(37, S_BCM1480_MC_ECC_ERR_ADDR) +#define V_BCM1480_MC_ECC_ERR_ADDR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR) +#define G_BCM1480_MC_ECC_ERR_ADDR(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR, M_BCM1480_MC_ECC_ERR_ADDR) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define M_BCM1480_MC_ECC_ERR_RMW _SB_MAKEMASK1(60) @@ -955,27 +955,27 @@ */ #define S_BCM1480_MC_ECC_CORR_ADDR 0 -#define M_BCM1480_MC_ECC_CORR_ADDR _SB_MAKEMASK(37,S_BCM1480_MC_ECC_CORR_ADDR) -#define V_BCM1480_MC_ECC_CORR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR) -#define G_BCM1480_MC_ECC_CORR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR,M_BCM1480_MC_ECC_CORR_ADDR) +#define M_BCM1480_MC_ECC_CORR_ADDR _SB_MAKEMASK(37, S_BCM1480_MC_ECC_CORR_ADDR) +#define V_BCM1480_MC_ECC_CORR_ADDR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR) +#define G_BCM1480_MC_ECC_CORR_ADDR(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR, M_BCM1480_MC_ECC_CORR_ADDR) /* * Global ECC Correction Register (Table 103) */ #define S_BCM1480_MC_ECC_CORRECT 0 -#define M_BCM1480_MC_ECC_CORRECT _SB_MAKEMASK(64,S_BCM1480_MC_ECC_CORRECT) -#define V_BCM1480_MC_ECC_CORRECT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORRECT) -#define G_BCM1480_MC_ECC_CORRECT(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORRECT,M_BCM1480_MC_ECC_CORRECT) +#define M_BCM1480_MC_ECC_CORRECT _SB_MAKEMASK(64, S_BCM1480_MC_ECC_CORRECT) +#define V_BCM1480_MC_ECC_CORRECT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORRECT) +#define G_BCM1480_MC_ECC_CORRECT(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORRECT, M_BCM1480_MC_ECC_CORRECT) /* * Global ECC Performance Counters Control Register (Table 104) */ #define S_BCM1480_MC_CHANNEL_SELECT 0 -#define M_BCM1480_MC_CHANNEL_SELECT _SB_MAKEMASK(4,S_BCM1480_MC_CHANNEL_SELECT) -#define V_BCM1480_MC_CHANNEL_SELECT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CHANNEL_SELECT) -#define G_BCM1480_MC_CHANNEL_SELECT(x) _SB_GETVALUE(x,S_BCM1480_MC_CHANNEL_SELECT,M_BCM1480_MC_CHANNEL_SELECT) +#define M_BCM1480_MC_CHANNEL_SELECT _SB_MAKEMASK(4, S_BCM1480_MC_CHANNEL_SELECT) +#define V_BCM1480_MC_CHANNEL_SELECT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CHANNEL_SELECT) +#define G_BCM1480_MC_CHANNEL_SELECT(x) _SB_GETVALUE(x, S_BCM1480_MC_CHANNEL_SELECT, M_BCM1480_MC_CHANNEL_SELECT) #define K_BCM1480_MC_CHANNEL_SELECT_0 0x1 #define K_BCM1480_MC_CHANNEL_SELECT_1 0x2 #define K_BCM1480_MC_CHANNEL_SELECT_2 0x4 diff --git a/include/asm-mips/sibyte/bcm1480_regs.h b/include/asm-mips/sibyte/bcm1480_regs.h index c34d36b6b8c2..b4077bb72611 100644 --- a/include/asm-mips/sibyte/bcm1480_regs.h +++ b/include/asm-mips/sibyte/bcm1480_regs.h @@ -87,7 +87,7 @@ #define BCM1480_MC_REGISTER_SPACING 0x1000 #define A_BCM1480_MC_BASE(ctlid) (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING) -#define A_BCM1480_MC_REGISTER(ctlid,reg) (A_BCM1480_MC_BASE(ctlid)+(reg)) +#define A_BCM1480_MC_REGISTER(ctlid, reg) (A_BCM1480_MC_BASE(ctlid)+(reg)) #define R_BCM1480_MC_CONFIG 0x0000000100 #define R_BCM1480_MC_CS_START 0x0000000120 @@ -327,7 +327,7 @@ #define BCM1480_SCD_NUM_WDOGS 4 #define A_BCM1480_SCD_WDOG_BASE(w) (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100) -#define A_BCM1480_SCD_WDOG_REGISTER(w,r) (A_BCM1480_SCD_WDOG_BASE(w) + (r)) +#define A_BCM1480_SCD_WDOG_REGISTER(w, r) (A_BCM1480_SCD_WDOG_BASE(w) + (r)) #define A_BCM1480_SCD_WDOG_INIT_2 0x0010022050 #define A_BCM1480_SCD_WDOG_CNT_2 0x0010022058 @@ -372,7 +372,7 @@ #define BCM1480_IMR_REGISTER_SPACING_SHIFT 13 #define A_BCM1480_IMR_MAPPER(cpu) (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING) -#define A_BCM1480_IMR_REGISTER(cpu,reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg)) +#define A_BCM1480_IMR_REGISTER(cpu, reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg)) /* Most IMR registers are 128 bits, implemented as non-contiguous 64-bit registers high (_H) and low (_L) */ @@ -413,7 +413,7 @@ #define A_BCM1480_IMR_ALIAS_MAILBOX(cpu) (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \ (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING) -#define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu,reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg)) +#define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu, reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg)) #define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */ #define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */ @@ -427,7 +427,7 @@ #define R_BCM1480_IMR_MAILBOX_SET 0x08 #define R_BCM1480_IMR_MAILBOX_CLR 0x10 #define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20 -#define A_BCM1480_MAILBOX_REGISTER(num,reg,cpu) \ +#define A_BCM1480_MAILBOX_REGISTER(num, reg, cpu) \ (A_BCM1480_IMR_CPU0_BASE + \ (num * R_BCM1480_IMR_MAILBOX_NUM_SPACING) + \ (cpu * BCM1480_IMR_REGISTER_SPACING) + \ @@ -550,7 +550,7 @@ #define BCM1480_HR_REGISTER_SPACING 0x80000 #define A_BCM1480_HR_BASE(idx) (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING)) -#define A_BCM1480_HR_REGISTER(idx,reg) (A_BCM1480_HR_BASE(idx) + (reg)) +#define A_BCM1480_HR_REGISTER(idx, reg) (A_BCM1480_HR_BASE(idx) + (reg)) #define R_BCM1480_HR_CFG 0x0000000000 @@ -599,9 +599,9 @@ #define BCM1480_PM_NUM_CHANNELS 32 #define A_BCM1480_PMI_LCL_BASE(idx) (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) -#define A_BCM1480_PMI_LCL_REGISTER(idx,reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg)) +#define A_BCM1480_PMI_LCL_REGISTER(idx, reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg)) #define A_BCM1480_PMO_LCL_BASE(idx) (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) -#define A_BCM1480_PMO_LCL_REGISTER(idx,reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg)) +#define A_BCM1480_PMO_LCL_REGISTER(idx, reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg)) #define BCM1480_PM_INT_PACKING 8 #define BCM1480_PM_INT_FUNCTION_SPACING 0x40 @@ -721,7 +721,7 @@ #define BCM1480_HSP_REGISTER_SPACING 0x80000 #define A_BCM1480_HSP_BASE(idx) (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING)) -#define A_BCM1480_HSP_REGISTER(idx,reg) (A_BCM1480_HSP_BASE(idx) + (reg)) +#define A_BCM1480_HSP_REGISTER(idx, reg) (A_BCM1480_HSP_BASE(idx) + (reg)) #define R_BCM1480_HSP_RX_SPI4_CFG_0 0x0000000000 #define R_BCM1480_HSP_RX_SPI4_CFG_1 0x0000000008 diff --git a/include/asm-mips/sibyte/bcm1480_scd.h b/include/asm-mips/sibyte/bcm1480_scd.h index 6111d6dcf117..25ef24cbb92a 100644 --- a/include/asm-mips/sibyte/bcm1480_scd.h +++ b/include/asm-mips/sibyte/bcm1480_scd.h @@ -99,22 +99,22 @@ #define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5) #define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6) -#define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5,S_BCM1480_SYS_PLL_DIV) -#define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_PLL_DIV) -#define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_BCM1480_SYS_PLL_DIV,M_BCM1480_SYS_PLL_DIV) +#define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_PLL_DIV) +#define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_PLL_DIV) +#define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_PLL_DIV, M_BCM1480_SYS_PLL_DIV) #define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11) -#define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5,S_BCM1480_SYS_SW_DIV) -#define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_SW_DIV) -#define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x,S_BCM1480_SYS_SW_DIV,M_BCM1480_SYS_SW_DIV) +#define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_SW_DIV) +#define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_SW_DIV) +#define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_SW_DIV, M_BCM1480_SYS_SW_DIV) #define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) #define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17) #define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18) -#define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2,S_BCM1480_SYS_BOOT_MODE) -#define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_BOOT_MODE) -#define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_BCM1480_SYS_BOOT_MODE,M_BCM1480_SYS_BOOT_MODE) +#define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2, S_BCM1480_SYS_BOOT_MODE) +#define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_BOOT_MODE) +#define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_BCM1480_SYS_BOOT_MODE, M_BCM1480_SYS_BOOT_MODE) #define K_BCM1480_SYS_BOOT_MODE_ROM32 0 #define K_BCM1480_SYS_BOOT_MODE_ROM8 1 #define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2 @@ -129,16 +129,16 @@ #define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25) #define S_BCM1480_SYS_CONFIG 26 -#define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6,S_BCM1480_SYS_CONFIG) -#define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_CONFIG) -#define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x,S_BCM1480_SYS_CONFIG,M_BCM1480_SYS_CONFIG) +#define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6, S_BCM1480_SYS_CONFIG) +#define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_CONFIG) +#define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x, S_BCM1480_SYS_CONFIG, M_BCM1480_SYS_CONFIG) -#define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32,15) +#define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32, 15) #define S_BCM1480_SYS_NODEID 47 -#define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4,S_BCM1480_SYS_NODEID) -#define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_NODEID) -#define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x,S_BCM1480_SYS_NODEID,M_BCM1480_SYS_NODEID) +#define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4, S_BCM1480_SYS_NODEID) +#define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_NODEID) +#define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x, S_BCM1480_SYS_NODEID, M_BCM1480_SYS_NODEID) #define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51) #define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52) @@ -196,9 +196,9 @@ #define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0) #define S_BCM1480_SCD_WDOG_RESET_TYPE 2 -#define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5,S_BCM1480_SCD_WDOG_RESET_TYPE) -#define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_WDOG_RESET_TYPE) -#define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_BCM1480_SCD_WDOG_RESET_TYPE,M_BCM1480_SCD_WDOG_RESET_TYPE) +#define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE) +#define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE) +#define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE, M_BCM1480_SCD_WDOG_RESET_TYPE) #define K_BCM1480_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ #define K_BCM1480_SCD_WDOG_RESET_SOFT 1 @@ -244,24 +244,24 @@ */ #define S_SPC_CFG_SRC4 32 -#define M_SPC_CFG_SRC4 _SB_MAKEMASK(8,S_SPC_CFG_SRC4) -#define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC4) -#define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x,S_SPC_CFG_SRC4,M_SPC_CFG_SRC4) +#define M_SPC_CFG_SRC4 _SB_MAKEMASK(8, S_SPC_CFG_SRC4) +#define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC4) +#define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x, S_SPC_CFG_SRC4, M_SPC_CFG_SRC4) #define S_SPC_CFG_SRC5 40 -#define M_SPC_CFG_SRC5 _SB_MAKEMASK(8,S_SPC_CFG_SRC5) -#define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC5) -#define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x,S_SPC_CFG_SRC5,M_SPC_CFG_SRC5) +#define M_SPC_CFG_SRC5 _SB_MAKEMASK(8, S_SPC_CFG_SRC5) +#define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC5) +#define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x, S_SPC_CFG_SRC5, M_SPC_CFG_SRC5) #define S_SPC_CFG_SRC6 48 -#define M_SPC_CFG_SRC6 _SB_MAKEMASK(8,S_SPC_CFG_SRC6) -#define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC6) -#define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x,S_SPC_CFG_SRC6,M_SPC_CFG_SRC6) +#define M_SPC_CFG_SRC6 _SB_MAKEMASK(8, S_SPC_CFG_SRC6) +#define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC6) +#define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x, S_SPC_CFG_SRC6, M_SPC_CFG_SRC6) #define S_SPC_CFG_SRC7 56 -#define M_SPC_CFG_SRC7 _SB_MAKEMASK(8,S_SPC_CFG_SRC7) -#define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC7) -#define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x,S_SPC_CFG_SRC7,M_SPC_CFG_SRC7) +#define M_SPC_CFG_SRC7 _SB_MAKEMASK(8, S_SPC_CFG_SRC7) +#define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC7) +#define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x, S_SPC_CFG_SRC7, M_SPC_CFG_SRC7) /* * System Performance Counter Control Register (Table 32) @@ -281,9 +281,9 @@ */ #define S_BCM1480_SPC_CNT_COUNT 0 -#define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40,S_BCM1480_SPC_CNT_COUNT) -#define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CNT_COUNT) -#define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x,S_BCM1480_SPC_CNT_COUNT,M_BCM1480_SPC_CNT_COUNT) +#define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40, S_BCM1480_SPC_CNT_COUNT) +#define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x, S_BCM1480_SPC_CNT_COUNT) +#define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x, S_BCM1480_SPC_CNT_COUNT, M_BCM1480_SPC_CNT_COUNT) #define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40) @@ -322,13 +322,13 @@ * slightly different. */ -#define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4,0) -#define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40,0) +#define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4, 0) +#define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40, 0) #define S_BCM1480_ATRAP_CFG_CNT 0 -#define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_BCM1480_ATRAP_CFG_CNT) -#define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_CNT) -#define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_CNT,M_BCM1480_ATRAP_CFG_CNT) +#define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_BCM1480_ATRAP_CFG_CNT) +#define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CNT) +#define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CNT, M_BCM1480_ATRAP_CFG_CNT) #define M_BCM1480_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) #define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4) @@ -337,9 +337,9 @@ #define M_BCM1480_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) #define S_BCM1480_ATRAP_CFG_AGENTID 8 -#define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_BCM1480_ATRAP_CFG_AGENTID) -#define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_AGENTID) -#define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_AGENTID,M_BCM1480_ATRAP_CFG_AGENTID) +#define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_BCM1480_ATRAP_CFG_AGENTID) +#define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID) +#define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID, M_BCM1480_ATRAP_CFG_AGENTID) #define K_BCM1480_BUS_AGENT_CPU0 0 @@ -354,9 +354,9 @@ #define K_BCM1480_BUS_AGENT_PM 10 #define S_BCM1480_ATRAP_CFG_CATTR 12 -#define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2,S_BCM1480_ATRAP_CFG_CATTR) -#define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_CATTR) -#define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_CATTR,M_BCM1480_ATRAP_CFG_CATTR) +#define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2, S_BCM1480_ATRAP_CFG_CATTR) +#define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CATTR) +#define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CATTR, M_BCM1480_ATRAP_CFG_CATTR) #define K_BCM1480_ATRAP_CFG_CATTR_IGNORE 0 #define K_BCM1480_ATRAP_CFG_CATTR_UNC 1 @@ -382,9 +382,9 @@ #define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN _SB_MAKEMASK1(25) #define S_BCM1480_SCD_TRSEQ_SWFUNC 26 -#define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2,S_BCM1480_SCD_TRSEQ_SWFUNC) -#define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRSEQ_SWFUNC) -#define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRSEQ_SWFUNC,M_BCM1480_SCD_TRSEQ_SWFUNC) +#define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2, S_BCM1480_SCD_TRSEQ_SWFUNC) +#define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC) +#define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC, M_BCM1480_SCD_TRSEQ_SWFUNC) /* * Trace Control Register (Table 49) @@ -395,9 +395,9 @@ */ #define S_BCM1480_SCD_TRACE_CFG_MODE 16 -#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2,S_BCM1480_SCD_TRACE_CFG_MODE) -#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE) -#define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE,M_BCM1480_SCD_TRACE_CFG_MODE) +#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2, S_BCM1480_SCD_TRACE_CFG_MODE) +#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE) +#define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE, M_BCM1480_SCD_TRACE_CFG_MODE) #define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS 0 #define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1 diff --git a/include/asm-mips/sibyte/board.h b/include/asm-mips/sibyte/board.h index 73bce901a378..da198a1c8c81 100644 --- a/include/asm-mips/sibyte/board.h +++ b/include/asm-mips/sibyte/board.h @@ -41,7 +41,7 @@ #ifdef __ASSEMBLY__ #ifdef LEDS_PHYS -#define setleds(t0,t1,c0,c1,c2,c3) \ +#define setleds(t0, t1, c0, c1, c2, c3) \ li t0, (LEDS_PHYS|0xa0000000); \ li t1, c0; \ sb t1, 0x18(t0); \ @@ -52,7 +52,7 @@ li t1, c3; \ sb t1, 0x00(t0) #else -#define setleds(t0,t1,c0,c1,c2,c3) +#define setleds(t0, t1, c0, c1, c2, c3) #endif /* LEDS_PHYS */ #else diff --git a/include/asm-mips/sibyte/sb1250_defs.h b/include/asm-mips/sibyte/sb1250_defs.h index a885491217c1..09365f9111fa 100644 --- a/include/asm-mips/sibyte/sb1250_defs.h +++ b/include/asm-mips/sibyte/sb1250_defs.h @@ -232,18 +232,18 @@ * Make a mask for 'v' bits at position 'n' */ -#define _SB_MAKEMASK(v,n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n)) -#define _SB_MAKEMASK_32(v,n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n)) +#define _SB_MAKEMASK(v, n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n)) +#define _SB_MAKEMASK_32(v, n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n)) /* * Make a value at 'v' at bit position 'n' */ -#define _SB_MAKEVALUE(v,n) (_SB_MAKE64(v) << _SB_MAKE64(n)) -#define _SB_MAKEVALUE_32(v,n) (_SB_MAKE32(v) << _SB_MAKE32(n)) +#define _SB_MAKEVALUE(v, n) (_SB_MAKE64(v) << _SB_MAKE64(n)) +#define _SB_MAKEVALUE_32(v, n) (_SB_MAKE32(v) << _SB_MAKE32(n)) -#define _SB_GETVALUE(v,n,m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n)) -#define _SB_GETVALUE_32(v,n,m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n)) +#define _SB_GETVALUE(v, n, m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n)) +#define _SB_GETVALUE_32(v, n, m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n)) /* * Macros to read/write on-chip registers @@ -252,7 +252,7 @@ #if defined(__mips64) && !defined(__ASSEMBLY__) -#define SBWRITECSR(csr,val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val) +#define SBWRITECSR(csr, val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val) #define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr))) #endif /* __ASSEMBLY__ */ diff --git a/include/asm-mips/sibyte/sb1250_dma.h b/include/asm-mips/sibyte/sb1250_dma.h index e6145f524fbd..bad56171d747 100644 --- a/include/asm-mips/sibyte/sb1250_dma.h +++ b/include/asm-mips/sibyte/sb1250_dma.h @@ -57,9 +57,9 @@ #define M_DMA_RESERVED1 _SB_MAKEMASK1(2) #define S_DMA_DESC_TYPE _SB_MAKE64(1) -#define M_DMA_DESC_TYPE _SB_MAKEMASK(2,S_DMA_DESC_TYPE) -#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x,S_DMA_DESC_TYPE) -#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE) +#define M_DMA_DESC_TYPE _SB_MAKEMASK(2, S_DMA_DESC_TYPE) +#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x, S_DMA_DESC_TYPE) +#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x, S_DMA_DESC_TYPE, M_DMA_DESC_TYPE) #define K_DMA_DESC_TYPE_RING_AL 0 #define K_DMA_DESC_TYPE_CHAIN_AL 1 @@ -76,24 +76,24 @@ #define M_DMA_TDX_EN _SB_MAKEMASK1(7) #define S_DMA_INT_PKTCNT _SB_MAKE64(8) -#define M_DMA_INT_PKTCNT _SB_MAKEMASK(8,S_DMA_INT_PKTCNT) -#define V_DMA_INT_PKTCNT(x) _SB_MAKEVALUE(x,S_DMA_INT_PKTCNT) -#define G_DMA_INT_PKTCNT(x) _SB_GETVALUE(x,S_DMA_INT_PKTCNT,M_DMA_INT_PKTCNT) +#define M_DMA_INT_PKTCNT _SB_MAKEMASK(8, S_DMA_INT_PKTCNT) +#define V_DMA_INT_PKTCNT(x) _SB_MAKEVALUE(x, S_DMA_INT_PKTCNT) +#define G_DMA_INT_PKTCNT(x) _SB_GETVALUE(x, S_DMA_INT_PKTCNT, M_DMA_INT_PKTCNT) #define S_DMA_RINGSZ _SB_MAKE64(16) -#define M_DMA_RINGSZ _SB_MAKEMASK(16,S_DMA_RINGSZ) -#define V_DMA_RINGSZ(x) _SB_MAKEVALUE(x,S_DMA_RINGSZ) -#define G_DMA_RINGSZ(x) _SB_GETVALUE(x,S_DMA_RINGSZ,M_DMA_RINGSZ) +#define M_DMA_RINGSZ _SB_MAKEMASK(16, S_DMA_RINGSZ) +#define V_DMA_RINGSZ(x) _SB_MAKEVALUE(x, S_DMA_RINGSZ) +#define G_DMA_RINGSZ(x) _SB_GETVALUE(x, S_DMA_RINGSZ, M_DMA_RINGSZ) #define S_DMA_HIGH_WATERMARK _SB_MAKE64(32) -#define M_DMA_HIGH_WATERMARK _SB_MAKEMASK(16,S_DMA_HIGH_WATERMARK) -#define V_DMA_HIGH_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_HIGH_WATERMARK) -#define G_DMA_HIGH_WATERMARK(x) _SB_GETVALUE(x,S_DMA_HIGH_WATERMARK,M_DMA_HIGH_WATERMARK) +#define M_DMA_HIGH_WATERMARK _SB_MAKEMASK(16, S_DMA_HIGH_WATERMARK) +#define V_DMA_HIGH_WATERMARK(x) _SB_MAKEVALUE(x, S_DMA_HIGH_WATERMARK) +#define G_DMA_HIGH_WATERMARK(x) _SB_GETVALUE(x, S_DMA_HIGH_WATERMARK, M_DMA_HIGH_WATERMARK) #define S_DMA_LOW_WATERMARK _SB_MAKE64(48) -#define M_DMA_LOW_WATERMARK _SB_MAKEMASK(16,S_DMA_LOW_WATERMARK) -#define V_DMA_LOW_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_LOW_WATERMARK) -#define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x,S_DMA_LOW_WATERMARK,M_DMA_LOW_WATERMARK) +#define M_DMA_LOW_WATERMARK _SB_MAKEMASK(16, S_DMA_LOW_WATERMARK) +#define V_DMA_LOW_WATERMARK(x) _SB_MAKEVALUE(x, S_DMA_LOW_WATERMARK) +#define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x, S_DMA_LOW_WATERMARK, M_DMA_LOW_WATERMARK) /* * Ethernet and Serial DMA Configuration Register 1 (Table 7-5) @@ -116,37 +116,37 @@ #define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ -#define M_DMA_MBZ1 _SB_MAKEMASK(6,15) +#define M_DMA_MBZ1 _SB_MAKEMASK(6, 15) #define S_DMA_HDR_SIZE _SB_MAKE64(21) -#define M_DMA_HDR_SIZE _SB_MAKEMASK(9,S_DMA_HDR_SIZE) -#define V_DMA_HDR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_HDR_SIZE) -#define G_DMA_HDR_SIZE(x) _SB_GETVALUE(x,S_DMA_HDR_SIZE,M_DMA_HDR_SIZE) +#define M_DMA_HDR_SIZE _SB_MAKEMASK(9, S_DMA_HDR_SIZE) +#define V_DMA_HDR_SIZE(x) _SB_MAKEVALUE(x, S_DMA_HDR_SIZE) +#define G_DMA_HDR_SIZE(x) _SB_GETVALUE(x, S_DMA_HDR_SIZE, M_DMA_HDR_SIZE) -#define M_DMA_MBZ2 _SB_MAKEMASK(5,32) +#define M_DMA_MBZ2 _SB_MAKEMASK(5, 32) #define S_DMA_ASICXFR_SIZE _SB_MAKE64(37) -#define M_DMA_ASICXFR_SIZE _SB_MAKEMASK(9,S_DMA_ASICXFR_SIZE) -#define V_DMA_ASICXFR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_ASICXFR_SIZE) -#define G_DMA_ASICXFR_SIZE(x) _SB_GETVALUE(x,S_DMA_ASICXFR_SIZE,M_DMA_ASICXFR_SIZE) +#define M_DMA_ASICXFR_SIZE _SB_MAKEMASK(9, S_DMA_ASICXFR_SIZE) +#define V_DMA_ASICXFR_SIZE(x) _SB_MAKEVALUE(x, S_DMA_ASICXFR_SIZE) +#define G_DMA_ASICXFR_SIZE(x) _SB_GETVALUE(x, S_DMA_ASICXFR_SIZE, M_DMA_ASICXFR_SIZE) #define S_DMA_INT_TIMEOUT _SB_MAKE64(48) -#define M_DMA_INT_TIMEOUT _SB_MAKEMASK(16,S_DMA_INT_TIMEOUT) -#define V_DMA_INT_TIMEOUT(x) _SB_MAKEVALUE(x,S_DMA_INT_TIMEOUT) -#define G_DMA_INT_TIMEOUT(x) _SB_GETVALUE(x,S_DMA_INT_TIMEOUT,M_DMA_INT_TIMEOUT) +#define M_DMA_INT_TIMEOUT _SB_MAKEMASK(16, S_DMA_INT_TIMEOUT) +#define V_DMA_INT_TIMEOUT(x) _SB_MAKEVALUE(x, S_DMA_INT_TIMEOUT) +#define G_DMA_INT_TIMEOUT(x) _SB_GETVALUE(x, S_DMA_INT_TIMEOUT, M_DMA_INT_TIMEOUT) /* * Ethernet and Serial DMA Descriptor base address (Table 7-6) */ -#define M_DMA_DSCRBASE_MBZ _SB_MAKEMASK(4,0) +#define M_DMA_DSCRBASE_MBZ _SB_MAKEMASK(4, 0) /* * ASIC Mode Base Address (Table 7-7) */ -#define M_DMA_ASIC_BASE_MBZ _SB_MAKEMASK(20,0) +#define M_DMA_ASIC_BASE_MBZ _SB_MAKEMASK(20, 0) /* * DMA Descriptor Count Registers (Table 7-8) @@ -160,9 +160,9 @@ */ #define S_DMA_CURDSCR_ADDR _SB_MAKE64(0) -#define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40,S_DMA_CURDSCR_ADDR) +#define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40, S_DMA_CURDSCR_ADDR) #define S_DMA_CURDSCR_COUNT _SB_MAKE64(40) -#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT) +#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16, S_DMA_CURDSCR_COUNT) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56) @@ -173,12 +173,12 @@ */ #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_DMA_OODLOST_RX _SB_MAKE64(0) -#define M_DMA_OODLOST_RX _SB_MAKEMASK(16,S_DMA_OODLOST_RX) -#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX) +#define M_DMA_OODLOST_RX _SB_MAKEMASK(16, S_DMA_OODLOST_RX) +#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x, S_DMA_OODLOST_RX, M_DMA_OODLOST_RX) #define S_DMA_EOP_COUNT_RX _SB_MAKE64(16) -#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX) -#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX) +#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8, S_DMA_EOP_COUNT_RX) +#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x, S_DMA_EOP_COUNT_RX, M_DMA_EOP_COUNT_RX) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ /* ********************************************************************* @@ -190,39 +190,39 @@ */ #define S_DMA_DSCRA_OFFSET _SB_MAKE64(0) -#define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5,S_DMA_DSCRA_OFFSET) -#define V_DMA_DSCRA_OFFSET(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_OFFSET) -#define G_DMA_DSCRA_OFFSET(x) _SB_GETVALUE(x,S_DMA_DSCRA_OFFSET,M_DMA_DSCRA_OFFSET) +#define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5, S_DMA_DSCRA_OFFSET) +#define V_DMA_DSCRA_OFFSET(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_OFFSET) +#define G_DMA_DSCRA_OFFSET(x) _SB_GETVALUE(x, S_DMA_DSCRA_OFFSET, M_DMA_DSCRA_OFFSET) /* Note: Don't shift the address over, just mask it with the mask below */ #define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5) -#define M_DMA_DSCRA_A_ADDR _SB_MAKEMASK(35,S_DMA_DSCRA_A_ADDR) +#define M_DMA_DSCRA_A_ADDR _SB_MAKEMASK(35, S_DMA_DSCRA_A_ADDR) #define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0) -#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA) +#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40, S_DMA_DSCRA_A_ADDR_UA) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40) -#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE) -#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE) -#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE) +#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9, S_DMA_DSCRA_A_SIZE) +#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_A_SIZE) +#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRA_A_SIZE, M_DMA_DSCRA_A_SIZE) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40) -#define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT) -#define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT) +#define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8, S_DMA_DSCRA_DSCR_CNT) +#define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x, S_DMA_DSCRA_DSCR_CNT, M_DMA_DSCRA_DSCR_CNT) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49) #define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50) #define S_DMA_DSCRA_STATUS _SB_MAKE64(51) -#define M_DMA_DSCRA_STATUS _SB_MAKEMASK(13,S_DMA_DSCRA_STATUS) -#define V_DMA_DSCRA_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_STATUS) -#define G_DMA_DSCRA_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRA_STATUS,M_DMA_DSCRA_STATUS) +#define M_DMA_DSCRA_STATUS _SB_MAKEMASK(13, S_DMA_DSCRA_STATUS) +#define V_DMA_DSCRA_STATUS(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_STATUS) +#define G_DMA_DSCRA_STATUS(x) _SB_GETVALUE(x, S_DMA_DSCRA_STATUS, M_DMA_DSCRA_STATUS) /* * Descriptor doubleword "B" (Table 7-13) @@ -230,49 +230,49 @@ #define S_DMA_DSCRB_OPTIONS _SB_MAKE64(0) -#define M_DMA_DSCRB_OPTIONS _SB_MAKEMASK(4,S_DMA_DSCRB_OPTIONS) -#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS) -#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS) +#define M_DMA_DSCRB_OPTIONS _SB_MAKEMASK(4, S_DMA_DSCRB_OPTIONS) +#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_OPTIONS) +#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x, S_DMA_DSCRB_OPTIONS, M_DMA_DSCRB_OPTIONS) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8) -#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE) -#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE) -#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE) +#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14, S_DMA_DSCRB_A_SIZE) +#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_A_SIZE) +#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_A_SIZE, M_DMA_DSCRB_A_SIZE) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10) /* Note: Don't shift the address over, just mask it with the mask below */ #define S_DMA_DSCRB_B_ADDR _SB_MAKE64(5) -#define M_DMA_DSCRB_B_ADDR _SB_MAKEMASK(35,S_DMA_DSCRB_B_ADDR) +#define M_DMA_DSCRB_B_ADDR _SB_MAKEMASK(35, S_DMA_DSCRB_B_ADDR) #define S_DMA_DSCRB_B_SIZE _SB_MAKE64(40) -#define M_DMA_DSCRB_B_SIZE _SB_MAKEMASK(9,S_DMA_DSCRB_B_SIZE) -#define V_DMA_DSCRB_B_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_B_SIZE) -#define G_DMA_DSCRB_B_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_B_SIZE,M_DMA_DSCRB_B_SIZE) +#define M_DMA_DSCRB_B_SIZE _SB_MAKEMASK(9, S_DMA_DSCRB_B_SIZE) +#define V_DMA_DSCRB_B_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_B_SIZE) +#define G_DMA_DSCRB_B_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_B_SIZE, M_DMA_DSCRB_B_SIZE) #define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48) -#define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB) -#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB) -#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB) +#define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2, S_DMA_DSCRB_PKT_SIZE_MSB) +#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB) +#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB, M_DMA_DSCRB_PKT_SIZE_MSB) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50) -#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE) -#define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE) -#define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE,M_DMA_DSCRB_PKT_SIZE) +#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14, S_DMA_DSCRB_PKT_SIZE) +#define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE) +#define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE, M_DMA_DSCRB_PKT_SIZE) /* * from pass2 some bits in dscr_b are also used for rx status */ #define S_DMA_DSCRB_STATUS _SB_MAKE64(0) -#define M_DMA_DSCRB_STATUS _SB_MAKEMASK(1,S_DMA_DSCRB_STATUS) -#define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_STATUS) -#define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRB_STATUS,M_DMA_DSCRB_STATUS) +#define M_DMA_DSCRB_STATUS _SB_MAKEMASK(1, S_DMA_DSCRB_STATUS) +#define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_STATUS) +#define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x, S_DMA_DSCRB_STATUS, M_DMA_DSCRB_STATUS) /* * Ethernet Descriptor Status Bits (Table 7-15) @@ -293,14 +293,14 @@ #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define S_DMA_ETHRX_RXCH 53 -#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH) -#define V_DMA_ETHRX_RXCH(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_RXCH) -#define G_DMA_ETHRX_RXCH(x) _SB_GETVALUE(x,S_DMA_ETHRX_RXCH,M_DMA_ETHRX_RXCH) +#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2, S_DMA_ETHRX_RXCH) +#define V_DMA_ETHRX_RXCH(x) _SB_MAKEVALUE(x, S_DMA_ETHRX_RXCH) +#define G_DMA_ETHRX_RXCH(x) _SB_GETVALUE(x, S_DMA_ETHRX_RXCH, M_DMA_ETHRX_RXCH) #define S_DMA_ETHRX_PKTTYPE 55 -#define M_DMA_ETHRX_PKTTYPE _SB_MAKEMASK(3,S_DMA_ETHRX_PKTTYPE) -#define V_DMA_ETHRX_PKTTYPE(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_PKTTYPE) -#define G_DMA_ETHRX_PKTTYPE(x) _SB_GETVALUE(x,S_DMA_ETHRX_PKTTYPE,M_DMA_ETHRX_PKTTYPE) +#define M_DMA_ETHRX_PKTTYPE _SB_MAKEMASK(3, S_DMA_ETHRX_PKTTYPE) +#define V_DMA_ETHRX_PKTTYPE(x) _SB_MAKEVALUE(x, S_DMA_ETHRX_PKTTYPE) +#define G_DMA_ETHRX_PKTTYPE(x) _SB_GETVALUE(x, S_DMA_ETHRX_PKTTYPE, M_DMA_ETHRX_PKTTYPE) #define K_DMA_ETHRX_PKTTYPE_IPV4 0 #define K_DMA_ETHRX_PKTTYPE_ARPV4 1 @@ -385,21 +385,21 @@ * Register: DM_DSCR_BASE_3 */ -#define M_DM_DSCR_BASE_MBZ _SB_MAKEMASK(4,0) +#define M_DM_DSCR_BASE_MBZ _SB_MAKEMASK(4, 0) /* Note: Just mask the base address and then OR it in. */ #define S_DM_DSCR_BASE_ADDR _SB_MAKE64(4) -#define M_DM_DSCR_BASE_ADDR _SB_MAKEMASK(36,S_DM_DSCR_BASE_ADDR) +#define M_DM_DSCR_BASE_ADDR _SB_MAKEMASK(36, S_DM_DSCR_BASE_ADDR) #define S_DM_DSCR_BASE_RINGSZ _SB_MAKE64(40) -#define M_DM_DSCR_BASE_RINGSZ _SB_MAKEMASK(16,S_DM_DSCR_BASE_RINGSZ) -#define V_DM_DSCR_BASE_RINGSZ(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_RINGSZ) -#define G_DM_DSCR_BASE_RINGSZ(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_RINGSZ,M_DM_DSCR_BASE_RINGSZ) +#define M_DM_DSCR_BASE_RINGSZ _SB_MAKEMASK(16, S_DM_DSCR_BASE_RINGSZ) +#define V_DM_DSCR_BASE_RINGSZ(x) _SB_MAKEVALUE(x, S_DM_DSCR_BASE_RINGSZ) +#define G_DM_DSCR_BASE_RINGSZ(x) _SB_GETVALUE(x, S_DM_DSCR_BASE_RINGSZ, M_DM_DSCR_BASE_RINGSZ) #define S_DM_DSCR_BASE_PRIORITY _SB_MAKE64(56) -#define M_DM_DSCR_BASE_PRIORITY _SB_MAKEMASK(3,S_DM_DSCR_BASE_PRIORITY) -#define V_DM_DSCR_BASE_PRIORITY(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_PRIORITY) -#define G_DM_DSCR_BASE_PRIORITY(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_PRIORITY,M_DM_DSCR_BASE_PRIORITY) +#define M_DM_DSCR_BASE_PRIORITY _SB_MAKEMASK(3, S_DM_DSCR_BASE_PRIORITY) +#define V_DM_DSCR_BASE_PRIORITY(x) _SB_MAKEVALUE(x, S_DM_DSCR_BASE_PRIORITY) +#define G_DM_DSCR_BASE_PRIORITY(x) _SB_GETVALUE(x, S_DM_DSCR_BASE_PRIORITY, M_DM_DSCR_BASE_PRIORITY) #define K_DM_DSCR_BASE_PRIORITY_1 0 #define K_DM_DSCR_BASE_PRIORITY_2 1 @@ -429,12 +429,12 @@ */ #define S_DM_CUR_DSCR_DSCR_ADDR _SB_MAKE64(0) -#define M_DM_CUR_DSCR_DSCR_ADDR _SB_MAKEMASK(40,S_DM_CUR_DSCR_DSCR_ADDR) +#define M_DM_CUR_DSCR_DSCR_ADDR _SB_MAKEMASK(40, S_DM_CUR_DSCR_DSCR_ADDR) #define S_DM_CUR_DSCR_DSCR_COUNT _SB_MAKE64(48) -#define M_DM_CUR_DSCR_DSCR_COUNT _SB_MAKEMASK(16,S_DM_CUR_DSCR_DSCR_COUNT) -#define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT) -#define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT,\ +#define M_DM_CUR_DSCR_DSCR_COUNT _SB_MAKEMASK(16, S_DM_CUR_DSCR_DSCR_COUNT) +#define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT) +#define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT,\ M_DM_CUR_DSCR_DSCR_COUNT) @@ -447,15 +447,15 @@ * Register: DM_PARTIAL_3 */ #define S_DM_PARTIAL_CRC_PARTIAL _SB_MAKE64(0) -#define M_DM_PARTIAL_CRC_PARTIAL _SB_MAKEMASK(32,S_DM_PARTIAL_CRC_PARTIAL) -#define V_DM_PARTIAL_CRC_PARTIAL(r) _SB_MAKEVALUE(r,S_DM_PARTIAL_CRC_PARTIAL) -#define G_DM_PARTIAL_CRC_PARTIAL(r) _SB_GETVALUE(r,S_DM_PARTIAL_CRC_PARTIAL,\ +#define M_DM_PARTIAL_CRC_PARTIAL _SB_MAKEMASK(32, S_DM_PARTIAL_CRC_PARTIAL) +#define V_DM_PARTIAL_CRC_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_CRC_PARTIAL) +#define G_DM_PARTIAL_CRC_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_CRC_PARTIAL,\ M_DM_PARTIAL_CRC_PARTIAL) #define S_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKE64(32) -#define M_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKEMASK(16,S_DM_PARTIAL_TCPCS_PARTIAL) -#define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL) -#define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL,\ +#define M_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKEMASK(16, S_DM_PARTIAL_TCPCS_PARTIAL) +#define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL) +#define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL,\ M_DM_PARTIAL_TCPCS_PARTIAL) #define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48) @@ -469,15 +469,15 @@ * Register: CRC_DEF_1 */ #define S_CRC_DEF_CRC_INIT _SB_MAKE64(0) -#define M_CRC_DEF_CRC_INIT _SB_MAKEMASK(32,S_CRC_DEF_CRC_INIT) -#define V_CRC_DEF_CRC_INIT(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_INIT) -#define G_CRC_DEF_CRC_INIT(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_INIT,\ +#define M_CRC_DEF_CRC_INIT _SB_MAKEMASK(32, S_CRC_DEF_CRC_INIT) +#define V_CRC_DEF_CRC_INIT(r) _SB_MAKEVALUE(r, S_CRC_DEF_CRC_INIT) +#define G_CRC_DEF_CRC_INIT(r) _SB_GETVALUE(r, S_CRC_DEF_CRC_INIT,\ M_CRC_DEF_CRC_INIT) #define S_CRC_DEF_CRC_POLY _SB_MAKE64(32) -#define M_CRC_DEF_CRC_POLY _SB_MAKEMASK(32,S_CRC_DEF_CRC_POLY) -#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY) -#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\ +#define M_CRC_DEF_CRC_POLY _SB_MAKEMASK(32, S_CRC_DEF_CRC_POLY) +#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r, S_CRC_DEF_CRC_POLY) +#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r, S_CRC_DEF_CRC_POLY,\ M_CRC_DEF_CRC_POLY) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ @@ -489,21 +489,21 @@ * Register: CTCP_DEF_1 */ #define S_CTCP_DEF_CRC_TXOR _SB_MAKE64(0) -#define M_CTCP_DEF_CRC_TXOR _SB_MAKEMASK(32,S_CTCP_DEF_CRC_TXOR) -#define V_CTCP_DEF_CRC_TXOR(r) _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_TXOR) -#define G_CTCP_DEF_CRC_TXOR(r) _SB_GETVALUE(r,S_CTCP_DEF_CRC_TXOR,\ +#define M_CTCP_DEF_CRC_TXOR _SB_MAKEMASK(32, S_CTCP_DEF_CRC_TXOR) +#define V_CTCP_DEF_CRC_TXOR(r) _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_TXOR) +#define G_CTCP_DEF_CRC_TXOR(r) _SB_GETVALUE(r, S_CTCP_DEF_CRC_TXOR,\ M_CTCP_DEF_CRC_TXOR) #define S_CTCP_DEF_TCPCS_INIT _SB_MAKE64(32) -#define M_CTCP_DEF_TCPCS_INIT _SB_MAKEMASK(16,S_CTCP_DEF_TCPCS_INIT) -#define V_CTCP_DEF_TCPCS_INIT(r) _SB_MAKEVALUE(r,S_CTCP_DEF_TCPCS_INIT) -#define G_CTCP_DEF_TCPCS_INIT(r) _SB_GETVALUE(r,S_CTCP_DEF_TCPCS_INIT,\ +#define M_CTCP_DEF_TCPCS_INIT _SB_MAKEMASK(16, S_CTCP_DEF_TCPCS_INIT) +#define V_CTCP_DEF_TCPCS_INIT(r) _SB_MAKEVALUE(r, S_CTCP_DEF_TCPCS_INIT) +#define G_CTCP_DEF_TCPCS_INIT(r) _SB_GETVALUE(r, S_CTCP_DEF_TCPCS_INIT,\ M_CTCP_DEF_TCPCS_INIT) #define S_CTCP_DEF_CRC_WIDTH _SB_MAKE64(48) -#define M_CTCP_DEF_CRC_WIDTH _SB_MAKEMASK(2,S_CTCP_DEF_CRC_WIDTH) -#define V_CTCP_DEF_CRC_WIDTH(r) _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_WIDTH) -#define G_CTCP_DEF_CRC_WIDTH(r) _SB_GETVALUE(r,S_CTCP_DEF_CRC_WIDTH,\ +#define M_CTCP_DEF_CRC_WIDTH _SB_MAKEMASK(2, S_CTCP_DEF_CRC_WIDTH) +#define V_CTCP_DEF_CRC_WIDTH(r) _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_WIDTH) +#define G_CTCP_DEF_CRC_WIDTH(r) _SB_GETVALUE(r, S_CTCP_DEF_CRC_WIDTH,\ M_CTCP_DEF_CRC_WIDTH) #define K_CTCP_DEF_CRC_WIDTH_4 0 @@ -519,7 +519,7 @@ */ #define S_DM_DSCRA_DST_ADDR _SB_MAKE64(0) -#define M_DM_DSCRA_DST_ADDR _SB_MAKEMASK(40,S_DM_DSCRA_DST_ADDR) +#define M_DM_DSCRA_DST_ADDR _SB_MAKEMASK(40, S_DM_DSCRA_DST_ADDR) #define M_DM_DSCRA_UN_DEST _SB_MAKEMASK1(40) #define M_DM_DSCRA_UN_SRC _SB_MAKEMASK1(41) @@ -529,30 +529,30 @@ #endif /* up to 1250 PASS1 */ #define S_DM_DSCRA_DIR_DEST _SB_MAKE64(44) -#define M_DM_DSCRA_DIR_DEST _SB_MAKEMASK(2,S_DM_DSCRA_DIR_DEST) -#define V_DM_DSCRA_DIR_DEST(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_DEST) -#define G_DM_DSCRA_DIR_DEST(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_DEST,M_DM_DSCRA_DIR_DEST) +#define M_DM_DSCRA_DIR_DEST _SB_MAKEMASK(2, S_DM_DSCRA_DIR_DEST) +#define V_DM_DSCRA_DIR_DEST(x) _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_DEST) +#define G_DM_DSCRA_DIR_DEST(x) _SB_GETVALUE(x, S_DM_DSCRA_DIR_DEST, M_DM_DSCRA_DIR_DEST) #define K_DM_DSCRA_DIR_DEST_INCR 0 #define K_DM_DSCRA_DIR_DEST_DECR 1 #define K_DM_DSCRA_DIR_DEST_CONST 2 -#define V_DM_DSCRA_DIR_DEST_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR,S_DM_DSCRA_DIR_DEST) -#define V_DM_DSCRA_DIR_DEST_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR,S_DM_DSCRA_DIR_DEST) -#define V_DM_DSCRA_DIR_DEST_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST,S_DM_DSCRA_DIR_DEST) +#define V_DM_DSCRA_DIR_DEST_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR, S_DM_DSCRA_DIR_DEST) +#define V_DM_DSCRA_DIR_DEST_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR, S_DM_DSCRA_DIR_DEST) +#define V_DM_DSCRA_DIR_DEST_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST, S_DM_DSCRA_DIR_DEST) #define S_DM_DSCRA_DIR_SRC _SB_MAKE64(46) -#define M_DM_DSCRA_DIR_SRC _SB_MAKEMASK(2,S_DM_DSCRA_DIR_SRC) -#define V_DM_DSCRA_DIR_SRC(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_SRC) -#define G_DM_DSCRA_DIR_SRC(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_SRC,M_DM_DSCRA_DIR_SRC) +#define M_DM_DSCRA_DIR_SRC _SB_MAKEMASK(2, S_DM_DSCRA_DIR_SRC) +#define V_DM_DSCRA_DIR_SRC(x) _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_SRC) +#define G_DM_DSCRA_DIR_SRC(x) _SB_GETVALUE(x, S_DM_DSCRA_DIR_SRC, M_DM_DSCRA_DIR_SRC) #define K_DM_DSCRA_DIR_SRC_INCR 0 #define K_DM_DSCRA_DIR_SRC_DECR 1 #define K_DM_DSCRA_DIR_SRC_CONST 2 -#define V_DM_DSCRA_DIR_SRC_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR,S_DM_DSCRA_DIR_SRC) -#define V_DM_DSCRA_DIR_SRC_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR,S_DM_DSCRA_DIR_SRC) -#define V_DM_DSCRA_DIR_SRC_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST,S_DM_DSCRA_DIR_SRC) +#define V_DM_DSCRA_DIR_SRC_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR, S_DM_DSCRA_DIR_SRC) +#define V_DM_DSCRA_DIR_SRC_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR, S_DM_DSCRA_DIR_SRC) +#define V_DM_DSCRA_DIR_SRC_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST, S_DM_DSCRA_DIR_SRC) #define M_DM_DSCRA_ZERO_MEM _SB_MAKEMASK1(48) @@ -576,19 +576,19 @@ #define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ -#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3,61) +#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3, 61) /* * Data Mover Descriptor Doubleword "B" (Table 7-25) */ #define S_DM_DSCRB_SRC_ADDR _SB_MAKE64(0) -#define M_DM_DSCRB_SRC_ADDR _SB_MAKEMASK(40,S_DM_DSCRB_SRC_ADDR) +#define M_DM_DSCRB_SRC_ADDR _SB_MAKEMASK(40, S_DM_DSCRB_SRC_ADDR) #define S_DM_DSCRB_SRC_LENGTH _SB_MAKE64(40) -#define M_DM_DSCRB_SRC_LENGTH _SB_MAKEMASK(20,S_DM_DSCRB_SRC_LENGTH) -#define V_DM_DSCRB_SRC_LENGTH(x) _SB_MAKEVALUE(x,S_DM_DSCRB_SRC_LENGTH) -#define G_DM_DSCRB_SRC_LENGTH(x) _SB_GETVALUE(x,S_DM_DSCRB_SRC_LENGTH,M_DM_DSCRB_SRC_LENGTH) +#define M_DM_DSCRB_SRC_LENGTH _SB_MAKEMASK(20, S_DM_DSCRB_SRC_LENGTH) +#define V_DM_DSCRB_SRC_LENGTH(x) _SB_MAKEVALUE(x, S_DM_DSCRB_SRC_LENGTH) +#define G_DM_DSCRB_SRC_LENGTH(x) _SB_GETVALUE(x, S_DM_DSCRB_SRC_LENGTH, M_DM_DSCRB_SRC_LENGTH) #endif diff --git a/include/asm-mips/sibyte/sb1250_genbus.h b/include/asm-mips/sibyte/sb1250_genbus.h index 1b5cbc5c6454..94e9c7c8e783 100644 --- a/include/asm-mips/sibyte/sb1250_genbus.h +++ b/include/asm-mips/sibyte/sb1250_genbus.h @@ -11,7 +11,7 @@ * ********************************************************************* * - * Copyright 2000,2001,2002,2003 + * Copyright 2000, 2001, 2002, 2003 * Broadcom Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or @@ -47,7 +47,7 @@ #define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY) #define S_IO_WIDTH_SEL 2 -#define M_IO_WIDTH_SEL _SB_MAKEMASK(2,S_IO_WIDTH_SEL) +#define M_IO_WIDTH_SEL _SB_MAKEMASK(2, S_IO_WIDTH_SEL) #define K_IO_WIDTH_SEL_1 0 #define K_IO_WIDTH_SEL_2 1 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ @@ -55,8 +55,8 @@ #define K_IO_WIDTH_SEL_1L 2 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define K_IO_WIDTH_SEL_4 3 -#define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x,S_IO_WIDTH_SEL) -#define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL) +#define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x, S_IO_WIDTH_SEL) +#define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x, S_IO_WIDTH_SEL, M_IO_WIDTH_SEL) #define S_IO_PARITY_ENA 4 #define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA) @@ -71,18 +71,18 @@ #define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX) #define S_IO_TIMEOUT 8 -#define M_IO_TIMEOUT _SB_MAKEMASK(8,S_IO_TIMEOUT) -#define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x,S_IO_TIMEOUT) -#define G_IO_TIMEOUT(x) _SB_GETVALUE(x,S_IO_TIMEOUT,M_IO_TIMEOUT) +#define M_IO_TIMEOUT _SB_MAKEMASK(8, S_IO_TIMEOUT) +#define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x, S_IO_TIMEOUT) +#define G_IO_TIMEOUT(x) _SB_GETVALUE(x, S_IO_TIMEOUT, M_IO_TIMEOUT) /* * Generic Bus Region Size register (Table 11-5) */ #define S_IO_MULT_SIZE 0 -#define M_IO_MULT_SIZE _SB_MAKEMASK(12,S_IO_MULT_SIZE) -#define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x,S_IO_MULT_SIZE) -#define G_IO_MULT_SIZE(x) _SB_GETVALUE(x,S_IO_MULT_SIZE,M_IO_MULT_SIZE) +#define M_IO_MULT_SIZE _SB_MAKEMASK(12, S_IO_MULT_SIZE) +#define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x, S_IO_MULT_SIZE) +#define G_IO_MULT_SIZE(x) _SB_GETVALUE(x, S_IO_MULT_SIZE, M_IO_MULT_SIZE) #define S_IO_REGSIZE 16 /* # bits to shift size for this reg */ @@ -91,9 +91,9 @@ */ #define S_IO_START_ADDR 0 -#define M_IO_START_ADDR _SB_MAKEMASK(14,S_IO_START_ADDR) -#define V_IO_START_ADDR(x) _SB_MAKEVALUE(x,S_IO_START_ADDR) -#define G_IO_START_ADDR(x) _SB_GETVALUE(x,S_IO_START_ADDR,M_IO_START_ADDR) +#define M_IO_START_ADDR _SB_MAKEMASK(14, S_IO_START_ADDR) +#define V_IO_START_ADDR(x) _SB_MAKEVALUE(x, S_IO_START_ADDR) +#define G_IO_START_ADDR(x) _SB_GETVALUE(x, S_IO_START_ADDR, M_IO_START_ADDR) #define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */ @@ -105,9 +105,9 @@ */ #define S_IO_ALE_WIDTH 0 -#define M_IO_ALE_WIDTH _SB_MAKEMASK(3,S_IO_ALE_WIDTH) -#define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_ALE_WIDTH) -#define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH) +#define M_IO_ALE_WIDTH _SB_MAKEMASK(3, S_IO_ALE_WIDTH) +#define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_ALE_WIDTH) +#define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x, S_IO_ALE_WIDTH, M_IO_ALE_WIDTH) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ || SIBYTE_HDR_FEATURE_CHIP(1480) @@ -115,27 +115,27 @@ #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define S_IO_ALE_TO_CS 4 -#define M_IO_ALE_TO_CS _SB_MAKEMASK(2,S_IO_ALE_TO_CS) -#define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_CS) -#define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS) +#define M_IO_ALE_TO_CS _SB_MAKEMASK(2, S_IO_ALE_TO_CS) +#define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_CS) +#define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x, S_IO_ALE_TO_CS, M_IO_ALE_TO_CS) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_IO_BURST_WIDTH _SB_MAKE64(6) -#define M_IO_BURST_WIDTH _SB_MAKEMASK(2,S_IO_BURST_WIDTH) -#define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x,S_IO_BURST_WIDTH) -#define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x,S_IO_BURST_WIDTH,M_IO_BURST_WIDTH) +#define M_IO_BURST_WIDTH _SB_MAKEMASK(2, S_IO_BURST_WIDTH) +#define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x, S_IO_BURST_WIDTH) +#define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x, S_IO_BURST_WIDTH, M_IO_BURST_WIDTH) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define S_IO_CS_WIDTH 8 -#define M_IO_CS_WIDTH _SB_MAKEMASK(5,S_IO_CS_WIDTH) -#define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x,S_IO_CS_WIDTH) -#define G_IO_CS_WIDTH(x) _SB_GETVALUE(x,S_IO_CS_WIDTH,M_IO_CS_WIDTH) +#define M_IO_CS_WIDTH _SB_MAKEMASK(5, S_IO_CS_WIDTH) +#define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x, S_IO_CS_WIDTH) +#define G_IO_CS_WIDTH(x) _SB_GETVALUE(x, S_IO_CS_WIDTH, M_IO_CS_WIDTH) #define S_IO_RDY_SMPLE 13 -#define M_IO_RDY_SMPLE _SB_MAKEMASK(3,S_IO_RDY_SMPLE) -#define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x,S_IO_RDY_SMPLE) -#define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x,S_IO_RDY_SMPLE,M_IO_RDY_SMPLE) +#define M_IO_RDY_SMPLE _SB_MAKEMASK(3, S_IO_RDY_SMPLE) +#define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x, S_IO_RDY_SMPLE) +#define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x, S_IO_RDY_SMPLE, M_IO_RDY_SMPLE) /* @@ -143,9 +143,9 @@ */ #define S_IO_ALE_TO_WRITE 0 -#define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3,S_IO_ALE_TO_WRITE) -#define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE) -#define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE) +#define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3, S_IO_ALE_TO_WRITE) +#define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_WRITE) +#define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x, S_IO_ALE_TO_WRITE, M_IO_ALE_TO_WRITE) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ || SIBYTE_HDR_FEATURE_CHIP(1480) @@ -153,30 +153,30 @@ #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define S_IO_WRITE_WIDTH 4 -#define M_IO_WRITE_WIDTH _SB_MAKEMASK(4,S_IO_WRITE_WIDTH) -#define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_WRITE_WIDTH) -#define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x,S_IO_WRITE_WIDTH,M_IO_WRITE_WIDTH) +#define M_IO_WRITE_WIDTH _SB_MAKEMASK(4, S_IO_WRITE_WIDTH) +#define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_WRITE_WIDTH) +#define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x, S_IO_WRITE_WIDTH, M_IO_WRITE_WIDTH) #define S_IO_IDLE_CYCLE 8 -#define M_IO_IDLE_CYCLE _SB_MAKEMASK(4,S_IO_IDLE_CYCLE) -#define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x,S_IO_IDLE_CYCLE) -#define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x,S_IO_IDLE_CYCLE,M_IO_IDLE_CYCLE) +#define M_IO_IDLE_CYCLE _SB_MAKEMASK(4, S_IO_IDLE_CYCLE) +#define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x, S_IO_IDLE_CYCLE) +#define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x, S_IO_IDLE_CYCLE, M_IO_IDLE_CYCLE) #define S_IO_OE_TO_CS 12 -#define M_IO_OE_TO_CS _SB_MAKEMASK(2,S_IO_OE_TO_CS) -#define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_OE_TO_CS) -#define G_IO_OE_TO_CS(x) _SB_GETVALUE(x,S_IO_OE_TO_CS,M_IO_OE_TO_CS) +#define M_IO_OE_TO_CS _SB_MAKEMASK(2, S_IO_OE_TO_CS) +#define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_OE_TO_CS) +#define G_IO_OE_TO_CS(x) _SB_GETVALUE(x, S_IO_OE_TO_CS, M_IO_OE_TO_CS) #define S_IO_CS_TO_OE 14 -#define M_IO_CS_TO_OE _SB_MAKEMASK(2,S_IO_CS_TO_OE) -#define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x,S_IO_CS_TO_OE) -#define G_IO_CS_TO_OE(x) _SB_GETVALUE(x,S_IO_CS_TO_OE,M_IO_CS_TO_OE) +#define M_IO_CS_TO_OE _SB_MAKEMASK(2, S_IO_CS_TO_OE) +#define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x, S_IO_CS_TO_OE) +#define G_IO_CS_TO_OE(x) _SB_GETVALUE(x, S_IO_CS_TO_OE, M_IO_CS_TO_OE) /* * Generic Bus Interrupt Status Register (Table 11-9) */ -#define M_IO_CS_ERR_INT _SB_MAKEMASK(0,8) +#define M_IO_CS_ERR_INT _SB_MAKEMASK(0, 8) #define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0) #define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1) #define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2) @@ -200,116 +200,116 @@ */ #define S_IO_SLEW0 0 -#define M_IO_SLEW0 _SB_MAKEMASK(2,S_IO_SLEW0) -#define V_IO_SLEW0(x) _SB_MAKEVALUE(x,S_IO_SLEW0) -#define G_IO_SLEW0(x) _SB_GETVALUE(x,S_IO_SLEW0,M_IO_SLEW0) +#define M_IO_SLEW0 _SB_MAKEMASK(2, S_IO_SLEW0) +#define V_IO_SLEW0(x) _SB_MAKEVALUE(x, S_IO_SLEW0) +#define G_IO_SLEW0(x) _SB_GETVALUE(x, S_IO_SLEW0, M_IO_SLEW0) #define S_IO_DRV_A 2 -#define M_IO_DRV_A _SB_MAKEMASK(2,S_IO_DRV_A) -#define V_IO_DRV_A(x) _SB_MAKEVALUE(x,S_IO_DRV_A) -#define G_IO_DRV_A(x) _SB_GETVALUE(x,S_IO_DRV_A,M_IO_DRV_A) +#define M_IO_DRV_A _SB_MAKEMASK(2, S_IO_DRV_A) +#define V_IO_DRV_A(x) _SB_MAKEVALUE(x, S_IO_DRV_A) +#define G_IO_DRV_A(x) _SB_GETVALUE(x, S_IO_DRV_A, M_IO_DRV_A) #define S_IO_DRV_B 6 -#define M_IO_DRV_B _SB_MAKEMASK(2,S_IO_DRV_B) -#define V_IO_DRV_B(x) _SB_MAKEVALUE(x,S_IO_DRV_B) -#define G_IO_DRV_B(x) _SB_GETVALUE(x,S_IO_DRV_B,M_IO_DRV_B) +#define M_IO_DRV_B _SB_MAKEMASK(2, S_IO_DRV_B) +#define V_IO_DRV_B(x) _SB_MAKEVALUE(x, S_IO_DRV_B) +#define G_IO_DRV_B(x) _SB_GETVALUE(x, S_IO_DRV_B, M_IO_DRV_B) #define S_IO_DRV_C 10 -#define M_IO_DRV_C _SB_MAKEMASK(2,S_IO_DRV_C) -#define V_IO_DRV_C(x) _SB_MAKEVALUE(x,S_IO_DRV_C) -#define G_IO_DRV_C(x) _SB_GETVALUE(x,S_IO_DRV_C,M_IO_DRV_C) +#define M_IO_DRV_C _SB_MAKEMASK(2, S_IO_DRV_C) +#define V_IO_DRV_C(x) _SB_MAKEVALUE(x, S_IO_DRV_C) +#define G_IO_DRV_C(x) _SB_GETVALUE(x, S_IO_DRV_C, M_IO_DRV_C) #define S_IO_DRV_D 14 -#define M_IO_DRV_D _SB_MAKEMASK(2,S_IO_DRV_D) -#define V_IO_DRV_D(x) _SB_MAKEVALUE(x,S_IO_DRV_D) -#define G_IO_DRV_D(x) _SB_GETVALUE(x,S_IO_DRV_D,M_IO_DRV_D) +#define M_IO_DRV_D _SB_MAKEMASK(2, S_IO_DRV_D) +#define V_IO_DRV_D(x) _SB_MAKEVALUE(x, S_IO_DRV_D) +#define G_IO_DRV_D(x) _SB_GETVALUE(x, S_IO_DRV_D, M_IO_DRV_D) /* * Generic Bus Output Drive Control Register 1 (Table 14-19) */ #define S_IO_DRV_E 2 -#define M_IO_DRV_E _SB_MAKEMASK(2,S_IO_DRV_E) -#define V_IO_DRV_E(x) _SB_MAKEVALUE(x,S_IO_DRV_E) -#define G_IO_DRV_E(x) _SB_GETVALUE(x,S_IO_DRV_E,M_IO_DRV_E) +#define M_IO_DRV_E _SB_MAKEMASK(2, S_IO_DRV_E) +#define V_IO_DRV_E(x) _SB_MAKEVALUE(x, S_IO_DRV_E) +#define G_IO_DRV_E(x) _SB_GETVALUE(x, S_IO_DRV_E, M_IO_DRV_E) #define S_IO_DRV_F 6 -#define M_IO_DRV_F _SB_MAKEMASK(2,S_IO_DRV_F) -#define V_IO_DRV_F(x) _SB_MAKEVALUE(x,S_IO_DRV_F) -#define G_IO_DRV_F(x) _SB_GETVALUE(x,S_IO_DRV_F,M_IO_DRV_F) +#define M_IO_DRV_F _SB_MAKEMASK(2, S_IO_DRV_F) +#define V_IO_DRV_F(x) _SB_MAKEVALUE(x, S_IO_DRV_F) +#define G_IO_DRV_F(x) _SB_GETVALUE(x, S_IO_DRV_F, M_IO_DRV_F) #define S_IO_SLEW1 8 -#define M_IO_SLEW1 _SB_MAKEMASK(2,S_IO_SLEW1) -#define V_IO_SLEW1(x) _SB_MAKEVALUE(x,S_IO_SLEW1) -#define G_IO_SLEW1(x) _SB_GETVALUE(x,S_IO_SLEW1,M_IO_SLEW1) +#define M_IO_SLEW1 _SB_MAKEMASK(2, S_IO_SLEW1) +#define V_IO_SLEW1(x) _SB_MAKEVALUE(x, S_IO_SLEW1) +#define G_IO_SLEW1(x) _SB_GETVALUE(x, S_IO_SLEW1, M_IO_SLEW1) #define S_IO_DRV_G 10 -#define M_IO_DRV_G _SB_MAKEMASK(2,S_IO_DRV_G) -#define V_IO_DRV_G(x) _SB_MAKEVALUE(x,S_IO_DRV_G) -#define G_IO_DRV_G(x) _SB_GETVALUE(x,S_IO_DRV_G,M_IO_DRV_G) +#define M_IO_DRV_G _SB_MAKEMASK(2, S_IO_DRV_G) +#define V_IO_DRV_G(x) _SB_MAKEVALUE(x, S_IO_DRV_G) +#define G_IO_DRV_G(x) _SB_GETVALUE(x, S_IO_DRV_G, M_IO_DRV_G) #define S_IO_SLEW2 12 -#define M_IO_SLEW2 _SB_MAKEMASK(2,S_IO_SLEW2) -#define V_IO_SLEW2(x) _SB_MAKEVALUE(x,S_IO_SLEW2) -#define G_IO_SLEW2(x) _SB_GETVALUE(x,S_IO_SLEW2,M_IO_SLEW2) +#define M_IO_SLEW2 _SB_MAKEMASK(2, S_IO_SLEW2) +#define V_IO_SLEW2(x) _SB_MAKEVALUE(x, S_IO_SLEW2) +#define G_IO_SLEW2(x) _SB_GETVALUE(x, S_IO_SLEW2, M_IO_SLEW2) #define S_IO_DRV_H 14 -#define M_IO_DRV_H _SB_MAKEMASK(2,S_IO_DRV_H) -#define V_IO_DRV_H(x) _SB_MAKEVALUE(x,S_IO_DRV_H) -#define G_IO_DRV_H(x) _SB_GETVALUE(x,S_IO_DRV_H,M_IO_DRV_H) +#define M_IO_DRV_H _SB_MAKEMASK(2, S_IO_DRV_H) +#define V_IO_DRV_H(x) _SB_MAKEVALUE(x, S_IO_DRV_H) +#define G_IO_DRV_H(x) _SB_GETVALUE(x, S_IO_DRV_H, M_IO_DRV_H) /* * Generic Bus Output Drive Control Register 2 (Table 14-20) */ #define S_IO_DRV_J 2 -#define M_IO_DRV_J _SB_MAKEMASK(2,S_IO_DRV_J) -#define V_IO_DRV_J(x) _SB_MAKEVALUE(x,S_IO_DRV_J) -#define G_IO_DRV_J(x) _SB_GETVALUE(x,S_IO_DRV_J,M_IO_DRV_J) +#define M_IO_DRV_J _SB_MAKEMASK(2, S_IO_DRV_J) +#define V_IO_DRV_J(x) _SB_MAKEVALUE(x, S_IO_DRV_J) +#define G_IO_DRV_J(x) _SB_GETVALUE(x, S_IO_DRV_J, M_IO_DRV_J) #define S_IO_DRV_K 6 -#define M_IO_DRV_K _SB_MAKEMASK(2,S_IO_DRV_K) -#define V_IO_DRV_K(x) _SB_MAKEVALUE(x,S_IO_DRV_K) -#define G_IO_DRV_K(x) _SB_GETVALUE(x,S_IO_DRV_K,M_IO_DRV_K) +#define M_IO_DRV_K _SB_MAKEMASK(2, S_IO_DRV_K) +#define V_IO_DRV_K(x) _SB_MAKEVALUE(x, S_IO_DRV_K) +#define G_IO_DRV_K(x) _SB_GETVALUE(x, S_IO_DRV_K, M_IO_DRV_K) #define S_IO_DRV_L 10 -#define M_IO_DRV_L _SB_MAKEMASK(2,S_IO_DRV_L) -#define V_IO_DRV_L(x) _SB_MAKEVALUE(x,S_IO_DRV_L) -#define G_IO_DRV_L(x) _SB_GETVALUE(x,S_IO_DRV_L,M_IO_DRV_L) +#define M_IO_DRV_L _SB_MAKEMASK(2, S_IO_DRV_L) +#define V_IO_DRV_L(x) _SB_MAKEVALUE(x, S_IO_DRV_L) +#define G_IO_DRV_L(x) _SB_GETVALUE(x, S_IO_DRV_L, M_IO_DRV_L) #define S_IO_DRV_M 14 -#define M_IO_DRV_M _SB_MAKEMASK(2,S_IO_DRV_M) -#define V_IO_DRV_M(x) _SB_MAKEVALUE(x,S_IO_DRV_M) -#define G_IO_DRV_M(x) _SB_GETVALUE(x,S_IO_DRV_M,M_IO_DRV_M) +#define M_IO_DRV_M _SB_MAKEMASK(2, S_IO_DRV_M) +#define V_IO_DRV_M(x) _SB_MAKEVALUE(x, S_IO_DRV_M) +#define G_IO_DRV_M(x) _SB_GETVALUE(x, S_IO_DRV_M, M_IO_DRV_M) /* * Generic Bus Output Drive Control Register 3 (Table 14-21) */ #define S_IO_SLEW3 0 -#define M_IO_SLEW3 _SB_MAKEMASK(2,S_IO_SLEW3) -#define V_IO_SLEW3(x) _SB_MAKEVALUE(x,S_IO_SLEW3) -#define G_IO_SLEW3(x) _SB_GETVALUE(x,S_IO_SLEW3,M_IO_SLEW3) +#define M_IO_SLEW3 _SB_MAKEMASK(2, S_IO_SLEW3) +#define V_IO_SLEW3(x) _SB_MAKEVALUE(x, S_IO_SLEW3) +#define G_IO_SLEW3(x) _SB_GETVALUE(x, S_IO_SLEW3, M_IO_SLEW3) #define S_IO_DRV_N 2 -#define M_IO_DRV_N _SB_MAKEMASK(2,S_IO_DRV_N) -#define V_IO_DRV_N(x) _SB_MAKEVALUE(x,S_IO_DRV_N) -#define G_IO_DRV_N(x) _SB_GETVALUE(x,S_IO_DRV_N,M_IO_DRV_N) +#define M_IO_DRV_N _SB_MAKEMASK(2, S_IO_DRV_N) +#define V_IO_DRV_N(x) _SB_MAKEVALUE(x, S_IO_DRV_N) +#define G_IO_DRV_N(x) _SB_GETVALUE(x, S_IO_DRV_N, M_IO_DRV_N) #define S_IO_DRV_P 6 -#define M_IO_DRV_P _SB_MAKEMASK(2,S_IO_DRV_P) -#define V_IO_DRV_P(x) _SB_MAKEVALUE(x,S_IO_DRV_P) -#define G_IO_DRV_P(x) _SB_GETVALUE(x,S_IO_DRV_P,M_IO_DRV_P) +#define M_IO_DRV_P _SB_MAKEMASK(2, S_IO_DRV_P) +#define V_IO_DRV_P(x) _SB_MAKEVALUE(x, S_IO_DRV_P) +#define G_IO_DRV_P(x) _SB_GETVALUE(x, S_IO_DRV_P, M_IO_DRV_P) #define S_IO_DRV_Q 10 -#define M_IO_DRV_Q _SB_MAKEMASK(2,S_IO_DRV_Q) -#define V_IO_DRV_Q(x) _SB_MAKEVALUE(x,S_IO_DRV_Q) -#define G_IO_DRV_Q(x) _SB_GETVALUE(x,S_IO_DRV_Q,M_IO_DRV_Q) +#define M_IO_DRV_Q _SB_MAKEMASK(2, S_IO_DRV_Q) +#define V_IO_DRV_Q(x) _SB_MAKEVALUE(x, S_IO_DRV_Q) +#define G_IO_DRV_Q(x) _SB_GETVALUE(x, S_IO_DRV_Q, M_IO_DRV_Q) #define S_IO_DRV_R 14 -#define M_IO_DRV_R _SB_MAKEMASK(2,S_IO_DRV_R) -#define V_IO_DRV_R(x) _SB_MAKEVALUE(x,S_IO_DRV_R) -#define G_IO_DRV_R(x) _SB_GETVALUE(x,S_IO_DRV_R,M_IO_DRV_R) +#define M_IO_DRV_R _SB_MAKEMASK(2, S_IO_DRV_R) +#define V_IO_DRV_R(x) _SB_MAKEVALUE(x, S_IO_DRV_R) +#define G_IO_DRV_R(x) _SB_GETVALUE(x, S_IO_DRV_R, M_IO_DRV_R) /* @@ -329,9 +329,9 @@ #if SIBYTE_HDR_FEATURE_CHIP(1480) #define S_PCMCIA_MODE 16 -#define M_PCMCIA_MODE _SB_MAKEMASK(3,S_PCMCIA_MODE) -#define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x,S_PCMCIA_MODE) -#define G_PCMCIA_MODE(x) _SB_GETVALUE(x,S_PCMCIA_MODE,M_PCMCIA_MODE) +#define M_PCMCIA_MODE _SB_MAKEMASK(3, S_PCMCIA_MODE) +#define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x, S_PCMCIA_MODE) +#define G_PCMCIA_MODE(x) _SB_GETVALUE(x, S_PCMCIA_MODE, M_PCMCIA_MODE) #define K_PCMCIA_MODE_PCMA_NOB 0 /* standard PCMCIA "A", no "B" */ #define K_PCMCIA_MODE_IDEA_NOB 1 /* IDE "A", no "B" */ @@ -369,49 +369,49 @@ #define K_GPIO_INTR_SPLIT 3 #define S_GPIO_INTR_TYPEX(n) (((n)/2)*2) -#define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_TYPEX(n)) -#define V_GPIO_INTR_TYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPEX(n)) -#define G_GPIO_INTR_TYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_TYPEX(n),M_GPIO_INTR_TYPEX(n)) +#define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_TYPEX(n)) +#define V_GPIO_INTR_TYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPEX(n)) +#define G_GPIO_INTR_TYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_TYPEX(n), M_GPIO_INTR_TYPEX(n)) #define S_GPIO_INTR_TYPE0 0 -#define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE0) -#define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE0) -#define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE0,M_GPIO_INTR_TYPE0) +#define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE0) +#define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE0) +#define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE0, M_GPIO_INTR_TYPE0) #define S_GPIO_INTR_TYPE2 2 -#define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE2) -#define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE2) -#define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE2,M_GPIO_INTR_TYPE2) +#define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE2) +#define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE2) +#define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE2, M_GPIO_INTR_TYPE2) #define S_GPIO_INTR_TYPE4 4 -#define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE4) -#define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE4) -#define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE4,M_GPIO_INTR_TYPE4) +#define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE4) +#define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE4) +#define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE4, M_GPIO_INTR_TYPE4) #define S_GPIO_INTR_TYPE6 6 -#define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE6) -#define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE6) -#define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE6,M_GPIO_INTR_TYPE6) +#define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE6) +#define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE6) +#define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE6, M_GPIO_INTR_TYPE6) #define S_GPIO_INTR_TYPE8 8 -#define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE8) -#define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE8) -#define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE8,M_GPIO_INTR_TYPE8) +#define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE8) +#define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE8) +#define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE8, M_GPIO_INTR_TYPE8) #define S_GPIO_INTR_TYPE10 10 -#define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE10) -#define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE10) -#define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE10,M_GPIO_INTR_TYPE10) +#define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE10) +#define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE10) +#define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE10, M_GPIO_INTR_TYPE10) #define S_GPIO_INTR_TYPE12 12 -#define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE12) -#define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE12) -#define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE12,M_GPIO_INTR_TYPE12) +#define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE12) +#define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE12) +#define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE12, M_GPIO_INTR_TYPE12) #define S_GPIO_INTR_TYPE14 14 -#define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE14) -#define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14) -#define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14) +#define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE14) +#define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE14) +#define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE14, M_GPIO_INTR_TYPE14) #if SIBYTE_HDR_FEATURE_CHIP(1480) @@ -425,49 +425,49 @@ #define K_GPIO_INTR_UNPRED2 3 #define S_GPIO_INTR_ATYPEX(n) (((n)/2)*2) -#define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_ATYPEX(n)) -#define V_GPIO_INTR_ATYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPEX(n)) -#define G_GPIO_INTR_ATYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPEX(n),M_GPIO_INTR_ATYPEX(n)) +#define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_ATYPEX(n)) +#define V_GPIO_INTR_ATYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPEX(n)) +#define G_GPIO_INTR_ATYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPEX(n), M_GPIO_INTR_ATYPEX(n)) #define S_GPIO_INTR_ATYPE0 0 -#define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE0) -#define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE0) -#define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE0,M_GPIO_INTR_ATYPE0) +#define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE0) +#define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE0) +#define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE0, M_GPIO_INTR_ATYPE0) #define S_GPIO_INTR_ATYPE2 2 -#define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE2) -#define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE2) -#define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE2,M_GPIO_INTR_ATYPE2) +#define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE2) +#define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE2) +#define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE2, M_GPIO_INTR_ATYPE2) #define S_GPIO_INTR_ATYPE4 4 -#define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE4) -#define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE4) -#define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE4,M_GPIO_INTR_ATYPE4) +#define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE4) +#define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE4) +#define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE4, M_GPIO_INTR_ATYPE4) #define S_GPIO_INTR_ATYPE6 6 -#define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE6) -#define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE6) -#define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE6,M_GPIO_INTR_ATYPE6) +#define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE6) +#define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE6) +#define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE6, M_GPIO_INTR_ATYPE6) #define S_GPIO_INTR_ATYPE8 8 -#define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE8) -#define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE8) -#define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE8,M_GPIO_INTR_ATYPE8) +#define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE8) +#define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE8) +#define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE8, M_GPIO_INTR_ATYPE8) #define S_GPIO_INTR_ATYPE10 10 -#define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE10) -#define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE10) -#define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE10,M_GPIO_INTR_ATYPE10) +#define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE10) +#define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE10) +#define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE10, M_GPIO_INTR_ATYPE10) #define S_GPIO_INTR_ATYPE12 12 -#define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE12) -#define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE12) -#define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE12,M_GPIO_INTR_ATYPE12) +#define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE12) +#define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE12) +#define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE12, M_GPIO_INTR_ATYPE12) #define S_GPIO_INTR_ATYPE14 14 -#define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE14) -#define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE14) -#define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE14,M_GPIO_INTR_ATYPE14) +#define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE14) +#define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE14) +#define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE14, M_GPIO_INTR_ATYPE14) #endif diff --git a/include/asm-mips/sibyte/sb1250_int.h b/include/asm-mips/sibyte/sb1250_int.h index 94e8299b0a2a..f2850b4bcfd4 100644 --- a/include/asm-mips/sibyte/sb1250_int.h +++ b/include/asm-mips/sibyte/sb1250_int.h @@ -10,7 +10,7 @@ * ********************************************************************* * - * Copyright 2000,2001,2002,2003 + * Copyright 2000, 2001, 2002, 2003 * Broadcom Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or @@ -150,7 +150,7 @@ #define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1) #define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2) #define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3) -#define M_INT_MBOX_ALL _SB_MAKEMASK(4,K_INT_MBOX_0) +#define M_INT_MBOX_ALL _SB_MAKEMASK(4, K_INT_MBOX_0) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) #define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT) #define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT) @@ -208,9 +208,9 @@ */ #define S_INT_LDT_INTMSG 0 -#define M_INT_LDT_INTMSG _SB_MAKEMASK(3,S_INT_LDT_INTMSG) -#define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x,S_INT_LDT_INTMSG) -#define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x,S_INT_LDT_INTMSG,M_INT_LDT_INTMSG) +#define M_INT_LDT_INTMSG _SB_MAKEMASK(3, S_INT_LDT_INTMSG) +#define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x, S_INT_LDT_INTMSG) +#define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x, S_INT_LDT_INTMSG, M_INT_LDT_INTMSG) #define K_INT_LDT_INTMSG_FIXED 0 #define K_INT_LDT_INTMSG_ARBITRATED 1 @@ -228,14 +228,14 @@ #define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4) #define S_INT_LDT_INTDEST 5 -#define M_INT_LDT_INTDEST _SB_MAKEMASK(10,S_INT_LDT_INTDEST) -#define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x,S_INT_LDT_INTDEST) -#define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x,S_INT_LDT_INTDEST,M_INT_LDT_INTDEST) +#define M_INT_LDT_INTDEST _SB_MAKEMASK(10, S_INT_LDT_INTDEST) +#define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x, S_INT_LDT_INTDEST) +#define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x, S_INT_LDT_INTDEST, M_INT_LDT_INTDEST) #define S_INT_LDT_VECTOR 13 -#define M_INT_LDT_VECTOR _SB_MAKEMASK(8,S_INT_LDT_VECTOR) -#define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x,S_INT_LDT_VECTOR) -#define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x,S_INT_LDT_VECTOR,M_INT_LDT_VECTOR) +#define M_INT_LDT_VECTOR _SB_MAKEMASK(8, S_INT_LDT_VECTOR) +#define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x, S_INT_LDT_VECTOR) +#define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x, S_INT_LDT_VECTOR, M_INT_LDT_VECTOR) /* * Vector format (Table 4-6) diff --git a/include/asm-mips/sibyte/sb1250_l2c.h b/include/asm-mips/sibyte/sb1250_l2c.h index 842f205094af..6554dcf05cfe 100644 --- a/include/asm-mips/sibyte/sb1250_l2c.h +++ b/include/asm-mips/sibyte/sb1250_l2c.h @@ -40,27 +40,27 @@ */ #define S_L2C_TAG_MBZ 0 -#define M_L2C_TAG_MBZ _SB_MAKEMASK(5,S_L2C_TAG_MBZ) +#define M_L2C_TAG_MBZ _SB_MAKEMASK(5, S_L2C_TAG_MBZ) #define S_L2C_TAG_INDEX 5 -#define M_L2C_TAG_INDEX _SB_MAKEMASK(12,S_L2C_TAG_INDEX) -#define V_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x,S_L2C_TAG_INDEX) -#define G_L2C_TAG_INDEX(x) _SB_GETVALUE(x,S_L2C_TAG_INDEX,M_L2C_TAG_INDEX) +#define M_L2C_TAG_INDEX _SB_MAKEMASK(12, S_L2C_TAG_INDEX) +#define V_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x, S_L2C_TAG_INDEX) +#define G_L2C_TAG_INDEX(x) _SB_GETVALUE(x, S_L2C_TAG_INDEX, M_L2C_TAG_INDEX) #define S_L2C_TAG_TAG 17 -#define M_L2C_TAG_TAG _SB_MAKEMASK(23,S_L2C_TAG_TAG) -#define V_L2C_TAG_TAG(x) _SB_MAKEVALUE(x,S_L2C_TAG_TAG) -#define G_L2C_TAG_TAG(x) _SB_GETVALUE(x,S_L2C_TAG_TAG,M_L2C_TAG_TAG) +#define M_L2C_TAG_TAG _SB_MAKEMASK(23, S_L2C_TAG_TAG) +#define V_L2C_TAG_TAG(x) _SB_MAKEVALUE(x, S_L2C_TAG_TAG) +#define G_L2C_TAG_TAG(x) _SB_GETVALUE(x, S_L2C_TAG_TAG, M_L2C_TAG_TAG) #define S_L2C_TAG_ECC 40 -#define M_L2C_TAG_ECC _SB_MAKEMASK(6,S_L2C_TAG_ECC) -#define V_L2C_TAG_ECC(x) _SB_MAKEVALUE(x,S_L2C_TAG_ECC) -#define G_L2C_TAG_ECC(x) _SB_GETVALUE(x,S_L2C_TAG_ECC,M_L2C_TAG_ECC) +#define M_L2C_TAG_ECC _SB_MAKEMASK(6, S_L2C_TAG_ECC) +#define V_L2C_TAG_ECC(x) _SB_MAKEVALUE(x, S_L2C_TAG_ECC) +#define G_L2C_TAG_ECC(x) _SB_GETVALUE(x, S_L2C_TAG_ECC, M_L2C_TAG_ECC) #define S_L2C_TAG_WAY 46 -#define M_L2C_TAG_WAY _SB_MAKEMASK(2,S_L2C_TAG_WAY) -#define V_L2C_TAG_WAY(x) _SB_MAKEVALUE(x,S_L2C_TAG_WAY) -#define G_L2C_TAG_WAY(x) _SB_GETVALUE(x,S_L2C_TAG_WAY,M_L2C_TAG_WAY) +#define M_L2C_TAG_WAY _SB_MAKEMASK(2, S_L2C_TAG_WAY) +#define V_L2C_TAG_WAY(x) _SB_MAKEVALUE(x, S_L2C_TAG_WAY) +#define G_L2C_TAG_WAY(x) _SB_GETVALUE(x, S_L2C_TAG_WAY, M_L2C_TAG_WAY) #define M_L2C_TAG_DIRTY _SB_MAKEMASK1(48) #define M_L2C_TAG_VALID _SB_MAKEMASK1(49) @@ -70,32 +70,32 @@ */ #define S_L2C_MGMT_INDEX 5 -#define M_L2C_MGMT_INDEX _SB_MAKEMASK(12,S_L2C_MGMT_INDEX) -#define V_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x,S_L2C_MGMT_INDEX) -#define G_L2C_MGMT_INDEX(x) _SB_GETVALUE(x,S_L2C_MGMT_INDEX,M_L2C_MGMT_INDEX) +#define M_L2C_MGMT_INDEX _SB_MAKEMASK(12, S_L2C_MGMT_INDEX) +#define V_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x, S_L2C_MGMT_INDEX) +#define G_L2C_MGMT_INDEX(x) _SB_GETVALUE(x, S_L2C_MGMT_INDEX, M_L2C_MGMT_INDEX) #define S_L2C_MGMT_QUADRANT 15 -#define M_L2C_MGMT_QUADRANT _SB_MAKEMASK(2,S_L2C_MGMT_QUADRANT) -#define V_L2C_MGMT_QUADRANT(x) _SB_MAKEVALUE(x,S_L2C_MGMT_QUADRANT) -#define G_L2C_MGMT_QUADRANT(x) _SB_GETVALUE(x,S_L2C_MGMT_QUADRANT,M_L2C_MGMT_QUADRANT) +#define M_L2C_MGMT_QUADRANT _SB_MAKEMASK(2, S_L2C_MGMT_QUADRANT) +#define V_L2C_MGMT_QUADRANT(x) _SB_MAKEVALUE(x, S_L2C_MGMT_QUADRANT) +#define G_L2C_MGMT_QUADRANT(x) _SB_GETVALUE(x, S_L2C_MGMT_QUADRANT, M_L2C_MGMT_QUADRANT) #define S_L2C_MGMT_HALF 16 -#define M_L2C_MGMT_HALF _SB_MAKEMASK(1,S_L2C_MGMT_HALF) +#define M_L2C_MGMT_HALF _SB_MAKEMASK(1, S_L2C_MGMT_HALF) #define S_L2C_MGMT_WAY 17 -#define M_L2C_MGMT_WAY _SB_MAKEMASK(2,S_L2C_MGMT_WAY) -#define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x,S_L2C_MGMT_WAY) -#define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x,S_L2C_MGMT_WAY,M_L2C_MGMT_WAY) +#define M_L2C_MGMT_WAY _SB_MAKEMASK(2, S_L2C_MGMT_WAY) +#define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x, S_L2C_MGMT_WAY) +#define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x, S_L2C_MGMT_WAY, M_L2C_MGMT_WAY) #define S_L2C_MGMT_ECC_DIAG 21 -#define M_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2,S_L2C_MGMT_ECC_DIAG) -#define V_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x,S_L2C_MGMT_ECC_DIAG) -#define G_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x,S_L2C_MGMT_ECC_DIAG,M_L2C_MGMT_ECC_DIAG) +#define M_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2, S_L2C_MGMT_ECC_DIAG) +#define V_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x, S_L2C_MGMT_ECC_DIAG) +#define G_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x, S_L2C_MGMT_ECC_DIAG, M_L2C_MGMT_ECC_DIAG) #define S_L2C_MGMT_TAG 23 -#define M_L2C_MGMT_TAG _SB_MAKEMASK(4,S_L2C_MGMT_TAG) -#define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x,S_L2C_MGMT_TAG) -#define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x,S_L2C_MGMT_TAG,M_L2C_MGMT_TAG) +#define M_L2C_MGMT_TAG _SB_MAKEMASK(4, S_L2C_MGMT_TAG) +#define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x, S_L2C_MGMT_TAG) +#define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x, S_L2C_MGMT_TAG, M_L2C_MGMT_TAG) #define M_L2C_MGMT_DIRTY _SB_MAKEMASK1(19) #define M_L2C_MGMT_VALID _SB_MAKEMASK1(20) @@ -111,9 +111,9 @@ * L2 Read Misc. register (A_L2_READ_MISC) */ #define S_L2C_MISC_NO_WAY 10 -#define M_L2C_MISC_NO_WAY _SB_MAKEMASK(4,S_L2C_MISC_NO_WAY) -#define V_L2C_MISC_NO_WAY(x) _SB_MAKEVALUE(x,S_L2C_MISC_NO_WAY) -#define G_L2C_MISC_NO_WAY(x) _SB_GETVALUE(x,S_L2C_MISC_NO_WAY,M_L2C_MISC_NO_WAY) +#define M_L2C_MISC_NO_WAY _SB_MAKEMASK(4, S_L2C_MISC_NO_WAY) +#define V_L2C_MISC_NO_WAY(x) _SB_MAKEVALUE(x, S_L2C_MISC_NO_WAY) +#define G_L2C_MISC_NO_WAY(x) _SB_GETVALUE(x, S_L2C_MISC_NO_WAY, M_L2C_MISC_NO_WAY) #define M_L2C_MISC_ECC_CLEANUP_DIS _SB_MAKEMASK1(9) #define M_L2C_MISC_MC_PRIO_LOW _SB_MAKEMASK1(8) diff --git a/include/asm-mips/sibyte/sb1250_ldt.h b/include/asm-mips/sibyte/sb1250_ldt.h index 7092535d1108..081e8b1c4ad0 100644 --- a/include/asm-mips/sibyte/sb1250_ldt.h +++ b/include/asm-mips/sibyte/sb1250_ldt.h @@ -10,7 +10,7 @@ * ********************************************************************* * - * Copyright 2000,2001,2002,2003 + * Copyright 2000, 2001, 2002, 2003 * Broadcom Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or @@ -81,14 +81,14 @@ */ #define S_LDT_DEVICEID_VENDOR 0 -#define M_LDT_DEVICEID_VENDOR _SB_MAKEMASK_32(16,S_LDT_DEVICEID_VENDOR) -#define V_LDT_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x,S_LDT_DEVICEID_VENDOR) -#define G_LDT_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x,S_LDT_DEVICEID_VENDOR,M_LDT_DEVICEID_VENDOR) +#define M_LDT_DEVICEID_VENDOR _SB_MAKEMASK_32(16, S_LDT_DEVICEID_VENDOR) +#define V_LDT_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_VENDOR) +#define G_LDT_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_VENDOR, M_LDT_DEVICEID_VENDOR) #define S_LDT_DEVICEID_DEVICEID 16 -#define M_LDT_DEVICEID_DEVICEID _SB_MAKEMASK_32(16,S_LDT_DEVICEID_DEVICEID) -#define V_LDT_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x,S_LDT_DEVICEID_DEVICEID) -#define G_LDT_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x,S_LDT_DEVICEID_DEVICEID,M_LDT_DEVICEID_DEVICEID) +#define M_LDT_DEVICEID_DEVICEID _SB_MAKEMASK_32(16, S_LDT_DEVICEID_DEVICEID) +#define V_LDT_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_DEVICEID) +#define G_LDT_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_DEVICEID, M_LDT_DEVICEID_DEVICEID) /* @@ -111,14 +111,14 @@ */ #define S_LDT_CLASSREV_REV 0 -#define M_LDT_CLASSREV_REV _SB_MAKEMASK_32(8,S_LDT_CLASSREV_REV) -#define V_LDT_CLASSREV_REV(x) _SB_MAKEVALUE_32(x,S_LDT_CLASSREV_REV) -#define G_LDT_CLASSREV_REV(x) _SB_GETVALUE_32(x,S_LDT_CLASSREV_REV,M_LDT_CLASSREV_REV) +#define M_LDT_CLASSREV_REV _SB_MAKEMASK_32(8, S_LDT_CLASSREV_REV) +#define V_LDT_CLASSREV_REV(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_REV) +#define G_LDT_CLASSREV_REV(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_REV, M_LDT_CLASSREV_REV) #define S_LDT_CLASSREV_CLASS 8 -#define M_LDT_CLASSREV_CLASS _SB_MAKEMASK_32(24,S_LDT_CLASSREV_CLASS) -#define V_LDT_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x,S_LDT_CLASSREV_CLASS) -#define G_LDT_CLASSREV_CLASS(x) _SB_GETVALUE_32(x,S_LDT_CLASSREV_CLASS,M_LDT_CLASSREV_CLASS) +#define M_LDT_CLASSREV_CLASS _SB_MAKEMASK_32(24, S_LDT_CLASSREV_CLASS) +#define V_LDT_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_CLASS) +#define G_LDT_CLASSREV_CLASS(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_CLASS, M_LDT_CLASSREV_CLASS) #define K_LDT_REV 0x01 #define K_LDT_CLASS 0x060000 @@ -128,26 +128,26 @@ */ #define S_LDT_DEVHDR_CLINESZ 0 -#define M_LDT_DEVHDR_CLINESZ _SB_MAKEMASK_32(8,S_LDT_DEVHDR_CLINESZ) -#define V_LDT_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_CLINESZ) -#define G_LDT_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_CLINESZ,M_LDT_DEVHDR_CLINESZ) +#define M_LDT_DEVHDR_CLINESZ _SB_MAKEMASK_32(8, S_LDT_DEVHDR_CLINESZ) +#define V_LDT_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_CLINESZ) +#define G_LDT_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_CLINESZ, M_LDT_DEVHDR_CLINESZ) #define S_LDT_DEVHDR_LATTMR 8 -#define M_LDT_DEVHDR_LATTMR _SB_MAKEMASK_32(8,S_LDT_DEVHDR_LATTMR) -#define V_LDT_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_LATTMR) -#define G_LDT_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_LATTMR,M_LDT_DEVHDR_LATTMR) +#define M_LDT_DEVHDR_LATTMR _SB_MAKEMASK_32(8, S_LDT_DEVHDR_LATTMR) +#define V_LDT_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_LATTMR) +#define G_LDT_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_LATTMR, M_LDT_DEVHDR_LATTMR) #define S_LDT_DEVHDR_HDRTYPE 16 -#define M_LDT_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8,S_LDT_DEVHDR_HDRTYPE) -#define V_LDT_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_HDRTYPE) -#define G_LDT_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_HDRTYPE,M_LDT_DEVHDR_HDRTYPE) +#define M_LDT_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8, S_LDT_DEVHDR_HDRTYPE) +#define V_LDT_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_HDRTYPE) +#define G_LDT_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_HDRTYPE, M_LDT_DEVHDR_HDRTYPE) #define K_LDT_DEVHDR_HDRTYPE_TYPE1 1 #define S_LDT_DEVHDR_BIST 24 -#define M_LDT_DEVHDR_BIST _SB_MAKEMASK_32(8,S_LDT_DEVHDR_BIST) -#define V_LDT_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_BIST) -#define G_LDT_DEVHDR_BIST(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_BIST,M_LDT_DEVHDR_BIST) +#define M_LDT_DEVHDR_BIST _SB_MAKEMASK_32(8, S_LDT_DEVHDR_BIST) +#define V_LDT_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_BIST) +#define G_LDT_DEVHDR_BIST(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_BIST, M_LDT_DEVHDR_BIST) @@ -170,9 +170,9 @@ #define M_LDT_STATUS_MSTRDPARERR _SB_MAKEMASK1_32(24) #define S_LDT_STATUS_DEVSELTIMING 25 -#define M_LDT_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2,S_LDT_STATUS_DEVSELTIMING) -#define V_LDT_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x,S_LDT_STATUS_DEVSELTIMING) -#define G_LDT_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x,S_LDT_STATUS_DEVSELTIMING,M_LDT_STATUS_DEVSELTIMING) +#define M_LDT_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2, S_LDT_STATUS_DEVSELTIMING) +#define V_LDT_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x, S_LDT_STATUS_DEVSELTIMING) +#define G_LDT_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x, S_LDT_STATUS_DEVSELTIMING, M_LDT_STATUS_DEVSELTIMING) #define M_LDT_STATUS_SIGDTGTABORT _SB_MAKEMASK1_32(27) #define M_LDT_STATUS_RCVDTGTABORT _SB_MAKEMASK1_32(28) @@ -208,9 +208,9 @@ #define M_LDT_CMD_DOUBLEENDED _SB_MAKEMASK1_32(17) #define S_LDT_CMD_CAPTYPE 29 -#define M_LDT_CMD_CAPTYPE _SB_MAKEMASK_32(3,S_LDT_CMD_CAPTYPE) -#define V_LDT_CMD_CAPTYPE(x) _SB_MAKEVALUE_32(x,S_LDT_CMD_CAPTYPE) -#define G_LDT_CMD_CAPTYPE(x) _SB_GETVALUE_32(x,S_LDT_CMD_CAPTYPE,M_LDT_CMD_CAPTYPE) +#define M_LDT_CMD_CAPTYPE _SB_MAKEMASK_32(3, S_LDT_CMD_CAPTYPE) +#define V_LDT_CMD_CAPTYPE(x) _SB_MAKEVALUE_32(x, S_LDT_CMD_CAPTYPE) +#define G_LDT_CMD_CAPTYPE(x) _SB_GETVALUE_32(x, S_LDT_CMD_CAPTYPE, M_LDT_CMD_CAPTYPE) /* * LDT link control register (Table 8-18), and (Table 8-19) @@ -225,35 +225,35 @@ #define M_LDT_LINKCTRL_XMITOFF _SB_MAKEMASK1_32(7) #define S_LDT_LINKCTRL_CRCERR 8 -#define M_LDT_LINKCTRL_CRCERR _SB_MAKEMASK_32(4,S_LDT_LINKCTRL_CRCERR) -#define V_LDT_LINKCTRL_CRCERR(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_CRCERR) -#define G_LDT_LINKCTRL_CRCERR(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_CRCERR,M_LDT_LINKCTRL_CRCERR) +#define M_LDT_LINKCTRL_CRCERR _SB_MAKEMASK_32(4, S_LDT_LINKCTRL_CRCERR) +#define V_LDT_LINKCTRL_CRCERR(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_CRCERR) +#define G_LDT_LINKCTRL_CRCERR(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_CRCERR, M_LDT_LINKCTRL_CRCERR) #define S_LDT_LINKCTRL_MAXIN 16 -#define M_LDT_LINKCTRL_MAXIN _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_MAXIN) -#define V_LDT_LINKCTRL_MAXIN(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_MAXIN) -#define G_LDT_LINKCTRL_MAXIN(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_MAXIN,M_LDT_LINKCTRL_MAXIN) +#define M_LDT_LINKCTRL_MAXIN _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXIN) +#define V_LDT_LINKCTRL_MAXIN(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXIN) +#define G_LDT_LINKCTRL_MAXIN(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXIN, M_LDT_LINKCTRL_MAXIN) #define M_LDT_LINKCTRL_DWFCLN _SB_MAKEMASK1_32(19) #define S_LDT_LINKCTRL_MAXOUT 20 -#define M_LDT_LINKCTRL_MAXOUT _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_MAXOUT) -#define V_LDT_LINKCTRL_MAXOUT(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_MAXOUT) -#define G_LDT_LINKCTRL_MAXOUT(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_MAXOUT,M_LDT_LINKCTRL_MAXOUT) +#define M_LDT_LINKCTRL_MAXOUT _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXOUT) +#define V_LDT_LINKCTRL_MAXOUT(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXOUT) +#define G_LDT_LINKCTRL_MAXOUT(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXOUT, M_LDT_LINKCTRL_MAXOUT) #define M_LDT_LINKCTRL_DWFCOUT _SB_MAKEMASK1_32(23) #define S_LDT_LINKCTRL_WIDTHIN 24 -#define M_LDT_LINKCTRL_WIDTHIN _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_WIDTHIN) -#define V_LDT_LINKCTRL_WIDTHIN(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_WIDTHIN) -#define G_LDT_LINKCTRL_WIDTHIN(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_WIDTHIN,M_LDT_LINKCTRL_WIDTHIN) +#define M_LDT_LINKCTRL_WIDTHIN _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHIN) +#define V_LDT_LINKCTRL_WIDTHIN(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN) +#define G_LDT_LINKCTRL_WIDTHIN(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN, M_LDT_LINKCTRL_WIDTHIN) #define M_LDT_LINKCTRL_DWFCLIN_EN _SB_MAKEMASK1_32(27) #define S_LDT_LINKCTRL_WIDTHOUT 28 -#define M_LDT_LINKCTRL_WIDTHOUT _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_WIDTHOUT) -#define V_LDT_LINKCTRL_WIDTHOUT(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_WIDTHOUT) -#define G_LDT_LINKCTRL_WIDTHOUT(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_WIDTHOUT,M_LDT_LINKCTRL_WIDTHOUT) +#define M_LDT_LINKCTRL_WIDTHOUT _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHOUT) +#define V_LDT_LINKCTRL_WIDTHOUT(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT) +#define G_LDT_LINKCTRL_WIDTHOUT(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT, M_LDT_LINKCTRL_WIDTHOUT) #define M_LDT_LINKCTRL_DWFCOUT_EN _SB_MAKEMASK1_32(31) @@ -262,9 +262,9 @@ */ #define S_LDT_LINKFREQ_FREQ 8 -#define M_LDT_LINKFREQ_FREQ _SB_MAKEMASK_32(4,S_LDT_LINKFREQ_FREQ) -#define V_LDT_LINKFREQ_FREQ(x) _SB_MAKEVALUE_32(x,S_LDT_LINKFREQ_FREQ) -#define G_LDT_LINKFREQ_FREQ(x) _SB_GETVALUE_32(x,S_LDT_LINKFREQ_FREQ,M_LDT_LINKFREQ_FREQ) +#define M_LDT_LINKFREQ_FREQ _SB_MAKEMASK_32(4, S_LDT_LINKFREQ_FREQ) +#define V_LDT_LINKFREQ_FREQ(x) _SB_MAKEVALUE_32(x, S_LDT_LINKFREQ_FREQ) +#define G_LDT_LINKFREQ_FREQ(x) _SB_GETVALUE_32(x, S_LDT_LINKFREQ_FREQ, M_LDT_LINKFREQ_FREQ) #define K_LDT_LINKFREQ_200MHZ 0 #define K_LDT_LINKFREQ_300MHZ 1 @@ -293,16 +293,16 @@ #define S_LDT_SRICMD_RXMARGIN 20 -#define M_LDT_SRICMD_RXMARGIN _SB_MAKEMASK_32(5,S_LDT_SRICMD_RXMARGIN) -#define V_LDT_SRICMD_RXMARGIN(x) _SB_MAKEVALUE_32(x,S_LDT_SRICMD_RXMARGIN) -#define G_LDT_SRICMD_RXMARGIN(x) _SB_GETVALUE_32(x,S_LDT_SRICMD_RXMARGIN,M_LDT_SRICMD_RXMARGIN) +#define M_LDT_SRICMD_RXMARGIN _SB_MAKEMASK_32(5, S_LDT_SRICMD_RXMARGIN) +#define V_LDT_SRICMD_RXMARGIN(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_RXMARGIN) +#define G_LDT_SRICMD_RXMARGIN(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_RXMARGIN, M_LDT_SRICMD_RXMARGIN) #define M_LDT_SRICMD_LDTPLLCOMPAT _SB_MAKEMASK1_32(25) #define S_LDT_SRICMD_TXINITIALOFFSET 28 -#define M_LDT_SRICMD_TXINITIALOFFSET _SB_MAKEMASK_32(3,S_LDT_SRICMD_TXINITIALOFFSET) -#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x,S_LDT_SRICMD_TXINITIALOFFSET) -#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x,S_LDT_SRICMD_TXINITIALOFFSET,M_LDT_SRICMD_TXINITIALOFFSET) +#define M_LDT_SRICMD_TXINITIALOFFSET _SB_MAKEMASK_32(3, S_LDT_SRICMD_TXINITIALOFFSET) +#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET) +#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET, M_LDT_SRICMD_TXINITIALOFFSET) #define M_LDT_SRICMD_LINKFREQDIRECT _SB_MAKEMASK1_32(31) @@ -340,73 +340,73 @@ */ #define S_LDT_SRICTRL_NEEDRESP 0 -#define M_LDT_SRICTRL_NEEDRESP _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDRESP) -#define V_LDT_SRICTRL_NEEDRESP(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDRESP) -#define G_LDT_SRICTRL_NEEDRESP(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDRESP,M_LDT_SRICTRL_NEEDRESP) +#define M_LDT_SRICTRL_NEEDRESP _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDRESP) +#define V_LDT_SRICTRL_NEEDRESP(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDRESP) +#define G_LDT_SRICTRL_NEEDRESP(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDRESP, M_LDT_SRICTRL_NEEDRESP) #define S_LDT_SRICTRL_NEEDNPREQ 2 -#define M_LDT_SRICTRL_NEEDNPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDNPREQ) -#define V_LDT_SRICTRL_NEEDNPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDNPREQ) -#define G_LDT_SRICTRL_NEEDNPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDNPREQ,M_LDT_SRICTRL_NEEDNPREQ) +#define M_LDT_SRICTRL_NEEDNPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDNPREQ) +#define V_LDT_SRICTRL_NEEDNPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ) +#define G_LDT_SRICTRL_NEEDNPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ, M_LDT_SRICTRL_NEEDNPREQ) #define S_LDT_SRICTRL_NEEDPREQ 4 -#define M_LDT_SRICTRL_NEEDPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDPREQ) -#define V_LDT_SRICTRL_NEEDPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDPREQ) -#define G_LDT_SRICTRL_NEEDPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDPREQ,M_LDT_SRICTRL_NEEDPREQ) +#define M_LDT_SRICTRL_NEEDPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDPREQ) +#define V_LDT_SRICTRL_NEEDPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ) +#define G_LDT_SRICTRL_NEEDPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ, M_LDT_SRICTRL_NEEDPREQ) #define S_LDT_SRICTRL_WANTRESP 8 -#define M_LDT_SRICTRL_WANTRESP _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTRESP) -#define V_LDT_SRICTRL_WANTRESP(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTRESP) -#define G_LDT_SRICTRL_WANTRESP(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTRESP,M_LDT_SRICTRL_WANTRESP) +#define M_LDT_SRICTRL_WANTRESP _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTRESP) +#define V_LDT_SRICTRL_WANTRESP(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTRESP) +#define G_LDT_SRICTRL_WANTRESP(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTRESP, M_LDT_SRICTRL_WANTRESP) #define S_LDT_SRICTRL_WANTNPREQ 10 -#define M_LDT_SRICTRL_WANTNPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTNPREQ) -#define V_LDT_SRICTRL_WANTNPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTNPREQ) -#define G_LDT_SRICTRL_WANTNPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTNPREQ,M_LDT_SRICTRL_WANTNPREQ) +#define M_LDT_SRICTRL_WANTNPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTNPREQ) +#define V_LDT_SRICTRL_WANTNPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ) +#define G_LDT_SRICTRL_WANTNPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ, M_LDT_SRICTRL_WANTNPREQ) #define S_LDT_SRICTRL_WANTPREQ 12 -#define M_LDT_SRICTRL_WANTPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTPREQ) -#define V_LDT_SRICTRL_WANTPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTPREQ) -#define G_LDT_SRICTRL_WANTPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTPREQ,M_LDT_SRICTRL_WANTPREQ) +#define M_LDT_SRICTRL_WANTPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTPREQ) +#define V_LDT_SRICTRL_WANTPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTPREQ) +#define G_LDT_SRICTRL_WANTPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTPREQ, M_LDT_SRICTRL_WANTPREQ) #define S_LDT_SRICTRL_BUFRELSPACE 16 -#define M_LDT_SRICTRL_BUFRELSPACE _SB_MAKEMASK_32(4,S_LDT_SRICTRL_BUFRELSPACE) -#define V_LDT_SRICTRL_BUFRELSPACE(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_BUFRELSPACE) -#define G_LDT_SRICTRL_BUFRELSPACE(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_BUFRELSPACE,M_LDT_SRICTRL_BUFRELSPACE) +#define M_LDT_SRICTRL_BUFRELSPACE _SB_MAKEMASK_32(4, S_LDT_SRICTRL_BUFRELSPACE) +#define V_LDT_SRICTRL_BUFRELSPACE(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE) +#define G_LDT_SRICTRL_BUFRELSPACE(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE, M_LDT_SRICTRL_BUFRELSPACE) /* * LDT SRI Transmit Buffer Count register (Table 8-26) */ #define S_LDT_TXBUFCNT_PCMD 0 -#define M_LDT_TXBUFCNT_PCMD _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_PCMD) -#define V_LDT_TXBUFCNT_PCMD(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_PCMD) -#define G_LDT_TXBUFCNT_PCMD(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_PCMD,M_LDT_TXBUFCNT_PCMD) +#define M_LDT_TXBUFCNT_PCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PCMD) +#define V_LDT_TXBUFCNT_PCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PCMD) +#define G_LDT_TXBUFCNT_PCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PCMD, M_LDT_TXBUFCNT_PCMD) #define S_LDT_TXBUFCNT_PDATA 4 -#define M_LDT_TXBUFCNT_PDATA _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_PDATA) -#define V_LDT_TXBUFCNT_PDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_PDATA) -#define G_LDT_TXBUFCNT_PDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_PDATA,M_LDT_TXBUFCNT_PDATA) +#define M_LDT_TXBUFCNT_PDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PDATA) +#define V_LDT_TXBUFCNT_PDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PDATA) +#define G_LDT_TXBUFCNT_PDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PDATA, M_LDT_TXBUFCNT_PDATA) #define S_LDT_TXBUFCNT_NPCMD 8 -#define M_LDT_TXBUFCNT_NPCMD _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_NPCMD) -#define V_LDT_TXBUFCNT_NPCMD(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_NPCMD) -#define G_LDT_TXBUFCNT_NPCMD(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_NPCMD,M_LDT_TXBUFCNT_NPCMD) +#define M_LDT_TXBUFCNT_NPCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPCMD) +#define V_LDT_TXBUFCNT_NPCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPCMD) +#define G_LDT_TXBUFCNT_NPCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPCMD, M_LDT_TXBUFCNT_NPCMD) #define S_LDT_TXBUFCNT_NPDATA 12 -#define M_LDT_TXBUFCNT_NPDATA _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_NPDATA) -#define V_LDT_TXBUFCNT_NPDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_NPDATA) -#define G_LDT_TXBUFCNT_NPDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_NPDATA,M_LDT_TXBUFCNT_NPDATA) +#define M_LDT_TXBUFCNT_NPDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPDATA) +#define V_LDT_TXBUFCNT_NPDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPDATA) +#define G_LDT_TXBUFCNT_NPDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPDATA, M_LDT_TXBUFCNT_NPDATA) #define S_LDT_TXBUFCNT_RCMD 16 -#define M_LDT_TXBUFCNT_RCMD _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_RCMD) -#define V_LDT_TXBUFCNT_RCMD(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_RCMD) -#define G_LDT_TXBUFCNT_RCMD(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_RCMD,M_LDT_TXBUFCNT_RCMD) +#define M_LDT_TXBUFCNT_RCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RCMD) +#define V_LDT_TXBUFCNT_RCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RCMD) +#define G_LDT_TXBUFCNT_RCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RCMD, M_LDT_TXBUFCNT_RCMD) #define S_LDT_TXBUFCNT_RDATA 20 -#define M_LDT_TXBUFCNT_RDATA _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_RDATA) -#define V_LDT_TXBUFCNT_RDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_RDATA) -#define G_LDT_TXBUFCNT_RDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_RDATA,M_LDT_TXBUFCNT_RDATA) +#define M_LDT_TXBUFCNT_RDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RDATA) +#define V_LDT_TXBUFCNT_RDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RDATA) +#define G_LDT_TXBUFCNT_RDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RDATA, M_LDT_TXBUFCNT_RDATA) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) /* @@ -414,9 +414,9 @@ */ #define S_LDT_ADDSTATUS_TGTDONE 0 -#define M_LDT_ADDSTATUS_TGTDONE _SB_MAKEMASK_32(8,S_LDT_ADDSTATUS_TGTDONE) -#define V_LDT_ADDSTATUS_TGTDONE(x) _SB_MAKEVALUE_32(x,S_LDT_ADDSTATUS_TGTDONE) -#define G_LDT_ADDSTATUS_TGTDONE(x) _SB_GETVALUE_32(x,S_LDT_ADDSTATUS_TGTDONE,M_LDT_ADDSTATUS_TGTDONE) +#define M_LDT_ADDSTATUS_TGTDONE _SB_MAKEMASK_32(8, S_LDT_ADDSTATUS_TGTDONE) +#define V_LDT_ADDSTATUS_TGTDONE(x) _SB_MAKEVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE) +#define G_LDT_ADDSTATUS_TGTDONE(x) _SB_GETVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE, M_LDT_ADDSTATUS_TGTDONE) #endif /* 1250 PASS2 || 112x PASS1 */ #endif diff --git a/include/asm-mips/sibyte/sb1250_mac.h b/include/asm-mips/sibyte/sb1250_mac.h index 833c8b59d687..b6faf08ca81d 100644 --- a/include/asm-mips/sibyte/sb1250_mac.h +++ b/include/asm-mips/sibyte/sb1250_mac.h @@ -55,8 +55,8 @@ #define M_MAC_BURST_EN _SB_MAKEMASK1(5) #define S_MAC_TX_PAUSE _SB_MAKE64(6) -#define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3,S_MAC_TX_PAUSE) -#define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x,S_MAC_TX_PAUSE) +#define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3, S_MAC_TX_PAUSE) +#define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x, S_MAC_TX_PAUSE) #define K_MAC_TX_PAUSE_CNT_512 0 #define K_MAC_TX_PAUSE_CNT_1K 1 @@ -76,7 +76,7 @@ #define V_MAC_TX_PAUSE_CNT_32K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K) #define V_MAC_TX_PAUSE_CNT_64K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K) -#define M_MAC_RESERVED1 _SB_MAKEMASK(8,9) +#define M_MAC_RESERVED1 _SB_MAKEMASK(8, 9) #define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17) @@ -91,15 +91,15 @@ #define M_MAC_DRP_OSZPKT_EN _SB_MAKEMASK1(24) #define M_MAC_DRP_LENERRPKT_EN _SB_MAKEMASK1(25) -#define M_MAC_RESERVED3 _SB_MAKEMASK(6,26) +#define M_MAC_RESERVED3 _SB_MAKEMASK(6, 26) #define M_MAC_BYPASS_SEL _SB_MAKEMASK1(32) #define M_MAC_HDX_EN _SB_MAKEMASK1(33) #define S_MAC_SPEED_SEL _SB_MAKE64(34) -#define M_MAC_SPEED_SEL _SB_MAKEMASK(2,S_MAC_SPEED_SEL) -#define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x,S_MAC_SPEED_SEL) -#define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x,S_MAC_SPEED_SEL,M_MAC_SPEED_SEL) +#define M_MAC_SPEED_SEL _SB_MAKEMASK(2, S_MAC_SPEED_SEL) +#define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x, S_MAC_SPEED_SEL) +#define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x, S_MAC_SPEED_SEL, M_MAC_SPEED_SEL) #define K_MAC_SPEED_SEL_10MBPS 0 #define K_MAC_SPEED_SEL_100MBPS 1 @@ -117,9 +117,9 @@ #define M_MAC_SS_EN _SB_MAKEMASK1(39) #define S_MAC_BYPASS_CFG _SB_MAKE64(40) -#define M_MAC_BYPASS_CFG _SB_MAKEMASK(2,S_MAC_BYPASS_CFG) -#define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_CFG) -#define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_CFG,M_MAC_BYPASS_CFG) +#define M_MAC_BYPASS_CFG _SB_MAKEMASK(2, S_MAC_BYPASS_CFG) +#define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x, S_MAC_BYPASS_CFG) +#define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x, S_MAC_BYPASS_CFG, M_MAC_BYPASS_CFG) #define K_MAC_BYPASS_GMII 0 #define K_MAC_BYPASS_ENCODED 1 @@ -138,9 +138,9 @@ #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define S_MAC_BYPASS_IFG _SB_MAKE64(46) -#define M_MAC_BYPASS_IFG _SB_MAKEMASK(8,S_MAC_BYPASS_IFG) -#define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_IFG) -#define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_IFG,M_MAC_BYPASS_IFG) +#define M_MAC_BYPASS_IFG _SB_MAKEMASK(8, S_MAC_BYPASS_IFG) +#define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x, S_MAC_BYPASS_IFG) +#define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x, S_MAC_BYPASS_IFG, M_MAC_BYPASS_IFG) #define K_MAC_FC_CMD_DISABLED 0 #define K_MAC_FC_CMD_ENABLED 1 @@ -153,14 +153,14 @@ #define M_MAC_FC_SEL _SB_MAKEMASK1(54) #define S_MAC_FC_CMD _SB_MAKE64(55) -#define M_MAC_FC_CMD _SB_MAKEMASK(2,S_MAC_FC_CMD) -#define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x,S_MAC_FC_CMD) -#define G_MAC_FC_CMD(x) _SB_GETVALUE(x,S_MAC_FC_CMD,M_MAC_FC_CMD) +#define M_MAC_FC_CMD _SB_MAKEMASK(2, S_MAC_FC_CMD) +#define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x, S_MAC_FC_CMD) +#define G_MAC_FC_CMD(x) _SB_GETVALUE(x, S_MAC_FC_CMD, M_MAC_FC_CMD) #define S_MAC_RX_CH_SEL _SB_MAKE64(57) -#define M_MAC_RX_CH_SEL _SB_MAKEMASK(7,S_MAC_RX_CH_SEL) -#define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_SEL) -#define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_SEL,M_MAC_RX_CH_SEL) +#define M_MAC_RX_CH_SEL _SB_MAKEMASK(7, S_MAC_RX_CH_SEL) +#define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_SEL) +#define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_SEL, M_MAC_RX_CH_SEL) /* @@ -202,14 +202,14 @@ */ #define S_MAC_TXD_WEIGHT0 _SB_MAKE64(0) -#define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT0) -#define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT0) -#define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT0,M_MAC_TXD_WEIGHT0) +#define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT0) +#define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT0) +#define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT0, M_MAC_TXD_WEIGHT0) #define S_MAC_TXD_WEIGHT1 _SB_MAKE64(4) -#define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT1) -#define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT1) -#define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT1,M_MAC_TXD_WEIGHT1) +#define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT1) +#define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT1) +#define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT1, M_MAC_TXD_WEIGHT1) /* * MAC Fifo Threshhold registers (Table 9-14) @@ -221,50 +221,50 @@ #define S_MAC_TX_WR_THRSH _SB_MAKE64(0) #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) /* XXX: Can't enable, as it has the same name as a pass2+ define below. */ -/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6,S_MAC_TX_WR_THRSH) */ +/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6, S_MAC_TX_WR_THRSH) */ #endif /* up to 1250 PASS1 */ #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7,S_MAC_TX_WR_THRSH) +#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7, S_MAC_TX_WR_THRSH) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ -#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_WR_THRSH) -#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_WR_THRSH,M_MAC_TX_WR_THRSH) +#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_WR_THRSH) +#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_WR_THRSH, M_MAC_TX_WR_THRSH) #define S_MAC_TX_RD_THRSH _SB_MAKE64(8) #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) /* XXX: Can't enable, as it has the same name as a pass2+ define below. */ -/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6,S_MAC_TX_RD_THRSH) */ +/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6, S_MAC_TX_RD_THRSH) */ #endif /* up to 1250 PASS1 */ #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7,S_MAC_TX_RD_THRSH) +#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7, S_MAC_TX_RD_THRSH) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ -#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RD_THRSH) -#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RD_THRSH,M_MAC_TX_RD_THRSH) +#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_RD_THRSH) +#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_RD_THRSH, M_MAC_TX_RD_THRSH) #define S_MAC_TX_RL_THRSH _SB_MAKE64(16) -#define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4,S_MAC_TX_RL_THRSH) -#define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RL_THRSH) -#define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RL_THRSH,M_MAC_TX_RL_THRSH) +#define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4, S_MAC_TX_RL_THRSH) +#define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_RL_THRSH) +#define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_RL_THRSH, M_MAC_TX_RL_THRSH) #define S_MAC_RX_PL_THRSH _SB_MAKE64(24) -#define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6,S_MAC_RX_PL_THRSH) -#define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_PL_THRSH) -#define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_PL_THRSH,M_MAC_RX_PL_THRSH) +#define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6, S_MAC_RX_PL_THRSH) +#define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_PL_THRSH) +#define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_PL_THRSH, M_MAC_RX_PL_THRSH) #define S_MAC_RX_RD_THRSH _SB_MAKE64(32) -#define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6,S_MAC_RX_RD_THRSH) -#define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RD_THRSH) -#define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RD_THRSH,M_MAC_RX_RD_THRSH) +#define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6, S_MAC_RX_RD_THRSH) +#define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_RD_THRSH) +#define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_RD_THRSH, M_MAC_RX_RD_THRSH) #define S_MAC_RX_RL_THRSH _SB_MAKE64(40) -#define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6,S_MAC_RX_RL_THRSH) -#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RL_THRSH) -#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RL_THRSH,M_MAC_RX_RL_THRSH) +#define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6, S_MAC_RX_RL_THRSH) +#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_RL_THRSH) +#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_RL_THRSH, M_MAC_RX_RL_THRSH) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_MAC_ENC_FC_THRSH _SB_MAKE64(56) -#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6,S_MAC_ENC_FC_THRSH) -#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x,S_MAC_ENC_FC_THRSH) -#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x,S_MAC_ENC_FC_THRSH,M_MAC_ENC_FC_THRSH) +#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6, S_MAC_ENC_FC_THRSH) +#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x, S_MAC_ENC_FC_THRSH) +#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x, S_MAC_ENC_FC_THRSH, M_MAC_ENC_FC_THRSH) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ /* @@ -276,51 +276,51 @@ /* XXXCGD: ??? Unused in pass2? */ #define S_MAC_IFG_RX _SB_MAKE64(0) -#define M_MAC_IFG_RX _SB_MAKEMASK(6,S_MAC_IFG_RX) -#define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x,S_MAC_IFG_RX) -#define G_MAC_IFG_RX(x) _SB_GETVALUE(x,S_MAC_IFG_RX,M_MAC_IFG_RX) +#define M_MAC_IFG_RX _SB_MAKEMASK(6, S_MAC_IFG_RX) +#define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x, S_MAC_IFG_RX) +#define G_MAC_IFG_RX(x) _SB_GETVALUE(x, S_MAC_IFG_RX, M_MAC_IFG_RX) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_MAC_PRE_LEN _SB_MAKE64(0) -#define M_MAC_PRE_LEN _SB_MAKEMASK(6,S_MAC_PRE_LEN) -#define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x,S_MAC_PRE_LEN) -#define G_MAC_PRE_LEN(x) _SB_GETVALUE(x,S_MAC_PRE_LEN,M_MAC_PRE_LEN) +#define M_MAC_PRE_LEN _SB_MAKEMASK(6, S_MAC_PRE_LEN) +#define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x, S_MAC_PRE_LEN) +#define G_MAC_PRE_LEN(x) _SB_GETVALUE(x, S_MAC_PRE_LEN, M_MAC_PRE_LEN) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define S_MAC_IFG_TX _SB_MAKE64(6) -#define M_MAC_IFG_TX _SB_MAKEMASK(6,S_MAC_IFG_TX) -#define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x,S_MAC_IFG_TX) -#define G_MAC_IFG_TX(x) _SB_GETVALUE(x,S_MAC_IFG_TX,M_MAC_IFG_TX) +#define M_MAC_IFG_TX _SB_MAKEMASK(6, S_MAC_IFG_TX) +#define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x, S_MAC_IFG_TX) +#define G_MAC_IFG_TX(x) _SB_GETVALUE(x, S_MAC_IFG_TX, M_MAC_IFG_TX) #define S_MAC_IFG_THRSH _SB_MAKE64(12) -#define M_MAC_IFG_THRSH _SB_MAKEMASK(6,S_MAC_IFG_THRSH) -#define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x,S_MAC_IFG_THRSH) -#define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x,S_MAC_IFG_THRSH,M_MAC_IFG_THRSH) +#define M_MAC_IFG_THRSH _SB_MAKEMASK(6, S_MAC_IFG_THRSH) +#define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x, S_MAC_IFG_THRSH) +#define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x, S_MAC_IFG_THRSH, M_MAC_IFG_THRSH) #define S_MAC_BACKOFF_SEL _SB_MAKE64(18) -#define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4,S_MAC_BACKOFF_SEL) -#define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x,S_MAC_BACKOFF_SEL) -#define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x,S_MAC_BACKOFF_SEL,M_MAC_BACKOFF_SEL) +#define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4, S_MAC_BACKOFF_SEL) +#define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x, S_MAC_BACKOFF_SEL) +#define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x, S_MAC_BACKOFF_SEL, M_MAC_BACKOFF_SEL) #define S_MAC_LFSR_SEED _SB_MAKE64(22) -#define M_MAC_LFSR_SEED _SB_MAKEMASK(8,S_MAC_LFSR_SEED) -#define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x,S_MAC_LFSR_SEED) -#define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x,S_MAC_LFSR_SEED,M_MAC_LFSR_SEED) +#define M_MAC_LFSR_SEED _SB_MAKEMASK(8, S_MAC_LFSR_SEED) +#define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x, S_MAC_LFSR_SEED) +#define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x, S_MAC_LFSR_SEED, M_MAC_LFSR_SEED) #define S_MAC_SLOT_SIZE _SB_MAKE64(30) -#define M_MAC_SLOT_SIZE _SB_MAKEMASK(10,S_MAC_SLOT_SIZE) -#define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x,S_MAC_SLOT_SIZE) -#define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x,S_MAC_SLOT_SIZE,M_MAC_SLOT_SIZE) +#define M_MAC_SLOT_SIZE _SB_MAKEMASK(10, S_MAC_SLOT_SIZE) +#define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x, S_MAC_SLOT_SIZE) +#define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x, S_MAC_SLOT_SIZE, M_MAC_SLOT_SIZE) #define S_MAC_MIN_FRAMESZ _SB_MAKE64(40) -#define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8,S_MAC_MIN_FRAMESZ) -#define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MIN_FRAMESZ) -#define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MIN_FRAMESZ,M_MAC_MIN_FRAMESZ) +#define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8, S_MAC_MIN_FRAMESZ) +#define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x, S_MAC_MIN_FRAMESZ) +#define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x, S_MAC_MIN_FRAMESZ, M_MAC_MIN_FRAMESZ) #define S_MAC_MAX_FRAMESZ _SB_MAKE64(48) -#define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16,S_MAC_MAX_FRAMESZ) -#define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MAX_FRAMESZ) -#define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MAX_FRAMESZ,M_MAC_MAX_FRAMESZ) +#define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16, S_MAC_MAX_FRAMESZ) +#define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x, S_MAC_MAX_FRAMESZ) +#define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x, S_MAC_MAX_FRAMESZ, M_MAC_MAX_FRAMESZ) /* * These constants are used to configure the fields within the Frame @@ -377,20 +377,20 @@ */ #define S_MAC_VLAN_TAG _SB_MAKE64(0) -#define M_MAC_VLAN_TAG _SB_MAKEMASK(32,S_MAC_VLAN_TAG) -#define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x,S_MAC_VLAN_TAG) -#define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x,S_MAC_VLAN_TAG,M_MAC_VLAN_TAG) +#define M_MAC_VLAN_TAG _SB_MAKEMASK(32, S_MAC_VLAN_TAG) +#define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x, S_MAC_VLAN_TAG) +#define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x, S_MAC_VLAN_TAG, M_MAC_VLAN_TAG) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) #define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32) -#define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_TX_PKT_OFFSET) -#define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_PKT_OFFSET) -#define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_PKT_OFFSET,M_MAC_TX_PKT_OFFSET) +#define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8, S_MAC_TX_PKT_OFFSET) +#define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_TX_PKT_OFFSET) +#define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_TX_PKT_OFFSET, M_MAC_TX_PKT_OFFSET) #define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40) -#define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_TX_CRC_OFFSET) -#define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_CRC_OFFSET) -#define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_CRC_OFFSET,M_MAC_TX_CRC_OFFSET) +#define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8, S_MAC_TX_CRC_OFFSET) +#define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_TX_CRC_OFFSET) +#define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_TX_CRC_OFFSET, M_MAC_TX_CRC_OFFSET) #define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48) #endif /* 1250 PASS3 || 112x PASS1 */ @@ -425,7 +425,7 @@ * is that you'll use one of the "S_" things above * and pass just the six bits to a DMA-channel-specific ISR */ -#define M_MAC_INT_CHANNEL _SB_MAKEMASK(8,0) +#define M_MAC_INT_CHANNEL _SB_MAKEMASK(8, 0) #define M_MAC_INT_EOP_COUNT _SB_MAKEMASK1(0) #define M_MAC_INT_EOP_TIMER _SB_MAKEMASK1(1) #define M_MAC_INT_EOP_SEEN _SB_MAKEMASK1(2) @@ -440,19 +440,19 @@ * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see * also DMA_TX/DMA_RX in sb_regs.h). */ -#define S_MAC_STATUS_CH_OFFSET(ch,txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH) +#define S_MAC_STATUS_CH_OFFSET(ch, txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH) -#define M_MAC_STATUS_CHANNEL(ch,txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8,0),S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_EOP_COUNT(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_EOP_TIMER(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_EOP_SEEN(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_HWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_HWM,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_LWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_LWM,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_DSCR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_ERR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_ERR,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_DZERO(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_DROP(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DROP,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7,0),40) +#define M_MAC_STATUS_CHANNEL(ch, txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8, 0), S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_EOP_COUNT(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_EOP_TIMER(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_EOP_SEEN(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_HWM(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_HWM, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_LWM(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_LWM, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_DSCR(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_ERR(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_ERR, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_DZERO(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_DROP(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DROP, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7, 0), 40) #define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40) @@ -467,9 +467,9 @@ #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define S_MAC_COUNTER_ADDR _SB_MAKE64(47) -#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5,S_MAC_COUNTER_ADDR) -#define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR) -#define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR) +#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5, S_MAC_COUNTER_ADDR) +#define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x, S_MAC_COUNTER_ADDR) +#define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x, S_MAC_COUNTER_ADDR, M_MAC_COUNTER_ADDR) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52) @@ -483,24 +483,24 @@ */ #define S_MAC_TX_WRPTR _SB_MAKE64(0) -#define M_MAC_TX_WRPTR _SB_MAKEMASK(6,S_MAC_TX_WRPTR) -#define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_WRPTR) -#define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x,S_MAC_TX_WRPTR,M_MAC_TX_WRPTR) +#define M_MAC_TX_WRPTR _SB_MAKEMASK(6, S_MAC_TX_WRPTR) +#define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x, S_MAC_TX_WRPTR) +#define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x, S_MAC_TX_WRPTR, M_MAC_TX_WRPTR) #define S_MAC_TX_RDPTR _SB_MAKE64(8) -#define M_MAC_TX_RDPTR _SB_MAKEMASK(6,S_MAC_TX_RDPTR) -#define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_RDPTR) -#define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x,S_MAC_TX_RDPTR,M_MAC_TX_RDPTR) +#define M_MAC_TX_RDPTR _SB_MAKEMASK(6, S_MAC_TX_RDPTR) +#define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x, S_MAC_TX_RDPTR) +#define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x, S_MAC_TX_RDPTR, M_MAC_TX_RDPTR) #define S_MAC_RX_WRPTR _SB_MAKE64(16) -#define M_MAC_RX_WRPTR _SB_MAKEMASK(6,S_MAC_RX_WRPTR) -#define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_WRPTR) -#define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x,S_MAC_RX_WRPTR,M_MAC_TX_WRPTR) +#define M_MAC_RX_WRPTR _SB_MAKEMASK(6, S_MAC_RX_WRPTR) +#define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x, S_MAC_RX_WRPTR) +#define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x, S_MAC_RX_WRPTR, M_MAC_TX_WRPTR) #define S_MAC_RX_RDPTR _SB_MAKE64(24) -#define M_MAC_RX_RDPTR _SB_MAKEMASK(6,S_MAC_RX_RDPTR) -#define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_RDPTR) -#define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x,S_MAC_RX_RDPTR,M_MAC_TX_RDPTR) +#define M_MAC_RX_RDPTR _SB_MAKEMASK(6, S_MAC_RX_RDPTR) +#define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x, S_MAC_RX_RDPTR) +#define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x, S_MAC_RX_RDPTR, M_MAC_TX_RDPTR) /* * MAC Fifo End Of Packet Count Registers (Table 9-20) [Debug register] @@ -510,14 +510,14 @@ */ #define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0) -#define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_TX_EOP_COUNTER) -#define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_TX_EOP_COUNTER) -#define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_TX_EOP_COUNTER,M_MAC_TX_EOP_COUNTER) +#define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6, S_MAC_TX_EOP_COUNTER) +#define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x, S_MAC_TX_EOP_COUNTER) +#define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_TX_EOP_COUNTER, M_MAC_TX_EOP_COUNTER) #define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8) -#define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_RX_EOP_COUNTER) -#define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_RX_EOP_COUNTER) -#define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_RX_EOP_COUNTER,M_MAC_RX_EOP_COUNTER) +#define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6, S_MAC_RX_EOP_COUNTER) +#define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x, S_MAC_RX_EOP_COUNTER) +#define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_RX_EOP_COUNTER, M_MAC_RX_EOP_COUNTER) /* * MAC Recieve Address Filter Exact Match Registers (Table 9-21) @@ -565,24 +565,24 @@ #define S_TYPECFG_TYPESIZE _SB_MAKE64(16) #define S_TYPECFG_TYPE0 _SB_MAKE64(0) -#define M_TYPECFG_TYPE0 _SB_MAKEMASK(16,S_TYPECFG_TYPE0) -#define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE0) -#define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x,S_TYPECFG_TYPE0,M_TYPECFG_TYPE0) +#define M_TYPECFG_TYPE0 _SB_MAKEMASK(16, S_TYPECFG_TYPE0) +#define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE0) +#define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x, S_TYPECFG_TYPE0, M_TYPECFG_TYPE0) #define S_TYPECFG_TYPE1 _SB_MAKE64(0) -#define M_TYPECFG_TYPE1 _SB_MAKEMASK(16,S_TYPECFG_TYPE1) -#define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE1) -#define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x,S_TYPECFG_TYPE1,M_TYPECFG_TYPE1) +#define M_TYPECFG_TYPE1 _SB_MAKEMASK(16, S_TYPECFG_TYPE1) +#define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE1) +#define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x, S_TYPECFG_TYPE1, M_TYPECFG_TYPE1) #define S_TYPECFG_TYPE2 _SB_MAKE64(0) -#define M_TYPECFG_TYPE2 _SB_MAKEMASK(16,S_TYPECFG_TYPE2) -#define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE2) -#define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x,S_TYPECFG_TYPE2,M_TYPECFG_TYPE2) +#define M_TYPECFG_TYPE2 _SB_MAKEMASK(16, S_TYPECFG_TYPE2) +#define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE2) +#define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x, S_TYPECFG_TYPE2, M_TYPECFG_TYPE2) #define S_TYPECFG_TYPE3 _SB_MAKE64(0) -#define M_TYPECFG_TYPE3 _SB_MAKEMASK(16,S_TYPECFG_TYPE3) -#define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE3) -#define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x,S_TYPECFG_TYPE3,M_TYPECFG_TYPE3) +#define M_TYPECFG_TYPE3 _SB_MAKEMASK(16, S_TYPECFG_TYPE3) +#define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE3) +#define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x, S_TYPECFG_TYPE3, M_TYPECFG_TYPE3) /* * MAC Receive Address Filter Control Registers (Table 9-24) @@ -603,28 +603,28 @@ #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define S_MAC_IPHDR_OFFSET _SB_MAKE64(8) -#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8,S_MAC_IPHDR_OFFSET) -#define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET) -#define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET) +#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8, S_MAC_IPHDR_OFFSET) +#define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_IPHDR_OFFSET) +#define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x, S_MAC_IPHDR_OFFSET, M_MAC_IPHDR_OFFSET) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16) -#define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_RX_CRC_OFFSET) -#define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_CRC_OFFSET) -#define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_CRC_OFFSET,M_MAC_RX_CRC_OFFSET) +#define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8, S_MAC_RX_CRC_OFFSET) +#define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_CRC_OFFSET) +#define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_CRC_OFFSET, M_MAC_RX_CRC_OFFSET) #define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24) -#define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_RX_PKT_OFFSET) -#define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_PKT_OFFSET) -#define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_PKT_OFFSET,M_MAC_RX_PKT_OFFSET) +#define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8, S_MAC_RX_PKT_OFFSET) +#define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_PKT_OFFSET) +#define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_PKT_OFFSET, M_MAC_RX_PKT_OFFSET) #define M_MAC_FWDPAUSE_EN _SB_MAKEMASK1(32) #define M_MAC_VLAN_DET_EN _SB_MAKEMASK1(33) #define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34) -#define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8,S_MAC_RX_CH_MSN_SEL) -#define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_MSN_SEL) -#define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_MSN_SEL,M_MAC_RX_CH_MSN_SEL) +#define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8, S_MAC_RX_CH_MSN_SEL) +#define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_MSN_SEL) +#define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_MSN_SEL, M_MAC_RX_CH_MSN_SEL) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ /* diff --git a/include/asm-mips/sibyte/sb1250_mc.h b/include/asm-mips/sibyte/sb1250_mc.h index 4fe848ffbc31..1eb1b5a88736 100644 --- a/include/asm-mips/sibyte/sb1250_mc.h +++ b/include/asm-mips/sibyte/sb1250_mc.h @@ -10,7 +10,7 @@ * ********************************************************************* * - * Copyright 2000,2001,2002,2003 + * Copyright 2000, 2001, 2002, 2003 * Broadcom Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or @@ -40,73 +40,73 @@ */ #define S_MC_RESERVED0 0 -#define M_MC_RESERVED0 _SB_MAKEMASK(8,S_MC_RESERVED0) +#define M_MC_RESERVED0 _SB_MAKEMASK(8, S_MC_RESERVED0) #define S_MC_CHANNEL_SEL 8 -#define M_MC_CHANNEL_SEL _SB_MAKEMASK(8,S_MC_CHANNEL_SEL) -#define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x,S_MC_CHANNEL_SEL) -#define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x,S_MC_CHANNEL_SEL,M_MC_CHANNEL_SEL) +#define M_MC_CHANNEL_SEL _SB_MAKEMASK(8, S_MC_CHANNEL_SEL) +#define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x, S_MC_CHANNEL_SEL) +#define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x, S_MC_CHANNEL_SEL, M_MC_CHANNEL_SEL) #define S_MC_BANK0_MAP 16 -#define M_MC_BANK0_MAP _SB_MAKEMASK(4,S_MC_BANK0_MAP) -#define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK0_MAP) -#define G_MC_BANK0_MAP(x) _SB_GETVALUE(x,S_MC_BANK0_MAP,M_MC_BANK0_MAP) +#define M_MC_BANK0_MAP _SB_MAKEMASK(4, S_MC_BANK0_MAP) +#define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK0_MAP) +#define G_MC_BANK0_MAP(x) _SB_GETVALUE(x, S_MC_BANK0_MAP, M_MC_BANK0_MAP) #define K_MC_BANK0_MAP_DEFAULT 0x00 #define V_MC_BANK0_MAP_DEFAULT V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT) #define S_MC_BANK1_MAP 20 -#define M_MC_BANK1_MAP _SB_MAKEMASK(4,S_MC_BANK1_MAP) -#define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK1_MAP) -#define G_MC_BANK1_MAP(x) _SB_GETVALUE(x,S_MC_BANK1_MAP,M_MC_BANK1_MAP) +#define M_MC_BANK1_MAP _SB_MAKEMASK(4, S_MC_BANK1_MAP) +#define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK1_MAP) +#define G_MC_BANK1_MAP(x) _SB_GETVALUE(x, S_MC_BANK1_MAP, M_MC_BANK1_MAP) #define K_MC_BANK1_MAP_DEFAULT 0x08 #define V_MC_BANK1_MAP_DEFAULT V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT) #define S_MC_BANK2_MAP 24 -#define M_MC_BANK2_MAP _SB_MAKEMASK(4,S_MC_BANK2_MAP) -#define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK2_MAP) -#define G_MC_BANK2_MAP(x) _SB_GETVALUE(x,S_MC_BANK2_MAP,M_MC_BANK2_MAP) +#define M_MC_BANK2_MAP _SB_MAKEMASK(4, S_MC_BANK2_MAP) +#define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK2_MAP) +#define G_MC_BANK2_MAP(x) _SB_GETVALUE(x, S_MC_BANK2_MAP, M_MC_BANK2_MAP) #define K_MC_BANK2_MAP_DEFAULT 0x09 #define V_MC_BANK2_MAP_DEFAULT V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT) #define S_MC_BANK3_MAP 28 -#define M_MC_BANK3_MAP _SB_MAKEMASK(4,S_MC_BANK3_MAP) -#define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK3_MAP) -#define G_MC_BANK3_MAP(x) _SB_GETVALUE(x,S_MC_BANK3_MAP,M_MC_BANK3_MAP) +#define M_MC_BANK3_MAP _SB_MAKEMASK(4, S_MC_BANK3_MAP) +#define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK3_MAP) +#define G_MC_BANK3_MAP(x) _SB_GETVALUE(x, S_MC_BANK3_MAP, M_MC_BANK3_MAP) #define K_MC_BANK3_MAP_DEFAULT 0x0C #define V_MC_BANK3_MAP_DEFAULT V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT) -#define M_MC_RESERVED1 _SB_MAKEMASK(8,32) +#define M_MC_RESERVED1 _SB_MAKEMASK(8, 32) #define S_MC_QUEUE_SIZE 40 -#define M_MC_QUEUE_SIZE _SB_MAKEMASK(4,S_MC_QUEUE_SIZE) -#define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x,S_MC_QUEUE_SIZE) -#define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x,S_MC_QUEUE_SIZE,M_MC_QUEUE_SIZE) +#define M_MC_QUEUE_SIZE _SB_MAKEMASK(4, S_MC_QUEUE_SIZE) +#define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x, S_MC_QUEUE_SIZE) +#define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x, S_MC_QUEUE_SIZE, M_MC_QUEUE_SIZE) #define V_MC_QUEUE_SIZE_DEFAULT V_MC_QUEUE_SIZE(0x0A) #define S_MC_AGE_LIMIT 44 -#define M_MC_AGE_LIMIT _SB_MAKEMASK(4,S_MC_AGE_LIMIT) -#define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x,S_MC_AGE_LIMIT) -#define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x,S_MC_AGE_LIMIT,M_MC_AGE_LIMIT) +#define M_MC_AGE_LIMIT _SB_MAKEMASK(4, S_MC_AGE_LIMIT) +#define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x, S_MC_AGE_LIMIT) +#define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x, S_MC_AGE_LIMIT, M_MC_AGE_LIMIT) #define V_MC_AGE_LIMIT_DEFAULT V_MC_AGE_LIMIT(8) #define S_MC_WR_LIMIT 48 -#define M_MC_WR_LIMIT _SB_MAKEMASK(4,S_MC_WR_LIMIT) -#define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x,S_MC_WR_LIMIT) -#define G_MC_WR_LIMIT(x) _SB_GETVALUE(x,S_MC_WR_LIMIT,M_MC_WR_LIMIT) +#define M_MC_WR_LIMIT _SB_MAKEMASK(4, S_MC_WR_LIMIT) +#define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x, S_MC_WR_LIMIT) +#define G_MC_WR_LIMIT(x) _SB_GETVALUE(x, S_MC_WR_LIMIT, M_MC_WR_LIMIT) #define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5) #define M_MC_IOB1HIGHPRIORITY _SB_MAKEMASK1(52) -#define M_MC_RESERVED2 _SB_MAKEMASK(3,53) +#define M_MC_RESERVED2 _SB_MAKEMASK(3, 53) #define S_MC_CS_MODE 56 -#define M_MC_CS_MODE _SB_MAKEMASK(4,S_MC_CS_MODE) -#define V_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_MC_CS_MODE) -#define G_MC_CS_MODE(x) _SB_GETVALUE(x,S_MC_CS_MODE,M_MC_CS_MODE) +#define M_MC_CS_MODE _SB_MAKEMASK(4, S_MC_CS_MODE) +#define V_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_MC_CS_MODE) +#define G_MC_CS_MODE(x) _SB_GETVALUE(x, S_MC_CS_MODE, M_MC_CS_MODE) #define K_MC_CS_MODE_MSB_CS 0 #define K_MC_CS_MODE_INTLV_CS 15 @@ -138,9 +138,9 @@ */ #define S_MC_CLK_RATIO 0 -#define M_MC_CLK_RATIO _SB_MAKEMASK(4,S_MC_CLK_RATIO) -#define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_MC_CLK_RATIO) -#define G_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_MC_CLK_RATIO,M_MC_CLK_RATIO) +#define M_MC_CLK_RATIO _SB_MAKEMASK(4, S_MC_CLK_RATIO) +#define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_MC_CLK_RATIO) +#define G_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_MC_CLK_RATIO, M_MC_CLK_RATIO) #define K_MC_CLK_RATIO_2X 4 #define K_MC_CLK_RATIO_25X 5 @@ -158,9 +158,9 @@ #define V_MC_CLK_RATIO_DEFAULT V_MC_CLK_RATIO_25X #define S_MC_REF_RATE 8 -#define M_MC_REF_RATE _SB_MAKEMASK(8,S_MC_REF_RATE) -#define V_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_MC_REF_RATE) -#define G_MC_REF_RATE(x) _SB_GETVALUE(x,S_MC_REF_RATE,M_MC_REF_RATE) +#define M_MC_REF_RATE _SB_MAKEMASK(8, S_MC_REF_RATE) +#define V_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_MC_REF_RATE) +#define G_MC_REF_RATE(x) _SB_GETVALUE(x, S_MC_REF_RATE, M_MC_REF_RATE) #define K_MC_REF_RATE_100MHz 0x62 #define K_MC_REF_RATE_133MHz 0x81 @@ -172,21 +172,21 @@ #define V_MC_REF_RATE_DEFAULT V_MC_REF_RATE_100MHz #define S_MC_CLOCK_DRIVE 16 -#define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4,S_MC_CLOCK_DRIVE) -#define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x,S_MC_CLOCK_DRIVE) -#define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x,S_MC_CLOCK_DRIVE,M_MC_CLOCK_DRIVE) +#define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4, S_MC_CLOCK_DRIVE) +#define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x, S_MC_CLOCK_DRIVE) +#define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x, S_MC_CLOCK_DRIVE, M_MC_CLOCK_DRIVE) #define V_MC_CLOCK_DRIVE_DEFAULT V_MC_CLOCK_DRIVE(0xF) #define S_MC_DATA_DRIVE 20 -#define M_MC_DATA_DRIVE _SB_MAKEMASK(4,S_MC_DATA_DRIVE) -#define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x,S_MC_DATA_DRIVE) -#define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x,S_MC_DATA_DRIVE,M_MC_DATA_DRIVE) +#define M_MC_DATA_DRIVE _SB_MAKEMASK(4, S_MC_DATA_DRIVE) +#define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x, S_MC_DATA_DRIVE) +#define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x, S_MC_DATA_DRIVE, M_MC_DATA_DRIVE) #define V_MC_DATA_DRIVE_DEFAULT V_MC_DATA_DRIVE(0x0) #define S_MC_ADDR_DRIVE 24 -#define M_MC_ADDR_DRIVE _SB_MAKEMASK(4,S_MC_ADDR_DRIVE) -#define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x,S_MC_ADDR_DRIVE) -#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x,S_MC_ADDR_DRIVE,M_MC_ADDR_DRIVE) +#define M_MC_ADDR_DRIVE _SB_MAKEMASK(4, S_MC_ADDR_DRIVE) +#define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x, S_MC_ADDR_DRIVE) +#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x, S_MC_ADDR_DRIVE, M_MC_ADDR_DRIVE) #define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) @@ -196,27 +196,27 @@ #define M_MC_DLL_BYPASS _SB_MAKEMASK1(31) #define S_MC_DQI_SKEW 32 -#define M_MC_DQI_SKEW _SB_MAKEMASK(8,S_MC_DQI_SKEW) -#define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQI_SKEW) -#define G_MC_DQI_SKEW(x) _SB_GETVALUE(x,S_MC_DQI_SKEW,M_MC_DQI_SKEW) +#define M_MC_DQI_SKEW _SB_MAKEMASK(8, S_MC_DQI_SKEW) +#define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQI_SKEW) +#define G_MC_DQI_SKEW(x) _SB_GETVALUE(x, S_MC_DQI_SKEW, M_MC_DQI_SKEW) #define V_MC_DQI_SKEW_DEFAULT V_MC_DQI_SKEW(0) #define S_MC_DQO_SKEW 40 -#define M_MC_DQO_SKEW _SB_MAKEMASK(8,S_MC_DQO_SKEW) -#define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQO_SKEW) -#define G_MC_DQO_SKEW(x) _SB_GETVALUE(x,S_MC_DQO_SKEW,M_MC_DQO_SKEW) +#define M_MC_DQO_SKEW _SB_MAKEMASK(8, S_MC_DQO_SKEW) +#define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQO_SKEW) +#define G_MC_DQO_SKEW(x) _SB_GETVALUE(x, S_MC_DQO_SKEW, M_MC_DQO_SKEW) #define V_MC_DQO_SKEW_DEFAULT V_MC_DQO_SKEW(0) #define S_MC_ADDR_SKEW 48 -#define M_MC_ADDR_SKEW _SB_MAKEMASK(8,S_MC_ADDR_SKEW) -#define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x,S_MC_ADDR_SKEW) -#define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x,S_MC_ADDR_SKEW,M_MC_ADDR_SKEW) +#define M_MC_ADDR_SKEW _SB_MAKEMASK(8, S_MC_ADDR_SKEW) +#define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x, S_MC_ADDR_SKEW) +#define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x, S_MC_ADDR_SKEW, M_MC_ADDR_SKEW) #define V_MC_ADDR_SKEW_DEFAULT V_MC_ADDR_SKEW(0x0F) #define S_MC_DLL_DEFAULT 56 -#define M_MC_DLL_DEFAULT _SB_MAKEMASK(8,S_MC_DLL_DEFAULT) -#define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_MC_DLL_DEFAULT) -#define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_MC_DLL_DEFAULT,M_MC_DLL_DEFAULT) +#define M_MC_DLL_DEFAULT _SB_MAKEMASK(8, S_MC_DLL_DEFAULT) +#define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_MC_DLL_DEFAULT) +#define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_MC_DLL_DEFAULT, M_MC_DLL_DEFAULT) #define V_MC_DLL_DEFAULT_DEFAULT V_MC_DLL_DEFAULT(0x10) #define V_MC_CLKCONFIG_DEFAULT V_MC_DLL_DEFAULT_DEFAULT | \ @@ -235,9 +235,9 @@ */ #define S_MC_COMMAND 0 -#define M_MC_COMMAND _SB_MAKEMASK(4,S_MC_COMMAND) -#define V_MC_COMMAND(x) _SB_MAKEVALUE(x,S_MC_COMMAND) -#define G_MC_COMMAND(x) _SB_GETVALUE(x,S_MC_COMMAND,M_MC_COMMAND) +#define M_MC_COMMAND _SB_MAKEMASK(4, S_MC_COMMAND) +#define V_MC_COMMAND(x) _SB_MAKEVALUE(x, S_MC_COMMAND) +#define G_MC_COMMAND(x) _SB_GETVALUE(x, S_MC_COMMAND, M_MC_COMMAND) #define K_MC_COMMAND_EMRS 0 #define K_MC_COMMAND_MRS 1 @@ -267,21 +267,21 @@ */ #define S_MC_EMODE 0 -#define M_MC_EMODE _SB_MAKEMASK(15,S_MC_EMODE) -#define V_MC_EMODE(x) _SB_MAKEVALUE(x,S_MC_EMODE) -#define G_MC_EMODE(x) _SB_GETVALUE(x,S_MC_EMODE,M_MC_EMODE) +#define M_MC_EMODE _SB_MAKEMASK(15, S_MC_EMODE) +#define V_MC_EMODE(x) _SB_MAKEVALUE(x, S_MC_EMODE) +#define G_MC_EMODE(x) _SB_GETVALUE(x, S_MC_EMODE, M_MC_EMODE) #define V_MC_EMODE_DEFAULT V_MC_EMODE(0) #define S_MC_MODE 16 -#define M_MC_MODE _SB_MAKEMASK(15,S_MC_MODE) -#define V_MC_MODE(x) _SB_MAKEVALUE(x,S_MC_MODE) -#define G_MC_MODE(x) _SB_GETVALUE(x,S_MC_MODE,M_MC_MODE) +#define M_MC_MODE _SB_MAKEMASK(15, S_MC_MODE) +#define V_MC_MODE(x) _SB_MAKEVALUE(x, S_MC_MODE) +#define G_MC_MODE(x) _SB_GETVALUE(x, S_MC_MODE, M_MC_MODE) #define V_MC_MODE_DEFAULT V_MC_MODE(0x22) #define S_MC_DRAM_TYPE 32 -#define M_MC_DRAM_TYPE _SB_MAKEMASK(3,S_MC_DRAM_TYPE) -#define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_MC_DRAM_TYPE) -#define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_MC_DRAM_TYPE,M_MC_DRAM_TYPE) +#define M_MC_DRAM_TYPE _SB_MAKEMASK(3, S_MC_DRAM_TYPE) +#define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_MC_DRAM_TYPE) +#define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_MC_DRAM_TYPE, M_MC_DRAM_TYPE) #define K_MC_DRAM_TYPE_JEDEC 0 #define K_MC_DRAM_TYPE_FCRAM 1 @@ -309,16 +309,16 @@ #define M_MC_r2rIDLE_TWOCYCLES _SB_MAKEMASK1(62) #define S_MC_tFIFO 56 -#define M_MC_tFIFO _SB_MAKEMASK(4,S_MC_tFIFO) -#define V_MC_tFIFO(x) _SB_MAKEVALUE(x,S_MC_tFIFO) -#define G_MC_tFIFO(x) _SB_GETVALUE(x,S_MC_tFIFO,M_MC_tFIFO) +#define M_MC_tFIFO _SB_MAKEMASK(4, S_MC_tFIFO) +#define V_MC_tFIFO(x) _SB_MAKEVALUE(x, S_MC_tFIFO) +#define G_MC_tFIFO(x) _SB_GETVALUE(x, S_MC_tFIFO, M_MC_tFIFO) #define K_MC_tFIFO_DEFAULT 1 #define V_MC_tFIFO_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) #define S_MC_tRFC 52 -#define M_MC_tRFC _SB_MAKEMASK(4,S_MC_tRFC) -#define V_MC_tRFC(x) _SB_MAKEVALUE(x,S_MC_tRFC) -#define G_MC_tRFC(x) _SB_GETVALUE(x,S_MC_tRFC,M_MC_tRFC) +#define M_MC_tRFC _SB_MAKEMASK(4, S_MC_tRFC) +#define V_MC_tRFC(x) _SB_MAKEVALUE(x, S_MC_tRFC) +#define G_MC_tRFC(x) _SB_GETVALUE(x, S_MC_tRFC, M_MC_tRFC) #define K_MC_tRFC_DEFAULT 12 #define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT) @@ -327,44 +327,44 @@ #endif #define S_MC_tCwCr 40 -#define M_MC_tCwCr _SB_MAKEMASK(4,S_MC_tCwCr) -#define V_MC_tCwCr(x) _SB_MAKEVALUE(x,S_MC_tCwCr) -#define G_MC_tCwCr(x) _SB_GETVALUE(x,S_MC_tCwCr,M_MC_tCwCr) +#define M_MC_tCwCr _SB_MAKEMASK(4, S_MC_tCwCr) +#define V_MC_tCwCr(x) _SB_MAKEVALUE(x, S_MC_tCwCr) +#define G_MC_tCwCr(x) _SB_GETVALUE(x, S_MC_tCwCr, M_MC_tCwCr) #define K_MC_tCwCr_DEFAULT 4 #define V_MC_tCwCr_DEFAULT V_MC_tCwCr(K_MC_tCwCr_DEFAULT) #define S_MC_tRCr 28 -#define M_MC_tRCr _SB_MAKEMASK(4,S_MC_tRCr) -#define V_MC_tRCr(x) _SB_MAKEVALUE(x,S_MC_tRCr) -#define G_MC_tRCr(x) _SB_GETVALUE(x,S_MC_tRCr,M_MC_tRCr) +#define M_MC_tRCr _SB_MAKEMASK(4, S_MC_tRCr) +#define V_MC_tRCr(x) _SB_MAKEVALUE(x, S_MC_tRCr) +#define G_MC_tRCr(x) _SB_GETVALUE(x, S_MC_tRCr, M_MC_tRCr) #define K_MC_tRCr_DEFAULT 9 #define V_MC_tRCr_DEFAULT V_MC_tRCr(K_MC_tRCr_DEFAULT) #define S_MC_tRCw 24 -#define M_MC_tRCw _SB_MAKEMASK(4,S_MC_tRCw) -#define V_MC_tRCw(x) _SB_MAKEVALUE(x,S_MC_tRCw) -#define G_MC_tRCw(x) _SB_GETVALUE(x,S_MC_tRCw,M_MC_tRCw) +#define M_MC_tRCw _SB_MAKEMASK(4, S_MC_tRCw) +#define V_MC_tRCw(x) _SB_MAKEVALUE(x, S_MC_tRCw) +#define G_MC_tRCw(x) _SB_GETVALUE(x, S_MC_tRCw, M_MC_tRCw) #define K_MC_tRCw_DEFAULT 10 #define V_MC_tRCw_DEFAULT V_MC_tRCw(K_MC_tRCw_DEFAULT) #define S_MC_tRRD 20 -#define M_MC_tRRD _SB_MAKEMASK(4,S_MC_tRRD) -#define V_MC_tRRD(x) _SB_MAKEVALUE(x,S_MC_tRRD) -#define G_MC_tRRD(x) _SB_GETVALUE(x,S_MC_tRRD,M_MC_tRRD) +#define M_MC_tRRD _SB_MAKEMASK(4, S_MC_tRRD) +#define V_MC_tRRD(x) _SB_MAKEVALUE(x, S_MC_tRRD) +#define G_MC_tRRD(x) _SB_GETVALUE(x, S_MC_tRRD, M_MC_tRRD) #define K_MC_tRRD_DEFAULT 2 #define V_MC_tRRD_DEFAULT V_MC_tRRD(K_MC_tRRD_DEFAULT) #define S_MC_tRP 16 -#define M_MC_tRP _SB_MAKEMASK(4,S_MC_tRP) -#define V_MC_tRP(x) _SB_MAKEVALUE(x,S_MC_tRP) -#define G_MC_tRP(x) _SB_GETVALUE(x,S_MC_tRP,M_MC_tRP) +#define M_MC_tRP _SB_MAKEMASK(4, S_MC_tRP) +#define V_MC_tRP(x) _SB_MAKEVALUE(x, S_MC_tRP) +#define G_MC_tRP(x) _SB_GETVALUE(x, S_MC_tRP, M_MC_tRP) #define K_MC_tRP_DEFAULT 4 #define V_MC_tRP_DEFAULT V_MC_tRP(K_MC_tRP_DEFAULT) #define S_MC_tCwD 8 -#define M_MC_tCwD _SB_MAKEMASK(4,S_MC_tCwD) -#define V_MC_tCwD(x) _SB_MAKEVALUE(x,S_MC_tCwD) -#define G_MC_tCwD(x) _SB_GETVALUE(x,S_MC_tCwD,M_MC_tCwD) +#define M_MC_tCwD _SB_MAKEMASK(4, S_MC_tCwD) +#define V_MC_tCwD(x) _SB_MAKEVALUE(x, S_MC_tCwD) +#define G_MC_tCwD(x) _SB_GETVALUE(x, S_MC_tCwD, M_MC_tCwD) #define K_MC_tCwD_DEFAULT 1 #define V_MC_tCwD_DEFAULT V_MC_tCwD(K_MC_tCwD_DEFAULT) @@ -372,16 +372,16 @@ #define M_MC_tCrDh M_tCrDh #define S_MC_tCrD 4 -#define M_MC_tCrD _SB_MAKEMASK(3,S_MC_tCrD) -#define V_MC_tCrD(x) _SB_MAKEVALUE(x,S_MC_tCrD) -#define G_MC_tCrD(x) _SB_GETVALUE(x,S_MC_tCrD,M_MC_tCrD) +#define M_MC_tCrD _SB_MAKEMASK(3, S_MC_tCrD) +#define V_MC_tCrD(x) _SB_MAKEVALUE(x, S_MC_tCrD) +#define G_MC_tCrD(x) _SB_GETVALUE(x, S_MC_tCrD, M_MC_tCrD) #define K_MC_tCrD_DEFAULT 2 #define V_MC_tCrD_DEFAULT V_MC_tCrD(K_MC_tCrD_DEFAULT) #define S_MC_tRCD 0 -#define M_MC_tRCD _SB_MAKEMASK(4,S_MC_tRCD) -#define V_MC_tRCD(x) _SB_MAKEVALUE(x,S_MC_tRCD) -#define G_MC_tRCD(x) _SB_GETVALUE(x,S_MC_tRCD,M_MC_tRCD) +#define M_MC_tRCD _SB_MAKEMASK(4, S_MC_tRCD) +#define V_MC_tRCD(x) _SB_MAKEVALUE(x, S_MC_tRCD) +#define G_MC_tRCD(x) _SB_GETVALUE(x, S_MC_tRCD, M_MC_tRCD) #define K_MC_tRCD_DEFAULT 3 #define V_MC_tRCD_DEFAULT V_MC_tRCD(K_MC_tRCD_DEFAULT) @@ -409,76 +409,76 @@ */ #define S_MC_CS0_START 0 -#define M_MC_CS0_START _SB_MAKEMASK(16,S_MC_CS0_START) -#define V_MC_CS0_START(x) _SB_MAKEVALUE(x,S_MC_CS0_START) -#define G_MC_CS0_START(x) _SB_GETVALUE(x,S_MC_CS0_START,M_MC_CS0_START) +#define M_MC_CS0_START _SB_MAKEMASK(16, S_MC_CS0_START) +#define V_MC_CS0_START(x) _SB_MAKEVALUE(x, S_MC_CS0_START) +#define G_MC_CS0_START(x) _SB_GETVALUE(x, S_MC_CS0_START, M_MC_CS0_START) #define S_MC_CS1_START 16 -#define M_MC_CS1_START _SB_MAKEMASK(16,S_MC_CS1_START) -#define V_MC_CS1_START(x) _SB_MAKEVALUE(x,S_MC_CS1_START) -#define G_MC_CS1_START(x) _SB_GETVALUE(x,S_MC_CS1_START,M_MC_CS1_START) +#define M_MC_CS1_START _SB_MAKEMASK(16, S_MC_CS1_START) +#define V_MC_CS1_START(x) _SB_MAKEVALUE(x, S_MC_CS1_START) +#define G_MC_CS1_START(x) _SB_GETVALUE(x, S_MC_CS1_START, M_MC_CS1_START) #define S_MC_CS2_START 32 -#define M_MC_CS2_START _SB_MAKEMASK(16,S_MC_CS2_START) -#define V_MC_CS2_START(x) _SB_MAKEVALUE(x,S_MC_CS2_START) -#define G_MC_CS2_START(x) _SB_GETVALUE(x,S_MC_CS2_START,M_MC_CS2_START) +#define M_MC_CS2_START _SB_MAKEMASK(16, S_MC_CS2_START) +#define V_MC_CS2_START(x) _SB_MAKEVALUE(x, S_MC_CS2_START) +#define G_MC_CS2_START(x) _SB_GETVALUE(x, S_MC_CS2_START, M_MC_CS2_START) #define S_MC_CS3_START 48 -#define M_MC_CS3_START _SB_MAKEMASK(16,S_MC_CS3_START) -#define V_MC_CS3_START(x) _SB_MAKEVALUE(x,S_MC_CS3_START) -#define G_MC_CS3_START(x) _SB_GETVALUE(x,S_MC_CS3_START,M_MC_CS3_START) +#define M_MC_CS3_START _SB_MAKEMASK(16, S_MC_CS3_START) +#define V_MC_CS3_START(x) _SB_MAKEVALUE(x, S_MC_CS3_START) +#define G_MC_CS3_START(x) _SB_GETVALUE(x, S_MC_CS3_START, M_MC_CS3_START) /* * Chip Select End Address Register (Table 6-18) */ #define S_MC_CS0_END 0 -#define M_MC_CS0_END _SB_MAKEMASK(16,S_MC_CS0_END) -#define V_MC_CS0_END(x) _SB_MAKEVALUE(x,S_MC_CS0_END) -#define G_MC_CS0_END(x) _SB_GETVALUE(x,S_MC_CS0_END,M_MC_CS0_END) +#define M_MC_CS0_END _SB_MAKEMASK(16, S_MC_CS0_END) +#define V_MC_CS0_END(x) _SB_MAKEVALUE(x, S_MC_CS0_END) +#define G_MC_CS0_END(x) _SB_GETVALUE(x, S_MC_CS0_END, M_MC_CS0_END) #define S_MC_CS1_END 16 -#define M_MC_CS1_END _SB_MAKEMASK(16,S_MC_CS1_END) -#define V_MC_CS1_END(x) _SB_MAKEVALUE(x,S_MC_CS1_END) -#define G_MC_CS1_END(x) _SB_GETVALUE(x,S_MC_CS1_END,M_MC_CS1_END) +#define M_MC_CS1_END _SB_MAKEMASK(16, S_MC_CS1_END) +#define V_MC_CS1_END(x) _SB_MAKEVALUE(x, S_MC_CS1_END) +#define G_MC_CS1_END(x) _SB_GETVALUE(x, S_MC_CS1_END, M_MC_CS1_END) #define S_MC_CS2_END 32 -#define M_MC_CS2_END _SB_MAKEMASK(16,S_MC_CS2_END) -#define V_MC_CS2_END(x) _SB_MAKEVALUE(x,S_MC_CS2_END) -#define G_MC_CS2_END(x) _SB_GETVALUE(x,S_MC_CS2_END,M_MC_CS2_END) +#define M_MC_CS2_END _SB_MAKEMASK(16, S_MC_CS2_END) +#define V_MC_CS2_END(x) _SB_MAKEVALUE(x, S_MC_CS2_END) +#define G_MC_CS2_END(x) _SB_GETVALUE(x, S_MC_CS2_END, M_MC_CS2_END) #define S_MC_CS3_END 48 -#define M_MC_CS3_END _SB_MAKEMASK(16,S_MC_CS3_END) -#define V_MC_CS3_END(x) _SB_MAKEVALUE(x,S_MC_CS3_END) -#define G_MC_CS3_END(x) _SB_GETVALUE(x,S_MC_CS3_END,M_MC_CS3_END) +#define M_MC_CS3_END _SB_MAKEMASK(16, S_MC_CS3_END) +#define V_MC_CS3_END(x) _SB_MAKEVALUE(x, S_MC_CS3_END) +#define G_MC_CS3_END(x) _SB_GETVALUE(x, S_MC_CS3_END, M_MC_CS3_END) /* * Chip Select Interleave Register (Table 6-19) */ #define S_MC_INTLV_RESERVED 0 -#define M_MC_INTLV_RESERVED _SB_MAKEMASK(5,S_MC_INTLV_RESERVED) +#define M_MC_INTLV_RESERVED _SB_MAKEMASK(5, S_MC_INTLV_RESERVED) #define S_MC_INTERLEAVE 7 -#define M_MC_INTERLEAVE _SB_MAKEMASK(18,S_MC_INTERLEAVE) -#define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x,S_MC_INTERLEAVE) +#define M_MC_INTERLEAVE _SB_MAKEMASK(18, S_MC_INTERLEAVE) +#define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x, S_MC_INTERLEAVE) #define S_MC_INTLV_MBZ 25 -#define M_MC_INTLV_MBZ _SB_MAKEMASK(39,S_MC_INTLV_MBZ) +#define M_MC_INTLV_MBZ _SB_MAKEMASK(39, S_MC_INTLV_MBZ) /* * Row Address Bits Register (Table 6-20) */ #define S_MC_RAS_RESERVED 0 -#define M_MC_RAS_RESERVED _SB_MAKEMASK(5,S_MC_RAS_RESERVED) +#define M_MC_RAS_RESERVED _SB_MAKEMASK(5, S_MC_RAS_RESERVED) #define S_MC_RAS_SELECT 12 -#define M_MC_RAS_SELECT _SB_MAKEMASK(25,S_MC_RAS_SELECT) -#define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_RAS_SELECT) +#define M_MC_RAS_SELECT _SB_MAKEMASK(25, S_MC_RAS_SELECT) +#define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_RAS_SELECT) #define S_MC_RAS_MBZ 37 -#define M_MC_RAS_MBZ _SB_MAKEMASK(27,S_MC_RAS_MBZ) +#define M_MC_RAS_MBZ _SB_MAKEMASK(27, S_MC_RAS_MBZ) /* @@ -486,14 +486,14 @@ */ #define S_MC_CAS_RESERVED 0 -#define M_MC_CAS_RESERVED _SB_MAKEMASK(5,S_MC_CAS_RESERVED) +#define M_MC_CAS_RESERVED _SB_MAKEMASK(5, S_MC_CAS_RESERVED) #define S_MC_CAS_SELECT 5 -#define M_MC_CAS_SELECT _SB_MAKEMASK(18,S_MC_CAS_SELECT) -#define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_CAS_SELECT) +#define M_MC_CAS_SELECT _SB_MAKEMASK(18, S_MC_CAS_SELECT) +#define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_CAS_SELECT) #define S_MC_CAS_MBZ 23 -#define M_MC_CAS_MBZ _SB_MAKEMASK(41,S_MC_CAS_MBZ) +#define M_MC_CAS_MBZ _SB_MAKEMASK(41, S_MC_CAS_MBZ) /* @@ -501,14 +501,14 @@ */ #define S_MC_BA_RESERVED 0 -#define M_MC_BA_RESERVED _SB_MAKEMASK(5,S_MC_BA_RESERVED) +#define M_MC_BA_RESERVED _SB_MAKEMASK(5, S_MC_BA_RESERVED) #define S_MC_BA_SELECT 5 -#define M_MC_BA_SELECT _SB_MAKEMASK(20,S_MC_BA_SELECT) -#define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x,S_MC_BA_SELECT) +#define M_MC_BA_SELECT _SB_MAKEMASK(20, S_MC_BA_SELECT) +#define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x, S_MC_BA_SELECT) #define S_MC_BA_MBZ 25 -#define M_MC_BA_MBZ _SB_MAKEMASK(39,S_MC_BA_MBZ) +#define M_MC_BA_MBZ _SB_MAKEMASK(39, S_MC_BA_MBZ) /* * Chip Select Attribute Register (Table 6-23) @@ -520,31 +520,31 @@ #define K_MC_CS_ATTR_OPEN 3 #define S_MC_CS0_PAGE 0 -#define M_MC_CS0_PAGE _SB_MAKEMASK(2,S_MC_CS0_PAGE) -#define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS0_PAGE) -#define G_MC_CS0_PAGE(x) _SB_GETVALUE(x,S_MC_CS0_PAGE,M_MC_CS0_PAGE) +#define M_MC_CS0_PAGE _SB_MAKEMASK(2, S_MC_CS0_PAGE) +#define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS0_PAGE) +#define G_MC_CS0_PAGE(x) _SB_GETVALUE(x, S_MC_CS0_PAGE, M_MC_CS0_PAGE) #define S_MC_CS1_PAGE 16 -#define M_MC_CS1_PAGE _SB_MAKEMASK(2,S_MC_CS1_PAGE) -#define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS1_PAGE) -#define G_MC_CS1_PAGE(x) _SB_GETVALUE(x,S_MC_CS1_PAGE,M_MC_CS1_PAGE) +#define M_MC_CS1_PAGE _SB_MAKEMASK(2, S_MC_CS1_PAGE) +#define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS1_PAGE) +#define G_MC_CS1_PAGE(x) _SB_GETVALUE(x, S_MC_CS1_PAGE, M_MC_CS1_PAGE) #define S_MC_CS2_PAGE 32 -#define M_MC_CS2_PAGE _SB_MAKEMASK(2,S_MC_CS2_PAGE) -#define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS2_PAGE) -#define G_MC_CS2_PAGE(x) _SB_GETVALUE(x,S_MC_CS2_PAGE,M_MC_CS2_PAGE) +#define M_MC_CS2_PAGE _SB_MAKEMASK(2, S_MC_CS2_PAGE) +#define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS2_PAGE) +#define G_MC_CS2_PAGE(x) _SB_GETVALUE(x, S_MC_CS2_PAGE, M_MC_CS2_PAGE) #define S_MC_CS3_PAGE 48 -#define M_MC_CS3_PAGE _SB_MAKEMASK(2,S_MC_CS3_PAGE) -#define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS3_PAGE) -#define G_MC_CS3_PAGE(x) _SB_GETVALUE(x,S_MC_CS3_PAGE,M_MC_CS3_PAGE) +#define M_MC_CS3_PAGE _SB_MAKEMASK(2, S_MC_CS3_PAGE) +#define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS3_PAGE) +#define G_MC_CS3_PAGE(x) _SB_GETVALUE(x, S_MC_CS3_PAGE, M_MC_CS3_PAGE) /* * ECC Test ECC Register (Table 6-25) */ #define S_MC_ECC_INVERT 0 -#define M_MC_ECC_INVERT _SB_MAKEMASK(8,S_MC_ECC_INVERT) +#define M_MC_ECC_INVERT _SB_MAKEMASK(8, S_MC_ECC_INVERT) #endif diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h index 220b7e94f1bf..8f53ec817a5e 100644 --- a/include/asm-mips/sibyte/sb1250_regs.h +++ b/include/asm-mips/sibyte/sb1250_regs.h @@ -66,7 +66,7 @@ #define MC_REGISTER_SPACING 0x1000 #define A_MC_BASE(ctlid) ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0) -#define A_MC_REGISTER(ctlid,reg) (A_MC_BASE(ctlid)+(reg)) +#define A_MC_REGISTER(ctlid, reg) (A_MC_BASE(ctlid)+(reg)) #define R_MC_CONFIG 0x0000000100 #define R_MC_DRAMCMD 0x0000000120 @@ -173,23 +173,23 @@ #define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */ -#define A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) \ +#define A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) \ ((A_MAC_CHANNEL_BASE(macnum)) + \ R_MAC_DMA_CHANNELS + \ (MAC_DMA_TXRX_SPACING*(txrx)) + \ (MAC_DMA_CHANNEL_SPACING*(chan))) -#define R_MAC_DMA_CHANNEL_BASE(txrx,chan) \ +#define R_MAC_DMA_CHANNEL_BASE(txrx, chan) \ (R_MAC_DMA_CHANNELS + \ (MAC_DMA_TXRX_SPACING*(txrx)) + \ (MAC_DMA_CHANNEL_SPACING*(chan))) -#define A_MAC_DMA_REGISTER(macnum,txrx,chan,reg) \ - (A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) + \ +#define A_MAC_DMA_REGISTER(macnum, txrx, chan, reg) \ + (A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) + \ (reg)) -#define R_MAC_DMA_REGISTER(txrx,chan,reg) \ - (R_MAC_DMA_CHANNEL_BASE(txrx,chan) + \ +#define R_MAC_DMA_REGISTER(txrx, chan, reg) \ + (R_MAC_DMA_CHANNEL_BASE(txrx, chan) + \ (reg)) /* @@ -415,8 +415,8 @@ R_SER_DMA_CHANNELS + \ (SER_DMA_TXRX_SPACING*(txrx))) -#define A_SER_DMA_REGISTER(sernum,txrx,reg) \ - (A_SER_DMA_CHANNEL_BASE(sernum,txrx) + \ +#define A_SER_DMA_REGISTER(sernum, txrx, reg) \ + (A_SER_DMA_CHANNEL_BASE(sernum, txrx) + \ (reg)) @@ -499,7 +499,7 @@ #define IO_EXT_REGISTER_SPACING 8 #define A_IO_EXT_CS_BASE(cs) (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs)) -#define R_IO_EXT_REG(reg,cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg)) +#define R_IO_EXT_REG(reg, cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg)) #define R_IO_EXT_CFG 0x0000 #define R_IO_EXT_MULT_SIZE 0x0100 @@ -587,7 +587,7 @@ #define A_SMB_1 0x0010060008 #define SMB_REGISTER_SPACING 0x8 #define A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING) -#define A_SMB_REGISTER(idx,reg) (A_SMB_BASE(idx)+(reg)) +#define A_SMB_REGISTER(idx, reg) (A_SMB_BASE(idx)+(reg)) #define R_SMB_XTRA 0x0000000000 #define R_SMB_FREQ 0x0000000010 @@ -611,7 +611,7 @@ #define SCD_WDOG_SPACING 0x100 #define SCD_NUM_WDOGS 2 #define A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w)) -#define A_SCD_WDOG_REGISTER(w,r) (A_SCD_WDOG_BASE(w) + (r)) +#define A_SCD_WDOG_REGISTER(w, r) (A_SCD_WDOG_BASE(w) + (r)) #define R_SCD_WDOG_INIT 0x0000000000 #define R_SCD_WDOG_CNT 0x0000000008 @@ -635,7 +635,7 @@ #define A_SCD_TIMER_3 0x0010020178 #define SCD_NUM_TIMERS 4 #define A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1)) -#define A_SCD_TIMER_REGISTER(w,r) (A_SCD_TIMER_BASE(w) + (r)) +#define A_SCD_TIMER_REGISTER(w, r) (A_SCD_TIMER_BASE(w) + (r)) #define R_SCD_TIMER_INIT 0x0000000000 #define R_SCD_TIMER_CNT 0x0000000010 @@ -714,7 +714,7 @@ #define IMR_REGISTER_SPACING_SHIFT 13 #define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING) -#define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg)) +#define A_IMR_REGISTER(cpu, reg) (A_IMR_MAPPER(cpu)+(reg)) #define R_IMR_INTERRUPT_DIAG 0x0010 #define R_IMR_INTERRUPT_LDT 0x0018 @@ -821,7 +821,7 @@ #define DM_REGISTER_SPACING 0x20 #define DM_NUM_CHANNELS 4 #define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING)) -#define A_DM_REGISTER(idx,reg) (A_DM_BASE(idx) + (reg)) +#define A_DM_REGISTER(idx, reg) (A_DM_BASE(idx) + (reg)) #define R_DM_DSCR_BASE 0x0000000000 #define R_DM_DSCR_COUNT 0x0000000008 @@ -843,7 +843,7 @@ #define DM_CRC_REGISTER_SPACING 0x10 #define DM_CRC_NUM_CHANNELS 2 #define A_DM_CRC_BASE(idx) (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING)) -#define A_DM_CRC_REGISTER(idx,reg) (A_DM_CRC_BASE(idx) + (reg)) +#define A_DM_CRC_REGISTER(idx, reg) (A_DM_CRC_BASE(idx) + (reg)) #define R_CRC_DEF_0 0x00 #define R_CTCP_DEF_0 0x08 diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h index 9ea3da367ab6..e49c3e89b5ee 100644 --- a/include/asm-mips/sibyte/sb1250_scd.h +++ b/include/asm-mips/sibyte/sb1250_scd.h @@ -42,12 +42,12 @@ * System Revision Register (Table 4-1) */ -#define M_SYS_RESERVED _SB_MAKEMASK(8,0) +#define M_SYS_RESERVED _SB_MAKEMASK(8, 0) #define S_SYS_REVISION _SB_MAKE64(8) -#define M_SYS_REVISION _SB_MAKEMASK(8,S_SYS_REVISION) -#define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION) -#define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION) +#define M_SYS_REVISION _SB_MAKEMASK(8, S_SYS_REVISION) +#define V_SYS_REVISION(x) _SB_MAKEVALUE(x, S_SYS_REVISION) +#define G_SYS_REVISION(x) _SB_GETVALUE(x, S_SYS_REVISION, M_SYS_REVISION) #define K_SYS_REVISION_BCM1250_PASS1 0x01 @@ -94,9 +94,9 @@ /*Cache size - 23:20 of revision register*/ #define S_SYS_L2C_SIZE _SB_MAKE64(20) -#define M_SYS_L2C_SIZE _SB_MAKEMASK(4,S_SYS_L2C_SIZE) -#define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x,S_SYS_L2C_SIZE) -#define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x,S_SYS_L2C_SIZE,M_SYS_L2C_SIZE) +#define M_SYS_L2C_SIZE _SB_MAKEMASK(4, S_SYS_L2C_SIZE) +#define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x, S_SYS_L2C_SIZE) +#define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x, S_SYS_L2C_SIZE, M_SYS_L2C_SIZE) #define K_SYS_L2C_SIZE_1MB 0 #define K_SYS_L2C_SIZE_512KB 5 @@ -110,16 +110,16 @@ /* Number of CPU cores, bits 27:24 of revision register*/ #define S_SYS_NUM_CPUS _SB_MAKE64(24) -#define M_SYS_NUM_CPUS _SB_MAKEMASK(4,S_SYS_NUM_CPUS) -#define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x,S_SYS_NUM_CPUS) -#define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x,S_SYS_NUM_CPUS,M_SYS_NUM_CPUS) +#define M_SYS_NUM_CPUS _SB_MAKEMASK(4, S_SYS_NUM_CPUS) +#define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x, S_SYS_NUM_CPUS) +#define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x, S_SYS_NUM_CPUS, M_SYS_NUM_CPUS) /* XXX: discourage people from using these constants. */ #define S_SYS_PART _SB_MAKE64(16) -#define M_SYS_PART _SB_MAKEMASK(16,S_SYS_PART) -#define V_SYS_PART(x) _SB_MAKEVALUE(x,S_SYS_PART) -#define G_SYS_PART(x) _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART) +#define M_SYS_PART _SB_MAKEMASK(16, S_SYS_PART) +#define V_SYS_PART(x) _SB_MAKEVALUE(x, S_SYS_PART) +#define G_SYS_PART(x) _SB_GETVALUE(x, S_SYS_PART, M_SYS_PART) /* XXX: discourage people from using these constants. */ #define K_SYS_PART_SB1250 0x1250 @@ -131,9 +131,9 @@ /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ #define S_SYS_SOC_TYPE _SB_MAKE64(16) -#define M_SYS_SOC_TYPE _SB_MAKEMASK(4,S_SYS_SOC_TYPE) -#define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x,S_SYS_SOC_TYPE) -#define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x,S_SYS_SOC_TYPE,M_SYS_SOC_TYPE) +#define M_SYS_SOC_TYPE _SB_MAKEMASK(4, S_SYS_SOC_TYPE) +#define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x, S_SYS_SOC_TYPE) +#define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x, S_SYS_SOC_TYPE, M_SYS_SOC_TYPE) #define K_SYS_SOC_TYPE_BCM1250 0x0 #define K_SYS_SOC_TYPE_BCM1120 0x1 @@ -170,9 +170,9 @@ #endif #define S_SYS_WID _SB_MAKE64(32) -#define M_SYS_WID _SB_MAKEMASK(32,S_SYS_WID) -#define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID) -#define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID) +#define M_SYS_WID _SB_MAKEMASK(32, S_SYS_WID) +#define V_SYS_WID(x) _SB_MAKEVALUE(x, S_SYS_WID) +#define G_SYS_WID(x) _SB_GETVALUE(x, S_SYS_WID, M_SYS_WID) /* * System Manufacturing Register @@ -182,36 +182,36 @@ #if SIBYTE_HDR_FEATURE_1250_112x /* Wafer ID: bits 31:0 */ #define S_SYS_WAFERID1_200 _SB_MAKE64(0) -#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200) -#define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID1_200) -#define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200) +#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32, S_SYS_WAFERID1_200) +#define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x, S_SYS_WAFERID1_200) +#define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x, S_SYS_WAFERID1_200, M_SYS_WAFERID1_200) #define S_SYS_BIN _SB_MAKE64(32) -#define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN) -#define V_SYS_BIN(x) _SB_MAKEVALUE(x,S_SYS_BIN) -#define G_SYS_BIN(x) _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) +#define M_SYS_BIN _SB_MAKEMASK(4, S_SYS_BIN) +#define V_SYS_BIN(x) _SB_MAKEVALUE(x, S_SYS_BIN) +#define G_SYS_BIN(x) _SB_GETVALUE(x, S_SYS_BIN, M_SYS_BIN) /* Wafer ID: bits 39:36 */ #define S_SYS_WAFERID2_200 _SB_MAKE64(36) -#define M_SYS_WAFERID2_200 _SB_MAKEMASK(4,S_SYS_WAFERID2_200) -#define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID2_200) -#define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200) +#define M_SYS_WAFERID2_200 _SB_MAKEMASK(4, S_SYS_WAFERID2_200) +#define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x, S_SYS_WAFERID2_200) +#define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x, S_SYS_WAFERID2_200, M_SYS_WAFERID2_200) /* Wafer ID: bits 39:0 */ #define S_SYS_WAFERID_300 _SB_MAKE64(0) -#define M_SYS_WAFERID_300 _SB_MAKEMASK(40,S_SYS_WAFERID_300) -#define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x,S_SYS_WAFERID_300) -#define G_SYS_WAFERID_300(x) _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300) +#define M_SYS_WAFERID_300 _SB_MAKEMASK(40, S_SYS_WAFERID_300) +#define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x, S_SYS_WAFERID_300) +#define G_SYS_WAFERID_300(x) _SB_GETVALUE(x, S_SYS_WAFERID_300, M_SYS_WAFERID_300) #define S_SYS_XPOS _SB_MAKE64(40) -#define M_SYS_XPOS _SB_MAKEMASK(6,S_SYS_XPOS) -#define V_SYS_XPOS(x) _SB_MAKEVALUE(x,S_SYS_XPOS) -#define G_SYS_XPOS(x) _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS) +#define M_SYS_XPOS _SB_MAKEMASK(6, S_SYS_XPOS) +#define V_SYS_XPOS(x) _SB_MAKEVALUE(x, S_SYS_XPOS) +#define G_SYS_XPOS(x) _SB_GETVALUE(x, S_SYS_XPOS, M_SYS_XPOS) #define S_SYS_YPOS _SB_MAKE64(46) -#define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS) -#define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS) -#define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) +#define M_SYS_YPOS _SB_MAKEMASK(6, S_SYS_YPOS) +#define V_SYS_YPOS(x) _SB_MAKEVALUE(x, S_SYS_YPOS) +#define G_SYS_YPOS(x) _SB_GETVALUE(x, S_SYS_YPOS, M_SYS_YPOS) #endif @@ -227,9 +227,9 @@ #define M_SYS_IOB1_DIV _SB_MAKEMASK1(6) #define S_SYS_PLL_DIV _SB_MAKE64(7) -#define M_SYS_PLL_DIV _SB_MAKEMASK(5,S_SYS_PLL_DIV) -#define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_SYS_PLL_DIV) -#define G_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV) +#define M_SYS_PLL_DIV _SB_MAKEMASK(5, S_SYS_PLL_DIV) +#define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_SYS_PLL_DIV) +#define G_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_SYS_PLL_DIV, M_SYS_PLL_DIV) #define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12) #define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13) @@ -238,9 +238,9 @@ #define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) #define S_SYS_BOOT_MODE _SB_MAKE64(17) -#define M_SYS_BOOT_MODE _SB_MAKEMASK(2,S_SYS_BOOT_MODE) -#define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_SYS_BOOT_MODE) -#define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE) +#define M_SYS_BOOT_MODE _SB_MAKEMASK(2, S_SYS_BOOT_MODE) +#define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_SYS_BOOT_MODE) +#define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_SYS_BOOT_MODE, M_SYS_BOOT_MODE) #define K_SYS_BOOT_MODE_ROM32 0 #define K_SYS_BOOT_MODE_ROM8 1 #define K_SYS_BOOT_MODE_SMBUS_SMALL 2 @@ -255,9 +255,9 @@ #define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25) #define S_SYS_CONFIG 26 -#define M_SYS_CONFIG _SB_MAKEMASK(6,S_SYS_CONFIG) -#define V_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_SYS_CONFIG) -#define G_SYS_CONFIG(x) _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG) +#define M_SYS_CONFIG _SB_MAKEMASK(6, S_SYS_CONFIG) +#define V_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_SYS_CONFIG) +#define G_SYS_CONFIG(x) _SB_GETVALUE(x, S_SYS_CONFIG, M_SYS_CONFIG) /* The following bits are writeable by JTAG only. */ @@ -265,20 +265,20 @@ #define M_SYS_CLKSTEP _SB_MAKEMASK1(33) #define S_SYS_CLKCOUNT 34 -#define M_SYS_CLKCOUNT _SB_MAKEMASK(8,S_SYS_CLKCOUNT) -#define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x,S_SYS_CLKCOUNT) -#define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT) +#define M_SYS_CLKCOUNT _SB_MAKEMASK(8, S_SYS_CLKCOUNT) +#define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x, S_SYS_CLKCOUNT) +#define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x, S_SYS_CLKCOUNT, M_SYS_CLKCOUNT) #define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42) #define S_SYS_PLL_IREF 43 -#define M_SYS_PLL_IREF _SB_MAKEMASK(2,S_SYS_PLL_IREF) +#define M_SYS_PLL_IREF _SB_MAKEMASK(2, S_SYS_PLL_IREF) #define S_SYS_PLL_VCO 45 -#define M_SYS_PLL_VCO _SB_MAKEMASK(2,S_SYS_PLL_VCO) +#define M_SYS_PLL_VCO _SB_MAKEMASK(2, S_SYS_PLL_VCO) #define S_SYS_PLL_VREG 47 -#define M_SYS_PLL_VREG _SB_MAKEMASK(2,S_SYS_PLL_VREG) +#define M_SYS_PLL_VREG _SB_MAKEMASK(2, S_SYS_PLL_VREG) #define M_SYS_MEM_RESET _SB_MAKEMASK1(49) #define M_SYS_L2C_RESET _SB_MAKEMASK1(50) @@ -314,13 +314,13 @@ */ #define S_MBOX_INT_3 0 -#define M_MBOX_INT_3 _SB_MAKEMASK(16,S_MBOX_INT_3) +#define M_MBOX_INT_3 _SB_MAKEMASK(16, S_MBOX_INT_3) #define S_MBOX_INT_2 16 -#define M_MBOX_INT_2 _SB_MAKEMASK(16,S_MBOX_INT_2) +#define M_MBOX_INT_2 _SB_MAKEMASK(16, S_MBOX_INT_2) #define S_MBOX_INT_1 32 -#define M_MBOX_INT_1 _SB_MAKEMASK(16,S_MBOX_INT_1) +#define M_MBOX_INT_1 _SB_MAKEMASK(16, S_MBOX_INT_1) #define S_MBOX_INT_0 48 -#define M_MBOX_INT_0 _SB_MAKEMASK(16,S_MBOX_INT_0) +#define M_MBOX_INT_0 _SB_MAKEMASK(16, S_MBOX_INT_0) /* * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10) @@ -330,18 +330,18 @@ #define V_SCD_WDOG_FREQ 1000000 #define S_SCD_WDOG_INIT 0 -#define M_SCD_WDOG_INIT _SB_MAKEMASK(23,S_SCD_WDOG_INIT) +#define M_SCD_WDOG_INIT _SB_MAKEMASK(23, S_SCD_WDOG_INIT) #define S_SCD_WDOG_CNT 0 -#define M_SCD_WDOG_CNT _SB_MAKEMASK(23,S_SCD_WDOG_CNT) +#define M_SCD_WDOG_CNT _SB_MAKEMASK(23, S_SCD_WDOG_CNT) #define S_SCD_WDOG_ENABLE 0 #define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE) #define S_SCD_WDOG_RESET_TYPE 2 -#define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3,S_SCD_WDOG_RESET_TYPE) -#define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_SCD_WDOG_RESET_TYPE) -#define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_SCD_WDOG_RESET_TYPE,M_SCD_WDOG_RESET_TYPE) +#define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3, S_SCD_WDOG_RESET_TYPE) +#define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_SCD_WDOG_RESET_TYPE) +#define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_SCD_WDOG_RESET_TYPE, M_SCD_WDOG_RESET_TYPE) #define K_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ #define K_SCD_WDOG_RESET_SOFT 1 @@ -363,15 +363,15 @@ #define V_SCD_TIMER_FREQ 1000000 #define S_SCD_TIMER_INIT 0 -#define M_SCD_TIMER_INIT _SB_MAKEMASK(23,S_SCD_TIMER_INIT) -#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT) -#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT) +#define M_SCD_TIMER_INIT _SB_MAKEMASK(23, S_SCD_TIMER_INIT) +#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x, S_SCD_TIMER_INIT) +#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x, S_SCD_TIMER_INIT, M_SCD_TIMER_INIT) #define V_SCD_TIMER_WIDTH 23 #define S_SCD_TIMER_CNT 0 -#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_CNT) -#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT) -#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT) +#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH, S_SCD_TIMER_CNT) +#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x, S_SCD_TIMER_CNT) +#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x, S_SCD_TIMER_CNT, M_SCD_TIMER_CNT) #define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0) #define M_SCD_TIMER_MODE _SB_MAKEMASK1(1) @@ -382,24 +382,24 @@ */ #define S_SPC_CFG_SRC0 0 -#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) -#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) -#define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_SPC_CFG_SRC0,M_SPC_CFG_SRC0) +#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8, S_SPC_CFG_SRC0) +#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC0) +#define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x, S_SPC_CFG_SRC0, M_SPC_CFG_SRC0) #define S_SPC_CFG_SRC1 8 -#define M_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_SPC_CFG_SRC1) -#define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC1) -#define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_SPC_CFG_SRC1,M_SPC_CFG_SRC1) +#define M_SPC_CFG_SRC1 _SB_MAKEMASK(8, S_SPC_CFG_SRC1) +#define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC1) +#define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x, S_SPC_CFG_SRC1, M_SPC_CFG_SRC1) #define S_SPC_CFG_SRC2 16 -#define M_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_SPC_CFG_SRC2) -#define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC2) -#define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_SPC_CFG_SRC2,M_SPC_CFG_SRC2) +#define M_SPC_CFG_SRC2 _SB_MAKEMASK(8, S_SPC_CFG_SRC2) +#define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC2) +#define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x, S_SPC_CFG_SRC2, M_SPC_CFG_SRC2) #define S_SPC_CFG_SRC3 24 -#define M_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_SPC_CFG_SRC3) -#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3) -#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3) +#define M_SPC_CFG_SRC3 _SB_MAKEMASK(8, S_SPC_CFG_SRC3) +#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC3) +#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x, S_SPC_CFG_SRC3, M_SPC_CFG_SRC3) #if SIBYTE_HDR_FEATURE_1250_112x #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) @@ -412,57 +412,57 @@ */ #define S_SCD_BERR_TID 8 -#define M_SCD_BERR_TID _SB_MAKEMASK(10,S_SCD_BERR_TID) -#define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x,S_SCD_BERR_TID) -#define G_SCD_BERR_TID(x) _SB_GETVALUE(x,S_SCD_BERR_TID,M_SCD_BERR_TID) +#define M_SCD_BERR_TID _SB_MAKEMASK(10, S_SCD_BERR_TID) +#define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x, S_SCD_BERR_TID) +#define G_SCD_BERR_TID(x) _SB_GETVALUE(x, S_SCD_BERR_TID, M_SCD_BERR_TID) #define S_SCD_BERR_RID 18 -#define M_SCD_BERR_RID _SB_MAKEMASK(4,S_SCD_BERR_RID) -#define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x,S_SCD_BERR_RID) -#define G_SCD_BERR_RID(x) _SB_GETVALUE(x,S_SCD_BERR_RID,M_SCD_BERR_RID) +#define M_SCD_BERR_RID _SB_MAKEMASK(4, S_SCD_BERR_RID) +#define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x, S_SCD_BERR_RID) +#define G_SCD_BERR_RID(x) _SB_GETVALUE(x, S_SCD_BERR_RID, M_SCD_BERR_RID) #define S_SCD_BERR_DCODE 22 -#define M_SCD_BERR_DCODE _SB_MAKEMASK(3,S_SCD_BERR_DCODE) -#define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x,S_SCD_BERR_DCODE) -#define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE) +#define M_SCD_BERR_DCODE _SB_MAKEMASK(3, S_SCD_BERR_DCODE) +#define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x, S_SCD_BERR_DCODE) +#define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x, S_SCD_BERR_DCODE, M_SCD_BERR_DCODE) #define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30) #define S_SCD_L2ECC_CORR_D 0 -#define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D) -#define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D) -#define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D) +#define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_D) +#define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_D) +#define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x, S_SCD_L2ECC_CORR_D, M_SCD_L2ECC_CORR_D) #define S_SCD_L2ECC_BAD_D 8 -#define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D) -#define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D) -#define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D) +#define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_D) +#define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_D) +#define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x, S_SCD_L2ECC_BAD_D, M_SCD_L2ECC_BAD_D) #define S_SCD_L2ECC_CORR_T 16 -#define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T) -#define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T) -#define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T) +#define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_T) +#define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_T) +#define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x, S_SCD_L2ECC_CORR_T, M_SCD_L2ECC_CORR_T) #define S_SCD_L2ECC_BAD_T 24 -#define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T) -#define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T) -#define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T) +#define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_T) +#define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_T) +#define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x, S_SCD_L2ECC_BAD_T, M_SCD_L2ECC_BAD_T) #define S_SCD_MEM_ECC_CORR 0 -#define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR) -#define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR) -#define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR) +#define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8, S_SCD_MEM_ECC_CORR) +#define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x, S_SCD_MEM_ECC_CORR) +#define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x, S_SCD_MEM_ECC_CORR, M_SCD_MEM_ECC_CORR) #define S_SCD_MEM_ECC_BAD 8 -#define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD) -#define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD) -#define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD) +#define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8, S_SCD_MEM_ECC_BAD) +#define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x, S_SCD_MEM_ECC_BAD) +#define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x, S_SCD_MEM_ECC_BAD, M_SCD_MEM_ECC_BAD) #define S_SCD_MEM_BUSERR 16 -#define M_SCD_MEM_BUSERR _SB_MAKEMASK(8,S_SCD_MEM_BUSERR) -#define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR) -#define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR) +#define M_SCD_MEM_BUSERR _SB_MAKEMASK(8, S_SCD_MEM_BUSERR) +#define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x, S_SCD_MEM_BUSERR) +#define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x, S_SCD_MEM_BUSERR, M_SCD_MEM_BUSERR) /* @@ -470,13 +470,13 @@ */ #if SIBYTE_HDR_FEATURE_1250_112x -#define M_ATRAP_INDEX _SB_MAKEMASK(4,0) -#define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0) +#define M_ATRAP_INDEX _SB_MAKEMASK(4, 0) +#define M_ATRAP_ADDRESS _SB_MAKEMASK(40, 0) #define S_ATRAP_CFG_CNT 0 -#define M_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_ATRAP_CFG_CNT) -#define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CNT) -#define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_ATRAP_CFG_CNT,M_ATRAP_CFG_CNT) +#define M_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_ATRAP_CFG_CNT) +#define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_CNT) +#define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_ATRAP_CFG_CNT, M_ATRAP_CFG_CNT) #define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) #define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4) @@ -485,9 +485,9 @@ #define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) #define S_ATRAP_CFG_AGENTID 8 -#define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_ATRAP_CFG_AGENTID) -#define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_AGENTID) -#define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_ATRAP_CFG_AGENTID,M_ATRAP_CFG_AGENTID) +#define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_ATRAP_CFG_AGENTID) +#define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_AGENTID) +#define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_ATRAP_CFG_AGENTID, M_ATRAP_CFG_AGENTID) #define K_BUS_AGENT_CPU0 0 #define K_BUS_AGENT_CPU1 1 @@ -498,9 +498,9 @@ #define K_BUS_AGENT_MC 7 #define S_ATRAP_CFG_CATTR 12 -#define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3,S_ATRAP_CFG_CATTR) -#define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CATTR) -#define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_ATRAP_CFG_CATTR,M_ATRAP_CFG_CATTR) +#define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3, S_ATRAP_CFG_CATTR) +#define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_CATTR) +#define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_ATRAP_CFG_CATTR, M_ATRAP_CFG_CATTR) #define K_ATRAP_CFG_CATTR_IGNORE 0 #define K_ATRAP_CFG_CATTR_UNC 1 @@ -541,18 +541,18 @@ #endif /* 1480 */ #endif /* 1250/112x */ -#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR) -#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) -#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) +#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8, S_SCD_TRACE_CFG_CUR_ADDR) +#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR) +#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR, M_SCD_TRACE_CFG_CUR_ADDR) /* * Trace Event registers */ #define S_SCD_TREVT_ADDR_MATCH 0 -#define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4,S_SCD_TREVT_ADDR_MATCH) -#define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x,S_SCD_TREVT_ADDR_MATCH) -#define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x,S_SCD_TREVT_ADDR_MATCH,M_SCD_TREVT_ADDR_MATCH) +#define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4, S_SCD_TREVT_ADDR_MATCH) +#define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x, S_SCD_TREVT_ADDR_MATCH) +#define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x, S_SCD_TREVT_ADDR_MATCH, M_SCD_TREVT_ADDR_MATCH) #define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4) #define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5) @@ -563,48 +563,48 @@ #define M_SCD_TREVT_READ _SB_MAKEMASK1(11) #define S_SCD_TREVT_REQID 12 -#define M_SCD_TREVT_REQID _SB_MAKEMASK(4,S_SCD_TREVT_REQID) -#define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_REQID) -#define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x,S_SCD_TREVT_REQID,M_SCD_TREVT_REQID) +#define M_SCD_TREVT_REQID _SB_MAKEMASK(4, S_SCD_TREVT_REQID) +#define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_REQID) +#define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x, S_SCD_TREVT_REQID, M_SCD_TREVT_REQID) #define S_SCD_TREVT_RESPID 16 -#define M_SCD_TREVT_RESPID _SB_MAKEMASK(4,S_SCD_TREVT_RESPID) -#define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_RESPID) -#define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x,S_SCD_TREVT_RESPID,M_SCD_TREVT_RESPID) +#define M_SCD_TREVT_RESPID _SB_MAKEMASK(4, S_SCD_TREVT_RESPID) +#define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_RESPID) +#define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x, S_SCD_TREVT_RESPID, M_SCD_TREVT_RESPID) #define S_SCD_TREVT_DATAID 20 -#define M_SCD_TREVT_DATAID _SB_MAKEMASK(4,S_SCD_TREVT_DATAID) -#define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_DATAID) -#define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x,S_SCD_TREVT_DATAID,M_SCD_TREVT_DATID) +#define M_SCD_TREVT_DATAID _SB_MAKEMASK(4, S_SCD_TREVT_DATAID) +#define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_DATAID) +#define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x, S_SCD_TREVT_DATAID, M_SCD_TREVT_DATID) #define S_SCD_TREVT_COUNT 24 -#define M_SCD_TREVT_COUNT _SB_MAKEMASK(8,S_SCD_TREVT_COUNT) -#define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x,S_SCD_TREVT_COUNT) -#define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x,S_SCD_TREVT_COUNT,M_SCD_TREVT_COUNT) +#define M_SCD_TREVT_COUNT _SB_MAKEMASK(8, S_SCD_TREVT_COUNT) +#define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x, S_SCD_TREVT_COUNT) +#define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x, S_SCD_TREVT_COUNT, M_SCD_TREVT_COUNT) /* * Trace Sequence registers */ #define S_SCD_TRSEQ_EVENT4 0 -#define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT4) -#define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT4) -#define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT4,M_SCD_TRSEQ_EVENT4) +#define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT4) +#define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT4) +#define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT4, M_SCD_TRSEQ_EVENT4) #define S_SCD_TRSEQ_EVENT3 4 -#define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT3) -#define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT3) -#define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT3,M_SCD_TRSEQ_EVENT3) +#define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT3) +#define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT3) +#define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT3, M_SCD_TRSEQ_EVENT3) #define S_SCD_TRSEQ_EVENT2 8 -#define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT2) -#define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT2) -#define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT2,M_SCD_TRSEQ_EVENT2) +#define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT2) +#define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT2) +#define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT2, M_SCD_TRSEQ_EVENT2) #define S_SCD_TRSEQ_EVENT1 12 -#define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT1) -#define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT1) -#define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT1,M_SCD_TRSEQ_EVENT1) +#define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT1) +#define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT1) +#define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT1, M_SCD_TRSEQ_EVENT1) #define K_SCD_TRSEQ_E0 0 #define K_SCD_TRSEQ_E1 1 @@ -629,9 +629,9 @@ V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED)) #define S_SCD_TRSEQ_FUNCTION 16 -#define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4,S_SCD_TRSEQ_FUNCTION) -#define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_FUNCTION) -#define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x,S_SCD_TRSEQ_FUNCTION,M_SCD_TRSEQ_FUNCTION) +#define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4, S_SCD_TRSEQ_FUNCTION) +#define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_FUNCTION) +#define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x, S_SCD_TRSEQ_FUNCTION, M_SCD_TRSEQ_FUNCTION) #define K_SCD_TRSEQ_FUNC_NOP 0 #define K_SCD_TRSEQ_FUNC_START 1 diff --git a/include/asm-mips/sibyte/sb1250_smbus.h b/include/asm-mips/sibyte/sb1250_smbus.h index 279a912213cd..04769923cf1e 100644 --- a/include/asm-mips/sibyte/sb1250_smbus.h +++ b/include/asm-mips/sibyte/sb1250_smbus.h @@ -41,16 +41,16 @@ */ #define S_SMB_FREQ_DIV 0 -#define M_SMB_FREQ_DIV _SB_MAKEMASK(13,S_SMB_FREQ_DIV) -#define V_SMB_FREQ_DIV(x) _SB_MAKEVALUE(x,S_SMB_FREQ_DIV) +#define M_SMB_FREQ_DIV _SB_MAKEMASK(13, S_SMB_FREQ_DIV) +#define V_SMB_FREQ_DIV(x) _SB_MAKEVALUE(x, S_SMB_FREQ_DIV) #define K_SMB_FREQ_400KHZ 0x1F #define K_SMB_FREQ_100KHZ 0x7D #define K_SMB_FREQ_10KHZ 1250 #define S_SMB_CMD 0 -#define M_SMB_CMD _SB_MAKEMASK(8,S_SMB_CMD) -#define V_SMB_CMD(x) _SB_MAKEVALUE(x,S_SMB_CMD) +#define M_SMB_CMD _SB_MAKEMASK(8, S_SMB_CMD) +#define V_SMB_CMD(x) _SB_MAKEVALUE(x, S_SMB_CMD) /* * SMBus control register (Table 14-4) @@ -61,7 +61,7 @@ #define S_SMB_DATA_OUT 4 #define M_SMB_DATA_OUT _SB_MAKEMASK1(S_SMB_DATA_OUT) -#define V_SMB_DATA_OUT(x) _SB_MAKEVALUE(x,S_SMB_DATA_OUT) +#define V_SMB_DATA_OUT(x) _SB_MAKEVALUE(x, S_SMB_DATA_OUT) #define M_SMB_DATA_DIR _SB_MAKEMASK1(5) #define M_SMB_DATA_DIR_OUTPUT M_SMB_DATA_DIR @@ -79,35 +79,35 @@ #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_SMB_SCL_IN 5 #define M_SMB_SCL_IN _SB_MAKEMASK1(S_SMB_SCL_IN) -#define V_SMB_SCL_IN(x) _SB_MAKEVALUE(x,S_SMB_SCL_IN) -#define G_SMB_SCL_IN(x) _SB_GETVALUE(x,S_SMB_SCL_IN,M_SMB_SCL_IN) +#define V_SMB_SCL_IN(x) _SB_MAKEVALUE(x, S_SMB_SCL_IN) +#define G_SMB_SCL_IN(x) _SB_GETVALUE(x, S_SMB_SCL_IN, M_SMB_SCL_IN) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define S_SMB_REF 6 #define M_SMB_REF _SB_MAKEMASK1(S_SMB_REF) -#define V_SMB_REF(x) _SB_MAKEVALUE(x,S_SMB_REF) -#define G_SMB_REF(x) _SB_GETVALUE(x,S_SMB_REF,M_SMB_REF) +#define V_SMB_REF(x) _SB_MAKEVALUE(x, S_SMB_REF) +#define G_SMB_REF(x) _SB_GETVALUE(x, S_SMB_REF, M_SMB_REF) #define S_SMB_DATA_IN 7 #define M_SMB_DATA_IN _SB_MAKEMASK1(S_SMB_DATA_IN) -#define V_SMB_DATA_IN(x) _SB_MAKEVALUE(x,S_SMB_DATA_IN) -#define G_SMB_DATA_IN(x) _SB_GETVALUE(x,S_SMB_DATA_IN,M_SMB_DATA_IN) +#define V_SMB_DATA_IN(x) _SB_MAKEVALUE(x, S_SMB_DATA_IN) +#define G_SMB_DATA_IN(x) _SB_GETVALUE(x, S_SMB_DATA_IN, M_SMB_DATA_IN) /* * SMBus Start/Command registers (Table 14-9) */ #define S_SMB_ADDR 0 -#define M_SMB_ADDR _SB_MAKEMASK(7,S_SMB_ADDR) -#define V_SMB_ADDR(x) _SB_MAKEVALUE(x,S_SMB_ADDR) -#define G_SMB_ADDR(x) _SB_GETVALUE(x,S_SMB_ADDR,M_SMB_ADDR) +#define M_SMB_ADDR _SB_MAKEMASK(7, S_SMB_ADDR) +#define V_SMB_ADDR(x) _SB_MAKEVALUE(x, S_SMB_ADDR) +#define G_SMB_ADDR(x) _SB_GETVALUE(x, S_SMB_ADDR, M_SMB_ADDR) #define M_SMB_QDATA _SB_MAKEMASK1(7) #define S_SMB_TT 8 -#define M_SMB_TT _SB_MAKEMASK(3,S_SMB_TT) -#define V_SMB_TT(x) _SB_MAKEVALUE(x,S_SMB_TT) -#define G_SMB_TT(x) _SB_GETVALUE(x,S_SMB_TT,M_SMB_TT) +#define M_SMB_TT _SB_MAKEMASK(3, S_SMB_TT) +#define V_SMB_TT(x) _SB_MAKEVALUE(x, S_SMB_TT) +#define G_SMB_TT(x) _SB_GETVALUE(x, S_SMB_TT, M_SMB_TT) #define K_SMB_TT_WR1BYTE 0 #define K_SMB_TT_WR2BYTE 1 @@ -134,12 +134,12 @@ */ #define S_SMB_LB 0 -#define M_SMB_LB _SB_MAKEMASK(8,S_SMB_LB) -#define V_SMB_LB(x) _SB_MAKEVALUE(x,S_SMB_LB) +#define M_SMB_LB _SB_MAKEMASK(8, S_SMB_LB) +#define V_SMB_LB(x) _SB_MAKEVALUE(x, S_SMB_LB) #define S_SMB_MB 8 -#define M_SMB_MB _SB_MAKEMASK(8,S_SMB_MB) -#define V_SMB_MB(x) _SB_MAKEVALUE(x,S_SMB_MB) +#define M_SMB_MB _SB_MAKEMASK(8, S_SMB_MB) +#define V_SMB_MB(x) _SB_MAKEVALUE(x, S_SMB_MB) /* @@ -147,22 +147,22 @@ */ #define S_SPEC_PEC 0 -#define M_SPEC_PEC _SB_MAKEMASK(8,S_SPEC_PEC) -#define V_SPEC_MB(x) _SB_MAKEVALUE(x,S_SPEC_PEC) +#define M_SPEC_PEC _SB_MAKEMASK(8, S_SPEC_PEC) +#define V_SPEC_MB(x) _SB_MAKEVALUE(x, S_SPEC_PEC) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_SMB_CMDH 8 -#define M_SMB_CMDH _SB_MAKEMASK(8,S_SMB_CMDH) -#define V_SMB_CMDH(x) _SB_MAKEVALUE(x,S_SMB_CMDH) +#define M_SMB_CMDH _SB_MAKEMASK(8, S_SMB_CMDH) +#define V_SMB_CMDH(x) _SB_MAKEVALUE(x, S_SMB_CMDH) #define M_SMB_EXTEND _SB_MAKEMASK1(14) #define S_SMB_DFMT 8 -#define M_SMB_DFMT _SB_MAKEMASK(3,S_SMB_DFMT) -#define V_SMB_DFMT(x) _SB_MAKEVALUE(x,S_SMB_DFMT) -#define G_SMB_DFMT(x) _SB_GETVALUE(x,S_SMB_DFMT,M_SMB_DFMT) +#define M_SMB_DFMT _SB_MAKEMASK(3, S_SMB_DFMT) +#define V_SMB_DFMT(x) _SB_MAKEVALUE(x, S_SMB_DFMT) +#define G_SMB_DFMT(x) _SB_GETVALUE(x, S_SMB_DFMT, M_SMB_DFMT) #define K_SMB_DFMT_1BYTE 0 #define K_SMB_DFMT_2BYTE 1 @@ -183,9 +183,9 @@ #define V_SMB_DFMT_RESERVED V_SMB_DFMT(K_SMB_DFMT_RESERVED) #define S_SMB_AFMT 11 -#define M_SMB_AFMT _SB_MAKEMASK(2,S_SMB_AFMT) -#define V_SMB_AFMT(x) _SB_MAKEVALUE(x,S_SMB_AFMT) -#define G_SMB_AFMT(x) _SB_GETVALUE(x,S_SMB_AFMT,M_SMB_AFMT) +#define M_SMB_AFMT _SB_MAKEMASK(2, S_SMB_AFMT) +#define V_SMB_AFMT(x) _SB_MAKEVALUE(x, S_SMB_AFMT) +#define G_SMB_AFMT(x) _SB_GETVALUE(x, S_SMB_AFMT, M_SMB_AFMT) #define K_SMB_AFMT_NONE 0 #define K_SMB_AFMT_ADDR 1 diff --git a/include/asm-mips/sibyte/sb1250_syncser.h b/include/asm-mips/sibyte/sb1250_syncser.h index dd154ac505d8..d4b8558e0bf1 100644 --- a/include/asm-mips/sibyte/sb1250_syncser.h +++ b/include/asm-mips/sibyte/sb1250_syncser.h @@ -43,8 +43,8 @@ #define M_SYNCSER_MSB_FIRST _SB_MAKEMASK1(1) #define S_SYNCSER_FLAG_NUM 2 -#define M_SYNCSER_FLAG_NUM _SB_MAKEMASK(4,S_SYNCSER_FLAG_NUM) -#define V_SYNCSER_FLAG_NUM _SB_MAKEVALUE(x,S_SYNCSER_FLAG_NUM) +#define M_SYNCSER_FLAG_NUM _SB_MAKEMASK(4, S_SYNCSER_FLAG_NUM) +#define V_SYNCSER_FLAG_NUM _SB_MAKEVALUE(x, S_SYNCSER_FLAG_NUM) #define M_SYNCSER_FLAG_EN _SB_MAKEMASK1(6) #define M_SYNCSER_HDLC_EN _SB_MAKEMASK1(7) @@ -59,8 +59,8 @@ #define M_SYNCSER_RXCLK_EXT _SB_MAKEMASK1(1) #define S_SYNCSER_RXSYNC_DLY 2 -#define M_SYNCSER_RXSYNC_DLY _SB_MAKEMASK(2,S_SYNCSER_RXSYNC_DLY) -#define V_SYNCSER_RXSYNC_DLY(x) _SB_MAKEVALUE(x,S_SYNCSER_RXSYNC_DLY) +#define M_SYNCSER_RXSYNC_DLY _SB_MAKEMASK(2, S_SYNCSER_RXSYNC_DLY) +#define V_SYNCSER_RXSYNC_DLY(x) _SB_MAKEVALUE(x, S_SYNCSER_RXSYNC_DLY) #define M_SYNCSER_RXSYNC_LOW _SB_MAKEMASK1(4) #define M_SYNCSER_RXSTRB_LOW _SB_MAKEMASK1(5) @@ -72,8 +72,8 @@ #define M_SYNCSER_TXCLK_EXT _SB_MAKEMASK1(9) #define S_SYNCSER_TXSYNC_DLY 10 -#define M_SYNCSER_TXSYNC_DLY _SB_MAKEMASK(2,S_SYNCSER_TXSYNC_DLY) -#define V_SYNCSER_TXSYNC_DLY(x) _SB_MAKEVALUE(x,S_SYNCSER_TXSYNC_DLY) +#define M_SYNCSER_TXSYNC_DLY _SB_MAKEMASK(2, S_SYNCSER_TXSYNC_DLY) +#define V_SYNCSER_TXSYNC_DLY(x) _SB_MAKEVALUE(x, S_SYNCSER_TXSYNC_DLY) #define M_SYNCSER_TXSYNC_LOW _SB_MAKEMASK1(12) #define M_SYNCSER_TXSTRB_LOW _SB_MAKEMASK1(13) @@ -137,8 +137,8 @@ #define M_SYNCSER_SEQ_BYTE _SB_MAKEMASK1(1) #define S_SYNCSER_SEQ_COUNT 2 -#define M_SYNCSER_SEQ_COUNT _SB_MAKEMASK(4,S_SYNCSER_SEQ_COUNT) -#define V_SYNCSER_SEQ_COUNT(x) _SB_MAKEVALUE(x,S_SYNCSER_SEQ_COUNT) +#define M_SYNCSER_SEQ_COUNT _SB_MAKEMASK(4, S_SYNCSER_SEQ_COUNT) +#define V_SYNCSER_SEQ_COUNT(x) _SB_MAKEVALUE(x, S_SYNCSER_SEQ_COUNT) #define M_SYNCSER_SEQ_ENABLE _SB_MAKEMASK1(6) #define M_SYNCSER_SEQ_STROBE _SB_MAKEMASK1(7) diff --git a/include/asm-mips/sibyte/sb1250_uart.h b/include/asm-mips/sibyte/sb1250_uart.h index cf74fedcbef1..d835bf280140 100644 --- a/include/asm-mips/sibyte/sb1250_uart.h +++ b/include/asm-mips/sibyte/sb1250_uart.h @@ -46,8 +46,8 @@ */ #define S_DUART_BITS_PER_CHAR 0 -#define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2,S_DUART_BITS_PER_CHAR) -#define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x,S_DUART_BITS_PER_CHAR) +#define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2, S_DUART_BITS_PER_CHAR) +#define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x, S_DUART_BITS_PER_CHAR) #define K_DUART_BITS_PER_CHAR_RSV0 0 #define K_DUART_BITS_PER_CHAR_RSV1 1 @@ -64,8 +64,8 @@ #define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2) #define S_DUART_PARITY_MODE 3 -#define M_DUART_PARITY_MODE _SB_MAKEMASK(2,S_DUART_PARITY_MODE) -#define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x,S_DUART_PARITY_MODE) +#define M_DUART_PARITY_MODE _SB_MAKEMASK(2, S_DUART_PARITY_MODE) +#define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x, S_DUART_PARITY_MODE) #define K_DUART_PARITY_MODE_ADD 0 #define K_DUART_PARITY_MODE_ADD_FIXED 1 @@ -89,7 +89,7 @@ * Register: DUART_MODE_REG_2_B */ -#define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3,0) /* ignored */ +#define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3, 0) /* ignored */ #define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3) #define M_DUART_STOP_BIT_LEN_1 0 @@ -100,8 +100,8 @@ #define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */ #define S_DUART_CHAN_MODE 6 -#define M_DUART_CHAN_MODE _SB_MAKEMASK(2,S_DUART_CHAN_MODE) -#define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x,S_DUART_CHAN_MODE) +#define M_DUART_CHAN_MODE _SB_MAKEMASK(2, S_DUART_CHAN_MODE) +#define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x, S_DUART_CHAN_MODE) #define K_DUART_CHAN_MODE_NORMAL 0 #define K_DUART_CHAN_MODE_LCL_LOOP 2 @@ -123,8 +123,8 @@ #define M_DUART_TX_DIS _SB_MAKEMASK1(3) #define S_DUART_MISC_CMD 4 -#define M_DUART_MISC_CMD _SB_MAKEMASK(3,S_DUART_MISC_CMD) -#define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x,S_DUART_MISC_CMD) +#define M_DUART_MISC_CMD _SB_MAKEMASK(3, S_DUART_MISC_CMD) +#define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x, S_DUART_MISC_CMD) #define K_DUART_MISC_CMD_NOACTION0 0 #define K_DUART_MISC_CMD_NOACTION1 1 @@ -168,7 +168,7 @@ * Register: DUART_CLK_SEL_B */ -#define M_DUART_CLK_COUNTER _SB_MAKEMASK(12,0) +#define M_DUART_CLK_COUNTER _SB_MAKEMASK(12, 0) #define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1) /* @@ -179,8 +179,8 @@ * Register: DUART_TX_HOLD_B */ -#define M_DUART_RX_DATA _SB_MAKEMASK(8,0) -#define M_DUART_TX_DATA _SB_MAKEMASK(8,0) +#define M_DUART_RX_DATA _SB_MAKEMASK(8, 0) +#define M_DUART_TX_DATA _SB_MAKEMASK(8, 0) /* * DUART Input Port Register (Table 10-10) @@ -202,10 +202,10 @@ */ #define S_DUART_IN_PIN_VAL 0 -#define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4,S_DUART_IN_PIN_VAL) +#define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4, S_DUART_IN_PIN_VAL) #define S_DUART_IN_PIN_CHNG 4 -#define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4,S_DUART_IN_PIN_CHNG) +#define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4, S_DUART_IN_PIN_CHNG) /* @@ -217,7 +217,7 @@ #define M_DUART_OPC2_SEL _SB_MAKEMASK1(1) #define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */ #define M_DUART_OPC3_SEL _SB_MAKEMASK1(3) -#define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4,4) /* must be zero */ +#define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4, 4) /* must be zero */ /* * DUART Aux Control Register (Table 10-15) @@ -228,7 +228,7 @@ #define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1) #define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2) #define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3) -#define M_DUART_ACR_RESERVED _SB_MAKEMASK(4,4) +#define M_DUART_ACR_RESERVED _SB_MAKEMASK(4, 4) #define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0) #define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2) @@ -242,18 +242,18 @@ #define S_DUART_ISR_RX_A 1 #define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A) -#define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x,S_DUART_ISR_RX_A) -#define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x,S_DUART_ISR_RX_A,M_DUART_ISR_RX_A) +#define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x, S_DUART_ISR_RX_A) +#define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x, S_DUART_ISR_RX_A, M_DUART_ISR_RX_A) #define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) #define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) -#define M_DUART_ISR_ALL_A _SB_MAKEMASK(4,0) +#define M_DUART_ISR_ALL_A _SB_MAKEMASK(4, 0) #define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) #define M_DUART_ISR_RX_B _SB_MAKEMASK1(5) #define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6) #define M_DUART_ISR_IN_B _SB_MAKEMASK1(7) -#define M_DUART_ISR_ALL_B _SB_MAKEMASK(4,4) +#define M_DUART_ISR_ALL_B _SB_MAKEMASK(4, 4) /* * DUART Channel A Interrupt Status Register (Table 10-17) @@ -266,8 +266,8 @@ #define M_DUART_ISR_RX _SB_MAKEMASK1(1) #define M_DUART_ISR_BRK _SB_MAKEMASK1(2) #define M_DUART_ISR_IN _SB_MAKEMASK1(3) -#define M_DUART_ISR_ALL _SB_MAKEMASK(4,0) -#define M_DUART_ISR_RESERVED _SB_MAKEMASK(4,4) +#define M_DUART_ISR_ALL _SB_MAKEMASK(4, 0) +#define M_DUART_ISR_RESERVED _SB_MAKEMASK(4, 4) /* * DUART Interrupt Mask Register (Table 10-19) @@ -278,13 +278,13 @@ #define M_DUART_IMR_RX_A _SB_MAKEMASK1(1) #define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2) #define M_DUART_IMR_IN_A _SB_MAKEMASK1(3) -#define M_DUART_IMR_ALL_A _SB_MAKEMASK(4,0) +#define M_DUART_IMR_ALL_A _SB_MAKEMASK(4, 0) #define M_DUART_IMR_TX_B _SB_MAKEMASK1(4) #define M_DUART_IMR_RX_B _SB_MAKEMASK1(5) #define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6) #define M_DUART_IMR_IN_B _SB_MAKEMASK1(7) -#define M_DUART_IMR_ALL_B _SB_MAKEMASK(4,4) +#define M_DUART_IMR_ALL_B _SB_MAKEMASK(4, 4) /* * DUART Channel A Interrupt Mask Register (Table 10-20) @@ -297,8 +297,8 @@ #define M_DUART_IMR_RX _SB_MAKEMASK1(1) #define M_DUART_IMR_BRK _SB_MAKEMASK1(2) #define M_DUART_IMR_IN _SB_MAKEMASK1(3) -#define M_DUART_IMR_ALL _SB_MAKEMASK(4,0) -#define M_DUART_IMR_RESERVED _SB_MAKEMASK(4,4) +#define M_DUART_IMR_ALL _SB_MAKEMASK(4, 0) +#define M_DUART_IMR_RESERVED _SB_MAKEMASK(4, 4) /* @@ -310,7 +310,7 @@ #define M_DUART_SET_OPR1 _SB_MAKEMASK1(1) #define M_DUART_SET_OPR2 _SB_MAKEMASK1(2) #define M_DUART_SET_OPR3 _SB_MAKEMASK1(3) -#define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4,4) +#define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4, 4) /* * DUART Output Port Clear Register (Table 10-23) @@ -321,7 +321,7 @@ #define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1) #define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2) #define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3) -#define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4,4) +#define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4, 4) /* * DUART Output Port RTS Register (Table 10-24) @@ -332,7 +332,7 @@ #define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1) #define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2) #define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3) -#define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4,4) +#define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4, 4) #define M_DUART_OUT_PIN_SET(chan) \ (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1) @@ -345,14 +345,14 @@ */ #define S_DUART_SIG_FULL _SB_MAKE64(0) -#define M_DUART_SIG_FULL _SB_MAKEMASK(4,S_DUART_SIG_FULL) -#define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x,S_DUART_SIG_FULL) -#define G_DUART_SIG_FULL(x) _SB_GETVALUE(x,S_DUART_SIG_FULL,M_DUART_SIG_FULL) +#define M_DUART_SIG_FULL _SB_MAKEMASK(4, S_DUART_SIG_FULL) +#define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x, S_DUART_SIG_FULL) +#define G_DUART_SIG_FULL(x) _SB_GETVALUE(x, S_DUART_SIG_FULL, M_DUART_SIG_FULL) #define S_DUART_INT_TIME _SB_MAKE64(4) -#define M_DUART_INT_TIME _SB_MAKEMASK(4,S_DUART_INT_TIME) -#define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x,S_DUART_INT_TIME) -#define G_DUART_INT_TIME(x) _SB_GETVALUE(x,S_DUART_INT_TIME,M_DUART_INT_TIME) +#define M_DUART_INT_TIME _SB_MAKEMASK(4, S_DUART_INT_TIME) +#define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x, S_DUART_INT_TIME) +#define G_DUART_INT_TIME(x) _SB_GETVALUE(x, S_DUART_INT_TIME, M_DUART_INT_TIME) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ diff --git a/include/asm-mips/siginfo.h b/include/asm-mips/siginfo.h index 2e32949bd674..96e28f18dad1 100644 --- a/include/asm-mips/siginfo.h +++ b/include/asm-mips/siginfo.h @@ -106,8 +106,8 @@ typedef struct siginfo { #undef SI_TIMER #undef SI_MESGQ #define SI_ASYNCIO -2 /* sent by AIO completion */ -#define SI_TIMER __SI_CODE(__SI_TIMER,-3) /* sent by timer expiration */ -#define SI_MESGQ __SI_CODE(__SI_MESGQ,-4) /* sent by real time mesq state change */ +#define SI_TIMER __SI_CODE(__SI_TIMER, -3) /* sent by timer expiration */ +#define SI_MESGQ __SI_CODE(__SI_MESGQ, -4) /* sent by real time mesq state change */ #ifdef __KERNEL__ diff --git a/include/asm-mips/sim.h b/include/asm-mips/sim.h index 67c4fe52bb42..0cd719fabb51 100644 --- a/include/asm-mips/sim.h +++ b/include/asm-mips/sim.h @@ -18,7 +18,7 @@ #ifdef CONFIG_32BIT #define save_static_function(symbol) \ -__asm__ ( \ +__asm__( \ ".text\n\t" \ ".globl\t" #symbol "\n\t" \ ".align\t2\n\t" \ @@ -46,7 +46,7 @@ __asm__ ( \ #ifdef CONFIG_64BIT #define save_static_function(symbol) \ -__asm__ ( \ +__asm__( \ ".text\n\t" \ ".globl\t" #symbol "\n\t" \ ".align\t2\n\t" \ diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h index 13aef6af422c..dc770025a9b0 100644 --- a/include/asm-mips/smp.h +++ b/include/asm-mips/smp.h @@ -60,6 +60,15 @@ extern cpumask_t phys_cpu_present_map; */ extern void core_send_ipi(int cpu, unsigned int action); +static inline void core_send_ipi_mask(cpumask_t mask, unsigned int action) +{ + unsigned int i; + + for_each_cpu_mask(i, mask) + core_send_ipi(i, action); +} + + /* * Firmware CPU startup hook */ diff --git a/include/asm-mips/smtc_ipi.h b/include/asm-mips/smtc_ipi.h index a52a4a7a36e0..e09131a6127d 100644 --- a/include/asm-mips/smtc_ipi.h +++ b/include/asm-mips/smtc_ipi.h @@ -34,6 +34,7 @@ struct smtc_ipi { #define LINUX_SMP_IPI 1 #define SMTC_CLOCK_TICK 2 +#define IRQ_AFFINITY_IPI 3 /* * A queue of IPI messages diff --git a/include/asm-mips/sn/addrs.h b/include/asm-mips/sn/addrs.h index 8fa0af6b68d2..fec9bdd34913 100644 --- a/include/asm-mips/sn/addrs.h +++ b/include/asm-mips/sn/addrs.h @@ -50,7 +50,7 @@ #define TO_NODE_ADDRSPACE(_pa) (UINT64_CAST (_pa) & NODE_ADDRSPACE_MASK) #define CHANGE_ADDR_NASID(_pa, _nasid) \ - ((UINT64_CAST (_pa) & ~NASID_MASK) | \ + ((UINT64_CAST(_pa) & ~NASID_MASK) | \ (UINT64_CAST(_nasid) << NASID_SHFT)) @@ -75,7 +75,7 @@ #define RAW_NODE_SWIN_BASE(nasid, widget) \ - (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS)) + (NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS)) #define WIDGETID_GET(addr) ((unsigned char)((addr >> SWIN_SIZE_BITS) & 0xff)) @@ -192,31 +192,31 @@ #define BDDIR_ENTRY_LO(_pa) ((HSPEC_BASE + \ NODE_ADDRSPACE_SIZE * 3 / 4 + \ 0x200) | \ - UINT64_CAST (_pa) & NASID_MASK | \ - UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \ - UINT64_CAST (_pa) >> 3 & 0x1f << 4) + UINT64_CAST(_pa) & NASID_MASK | \ + UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \ + UINT64_CAST(_pa) >> 3 & 0x1f << 4) #define BDDIR_ENTRY_HI(_pa) ((HSPEC_BASE + \ NODE_ADDRSPACE_SIZE * 3 / 4 + \ 0x208) | \ - UINT64_CAST (_pa) & NASID_MASK | \ - UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \ - UINT64_CAST (_pa) >> 3 & 0x1f << 4) + UINT64_CAST(_pa) & NASID_MASK | \ + UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \ + UINT64_CAST(_pa) >> 3 & 0x1f << 4) #define BDPRT_ENTRY(_pa, _rgn) ((HSPEC_BASE + \ NODE_ADDRSPACE_SIZE * 3 / 4) | \ - UINT64_CAST (_pa) & NASID_MASK | \ - UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \ + UINT64_CAST(_pa) & NASID_MASK | \ + UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \ (_rgn) << 3) -#define BDPRT_ENTRY_ADDR(_pa,_rgn) (BDPRT_ENTRY((_pa),(_rgn))) -#define BDPRT_ENTRY_S(_pa,_rgn,_val) (*(__psunsigned_t *)BDPRT_ENTRY((_pa),(_rgn))=(_val)) -#define BDPRT_ENTRY_L(_pa,_rgn) (*(__psunsigned_t *)BDPRT_ENTRY((_pa),(_rgn))) +#define BDPRT_ENTRY_ADDR(_pa, _rgn) (BDPRT_ENTRY((_pa), (_rgn))) +#define BDPRT_ENTRY_S(_pa, _rgn, _val) (*(__psunsigned_t *)BDPRT_ENTRY((_pa), (_rgn))=(_val)) +#define BDPRT_ENTRY_L(_pa, _rgn) (*(__psunsigned_t *)BDPRT_ENTRY((_pa), (_rgn))) #define BDECC_ENTRY(_pa) ((HSPEC_BASE + \ NODE_ADDRSPACE_SIZE / 2) | \ - UINT64_CAST (_pa) & NASID_MASK | \ - UINT64_CAST (_pa) >> 2 & BDECC_UPPER_MASK | \ - UINT64_CAST (_pa) >> 3 & 3) + UINT64_CAST(_pa) & NASID_MASK | \ + UINT64_CAST(_pa) >> 2 & BDECC_UPPER_MASK | \ + UINT64_CAST(_pa) >> 3 & 3) /* * Macro to convert a back door directory or protection address into the @@ -225,16 +225,16 @@ #define BDADDR_IS_DIR(_ba) ((UINT64_CAST (_ba) & 0x200) != 0) #define BDADDR_IS_PRT(_ba) ((UINT64_CAST (_ba) & 0x200) == 0) -#define BDDIR_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ - (UINT64_CAST (_ba) & BDDIR_UPPER_MASK)<<2 | \ - (UINT64_CAST (_ba) & 0x1f << 4) << 3) +#define BDDIR_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ + (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2 | \ + (UINT64_CAST(_ba) & 0x1f << 4) << 3) -#define BDPRT_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ - (UINT64_CAST (_ba) & BDDIR_UPPER_MASK)<<2) +#define BDPRT_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ + (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2) -#define BDECC_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ - (UINT64_CAST (_ba) & BDECC_UPPER_MASK)<<2 | \ - (UINT64_CAST (_ba) & 3) << 3) +#define BDECC_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ + (UINT64_CAST(_ba) & BDECC_UPPER_MASK)<<2 | \ + (UINT64_CAST(_ba) & 3) << 3) #endif /* CONFIG_SGI_IP27 */ @@ -282,7 +282,7 @@ * the base of the register space. */ #define HUB_REG_PTR(_base, _off) \ - (HUBREG_CAST ((__psunsigned_t)(_base) + (__psunsigned_t)(_off))) + (HUBREG_CAST((__psunsigned_t)(_base) + (__psunsigned_t)(_off))) #define HUB_REG_PTR_L(_base, _off) \ HUB_L(HUB_REG_PTR((_base), (_off))) diff --git a/include/asm-mips/sn/arch.h b/include/asm-mips/sn/arch.h index da523de628be..bd75945e10ff 100644 --- a/include/asm-mips/sn/arch.h +++ b/include/asm-mips/sn/arch.h @@ -19,8 +19,8 @@ typedef u64 hubreg_t; -#define cputonasid(cpu) (cpu_data[(cpu)].p_nasid) -#define cputoslice(cpu) (cpu_data[(cpu)].p_slice) +#define cputonasid(cpu) (sn_cpu_info[(cpu)].p_nasid) +#define cputoslice(cpu) (sn_cpu_info[(cpu)].p_slice) #define makespnum(_nasid, _slice) \ (((_nasid) << CPUS_PER_NODE_SHFT) | (_slice)) diff --git a/include/asm-mips/sn/io.h b/include/asm-mips/sn/io.h index ab2fa8cd2627..24c6775fbb0f 100644 --- a/include/asm-mips/sn/io.h +++ b/include/asm-mips/sn/io.h @@ -9,7 +9,7 @@ #ifndef _ASM_SN_IO_H #define _ASM_SN_IO_H -#if defined (CONFIG_SGI_IP27) +#if defined(CONFIG_SGI_IP27) #include <asm/sn/sn0/hubio.h> #endif diff --git a/include/asm-mips/sn/klconfig.h b/include/asm-mips/sn/klconfig.h index 82aeb9e322db..96cfd2ab1bcd 100644 --- a/include/asm-mips/sn/klconfig.h +++ b/include/asm-mips/sn/klconfig.h @@ -51,8 +51,8 @@ #if defined(CONFIG_SGI_IP27) || defined(CONFIG_SGI_IP35) #include <asm/sn/agent.h> -#include <asm/arc/types.h> -#include <asm/arc/hinv.h> +#include <asm/fw/arc/types.h> +#include <asm/fw/arc/hinv.h> #if defined(CONFIG_SGI_IP35) // The hack file has to be before vector and after sn0_fru.... #include <asm/hack.h> @@ -405,7 +405,7 @@ typedef struct kl_config_hdr { #define KLTYPE(_x) ((_x) & KLTYPE_MASK) #define IS_MIO_PRESENT(l) ((l->brd_type == KLTYPE_BASEIO) && \ (l->brd_flags & SECOND_NIC_PRESENT)) -#define IS_MIO_IOC3(l,n) (IS_MIO_PRESENT(l) && (n > 2)) +#define IS_MIO_IOC3(l, n) (IS_MIO_PRESENT(l) && (n > 2)) /* * board structures diff --git a/include/asm-mips/sn/kldir.h b/include/asm-mips/sn/kldir.h index 0573cbffc104..1327e12e9645 100644 --- a/include/asm-mips/sn/kldir.h +++ b/include/asm-mips/sn/kldir.h @@ -140,7 +140,7 @@ */ #define SYMMON_STACK_SIZE 0x8000 -#if defined (PROM) +#if defined(PROM) /* * These defines are prom version dependent. No code other than the IP27 diff --git a/include/asm-mips/sn/sn0/addrs.h b/include/asm-mips/sn/sn0/addrs.h index 9e8cc52910f6..b06190093bbc 100644 --- a/include/asm-mips/sn/sn0/addrs.h +++ b/include/asm-mips/sn/sn0/addrs.h @@ -91,7 +91,7 @@ : RAW_NODE_SWIN_BASE(nasid, widget)) #else /* __ASSEMBLY__ */ #define NODE_SWIN_BASE(nasid, widget) \ - (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS)) + (NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS)) #endif /* __ASSEMBLY__ */ /* @@ -106,7 +106,7 @@ #define BWIN_WIDGET_MASK 0x7 #define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE) #define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \ - (UINT64_CAST (bigwin) << BWIN_SIZE_BITS)) + (UINT64_CAST(bigwin) << BWIN_SIZE_BITS)) #define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK) #define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK) @@ -259,7 +259,7 @@ * CACHE_ERR_SP_PTR could either contain an address to the stack, or * the stack could start at CACHE_ERR_SP_PTR */ -#if defined (HUB_ERR_STS_WAR) +#if defined(HUB_ERR_STS_WAR) #define CACHE_ERR_EFRAME 0x480 #else /* HUB_ERR_STS_WAR */ #define CACHE_ERR_EFRAME 0x400 @@ -275,7 +275,7 @@ #define _ARCSPROM -#if defined (HUB_ERR_STS_WAR) +#if defined(HUB_ERR_STS_WAR) #define ERR_STS_WAR_REGISTER IIO_IIBUSERR #define ERR_STS_WAR_ADDR LOCAL_HUB_ADDR(IIO_IIBUSERR) diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h index ddaf36a1e389..4d43dbb7f8b8 100644 --- a/include/asm-mips/sni.h +++ b/include/asm-mips/sni.h @@ -194,17 +194,17 @@ extern unsigned int sni_brd_type; #define PCIMT_INT_ACKNOWLEDGE 0xba000000 /* board specific init functions */ -extern void sni_a20r_init (void); -extern void sni_pcit_init (void); -extern void sni_rm200_init (void); -extern void sni_pcimt_init (void); +extern void sni_a20r_init(void); +extern void sni_pcit_init(void); +extern void sni_rm200_init(void); +extern void sni_pcimt_init(void); /* board specific irq init functions */ -extern void sni_a20r_irq_init (void); -extern void sni_pcit_irq_init (void); -extern void sni_pcit_cplus_irq_init (void); -extern void sni_rm200_irq_init (void); -extern void sni_pcimt_irq_init (void); +extern void sni_a20r_irq_init(void); +extern void sni_pcit_irq_init(void); +extern void sni_pcit_cplus_irq_init(void); +extern void sni_rm200_irq_init(void); +extern void sni_pcimt_irq_init(void); /* timer inits */ extern void sni_cpu_time_init(void); diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h index ed33366b85b8..fb41a8d76392 100644 --- a/include/asm-mips/stackframe.h +++ b/include/asm-mips/stackframe.h @@ -91,14 +91,14 @@ #else MFC0 k0, CP0_CONTEXT #endif -#if defined(CONFIG_BUILD_ELF64) || (defined(CONFIG_64BIT) && __GNUC__ < 4) +#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) + lui k1, %hi(kernelsp) +#else lui k1, %highest(kernelsp) daddiu k1, %higher(kernelsp) dsll k1, 16 daddiu k1, %hi(kernelsp) dsll k1, 16 -#else - lui k1, %hi(kernelsp) #endif LONG_SRL k0, PTEBASE_SHIFT LONG_ADDU k1, k0 @@ -116,14 +116,14 @@ .endm #else .macro get_saved_sp /* Uniprocessor variation */ -#if defined(CONFIG_BUILD_ELF64) || (defined(CONFIG_64BIT) && __GNUC__ < 4) +#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) + lui k1, %hi(kernelsp) +#else lui k1, %highest(kernelsp) daddiu k1, %higher(kernelsp) dsll k1, k1, 16 daddiu k1, %hi(kernelsp) dsll k1, k1, 16 -#else - lui k1, %hi(kernelsp) #endif LONG_L k1, %lo(kernelsp)(k1) .endm @@ -393,11 +393,11 @@ * and disable interrupts only for the * current TC, using the TCStatus register. */ - mfc0 t0,CP0_TCSTATUS + mfc0 t0, CP0_TCSTATUS /* Fortunately CU 0 is in the same place in both registers */ /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */ li t1, ST0_CU0 | 0x08001c00 - or t0,t1 + or t0, t1 /* Clear TKSU, leave IXMT */ xori t0, 0x00001800 mtc0 t0, CP0_TCSTATUS @@ -429,11 +429,11 @@ * current TC, using the TCStatus register. */ _ehb - mfc0 t0,CP0_TCSTATUS + mfc0 t0, CP0_TCSTATUS /* Fortunately CU 0 is in the same place in both registers */ /* Set TCU0, TKSU (for later inversion) and IXMT */ li t1, ST0_CU0 | 0x08001c00 - or t0,t1 + or t0, t1 /* Clear TKSU *and* IXMT */ xori t0, 0x00001c00 mtc0 t0, CP0_TCSTATUS diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index 480b574e2483..90e4b403f531 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h @@ -62,7 +62,7 @@ do { \ #define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0) #endif -#define switch_to(prev,next,last) \ +#define switch_to(prev, next, last) \ do { \ __mips_mt_fpaff_switch_to(prev); \ if (cpu_has_dsp) \ @@ -193,13 +193,13 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz return x; } -#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) +#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))) -extern void set_handler (unsigned long offset, void *addr, unsigned long len); -extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len); +extern void set_handler(unsigned long offset, void *addr, unsigned long len); +extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len); typedef void (*vi_handler_t)(void); -extern void *set_vi_handler (int n, vi_handler_t addr); +extern void *set_vi_handler(int n, vi_handler_t addr); extern void *set_except_vector(int n, void *addr); extern unsigned long ebase; diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h index a632cef830a2..35555bd5c52d 100644 --- a/include/asm-mips/time.h +++ b/include/asm-mips/time.h @@ -26,15 +26,13 @@ extern spinlock_t rtc_lock; /* - * RTC ops. By default, they point to no-RTC functions. - * rtc_mips_get_time - mktime(year, mon, day, hour, min, sec) in seconds. + * RTC ops. By default, they point to weak no-op RTC functions. * rtc_mips_set_time - reverse the above translation and set time to RTC. * rtc_mips_set_mmss - similar to rtc_set_time, but only min and sec need * to be set. Used by RTC sync-up. */ -extern unsigned long (*rtc_mips_get_time)(void); -extern int (*rtc_mips_set_time)(unsigned long); -extern int (*rtc_mips_set_mmss)(unsigned long); +extern int rtc_mips_set_time(unsigned long); +extern int rtc_mips_set_mmss(unsigned long); /* * Timer interrupt functions. @@ -51,35 +49,15 @@ extern void (*mips_timer_ack)(void); extern struct clocksource clocksource_mips; /* - * to_tm() converts system time back to (year, mon, day, hour, min, sec). - * It is intended to help implement rtc_set_time() functions. - * Copied from PPC implementation. - */ -extern void to_tm(unsigned long tim, struct rtc_time *tm); - -/* - * high-level timer interrupt routines. - */ -extern irqreturn_t timer_interrupt(int irq, void *dev_id); - -/* - * the corresponding low-level timer interrupt routine. - */ -extern asmlinkage void ll_timer_interrupt(int irq); - -/* * profiling and process accouting is done separately in local_timer_interrupt */ extern void local_timer_interrupt(int irq, void *dev_id); -extern asmlinkage void ll_local_timer_interrupt(int irq); /* * board specific routines required by time_init(). - * board_time_init is defaulted to NULL and can remain so. - * plat_timer_setup must be setup properly in machine setup routine. */ struct irqaction; -extern void (*board_time_init)(void); +extern void plat_time_init(void); extern void plat_timer_setup(struct irqaction *irq); /* @@ -89,4 +67,15 @@ extern void plat_timer_setup(struct irqaction *irq); */ extern unsigned int mips_hpt_frequency; +/* + * The performance counter IRQ on MIPS is a close relative to the timer IRQ + * so it lives here. + */ +extern int (*perf_irq)(void); + +/* + * Initialize the calling CPU's compare interrupt as clockevent device + */ +extern void mips_clockevent_init(void); + #endif /* _ASM_TIME_H */ diff --git a/include/asm-mips/timex.h b/include/asm-mips/timex.h index b80de8e0fbbd..87c68ae76ff8 100644 --- a/include/asm-mips/timex.h +++ b/include/asm-mips/timex.h @@ -48,7 +48,7 @@ typedef unsigned int cycles_t; -static inline cycles_t get_cycles (void) +static inline cycles_t get_cycles(void) { return read_c0_count(); } diff --git a/include/asm-mips/tlbflush.h b/include/asm-mips/tlbflush.h index 276be77c3e85..730e841fb08a 100644 --- a/include/asm-mips/tlbflush.h +++ b/include/asm-mips/tlbflush.h @@ -37,10 +37,10 @@ extern void flush_tlb_one(unsigned long vaddr); #define flush_tlb_all() local_flush_tlb_all() #define flush_tlb_mm(mm) local_flush_tlb_mm(mm) -#define flush_tlb_range(vma,vmaddr,end) local_flush_tlb_range(vma, vmaddr, end) +#define flush_tlb_range(vma, vmaddr, end) local_flush_tlb_range(vma, vmaddr, end) #define flush_tlb_kernel_range(vmaddr,end) \ local_flush_tlb_kernel_range(vmaddr, end) -#define flush_tlb_page(vma,page) local_flush_tlb_page(vma, page) +#define flush_tlb_page(vma, page) local_flush_tlb_page(vma, page) #define flush_tlb_one(vaddr) local_flush_tlb_one(vaddr) #endif /* CONFIG_SMP */ diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h index a60649569c2c..b188a659ce02 100644 --- a/include/asm-mips/tx4927/toshiba_rbtx4927.h +++ b/include/asm-mips/tx4927/toshiba_rbtx4927.h @@ -28,24 +28,20 @@ #define __ASM_TX4927_TOSHIBA_RBTX4927_H #include <asm/tx4927/tx4927.h> -#include <asm/tx4927/tx4927_mips.h> #ifdef CONFIG_PCI #include <asm/tx4927/tx4927_pci.h> #endif -#define TOSHIBA_RBTX4927_WR08(a,b) do { TX4927_WR08(a,b); wbflush(); } while ( 0 ) - - #ifdef CONFIG_PCI #define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO #else #define TBTX4927_ISA_IO_OFFSET 0 #endif -#define RBTX4927_SW_RESET_DO 0xbc00f000 +#define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL #define RBTX4927_SW_RESET_DO_SET 0x01 -#define RBTX4927_SW_RESET_ENABLE 0xbc00f002 +#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL #define RBTX4927_SW_RESET_ENABLE_SET 0x01 diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h index 4bd4368e188c..193e80a17c12 100644 --- a/include/asm-mips/tx4927/tx4927.h +++ b/include/asm-mips/tx4927/tx4927.h @@ -27,447 +27,8 @@ #ifndef __ASM_TX4927_TX4927_H #define __ASM_TX4927_TX4927_H -#include <asm/tx4927/tx4927_mips.h> #include <asm/txx9irq.h> -/* - This register naming came from the integrated CPU/controller name TX4927 - followed by the device name from table 4.2.2 on page 4-3 and then followed - by the register name from table 4.2.3 on pages 4-4 to 4-8. The manaul - used was "TMPR4927BT Preliminary Rev 0.1 20.Jul.2001". - */ - -#define TX4927_SIO_0_BASE - -/* TX4927 controller */ -#define TX4927_BASE 0xfff1f0000 -#define TX4927_BASE 0xfff1f0000 -#define TX4927_LIMIT 0xfff1fffff - - -/* TX4927 SDRAM controller (64-bit registers) */ -#define TX4927_SDRAMC_BASE 0x8000 -#define TX4927_SDRAMC_SDCCR0 0x8000 -#define TX4927_SDRAMC_SDCCR1 0x8008 -#define TX4927_SDRAMC_SDCCR2 0x8010 -#define TX4927_SDRAMC_SDCCR3 0x8018 -#define TX4927_SDRAMC_SDCTR 0x8040 -#define TX4927_SDRAMC_SDCMD 0x8058 -#define TX4927_SDRAMC_LIMIT 0x8fff - - -/* TX4927 external bus controller (64-bit registers) */ -#define TX4927_EBUSC_BASE 0x9000 -#define TX4927_EBUSC_EBCCR0 0x9000 -#define TX4927_EBUSC_EBCCR1 0x9008 -#define TX4927_EBUSC_EBCCR2 0x9010 -#define TX4927_EBUSC_EBCCR3 0x9018 -#define TX4927_EBUSC_EBCCR4 0x9020 -#define TX4927_EBUSC_EBCCR5 0x9028 -#define TX4927_EBUSC_EBCCR6 0x9030 -#define TX4927_EBUSC_EBCCR7 0x9008 -#define TX4927_EBUSC_LIMIT 0x9fff - - -/* TX4927 SDRRAM Error Check Correction (64-bit registers) */ -#define TX4927_ECC_BASE 0xa000 -#define TX4927_ECC_ECCCR 0xa000 -#define TX4927_ECC_ECCSR 0xa008 -#define TX4927_ECC_LIMIT 0xafff - - -/* TX4927 DMA Controller (64-bit registers) */ -#define TX4927_DMAC_BASE 0xb000 -#define TX4927_DMAC_TBD 0xb000 -#define TX4927_DMAC_LIMIT 0xbfff - - -/* TX4927 PCI Controller (32-bit registers) */ -#define TX4927_PCIC_BASE 0xd000 -#define TX4927_PCIC_TBD 0xb000 -#define TX4927_PCIC_LIMIT 0xdfff - - -/* TX4927 Configuration registers (64-bit registers) */ -#define TX4927_CONFIG_BASE 0xe000 -#define TX4927_CONFIG_CCFG 0xe000 -#define TX4927_CONFIG_CCFG_RESERVED_42_63 BM_63_42 -#define TX4927_CONFIG_CCFG_WDRST BM_41_41 -#define TX4927_CONFIG_CCFG_WDREXEN BM_40_40 -#define TX4927_CONFIG_CCFG_BCFG BM_39_32 -#define TX4927_CONFIG_CCFG_RESERVED_27_31 BM_31_27 -#define TX4927_CONFIG_CCFG_GTOT BM_26_25 -#define TX4927_CONFIG_CCFG_GTOT_4096 BM_26_25 -#define TX4927_CONFIG_CCFG_GTOT_2048 BM_26_26 -#define TX4927_CONFIG_CCFG_GTOT_1024 BM_25_25 -#define TX4927_CONFIG_CCFG_GTOT_0512 (~BM_26_25) -#define TX4927_CONFIG_CCFG_TINTDIS BM_24_24 -#define TX4927_CONFIG_CCFG_PCI66 BM_23_23 -#define TX4927_CONFIG_CCFG_PCIMODE BM_22_22 -#define TX4927_CONFIG_CCFG_RESERVED_20_21 BM_21_20 -#define TX4927_CONFIG_CCFG_DIVMODE BM_19_17 -#define TX4927_CONFIG_CCFG_DIVMODE_2_0 BM_19_19 -#define TX4927_CONFIG_CCFG_DIVMODE_3_0 (BM_19_19|BM_17_17) -#define TX4927_CONFIG_CCFG_DIVMODE_4_0 BM_19_18 -#define TX4927_CONFIG_CCFG_DIVMODE_2_5 BM_19_17 -#define TX4927_CONFIG_CCFG_DIVMODE_8_0 (~BM_19_17) -#define TX4927_CONFIG_CCFG_DIVMODE_12_0 BM_17_17 -#define TX4927_CONFIG_CCFG_DIVMODE_16_0 BM_18_18 -#define TX4927_CONFIG_CCFG_DIVMODE_10_0 BM_18_17 -#define TX4927_CONFIG_CCFG_BEOW BM_16_16 -#define TX4927_CONFIG_CCFG_WR BM_15_15 -#define TX4927_CONFIG_CCFG_TOE BM_14_14 -#define TX4927_CONFIG_CCFG_PCIARB BM_13_13 -#define TX4927_CONFIG_CCFG_PCIDIVMODE BM_12_11 -#define TX4927_CONFIG_CCFG_RESERVED_08_10 BM_10_08 -#define TX4927_CONFIG_CCFG_SYSSP BM_07_06 -#define TX4927_CONFIG_CCFG_RESERVED_03_05 BM_05_03 -#define TX4927_CONFIG_CCFG_ENDIAN BM_02_02 -#define TX4927_CONFIG_CCFG_ARMODE BM_01_01 -#define TX4927_CONFIG_CCFG_ACEHOLD BM_00_00 -#define TX4927_CONFIG_REVID 0xe008 -#define TX4927_CONFIG_REVID_RESERVED_32_63 BM_32_63 -#define TX4927_CONFIG_REVID_PCODE BM_16_31 -#define TX4927_CONFIG_REVID_MJERREV BM_12_15 -#define TX4927_CONFIG_REVID_MINEREV BM_08_11 -#define TX4927_CONFIG_REVID_MJREV BM_04_07 -#define TX4927_CONFIG_REVID_MINREV BM_00_03 -#define TX4927_CONFIG_PCFG 0xe010 -#define TX4927_CONFIG_PCFG_RESERVED_57_63 BM_57_63 -#define TX4927_CONFIG_PCFG_DRVDATA BM_56_56 -#define TX4927_CONFIG_PCFG_DRVCB BM_55_55 -#define TX4927_CONFIG_PCFG_DRVDQM BM_54_54 -#define TX4927_CONFIG_PCFG_DRVADDR BM_53_53 -#define TX4927_CONFIG_PCFG_DRVCKE BM_52_52 -#define TX4927_CONFIG_PCFG_DRVRAS BM_51_51 -#define TX4927_CONFIG_PCFG_DRVCAS BM_50_50 -#define TX4927_CONFIG_PCFG_DRVWE BM_49_49 -#define TX4927_CONFIG_PCFG_DRVCS3 BM_48_48 -#define TX4927_CONFIG_PCFG_DRVCS2 BM_47_47 -#define TX4927_CONFIG_PCFG_DRVCS1 BM_46_4k -#define TX4927_CONFIG_PCFG_DRVCS0 BM_45_45 -#define TX4927_CONFIG_PCFG_DRVCK3 BM_44_44 -#define TX4927_CONFIG_PCFG_DRVCK2 BM_43_43 -#define TX4927_CONFIG_PCFG_DRVCK1 BM_42_42 -#define TX4927_CONFIG_PCFG_DRVCK0 BM_41_41 -#define TX4927_CONFIG_PCFG_DRVCKIN BM_40_40 -#define TX4927_CONFIG_PCFG_RESERVED_33_39 BM_33_39 -#define TX4927_CONFIG_PCFG_BYPASS_PLL BM_32_32 -#define TX4927_CONFIG_PCFG_RESERVED_30_31 BM_30_31 -#define TX4927_CONFIG_PCFG_SDCLKDLY BM_28_29 -#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_1 (~BM_28_29) -#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_2 BM_28_28 -#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_3 BM_29_29 -#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_4 BM_28_29 -#define TX4927_CONFIG_PCFG_SYSCLKEN BM_27_27 -#define TX4927_CONFIG_PCFG_SDCLKEN3 BM_26_26 -#define TX4927_CONFIG_PCFG_SDCLKEN2 BM_25_25 -#define TX4927_CONFIG_PCFG_SDCLKEN1 BM_24_24 -#define TX4927_CONFIG_PCFG_SDCLKEN0 BM_23_23 -#define TX4927_CONFIG_PCFG_SDCLKINEN BM_22_22 -#define TX4927_CONFIG_PCFG_PCICLKEN5 BM_21_21 -#define TX4927_CONFIG_PCFG_PCICLKEN4 BM_20_20 -#define TX4927_CONFIG_PCFG_PCICLKEN3 BM_19_19 -#define TX4927_CONFIG_PCFG_PCICLKEN2 BM_18_18 -#define TX4927_CONFIG_PCFG_PCICLKEN1 BM_17_17 -#define TX4927_CONFIG_PCFG_PCICLKEN0 BM_16_16 -#define TX4927_CONFIG_PCFG_RESERVED_10_15 BM_10_15 -#define TX4927_CONFIG_PCFG_SEL2 BM_09_09 -#define TX4927_CONFIG_PCFG_SEL1 BM_08_08 -#define TX4927_CONFIG_PCFG_DMASEL3 BM_06_07 -#define TX4927_CONFIG_PCFG_DMASEL3_DMAREQ3 (~BM_06_07) -#define TX4927_CONFIG_PCFG_DMASEL3_SIO0 BM_06_06 -#define TX4927_CONFIG_PCFG_DMASEL3_ACLC3 BM_07_07 -#define TX4927_CONFIG_PCFG_DMASEL3_ACLC1 BM_06_07 -#define TX4927_CONFIG_PCFG_DMASEL2 BM_06_07 -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_DMAREQ2 (~BM_06_07) -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_SIO0 BM_06_06 -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_RESERVED_10 BM_07_07 -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_RESERVED_11 BM_06_07 -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC1 (~BM_06_07) -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_SIO0 BM_06_06 -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC2 BM_07_07 -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC0 BM_06_07 -#define TX4927_CONFIG_PCFG_DMASEL1 BM_02_03 -#define TX4927_CONFIG_PCFG_DMASEL1_DMAREQ1 (~BM_02_03) -#define TX4927_CONFIG_PCFG_DMASEL1_SIO1 BM_02_02 -#define TX4927_CONFIG_PCFG_DMASEL1_ACLC1 BM_03_03 -#define TX4927_CONFIG_PCFG_DMASEL1_ACLC3 BM_02_03 -#define TX4927_CONFIG_PCFG_DMASEL0 BM_00_01 -#define TX4927_CONFIG_PCFG_DMASEL0_DMAREQ0 (~BM_00_01) -#define TX4927_CONFIG_PCFG_DMASEL0_SIO1 BM_00_00 -#define TX4927_CONFIG_PCFG_DMASEL0_ACLC0 BM_01_01 -#define TX4927_CONFIG_PCFG_DMASEL0_ACLC2 BM_00_01 -#define TX4927_CONFIG_TOEA 0xe018 -#define TX4927_CONFIG_TOEA_RESERVED_36_63 BM_36_63 -#define TX4927_CONFIG_TOEA_TOEA BM_00_35 -#define TX4927_CONFIG_CLKCTR 0xe020 -#define TX4927_CONFIG_CLKCTR_RESERVED_26_63 BM_26_63 -#define TX4927_CONFIG_CLKCTR_ACLCKD BM_25_25 -#define TX4927_CONFIG_CLKCTR_PIOCKD BM_24_24 -#define TX4927_CONFIG_CLKCTR_DMACKD BM_23_23 -#define TX4927_CONFIG_CLKCTR_PCICKD BM_22_22 -#define TX4927_CONFIG_CLKCTR_SET_21 BM_21_21 -#define TX4927_CONFIG_CLKCTR_TM0CKD BM_20_20 -#define TX4927_CONFIG_CLKCTR_TM1CKD BM_19_19 -#define TX4927_CONFIG_CLKCTR_TM2CKD BM_18_18 -#define TX4927_CONFIG_CLKCTR_SIO0CKD BM_17_17 -#define TX4927_CONFIG_CLKCTR_SIO1CKD BM_16_16 -#define TX4927_CONFIG_CLKCTR_RESERVED_10_15 BM_10_15 -#define TX4927_CONFIG_CLKCTR_ACLRST BM_09_09 -#define TX4927_CONFIG_CLKCTR_PIORST BM_08_08 -#define TX4927_CONFIG_CLKCTR_DMARST BM_07_07 -#define TX4927_CONFIG_CLKCTR_PCIRST BM_06_06 -#define TX4927_CONFIG_CLKCTR_RESERVED_05_05 BM_05_05 -#define TX4927_CONFIG_CLKCTR_TM0RST BM_04_04 -#define TX4927_CONFIG_CLKCTR_TM1RST BM_03_03 -#define TX4927_CONFIG_CLKCTR_TM2RST BM_02_02 -#define TX4927_CONFIG_CLKCTR_SIO0RST BM_01_01 -#define TX4927_CONFIG_CLKCTR_SIO1RST BM_00_00 -#define TX4927_CONFIG_GARBC 0xe030 -#define TX4927_CONFIG_GARBC_RESERVED_10_63 BM_10_63 -#define TX4927_CONFIG_GARBC_SET_09 BM_09_09 -#define TX4927_CONFIG_GARBC_ARBMD BM_08_08 -#define TX4927_CONFIG_GARBC_RESERVED_06_07 BM_06_07 -#define TX4927_CONFIG_GARBC_PRIORITY_H1 BM_04_05 -#define TX4927_CONFIG_GARBC_PRIORITY_H1_PCI (~BM_04_05) -#define TX4927_CONFIG_GARBC_PRIORITY_H1_PDMAC BM_04_04 -#define TX4927_CONFIG_GARBC_PRIORITY_H1_DMAC BM_05_05 -#define TX4927_CONFIG_GARBC_PRIORITY_H1_BAD_VALUE BM_04_05 -#define TX4927_CONFIG_GARBC_PRIORITY_H2 BM_02_03 -#define TX4927_CONFIG_GARBC_PRIORITY_H2_PCI (~BM_02_03) -#define TX4927_CONFIG_GARBC_PRIORITY_H2_PDMAC BM_02_02 -#define TX4927_CONFIG_GARBC_PRIORITY_H2_DMAC BM_03_03 -#define TX4927_CONFIG_GARBC_PRIORITY_H2_BAD_VALUE BM_02_03 -#define TX4927_CONFIG_GARBC_PRIORITY_H3 BM_00_01 -#define TX4927_CONFIG_GARBC_PRIORITY_H3_PCI (~BM_00_01) -#define TX4927_CONFIG_GARBC_PRIORITY_H3_PDMAC BM_00_00 -#define TX4927_CONFIG_GARBC_PRIORITY_H3_DMAC BM_01_01 -#define TX4927_CONFIG_GARBC_PRIORITY_H3_BAD_VALUE BM_00_01 -#define TX4927_CONFIG_RAMP 0xe048 -#define TX4927_CONFIG_RAMP_RESERVED_20_63 BM_20_63 -#define TX4927_CONFIG_RAMP_RAMP BM_00_19 -#define TX4927_CONFIG_LIMIT 0xefff - - -/* TX4927 Timer 0 (32-bit registers) */ -#define TX4927_TMR0_BASE 0xf000 -#define TX4927_TMR0_TMTCR0 0xf000 -#define TX4927_TMR0_TMTISR0 0xf004 -#define TX4927_TMR0_TMCPRA0 0xf008 -#define TX4927_TMR0_TMCPRB0 0xf00c -#define TX4927_TMR0_TMITMR0 0xf010 -#define TX4927_TMR0_TMCCDR0 0xf020 -#define TX4927_TMR0_TMPGMR0 0xf030 -#define TX4927_TMR0_TMTRR0 0xf0f0 -#define TX4927_TMR0_LIMIT 0xf0ff - - -/* TX4927 Timer 1 (32-bit registers) */ -#define TX4927_TMR1_BASE 0xf100 -#define TX4927_TMR1_TMTCR1 0xf100 -#define TX4927_TMR1_TMTISR1 0xf104 -#define TX4927_TMR1_TMCPRA1 0xf108 -#define TX4927_TMR1_TMCPRB1 0xf10c -#define TX4927_TMR1_TMITMR1 0xf110 -#define TX4927_TMR1_TMCCDR1 0xf120 -#define TX4927_TMR1_TMPGMR1 0xf130 -#define TX4927_TMR1_TMTRR1 0xf1f0 -#define TX4927_TMR1_LIMIT 0xf1ff - - -/* TX4927 Timer 2 (32-bit registers) */ -#define TX4927_TMR2_BASE 0xf200 -#define TX4927_TMR2_TMTCR2 0xf200 -#define TX4927_TMR2_TMTISR2 0xf204 -#define TX4927_TMR2_TMCPRA2 0xf208 -#define TX4927_TMR2_TMITMR2 0xf210 -#define TX4927_TMR2_TMCCDR2 0xf220 -#define TX4927_TMR2_TMWTMR2 0xf240 -#define TX4927_TMR2_TMTRR2 0xf2f0 -#define TX4927_TMR2_LIMIT 0xf2ff - - -/* TX4927 serial port 0 (32-bit registers) */ -#define TX4927_SIO0_BASE 0xf300 -#define TX4927_SIO0_SILCR0 0xf300 -#define TX4927_SIO0_SILCR0_RESERVED_16_31 BM_16_31 -#define TX4927_SIO0_SILCR0_RWUB BM_15_15 -#define TX4927_SIO0_SILCR0_TWUB BM_14_14 -#define TX4927_SIO0_SILCR0_UODE BM_13_13 -#define TX4927_SIO0_SILCR0_RESERVED_07_12 BM_07_12 -#define TX4927_SIO0_SILCR0_SCS BM_05_06 -#define TX4927_SIO0_SILCR0_SCS_IMBUSCLK_IC (~BM_05_06) -#define TX4927_SIO0_SILCR0_SCS_IMBUSCLK_BRG BM_05_05 -#define TX4927_SIO0_SILCR0_SCS_SCLK_EC BM_06_06 -#define TX4927_SIO0_SILCR0_SCS_SCLK_BRG BM_05_06 -#define TX4927_SIO0_SILCR0_UEPS BM_04_04 -#define TX4927_SIO0_SILCR0_UPEN BM_03_03 -#define TX4927_SIO0_SILCR0_USBL BM_02_02 -#define TX4927_SIO0_SILCR0_UMODE BM_00_01 -#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT BM_00_01 -#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT (~BM_00_01) -#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT_MC BM_01_01 -#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT_MC BM_00_01 -#define TX4927_SIO0_SIDICR0 0xf304 -#define TX4927_SIO0_SIDICR0_RESERVED_16_31 BM_16_31 -#define TX4927_SIO0_SIDICR0_TDE BM_15_15 -#define TX4927_SIO0_SIDICR0_RDE BM_14_14 -#define TX4927_SIO0_SIDICR0_TIE BM_13_13 -#define TX4927_SIO0_SIDICR0_RIE BM_12_12 -#define TX4927_SIO0_SIDICR0_SPIE BM_11_11 -#define TX4927_SIO0_SIDICR0_CTSAC BM_09_10 -#define TX4927_SIO0_SIDICR0_CTSAC_NONE (~BM_09_10) -#define TX4927_SIO0_SIDICR0_CTSAC_RISE BM_09_09 -#define TX4927_SIO0_SIDICR0_CTSAC_FALL BM_10_10 -#define TX4927_SIO0_SIDICR0_CTSAC_BOTH BM_09_10 -#define TX4927_SIO0_SIDICR0_RESERVED_06_08 BM_06_08 -#define TX4927_SIO0_SIDICR0_STIE BM_00_05 -#define TX4927_SIO0_SIDICR0_STIE_NONE (~BM_00_05) -#define TX4927_SIO0_SIDICR0_STIE_OERS BM_05_05 -#define TX4927_SIO0_SIDICR0_STIE_CTSAC BM_04_04 -#define TX4927_SIO0_SIDICR0_STIE_RBRKD BM_03_03 -#define TX4927_SIO0_SIDICR0_STIE_TRDY BM_02_02 -#define TX4927_SIO0_SIDICR0_STIE_TXALS BM_01_01 -#define TX4927_SIO0_SIDICR0_STIE_UBRKD BM_00_00 -#define TX4927_SIO0_SIDISR0 0xf308 -#define TX4927_SIO0_SIDISR0_RESERVED_16_31 BM_16_31 -#define TX4927_SIO0_SIDISR0_UBRK BM_15_15 -#define TX4927_SIO0_SIDISR0_UVALID BM_14_14 -#define TX4927_SIO0_SIDISR0_UFER BM_13_13 -#define TX4927_SIO0_SIDISR0_UPER BM_12_12 -#define TX4927_SIO0_SIDISR0_UOER BM_11_11 -#define TX4927_SIO0_SIDISR0_ERI BM_10_10 -#define TX4927_SIO0_SIDISR0_TOUT BM_09_09 -#define TX4927_SIO0_SIDISR0_TDIS BM_08_08 -#define TX4927_SIO0_SIDISR0_RDIS BM_07_07 -#define TX4927_SIO0_SIDISR0_STIS BM_06_06 -#define TX4927_SIO0_SIDISR0_RESERVED_05_05 BM_05_05 -#define TX4927_SIO0_SIDISR0_RFDN BM_00_04 -#define TX4927_SIO0_SISCISR0 0xf30c -#define TX4927_SIO0_SISCISR0_RESERVED_06_31 BM_06_31 -#define TX4927_SIO0_SISCISR0_OERS BM_05_05 -#define TX4927_SIO0_SISCISR0_CTSS BM_04_04 -#define TX4927_SIO0_SISCISR0_RBRKD BM_03_03 -#define TX4927_SIO0_SISCISR0_TRDY BM_02_02 -#define TX4927_SIO0_SISCISR0_TXALS BM_01_01 -#define TX4927_SIO0_SISCISR0_UBRKD BM_00_00 -#define TX4927_SIO0_SIFCR0 0xf310 -#define TX4927_SIO0_SIFCR0_RESERVED_16_31 BM_16_31 -#define TX4927_SIO0_SIFCR0_SWRST BM_16_31 -#define TX4927_SIO0_SIFCR0_RESERVED_09_14 BM_09_14 -#define TX4927_SIO0_SIFCR0_RDIL BM_16_31 -#define TX4927_SIO0_SIFCR0_RDIL_BYTES_1 (~BM_07_08) -#define TX4927_SIO0_SIFCR0_RDIL_BYTES_4 BM_07_07 -#define TX4927_SIO0_SIFCR0_RDIL_BYTES_8 BM_08_08 -#define TX4927_SIO0_SIFCR0_RDIL_BYTES_12 BM_07_08 -#define TX4927_SIO0_SIFCR0_RESERVED_05_06 BM_05_06 -#define TX4927_SIO0_SIFCR0_TDIL BM_03_04 -#define TX4927_SIO0_SIFCR0_TDIL_BYTES_1 (~BM_03_04) -#define TX4927_SIO0_SIFCR0_TDIL_BYTES_4 BM_03_03 -#define TX4927_SIO0_SIFCR0_TDIL_BYTES_8 BM_04_04 -#define TX4927_SIO0_SIFCR0_TDIL_BYTES_0 BM_03_04 -#define TX4927_SIO0_SIFCR0_TFRST BM_02_02 -#define TX4927_SIO0_SIFCR0_RFRST BM_01_01 -#define TX4927_SIO0_SIFCR0_FRSTE BM_00_00 -#define TX4927_SIO0_SIFLCR0 0xf314 -#define TX4927_SIO0_SIFLCR0_RESERVED_13_31 BM_13_31 -#define TX4927_SIO0_SIFLCR0_RCS BM_12_12 -#define TX4927_SIO0_SIFLCR0_TES BM_11_11 -#define TX4927_SIO0_SIFLCR0_RESERVED_10_10 BM_10_10 -#define TX4927_SIO0_SIFLCR0_RTSSC BM_09_09 -#define TX4927_SIO0_SIFLCR0_RSDE BM_08_08 -#define TX4927_SIO0_SIFLCR0_TSDE BM_07_07 -#define TX4927_SIO0_SIFLCR0_RESERVED_05_06 BM_05_06 -#define TX4927_SIO0_SIFLCR0_RTSTL BM_01_04 -#define TX4927_SIO0_SIFLCR0_TBRK BM_00_00 -#define TX4927_SIO0_SIBGR0 0xf318 -#define TX4927_SIO0_SIBGR0_RESERVED_10_31 BM_10_31 -#define TX4927_SIO0_SIBGR0_BCLK BM_08_09 -#define TX4927_SIO0_SIBGR0_BCLK_T0 (~BM_08_09) -#define TX4927_SIO0_SIBGR0_BCLK_T2 BM_08_08 -#define TX4927_SIO0_SIBGR0_BCLK_T4 BM_09_09 -#define TX4927_SIO0_SIBGR0_BCLK_T6 BM_08_09 -#define TX4927_SIO0_SIBGR0_BRD BM_00_07 -#define TX4927_SIO0_SITFIF00 0xf31c -#define TX4927_SIO0_SITFIF00_RESERVED_08_31 BM_08_31 -#define TX4927_SIO0_SITFIF00_TXD BM_00_07 -#define TX4927_SIO0_SIRFIFO0 0xf320 -#define TX4927_SIO0_SIRFIFO0_RESERVED_08_31 BM_08_31 -#define TX4927_SIO0_SIRFIFO0_RXD BM_00_07 -#define TX4927_SIO0_SIRFIFO0 0xf320 -#define TX4927_SIO0_LIMIT 0xf3ff - - -/* TX4927 serial port 1 (32-bit registers) */ -#define TX4927_SIO1_BASE 0xf400 -#define TX4927_SIO1_SILCR1 0xf400 -#define TX4927_SIO1_SIDICR1 0xf404 -#define TX4927_SIO1_SIDISR1 0xf408 -#define TX4927_SIO1_SISCISR1 0xf40c -#define TX4927_SIO1_SIFCR1 0xf410 -#define TX4927_SIO1_SIFLCR1 0xf414 -#define TX4927_SIO1_SIBGR1 0xf418 -#define TX4927_SIO1_SITFIF01 0xf41c -#define TX4927_SIO1_SIRFIFO1 0xf420 -#define TX4927_SIO1_LIMIT 0xf4ff - - -/* TX4927 parallel port (32-bit registers) */ -#define TX4927_PIO_BASE 0xf500 -#define TX4927_PIO_PIOD0 0xf500 -#define TX4927_PIO_PIODI 0xf504 -#define TX4927_PIO_PIODIR 0xf508 -#define TX4927_PIO_PIOOD 0xf50c -#define TX4927_PIO_LIMIT 0xf50f - - -/* TX4927 AC-link controller (32-bit registers) */ -#define TX4927_ACLC_BASE 0xf700 -#define TX4927_ACLC_ACCTLEN 0xf700 -#define TX4927_ACLC_ACCTLDIS 0xf704 -#define TX4927_ACLC_ACREGACC 0xf708 -#define TX4927_ACLC_ACINTSTS 0xf710 -#define TX4927_ACLC_ACINTMSTS 0xf714 -#define TX4927_ACLC_ACINTEN 0xf718 -#define TX4927_ACLC_ACINTDIS 0xf71c -#define TX4927_ACLC_ACSEMAPH 0xf720 -#define TX4927_ACLC_ACGPIDAT 0xf740 -#define TX4927_ACLC_ACGPODAT 0xf744 -#define TX4927_ACLC_ACSLTEN 0xf748 -#define TX4927_ACLC_ACSLTDIS 0xf74c -#define TX4927_ACLC_ACFIFOSTS 0xf750 -#define TX4927_ACLC_ACDMASTS 0xf780 -#define TX4927_ACLC_ACDMASEL 0xf784 -#define TX4927_ACLC_ACAUDODAT 0xf7a0 -#define TX4927_ACLC_ACSURRDAT 0xf7a4 -#define TX4927_ACLC_ACCENTDAT 0xf7a8 -#define TX4927_ACLC_ACLFEDAT 0xf7ac -#define TX4927_ACLC_ACAUDIDAT 0xf7b0 -#define TX4927_ACLC_ACMODODAT 0xf7b8 -#define TX4927_ACLC_ACMODIDAT 0xf7bc -#define TX4927_ACLC_ACREVID 0xf7fc -#define TX4927_ACLC_LIMIT 0xf7ff - - -#define TX4927_REG(x) ((TX4927_BASE)+(x)) - -#define TX4927_RD08( reg ) (*(vu08*)(reg)) -#define TX4927_WR08( reg, val ) ((*(vu08*)(reg))=(val)) - -#define TX4927_RD16( reg ) (*(vu16*)(reg)) -#define TX4927_WR16( reg, val ) ((*(vu16*)(reg))=(val)) - -#define TX4927_RD32( reg ) (*(vu32*)(reg)) -#define TX4927_WR32( reg, val ) ((*(vu32*)(reg))=(val)) - -#define TX4927_RD64( reg ) (*(vu64*)(reg)) -#define TX4927_WR64( reg, val ) ((*(vu64*)(reg))=(val)) - -#define TX4927_RD( reg ) TX4927_RD32( reg ) -#define TX4927_WR( reg, val ) TX4927_WR32( reg, val ) - - #define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE #define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) diff --git a/include/asm-mips/tx4927/tx4927_mips.h b/include/asm-mips/tx4927/tx4927_mips.h deleted file mode 100644 index 242ab93bf2e2..000000000000 --- a/include/asm-mips/tx4927/tx4927_mips.h +++ /dev/null @@ -1,4177 +0,0 @@ -/* - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#ifndef __ASM_TX4927_TX4927_MIPS_H -#define __ASM_TX4927_TX4927_MIPS_H - -#ifndef __ASSEMBLY__ - -static inline void asm_wait(void) -{ - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -#define reg_rd08(r) ((u8 )(*((vu8 *)(r)))) -#define reg_rd16(r) ((u16)(*((vu16*)(r)))) -#define reg_rd32(r) ((u32)(*((vu32*)(r)))) -#define reg_rd64(r) ((u64)(*((vu64*)(r)))) - -#define reg_wr08(r,v) ((*((vu8 *)(r)))=((u8 )(v))) -#define reg_wr16(r,v) ((*((vu16*)(r)))=((u16)(v))) -#define reg_wr32(r,v) ((*((vu32*)(r)))=((u32)(v))) -#define reg_wr64(r,v) ((*((vu64*)(r)))=((u64)(v))) - -typedef volatile __signed char vs8; -typedef volatile unsigned char vu8; - -typedef volatile __signed short vs16; -typedef volatile unsigned short vu16; - -typedef volatile __signed int vs32; -typedef volatile unsigned int vu32; - -typedef s8 s08; -typedef vs8 vs08; - -typedef u8 u08; -typedef vu8 vu08; - - -#if (_MIPS_SZLONG == 64) - -typedef volatile __signed__ long vs64; -typedef volatile unsigned long vu64; - -#else - -typedef volatile __signed__ long long vs64; -typedef volatile unsigned long long vu64; - -#endif - - -#define BM_00_00 0x0000000000000001 -#define BM_01_00 0x0000000000000003 -#define BM_00_01 BM_01_00 -#define BM_02_00 0x0000000000000007 -#define BM_00_02 BM_02_00 -#define BM_03_00 0x000000000000000f -#define BM_00_03 BM_03_00 -#define BM_04_00 0x000000000000001f -#define BM_00_04 BM_04_00 -#define BM_05_00 0x000000000000003f -#define BM_00_05 BM_05_00 -#define BM_06_00 0x000000000000007f -#define BM_00_06 BM_06_00 -#define BM_07_00 0x00000000000000ff -#define BM_00_07 BM_07_00 -#define BM_08_00 0x00000000000001ff -#define BM_00_08 BM_08_00 -#define BM_09_00 0x00000000000003ff -#define BM_00_09 BM_09_00 -#define BM_10_00 0x00000000000007ff -#define BM_00_10 BM_10_00 -#define BM_11_00 0x0000000000000fff -#define BM_00_11 BM_11_00 -#define BM_12_00 0x0000000000001fff -#define BM_00_12 BM_12_00 -#define BM_13_00 0x0000000000003fff -#define BM_00_13 BM_13_00 -#define BM_14_00 0x0000000000007fff -#define BM_00_14 BM_14_00 -#define BM_15_00 0x000000000000ffff -#define BM_00_15 BM_15_00 -#define BM_16_00 0x000000000001ffff -#define BM_00_16 BM_16_00 -#define BM_17_00 0x000000000003ffff -#define BM_00_17 BM_17_00 -#define BM_18_00 0x000000000007ffff -#define BM_00_18 BM_18_00 -#define BM_19_00 0x00000000000fffff -#define BM_00_19 BM_19_00 -#define BM_20_00 0x00000000001fffff -#define BM_00_20 BM_20_00 -#define BM_21_00 0x00000000003fffff -#define BM_00_21 BM_21_00 -#define BM_22_00 0x00000000007fffff -#define BM_00_22 BM_22_00 -#define BM_23_00 0x0000000000ffffff -#define BM_00_23 BM_23_00 -#define BM_24_00 0x0000000001ffffff -#define BM_00_24 BM_24_00 -#define BM_25_00 0x0000000003ffffff -#define BM_00_25 BM_25_00 -#define BM_26_00 0x0000000007ffffff -#define BM_00_26 BM_26_00 -#define BM_27_00 0x000000000fffffff -#define BM_00_27 BM_27_00 -#define BM_28_00 0x000000001fffffff -#define BM_00_28 BM_28_00 -#define BM_29_00 0x000000003fffffff -#define BM_00_29 BM_29_00 -#define BM_30_00 0x000000007fffffff -#define BM_00_30 BM_30_00 -#define BM_31_00 0x00000000ffffffff -#define BM_00_31 BM_31_00 -#define BM_32_00 0x00000001ffffffff -#define BM_00_32 BM_32_00 -#define BM_33_00 0x00000003ffffffff -#define BM_00_33 BM_33_00 -#define BM_34_00 0x00000007ffffffff -#define BM_00_34 BM_34_00 -#define BM_35_00 0x0000000fffffffff -#define BM_00_35 BM_35_00 -#define BM_36_00 0x0000001fffffffff -#define BM_00_36 BM_36_00 -#define BM_37_00 0x0000003fffffffff -#define BM_00_37 BM_37_00 -#define BM_38_00 0x0000007fffffffff -#define BM_00_38 BM_38_00 -#define BM_39_00 0x000000ffffffffff -#define BM_00_39 BM_39_00 -#define BM_40_00 0x000001ffffffffff -#define BM_00_40 BM_40_00 -#define BM_41_00 0x000003ffffffffff -#define BM_00_41 BM_41_00 -#define BM_42_00 0x000007ffffffffff -#define BM_00_42 BM_42_00 -#define BM_43_00 0x00000fffffffffff -#define BM_00_43 BM_43_00 -#define BM_44_00 0x00001fffffffffff -#define BM_00_44 BM_44_00 -#define BM_45_00 0x00003fffffffffff -#define BM_00_45 BM_45_00 -#define BM_46_00 0x00007fffffffffff -#define BM_00_46 BM_46_00 -#define BM_47_00 0x0000ffffffffffff -#define BM_00_47 BM_47_00 -#define BM_48_00 0x0001ffffffffffff -#define BM_00_48 BM_48_00 -#define BM_49_00 0x0003ffffffffffff -#define BM_00_49 BM_49_00 -#define BM_50_00 0x0007ffffffffffff -#define BM_00_50 BM_50_00 -#define BM_51_00 0x000fffffffffffff -#define BM_00_51 BM_51_00 -#define BM_52_00 0x001fffffffffffff -#define BM_00_52 BM_52_00 -#define BM_53_00 0x003fffffffffffff -#define BM_00_53 BM_53_00 -#define BM_54_00 0x007fffffffffffff -#define BM_00_54 BM_54_00 -#define BM_55_00 0x00ffffffffffffff -#define BM_00_55 BM_55_00 -#define BM_56_00 0x01ffffffffffffff -#define BM_00_56 BM_56_00 -#define BM_57_00 0x03ffffffffffffff -#define BM_00_57 BM_57_00 -#define BM_58_00 0x07ffffffffffffff -#define BM_00_58 BM_58_00 -#define BM_59_00 0x0fffffffffffffff -#define BM_00_59 BM_59_00 -#define BM_60_00 0x1fffffffffffffff -#define BM_00_60 BM_60_00 -#define BM_61_00 0x3fffffffffffffff -#define BM_00_61 BM_61_00 -#define BM_62_00 0x7fffffffffffffff -#define BM_00_62 BM_62_00 -#define BM_63_00 0xffffffffffffffff -#define BM_00_63 BM_63_00 -#define BM_01_01 0x0000000000000002 -#define BM_02_01 0x0000000000000006 -#define BM_01_02 BM_02_01 -#define BM_03_01 0x000000000000000e -#define BM_01_03 BM_03_01 -#define BM_04_01 0x000000000000001e -#define BM_01_04 BM_04_01 -#define BM_05_01 0x000000000000003e -#define BM_01_05 BM_05_01 -#define BM_06_01 0x000000000000007e -#define BM_01_06 BM_06_01 -#define BM_07_01 0x00000000000000fe -#define BM_01_07 BM_07_01 -#define BM_08_01 0x00000000000001fe -#define BM_01_08 BM_08_01 -#define BM_09_01 0x00000000000003fe -#define BM_01_09 BM_09_01 -#define BM_10_01 0x00000000000007fe -#define BM_01_10 BM_10_01 -#define BM_11_01 0x0000000000000ffe -#define BM_01_11 BM_11_01 -#define BM_12_01 0x0000000000001ffe -#define BM_01_12 BM_12_01 -#define BM_13_01 0x0000000000003ffe -#define BM_01_13 BM_13_01 -#define BM_14_01 0x0000000000007ffe -#define BM_01_14 BM_14_01 -#define BM_15_01 0x000000000000fffe -#define BM_01_15 BM_15_01 -#define BM_16_01 0x000000000001fffe -#define BM_01_16 BM_16_01 -#define BM_17_01 0x000000000003fffe -#define BM_01_17 BM_17_01 -#define BM_18_01 0x000000000007fffe -#define BM_01_18 BM_18_01 -#define BM_19_01 0x00000000000ffffe -#define BM_01_19 BM_19_01 -#define BM_20_01 0x00000000001ffffe -#define BM_01_20 BM_20_01 -#define BM_21_01 0x00000000003ffffe -#define BM_01_21 BM_21_01 -#define BM_22_01 0x00000000007ffffe -#define BM_01_22 BM_22_01 -#define BM_23_01 0x0000000000fffffe -#define BM_01_23 BM_23_01 -#define BM_24_01 0x0000000001fffffe -#define BM_01_24 BM_24_01 -#define BM_25_01 0x0000000003fffffe -#define BM_01_25 BM_25_01 -#define BM_26_01 0x0000000007fffffe -#define BM_01_26 BM_26_01 -#define BM_27_01 0x000000000ffffffe -#define BM_01_27 BM_27_01 -#define BM_28_01 0x000000001ffffffe -#define BM_01_28 BM_28_01 -#define BM_29_01 0x000000003ffffffe -#define BM_01_29 BM_29_01 -#define BM_30_01 0x000000007ffffffe -#define BM_01_30 BM_30_01 -#define BM_31_01 0x00000000fffffffe -#define BM_01_31 BM_31_01 -#define BM_32_01 0x00000001fffffffe -#define BM_01_32 BM_32_01 -#define BM_33_01 0x00000003fffffffe -#define BM_01_33 BM_33_01 -#define BM_34_01 0x00000007fffffffe -#define BM_01_34 BM_34_01 -#define BM_35_01 0x0000000ffffffffe -#define BM_01_35 BM_35_01 -#define BM_36_01 0x0000001ffffffffe -#define BM_01_36 BM_36_01 -#define BM_37_01 0x0000003ffffffffe -#define BM_01_37 BM_37_01 -#define BM_38_01 0x0000007ffffffffe -#define BM_01_38 BM_38_01 -#define BM_39_01 0x000000fffffffffe -#define BM_01_39 BM_39_01 -#define BM_40_01 0x000001fffffffffe -#define BM_01_40 BM_40_01 -#define BM_41_01 0x000003fffffffffe -#define BM_01_41 BM_41_01 -#define BM_42_01 0x000007fffffffffe -#define BM_01_42 BM_42_01 -#define BM_43_01 0x00000ffffffffffe -#define BM_01_43 BM_43_01 -#define BM_44_01 0x00001ffffffffffe -#define BM_01_44 BM_44_01 -#define BM_45_01 0x00003ffffffffffe -#define BM_01_45 BM_45_01 -#define BM_46_01 0x00007ffffffffffe -#define BM_01_46 BM_46_01 -#define BM_47_01 0x0000fffffffffffe -#define BM_01_47 BM_47_01 -#define BM_48_01 0x0001fffffffffffe -#define BM_01_48 BM_48_01 -#define BM_49_01 0x0003fffffffffffe -#define BM_01_49 BM_49_01 -#define BM_50_01 0x0007fffffffffffe -#define BM_01_50 BM_50_01 -#define BM_51_01 0x000ffffffffffffe -#define BM_01_51 BM_51_01 -#define BM_52_01 0x001ffffffffffffe -#define BM_01_52 BM_52_01 -#define BM_53_01 0x003ffffffffffffe -#define BM_01_53 BM_53_01 -#define BM_54_01 0x007ffffffffffffe -#define BM_01_54 BM_54_01 -#define BM_55_01 0x00fffffffffffffe -#define BM_01_55 BM_55_01 -#define BM_56_01 0x01fffffffffffffe -#define BM_01_56 BM_56_01 -#define BM_57_01 0x03fffffffffffffe -#define BM_01_57 BM_57_01 -#define BM_58_01 0x07fffffffffffffe -#define BM_01_58 BM_58_01 -#define BM_59_01 0x0ffffffffffffffe -#define BM_01_59 BM_59_01 -#define BM_60_01 0x1ffffffffffffffe -#define BM_01_60 BM_60_01 -#define BM_61_01 0x3ffffffffffffffe -#define BM_01_61 BM_61_01 -#define BM_62_01 0x7ffffffffffffffe -#define BM_01_62 BM_62_01 -#define BM_63_01 0xfffffffffffffffe -#define BM_01_63 BM_63_01 -#define BM_02_02 0x0000000000000004 -#define BM_03_02 0x000000000000000c -#define BM_02_03 BM_03_02 -#define BM_04_02 0x000000000000001c -#define BM_02_04 BM_04_02 -#define BM_05_02 0x000000000000003c -#define BM_02_05 BM_05_02 -#define BM_06_02 0x000000000000007c -#define BM_02_06 BM_06_02 -#define BM_07_02 0x00000000000000fc -#define BM_02_07 BM_07_02 -#define BM_08_02 0x00000000000001fc -#define BM_02_08 BM_08_02 -#define BM_09_02 0x00000000000003fc -#define BM_02_09 BM_09_02 -#define BM_10_02 0x00000000000007fc -#define BM_02_10 BM_10_02 -#define BM_11_02 0x0000000000000ffc -#define BM_02_11 BM_11_02 -#define BM_12_02 0x0000000000001ffc -#define BM_02_12 BM_12_02 -#define BM_13_02 0x0000000000003ffc -#define BM_02_13 BM_13_02 -#define BM_14_02 0x0000000000007ffc -#define BM_02_14 BM_14_02 -#define BM_15_02 0x000000000000fffc -#define BM_02_15 BM_15_02 -#define BM_16_02 0x000000000001fffc -#define BM_02_16 BM_16_02 -#define BM_17_02 0x000000000003fffc -#define BM_02_17 BM_17_02 -#define BM_18_02 0x000000000007fffc -#define BM_02_18 BM_18_02 -#define BM_19_02 0x00000000000ffffc -#define BM_02_19 BM_19_02 -#define BM_20_02 0x00000000001ffffc -#define BM_02_20 BM_20_02 -#define BM_21_02 0x00000000003ffffc -#define BM_02_21 BM_21_02 -#define BM_22_02 0x00000000007ffffc -#define BM_02_22 BM_22_02 -#define BM_23_02 0x0000000000fffffc -#define BM_02_23 BM_23_02 -#define BM_24_02 0x0000000001fffffc -#define BM_02_24 BM_24_02 -#define BM_25_02 0x0000000003fffffc -#define BM_02_25 BM_25_02 -#define BM_26_02 0x0000000007fffffc -#define BM_02_26 BM_26_02 -#define BM_27_02 0x000000000ffffffc -#define BM_02_27 BM_27_02 -#define BM_28_02 0x000000001ffffffc -#define BM_02_28 BM_28_02 -#define BM_29_02 0x000000003ffffffc -#define BM_02_29 BM_29_02 -#define BM_30_02 0x000000007ffffffc -#define BM_02_30 BM_30_02 -#define BM_31_02 0x00000000fffffffc -#define BM_02_31 BM_31_02 -#define BM_32_02 0x00000001fffffffc -#define BM_02_32 BM_32_02 -#define BM_33_02 0x00000003fffffffc -#define BM_02_33 BM_33_02 -#define BM_34_02 0x00000007fffffffc -#define BM_02_34 BM_34_02 -#define BM_35_02 0x0000000ffffffffc -#define BM_02_35 BM_35_02 -#define BM_36_02 0x0000001ffffffffc -#define BM_02_36 BM_36_02 -#define BM_37_02 0x0000003ffffffffc -#define BM_02_37 BM_37_02 -#define BM_38_02 0x0000007ffffffffc -#define BM_02_38 BM_38_02 -#define BM_39_02 0x000000fffffffffc -#define BM_02_39 BM_39_02 -#define BM_40_02 0x000001fffffffffc -#define BM_02_40 BM_40_02 -#define BM_41_02 0x000003fffffffffc -#define BM_02_41 BM_41_02 -#define BM_42_02 0x000007fffffffffc -#define BM_02_42 BM_42_02 -#define BM_43_02 0x00000ffffffffffc -#define BM_02_43 BM_43_02 -#define BM_44_02 0x00001ffffffffffc -#define BM_02_44 BM_44_02 -#define BM_45_02 0x00003ffffffffffc -#define BM_02_45 BM_45_02 -#define BM_46_02 0x00007ffffffffffc -#define BM_02_46 BM_46_02 -#define BM_47_02 0x0000fffffffffffc -#define BM_02_47 BM_47_02 -#define BM_48_02 0x0001fffffffffffc -#define BM_02_48 BM_48_02 -#define BM_49_02 0x0003fffffffffffc -#define BM_02_49 BM_49_02 -#define BM_50_02 0x0007fffffffffffc -#define BM_02_50 BM_50_02 -#define BM_51_02 0x000ffffffffffffc -#define BM_02_51 BM_51_02 -#define BM_52_02 0x001ffffffffffffc -#define BM_02_52 BM_52_02 -#define BM_53_02 0x003ffffffffffffc -#define BM_02_53 BM_53_02 -#define BM_54_02 0x007ffffffffffffc -#define BM_02_54 BM_54_02 -#define BM_55_02 0x00fffffffffffffc -#define BM_02_55 BM_55_02 -#define BM_56_02 0x01fffffffffffffc -#define BM_02_56 BM_56_02 -#define BM_57_02 0x03fffffffffffffc -#define BM_02_57 BM_57_02 -#define BM_58_02 0x07fffffffffffffc -#define BM_02_58 BM_58_02 -#define BM_59_02 0x0ffffffffffffffc -#define BM_02_59 BM_59_02 -#define BM_60_02 0x1ffffffffffffffc -#define BM_02_60 BM_60_02 -#define BM_61_02 0x3ffffffffffffffc -#define BM_02_61 BM_61_02 -#define BM_62_02 0x7ffffffffffffffc -#define BM_02_62 BM_62_02 -#define BM_63_02 0xfffffffffffffffc -#define BM_02_63 BM_63_02 -#define BM_03_03 0x0000000000000008 -#define BM_04_03 0x0000000000000018 -#define BM_03_04 BM_04_03 -#define BM_05_03 0x0000000000000038 -#define BM_03_05 BM_05_03 -#define BM_06_03 0x0000000000000078 -#define BM_03_06 BM_06_03 -#define BM_07_03 0x00000000000000f8 -#define BM_03_07 BM_07_03 -#define BM_08_03 0x00000000000001f8 -#define BM_03_08 BM_08_03 -#define BM_09_03 0x00000000000003f8 -#define BM_03_09 BM_09_03 -#define BM_10_03 0x00000000000007f8 -#define BM_03_10 BM_10_03 -#define BM_11_03 0x0000000000000ff8 -#define BM_03_11 BM_11_03 -#define BM_12_03 0x0000000000001ff8 -#define BM_03_12 BM_12_03 -#define BM_13_03 0x0000000000003ff8 -#define BM_03_13 BM_13_03 -#define BM_14_03 0x0000000000007ff8 -#define BM_03_14 BM_14_03 -#define BM_15_03 0x000000000000fff8 -#define BM_03_15 BM_15_03 -#define BM_16_03 0x000000000001fff8 -#define BM_03_16 BM_16_03 -#define BM_17_03 0x000000000003fff8 -#define BM_03_17 BM_17_03 -#define BM_18_03 0x000000000007fff8 -#define BM_03_18 BM_18_03 -#define BM_19_03 0x00000000000ffff8 -#define BM_03_19 BM_19_03 -#define BM_20_03 0x00000000001ffff8 -#define BM_03_20 BM_20_03 -#define BM_21_03 0x00000000003ffff8 -#define BM_03_21 BM_21_03 -#define BM_22_03 0x00000000007ffff8 -#define BM_03_22 BM_22_03 -#define BM_23_03 0x0000000000fffff8 -#define BM_03_23 BM_23_03 -#define BM_24_03 0x0000000001fffff8 -#define BM_03_24 BM_24_03 -#define BM_25_03 0x0000000003fffff8 -#define BM_03_25 BM_25_03 -#define BM_26_03 0x0000000007fffff8 -#define BM_03_26 BM_26_03 -#define BM_27_03 0x000000000ffffff8 -#define BM_03_27 BM_27_03 -#define BM_28_03 0x000000001ffffff8 -#define BM_03_28 BM_28_03 -#define BM_29_03 0x000000003ffffff8 -#define BM_03_29 BM_29_03 -#define BM_30_03 0x000000007ffffff8 -#define BM_03_30 BM_30_03 -#define BM_31_03 0x00000000fffffff8 -#define BM_03_31 BM_31_03 -#define BM_32_03 0x00000001fffffff8 -#define BM_03_32 BM_32_03 -#define BM_33_03 0x00000003fffffff8 -#define BM_03_33 BM_33_03 -#define BM_34_03 0x00000007fffffff8 -#define BM_03_34 BM_34_03 -#define BM_35_03 0x0000000ffffffff8 -#define BM_03_35 BM_35_03 -#define BM_36_03 0x0000001ffffffff8 -#define BM_03_36 BM_36_03 -#define BM_37_03 0x0000003ffffffff8 -#define BM_03_37 BM_37_03 -#define BM_38_03 0x0000007ffffffff8 -#define BM_03_38 BM_38_03 -#define BM_39_03 0x000000fffffffff8 -#define BM_03_39 BM_39_03 -#define BM_40_03 0x000001fffffffff8 -#define BM_03_40 BM_40_03 -#define BM_41_03 0x000003fffffffff8 -#define BM_03_41 BM_41_03 -#define BM_42_03 0x000007fffffffff8 -#define BM_03_42 BM_42_03 -#define BM_43_03 0x00000ffffffffff8 -#define BM_03_43 BM_43_03 -#define BM_44_03 0x00001ffffffffff8 -#define BM_03_44 BM_44_03 -#define BM_45_03 0x00003ffffffffff8 -#define BM_03_45 BM_45_03 -#define BM_46_03 0x00007ffffffffff8 -#define BM_03_46 BM_46_03 -#define BM_47_03 0x0000fffffffffff8 -#define BM_03_47 BM_47_03 -#define BM_48_03 0x0001fffffffffff8 -#define BM_03_48 BM_48_03 -#define BM_49_03 0x0003fffffffffff8 -#define BM_03_49 BM_49_03 -#define BM_50_03 0x0007fffffffffff8 -#define BM_03_50 BM_50_03 -#define BM_51_03 0x000ffffffffffff8 -#define BM_03_51 BM_51_03 -#define BM_52_03 0x001ffffffffffff8 -#define BM_03_52 BM_52_03 -#define BM_53_03 0x003ffffffffffff8 -#define BM_03_53 BM_53_03 -#define BM_54_03 0x007ffffffffffff8 -#define BM_03_54 BM_54_03 -#define BM_55_03 0x00fffffffffffff8 -#define BM_03_55 BM_55_03 -#define BM_56_03 0x01fffffffffffff8 -#define BM_03_56 BM_56_03 -#define BM_57_03 0x03fffffffffffff8 -#define BM_03_57 BM_57_03 -#define BM_58_03 0x07fffffffffffff8 -#define BM_03_58 BM_58_03 -#define BM_59_03 0x0ffffffffffffff8 -#define BM_03_59 BM_59_03 -#define BM_60_03 0x1ffffffffffffff8 -#define BM_03_60 BM_60_03 -#define BM_61_03 0x3ffffffffffffff8 -#define BM_03_61 BM_61_03 -#define BM_62_03 0x7ffffffffffffff8 -#define BM_03_62 BM_62_03 -#define BM_63_03 0xfffffffffffffff8 -#define BM_03_63 BM_63_03 -#define BM_04_04 0x0000000000000010 -#define BM_05_04 0x0000000000000030 -#define BM_04_05 BM_05_04 -#define BM_06_04 0x0000000000000070 -#define BM_04_06 BM_06_04 -#define BM_07_04 0x00000000000000f0 -#define BM_04_07 BM_07_04 -#define BM_08_04 0x00000000000001f0 -#define BM_04_08 BM_08_04 -#define BM_09_04 0x00000000000003f0 -#define BM_04_09 BM_09_04 -#define BM_10_04 0x00000000000007f0 -#define BM_04_10 BM_10_04 -#define BM_11_04 0x0000000000000ff0 -#define BM_04_11 BM_11_04 -#define BM_12_04 0x0000000000001ff0 -#define BM_04_12 BM_12_04 -#define BM_13_04 0x0000000000003ff0 -#define BM_04_13 BM_13_04 -#define BM_14_04 0x0000000000007ff0 -#define BM_04_14 BM_14_04 -#define BM_15_04 0x000000000000fff0 -#define BM_04_15 BM_15_04 -#define BM_16_04 0x000000000001fff0 -#define BM_04_16 BM_16_04 -#define BM_17_04 0x000000000003fff0 -#define BM_04_17 BM_17_04 -#define BM_18_04 0x000000000007fff0 -#define BM_04_18 BM_18_04 -#define BM_19_04 0x00000000000ffff0 -#define BM_04_19 BM_19_04 -#define BM_20_04 0x00000000001ffff0 -#define BM_04_20 BM_20_04 -#define BM_21_04 0x00000000003ffff0 -#define BM_04_21 BM_21_04 -#define BM_22_04 0x00000000007ffff0 -#define BM_04_22 BM_22_04 -#define BM_23_04 0x0000000000fffff0 -#define BM_04_23 BM_23_04 -#define BM_24_04 0x0000000001fffff0 -#define BM_04_24 BM_24_04 -#define BM_25_04 0x0000000003fffff0 -#define BM_04_25 BM_25_04 -#define BM_26_04 0x0000000007fffff0 -#define BM_04_26 BM_26_04 -#define BM_27_04 0x000000000ffffff0 -#define BM_04_27 BM_27_04 -#define BM_28_04 0x000000001ffffff0 -#define BM_04_28 BM_28_04 -#define BM_29_04 0x000000003ffffff0 -#define BM_04_29 BM_29_04 -#define BM_30_04 0x000000007ffffff0 -#define BM_04_30 BM_30_04 -#define BM_31_04 0x00000000fffffff0 -#define BM_04_31 BM_31_04 -#define BM_32_04 0x00000001fffffff0 -#define BM_04_32 BM_32_04 -#define BM_33_04 0x00000003fffffff0 -#define BM_04_33 BM_33_04 -#define BM_34_04 0x00000007fffffff0 -#define BM_04_34 BM_34_04 -#define BM_35_04 0x0000000ffffffff0 -#define BM_04_35 BM_35_04 -#define BM_36_04 0x0000001ffffffff0 -#define BM_04_36 BM_36_04 -#define BM_37_04 0x0000003ffffffff0 -#define BM_04_37 BM_37_04 -#define BM_38_04 0x0000007ffffffff0 -#define BM_04_38 BM_38_04 -#define BM_39_04 0x000000fffffffff0 -#define BM_04_39 BM_39_04 -#define BM_40_04 0x000001fffffffff0 -#define BM_04_40 BM_40_04 -#define BM_41_04 0x000003fffffffff0 -#define BM_04_41 BM_41_04 -#define BM_42_04 0x000007fffffffff0 -#define BM_04_42 BM_42_04 -#define BM_43_04 0x00000ffffffffff0 -#define BM_04_43 BM_43_04 -#define BM_44_04 0x00001ffffffffff0 -#define BM_04_44 BM_44_04 -#define BM_45_04 0x00003ffffffffff0 -#define BM_04_45 BM_45_04 -#define BM_46_04 0x00007ffffffffff0 -#define BM_04_46 BM_46_04 -#define BM_47_04 0x0000fffffffffff0 -#define BM_04_47 BM_47_04 -#define BM_48_04 0x0001fffffffffff0 -#define BM_04_48 BM_48_04 -#define BM_49_04 0x0003fffffffffff0 -#define BM_04_49 BM_49_04 -#define BM_50_04 0x0007fffffffffff0 -#define BM_04_50 BM_50_04 -#define BM_51_04 0x000ffffffffffff0 -#define BM_04_51 BM_51_04 -#define BM_52_04 0x001ffffffffffff0 -#define BM_04_52 BM_52_04 -#define BM_53_04 0x003ffffffffffff0 -#define BM_04_53 BM_53_04 -#define BM_54_04 0x007ffffffffffff0 -#define BM_04_54 BM_54_04 -#define BM_55_04 0x00fffffffffffff0 -#define BM_04_55 BM_55_04 -#define BM_56_04 0x01fffffffffffff0 -#define BM_04_56 BM_56_04 -#define BM_57_04 0x03fffffffffffff0 -#define BM_04_57 BM_57_04 -#define BM_58_04 0x07fffffffffffff0 -#define BM_04_58 BM_58_04 -#define BM_59_04 0x0ffffffffffffff0 -#define BM_04_59 BM_59_04 -#define BM_60_04 0x1ffffffffffffff0 -#define BM_04_60 BM_60_04 -#define BM_61_04 0x3ffffffffffffff0 -#define BM_04_61 BM_61_04 -#define BM_62_04 0x7ffffffffffffff0 -#define BM_04_62 BM_62_04 -#define BM_63_04 0xfffffffffffffff0 -#define BM_04_63 BM_63_04 -#define BM_05_05 0x0000000000000020 -#define BM_06_05 0x0000000000000060 -#define BM_05_06 BM_06_05 -#define BM_07_05 0x00000000000000e0 -#define BM_05_07 BM_07_05 -#define BM_08_05 0x00000000000001e0 -#define BM_05_08 BM_08_05 -#define BM_09_05 0x00000000000003e0 -#define BM_05_09 BM_09_05 -#define BM_10_05 0x00000000000007e0 -#define BM_05_10 BM_10_05 -#define BM_11_05 0x0000000000000fe0 -#define BM_05_11 BM_11_05 -#define BM_12_05 0x0000000000001fe0 -#define BM_05_12 BM_12_05 -#define BM_13_05 0x0000000000003fe0 -#define BM_05_13 BM_13_05 -#define BM_14_05 0x0000000000007fe0 -#define BM_05_14 BM_14_05 -#define BM_15_05 0x000000000000ffe0 -#define BM_05_15 BM_15_05 -#define BM_16_05 0x000000000001ffe0 -#define BM_05_16 BM_16_05 -#define BM_17_05 0x000000000003ffe0 -#define BM_05_17 BM_17_05 -#define BM_18_05 0x000000000007ffe0 -#define BM_05_18 BM_18_05 -#define BM_19_05 0x00000000000fffe0 -#define BM_05_19 BM_19_05 -#define BM_20_05 0x00000000001fffe0 -#define BM_05_20 BM_20_05 -#define BM_21_05 0x00000000003fffe0 -#define BM_05_21 BM_21_05 -#define BM_22_05 0x00000000007fffe0 -#define BM_05_22 BM_22_05 -#define BM_23_05 0x0000000000ffffe0 -#define BM_05_23 BM_23_05 -#define BM_24_05 0x0000000001ffffe0 -#define BM_05_24 BM_24_05 -#define BM_25_05 0x0000000003ffffe0 -#define BM_05_25 BM_25_05 -#define BM_26_05 0x0000000007ffffe0 -#define BM_05_26 BM_26_05 -#define BM_27_05 0x000000000fffffe0 -#define BM_05_27 BM_27_05 -#define BM_28_05 0x000000001fffffe0 -#define BM_05_28 BM_28_05 -#define BM_29_05 0x000000003fffffe0 -#define BM_05_29 BM_29_05 -#define BM_30_05 0x000000007fffffe0 -#define BM_05_30 BM_30_05 -#define BM_31_05 0x00000000ffffffe0 -#define BM_05_31 BM_31_05 -#define BM_32_05 0x00000001ffffffe0 -#define BM_05_32 BM_32_05 -#define BM_33_05 0x00000003ffffffe0 -#define BM_05_33 BM_33_05 -#define BM_34_05 0x00000007ffffffe0 -#define BM_05_34 BM_34_05 -#define BM_35_05 0x0000000fffffffe0 -#define BM_05_35 BM_35_05 -#define BM_36_05 0x0000001fffffffe0 -#define BM_05_36 BM_36_05 -#define BM_37_05 0x0000003fffffffe0 -#define BM_05_37 BM_37_05 -#define BM_38_05 0x0000007fffffffe0 -#define BM_05_38 BM_38_05 -#define BM_39_05 0x000000ffffffffe0 -#define BM_05_39 BM_39_05 -#define BM_40_05 0x000001ffffffffe0 -#define BM_05_40 BM_40_05 -#define BM_41_05 0x000003ffffffffe0 -#define BM_05_41 BM_41_05 -#define BM_42_05 0x000007ffffffffe0 -#define BM_05_42 BM_42_05 -#define BM_43_05 0x00000fffffffffe0 -#define BM_05_43 BM_43_05 -#define BM_44_05 0x00001fffffffffe0 -#define BM_05_44 BM_44_05 -#define BM_45_05 0x00003fffffffffe0 -#define BM_05_45 BM_45_05 -#define BM_46_05 0x00007fffffffffe0 -#define BM_05_46 BM_46_05 -#define BM_47_05 0x0000ffffffffffe0 -#define BM_05_47 BM_47_05 -#define BM_48_05 0x0001ffffffffffe0 -#define BM_05_48 BM_48_05 -#define BM_49_05 0x0003ffffffffffe0 -#define BM_05_49 BM_49_05 -#define BM_50_05 0x0007ffffffffffe0 -#define BM_05_50 BM_50_05 -#define BM_51_05 0x000fffffffffffe0 -#define BM_05_51 BM_51_05 -#define BM_52_05 0x001fffffffffffe0 -#define BM_05_52 BM_52_05 -#define BM_53_05 0x003fffffffffffe0 -#define BM_05_53 BM_53_05 -#define BM_54_05 0x007fffffffffffe0 -#define BM_05_54 BM_54_05 -#define BM_55_05 0x00ffffffffffffe0 -#define BM_05_55 BM_55_05 -#define BM_56_05 0x01ffffffffffffe0 -#define BM_05_56 BM_56_05 -#define BM_57_05 0x03ffffffffffffe0 -#define BM_05_57 BM_57_05 -#define BM_58_05 0x07ffffffffffffe0 -#define BM_05_58 BM_58_05 -#define BM_59_05 0x0fffffffffffffe0 -#define BM_05_59 BM_59_05 -#define BM_60_05 0x1fffffffffffffe0 -#define BM_05_60 BM_60_05 -#define BM_61_05 0x3fffffffffffffe0 -#define BM_05_61 BM_61_05 -#define BM_62_05 0x7fffffffffffffe0 -#define BM_05_62 BM_62_05 -#define BM_63_05 0xffffffffffffffe0 -#define BM_05_63 BM_63_05 -#define BM_06_06 0x0000000000000040 -#define BM_07_06 0x00000000000000c0 -#define BM_06_07 BM_07_06 -#define BM_08_06 0x00000000000001c0 -#define BM_06_08 BM_08_06 -#define BM_09_06 0x00000000000003c0 -#define BM_06_09 BM_09_06 -#define BM_10_06 0x00000000000007c0 -#define BM_06_10 BM_10_06 -#define BM_11_06 0x0000000000000fc0 -#define BM_06_11 BM_11_06 -#define BM_12_06 0x0000000000001fc0 -#define BM_06_12 BM_12_06 -#define BM_13_06 0x0000000000003fc0 -#define BM_06_13 BM_13_06 -#define BM_14_06 0x0000000000007fc0 -#define BM_06_14 BM_14_06 -#define BM_15_06 0x000000000000ffc0 -#define BM_06_15 BM_15_06 -#define BM_16_06 0x000000000001ffc0 -#define BM_06_16 BM_16_06 -#define BM_17_06 0x000000000003ffc0 -#define BM_06_17 BM_17_06 -#define BM_18_06 0x000000000007ffc0 -#define BM_06_18 BM_18_06 -#define BM_19_06 0x00000000000fffc0 -#define BM_06_19 BM_19_06 -#define BM_20_06 0x00000000001fffc0 -#define BM_06_20 BM_20_06 -#define BM_21_06 0x00000000003fffc0 -#define BM_06_21 BM_21_06 -#define BM_22_06 0x00000000007fffc0 -#define BM_06_22 BM_22_06 -#define BM_23_06 0x0000000000ffffc0 -#define BM_06_23 BM_23_06 -#define BM_24_06 0x0000000001ffffc0 -#define BM_06_24 BM_24_06 -#define BM_25_06 0x0000000003ffffc0 -#define BM_06_25 BM_25_06 -#define BM_26_06 0x0000000007ffffc0 -#define BM_06_26 BM_26_06 -#define BM_27_06 0x000000000fffffc0 -#define BM_06_27 BM_27_06 -#define BM_28_06 0x000000001fffffc0 -#define BM_06_28 BM_28_06 -#define BM_29_06 0x000000003fffffc0 -#define BM_06_29 BM_29_06 -#define BM_30_06 0x000000007fffffc0 -#define BM_06_30 BM_30_06 -#define BM_31_06 0x00000000ffffffc0 -#define BM_06_31 BM_31_06 -#define BM_32_06 0x00000001ffffffc0 -#define BM_06_32 BM_32_06 -#define BM_33_06 0x00000003ffffffc0 -#define BM_06_33 BM_33_06 -#define BM_34_06 0x00000007ffffffc0 -#define BM_06_34 BM_34_06 -#define BM_35_06 0x0000000fffffffc0 -#define BM_06_35 BM_35_06 -#define BM_36_06 0x0000001fffffffc0 -#define BM_06_36 BM_36_06 -#define BM_37_06 0x0000003fffffffc0 -#define BM_06_37 BM_37_06 -#define BM_38_06 0x0000007fffffffc0 -#define BM_06_38 BM_38_06 -#define BM_39_06 0x000000ffffffffc0 -#define BM_06_39 BM_39_06 -#define BM_40_06 0x000001ffffffffc0 -#define BM_06_40 BM_40_06 -#define BM_41_06 0x000003ffffffffc0 -#define BM_06_41 BM_41_06 -#define BM_42_06 0x000007ffffffffc0 -#define BM_06_42 BM_42_06 -#define BM_43_06 0x00000fffffffffc0 -#define BM_06_43 BM_43_06 -#define BM_44_06 0x00001fffffffffc0 -#define BM_06_44 BM_44_06 -#define BM_45_06 0x00003fffffffffc0 -#define BM_06_45 BM_45_06 -#define BM_46_06 0x00007fffffffffc0 -#define BM_06_46 BM_46_06 -#define BM_47_06 0x0000ffffffffffc0 -#define BM_06_47 BM_47_06 -#define BM_48_06 0x0001ffffffffffc0 -#define BM_06_48 BM_48_06 -#define BM_49_06 0x0003ffffffffffc0 -#define BM_06_49 BM_49_06 -#define BM_50_06 0x0007ffffffffffc0 -#define BM_06_50 BM_50_06 -#define BM_51_06 0x000fffffffffffc0 -#define BM_06_51 BM_51_06 -#define BM_52_06 0x001fffffffffffc0 -#define BM_06_52 BM_52_06 -#define BM_53_06 0x003fffffffffffc0 -#define BM_06_53 BM_53_06 -#define BM_54_06 0x007fffffffffffc0 -#define BM_06_54 BM_54_06 -#define BM_55_06 0x00ffffffffffffc0 -#define BM_06_55 BM_55_06 -#define BM_56_06 0x01ffffffffffffc0 -#define BM_06_56 BM_56_06 -#define BM_57_06 0x03ffffffffffffc0 -#define BM_06_57 BM_57_06 -#define BM_58_06 0x07ffffffffffffc0 -#define BM_06_58 BM_58_06 -#define BM_59_06 0x0fffffffffffffc0 -#define BM_06_59 BM_59_06 -#define BM_60_06 0x1fffffffffffffc0 -#define BM_06_60 BM_60_06 -#define BM_61_06 0x3fffffffffffffc0 -#define BM_06_61 BM_61_06 -#define BM_62_06 0x7fffffffffffffc0 -#define BM_06_62 BM_62_06 -#define BM_63_06 0xffffffffffffffc0 -#define BM_06_63 BM_63_06 -#define BM_07_07 0x0000000000000080 -#define BM_08_07 0x0000000000000180 -#define BM_07_08 BM_08_07 -#define BM_09_07 0x0000000000000380 -#define BM_07_09 BM_09_07 -#define BM_10_07 0x0000000000000780 -#define BM_07_10 BM_10_07 -#define BM_11_07 0x0000000000000f80 -#define BM_07_11 BM_11_07 -#define BM_12_07 0x0000000000001f80 -#define BM_07_12 BM_12_07 -#define BM_13_07 0x0000000000003f80 -#define BM_07_13 BM_13_07 -#define BM_14_07 0x0000000000007f80 -#define BM_07_14 BM_14_07 -#define BM_15_07 0x000000000000ff80 -#define BM_07_15 BM_15_07 -#define BM_16_07 0x000000000001ff80 -#define BM_07_16 BM_16_07 -#define BM_17_07 0x000000000003ff80 -#define BM_07_17 BM_17_07 -#define BM_18_07 0x000000000007ff80 -#define BM_07_18 BM_18_07 -#define BM_19_07 0x00000000000fff80 -#define BM_07_19 BM_19_07 -#define BM_20_07 0x00000000001fff80 -#define BM_07_20 BM_20_07 -#define BM_21_07 0x00000000003fff80 -#define BM_07_21 BM_21_07 -#define BM_22_07 0x00000000007fff80 -#define BM_07_22 BM_22_07 -#define BM_23_07 0x0000000000ffff80 -#define BM_07_23 BM_23_07 -#define BM_24_07 0x0000000001ffff80 -#define BM_07_24 BM_24_07 -#define BM_25_07 0x0000000003ffff80 -#define BM_07_25 BM_25_07 -#define BM_26_07 0x0000000007ffff80 -#define BM_07_26 BM_26_07 -#define BM_27_07 0x000000000fffff80 -#define BM_07_27 BM_27_07 -#define BM_28_07 0x000000001fffff80 -#define BM_07_28 BM_28_07 -#define BM_29_07 0x000000003fffff80 -#define BM_07_29 BM_29_07 -#define BM_30_07 0x000000007fffff80 -#define BM_07_30 BM_30_07 -#define BM_31_07 0x00000000ffffff80 -#define BM_07_31 BM_31_07 -#define BM_32_07 0x00000001ffffff80 -#define BM_07_32 BM_32_07 -#define BM_33_07 0x00000003ffffff80 -#define BM_07_33 BM_33_07 -#define BM_34_07 0x00000007ffffff80 -#define BM_07_34 BM_34_07 -#define BM_35_07 0x0000000fffffff80 -#define BM_07_35 BM_35_07 -#define BM_36_07 0x0000001fffffff80 -#define BM_07_36 BM_36_07 -#define BM_37_07 0x0000003fffffff80 -#define BM_07_37 BM_37_07 -#define BM_38_07 0x0000007fffffff80 -#define BM_07_38 BM_38_07 -#define BM_39_07 0x000000ffffffff80 -#define BM_07_39 BM_39_07 -#define BM_40_07 0x000001ffffffff80 -#define BM_07_40 BM_40_07 -#define BM_41_07 0x000003ffffffff80 -#define BM_07_41 BM_41_07 -#define BM_42_07 0x000007ffffffff80 -#define BM_07_42 BM_42_07 -#define BM_43_07 0x00000fffffffff80 -#define BM_07_43 BM_43_07 -#define BM_44_07 0x00001fffffffff80 -#define BM_07_44 BM_44_07 -#define BM_45_07 0x00003fffffffff80 -#define BM_07_45 BM_45_07 -#define BM_46_07 0x00007fffffffff80 -#define BM_07_46 BM_46_07 -#define BM_47_07 0x0000ffffffffff80 -#define BM_07_47 BM_47_07 -#define BM_48_07 0x0001ffffffffff80 -#define BM_07_48 BM_48_07 -#define BM_49_07 0x0003ffffffffff80 -#define BM_07_49 BM_49_07 -#define BM_50_07 0x0007ffffffffff80 -#define BM_07_50 BM_50_07 -#define BM_51_07 0x000fffffffffff80 -#define BM_07_51 BM_51_07 -#define BM_52_07 0x001fffffffffff80 -#define BM_07_52 BM_52_07 -#define BM_53_07 0x003fffffffffff80 -#define BM_07_53 BM_53_07 -#define BM_54_07 0x007fffffffffff80 -#define BM_07_54 BM_54_07 -#define BM_55_07 0x00ffffffffffff80 -#define BM_07_55 BM_55_07 -#define BM_56_07 0x01ffffffffffff80 -#define BM_07_56 BM_56_07 -#define BM_57_07 0x03ffffffffffff80 -#define BM_07_57 BM_57_07 -#define BM_58_07 0x07ffffffffffff80 -#define BM_07_58 BM_58_07 -#define BM_59_07 0x0fffffffffffff80 -#define BM_07_59 BM_59_07 -#define BM_60_07 0x1fffffffffffff80 -#define BM_07_60 BM_60_07 -#define BM_61_07 0x3fffffffffffff80 -#define BM_07_61 BM_61_07 -#define BM_62_07 0x7fffffffffffff80 -#define BM_07_62 BM_62_07 -#define BM_63_07 0xffffffffffffff80 -#define BM_07_63 BM_63_07 -#define BM_08_08 0x0000000000000100 -#define BM_09_08 0x0000000000000300 -#define BM_08_09 BM_09_08 -#define BM_10_08 0x0000000000000700 -#define BM_08_10 BM_10_08 -#define BM_11_08 0x0000000000000f00 -#define BM_08_11 BM_11_08 -#define BM_12_08 0x0000000000001f00 -#define BM_08_12 BM_12_08 -#define BM_13_08 0x0000000000003f00 -#define BM_08_13 BM_13_08 -#define BM_14_08 0x0000000000007f00 -#define BM_08_14 BM_14_08 -#define BM_15_08 0x000000000000ff00 -#define BM_08_15 BM_15_08 -#define BM_16_08 0x000000000001ff00 -#define BM_08_16 BM_16_08 -#define BM_17_08 0x000000000003ff00 -#define BM_08_17 BM_17_08 -#define BM_18_08 0x000000000007ff00 -#define BM_08_18 BM_18_08 -#define BM_19_08 0x00000000000fff00 -#define BM_08_19 BM_19_08 -#define BM_20_08 0x00000000001fff00 -#define BM_08_20 BM_20_08 -#define BM_21_08 0x00000000003fff00 -#define BM_08_21 BM_21_08 -#define BM_22_08 0x00000000007fff00 -#define BM_08_22 BM_22_08 -#define BM_23_08 0x0000000000ffff00 -#define BM_08_23 BM_23_08 -#define BM_24_08 0x0000000001ffff00 -#define BM_08_24 BM_24_08 -#define BM_25_08 0x0000000003ffff00 -#define BM_08_25 BM_25_08 -#define BM_26_08 0x0000000007ffff00 -#define BM_08_26 BM_26_08 -#define BM_27_08 0x000000000fffff00 -#define BM_08_27 BM_27_08 -#define BM_28_08 0x000000001fffff00 -#define BM_08_28 BM_28_08 -#define BM_29_08 0x000000003fffff00 -#define BM_08_29 BM_29_08 -#define BM_30_08 0x000000007fffff00 -#define BM_08_30 BM_30_08 -#define BM_31_08 0x00000000ffffff00 -#define BM_08_31 BM_31_08 -#define BM_32_08 0x00000001ffffff00 -#define BM_08_32 BM_32_08 -#define BM_33_08 0x00000003ffffff00 -#define BM_08_33 BM_33_08 -#define BM_34_08 0x00000007ffffff00 -#define BM_08_34 BM_34_08 -#define BM_35_08 0x0000000fffffff00 -#define BM_08_35 BM_35_08 -#define BM_36_08 0x0000001fffffff00 -#define BM_08_36 BM_36_08 -#define BM_37_08 0x0000003fffffff00 -#define BM_08_37 BM_37_08 -#define BM_38_08 0x0000007fffffff00 -#define BM_08_38 BM_38_08 -#define BM_39_08 0x000000ffffffff00 -#define BM_08_39 BM_39_08 -#define BM_40_08 0x000001ffffffff00 -#define BM_08_40 BM_40_08 -#define BM_41_08 0x000003ffffffff00 -#define BM_08_41 BM_41_08 -#define BM_42_08 0x000007ffffffff00 -#define BM_08_42 BM_42_08 -#define BM_43_08 0x00000fffffffff00 -#define BM_08_43 BM_43_08 -#define BM_44_08 0x00001fffffffff00 -#define BM_08_44 BM_44_08 -#define BM_45_08 0x00003fffffffff00 -#define BM_08_45 BM_45_08 -#define BM_46_08 0x00007fffffffff00 -#define BM_08_46 BM_46_08 -#define BM_47_08 0x0000ffffffffff00 -#define BM_08_47 BM_47_08 -#define BM_48_08 0x0001ffffffffff00 -#define BM_08_48 BM_48_08 -#define BM_49_08 0x0003ffffffffff00 -#define BM_08_49 BM_49_08 -#define BM_50_08 0x0007ffffffffff00 -#define BM_08_50 BM_50_08 -#define BM_51_08 0x000fffffffffff00 -#define BM_08_51 BM_51_08 -#define BM_52_08 0x001fffffffffff00 -#define BM_08_52 BM_52_08 -#define BM_53_08 0x003fffffffffff00 -#define BM_08_53 BM_53_08 -#define BM_54_08 0x007fffffffffff00 -#define BM_08_54 BM_54_08 -#define BM_55_08 0x00ffffffffffff00 -#define BM_08_55 BM_55_08 -#define BM_56_08 0x01ffffffffffff00 -#define BM_08_56 BM_56_08 -#define BM_57_08 0x03ffffffffffff00 -#define BM_08_57 BM_57_08 -#define BM_58_08 0x07ffffffffffff00 -#define BM_08_58 BM_58_08 -#define BM_59_08 0x0fffffffffffff00 -#define BM_08_59 BM_59_08 -#define BM_60_08 0x1fffffffffffff00 -#define BM_08_60 BM_60_08 -#define BM_61_08 0x3fffffffffffff00 -#define BM_08_61 BM_61_08 -#define BM_62_08 0x7fffffffffffff00 -#define BM_08_62 BM_62_08 -#define BM_63_08 0xffffffffffffff00 -#define BM_08_63 BM_63_08 -#define BM_09_09 0x0000000000000200 -#define BM_10_09 0x0000000000000600 -#define BM_09_10 BM_10_09 -#define BM_11_09 0x0000000000000e00 -#define BM_09_11 BM_11_09 -#define BM_12_09 0x0000000000001e00 -#define BM_09_12 BM_12_09 -#define BM_13_09 0x0000000000003e00 -#define BM_09_13 BM_13_09 -#define BM_14_09 0x0000000000007e00 -#define BM_09_14 BM_14_09 -#define BM_15_09 0x000000000000fe00 -#define BM_09_15 BM_15_09 -#define BM_16_09 0x000000000001fe00 -#define BM_09_16 BM_16_09 -#define BM_17_09 0x000000000003fe00 -#define BM_09_17 BM_17_09 -#define BM_18_09 0x000000000007fe00 -#define BM_09_18 BM_18_09 -#define BM_19_09 0x00000000000ffe00 -#define BM_09_19 BM_19_09 -#define BM_20_09 0x00000000001ffe00 -#define BM_09_20 BM_20_09 -#define BM_21_09 0x00000000003ffe00 -#define BM_09_21 BM_21_09 -#define BM_22_09 0x00000000007ffe00 -#define BM_09_22 BM_22_09 -#define BM_23_09 0x0000000000fffe00 -#define BM_09_23 BM_23_09 -#define BM_24_09 0x0000000001fffe00 -#define BM_09_24 BM_24_09 -#define BM_25_09 0x0000000003fffe00 -#define BM_09_25 BM_25_09 -#define BM_26_09 0x0000000007fffe00 -#define BM_09_26 BM_26_09 -#define BM_27_09 0x000000000ffffe00 -#define BM_09_27 BM_27_09 -#define BM_28_09 0x000000001ffffe00 -#define BM_09_28 BM_28_09 -#define BM_29_09 0x000000003ffffe00 -#define BM_09_29 BM_29_09 -#define BM_30_09 0x000000007ffffe00 -#define BM_09_30 BM_30_09 -#define BM_31_09 0x00000000fffffe00 -#define BM_09_31 BM_31_09 -#define BM_32_09 0x00000001fffffe00 -#define BM_09_32 BM_32_09 -#define BM_33_09 0x00000003fffffe00 -#define BM_09_33 BM_33_09 -#define BM_34_09 0x00000007fffffe00 -#define BM_09_34 BM_34_09 -#define BM_35_09 0x0000000ffffffe00 -#define BM_09_35 BM_35_09 -#define BM_36_09 0x0000001ffffffe00 -#define BM_09_36 BM_36_09 -#define BM_37_09 0x0000003ffffffe00 -#define BM_09_37 BM_37_09 -#define BM_38_09 0x0000007ffffffe00 -#define BM_09_38 BM_38_09 -#define BM_39_09 0x000000fffffffe00 -#define BM_09_39 BM_39_09 -#define BM_40_09 0x000001fffffffe00 -#define BM_09_40 BM_40_09 -#define BM_41_09 0x000003fffffffe00 -#define BM_09_41 BM_41_09 -#define BM_42_09 0x000007fffffffe00 -#define BM_09_42 BM_42_09 -#define BM_43_09 0x00000ffffffffe00 -#define BM_09_43 BM_43_09 -#define BM_44_09 0x00001ffffffffe00 -#define BM_09_44 BM_44_09 -#define BM_45_09 0x00003ffffffffe00 -#define BM_09_45 BM_45_09 -#define BM_46_09 0x00007ffffffffe00 -#define BM_09_46 BM_46_09 -#define BM_47_09 0x0000fffffffffe00 -#define BM_09_47 BM_47_09 -#define BM_48_09 0x0001fffffffffe00 -#define BM_09_48 BM_48_09 -#define BM_49_09 0x0003fffffffffe00 -#define BM_09_49 BM_49_09 -#define BM_50_09 0x0007fffffffffe00 -#define BM_09_50 BM_50_09 -#define BM_51_09 0x000ffffffffffe00 -#define BM_09_51 BM_51_09 -#define BM_52_09 0x001ffffffffffe00 -#define BM_09_52 BM_52_09 -#define BM_53_09 0x003ffffffffffe00 -#define BM_09_53 BM_53_09 -#define BM_54_09 0x007ffffffffffe00 -#define BM_09_54 BM_54_09 -#define BM_55_09 0x00fffffffffffe00 -#define BM_09_55 BM_55_09 -#define BM_56_09 0x01fffffffffffe00 -#define BM_09_56 BM_56_09 -#define BM_57_09 0x03fffffffffffe00 -#define BM_09_57 BM_57_09 -#define BM_58_09 0x07fffffffffffe00 -#define BM_09_58 BM_58_09 -#define BM_59_09 0x0ffffffffffffe00 -#define BM_09_59 BM_59_09 -#define BM_60_09 0x1ffffffffffffe00 -#define BM_09_60 BM_60_09 -#define BM_61_09 0x3ffffffffffffe00 -#define BM_09_61 BM_61_09 -#define BM_62_09 0x7ffffffffffffe00 -#define BM_09_62 BM_62_09 -#define BM_63_09 0xfffffffffffffe00 -#define BM_09_63 BM_63_09 -#define BM_10_10 0x0000000000000400 -#define BM_11_10 0x0000000000000c00 -#define BM_10_11 BM_11_10 -#define BM_12_10 0x0000000000001c00 -#define BM_10_12 BM_12_10 -#define BM_13_10 0x0000000000003c00 -#define BM_10_13 BM_13_10 -#define BM_14_10 0x0000000000007c00 -#define BM_10_14 BM_14_10 -#define BM_15_10 0x000000000000fc00 -#define BM_10_15 BM_15_10 -#define BM_16_10 0x000000000001fc00 -#define BM_10_16 BM_16_10 -#define BM_17_10 0x000000000003fc00 -#define BM_10_17 BM_17_10 -#define BM_18_10 0x000000000007fc00 -#define BM_10_18 BM_18_10 -#define BM_19_10 0x00000000000ffc00 -#define BM_10_19 BM_19_10 -#define BM_20_10 0x00000000001ffc00 -#define BM_10_20 BM_20_10 -#define BM_21_10 0x00000000003ffc00 -#define BM_10_21 BM_21_10 -#define BM_22_10 0x00000000007ffc00 -#define BM_10_22 BM_22_10 -#define BM_23_10 0x0000000000fffc00 -#define BM_10_23 BM_23_10 -#define BM_24_10 0x0000000001fffc00 -#define BM_10_24 BM_24_10 -#define BM_25_10 0x0000000003fffc00 -#define BM_10_25 BM_25_10 -#define BM_26_10 0x0000000007fffc00 -#define BM_10_26 BM_26_10 -#define BM_27_10 0x000000000ffffc00 -#define BM_10_27 BM_27_10 -#define BM_28_10 0x000000001ffffc00 -#define BM_10_28 BM_28_10 -#define BM_29_10 0x000000003ffffc00 -#define BM_10_29 BM_29_10 -#define BM_30_10 0x000000007ffffc00 -#define BM_10_30 BM_30_10 -#define BM_31_10 0x00000000fffffc00 -#define BM_10_31 BM_31_10 -#define BM_32_10 0x00000001fffffc00 -#define BM_10_32 BM_32_10 -#define BM_33_10 0x00000003fffffc00 -#define BM_10_33 BM_33_10 -#define BM_34_10 0x00000007fffffc00 -#define BM_10_34 BM_34_10 -#define BM_35_10 0x0000000ffffffc00 -#define BM_10_35 BM_35_10 -#define BM_36_10 0x0000001ffffffc00 -#define BM_10_36 BM_36_10 -#define BM_37_10 0x0000003ffffffc00 -#define BM_10_37 BM_37_10 -#define BM_38_10 0x0000007ffffffc00 -#define BM_10_38 BM_38_10 -#define BM_39_10 0x000000fffffffc00 -#define BM_10_39 BM_39_10 -#define BM_40_10 0x000001fffffffc00 -#define BM_10_40 BM_40_10 -#define BM_41_10 0x000003fffffffc00 -#define BM_10_41 BM_41_10 -#define BM_42_10 0x000007fffffffc00 -#define BM_10_42 BM_42_10 -#define BM_43_10 0x00000ffffffffc00 -#define BM_10_43 BM_43_10 -#define BM_44_10 0x00001ffffffffc00 -#define BM_10_44 BM_44_10 -#define BM_45_10 0x00003ffffffffc00 -#define BM_10_45 BM_45_10 -#define BM_46_10 0x00007ffffffffc00 -#define BM_10_46 BM_46_10 -#define BM_47_10 0x0000fffffffffc00 -#define BM_10_47 BM_47_10 -#define BM_48_10 0x0001fffffffffc00 -#define BM_10_48 BM_48_10 -#define BM_49_10 0x0003fffffffffc00 -#define BM_10_49 BM_49_10 -#define BM_50_10 0x0007fffffffffc00 -#define BM_10_50 BM_50_10 -#define BM_51_10 0x000ffffffffffc00 -#define BM_10_51 BM_51_10 -#define BM_52_10 0x001ffffffffffc00 -#define BM_10_52 BM_52_10 -#define BM_53_10 0x003ffffffffffc00 -#define BM_10_53 BM_53_10 -#define BM_54_10 0x007ffffffffffc00 -#define BM_10_54 BM_54_10 -#define BM_55_10 0x00fffffffffffc00 -#define BM_10_55 BM_55_10 -#define BM_56_10 0x01fffffffffffc00 -#define BM_10_56 BM_56_10 -#define BM_57_10 0x03fffffffffffc00 -#define BM_10_57 BM_57_10 -#define BM_58_10 0x07fffffffffffc00 -#define BM_10_58 BM_58_10 -#define BM_59_10 0x0ffffffffffffc00 -#define BM_10_59 BM_59_10 -#define BM_60_10 0x1ffffffffffffc00 -#define BM_10_60 BM_60_10 -#define BM_61_10 0x3ffffffffffffc00 -#define BM_10_61 BM_61_10 -#define BM_62_10 0x7ffffffffffffc00 -#define BM_10_62 BM_62_10 -#define BM_63_10 0xfffffffffffffc00 -#define BM_10_63 BM_63_10 -#define BM_11_11 0x0000000000000800 -#define BM_12_11 0x0000000000001800 -#define BM_11_12 BM_12_11 -#define BM_13_11 0x0000000000003800 -#define BM_11_13 BM_13_11 -#define BM_14_11 0x0000000000007800 -#define BM_11_14 BM_14_11 -#define BM_15_11 0x000000000000f800 -#define BM_11_15 BM_15_11 -#define BM_16_11 0x000000000001f800 -#define BM_11_16 BM_16_11 -#define BM_17_11 0x000000000003f800 -#define BM_11_17 BM_17_11 -#define BM_18_11 0x000000000007f800 -#define BM_11_18 BM_18_11 -#define BM_19_11 0x00000000000ff800 -#define BM_11_19 BM_19_11 -#define BM_20_11 0x00000000001ff800 -#define BM_11_20 BM_20_11 -#define BM_21_11 0x00000000003ff800 -#define BM_11_21 BM_21_11 -#define BM_22_11 0x00000000007ff800 -#define BM_11_22 BM_22_11 -#define BM_23_11 0x0000000000fff800 -#define BM_11_23 BM_23_11 -#define BM_24_11 0x0000000001fff800 -#define BM_11_24 BM_24_11 -#define BM_25_11 0x0000000003fff800 -#define BM_11_25 BM_25_11 -#define BM_26_11 0x0000000007fff800 -#define BM_11_26 BM_26_11 -#define BM_27_11 0x000000000ffff800 -#define BM_11_27 BM_27_11 -#define BM_28_11 0x000000001ffff800 -#define BM_11_28 BM_28_11 -#define BM_29_11 0x000000003ffff800 -#define BM_11_29 BM_29_11 -#define BM_30_11 0x000000007ffff800 -#define BM_11_30 BM_30_11 -#define BM_31_11 0x00000000fffff800 -#define BM_11_31 BM_31_11 -#define BM_32_11 0x00000001fffff800 -#define BM_11_32 BM_32_11 -#define BM_33_11 0x00000003fffff800 -#define BM_11_33 BM_33_11 -#define BM_34_11 0x00000007fffff800 -#define BM_11_34 BM_34_11 -#define BM_35_11 0x0000000ffffff800 -#define BM_11_35 BM_35_11 -#define BM_36_11 0x0000001ffffff800 -#define BM_11_36 BM_36_11 -#define BM_37_11 0x0000003ffffff800 -#define BM_11_37 BM_37_11 -#define BM_38_11 0x0000007ffffff800 -#define BM_11_38 BM_38_11 -#define BM_39_11 0x000000fffffff800 -#define BM_11_39 BM_39_11 -#define BM_40_11 0x000001fffffff800 -#define BM_11_40 BM_40_11 -#define BM_41_11 0x000003fffffff800 -#define BM_11_41 BM_41_11 -#define BM_42_11 0x000007fffffff800 -#define BM_11_42 BM_42_11 -#define BM_43_11 0x00000ffffffff800 -#define BM_11_43 BM_43_11 -#define BM_44_11 0x00001ffffffff800 -#define BM_11_44 BM_44_11 -#define BM_45_11 0x00003ffffffff800 -#define BM_11_45 BM_45_11 -#define BM_46_11 0x00007ffffffff800 -#define BM_11_46 BM_46_11 -#define BM_47_11 0x0000fffffffff800 -#define BM_11_47 BM_47_11 -#define BM_48_11 0x0001fffffffff800 -#define BM_11_48 BM_48_11 -#define BM_49_11 0x0003fffffffff800 -#define BM_11_49 BM_49_11 -#define BM_50_11 0x0007fffffffff800 -#define BM_11_50 BM_50_11 -#define BM_51_11 0x000ffffffffff800 -#define BM_11_51 BM_51_11 -#define BM_52_11 0x001ffffffffff800 -#define BM_11_52 BM_52_11 -#define BM_53_11 0x003ffffffffff800 -#define BM_11_53 BM_53_11 -#define BM_54_11 0x007ffffffffff800 -#define BM_11_54 BM_54_11 -#define BM_55_11 0x00fffffffffff800 -#define BM_11_55 BM_55_11 -#define BM_56_11 0x01fffffffffff800 -#define BM_11_56 BM_56_11 -#define BM_57_11 0x03fffffffffff800 -#define BM_11_57 BM_57_11 -#define BM_58_11 0x07fffffffffff800 -#define BM_11_58 BM_58_11 -#define BM_59_11 0x0ffffffffffff800 -#define BM_11_59 BM_59_11 -#define BM_60_11 0x1ffffffffffff800 -#define BM_11_60 BM_60_11 -#define BM_61_11 0x3ffffffffffff800 -#define BM_11_61 BM_61_11 -#define BM_62_11 0x7ffffffffffff800 -#define BM_11_62 BM_62_11 -#define BM_63_11 0xfffffffffffff800 -#define BM_11_63 BM_63_11 -#define BM_12_12 0x0000000000001000 -#define BM_13_12 0x0000000000003000 -#define BM_12_13 BM_13_12 -#define BM_14_12 0x0000000000007000 -#define BM_12_14 BM_14_12 -#define BM_15_12 0x000000000000f000 -#define BM_12_15 BM_15_12 -#define BM_16_12 0x000000000001f000 -#define BM_12_16 BM_16_12 -#define BM_17_12 0x000000000003f000 -#define BM_12_17 BM_17_12 -#define BM_18_12 0x000000000007f000 -#define BM_12_18 BM_18_12 -#define BM_19_12 0x00000000000ff000 -#define BM_12_19 BM_19_12 -#define BM_20_12 0x00000000001ff000 -#define BM_12_20 BM_20_12 -#define BM_21_12 0x00000000003ff000 -#define BM_12_21 BM_21_12 -#define BM_22_12 0x00000000007ff000 -#define BM_12_22 BM_22_12 -#define BM_23_12 0x0000000000fff000 -#define BM_12_23 BM_23_12 -#define BM_24_12 0x0000000001fff000 -#define BM_12_24 BM_24_12 -#define BM_25_12 0x0000000003fff000 -#define BM_12_25 BM_25_12 -#define BM_26_12 0x0000000007fff000 -#define BM_12_26 BM_26_12 -#define BM_27_12 0x000000000ffff000 -#define BM_12_27 BM_27_12 -#define BM_28_12 0x000000001ffff000 -#define BM_12_28 BM_28_12 -#define BM_29_12 0x000000003ffff000 -#define BM_12_29 BM_29_12 -#define BM_30_12 0x000000007ffff000 -#define BM_12_30 BM_30_12 -#define BM_31_12 0x00000000fffff000 -#define BM_12_31 BM_31_12 -#define BM_32_12 0x00000001fffff000 -#define BM_12_32 BM_32_12 -#define BM_33_12 0x00000003fffff000 -#define BM_12_33 BM_33_12 -#define BM_34_12 0x00000007fffff000 -#define BM_12_34 BM_34_12 -#define BM_35_12 0x0000000ffffff000 -#define BM_12_35 BM_35_12 -#define BM_36_12 0x0000001ffffff000 -#define BM_12_36 BM_36_12 -#define BM_37_12 0x0000003ffffff000 -#define BM_12_37 BM_37_12 -#define BM_38_12 0x0000007ffffff000 -#define BM_12_38 BM_38_12 -#define BM_39_12 0x000000fffffff000 -#define BM_12_39 BM_39_12 -#define BM_40_12 0x000001fffffff000 -#define BM_12_40 BM_40_12 -#define BM_41_12 0x000003fffffff000 -#define BM_12_41 BM_41_12 -#define BM_42_12 0x000007fffffff000 -#define BM_12_42 BM_42_12 -#define BM_43_12 0x00000ffffffff000 -#define BM_12_43 BM_43_12 -#define BM_44_12 0x00001ffffffff000 -#define BM_12_44 BM_44_12 -#define BM_45_12 0x00003ffffffff000 -#define BM_12_45 BM_45_12 -#define BM_46_12 0x00007ffffffff000 -#define BM_12_46 BM_46_12 -#define BM_47_12 0x0000fffffffff000 -#define BM_12_47 BM_47_12 -#define BM_48_12 0x0001fffffffff000 -#define BM_12_48 BM_48_12 -#define BM_49_12 0x0003fffffffff000 -#define BM_12_49 BM_49_12 -#define BM_50_12 0x0007fffffffff000 -#define BM_12_50 BM_50_12 -#define BM_51_12 0x000ffffffffff000 -#define BM_12_51 BM_51_12 -#define BM_52_12 0x001ffffffffff000 -#define BM_12_52 BM_52_12 -#define BM_53_12 0x003ffffffffff000 -#define BM_12_53 BM_53_12 -#define BM_54_12 0x007ffffffffff000 -#define BM_12_54 BM_54_12 -#define BM_55_12 0x00fffffffffff000 -#define BM_12_55 BM_55_12 -#define BM_56_12 0x01fffffffffff000 -#define BM_12_56 BM_56_12 -#define BM_57_12 0x03fffffffffff000 -#define BM_12_57 BM_57_12 -#define BM_58_12 0x07fffffffffff000 -#define BM_12_58 BM_58_12 -#define BM_59_12 0x0ffffffffffff000 -#define BM_12_59 BM_59_12 -#define BM_60_12 0x1ffffffffffff000 -#define BM_12_60 BM_60_12 -#define BM_61_12 0x3ffffffffffff000 -#define BM_12_61 BM_61_12 -#define BM_62_12 0x7ffffffffffff000 -#define BM_12_62 BM_62_12 -#define BM_63_12 0xfffffffffffff000 -#define BM_12_63 BM_63_12 -#define BM_13_13 0x0000000000002000 -#define BM_14_13 0x0000000000006000 -#define BM_13_14 BM_14_13 -#define BM_15_13 0x000000000000e000 -#define BM_13_15 BM_15_13 -#define BM_16_13 0x000000000001e000 -#define BM_13_16 BM_16_13 -#define BM_17_13 0x000000000003e000 -#define BM_13_17 BM_17_13 -#define BM_18_13 0x000000000007e000 -#define BM_13_18 BM_18_13 -#define BM_19_13 0x00000000000fe000 -#define BM_13_19 BM_19_13 -#define BM_20_13 0x00000000001fe000 -#define BM_13_20 BM_20_13 -#define BM_21_13 0x00000000003fe000 -#define BM_13_21 BM_21_13 -#define BM_22_13 0x00000000007fe000 -#define BM_13_22 BM_22_13 -#define BM_23_13 0x0000000000ffe000 -#define BM_13_23 BM_23_13 -#define BM_24_13 0x0000000001ffe000 -#define BM_13_24 BM_24_13 -#define BM_25_13 0x0000000003ffe000 -#define BM_13_25 BM_25_13 -#define BM_26_13 0x0000000007ffe000 -#define BM_13_26 BM_26_13 -#define BM_27_13 0x000000000fffe000 -#define BM_13_27 BM_27_13 -#define BM_28_13 0x000000001fffe000 -#define BM_13_28 BM_28_13 -#define BM_29_13 0x000000003fffe000 -#define BM_13_29 BM_29_13 -#define BM_30_13 0x000000007fffe000 -#define BM_13_30 BM_30_13 -#define BM_31_13 0x00000000ffffe000 -#define BM_13_31 BM_31_13 -#define BM_32_13 0x00000001ffffe000 -#define BM_13_32 BM_32_13 -#define BM_33_13 0x00000003ffffe000 -#define BM_13_33 BM_33_13 -#define BM_34_13 0x00000007ffffe000 -#define BM_13_34 BM_34_13 -#define BM_35_13 0x0000000fffffe000 -#define BM_13_35 BM_35_13 -#define BM_36_13 0x0000001fffffe000 -#define BM_13_36 BM_36_13 -#define BM_37_13 0x0000003fffffe000 -#define BM_13_37 BM_37_13 -#define BM_38_13 0x0000007fffffe000 -#define BM_13_38 BM_38_13 -#define BM_39_13 0x000000ffffffe000 -#define BM_13_39 BM_39_13 -#define BM_40_13 0x000001ffffffe000 -#define BM_13_40 BM_40_13 -#define BM_41_13 0x000003ffffffe000 -#define BM_13_41 BM_41_13 -#define BM_42_13 0x000007ffffffe000 -#define BM_13_42 BM_42_13 -#define BM_43_13 0x00000fffffffe000 -#define BM_13_43 BM_43_13 -#define BM_44_13 0x00001fffffffe000 -#define BM_13_44 BM_44_13 -#define BM_45_13 0x00003fffffffe000 -#define BM_13_45 BM_45_13 -#define BM_46_13 0x00007fffffffe000 -#define BM_13_46 BM_46_13 -#define BM_47_13 0x0000ffffffffe000 -#define BM_13_47 BM_47_13 -#define BM_48_13 0x0001ffffffffe000 -#define BM_13_48 BM_48_13 -#define BM_49_13 0x0003ffffffffe000 -#define BM_13_49 BM_49_13 -#define BM_50_13 0x0007ffffffffe000 -#define BM_13_50 BM_50_13 -#define BM_51_13 0x000fffffffffe000 -#define BM_13_51 BM_51_13 -#define BM_52_13 0x001fffffffffe000 -#define BM_13_52 BM_52_13 -#define BM_53_13 0x003fffffffffe000 -#define BM_13_53 BM_53_13 -#define BM_54_13 0x007fffffffffe000 -#define BM_13_54 BM_54_13 -#define BM_55_13 0x00ffffffffffe000 -#define BM_13_55 BM_55_13 -#define BM_56_13 0x01ffffffffffe000 -#define BM_13_56 BM_56_13 -#define BM_57_13 0x03ffffffffffe000 -#define BM_13_57 BM_57_13 -#define BM_58_13 0x07ffffffffffe000 -#define BM_13_58 BM_58_13 -#define BM_59_13 0x0fffffffffffe000 -#define BM_13_59 BM_59_13 -#define BM_60_13 0x1fffffffffffe000 -#define BM_13_60 BM_60_13 -#define BM_61_13 0x3fffffffffffe000 -#define BM_13_61 BM_61_13 -#define BM_62_13 0x7fffffffffffe000 -#define BM_13_62 BM_62_13 -#define BM_63_13 0xffffffffffffe000 -#define BM_13_63 BM_63_13 -#define BM_14_14 0x0000000000004000 -#define BM_15_14 0x000000000000c000 -#define BM_14_15 BM_15_14 -#define BM_16_14 0x000000000001c000 -#define BM_14_16 BM_16_14 -#define BM_17_14 0x000000000003c000 -#define BM_14_17 BM_17_14 -#define BM_18_14 0x000000000007c000 -#define BM_14_18 BM_18_14 -#define BM_19_14 0x00000000000fc000 -#define BM_14_19 BM_19_14 -#define BM_20_14 0x00000000001fc000 -#define BM_14_20 BM_20_14 -#define BM_21_14 0x00000000003fc000 -#define BM_14_21 BM_21_14 -#define BM_22_14 0x00000000007fc000 -#define BM_14_22 BM_22_14 -#define BM_23_14 0x0000000000ffc000 -#define BM_14_23 BM_23_14 -#define BM_24_14 0x0000000001ffc000 -#define BM_14_24 BM_24_14 -#define BM_25_14 0x0000000003ffc000 -#define BM_14_25 BM_25_14 -#define BM_26_14 0x0000000007ffc000 -#define BM_14_26 BM_26_14 -#define BM_27_14 0x000000000fffc000 -#define BM_14_27 BM_27_14 -#define BM_28_14 0x000000001fffc000 -#define BM_14_28 BM_28_14 -#define BM_29_14 0x000000003fffc000 -#define BM_14_29 BM_29_14 -#define BM_30_14 0x000000007fffc000 -#define BM_14_30 BM_30_14 -#define BM_31_14 0x00000000ffffc000 -#define BM_14_31 BM_31_14 -#define BM_32_14 0x00000001ffffc000 -#define BM_14_32 BM_32_14 -#define BM_33_14 0x00000003ffffc000 -#define BM_14_33 BM_33_14 -#define BM_34_14 0x00000007ffffc000 -#define BM_14_34 BM_34_14 -#define BM_35_14 0x0000000fffffc000 -#define BM_14_35 BM_35_14 -#define BM_36_14 0x0000001fffffc000 -#define BM_14_36 BM_36_14 -#define BM_37_14 0x0000003fffffc000 -#define BM_14_37 BM_37_14 -#define BM_38_14 0x0000007fffffc000 -#define BM_14_38 BM_38_14 -#define BM_39_14 0x000000ffffffc000 -#define BM_14_39 BM_39_14 -#define BM_40_14 0x000001ffffffc000 -#define BM_14_40 BM_40_14 -#define BM_41_14 0x000003ffffffc000 -#define BM_14_41 BM_41_14 -#define BM_42_14 0x000007ffffffc000 -#define BM_14_42 BM_42_14 -#define BM_43_14 0x00000fffffffc000 -#define BM_14_43 BM_43_14 -#define BM_44_14 0x00001fffffffc000 -#define BM_14_44 BM_44_14 -#define BM_45_14 0x00003fffffffc000 -#define BM_14_45 BM_45_14 -#define BM_46_14 0x00007fffffffc000 -#define BM_14_46 BM_46_14 -#define BM_47_14 0x0000ffffffffc000 -#define BM_14_47 BM_47_14 -#define BM_48_14 0x0001ffffffffc000 -#define BM_14_48 BM_48_14 -#define BM_49_14 0x0003ffffffffc000 -#define BM_14_49 BM_49_14 -#define BM_50_14 0x0007ffffffffc000 -#define BM_14_50 BM_50_14 -#define BM_51_14 0x000fffffffffc000 -#define BM_14_51 BM_51_14 -#define BM_52_14 0x001fffffffffc000 -#define BM_14_52 BM_52_14 -#define BM_53_14 0x003fffffffffc000 -#define BM_14_53 BM_53_14 -#define BM_54_14 0x007fffffffffc000 -#define BM_14_54 BM_54_14 -#define BM_55_14 0x00ffffffffffc000 -#define BM_14_55 BM_55_14 -#define BM_56_14 0x01ffffffffffc000 -#define BM_14_56 BM_56_14 -#define BM_57_14 0x03ffffffffffc000 -#define BM_14_57 BM_57_14 -#define BM_58_14 0x07ffffffffffc000 -#define BM_14_58 BM_58_14 -#define BM_59_14 0x0fffffffffffc000 -#define BM_14_59 BM_59_14 -#define BM_60_14 0x1fffffffffffc000 -#define BM_14_60 BM_60_14 -#define BM_61_14 0x3fffffffffffc000 -#define BM_14_61 BM_61_14 -#define BM_62_14 0x7fffffffffffc000 -#define BM_14_62 BM_62_14 -#define BM_63_14 0xffffffffffffc000 -#define BM_14_63 BM_63_14 -#define BM_15_15 0x0000000000008000 -#define BM_16_15 0x0000000000018000 -#define BM_15_16 BM_16_15 -#define BM_17_15 0x0000000000038000 -#define BM_15_17 BM_17_15 -#define BM_18_15 0x0000000000078000 -#define BM_15_18 BM_18_15 -#define BM_19_15 0x00000000000f8000 -#define BM_15_19 BM_19_15 -#define BM_20_15 0x00000000001f8000 -#define BM_15_20 BM_20_15 -#define BM_21_15 0x00000000003f8000 -#define BM_15_21 BM_21_15 -#define BM_22_15 0x00000000007f8000 -#define BM_15_22 BM_22_15 -#define BM_23_15 0x0000000000ff8000 -#define BM_15_23 BM_23_15 -#define BM_24_15 0x0000000001ff8000 -#define BM_15_24 BM_24_15 -#define BM_25_15 0x0000000003ff8000 -#define BM_15_25 BM_25_15 -#define BM_26_15 0x0000000007ff8000 -#define BM_15_26 BM_26_15 -#define BM_27_15 0x000000000fff8000 -#define BM_15_27 BM_27_15 -#define BM_28_15 0x000000001fff8000 -#define BM_15_28 BM_28_15 -#define BM_29_15 0x000000003fff8000 -#define BM_15_29 BM_29_15 -#define BM_30_15 0x000000007fff8000 -#define BM_15_30 BM_30_15 -#define BM_31_15 0x00000000ffff8000 -#define BM_15_31 BM_31_15 -#define BM_32_15 0x00000001ffff8000 -#define BM_15_32 BM_32_15 -#define BM_33_15 0x00000003ffff8000 -#define BM_15_33 BM_33_15 -#define BM_34_15 0x00000007ffff8000 -#define BM_15_34 BM_34_15 -#define BM_35_15 0x0000000fffff8000 -#define BM_15_35 BM_35_15 -#define BM_36_15 0x0000001fffff8000 -#define BM_15_36 BM_36_15 -#define BM_37_15 0x0000003fffff8000 -#define BM_15_37 BM_37_15 -#define BM_38_15 0x0000007fffff8000 -#define BM_15_38 BM_38_15 -#define BM_39_15 0x000000ffffff8000 -#define BM_15_39 BM_39_15 -#define BM_40_15 0x000001ffffff8000 -#define BM_15_40 BM_40_15 -#define BM_41_15 0x000003ffffff8000 -#define BM_15_41 BM_41_15 -#define BM_42_15 0x000007ffffff8000 -#define BM_15_42 BM_42_15 -#define BM_43_15 0x00000fffffff8000 -#define BM_15_43 BM_43_15 -#define BM_44_15 0x00001fffffff8000 -#define BM_15_44 BM_44_15 -#define BM_45_15 0x00003fffffff8000 -#define BM_15_45 BM_45_15 -#define BM_46_15 0x00007fffffff8000 -#define BM_15_46 BM_46_15 -#define BM_47_15 0x0000ffffffff8000 -#define BM_15_47 BM_47_15 -#define BM_48_15 0x0001ffffffff8000 -#define BM_15_48 BM_48_15 -#define BM_49_15 0x0003ffffffff8000 -#define BM_15_49 BM_49_15 -#define BM_50_15 0x0007ffffffff8000 -#define BM_15_50 BM_50_15 -#define BM_51_15 0x000fffffffff8000 -#define BM_15_51 BM_51_15 -#define BM_52_15 0x001fffffffff8000 -#define BM_15_52 BM_52_15 -#define BM_53_15 0x003fffffffff8000 -#define BM_15_53 BM_53_15 -#define BM_54_15 0x007fffffffff8000 -#define BM_15_54 BM_54_15 -#define BM_55_15 0x00ffffffffff8000 -#define BM_15_55 BM_55_15 -#define BM_56_15 0x01ffffffffff8000 -#define BM_15_56 BM_56_15 -#define BM_57_15 0x03ffffffffff8000 -#define BM_15_57 BM_57_15 -#define BM_58_15 0x07ffffffffff8000 -#define BM_15_58 BM_58_15 -#define BM_59_15 0x0fffffffffff8000 -#define BM_15_59 BM_59_15 -#define BM_60_15 0x1fffffffffff8000 -#define BM_15_60 BM_60_15 -#define BM_61_15 0x3fffffffffff8000 -#define BM_15_61 BM_61_15 -#define BM_62_15 0x7fffffffffff8000 -#define BM_15_62 BM_62_15 -#define BM_63_15 0xffffffffffff8000 -#define BM_15_63 BM_63_15 -#define BM_16_16 0x0000000000010000 -#define BM_17_16 0x0000000000030000 -#define BM_16_17 BM_17_16 -#define BM_18_16 0x0000000000070000 -#define BM_16_18 BM_18_16 -#define BM_19_16 0x00000000000f0000 -#define BM_16_19 BM_19_16 -#define BM_20_16 0x00000000001f0000 -#define BM_16_20 BM_20_16 -#define BM_21_16 0x00000000003f0000 -#define BM_16_21 BM_21_16 -#define BM_22_16 0x00000000007f0000 -#define BM_16_22 BM_22_16 -#define BM_23_16 0x0000000000ff0000 -#define BM_16_23 BM_23_16 -#define BM_24_16 0x0000000001ff0000 -#define BM_16_24 BM_24_16 -#define BM_25_16 0x0000000003ff0000 -#define BM_16_25 BM_25_16 -#define BM_26_16 0x0000000007ff0000 -#define BM_16_26 BM_26_16 -#define BM_27_16 0x000000000fff0000 -#define BM_16_27 BM_27_16 -#define BM_28_16 0x000000001fff0000 -#define BM_16_28 BM_28_16 -#define BM_29_16 0x000000003fff0000 -#define BM_16_29 BM_29_16 -#define BM_30_16 0x000000007fff0000 -#define BM_16_30 BM_30_16 -#define BM_31_16 0x00000000ffff0000 -#define BM_16_31 BM_31_16 -#define BM_32_16 0x00000001ffff0000 -#define BM_16_32 BM_32_16 -#define BM_33_16 0x00000003ffff0000 -#define BM_16_33 BM_33_16 -#define BM_34_16 0x00000007ffff0000 -#define BM_16_34 BM_34_16 -#define BM_35_16 0x0000000fffff0000 -#define BM_16_35 BM_35_16 -#define BM_36_16 0x0000001fffff0000 -#define BM_16_36 BM_36_16 -#define BM_37_16 0x0000003fffff0000 -#define BM_16_37 BM_37_16 -#define BM_38_16 0x0000007fffff0000 -#define BM_16_38 BM_38_16 -#define BM_39_16 0x000000ffffff0000 -#define BM_16_39 BM_39_16 -#define BM_40_16 0x000001ffffff0000 -#define BM_16_40 BM_40_16 -#define BM_41_16 0x000003ffffff0000 -#define BM_16_41 BM_41_16 -#define BM_42_16 0x000007ffffff0000 -#define BM_16_42 BM_42_16 -#define BM_43_16 0x00000fffffff0000 -#define BM_16_43 BM_43_16 -#define BM_44_16 0x00001fffffff0000 -#define BM_16_44 BM_44_16 -#define BM_45_16 0x00003fffffff0000 -#define BM_16_45 BM_45_16 -#define BM_46_16 0x00007fffffff0000 -#define BM_16_46 BM_46_16 -#define BM_47_16 0x0000ffffffff0000 -#define BM_16_47 BM_47_16 -#define BM_48_16 0x0001ffffffff0000 -#define BM_16_48 BM_48_16 -#define BM_49_16 0x0003ffffffff0000 -#define BM_16_49 BM_49_16 -#define BM_50_16 0x0007ffffffff0000 -#define BM_16_50 BM_50_16 -#define BM_51_16 0x000fffffffff0000 -#define BM_16_51 BM_51_16 -#define BM_52_16 0x001fffffffff0000 -#define BM_16_52 BM_52_16 -#define BM_53_16 0x003fffffffff0000 -#define BM_16_53 BM_53_16 -#define BM_54_16 0x007fffffffff0000 -#define BM_16_54 BM_54_16 -#define BM_55_16 0x00ffffffffff0000 -#define BM_16_55 BM_55_16 -#define BM_56_16 0x01ffffffffff0000 -#define BM_16_56 BM_56_16 -#define BM_57_16 0x03ffffffffff0000 -#define BM_16_57 BM_57_16 -#define BM_58_16 0x07ffffffffff0000 -#define BM_16_58 BM_58_16 -#define BM_59_16 0x0fffffffffff0000 -#define BM_16_59 BM_59_16 -#define BM_60_16 0x1fffffffffff0000 -#define BM_16_60 BM_60_16 -#define BM_61_16 0x3fffffffffff0000 -#define BM_16_61 BM_61_16 -#define BM_62_16 0x7fffffffffff0000 -#define BM_16_62 BM_62_16 -#define BM_63_16 0xffffffffffff0000 -#define BM_16_63 BM_63_16 -#define BM_17_17 0x0000000000020000 -#define BM_18_17 0x0000000000060000 -#define BM_17_18 BM_18_17 -#define BM_19_17 0x00000000000e0000 -#define BM_17_19 BM_19_17 -#define BM_20_17 0x00000000001e0000 -#define BM_17_20 BM_20_17 -#define BM_21_17 0x00000000003e0000 -#define BM_17_21 BM_21_17 -#define BM_22_17 0x00000000007e0000 -#define BM_17_22 BM_22_17 -#define BM_23_17 0x0000000000fe0000 -#define BM_17_23 BM_23_17 -#define BM_24_17 0x0000000001fe0000 -#define BM_17_24 BM_24_17 -#define BM_25_17 0x0000000003fe0000 -#define BM_17_25 BM_25_17 -#define BM_26_17 0x0000000007fe0000 -#define BM_17_26 BM_26_17 -#define BM_27_17 0x000000000ffe0000 -#define BM_17_27 BM_27_17 -#define BM_28_17 0x000000001ffe0000 -#define BM_17_28 BM_28_17 -#define BM_29_17 0x000000003ffe0000 -#define BM_17_29 BM_29_17 -#define BM_30_17 0x000000007ffe0000 -#define BM_17_30 BM_30_17 -#define BM_31_17 0x00000000fffe0000 -#define BM_17_31 BM_31_17 -#define BM_32_17 0x00000001fffe0000 -#define BM_17_32 BM_32_17 -#define BM_33_17 0x00000003fffe0000 -#define BM_17_33 BM_33_17 -#define BM_34_17 0x00000007fffe0000 -#define BM_17_34 BM_34_17 -#define BM_35_17 0x0000000ffffe0000 -#define BM_17_35 BM_35_17 -#define BM_36_17 0x0000001ffffe0000 -#define BM_17_36 BM_36_17 -#define BM_37_17 0x0000003ffffe0000 -#define BM_17_37 BM_37_17 -#define BM_38_17 0x0000007ffffe0000 -#define BM_17_38 BM_38_17 -#define BM_39_17 0x000000fffffe0000 -#define BM_17_39 BM_39_17 -#define BM_40_17 0x000001fffffe0000 -#define BM_17_40 BM_40_17 -#define BM_41_17 0x000003fffffe0000 -#define BM_17_41 BM_41_17 -#define BM_42_17 0x000007fffffe0000 -#define BM_17_42 BM_42_17 -#define BM_43_17 0x00000ffffffe0000 -#define BM_17_43 BM_43_17 -#define BM_44_17 0x00001ffffffe0000 -#define BM_17_44 BM_44_17 -#define BM_45_17 0x00003ffffffe0000 -#define BM_17_45 BM_45_17 -#define BM_46_17 0x00007ffffffe0000 -#define BM_17_46 BM_46_17 -#define BM_47_17 0x0000fffffffe0000 -#define BM_17_47 BM_47_17 -#define BM_48_17 0x0001fffffffe0000 -#define BM_17_48 BM_48_17 -#define BM_49_17 0x0003fffffffe0000 -#define BM_17_49 BM_49_17 -#define BM_50_17 0x0007fffffffe0000 -#define BM_17_50 BM_50_17 -#define BM_51_17 0x000ffffffffe0000 -#define BM_17_51 BM_51_17 -#define BM_52_17 0x001ffffffffe0000 -#define BM_17_52 BM_52_17 -#define BM_53_17 0x003ffffffffe0000 -#define BM_17_53 BM_53_17 -#define BM_54_17 0x007ffffffffe0000 -#define BM_17_54 BM_54_17 -#define BM_55_17 0x00fffffffffe0000 -#define BM_17_55 BM_55_17 -#define BM_56_17 0x01fffffffffe0000 -#define BM_17_56 BM_56_17 -#define BM_57_17 0x03fffffffffe0000 -#define BM_17_57 BM_57_17 -#define BM_58_17 0x07fffffffffe0000 -#define BM_17_58 BM_58_17 -#define BM_59_17 0x0ffffffffffe0000 -#define BM_17_59 BM_59_17 -#define BM_60_17 0x1ffffffffffe0000 -#define BM_17_60 BM_60_17 -#define BM_61_17 0x3ffffffffffe0000 -#define BM_17_61 BM_61_17 -#define BM_62_17 0x7ffffffffffe0000 -#define BM_17_62 BM_62_17 -#define BM_63_17 0xfffffffffffe0000 -#define BM_17_63 BM_63_17 -#define BM_18_18 0x0000000000040000 -#define BM_19_18 0x00000000000c0000 -#define BM_18_19 BM_19_18 -#define BM_20_18 0x00000000001c0000 -#define BM_18_20 BM_20_18 -#define BM_21_18 0x00000000003c0000 -#define BM_18_21 BM_21_18 -#define BM_22_18 0x00000000007c0000 -#define BM_18_22 BM_22_18 -#define BM_23_18 0x0000000000fc0000 -#define BM_18_23 BM_23_18 -#define BM_24_18 0x0000000001fc0000 -#define BM_18_24 BM_24_18 -#define BM_25_18 0x0000000003fc0000 -#define BM_18_25 BM_25_18 -#define BM_26_18 0x0000000007fc0000 -#define BM_18_26 BM_26_18 -#define BM_27_18 0x000000000ffc0000 -#define BM_18_27 BM_27_18 -#define BM_28_18 0x000000001ffc0000 -#define BM_18_28 BM_28_18 -#define BM_29_18 0x000000003ffc0000 -#define BM_18_29 BM_29_18 -#define BM_30_18 0x000000007ffc0000 -#define BM_18_30 BM_30_18 -#define BM_31_18 0x00000000fffc0000 -#define BM_18_31 BM_31_18 -#define BM_32_18 0x00000001fffc0000 -#define BM_18_32 BM_32_18 -#define BM_33_18 0x00000003fffc0000 -#define BM_18_33 BM_33_18 -#define BM_34_18 0x00000007fffc0000 -#define BM_18_34 BM_34_18 -#define BM_35_18 0x0000000ffffc0000 -#define BM_18_35 BM_35_18 -#define BM_36_18 0x0000001ffffc0000 -#define BM_18_36 BM_36_18 -#define BM_37_18 0x0000003ffffc0000 -#define BM_18_37 BM_37_18 -#define BM_38_18 0x0000007ffffc0000 -#define BM_18_38 BM_38_18 -#define BM_39_18 0x000000fffffc0000 -#define BM_18_39 BM_39_18 -#define BM_40_18 0x000001fffffc0000 -#define BM_18_40 BM_40_18 -#define BM_41_18 0x000003fffffc0000 -#define BM_18_41 BM_41_18 -#define BM_42_18 0x000007fffffc0000 -#define BM_18_42 BM_42_18 -#define BM_43_18 0x00000ffffffc0000 -#define BM_18_43 BM_43_18 -#define BM_44_18 0x00001ffffffc0000 -#define BM_18_44 BM_44_18 -#define BM_45_18 0x00003ffffffc0000 -#define BM_18_45 BM_45_18 -#define BM_46_18 0x00007ffffffc0000 -#define BM_18_46 BM_46_18 -#define BM_47_18 0x0000fffffffc0000 -#define BM_18_47 BM_47_18 -#define BM_48_18 0x0001fffffffc0000 -#define BM_18_48 BM_48_18 -#define BM_49_18 0x0003fffffffc0000 -#define BM_18_49 BM_49_18 -#define BM_50_18 0x0007fffffffc0000 -#define BM_18_50 BM_50_18 -#define BM_51_18 0x000ffffffffc0000 -#define BM_18_51 BM_51_18 -#define BM_52_18 0x001ffffffffc0000 -#define BM_18_52 BM_52_18 -#define BM_53_18 0x003ffffffffc0000 -#define BM_18_53 BM_53_18 -#define BM_54_18 0x007ffffffffc0000 -#define BM_18_54 BM_54_18 -#define BM_55_18 0x00fffffffffc0000 -#define BM_18_55 BM_55_18 -#define BM_56_18 0x01fffffffffc0000 -#define BM_18_56 BM_56_18 -#define BM_57_18 0x03fffffffffc0000 -#define BM_18_57 BM_57_18 -#define BM_58_18 0x07fffffffffc0000 -#define BM_18_58 BM_58_18 -#define BM_59_18 0x0ffffffffffc0000 -#define BM_18_59 BM_59_18 -#define BM_60_18 0x1ffffffffffc0000 -#define BM_18_60 BM_60_18 -#define BM_61_18 0x3ffffffffffc0000 -#define BM_18_61 BM_61_18 -#define BM_62_18 0x7ffffffffffc0000 -#define BM_18_62 BM_62_18 -#define BM_63_18 0xfffffffffffc0000 -#define BM_18_63 BM_63_18 -#define BM_19_19 0x0000000000080000 -#define BM_20_19 0x0000000000180000 -#define BM_19_20 BM_20_19 -#define BM_21_19 0x0000000000380000 -#define BM_19_21 BM_21_19 -#define BM_22_19 0x0000000000780000 -#define BM_19_22 BM_22_19 -#define BM_23_19 0x0000000000f80000 -#define BM_19_23 BM_23_19 -#define BM_24_19 0x0000000001f80000 -#define BM_19_24 BM_24_19 -#define BM_25_19 0x0000000003f80000 -#define BM_19_25 BM_25_19 -#define BM_26_19 0x0000000007f80000 -#define BM_19_26 BM_26_19 -#define BM_27_19 0x000000000ff80000 -#define BM_19_27 BM_27_19 -#define BM_28_19 0x000000001ff80000 -#define BM_19_28 BM_28_19 -#define BM_29_19 0x000000003ff80000 -#define BM_19_29 BM_29_19 -#define BM_30_19 0x000000007ff80000 -#define BM_19_30 BM_30_19 -#define BM_31_19 0x00000000fff80000 -#define BM_19_31 BM_31_19 -#define BM_32_19 0x00000001fff80000 -#define BM_19_32 BM_32_19 -#define BM_33_19 0x00000003fff80000 -#define BM_19_33 BM_33_19 -#define BM_34_19 0x00000007fff80000 -#define BM_19_34 BM_34_19 -#define BM_35_19 0x0000000ffff80000 -#define BM_19_35 BM_35_19 -#define BM_36_19 0x0000001ffff80000 -#define BM_19_36 BM_36_19 -#define BM_37_19 0x0000003ffff80000 -#define BM_19_37 BM_37_19 -#define BM_38_19 0x0000007ffff80000 -#define BM_19_38 BM_38_19 -#define BM_39_19 0x000000fffff80000 -#define BM_19_39 BM_39_19 -#define BM_40_19 0x000001fffff80000 -#define BM_19_40 BM_40_19 -#define BM_41_19 0x000003fffff80000 -#define BM_19_41 BM_41_19 -#define BM_42_19 0x000007fffff80000 -#define BM_19_42 BM_42_19 -#define BM_43_19 0x00000ffffff80000 -#define BM_19_43 BM_43_19 -#define BM_44_19 0x00001ffffff80000 -#define BM_19_44 BM_44_19 -#define BM_45_19 0x00003ffffff80000 -#define BM_19_45 BM_45_19 -#define BM_46_19 0x00007ffffff80000 -#define BM_19_46 BM_46_19 -#define BM_47_19 0x0000fffffff80000 -#define BM_19_47 BM_47_19 -#define BM_48_19 0x0001fffffff80000 -#define BM_19_48 BM_48_19 -#define BM_49_19 0x0003fffffff80000 -#define BM_19_49 BM_49_19 -#define BM_50_19 0x0007fffffff80000 -#define BM_19_50 BM_50_19 -#define BM_51_19 0x000ffffffff80000 -#define BM_19_51 BM_51_19 -#define BM_52_19 0x001ffffffff80000 -#define BM_19_52 BM_52_19 -#define BM_53_19 0x003ffffffff80000 -#define BM_19_53 BM_53_19 -#define BM_54_19 0x007ffffffff80000 -#define BM_19_54 BM_54_19 -#define BM_55_19 0x00fffffffff80000 -#define BM_19_55 BM_55_19 -#define BM_56_19 0x01fffffffff80000 -#define BM_19_56 BM_56_19 -#define BM_57_19 0x03fffffffff80000 -#define BM_19_57 BM_57_19 -#define BM_58_19 0x07fffffffff80000 -#define BM_19_58 BM_58_19 -#define BM_59_19 0x0ffffffffff80000 -#define BM_19_59 BM_59_19 -#define BM_60_19 0x1ffffffffff80000 -#define BM_19_60 BM_60_19 -#define BM_61_19 0x3ffffffffff80000 -#define BM_19_61 BM_61_19 -#define BM_62_19 0x7ffffffffff80000 -#define BM_19_62 BM_62_19 -#define BM_63_19 0xfffffffffff80000 -#define BM_19_63 BM_63_19 -#define BM_20_20 0x0000000000100000 -#define BM_21_20 0x0000000000300000 -#define BM_20_21 BM_21_20 -#define BM_22_20 0x0000000000700000 -#define BM_20_22 BM_22_20 -#define BM_23_20 0x0000000000f00000 -#define BM_20_23 BM_23_20 -#define BM_24_20 0x0000000001f00000 -#define BM_20_24 BM_24_20 -#define BM_25_20 0x0000000003f00000 -#define BM_20_25 BM_25_20 -#define BM_26_20 0x0000000007f00000 -#define BM_20_26 BM_26_20 -#define BM_27_20 0x000000000ff00000 -#define BM_20_27 BM_27_20 -#define BM_28_20 0x000000001ff00000 -#define BM_20_28 BM_28_20 -#define BM_29_20 0x000000003ff00000 -#define BM_20_29 BM_29_20 -#define BM_30_20 0x000000007ff00000 -#define BM_20_30 BM_30_20 -#define BM_31_20 0x00000000fff00000 -#define BM_20_31 BM_31_20 -#define BM_32_20 0x00000001fff00000 -#define BM_20_32 BM_32_20 -#define BM_33_20 0x00000003fff00000 -#define BM_20_33 BM_33_20 -#define BM_34_20 0x00000007fff00000 -#define BM_20_34 BM_34_20 -#define BM_35_20 0x0000000ffff00000 -#define BM_20_35 BM_35_20 -#define BM_36_20 0x0000001ffff00000 -#define BM_20_36 BM_36_20 -#define BM_37_20 0x0000003ffff00000 -#define BM_20_37 BM_37_20 -#define BM_38_20 0x0000007ffff00000 -#define BM_20_38 BM_38_20 -#define BM_39_20 0x000000fffff00000 -#define BM_20_39 BM_39_20 -#define BM_40_20 0x000001fffff00000 -#define BM_20_40 BM_40_20 -#define BM_41_20 0x000003fffff00000 -#define BM_20_41 BM_41_20 -#define BM_42_20 0x000007fffff00000 -#define BM_20_42 BM_42_20 -#define BM_43_20 0x00000ffffff00000 -#define BM_20_43 BM_43_20 -#define BM_44_20 0x00001ffffff00000 -#define BM_20_44 BM_44_20 -#define BM_45_20 0x00003ffffff00000 -#define BM_20_45 BM_45_20 -#define BM_46_20 0x00007ffffff00000 -#define BM_20_46 BM_46_20 -#define BM_47_20 0x0000fffffff00000 -#define BM_20_47 BM_47_20 -#define BM_48_20 0x0001fffffff00000 -#define BM_20_48 BM_48_20 -#define BM_49_20 0x0003fffffff00000 -#define BM_20_49 BM_49_20 -#define BM_50_20 0x0007fffffff00000 -#define BM_20_50 BM_50_20 -#define BM_51_20 0x000ffffffff00000 -#define BM_20_51 BM_51_20 -#define BM_52_20 0x001ffffffff00000 -#define BM_20_52 BM_52_20 -#define BM_53_20 0x003ffffffff00000 -#define BM_20_53 BM_53_20 -#define BM_54_20 0x007ffffffff00000 -#define BM_20_54 BM_54_20 -#define BM_55_20 0x00fffffffff00000 -#define BM_20_55 BM_55_20 -#define BM_56_20 0x01fffffffff00000 -#define BM_20_56 BM_56_20 -#define BM_57_20 0x03fffffffff00000 -#define BM_20_57 BM_57_20 -#define BM_58_20 0x07fffffffff00000 -#define BM_20_58 BM_58_20 -#define BM_59_20 0x0ffffffffff00000 -#define BM_20_59 BM_59_20 -#define BM_60_20 0x1ffffffffff00000 -#define BM_20_60 BM_60_20 -#define BM_61_20 0x3ffffffffff00000 -#define BM_20_61 BM_61_20 -#define BM_62_20 0x7ffffffffff00000 -#define BM_20_62 BM_62_20 -#define BM_63_20 0xfffffffffff00000 -#define BM_20_63 BM_63_20 -#define BM_21_21 0x0000000000200000 -#define BM_22_21 0x0000000000600000 -#define BM_21_22 BM_22_21 -#define BM_23_21 0x0000000000e00000 -#define BM_21_23 BM_23_21 -#define BM_24_21 0x0000000001e00000 -#define BM_21_24 BM_24_21 -#define BM_25_21 0x0000000003e00000 -#define BM_21_25 BM_25_21 -#define BM_26_21 0x0000000007e00000 -#define BM_21_26 BM_26_21 -#define BM_27_21 0x000000000fe00000 -#define BM_21_27 BM_27_21 -#define BM_28_21 0x000000001fe00000 -#define BM_21_28 BM_28_21 -#define BM_29_21 0x000000003fe00000 -#define BM_21_29 BM_29_21 -#define BM_30_21 0x000000007fe00000 -#define BM_21_30 BM_30_21 -#define BM_31_21 0x00000000ffe00000 -#define BM_21_31 BM_31_21 -#define BM_32_21 0x00000001ffe00000 -#define BM_21_32 BM_32_21 -#define BM_33_21 0x00000003ffe00000 -#define BM_21_33 BM_33_21 -#define BM_34_21 0x00000007ffe00000 -#define BM_21_34 BM_34_21 -#define BM_35_21 0x0000000fffe00000 -#define BM_21_35 BM_35_21 -#define BM_36_21 0x0000001fffe00000 -#define BM_21_36 BM_36_21 -#define BM_37_21 0x0000003fffe00000 -#define BM_21_37 BM_37_21 -#define BM_38_21 0x0000007fffe00000 -#define BM_21_38 BM_38_21 -#define BM_39_21 0x000000ffffe00000 -#define BM_21_39 BM_39_21 -#define BM_40_21 0x000001ffffe00000 -#define BM_21_40 BM_40_21 -#define BM_41_21 0x000003ffffe00000 -#define BM_21_41 BM_41_21 -#define BM_42_21 0x000007ffffe00000 -#define BM_21_42 BM_42_21 -#define BM_43_21 0x00000fffffe00000 -#define BM_21_43 BM_43_21 -#define BM_44_21 0x00001fffffe00000 -#define BM_21_44 BM_44_21 -#define BM_45_21 0x00003fffffe00000 -#define BM_21_45 BM_45_21 -#define BM_46_21 0x00007fffffe00000 -#define BM_21_46 BM_46_21 -#define BM_47_21 0x0000ffffffe00000 -#define BM_21_47 BM_47_21 -#define BM_48_21 0x0001ffffffe00000 -#define BM_21_48 BM_48_21 -#define BM_49_21 0x0003ffffffe00000 -#define BM_21_49 BM_49_21 -#define BM_50_21 0x0007ffffffe00000 -#define BM_21_50 BM_50_21 -#define BM_51_21 0x000fffffffe00000 -#define BM_21_51 BM_51_21 -#define BM_52_21 0x001fffffffe00000 -#define BM_21_52 BM_52_21 -#define BM_53_21 0x003fffffffe00000 -#define BM_21_53 BM_53_21 -#define BM_54_21 0x007fffffffe00000 -#define BM_21_54 BM_54_21 -#define BM_55_21 0x00ffffffffe00000 -#define BM_21_55 BM_55_21 -#define BM_56_21 0x01ffffffffe00000 -#define BM_21_56 BM_56_21 -#define BM_57_21 0x03ffffffffe00000 -#define BM_21_57 BM_57_21 -#define BM_58_21 0x07ffffffffe00000 -#define BM_21_58 BM_58_21 -#define BM_59_21 0x0fffffffffe00000 -#define BM_21_59 BM_59_21 -#define BM_60_21 0x1fffffffffe00000 -#define BM_21_60 BM_60_21 -#define BM_61_21 0x3fffffffffe00000 -#define BM_21_61 BM_61_21 -#define BM_62_21 0x7fffffffffe00000 -#define BM_21_62 BM_62_21 -#define BM_63_21 0xffffffffffe00000 -#define BM_21_63 BM_63_21 -#define BM_22_22 0x0000000000400000 -#define BM_23_22 0x0000000000c00000 -#define BM_22_23 BM_23_22 -#define BM_24_22 0x0000000001c00000 -#define BM_22_24 BM_24_22 -#define BM_25_22 0x0000000003c00000 -#define BM_22_25 BM_25_22 -#define BM_26_22 0x0000000007c00000 -#define BM_22_26 BM_26_22 -#define BM_27_22 0x000000000fc00000 -#define BM_22_27 BM_27_22 -#define BM_28_22 0x000000001fc00000 -#define BM_22_28 BM_28_22 -#define BM_29_22 0x000000003fc00000 -#define BM_22_29 BM_29_22 -#define BM_30_22 0x000000007fc00000 -#define BM_22_30 BM_30_22 -#define BM_31_22 0x00000000ffc00000 -#define BM_22_31 BM_31_22 -#define BM_32_22 0x00000001ffc00000 -#define BM_22_32 BM_32_22 -#define BM_33_22 0x00000003ffc00000 -#define BM_22_33 BM_33_22 -#define BM_34_22 0x00000007ffc00000 -#define BM_22_34 BM_34_22 -#define BM_35_22 0x0000000fffc00000 -#define BM_22_35 BM_35_22 -#define BM_36_22 0x0000001fffc00000 -#define BM_22_36 BM_36_22 -#define BM_37_22 0x0000003fffc00000 -#define BM_22_37 BM_37_22 -#define BM_38_22 0x0000007fffc00000 -#define BM_22_38 BM_38_22 -#define BM_39_22 0x000000ffffc00000 -#define BM_22_39 BM_39_22 -#define BM_40_22 0x000001ffffc00000 -#define BM_22_40 BM_40_22 -#define BM_41_22 0x000003ffffc00000 -#define BM_22_41 BM_41_22 -#define BM_42_22 0x000007ffffc00000 -#define BM_22_42 BM_42_22 -#define BM_43_22 0x00000fffffc00000 -#define BM_22_43 BM_43_22 -#define BM_44_22 0x00001fffffc00000 -#define BM_22_44 BM_44_22 -#define BM_45_22 0x00003fffffc00000 -#define BM_22_45 BM_45_22 -#define BM_46_22 0x00007fffffc00000 -#define BM_22_46 BM_46_22 -#define BM_47_22 0x0000ffffffc00000 -#define BM_22_47 BM_47_22 -#define BM_48_22 0x0001ffffffc00000 -#define BM_22_48 BM_48_22 -#define BM_49_22 0x0003ffffffc00000 -#define BM_22_49 BM_49_22 -#define BM_50_22 0x0007ffffffc00000 -#define BM_22_50 BM_50_22 -#define BM_51_22 0x000fffffffc00000 -#define BM_22_51 BM_51_22 -#define BM_52_22 0x001fffffffc00000 -#define BM_22_52 BM_52_22 -#define BM_53_22 0x003fffffffc00000 -#define BM_22_53 BM_53_22 -#define BM_54_22 0x007fffffffc00000 -#define BM_22_54 BM_54_22 -#define BM_55_22 0x00ffffffffc00000 -#define BM_22_55 BM_55_22 -#define BM_56_22 0x01ffffffffc00000 -#define BM_22_56 BM_56_22 -#define BM_57_22 0x03ffffffffc00000 -#define BM_22_57 BM_57_22 -#define BM_58_22 0x07ffffffffc00000 -#define BM_22_58 BM_58_22 -#define BM_59_22 0x0fffffffffc00000 -#define BM_22_59 BM_59_22 -#define BM_60_22 0x1fffffffffc00000 -#define BM_22_60 BM_60_22 -#define BM_61_22 0x3fffffffffc00000 -#define BM_22_61 BM_61_22 -#define BM_62_22 0x7fffffffffc00000 -#define BM_22_62 BM_62_22 -#define BM_63_22 0xffffffffffc00000 -#define BM_22_63 BM_63_22 -#define BM_23_23 0x0000000000800000 -#define BM_24_23 0x0000000001800000 -#define BM_23_24 BM_24_23 -#define BM_25_23 0x0000000003800000 -#define BM_23_25 BM_25_23 -#define BM_26_23 0x0000000007800000 -#define BM_23_26 BM_26_23 -#define BM_27_23 0x000000000f800000 -#define BM_23_27 BM_27_23 -#define BM_28_23 0x000000001f800000 -#define BM_23_28 BM_28_23 -#define BM_29_23 0x000000003f800000 -#define BM_23_29 BM_29_23 -#define BM_30_23 0x000000007f800000 -#define BM_23_30 BM_30_23 -#define BM_31_23 0x00000000ff800000 -#define BM_23_31 BM_31_23 -#define BM_32_23 0x00000001ff800000 -#define BM_23_32 BM_32_23 -#define BM_33_23 0x00000003ff800000 -#define BM_23_33 BM_33_23 -#define BM_34_23 0x00000007ff800000 -#define BM_23_34 BM_34_23 -#define BM_35_23 0x0000000fff800000 -#define BM_23_35 BM_35_23 -#define BM_36_23 0x0000001fff800000 -#define BM_23_36 BM_36_23 -#define BM_37_23 0x0000003fff800000 -#define BM_23_37 BM_37_23 -#define BM_38_23 0x0000007fff800000 -#define BM_23_38 BM_38_23 -#define BM_39_23 0x000000ffff800000 -#define BM_23_39 BM_39_23 -#define BM_40_23 0x000001ffff800000 -#define BM_23_40 BM_40_23 -#define BM_41_23 0x000003ffff800000 -#define BM_23_41 BM_41_23 -#define BM_42_23 0x000007ffff800000 -#define BM_23_42 BM_42_23 -#define BM_43_23 0x00000fffff800000 -#define BM_23_43 BM_43_23 -#define BM_44_23 0x00001fffff800000 -#define BM_23_44 BM_44_23 -#define BM_45_23 0x00003fffff800000 -#define BM_23_45 BM_45_23 -#define BM_46_23 0x00007fffff800000 -#define BM_23_46 BM_46_23 -#define BM_47_23 0x0000ffffff800000 -#define BM_23_47 BM_47_23 -#define BM_48_23 0x0001ffffff800000 -#define BM_23_48 BM_48_23 -#define BM_49_23 0x0003ffffff800000 -#define BM_23_49 BM_49_23 -#define BM_50_23 0x0007ffffff800000 -#define BM_23_50 BM_50_23 -#define BM_51_23 0x000fffffff800000 -#define BM_23_51 BM_51_23 -#define BM_52_23 0x001fffffff800000 -#define BM_23_52 BM_52_23 -#define BM_53_23 0x003fffffff800000 -#define BM_23_53 BM_53_23 -#define BM_54_23 0x007fffffff800000 -#define BM_23_54 BM_54_23 -#define BM_55_23 0x00ffffffff800000 -#define BM_23_55 BM_55_23 -#define BM_56_23 0x01ffffffff800000 -#define BM_23_56 BM_56_23 -#define BM_57_23 0x03ffffffff800000 -#define BM_23_57 BM_57_23 -#define BM_58_23 0x07ffffffff800000 -#define BM_23_58 BM_58_23 -#define BM_59_23 0x0fffffffff800000 -#define BM_23_59 BM_59_23 -#define BM_60_23 0x1fffffffff800000 -#define BM_23_60 BM_60_23 -#define BM_61_23 0x3fffffffff800000 -#define BM_23_61 BM_61_23 -#define BM_62_23 0x7fffffffff800000 -#define BM_23_62 BM_62_23 -#define BM_63_23 0xffffffffff800000 -#define BM_23_63 BM_63_23 -#define BM_24_24 0x0000000001000000 -#define BM_25_24 0x0000000003000000 -#define BM_24_25 BM_25_24 -#define BM_26_24 0x0000000007000000 -#define BM_24_26 BM_26_24 -#define BM_27_24 0x000000000f000000 -#define BM_24_27 BM_27_24 -#define BM_28_24 0x000000001f000000 -#define BM_24_28 BM_28_24 -#define BM_29_24 0x000000003f000000 -#define BM_24_29 BM_29_24 -#define BM_30_24 0x000000007f000000 -#define BM_24_30 BM_30_24 -#define BM_31_24 0x00000000ff000000 -#define BM_24_31 BM_31_24 -#define BM_32_24 0x00000001ff000000 -#define BM_24_32 BM_32_24 -#define BM_33_24 0x00000003ff000000 -#define BM_24_33 BM_33_24 -#define BM_34_24 0x00000007ff000000 -#define BM_24_34 BM_34_24 -#define BM_35_24 0x0000000fff000000 -#define BM_24_35 BM_35_24 -#define BM_36_24 0x0000001fff000000 -#define BM_24_36 BM_36_24 -#define BM_37_24 0x0000003fff000000 -#define BM_24_37 BM_37_24 -#define BM_38_24 0x0000007fff000000 -#define BM_24_38 BM_38_24 -#define BM_39_24 0x000000ffff000000 -#define BM_24_39 BM_39_24 -#define BM_40_24 0x000001ffff000000 -#define BM_24_40 BM_40_24 -#define BM_41_24 0x000003ffff000000 -#define BM_24_41 BM_41_24 -#define BM_42_24 0x000007ffff000000 -#define BM_24_42 BM_42_24 -#define BM_43_24 0x00000fffff000000 -#define BM_24_43 BM_43_24 -#define BM_44_24 0x00001fffff000000 -#define BM_24_44 BM_44_24 -#define BM_45_24 0x00003fffff000000 -#define BM_24_45 BM_45_24 -#define BM_46_24 0x00007fffff000000 -#define BM_24_46 BM_46_24 -#define BM_47_24 0x0000ffffff000000 -#define BM_24_47 BM_47_24 -#define BM_48_24 0x0001ffffff000000 -#define BM_24_48 BM_48_24 -#define BM_49_24 0x0003ffffff000000 -#define BM_24_49 BM_49_24 -#define BM_50_24 0x0007ffffff000000 -#define BM_24_50 BM_50_24 -#define BM_51_24 0x000fffffff000000 -#define BM_24_51 BM_51_24 -#define BM_52_24 0x001fffffff000000 -#define BM_24_52 BM_52_24 -#define BM_53_24 0x003fffffff000000 -#define BM_24_53 BM_53_24 -#define BM_54_24 0x007fffffff000000 -#define BM_24_54 BM_54_24 -#define BM_55_24 0x00ffffffff000000 -#define BM_24_55 BM_55_24 -#define BM_56_24 0x01ffffffff000000 -#define BM_24_56 BM_56_24 -#define BM_57_24 0x03ffffffff000000 -#define BM_24_57 BM_57_24 -#define BM_58_24 0x07ffffffff000000 -#define BM_24_58 BM_58_24 -#define BM_59_24 0x0fffffffff000000 -#define BM_24_59 BM_59_24 -#define BM_60_24 0x1fffffffff000000 -#define BM_24_60 BM_60_24 -#define BM_61_24 0x3fffffffff000000 -#define BM_24_61 BM_61_24 -#define BM_62_24 0x7fffffffff000000 -#define BM_24_62 BM_62_24 -#define BM_63_24 0xffffffffff000000 -#define BM_24_63 BM_63_24 -#define BM_25_25 0x0000000002000000 -#define BM_26_25 0x0000000006000000 -#define BM_25_26 BM_26_25 -#define BM_27_25 0x000000000e000000 -#define BM_25_27 BM_27_25 -#define BM_28_25 0x000000001e000000 -#define BM_25_28 BM_28_25 -#define BM_29_25 0x000000003e000000 -#define BM_25_29 BM_29_25 -#define BM_30_25 0x000000007e000000 -#define BM_25_30 BM_30_25 -#define BM_31_25 0x00000000fe000000 -#define BM_25_31 BM_31_25 -#define BM_32_25 0x00000001fe000000 -#define BM_25_32 BM_32_25 -#define BM_33_25 0x00000003fe000000 -#define BM_25_33 BM_33_25 -#define BM_34_25 0x00000007fe000000 -#define BM_25_34 BM_34_25 -#define BM_35_25 0x0000000ffe000000 -#define BM_25_35 BM_35_25 -#define BM_36_25 0x0000001ffe000000 -#define BM_25_36 BM_36_25 -#define BM_37_25 0x0000003ffe000000 -#define BM_25_37 BM_37_25 -#define BM_38_25 0x0000007ffe000000 -#define BM_25_38 BM_38_25 -#define BM_39_25 0x000000fffe000000 -#define BM_25_39 BM_39_25 -#define BM_40_25 0x000001fffe000000 -#define BM_25_40 BM_40_25 -#define BM_41_25 0x000003fffe000000 -#define BM_25_41 BM_41_25 -#define BM_42_25 0x000007fffe000000 -#define BM_25_42 BM_42_25 -#define BM_43_25 0x00000ffffe000000 -#define BM_25_43 BM_43_25 -#define BM_44_25 0x00001ffffe000000 -#define BM_25_44 BM_44_25 -#define BM_45_25 0x00003ffffe000000 -#define BM_25_45 BM_45_25 -#define BM_46_25 0x00007ffffe000000 -#define BM_25_46 BM_46_25 -#define BM_47_25 0x0000fffffe000000 -#define BM_25_47 BM_47_25 -#define BM_48_25 0x0001fffffe000000 -#define BM_25_48 BM_48_25 -#define BM_49_25 0x0003fffffe000000 -#define BM_25_49 BM_49_25 -#define BM_50_25 0x0007fffffe000000 -#define BM_25_50 BM_50_25 -#define BM_51_25 0x000ffffffe000000 -#define BM_25_51 BM_51_25 -#define BM_52_25 0x001ffffffe000000 -#define BM_25_52 BM_52_25 -#define BM_53_25 0x003ffffffe000000 -#define BM_25_53 BM_53_25 -#define BM_54_25 0x007ffffffe000000 -#define BM_25_54 BM_54_25 -#define BM_55_25 0x00fffffffe000000 -#define BM_25_55 BM_55_25 -#define BM_56_25 0x01fffffffe000000 -#define BM_25_56 BM_56_25 -#define BM_57_25 0x03fffffffe000000 -#define BM_25_57 BM_57_25 -#define BM_58_25 0x07fffffffe000000 -#define BM_25_58 BM_58_25 -#define BM_59_25 0x0ffffffffe000000 -#define BM_25_59 BM_59_25 -#define BM_60_25 0x1ffffffffe000000 -#define BM_25_60 BM_60_25 -#define BM_61_25 0x3ffffffffe000000 -#define BM_25_61 BM_61_25 -#define BM_62_25 0x7ffffffffe000000 -#define BM_25_62 BM_62_25 -#define BM_63_25 0xfffffffffe000000 -#define BM_25_63 BM_63_25 -#define BM_26_26 0x0000000004000000 -#define BM_27_26 0x000000000c000000 -#define BM_26_27 BM_27_26 -#define BM_28_26 0x000000001c000000 -#define BM_26_28 BM_28_26 -#define BM_29_26 0x000000003c000000 -#define BM_26_29 BM_29_26 -#define BM_30_26 0x000000007c000000 -#define BM_26_30 BM_30_26 -#define BM_31_26 0x00000000fc000000 -#define BM_26_31 BM_31_26 -#define BM_32_26 0x00000001fc000000 -#define BM_26_32 BM_32_26 -#define BM_33_26 0x00000003fc000000 -#define BM_26_33 BM_33_26 -#define BM_34_26 0x00000007fc000000 -#define BM_26_34 BM_34_26 -#define BM_35_26 0x0000000ffc000000 -#define BM_26_35 BM_35_26 -#define BM_36_26 0x0000001ffc000000 -#define BM_26_36 BM_36_26 -#define BM_37_26 0x0000003ffc000000 -#define BM_26_37 BM_37_26 -#define BM_38_26 0x0000007ffc000000 -#define BM_26_38 BM_38_26 -#define BM_39_26 0x000000fffc000000 -#define BM_26_39 BM_39_26 -#define BM_40_26 0x000001fffc000000 -#define BM_26_40 BM_40_26 -#define BM_41_26 0x000003fffc000000 -#define BM_26_41 BM_41_26 -#define BM_42_26 0x000007fffc000000 -#define BM_26_42 BM_42_26 -#define BM_43_26 0x00000ffffc000000 -#define BM_26_43 BM_43_26 -#define BM_44_26 0x00001ffffc000000 -#define BM_26_44 BM_44_26 -#define BM_45_26 0x00003ffffc000000 -#define BM_26_45 BM_45_26 -#define BM_46_26 0x00007ffffc000000 -#define BM_26_46 BM_46_26 -#define BM_47_26 0x0000fffffc000000 -#define BM_26_47 BM_47_26 -#define BM_48_26 0x0001fffffc000000 -#define BM_26_48 BM_48_26 -#define BM_49_26 0x0003fffffc000000 -#define BM_26_49 BM_49_26 -#define BM_50_26 0x0007fffffc000000 -#define BM_26_50 BM_50_26 -#define BM_51_26 0x000ffffffc000000 -#define BM_26_51 BM_51_26 -#define BM_52_26 0x001ffffffc000000 -#define BM_26_52 BM_52_26 -#define BM_53_26 0x003ffffffc000000 -#define BM_26_53 BM_53_26 -#define BM_54_26 0x007ffffffc000000 -#define BM_26_54 BM_54_26 -#define BM_55_26 0x00fffffffc000000 -#define BM_26_55 BM_55_26 -#define BM_56_26 0x01fffffffc000000 -#define BM_26_56 BM_56_26 -#define BM_57_26 0x03fffffffc000000 -#define BM_26_57 BM_57_26 -#define BM_58_26 0x07fffffffc000000 -#define BM_26_58 BM_58_26 -#define BM_59_26 0x0ffffffffc000000 -#define BM_26_59 BM_59_26 -#define BM_60_26 0x1ffffffffc000000 -#define BM_26_60 BM_60_26 -#define BM_61_26 0x3ffffffffc000000 -#define BM_26_61 BM_61_26 -#define BM_62_26 0x7ffffffffc000000 -#define BM_26_62 BM_62_26 -#define BM_63_26 0xfffffffffc000000 -#define BM_26_63 BM_63_26 -#define BM_27_27 0x0000000008000000 -#define BM_28_27 0x0000000018000000 -#define BM_27_28 BM_28_27 -#define BM_29_27 0x0000000038000000 -#define BM_27_29 BM_29_27 -#define BM_30_27 0x0000000078000000 -#define BM_27_30 BM_30_27 -#define BM_31_27 0x00000000f8000000 -#define BM_27_31 BM_31_27 -#define BM_32_27 0x00000001f8000000 -#define BM_27_32 BM_32_27 -#define BM_33_27 0x00000003f8000000 -#define BM_27_33 BM_33_27 -#define BM_34_27 0x00000007f8000000 -#define BM_27_34 BM_34_27 -#define BM_35_27 0x0000000ff8000000 -#define BM_27_35 BM_35_27 -#define BM_36_27 0x0000001ff8000000 -#define BM_27_36 BM_36_27 -#define BM_37_27 0x0000003ff8000000 -#define BM_27_37 BM_37_27 -#define BM_38_27 0x0000007ff8000000 -#define BM_27_38 BM_38_27 -#define BM_39_27 0x000000fff8000000 -#define BM_27_39 BM_39_27 -#define BM_40_27 0x000001fff8000000 -#define BM_27_40 BM_40_27 -#define BM_41_27 0x000003fff8000000 -#define BM_27_41 BM_41_27 -#define BM_42_27 0x000007fff8000000 -#define BM_27_42 BM_42_27 -#define BM_43_27 0x00000ffff8000000 -#define BM_27_43 BM_43_27 -#define BM_44_27 0x00001ffff8000000 -#define BM_27_44 BM_44_27 -#define BM_45_27 0x00003ffff8000000 -#define BM_27_45 BM_45_27 -#define BM_46_27 0x00007ffff8000000 -#define BM_27_46 BM_46_27 -#define BM_47_27 0x0000fffff8000000 -#define BM_27_47 BM_47_27 -#define BM_48_27 0x0001fffff8000000 -#define BM_27_48 BM_48_27 -#define BM_49_27 0x0003fffff8000000 -#define BM_27_49 BM_49_27 -#define BM_50_27 0x0007fffff8000000 -#define BM_27_50 BM_50_27 -#define BM_51_27 0x000ffffff8000000 -#define BM_27_51 BM_51_27 -#define BM_52_27 0x001ffffff8000000 -#define BM_27_52 BM_52_27 -#define BM_53_27 0x003ffffff8000000 -#define BM_27_53 BM_53_27 -#define BM_54_27 0x007ffffff8000000 -#define BM_27_54 BM_54_27 -#define BM_55_27 0x00fffffff8000000 -#define BM_27_55 BM_55_27 -#define BM_56_27 0x01fffffff8000000 -#define BM_27_56 BM_56_27 -#define BM_57_27 0x03fffffff8000000 -#define BM_27_57 BM_57_27 -#define BM_58_27 0x07fffffff8000000 -#define BM_27_58 BM_58_27 -#define BM_59_27 0x0ffffffff8000000 -#define BM_27_59 BM_59_27 -#define BM_60_27 0x1ffffffff8000000 -#define BM_27_60 BM_60_27 -#define BM_61_27 0x3ffffffff8000000 -#define BM_27_61 BM_61_27 -#define BM_62_27 0x7ffffffff8000000 -#define BM_27_62 BM_62_27 -#define BM_63_27 0xfffffffff8000000 -#define BM_27_63 BM_63_27 -#define BM_28_28 0x0000000010000000 -#define BM_29_28 0x0000000030000000 -#define BM_28_29 BM_29_28 -#define BM_30_28 0x0000000070000000 -#define BM_28_30 BM_30_28 -#define BM_31_28 0x00000000f0000000 -#define BM_28_31 BM_31_28 -#define BM_32_28 0x00000001f0000000 -#define BM_28_32 BM_32_28 -#define BM_33_28 0x00000003f0000000 -#define BM_28_33 BM_33_28 -#define BM_34_28 0x00000007f0000000 -#define BM_28_34 BM_34_28 -#define BM_35_28 0x0000000ff0000000 -#define BM_28_35 BM_35_28 -#define BM_36_28 0x0000001ff0000000 -#define BM_28_36 BM_36_28 -#define BM_37_28 0x0000003ff0000000 -#define BM_28_37 BM_37_28 -#define BM_38_28 0x0000007ff0000000 -#define BM_28_38 BM_38_28 -#define BM_39_28 0x000000fff0000000 -#define BM_28_39 BM_39_28 -#define BM_40_28 0x000001fff0000000 -#define BM_28_40 BM_40_28 -#define BM_41_28 0x000003fff0000000 -#define BM_28_41 BM_41_28 -#define BM_42_28 0x000007fff0000000 -#define BM_28_42 BM_42_28 -#define BM_43_28 0x00000ffff0000000 -#define BM_28_43 BM_43_28 -#define BM_44_28 0x00001ffff0000000 -#define BM_28_44 BM_44_28 -#define BM_45_28 0x00003ffff0000000 -#define BM_28_45 BM_45_28 -#define BM_46_28 0x00007ffff0000000 -#define BM_28_46 BM_46_28 -#define BM_47_28 0x0000fffff0000000 -#define BM_28_47 BM_47_28 -#define BM_48_28 0x0001fffff0000000 -#define BM_28_48 BM_48_28 -#define BM_49_28 0x0003fffff0000000 -#define BM_28_49 BM_49_28 -#define BM_50_28 0x0007fffff0000000 -#define BM_28_50 BM_50_28 -#define BM_51_28 0x000ffffff0000000 -#define BM_28_51 BM_51_28 -#define BM_52_28 0x001ffffff0000000 -#define BM_28_52 BM_52_28 -#define BM_53_28 0x003ffffff0000000 -#define BM_28_53 BM_53_28 -#define BM_54_28 0x007ffffff0000000 -#define BM_28_54 BM_54_28 -#define BM_55_28 0x00fffffff0000000 -#define BM_28_55 BM_55_28 -#define BM_56_28 0x01fffffff0000000 -#define BM_28_56 BM_56_28 -#define BM_57_28 0x03fffffff0000000 -#define BM_28_57 BM_57_28 -#define BM_58_28 0x07fffffff0000000 -#define BM_28_58 BM_58_28 -#define BM_59_28 0x0ffffffff0000000 -#define BM_28_59 BM_59_28 -#define BM_60_28 0x1ffffffff0000000 -#define BM_28_60 BM_60_28 -#define BM_61_28 0x3ffffffff0000000 -#define BM_28_61 BM_61_28 -#define BM_62_28 0x7ffffffff0000000 -#define BM_28_62 BM_62_28 -#define BM_63_28 0xfffffffff0000000 -#define BM_28_63 BM_63_28 -#define BM_29_29 0x0000000020000000 -#define BM_30_29 0x0000000060000000 -#define BM_29_30 BM_30_29 -#define BM_31_29 0x00000000e0000000 -#define BM_29_31 BM_31_29 -#define BM_32_29 0x00000001e0000000 -#define BM_29_32 BM_32_29 -#define BM_33_29 0x00000003e0000000 -#define BM_29_33 BM_33_29 -#define BM_34_29 0x00000007e0000000 -#define BM_29_34 BM_34_29 -#define BM_35_29 0x0000000fe0000000 -#define BM_29_35 BM_35_29 -#define BM_36_29 0x0000001fe0000000 -#define BM_29_36 BM_36_29 -#define BM_37_29 0x0000003fe0000000 -#define BM_29_37 BM_37_29 -#define BM_38_29 0x0000007fe0000000 -#define BM_29_38 BM_38_29 -#define BM_39_29 0x000000ffe0000000 -#define BM_29_39 BM_39_29 -#define BM_40_29 0x000001ffe0000000 -#define BM_29_40 BM_40_29 -#define BM_41_29 0x000003ffe0000000 -#define BM_29_41 BM_41_29 -#define BM_42_29 0x000007ffe0000000 -#define BM_29_42 BM_42_29 -#define BM_43_29 0x00000fffe0000000 -#define BM_29_43 BM_43_29 -#define BM_44_29 0x00001fffe0000000 -#define BM_29_44 BM_44_29 -#define BM_45_29 0x00003fffe0000000 -#define BM_29_45 BM_45_29 -#define BM_46_29 0x00007fffe0000000 -#define BM_29_46 BM_46_29 -#define BM_47_29 0x0000ffffe0000000 -#define BM_29_47 BM_47_29 -#define BM_48_29 0x0001ffffe0000000 -#define BM_29_48 BM_48_29 -#define BM_49_29 0x0003ffffe0000000 -#define BM_29_49 BM_49_29 -#define BM_50_29 0x0007ffffe0000000 -#define BM_29_50 BM_50_29 -#define BM_51_29 0x000fffffe0000000 -#define BM_29_51 BM_51_29 -#define BM_52_29 0x001fffffe0000000 -#define BM_29_52 BM_52_29 -#define BM_53_29 0x003fffffe0000000 -#define BM_29_53 BM_53_29 -#define BM_54_29 0x007fffffe0000000 -#define BM_29_54 BM_54_29 -#define BM_55_29 0x00ffffffe0000000 -#define BM_29_55 BM_55_29 -#define BM_56_29 0x01ffffffe0000000 -#define BM_29_56 BM_56_29 -#define BM_57_29 0x03ffffffe0000000 -#define BM_29_57 BM_57_29 -#define BM_58_29 0x07ffffffe0000000 -#define BM_29_58 BM_58_29 -#define BM_59_29 0x0fffffffe0000000 -#define BM_29_59 BM_59_29 -#define BM_60_29 0x1fffffffe0000000 -#define BM_29_60 BM_60_29 -#define BM_61_29 0x3fffffffe0000000 -#define BM_29_61 BM_61_29 -#define BM_62_29 0x7fffffffe0000000 -#define BM_29_62 BM_62_29 -#define BM_63_29 0xffffffffe0000000 -#define BM_29_63 BM_63_29 -#define BM_30_30 0x0000000040000000 -#define BM_31_30 0x00000000c0000000 -#define BM_30_31 BM_31_30 -#define BM_32_30 0x00000001c0000000 -#define BM_30_32 BM_32_30 -#define BM_33_30 0x00000003c0000000 -#define BM_30_33 BM_33_30 -#define BM_34_30 0x00000007c0000000 -#define BM_30_34 BM_34_30 -#define BM_35_30 0x0000000fc0000000 -#define BM_30_35 BM_35_30 -#define BM_36_30 0x0000001fc0000000 -#define BM_30_36 BM_36_30 -#define BM_37_30 0x0000003fc0000000 -#define BM_30_37 BM_37_30 -#define BM_38_30 0x0000007fc0000000 -#define BM_30_38 BM_38_30 -#define BM_39_30 0x000000ffc0000000 -#define BM_30_39 BM_39_30 -#define BM_40_30 0x000001ffc0000000 -#define BM_30_40 BM_40_30 -#define BM_41_30 0x000003ffc0000000 -#define BM_30_41 BM_41_30 -#define BM_42_30 0x000007ffc0000000 -#define BM_30_42 BM_42_30 -#define BM_43_30 0x00000fffc0000000 -#define BM_30_43 BM_43_30 -#define BM_44_30 0x00001fffc0000000 -#define BM_30_44 BM_44_30 -#define BM_45_30 0x00003fffc0000000 -#define BM_30_45 BM_45_30 -#define BM_46_30 0x00007fffc0000000 -#define BM_30_46 BM_46_30 -#define BM_47_30 0x0000ffffc0000000 -#define BM_30_47 BM_47_30 -#define BM_48_30 0x0001ffffc0000000 -#define BM_30_48 BM_48_30 -#define BM_49_30 0x0003ffffc0000000 -#define BM_30_49 BM_49_30 -#define BM_50_30 0x0007ffffc0000000 -#define BM_30_50 BM_50_30 -#define BM_51_30 0x000fffffc0000000 -#define BM_30_51 BM_51_30 -#define BM_52_30 0x001fffffc0000000 -#define BM_30_52 BM_52_30 -#define BM_53_30 0x003fffffc0000000 -#define BM_30_53 BM_53_30 -#define BM_54_30 0x007fffffc0000000 -#define BM_30_54 BM_54_30 -#define BM_55_30 0x00ffffffc0000000 -#define BM_30_55 BM_55_30 -#define BM_56_30 0x01ffffffc0000000 -#define BM_30_56 BM_56_30 -#define BM_57_30 0x03ffffffc0000000 -#define BM_30_57 BM_57_30 -#define BM_58_30 0x07ffffffc0000000 -#define BM_30_58 BM_58_30 -#define BM_59_30 0x0fffffffc0000000 -#define BM_30_59 BM_59_30 -#define BM_60_30 0x1fffffffc0000000 -#define BM_30_60 BM_60_30 -#define BM_61_30 0x3fffffffc0000000 -#define BM_30_61 BM_61_30 -#define BM_62_30 0x7fffffffc0000000 -#define BM_30_62 BM_62_30 -#define BM_63_30 0xffffffffc0000000 -#define BM_30_63 BM_63_30 -#define BM_31_31 0x0000000080000000 -#define BM_32_31 0x0000000180000000 -#define BM_31_32 BM_32_31 -#define BM_33_31 0x0000000380000000 -#define BM_31_33 BM_33_31 -#define BM_34_31 0x0000000780000000 -#define BM_31_34 BM_34_31 -#define BM_35_31 0x0000000f80000000 -#define BM_31_35 BM_35_31 -#define BM_36_31 0x0000001f80000000 -#define BM_31_36 BM_36_31 -#define BM_37_31 0x0000003f80000000 -#define BM_31_37 BM_37_31 -#define BM_38_31 0x0000007f80000000 -#define BM_31_38 BM_38_31 -#define BM_39_31 0x000000ff80000000 -#define BM_31_39 BM_39_31 -#define BM_40_31 0x000001ff80000000 -#define BM_31_40 BM_40_31 -#define BM_41_31 0x000003ff80000000 -#define BM_31_41 BM_41_31 -#define BM_42_31 0x000007ff80000000 -#define BM_31_42 BM_42_31 -#define BM_43_31 0x00000fff80000000 -#define BM_31_43 BM_43_31 -#define BM_44_31 0x00001fff80000000 -#define BM_31_44 BM_44_31 -#define BM_45_31 0x00003fff80000000 -#define BM_31_45 BM_45_31 -#define BM_46_31 0x00007fff80000000 -#define BM_31_46 BM_46_31 -#define BM_47_31 0x0000ffff80000000 -#define BM_31_47 BM_47_31 -#define BM_48_31 0x0001ffff80000000 -#define BM_31_48 BM_48_31 -#define BM_49_31 0x0003ffff80000000 -#define BM_31_49 BM_49_31 -#define BM_50_31 0x0007ffff80000000 -#define BM_31_50 BM_50_31 -#define BM_51_31 0x000fffff80000000 -#define BM_31_51 BM_51_31 -#define BM_52_31 0x001fffff80000000 -#define BM_31_52 BM_52_31 -#define BM_53_31 0x003fffff80000000 -#define BM_31_53 BM_53_31 -#define BM_54_31 0x007fffff80000000 -#define BM_31_54 BM_54_31 -#define BM_55_31 0x00ffffff80000000 -#define BM_31_55 BM_55_31 -#define BM_56_31 0x01ffffff80000000 -#define BM_31_56 BM_56_31 -#define BM_57_31 0x03ffffff80000000 -#define BM_31_57 BM_57_31 -#define BM_58_31 0x07ffffff80000000 -#define BM_31_58 BM_58_31 -#define BM_59_31 0x0fffffff80000000 -#define BM_31_59 BM_59_31 -#define BM_60_31 0x1fffffff80000000 -#define BM_31_60 BM_60_31 -#define BM_61_31 0x3fffffff80000000 -#define BM_31_61 BM_61_31 -#define BM_62_31 0x7fffffff80000000 -#define BM_31_62 BM_62_31 -#define BM_63_31 0xffffffff80000000 -#define BM_31_63 BM_63_31 -#define BM_32_32 0x0000000100000000 -#define BM_33_32 0x0000000300000000 -#define BM_32_33 BM_33_32 -#define BM_34_32 0x0000000700000000 -#define BM_32_34 BM_34_32 -#define BM_35_32 0x0000000f00000000 -#define BM_32_35 BM_35_32 -#define BM_36_32 0x0000001f00000000 -#define BM_32_36 BM_36_32 -#define BM_37_32 0x0000003f00000000 -#define BM_32_37 BM_37_32 -#define BM_38_32 0x0000007f00000000 -#define BM_32_38 BM_38_32 -#define BM_39_32 0x000000ff00000000 -#define BM_32_39 BM_39_32 -#define BM_40_32 0x000001ff00000000 -#define BM_32_40 BM_40_32 -#define BM_41_32 0x000003ff00000000 -#define BM_32_41 BM_41_32 -#define BM_42_32 0x000007ff00000000 -#define BM_32_42 BM_42_32 -#define BM_43_32 0x00000fff00000000 -#define BM_32_43 BM_43_32 -#define BM_44_32 0x00001fff00000000 -#define BM_32_44 BM_44_32 -#define BM_45_32 0x00003fff00000000 -#define BM_32_45 BM_45_32 -#define BM_46_32 0x00007fff00000000 -#define BM_32_46 BM_46_32 -#define BM_47_32 0x0000ffff00000000 -#define BM_32_47 BM_47_32 -#define BM_48_32 0x0001ffff00000000 -#define BM_32_48 BM_48_32 -#define BM_49_32 0x0003ffff00000000 -#define BM_32_49 BM_49_32 -#define BM_50_32 0x0007ffff00000000 -#define BM_32_50 BM_50_32 -#define BM_51_32 0x000fffff00000000 -#define BM_32_51 BM_51_32 -#define BM_52_32 0x001fffff00000000 -#define BM_32_52 BM_52_32 -#define BM_53_32 0x003fffff00000000 -#define BM_32_53 BM_53_32 -#define BM_54_32 0x007fffff00000000 -#define BM_32_54 BM_54_32 -#define BM_55_32 0x00ffffff00000000 -#define BM_32_55 BM_55_32 -#define BM_56_32 0x01ffffff00000000 -#define BM_32_56 BM_56_32 -#define BM_57_32 0x03ffffff00000000 -#define BM_32_57 BM_57_32 -#define BM_58_32 0x07ffffff00000000 -#define BM_32_58 BM_58_32 -#define BM_59_32 0x0fffffff00000000 -#define BM_32_59 BM_59_32 -#define BM_60_32 0x1fffffff00000000 -#define BM_32_60 BM_60_32 -#define BM_61_32 0x3fffffff00000000 -#define BM_32_61 BM_61_32 -#define BM_62_32 0x7fffffff00000000 -#define BM_32_62 BM_62_32 -#define BM_63_32 0xffffffff00000000 -#define BM_32_63 BM_63_32 -#define BM_33_33 0x0000000200000000 -#define BM_34_33 0x0000000600000000 -#define BM_33_34 BM_34_33 -#define BM_35_33 0x0000000e00000000 -#define BM_33_35 BM_35_33 -#define BM_36_33 0x0000001e00000000 -#define BM_33_36 BM_36_33 -#define BM_37_33 0x0000003e00000000 -#define BM_33_37 BM_37_33 -#define BM_38_33 0x0000007e00000000 -#define BM_33_38 BM_38_33 -#define BM_39_33 0x000000fe00000000 -#define BM_33_39 BM_39_33 -#define BM_40_33 0x000001fe00000000 -#define BM_33_40 BM_40_33 -#define BM_41_33 0x000003fe00000000 -#define BM_33_41 BM_41_33 -#define BM_42_33 0x000007fe00000000 -#define BM_33_42 BM_42_33 -#define BM_43_33 0x00000ffe00000000 -#define BM_33_43 BM_43_33 -#define BM_44_33 0x00001ffe00000000 -#define BM_33_44 BM_44_33 -#define BM_45_33 0x00003ffe00000000 -#define BM_33_45 BM_45_33 -#define BM_46_33 0x00007ffe00000000 -#define BM_33_46 BM_46_33 -#define BM_47_33 0x0000fffe00000000 -#define BM_33_47 BM_47_33 -#define BM_48_33 0x0001fffe00000000 -#define BM_33_48 BM_48_33 -#define BM_49_33 0x0003fffe00000000 -#define BM_33_49 BM_49_33 -#define BM_50_33 0x0007fffe00000000 -#define BM_33_50 BM_50_33 -#define BM_51_33 0x000ffffe00000000 -#define BM_33_51 BM_51_33 -#define BM_52_33 0x001ffffe00000000 -#define BM_33_52 BM_52_33 -#define BM_53_33 0x003ffffe00000000 -#define BM_33_53 BM_53_33 -#define BM_54_33 0x007ffffe00000000 -#define BM_33_54 BM_54_33 -#define BM_55_33 0x00fffffe00000000 -#define BM_33_55 BM_55_33 -#define BM_56_33 0x01fffffe00000000 -#define BM_33_56 BM_56_33 -#define BM_57_33 0x03fffffe00000000 -#define BM_33_57 BM_57_33 -#define BM_58_33 0x07fffffe00000000 -#define BM_33_58 BM_58_33 -#define BM_59_33 0x0ffffffe00000000 -#define BM_33_59 BM_59_33 -#define BM_60_33 0x1ffffffe00000000 -#define BM_33_60 BM_60_33 -#define BM_61_33 0x3ffffffe00000000 -#define BM_33_61 BM_61_33 -#define BM_62_33 0x7ffffffe00000000 -#define BM_33_62 BM_62_33 -#define BM_63_33 0xfffffffe00000000 -#define BM_33_63 BM_63_33 -#define BM_34_34 0x0000000400000000 -#define BM_35_34 0x0000000c00000000 -#define BM_34_35 BM_35_34 -#define BM_36_34 0x0000001c00000000 -#define BM_34_36 BM_36_34 -#define BM_37_34 0x0000003c00000000 -#define BM_34_37 BM_37_34 -#define BM_38_34 0x0000007c00000000 -#define BM_34_38 BM_38_34 -#define BM_39_34 0x000000fc00000000 -#define BM_34_39 BM_39_34 -#define BM_40_34 0x000001fc00000000 -#define BM_34_40 BM_40_34 -#define BM_41_34 0x000003fc00000000 -#define BM_34_41 BM_41_34 -#define BM_42_34 0x000007fc00000000 -#define BM_34_42 BM_42_34 -#define BM_43_34 0x00000ffc00000000 -#define BM_34_43 BM_43_34 -#define BM_44_34 0x00001ffc00000000 -#define BM_34_44 BM_44_34 -#define BM_45_34 0x00003ffc00000000 -#define BM_34_45 BM_45_34 -#define BM_46_34 0x00007ffc00000000 -#define BM_34_46 BM_46_34 -#define BM_47_34 0x0000fffc00000000 -#define BM_34_47 BM_47_34 -#define BM_48_34 0x0001fffc00000000 -#define BM_34_48 BM_48_34 -#define BM_49_34 0x0003fffc00000000 -#define BM_34_49 BM_49_34 -#define BM_50_34 0x0007fffc00000000 -#define BM_34_50 BM_50_34 -#define BM_51_34 0x000ffffc00000000 -#define BM_34_51 BM_51_34 -#define BM_52_34 0x001ffffc00000000 -#define BM_34_52 BM_52_34 -#define BM_53_34 0x003ffffc00000000 -#define BM_34_53 BM_53_34 -#define BM_54_34 0x007ffffc00000000 -#define BM_34_54 BM_54_34 -#define BM_55_34 0x00fffffc00000000 -#define BM_34_55 BM_55_34 -#define BM_56_34 0x01fffffc00000000 -#define BM_34_56 BM_56_34 -#define BM_57_34 0x03fffffc00000000 -#define BM_34_57 BM_57_34 -#define BM_58_34 0x07fffffc00000000 -#define BM_34_58 BM_58_34 -#define BM_59_34 0x0ffffffc00000000 -#define BM_34_59 BM_59_34 -#define BM_60_34 0x1ffffffc00000000 -#define BM_34_60 BM_60_34 -#define BM_61_34 0x3ffffffc00000000 -#define BM_34_61 BM_61_34 -#define BM_62_34 0x7ffffffc00000000 -#define BM_34_62 BM_62_34 -#define BM_63_34 0xfffffffc00000000 -#define BM_34_63 BM_63_34 -#define BM_35_35 0x0000000800000000 -#define BM_36_35 0x0000001800000000 -#define BM_35_36 BM_36_35 -#define BM_37_35 0x0000003800000000 -#define BM_35_37 BM_37_35 -#define BM_38_35 0x0000007800000000 -#define BM_35_38 BM_38_35 -#define BM_39_35 0x000000f800000000 -#define BM_35_39 BM_39_35 -#define BM_40_35 0x000001f800000000 -#define BM_35_40 BM_40_35 -#define BM_41_35 0x000003f800000000 -#define BM_35_41 BM_41_35 -#define BM_42_35 0x000007f800000000 -#define BM_35_42 BM_42_35 -#define BM_43_35 0x00000ff800000000 -#define BM_35_43 BM_43_35 -#define BM_44_35 0x00001ff800000000 -#define BM_35_44 BM_44_35 -#define BM_45_35 0x00003ff800000000 -#define BM_35_45 BM_45_35 -#define BM_46_35 0x00007ff800000000 -#define BM_35_46 BM_46_35 -#define BM_47_35 0x0000fff800000000 -#define BM_35_47 BM_47_35 -#define BM_48_35 0x0001fff800000000 -#define BM_35_48 BM_48_35 -#define BM_49_35 0x0003fff800000000 -#define BM_35_49 BM_49_35 -#define BM_50_35 0x0007fff800000000 -#define BM_35_50 BM_50_35 -#define BM_51_35 0x000ffff800000000 -#define BM_35_51 BM_51_35 -#define BM_52_35 0x001ffff800000000 -#define BM_35_52 BM_52_35 -#define BM_53_35 0x003ffff800000000 -#define BM_35_53 BM_53_35 -#define BM_54_35 0x007ffff800000000 -#define BM_35_54 BM_54_35 -#define BM_55_35 0x00fffff800000000 -#define BM_35_55 BM_55_35 -#define BM_56_35 0x01fffff800000000 -#define BM_35_56 BM_56_35 -#define BM_57_35 0x03fffff800000000 -#define BM_35_57 BM_57_35 -#define BM_58_35 0x07fffff800000000 -#define BM_35_58 BM_58_35 -#define BM_59_35 0x0ffffff800000000 -#define BM_35_59 BM_59_35 -#define BM_60_35 0x1ffffff800000000 -#define BM_35_60 BM_60_35 -#define BM_61_35 0x3ffffff800000000 -#define BM_35_61 BM_61_35 -#define BM_62_35 0x7ffffff800000000 -#define BM_35_62 BM_62_35 -#define BM_63_35 0xfffffff800000000 -#define BM_35_63 BM_63_35 -#define BM_36_36 0x0000001000000000 -#define BM_37_36 0x0000003000000000 -#define BM_36_37 BM_37_36 -#define BM_38_36 0x0000007000000000 -#define BM_36_38 BM_38_36 -#define BM_39_36 0x000000f000000000 -#define BM_36_39 BM_39_36 -#define BM_40_36 0x000001f000000000 -#define BM_36_40 BM_40_36 -#define BM_41_36 0x000003f000000000 -#define BM_36_41 BM_41_36 -#define BM_42_36 0x000007f000000000 -#define BM_36_42 BM_42_36 -#define BM_43_36 0x00000ff000000000 -#define BM_36_43 BM_43_36 -#define BM_44_36 0x00001ff000000000 -#define BM_36_44 BM_44_36 -#define BM_45_36 0x00003ff000000000 -#define BM_36_45 BM_45_36 -#define BM_46_36 0x00007ff000000000 -#define BM_36_46 BM_46_36 -#define BM_47_36 0x0000fff000000000 -#define BM_36_47 BM_47_36 -#define BM_48_36 0x0001fff000000000 -#define BM_36_48 BM_48_36 -#define BM_49_36 0x0003fff000000000 -#define BM_36_49 BM_49_36 -#define BM_50_36 0x0007fff000000000 -#define BM_36_50 BM_50_36 -#define BM_51_36 0x000ffff000000000 -#define BM_36_51 BM_51_36 -#define BM_52_36 0x001ffff000000000 -#define BM_36_52 BM_52_36 -#define BM_53_36 0x003ffff000000000 -#define BM_36_53 BM_53_36 -#define BM_54_36 0x007ffff000000000 -#define BM_36_54 BM_54_36 -#define BM_55_36 0x00fffff000000000 -#define BM_36_55 BM_55_36 -#define BM_56_36 0x01fffff000000000 -#define BM_36_56 BM_56_36 -#define BM_57_36 0x03fffff000000000 -#define BM_36_57 BM_57_36 -#define BM_58_36 0x07fffff000000000 -#define BM_36_58 BM_58_36 -#define BM_59_36 0x0ffffff000000000 -#define BM_36_59 BM_59_36 -#define BM_60_36 0x1ffffff000000000 -#define BM_36_60 BM_60_36 -#define BM_61_36 0x3ffffff000000000 -#define BM_36_61 BM_61_36 -#define BM_62_36 0x7ffffff000000000 -#define BM_36_62 BM_62_36 -#define BM_63_36 0xfffffff000000000 -#define BM_36_63 BM_63_36 -#define BM_37_37 0x0000002000000000 -#define BM_38_37 0x0000006000000000 -#define BM_37_38 BM_38_37 -#define BM_39_37 0x000000e000000000 -#define BM_37_39 BM_39_37 -#define BM_40_37 0x000001e000000000 -#define BM_37_40 BM_40_37 -#define BM_41_37 0x000003e000000000 -#define BM_37_41 BM_41_37 -#define BM_42_37 0x000007e000000000 -#define BM_37_42 BM_42_37 -#define BM_43_37 0x00000fe000000000 -#define BM_37_43 BM_43_37 -#define BM_44_37 0x00001fe000000000 -#define BM_37_44 BM_44_37 -#define BM_45_37 0x00003fe000000000 -#define BM_37_45 BM_45_37 -#define BM_46_37 0x00007fe000000000 -#define BM_37_46 BM_46_37 -#define BM_47_37 0x0000ffe000000000 -#define BM_37_47 BM_47_37 -#define BM_48_37 0x0001ffe000000000 -#define BM_37_48 BM_48_37 -#define BM_49_37 0x0003ffe000000000 -#define BM_37_49 BM_49_37 -#define BM_50_37 0x0007ffe000000000 -#define BM_37_50 BM_50_37 -#define BM_51_37 0x000fffe000000000 -#define BM_37_51 BM_51_37 -#define BM_52_37 0x001fffe000000000 -#define BM_37_52 BM_52_37 -#define BM_53_37 0x003fffe000000000 -#define BM_37_53 BM_53_37 -#define BM_54_37 0x007fffe000000000 -#define BM_37_54 BM_54_37 -#define BM_55_37 0x00ffffe000000000 -#define BM_37_55 BM_55_37 -#define BM_56_37 0x01ffffe000000000 -#define BM_37_56 BM_56_37 -#define BM_57_37 0x03ffffe000000000 -#define BM_37_57 BM_57_37 -#define BM_58_37 0x07ffffe000000000 -#define BM_37_58 BM_58_37 -#define BM_59_37 0x0fffffe000000000 -#define BM_37_59 BM_59_37 -#define BM_60_37 0x1fffffe000000000 -#define BM_37_60 BM_60_37 -#define BM_61_37 0x3fffffe000000000 -#define BM_37_61 BM_61_37 -#define BM_62_37 0x7fffffe000000000 -#define BM_37_62 BM_62_37 -#define BM_63_37 0xffffffe000000000 -#define BM_37_63 BM_63_37 -#define BM_38_38 0x0000004000000000 -#define BM_39_38 0x000000c000000000 -#define BM_38_39 BM_39_38 -#define BM_40_38 0x000001c000000000 -#define BM_38_40 BM_40_38 -#define BM_41_38 0x000003c000000000 -#define BM_38_41 BM_41_38 -#define BM_42_38 0x000007c000000000 -#define BM_38_42 BM_42_38 -#define BM_43_38 0x00000fc000000000 -#define BM_38_43 BM_43_38 -#define BM_44_38 0x00001fc000000000 -#define BM_38_44 BM_44_38 -#define BM_45_38 0x00003fc000000000 -#define BM_38_45 BM_45_38 -#define BM_46_38 0x00007fc000000000 -#define BM_38_46 BM_46_38 -#define BM_47_38 0x0000ffc000000000 -#define BM_38_47 BM_47_38 -#define BM_48_38 0x0001ffc000000000 -#define BM_38_48 BM_48_38 -#define BM_49_38 0x0003ffc000000000 -#define BM_38_49 BM_49_38 -#define BM_50_38 0x0007ffc000000000 -#define BM_38_50 BM_50_38 -#define BM_51_38 0x000fffc000000000 -#define BM_38_51 BM_51_38 -#define BM_52_38 0x001fffc000000000 -#define BM_38_52 BM_52_38 -#define BM_53_38 0x003fffc000000000 -#define BM_38_53 BM_53_38 -#define BM_54_38 0x007fffc000000000 -#define BM_38_54 BM_54_38 -#define BM_55_38 0x00ffffc000000000 -#define BM_38_55 BM_55_38 -#define BM_56_38 0x01ffffc000000000 -#define BM_38_56 BM_56_38 -#define BM_57_38 0x03ffffc000000000 -#define BM_38_57 BM_57_38 -#define BM_58_38 0x07ffffc000000000 -#define BM_38_58 BM_58_38 -#define BM_59_38 0x0fffffc000000000 -#define BM_38_59 BM_59_38 -#define BM_60_38 0x1fffffc000000000 -#define BM_38_60 BM_60_38 -#define BM_61_38 0x3fffffc000000000 -#define BM_38_61 BM_61_38 -#define BM_62_38 0x7fffffc000000000 -#define BM_38_62 BM_62_38 -#define BM_63_38 0xffffffc000000000 -#define BM_38_63 BM_63_38 -#define BM_39_39 0x0000008000000000 -#define BM_40_39 0x0000018000000000 -#define BM_39_40 BM_40_39 -#define BM_41_39 0x0000038000000000 -#define BM_39_41 BM_41_39 -#define BM_42_39 0x0000078000000000 -#define BM_39_42 BM_42_39 -#define BM_43_39 0x00000f8000000000 -#define BM_39_43 BM_43_39 -#define BM_44_39 0x00001f8000000000 -#define BM_39_44 BM_44_39 -#define BM_45_39 0x00003f8000000000 -#define BM_39_45 BM_45_39 -#define BM_46_39 0x00007f8000000000 -#define BM_39_46 BM_46_39 -#define BM_47_39 0x0000ff8000000000 -#define BM_39_47 BM_47_39 -#define BM_48_39 0x0001ff8000000000 -#define BM_39_48 BM_48_39 -#define BM_49_39 0x0003ff8000000000 -#define BM_39_49 BM_49_39 -#define BM_50_39 0x0007ff8000000000 -#define BM_39_50 BM_50_39 -#define BM_51_39 0x000fff8000000000 -#define BM_39_51 BM_51_39 -#define BM_52_39 0x001fff8000000000 -#define BM_39_52 BM_52_39 -#define BM_53_39 0x003fff8000000000 -#define BM_39_53 BM_53_39 -#define BM_54_39 0x007fff8000000000 -#define BM_39_54 BM_54_39 -#define BM_55_39 0x00ffff8000000000 -#define BM_39_55 BM_55_39 -#define BM_56_39 0x01ffff8000000000 -#define BM_39_56 BM_56_39 -#define BM_57_39 0x03ffff8000000000 -#define BM_39_57 BM_57_39 -#define BM_58_39 0x07ffff8000000000 -#define BM_39_58 BM_58_39 -#define BM_59_39 0x0fffff8000000000 -#define BM_39_59 BM_59_39 -#define BM_60_39 0x1fffff8000000000 -#define BM_39_60 BM_60_39 -#define BM_61_39 0x3fffff8000000000 -#define BM_39_61 BM_61_39 -#define BM_62_39 0x7fffff8000000000 -#define BM_39_62 BM_62_39 -#define BM_63_39 0xffffff8000000000 -#define BM_39_63 BM_63_39 -#define BM_40_40 0x0000010000000000 -#define BM_41_40 0x0000030000000000 -#define BM_40_41 BM_41_40 -#define BM_42_40 0x0000070000000000 -#define BM_40_42 BM_42_40 -#define BM_43_40 0x00000f0000000000 -#define BM_40_43 BM_43_40 -#define BM_44_40 0x00001f0000000000 -#define BM_40_44 BM_44_40 -#define BM_45_40 0x00003f0000000000 -#define BM_40_45 BM_45_40 -#define BM_46_40 0x00007f0000000000 -#define BM_40_46 BM_46_40 -#define BM_47_40 0x0000ff0000000000 -#define BM_40_47 BM_47_40 -#define BM_48_40 0x0001ff0000000000 -#define BM_40_48 BM_48_40 -#define BM_49_40 0x0003ff0000000000 -#define BM_40_49 BM_49_40 -#define BM_50_40 0x0007ff0000000000 -#define BM_40_50 BM_50_40 -#define BM_51_40 0x000fff0000000000 -#define BM_40_51 BM_51_40 -#define BM_52_40 0x001fff0000000000 -#define BM_40_52 BM_52_40 -#define BM_53_40 0x003fff0000000000 -#define BM_40_53 BM_53_40 -#define BM_54_40 0x007fff0000000000 -#define BM_40_54 BM_54_40 -#define BM_55_40 0x00ffff0000000000 -#define BM_40_55 BM_55_40 -#define BM_56_40 0x01ffff0000000000 -#define BM_40_56 BM_56_40 -#define BM_57_40 0x03ffff0000000000 -#define BM_40_57 BM_57_40 -#define BM_58_40 0x07ffff0000000000 -#define BM_40_58 BM_58_40 -#define BM_59_40 0x0fffff0000000000 -#define BM_40_59 BM_59_40 -#define BM_60_40 0x1fffff0000000000 -#define BM_40_60 BM_60_40 -#define BM_61_40 0x3fffff0000000000 -#define BM_40_61 BM_61_40 -#define BM_62_40 0x7fffff0000000000 -#define BM_40_62 BM_62_40 -#define BM_63_40 0xffffff0000000000 -#define BM_40_63 BM_63_40 -#define BM_41_41 0x0000020000000000 -#define BM_42_41 0x0000060000000000 -#define BM_41_42 BM_42_41 -#define BM_43_41 0x00000e0000000000 -#define BM_41_43 BM_43_41 -#define BM_44_41 0x00001e0000000000 -#define BM_41_44 BM_44_41 -#define BM_45_41 0x00003e0000000000 -#define BM_41_45 BM_45_41 -#define BM_46_41 0x00007e0000000000 -#define BM_41_46 BM_46_41 -#define BM_47_41 0x0000fe0000000000 -#define BM_41_47 BM_47_41 -#define BM_48_41 0x0001fe0000000000 -#define BM_41_48 BM_48_41 -#define BM_49_41 0x0003fe0000000000 -#define BM_41_49 BM_49_41 -#define BM_50_41 0x0007fe0000000000 -#define BM_41_50 BM_50_41 -#define BM_51_41 0x000ffe0000000000 -#define BM_41_51 BM_51_41 -#define BM_52_41 0x001ffe0000000000 -#define BM_41_52 BM_52_41 -#define BM_53_41 0x003ffe0000000000 -#define BM_41_53 BM_53_41 -#define BM_54_41 0x007ffe0000000000 -#define BM_41_54 BM_54_41 -#define BM_55_41 0x00fffe0000000000 -#define BM_41_55 BM_55_41 -#define BM_56_41 0x01fffe0000000000 -#define BM_41_56 BM_56_41 -#define BM_57_41 0x03fffe0000000000 -#define BM_41_57 BM_57_41 -#define BM_58_41 0x07fffe0000000000 -#define BM_41_58 BM_58_41 -#define BM_59_41 0x0ffffe0000000000 -#define BM_41_59 BM_59_41 -#define BM_60_41 0x1ffffe0000000000 -#define BM_41_60 BM_60_41 -#define BM_61_41 0x3ffffe0000000000 -#define BM_41_61 BM_61_41 -#define BM_62_41 0x7ffffe0000000000 -#define BM_41_62 BM_62_41 -#define BM_63_41 0xfffffe0000000000 -#define BM_41_63 BM_63_41 -#define BM_42_42 0x0000040000000000 -#define BM_43_42 0x00000c0000000000 -#define BM_42_43 BM_43_42 -#define BM_44_42 0x00001c0000000000 -#define BM_42_44 BM_44_42 -#define BM_45_42 0x00003c0000000000 -#define BM_42_45 BM_45_42 -#define BM_46_42 0x00007c0000000000 -#define BM_42_46 BM_46_42 -#define BM_47_42 0x0000fc0000000000 -#define BM_42_47 BM_47_42 -#define BM_48_42 0x0001fc0000000000 -#define BM_42_48 BM_48_42 -#define BM_49_42 0x0003fc0000000000 -#define BM_42_49 BM_49_42 -#define BM_50_42 0x0007fc0000000000 -#define BM_42_50 BM_50_42 -#define BM_51_42 0x000ffc0000000000 -#define BM_42_51 BM_51_42 -#define BM_52_42 0x001ffc0000000000 -#define BM_42_52 BM_52_42 -#define BM_53_42 0x003ffc0000000000 -#define BM_42_53 BM_53_42 -#define BM_54_42 0x007ffc0000000000 -#define BM_42_54 BM_54_42 -#define BM_55_42 0x00fffc0000000000 -#define BM_42_55 BM_55_42 -#define BM_56_42 0x01fffc0000000000 -#define BM_42_56 BM_56_42 -#define BM_57_42 0x03fffc0000000000 -#define BM_42_57 BM_57_42 -#define BM_58_42 0x07fffc0000000000 -#define BM_42_58 BM_58_42 -#define BM_59_42 0x0ffffc0000000000 -#define BM_42_59 BM_59_42 -#define BM_60_42 0x1ffffc0000000000 -#define BM_42_60 BM_60_42 -#define BM_61_42 0x3ffffc0000000000 -#define BM_42_61 BM_61_42 -#define BM_62_42 0x7ffffc0000000000 -#define BM_42_62 BM_62_42 -#define BM_63_42 0xfffffc0000000000 -#define BM_42_63 BM_63_42 -#define BM_43_43 0x0000080000000000 -#define BM_44_43 0x0000180000000000 -#define BM_43_44 BM_44_43 -#define BM_45_43 0x0000380000000000 -#define BM_43_45 BM_45_43 -#define BM_46_43 0x0000780000000000 -#define BM_43_46 BM_46_43 -#define BM_47_43 0x0000f80000000000 -#define BM_43_47 BM_47_43 -#define BM_48_43 0x0001f80000000000 -#define BM_43_48 BM_48_43 -#define BM_49_43 0x0003f80000000000 -#define BM_43_49 BM_49_43 -#define BM_50_43 0x0007f80000000000 -#define BM_43_50 BM_50_43 -#define BM_51_43 0x000ff80000000000 -#define BM_43_51 BM_51_43 -#define BM_52_43 0x001ff80000000000 -#define BM_43_52 BM_52_43 -#define BM_53_43 0x003ff80000000000 -#define BM_43_53 BM_53_43 -#define BM_54_43 0x007ff80000000000 -#define BM_43_54 BM_54_43 -#define BM_55_43 0x00fff80000000000 -#define BM_43_55 BM_55_43 -#define BM_56_43 0x01fff80000000000 -#define BM_43_56 BM_56_43 -#define BM_57_43 0x03fff80000000000 -#define BM_43_57 BM_57_43 -#define BM_58_43 0x07fff80000000000 -#define BM_43_58 BM_58_43 -#define BM_59_43 0x0ffff80000000000 -#define BM_43_59 BM_59_43 -#define BM_60_43 0x1ffff80000000000 -#define BM_43_60 BM_60_43 -#define BM_61_43 0x3ffff80000000000 -#define BM_43_61 BM_61_43 -#define BM_62_43 0x7ffff80000000000 -#define BM_43_62 BM_62_43 -#define BM_63_43 0xfffff80000000000 -#define BM_43_63 BM_63_43 -#define BM_44_44 0x0000100000000000 -#define BM_45_44 0x0000300000000000 -#define BM_44_45 BM_45_44 -#define BM_46_44 0x0000700000000000 -#define BM_44_46 BM_46_44 -#define BM_47_44 0x0000f00000000000 -#define BM_44_47 BM_47_44 -#define BM_48_44 0x0001f00000000000 -#define BM_44_48 BM_48_44 -#define BM_49_44 0x0003f00000000000 -#define BM_44_49 BM_49_44 -#define BM_50_44 0x0007f00000000000 -#define BM_44_50 BM_50_44 -#define BM_51_44 0x000ff00000000000 -#define BM_44_51 BM_51_44 -#define BM_52_44 0x001ff00000000000 -#define BM_44_52 BM_52_44 -#define BM_53_44 0x003ff00000000000 -#define BM_44_53 BM_53_44 -#define BM_54_44 0x007ff00000000000 -#define BM_44_54 BM_54_44 -#define BM_55_44 0x00fff00000000000 -#define BM_44_55 BM_55_44 -#define BM_56_44 0x01fff00000000000 -#define BM_44_56 BM_56_44 -#define BM_57_44 0x03fff00000000000 -#define BM_44_57 BM_57_44 -#define BM_58_44 0x07fff00000000000 -#define BM_44_58 BM_58_44 -#define BM_59_44 0x0ffff00000000000 -#define BM_44_59 BM_59_44 -#define BM_60_44 0x1ffff00000000000 -#define BM_44_60 BM_60_44 -#define BM_61_44 0x3ffff00000000000 -#define BM_44_61 BM_61_44 -#define BM_62_44 0x7ffff00000000000 -#define BM_44_62 BM_62_44 -#define BM_63_44 0xfffff00000000000 -#define BM_44_63 BM_63_44 -#define BM_45_45 0x0000200000000000 -#define BM_46_45 0x0000600000000000 -#define BM_45_46 BM_46_45 -#define BM_47_45 0x0000e00000000000 -#define BM_45_47 BM_47_45 -#define BM_48_45 0x0001e00000000000 -#define BM_45_48 BM_48_45 -#define BM_49_45 0x0003e00000000000 -#define BM_45_49 BM_49_45 -#define BM_50_45 0x0007e00000000000 -#define BM_45_50 BM_50_45 -#define BM_51_45 0x000fe00000000000 -#define BM_45_51 BM_51_45 -#define BM_52_45 0x001fe00000000000 -#define BM_45_52 BM_52_45 -#define BM_53_45 0x003fe00000000000 -#define BM_45_53 BM_53_45 -#define BM_54_45 0x007fe00000000000 -#define BM_45_54 BM_54_45 -#define BM_55_45 0x00ffe00000000000 -#define BM_45_55 BM_55_45 -#define BM_56_45 0x01ffe00000000000 -#define BM_45_56 BM_56_45 -#define BM_57_45 0x03ffe00000000000 -#define BM_45_57 BM_57_45 -#define BM_58_45 0x07ffe00000000000 -#define BM_45_58 BM_58_45 -#define BM_59_45 0x0fffe00000000000 -#define BM_45_59 BM_59_45 -#define BM_60_45 0x1fffe00000000000 -#define BM_45_60 BM_60_45 -#define BM_61_45 0x3fffe00000000000 -#define BM_45_61 BM_61_45 -#define BM_62_45 0x7fffe00000000000 -#define BM_45_62 BM_62_45 -#define BM_63_45 0xffffe00000000000 -#define BM_45_63 BM_63_45 -#define BM_46_46 0x0000400000000000 -#define BM_47_46 0x0000c00000000000 -#define BM_46_47 BM_47_46 -#define BM_48_46 0x0001c00000000000 -#define BM_46_48 BM_48_46 -#define BM_49_46 0x0003c00000000000 -#define BM_46_49 BM_49_46 -#define BM_50_46 0x0007c00000000000 -#define BM_46_50 BM_50_46 -#define BM_51_46 0x000fc00000000000 -#define BM_46_51 BM_51_46 -#define BM_52_46 0x001fc00000000000 -#define BM_46_52 BM_52_46 -#define BM_53_46 0x003fc00000000000 -#define BM_46_53 BM_53_46 -#define BM_54_46 0x007fc00000000000 -#define BM_46_54 BM_54_46 -#define BM_55_46 0x00ffc00000000000 -#define BM_46_55 BM_55_46 -#define BM_56_46 0x01ffc00000000000 -#define BM_46_56 BM_56_46 -#define BM_57_46 0x03ffc00000000000 -#define BM_46_57 BM_57_46 -#define BM_58_46 0x07ffc00000000000 -#define BM_46_58 BM_58_46 -#define BM_59_46 0x0fffc00000000000 -#define BM_46_59 BM_59_46 -#define BM_60_46 0x1fffc00000000000 -#define BM_46_60 BM_60_46 -#define BM_61_46 0x3fffc00000000000 -#define BM_46_61 BM_61_46 -#define BM_62_46 0x7fffc00000000000 -#define BM_46_62 BM_62_46 -#define BM_63_46 0xffffc00000000000 -#define BM_46_63 BM_63_46 -#define BM_47_47 0x0000800000000000 -#define BM_48_47 0x0001800000000000 -#define BM_47_48 BM_48_47 -#define BM_49_47 0x0003800000000000 -#define BM_47_49 BM_49_47 -#define BM_50_47 0x0007800000000000 -#define BM_47_50 BM_50_47 -#define BM_51_47 0x000f800000000000 -#define BM_47_51 BM_51_47 -#define BM_52_47 0x001f800000000000 -#define BM_47_52 BM_52_47 -#define BM_53_47 0x003f800000000000 -#define BM_47_53 BM_53_47 -#define BM_54_47 0x007f800000000000 -#define BM_47_54 BM_54_47 -#define BM_55_47 0x00ff800000000000 -#define BM_47_55 BM_55_47 -#define BM_56_47 0x01ff800000000000 -#define BM_47_56 BM_56_47 -#define BM_57_47 0x03ff800000000000 -#define BM_47_57 BM_57_47 -#define BM_58_47 0x07ff800000000000 -#define BM_47_58 BM_58_47 -#define BM_59_47 0x0fff800000000000 -#define BM_47_59 BM_59_47 -#define BM_60_47 0x1fff800000000000 -#define BM_47_60 BM_60_47 -#define BM_61_47 0x3fff800000000000 -#define BM_47_61 BM_61_47 -#define BM_62_47 0x7fff800000000000 -#define BM_47_62 BM_62_47 -#define BM_63_47 0xffff800000000000 -#define BM_47_63 BM_63_47 -#define BM_48_48 0x0001000000000000 -#define BM_49_48 0x0003000000000000 -#define BM_48_49 BM_49_48 -#define BM_50_48 0x0007000000000000 -#define BM_48_50 BM_50_48 -#define BM_51_48 0x000f000000000000 -#define BM_48_51 BM_51_48 -#define BM_52_48 0x001f000000000000 -#define BM_48_52 BM_52_48 -#define BM_53_48 0x003f000000000000 -#define BM_48_53 BM_53_48 -#define BM_54_48 0x007f000000000000 -#define BM_48_54 BM_54_48 -#define BM_55_48 0x00ff000000000000 -#define BM_48_55 BM_55_48 -#define BM_56_48 0x01ff000000000000 -#define BM_48_56 BM_56_48 -#define BM_57_48 0x03ff000000000000 -#define BM_48_57 BM_57_48 -#define BM_58_48 0x07ff000000000000 -#define BM_48_58 BM_58_48 -#define BM_59_48 0x0fff000000000000 -#define BM_48_59 BM_59_48 -#define BM_60_48 0x1fff000000000000 -#define BM_48_60 BM_60_48 -#define BM_61_48 0x3fff000000000000 -#define BM_48_61 BM_61_48 -#define BM_62_48 0x7fff000000000000 -#define BM_48_62 BM_62_48 -#define BM_63_48 0xffff000000000000 -#define BM_48_63 BM_63_48 -#define BM_49_49 0x0002000000000000 -#define BM_50_49 0x0006000000000000 -#define BM_49_50 BM_50_49 -#define BM_51_49 0x000e000000000000 -#define BM_49_51 BM_51_49 -#define BM_52_49 0x001e000000000000 -#define BM_49_52 BM_52_49 -#define BM_53_49 0x003e000000000000 -#define BM_49_53 BM_53_49 -#define BM_54_49 0x007e000000000000 -#define BM_49_54 BM_54_49 -#define BM_55_49 0x00fe000000000000 -#define BM_49_55 BM_55_49 -#define BM_56_49 0x01fe000000000000 -#define BM_49_56 BM_56_49 -#define BM_57_49 0x03fe000000000000 -#define BM_49_57 BM_57_49 -#define BM_58_49 0x07fe000000000000 -#define BM_49_58 BM_58_49 -#define BM_59_49 0x0ffe000000000000 -#define BM_49_59 BM_59_49 -#define BM_60_49 0x1ffe000000000000 -#define BM_49_60 BM_60_49 -#define BM_61_49 0x3ffe000000000000 -#define BM_49_61 BM_61_49 -#define BM_62_49 0x7ffe000000000000 -#define BM_49_62 BM_62_49 -#define BM_63_49 0xfffe000000000000 -#define BM_49_63 BM_63_49 -#define BM_50_50 0x0004000000000000 -#define BM_51_50 0x000c000000000000 -#define BM_50_51 BM_51_50 -#define BM_52_50 0x001c000000000000 -#define BM_50_52 BM_52_50 -#define BM_53_50 0x003c000000000000 -#define BM_50_53 BM_53_50 -#define BM_54_50 0x007c000000000000 -#define BM_50_54 BM_54_50 -#define BM_55_50 0x00fc000000000000 -#define BM_50_55 BM_55_50 -#define BM_56_50 0x01fc000000000000 -#define BM_50_56 BM_56_50 -#define BM_57_50 0x03fc000000000000 -#define BM_50_57 BM_57_50 -#define BM_58_50 0x07fc000000000000 -#define BM_50_58 BM_58_50 -#define BM_59_50 0x0ffc000000000000 -#define BM_50_59 BM_59_50 -#define BM_60_50 0x1ffc000000000000 -#define BM_50_60 BM_60_50 -#define BM_61_50 0x3ffc000000000000 -#define BM_50_61 BM_61_50 -#define BM_62_50 0x7ffc000000000000 -#define BM_50_62 BM_62_50 -#define BM_63_50 0xfffc000000000000 -#define BM_50_63 BM_63_50 -#define BM_51_51 0x0008000000000000 -#define BM_52_51 0x0018000000000000 -#define BM_51_52 BM_52_51 -#define BM_53_51 0x0038000000000000 -#define BM_51_53 BM_53_51 -#define BM_54_51 0x0078000000000000 -#define BM_51_54 BM_54_51 -#define BM_55_51 0x00f8000000000000 -#define BM_51_55 BM_55_51 -#define BM_56_51 0x01f8000000000000 -#define BM_51_56 BM_56_51 -#define BM_57_51 0x03f8000000000000 -#define BM_51_57 BM_57_51 -#define BM_58_51 0x07f8000000000000 -#define BM_51_58 BM_58_51 -#define BM_59_51 0x0ff8000000000000 -#define BM_51_59 BM_59_51 -#define BM_60_51 0x1ff8000000000000 -#define BM_51_60 BM_60_51 -#define BM_61_51 0x3ff8000000000000 -#define BM_51_61 BM_61_51 -#define BM_62_51 0x7ff8000000000000 -#define BM_51_62 BM_62_51 -#define BM_63_51 0xfff8000000000000 -#define BM_51_63 BM_63_51 -#define BM_52_52 0x0010000000000000 -#define BM_53_52 0x0030000000000000 -#define BM_52_53 BM_53_52 -#define BM_54_52 0x0070000000000000 -#define BM_52_54 BM_54_52 -#define BM_55_52 0x00f0000000000000 -#define BM_52_55 BM_55_52 -#define BM_56_52 0x01f0000000000000 -#define BM_52_56 BM_56_52 -#define BM_57_52 0x03f0000000000000 -#define BM_52_57 BM_57_52 -#define BM_58_52 0x07f0000000000000 -#define BM_52_58 BM_58_52 -#define BM_59_52 0x0ff0000000000000 -#define BM_52_59 BM_59_52 -#define BM_60_52 0x1ff0000000000000 -#define BM_52_60 BM_60_52 -#define BM_61_52 0x3ff0000000000000 -#define BM_52_61 BM_61_52 -#define BM_62_52 0x7ff0000000000000 -#define BM_52_62 BM_62_52 -#define BM_63_52 0xfff0000000000000 -#define BM_52_63 BM_63_52 -#define BM_53_53 0x0020000000000000 -#define BM_54_53 0x0060000000000000 -#define BM_53_54 BM_54_53 -#define BM_55_53 0x00e0000000000000 -#define BM_53_55 BM_55_53 -#define BM_56_53 0x01e0000000000000 -#define BM_53_56 BM_56_53 -#define BM_57_53 0x03e0000000000000 -#define BM_53_57 BM_57_53 -#define BM_58_53 0x07e0000000000000 -#define BM_53_58 BM_58_53 -#define BM_59_53 0x0fe0000000000000 -#define BM_53_59 BM_59_53 -#define BM_60_53 0x1fe0000000000000 -#define BM_53_60 BM_60_53 -#define BM_61_53 0x3fe0000000000000 -#define BM_53_61 BM_61_53 -#define BM_62_53 0x7fe0000000000000 -#define BM_53_62 BM_62_53 -#define BM_63_53 0xffe0000000000000 -#define BM_53_63 BM_63_53 -#define BM_54_54 0x0040000000000000 -#define BM_55_54 0x00c0000000000000 -#define BM_54_55 BM_55_54 -#define BM_56_54 0x01c0000000000000 -#define BM_54_56 BM_56_54 -#define BM_57_54 0x03c0000000000000 -#define BM_54_57 BM_57_54 -#define BM_58_54 0x07c0000000000000 -#define BM_54_58 BM_58_54 -#define BM_59_54 0x0fc0000000000000 -#define BM_54_59 BM_59_54 -#define BM_60_54 0x1fc0000000000000 -#define BM_54_60 BM_60_54 -#define BM_61_54 0x3fc0000000000000 -#define BM_54_61 BM_61_54 -#define BM_62_54 0x7fc0000000000000 -#define BM_54_62 BM_62_54 -#define BM_63_54 0xffc0000000000000 -#define BM_54_63 BM_63_54 -#define BM_55_55 0x0080000000000000 -#define BM_56_55 0x0180000000000000 -#define BM_55_56 BM_56_55 -#define BM_57_55 0x0380000000000000 -#define BM_55_57 BM_57_55 -#define BM_58_55 0x0780000000000000 -#define BM_55_58 BM_58_55 -#define BM_59_55 0x0f80000000000000 -#define BM_55_59 BM_59_55 -#define BM_60_55 0x1f80000000000000 -#define BM_55_60 BM_60_55 -#define BM_61_55 0x3f80000000000000 -#define BM_55_61 BM_61_55 -#define BM_62_55 0x7f80000000000000 -#define BM_55_62 BM_62_55 -#define BM_63_55 0xff80000000000000 -#define BM_55_63 BM_63_55 -#define BM_56_56 0x0100000000000000 -#define BM_57_56 0x0300000000000000 -#define BM_56_57 BM_57_56 -#define BM_58_56 0x0700000000000000 -#define BM_56_58 BM_58_56 -#define BM_59_56 0x0f00000000000000 -#define BM_56_59 BM_59_56 -#define BM_60_56 0x1f00000000000000 -#define BM_56_60 BM_60_56 -#define BM_61_56 0x3f00000000000000 -#define BM_56_61 BM_61_56 -#define BM_62_56 0x7f00000000000000 -#define BM_56_62 BM_62_56 -#define BM_63_56 0xff00000000000000 -#define BM_56_63 BM_63_56 -#define BM_57_57 0x0200000000000000 -#define BM_58_57 0x0600000000000000 -#define BM_57_58 BM_58_57 -#define BM_59_57 0x0e00000000000000 -#define BM_57_59 BM_59_57 -#define BM_60_57 0x1e00000000000000 -#define BM_57_60 BM_60_57 -#define BM_61_57 0x3e00000000000000 -#define BM_57_61 BM_61_57 -#define BM_62_57 0x7e00000000000000 -#define BM_57_62 BM_62_57 -#define BM_63_57 0xfe00000000000000 -#define BM_57_63 BM_63_57 -#define BM_58_58 0x0400000000000000 -#define BM_59_58 0x0c00000000000000 -#define BM_58_59 BM_59_58 -#define BM_60_58 0x1c00000000000000 -#define BM_58_60 BM_60_58 -#define BM_61_58 0x3c00000000000000 -#define BM_58_61 BM_61_58 -#define BM_62_58 0x7c00000000000000 -#define BM_58_62 BM_62_58 -#define BM_63_58 0xfc00000000000000 -#define BM_58_63 BM_63_58 -#define BM_59_59 0x0800000000000000 -#define BM_60_59 0x1800000000000000 -#define BM_59_60 BM_60_59 -#define BM_61_59 0x3800000000000000 -#define BM_59_61 BM_61_59 -#define BM_62_59 0x7800000000000000 -#define BM_59_62 BM_62_59 -#define BM_63_59 0xf800000000000000 -#define BM_59_63 BM_63_59 -#define BM_60_60 0x1000000000000000 -#define BM_61_60 0x3000000000000000 -#define BM_60_61 BM_61_60 -#define BM_62_60 0x7000000000000000 -#define BM_60_62 BM_62_60 -#define BM_63_60 0xf000000000000000 -#define BM_60_63 BM_63_60 -#define BM_61_61 0x2000000000000000 -#define BM_62_61 0x6000000000000000 -#define BM_61_62 BM_62_61 -#define BM_63_61 0xe000000000000000 -#define BM_61_63 BM_63_61 -#define BM_62_62 0x4000000000000000 -#define BM_63_62 0xc000000000000000 -#define BM_62_63 BM_63_62 -#define BM_63_63 0x8000000000000000 - -#endif - -#endif /* __ASM_TX4927_TX4927_MIPS_H */ diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h index b14acb575be2..b180488dcdc4 100644 --- a/include/asm-mips/tx4938/rbtx4938.h +++ b/include/asm-mips/tx4938/rbtx4938.h @@ -153,7 +153,7 @@ #define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR) #define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n)) #define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n)) -#define RBTX4938_IRQ_IRC_DMA(ch,n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch,n)) +#define RBTX4938_IRQ_IRC_DMA(ch, n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n)) #define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO) #define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC) #define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC) diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h index afdb19813ca1..650b010761f9 100644 --- a/include/asm-mips/tx4938/tx4938.h +++ b/include/asm-mips/tx4938/tx4938.h @@ -16,7 +16,7 @@ #include <asm/tx4938/tx4938_mips.h> #define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) -#define tx4938_write_nfmc(b,addr) (*(volatile unsigned int *)(addr)) = (b) +#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b) #define TX4938_NR_IRQ_LOCAL TX4938_IRQ_PIC_BEG @@ -84,27 +84,27 @@ #include <asm/byteorder.h> #ifdef __BIG_ENDIAN -#define endian_def_l2(e1,e2) \ - volatile unsigned long e1,e2 -#define endian_def_s2(e1,e2) \ - volatile unsigned short e1,e2 -#define endian_def_sb2(e1,e2,e3) \ - volatile unsigned short e1;volatile unsigned char e2,e3 -#define endian_def_b2s(e1,e2,e3) \ - volatile unsigned char e1,e2;volatile unsigned short e3 -#define endian_def_b4(e1,e2,e3,e4) \ - volatile unsigned char e1,e2,e3,e4 +#define endian_def_l2(e1, e2) \ + volatile unsigned long e1, e2 +#define endian_def_s2(e1, e2) \ + volatile unsigned short e1, e2 +#define endian_def_sb2(e1, e2, e3) \ + volatile unsigned short e1;volatile unsigned char e2, e3 +#define endian_def_b2s(e1, e2, e3) \ + volatile unsigned char e1, e2;volatile unsigned short e3 +#define endian_def_b4(e1, e2, e3, e4) \ + volatile unsigned char e1, e2, e3, e4 #else -#define endian_def_l2(e1,e2) \ - volatile unsigned long e2,e1 -#define endian_def_s2(e1,e2) \ - volatile unsigned short e2,e1 -#define endian_def_sb2(e1,e2,e3) \ - volatile unsigned char e3,e2;volatile unsigned short e1 -#define endian_def_b2s(e1,e2,e3) \ - volatile unsigned short e3;volatile unsigned char e2,e1 -#define endian_def_b4(e1,e2,e3,e4) \ - volatile unsigned char e4,e3,e2,e1 +#define endian_def_l2(e1, e2) \ + volatile unsigned long e2, e1 +#define endian_def_s2(e1, e2) \ + volatile unsigned short e2, e1 +#define endian_def_sb2(e1, e2, e3) \ + volatile unsigned char e3, e2;volatile unsigned short e1 +#define endian_def_b2s(e1, e2, e3) \ + volatile unsigned short e3;volatile unsigned char e2, e1 +#define endian_def_b4(e1, e2, e3, e4) \ + volatile unsigned char e4, e3, e2, e1 #endif @@ -354,7 +354,7 @@ struct tx4938_ccfg_reg { #define TX4938_NUM_IR_SIO 2 #define TX4938_IR_SIO(n) (8 + (n)) #define TX4938_NUM_IR_DMA 4 -#define TX4938_IR_DMA(ch,n) ((ch ? 27 : 10) + (n)) /* 10-13,27-30 */ +#define TX4938_IR_DMA(ch, n) ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */ #define TX4938_IR_PIO 14 #define TX4938_IR_PDMAC 15 #define TX4938_IR_PCIC 16 diff --git a/include/asm-mips/tx4938/tx4938_mips.h b/include/asm-mips/tx4938/tx4938_mips.h index 5f8498fef005..f346ff58b947 100644 --- a/include/asm-mips/tx4938/tx4938_mips.h +++ b/include/asm-mips/tx4938/tx4938_mips.h @@ -19,10 +19,10 @@ #define reg_rd32(r) ((u32)(*((vu32*)(r)))) #define reg_rd64(r) ((u64)(*((vu64*)(r)))) -#define reg_wr08(r,v) ((*((vu8 *)(r)))=((u8 )(v))) -#define reg_wr16(r,v) ((*((vu16*)(r)))=((u16)(v))) -#define reg_wr32(r,v) ((*((vu32*)(r)))=((u32)(v))) -#define reg_wr64(r,v) ((*((vu64*)(r)))=((u64)(v))) +#define reg_wr08(r, v) ((*((vu8 *)(r)))=((u8 )(v))) +#define reg_wr16(r, v) ((*((vu16*)(r)))=((u16)(v))) +#define reg_wr32(r, v) ((*((vu32*)(r)))=((u32)(v))) +#define reg_wr64(r, v) ((*((vu64*)(r)))=((u64)(v))) typedef volatile __signed char vs8; typedef volatile unsigned char vu8; diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h index b25511787ee0..c30c718994c9 100644 --- a/include/asm-mips/uaccess.h +++ b/include/asm-mips/uaccess.h @@ -63,7 +63,7 @@ #define get_fs() (current_thread_info()->addr_limit) #define set_fs(x) (current_thread_info()->addr_limit = (x)) -#define segment_eq(a,b) ((a).seg == (b).seg) +#define segment_eq(a, b) ((a).seg == (b).seg) /* @@ -108,7 +108,7 @@ (((signed long)((mask) & ((addr) | ((addr) + (size)) | __ua_size(size)))) == 0) #define access_ok(type, addr, size) \ - likely(__access_ok((unsigned long)(addr), (size),__access_mask)) + likely(__access_ok((unsigned long)(addr), (size), __access_mask)) /* * put_user: - Write a simple value into user space. @@ -127,7 +127,7 @@ * Returns zero on success, or -EFAULT on error. */ #define put_user(x,ptr) \ - __put_user_check((x),(ptr),sizeof(*(ptr))) + __put_user_check((x), (ptr), sizeof(*(ptr))) /* * get_user: - Get a simple variable from user space. @@ -147,7 +147,7 @@ * On error, the variable @x is set to zero. */ #define get_user(x,ptr) \ - __get_user_check((x),(ptr),sizeof(*(ptr))) + __get_user_check((x), (ptr), sizeof(*(ptr))) /* * __put_user: - Write a simple value into user space, with less checking. @@ -169,7 +169,7 @@ * Returns zero on success, or -EFAULT on error. */ #define __put_user(x,ptr) \ - __put_user_nocheck((x),(ptr),sizeof(*(ptr))) + __put_user_nocheck((x), (ptr), sizeof(*(ptr))) /* * __get_user: - Get a simple variable from user space, with less checking. @@ -192,7 +192,7 @@ * On error, the variable @x is set to zero. */ #define __get_user(x,ptr) \ - __get_user_nocheck((x),(ptr),sizeof(*(ptr))) + __get_user_nocheck((x), (ptr), sizeof(*(ptr))) struct __large_struct { unsigned long buf[100]; }; #define __m(x) (*(struct __large_struct __user *)(x)) @@ -221,7 +221,7 @@ do { \ } \ } while (0) -#define __get_user_nocheck(x,ptr,size) \ +#define __get_user_nocheck(x, ptr, size) \ ({ \ long __gu_err; \ \ @@ -229,7 +229,7 @@ do { \ __gu_err; \ }) -#define __get_user_check(x,ptr,size) \ +#define __get_user_check(x, ptr, size) \ ({ \ long __gu_err = -EFAULT; \ const __typeof__(*(ptr)) __user * __gu_ptr = (ptr); \ @@ -300,7 +300,7 @@ do { \ #define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr) #endif -#define __put_user_nocheck(x,ptr,size) \ +#define __put_user_nocheck(x, ptr, size) \ ({ \ __typeof__(*(ptr)) __pu_val; \ long __pu_err = 0; \ @@ -316,7 +316,7 @@ do { \ __pu_err; \ }) -#define __put_user_check(x,ptr,size) \ +#define __put_user_check(x, ptr, size) \ ({ \ __typeof__(*(ptr)) __user *__pu_addr = (ptr); \ __typeof__(*(ptr)) __pu_val = (x); \ @@ -389,11 +389,11 @@ extern void __put_user_unknown(void); extern size_t __copy_user(void *__to, const void *__from, size_t __n); -#define __invoke_copy_to_user(to,from,n) \ +#define __invoke_copy_to_user(to, from, n) \ ({ \ - register void __user *__cu_to_r __asm__ ("$4"); \ - register const void *__cu_from_r __asm__ ("$5"); \ - register long __cu_len_r __asm__ ("$6"); \ + register void __user *__cu_to_r __asm__("$4"); \ + register const void *__cu_from_r __asm__("$5"); \ + register long __cu_len_r __asm__("$6"); \ \ __cu_to_r = (to); \ __cu_from_r = (from); \ @@ -421,7 +421,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); * Returns number of bytes that could not be copied. * On success, this will be zero. */ -#define __copy_to_user(to,from,n) \ +#define __copy_to_user(to, from, n) \ ({ \ void __user *__cu_to; \ const void *__cu_from; \ @@ -437,7 +437,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); -#define __copy_to_user_inatomic(to,from,n) \ +#define __copy_to_user_inatomic(to, from, n) \ ({ \ void __user *__cu_to; \ const void *__cu_from; \ @@ -450,7 +450,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); __cu_len; \ }) -#define __copy_from_user_inatomic(to,from,n) \ +#define __copy_from_user_inatomic(to, from, n) \ ({ \ void *__cu_to; \ const void __user *__cu_from; \ @@ -477,7 +477,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); * Returns number of bytes that could not be copied. * On success, this will be zero. */ -#define copy_to_user(to,from,n) \ +#define copy_to_user(to, from, n) \ ({ \ void __user *__cu_to; \ const void *__cu_from; \ @@ -493,11 +493,11 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); __cu_len; \ }) -#define __invoke_copy_from_user(to,from,n) \ +#define __invoke_copy_from_user(to, from, n) \ ({ \ - register void *__cu_to_r __asm__ ("$4"); \ - register const void __user *__cu_from_r __asm__ ("$5"); \ - register long __cu_len_r __asm__ ("$6"); \ + register void *__cu_to_r __asm__("$4"); \ + register const void __user *__cu_from_r __asm__("$5"); \ + register long __cu_len_r __asm__("$6"); \ \ __cu_to_r = (to); \ __cu_from_r = (from); \ @@ -516,11 +516,11 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); __cu_len_r; \ }) -#define __invoke_copy_from_user_inatomic(to,from,n) \ +#define __invoke_copy_from_user_inatomic(to, from, n) \ ({ \ - register void *__cu_to_r __asm__ ("$4"); \ - register const void __user *__cu_from_r __asm__ ("$5"); \ - register long __cu_len_r __asm__ ("$6"); \ + register void *__cu_to_r __asm__("$4"); \ + register const void __user *__cu_from_r __asm__("$5"); \ + register long __cu_len_r __asm__("$6"); \ \ __cu_to_r = (to); \ __cu_from_r = (from); \ @@ -556,7 +556,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); * If some data could not be copied, this function will pad the copied * data to the requested size using zero bytes. */ -#define __copy_from_user(to,from,n) \ +#define __copy_from_user(to, from, n) \ ({ \ void *__cu_to; \ const void __user *__cu_from; \ @@ -587,7 +587,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); * If some data could not be copied, this function will pad the copied * data to the requested size using zero bytes. */ -#define copy_from_user(to,from,n) \ +#define copy_from_user(to, from, n) \ ({ \ void *__cu_to; \ const void __user *__cu_from; \ @@ -605,7 +605,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); #define __copy_in_user(to, from, n) __copy_from_user(to, from, n) -#define copy_in_user(to,from,n) \ +#define copy_in_user(to, from, n) \ ({ \ void __user *__cu_to; \ const void __user *__cu_from; \ diff --git a/include/asm-mips/unaligned.h b/include/asm-mips/unaligned.h index a0042563838a..3249049e93aa 100644 --- a/include/asm-mips/unaligned.h +++ b/include/asm-mips/unaligned.h @@ -3,12 +3,27 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1996, 1999, 2000, 2001, 2003 by Ralf Baechle - * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. + * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) */ -#ifndef _ASM_UNALIGNED_H -#define _ASM_UNALIGNED_H +#ifndef __ASM_GENERIC_UNALIGNED_H +#define __ASM_GENERIC_UNALIGNED_H -#include <asm-generic/unaligned.h> +#include <linux/compiler.h> -#endif /* _ASM_UNALIGNED_H */ +#define get_unaligned(ptr) \ +({ \ + struct __packed { \ + typeof(*(ptr)) __v; \ + } *__p = (void *) (ptr); \ + __p->__v; \ +}) + +#define put_unaligned(val, ptr) \ +do { \ + struct __packed { \ + typeof(*(ptr)) __v; \ + } *__p = (void *) (ptr); \ + __p->__v = (val); \ +} while(0) + +#endif /* __ASM_GENERIC_UNALIGNED_H */ diff --git a/include/asm-mips/vga.h b/include/asm-mips/vga.h index c1dd0b10bc27..f4cff7e4fa8a 100644 --- a/include/asm-mips/vga.h +++ b/include/asm-mips/vga.h @@ -13,10 +13,10 @@ * access the videoram directly without any black magic. */ -#define VGA_MAP_MEM(x,s) (0xb0000000L + (unsigned long)(x)) +#define VGA_MAP_MEM(x, s) (0xb0000000L + (unsigned long)(x)) #define vga_readb(x) (*(x)) -#define vga_writeb(x,y) (*(y) = (x)) +#define vga_writeb(x, y) (*(y) = (x)) #define VT_BUF_HAVE_RW /* diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index c0715d0a6b28..d2808edfd4e9 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -3,20 +3,22 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2002, 2004 by Ralf Baechle + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle */ #ifndef _ASM_WAR_H #define _ASM_WAR_H +#include <war.h> /* * Another R4600 erratum. Due to the lack of errata information the exact * technical details aren't known. I've experimentally found that disabling * interrupts during indexed I-cache flushes seems to be sufficient to deal * with the issue. - * - * #define R4600_V1_INDEX_ICACHEOP_WAR 1 */ +#ifndef R4600_V1_INDEX_ICACHEOP_WAR +#error Check setting of R4600_V1_INDEX_ICACHEOP_WAR for your platform +#endif /* * Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata: @@ -43,9 +45,10 @@ * nop * nop * cache Hit_Writeback_Invalidate_D - * - * #define R4600_V1_HIT_CACHEOP_WAR 1 */ +#ifndef R4600_V1_HIT_CACHEOP_WAR +#error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform +#endif /* @@ -58,32 +61,11 @@ * by a load instruction to an uncached address to empty the response buffer." * (Revision 2.0 device errata from IDT available on http://www.idt.com/ * in .pdf format.) - * - * #define R4600_V2_HIT_CACHEOP_WAR 1 - */ - -/* - * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors. - */ -#ifdef CONFIG_SGI_IP22 - -#define R4600_V1_INDEX_ICACHEOP_WAR 1 -#define R4600_V1_HIT_CACHEOP_WAR 1 -#define R4600_V2_HIT_CACHEOP_WAR 1 - -#endif - -/* - * But the RM200C seems to have been shipped only with V2.0 R4600s */ -#ifdef CONFIG_SNI_RM - -#define R4600_V2_HIT_CACHEOP_WAR 1 - +#ifndef R4600_V2_HIT_CACHEOP_WAR +#error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform #endif -#ifdef CONFIG_CPU_R5432 - /* * When an interrupt happens on a CP0 register read instruction, CPU may * lock up or read corrupted values of CP0 registers after it enters @@ -93,13 +75,10 @@ * first thing in the exception handler, which breaks one of the * pre-conditions for this problem. */ -#define R5432_CP0_INTERRUPT_WAR 1 - +#ifndef R5432_CP0_INTERRUPT_WAR +#error Check setting of R5432_CP0_INTERRUPT_WAR for your platform #endif -#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \ - defined(CONFIG_SB1_PASS_2_WORKAROUNDS) - /* * Workaround for the Sibyte M3 errata the text of which can be found at * @@ -110,13 +89,15 @@ * will just return and take the exception again if the information was * found to be inconsistent. */ -#define BCM1250_M3_WAR 1 +#ifndef BCM1250_M3_WAR +#error Check setting of BCM1250_M3_WAR for your platform +#endif /* * This is a DUART workaround related to glitches around register accesses */ -#define SIBYTE_1956_WAR 1 - +#ifndef SIBYTE_1956_WAR +#error Check setting of SIBYTE_1956_WAR for your platform #endif /* @@ -131,9 +112,8 @@ * Affects: * MIPS 4K RTL revision <3.0, PRID revision <4 */ -#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS) || \ - defined(CONFIG_MIPS_SEAD) -#define MIPS4K_ICACHE_REFILL_WAR 1 +#ifndef MIPS4K_ICACHE_REFILL_WAR +#error Check setting of MIPS4K_ICACHE_REFILL_WAR for your platform #endif /* @@ -151,9 +131,8 @@ * MIPS 5Kc,5Kf RTL revision <2.3, PRID revision <8 * MIPS 20Kc RTL revision <4.0, PRID revision <? */ -#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS) || \ - defined(CONFIG_MIPS_SEAD) -#define MIPS_CACHE_SYNC_WAR 1 +#ifndef MIPS_CACHE_SYNC_WAR +#error Check setting of MIPS_CACHE_SYNC_WAR for your platform #endif /* @@ -163,16 +142,16 @@ * * Workaround: do two phase flushing for Index_Invalidate_I */ -#ifdef CONFIG_CPU_TX49XX -#define TX49XX_ICACHE_INDEX_INV_WAR 1 +#ifndef TX49XX_ICACHE_INDEX_INV_WAR +#error Check setting of TX49XX_ICACHE_INDEX_INV_WAR for your platform #endif /* * On the RM9000 there is a problem which makes the CreateDirtyExclusive * eache operation unusable on SMP systems. */ -#if defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE) -#define RM9000_CDEX_SMP_WAR 1 +#ifndef RM9000_CDEX_SMP_WAR +#error Check setting of RM9000_CDEX_SMP_WAR for your platform #endif /* @@ -181,69 +160,23 @@ * I-cache line worth of instructions being fetched may case spurious * exceptions. */ -#if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MIPS_ATLAS) || \ - defined(CONFIG_MIPS_MALTA) || defined(CONFIG_PMC_YOSEMITE) || \ - defined(CONFIG_SGI_IP32) || defined(CONFIG_WR_PPMC) -#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#ifndef ICACHE_REFILLS_WORKAROUND_WAR +#error Check setting of ICACHE_REFILLS_WORKAROUND_WAR for your platform #endif /* * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that * may cause ll / sc and lld / scd sequences to execute non-atomically. */ -#ifdef CONFIG_SGI_IP27 -#define R10000_LLSC_WAR 1 +#ifndef R10000_LLSC_WAR +#error Check setting of R10000_LLSC_WAR for your platform #endif /* * 34K core erratum: "Problems Executing the TLBR Instruction" */ -#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \ - defined(CONFIG_PMC_MSP7120_FPGA) -#define MIPS34K_MISSED_ITLB_WAR 1 -#endif - -/* - * Workarounds default to off - */ -#ifndef ICACHE_REFILLS_WORKAROUND_WAR -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#endif -#ifndef R4600_V1_INDEX_ICACHEOP_WAR -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#endif -#ifndef R4600_V1_HIT_CACHEOP_WAR -#define R4600_V1_HIT_CACHEOP_WAR 0 -#endif -#ifndef R4600_V2_HIT_CACHEOP_WAR -#define R4600_V2_HIT_CACHEOP_WAR 0 -#endif -#ifndef R5432_CP0_INTERRUPT_WAR -#define R5432_CP0_INTERRUPT_WAR 0 -#endif -#ifndef BCM1250_M3_WAR -#define BCM1250_M3_WAR 0 -#endif -#ifndef SIBYTE_1956_WAR -#define SIBYTE_1956_WAR 0 -#endif -#ifndef MIPS4K_ICACHE_REFILL_WAR -#define MIPS4K_ICACHE_REFILL_WAR 0 -#endif -#ifndef MIPS_CACHE_SYNC_WAR -#define MIPS_CACHE_SYNC_WAR 0 -#endif -#ifndef TX49XX_ICACHE_INDEX_INV_WAR -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#endif -#ifndef RM9000_CDEX_SMP_WAR -#define RM9000_CDEX_SMP_WAR 0 -#endif -#ifndef R10000_LLSC_WAR -#define R10000_LLSC_WAR 0 -#endif #ifndef MIPS34K_MISSED_ITLB_WAR -#define MIPS34K_MISSED_ITLB_WAR 0 +#error Check setting of MIPS34K_MISSED_ITLB_WAR for your platform #endif #endif /* _ASM_WAR_H */ diff --git a/include/asm-mips/xtalk/xtalk.h b/include/asm-mips/xtalk/xtalk.h index 4a60f27c8817..79bac882a739 100644 --- a/include/asm-mips/xtalk/xtalk.h +++ b/include/asm-mips/xtalk/xtalk.h @@ -45,7 +45,7 @@ typedef struct xtalk_piomap_s *xtalk_piomap_t; #define XIO_PACKED(x) (((x)&XIO_PORT_BITS) != 0) #define XIO_ADDR(x) ((x)&XIO_ADDR_BITS) #define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT)) -#define XIO_PACK(p,o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS)) +#define XIO_PACK(p, o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS)) #endif /* !__ASSEMBLY__ */ |