diff options
Diffstat (limited to 'drivers/staging')
-rw-r--r-- | drivers/staging/cxt1e1/comet.c | 512 |
1 files changed, 256 insertions, 256 deletions
diff --git a/drivers/staging/cxt1e1/comet.c b/drivers/staging/cxt1e1/comet.c index 7e7e1fbe0de5..68ac2a84488d 100644 --- a/drivers/staging/cxt1e1/comet.c +++ b/drivers/staging/cxt1e1/comet.c @@ -41,229 +41,229 @@ STATIC void WrtXmtWaveformTbl(ci_t * ci, comet_t * comet, u_int8_t table[COMET_N void *TWV_table[12] = { - TWVLongHaul0DB, TWVLongHaul7_5DB, TWVLongHaul15DB, TWVLongHaul22_5DB, - TWVShortHaul0, TWVShortHaul1, TWVShortHaul2, TWVShortHaul3, TWVShortHaul4, - TWVShortHaul5, - TWV_E1_75Ohm, /** PORT POINT - 75 Ohm not supported **/ - TWV_E1_120Ohm + TWVLongHaul0DB, TWVLongHaul7_5DB, TWVLongHaul15DB, TWVLongHaul22_5DB, + TWVShortHaul0, TWVShortHaul1, TWVShortHaul2, TWVShortHaul3, TWVShortHaul4, + TWVShortHaul5, + TWV_E1_75Ohm, /** PORT POINT - 75 Ohm not supported **/ + TWV_E1_120Ohm }; static int lbo_tbl_lkup(int t1, int lbo) { - if ((lbo < CFG_LBO_LH0) || (lbo > CFG_LBO_E120)) /* error switches to + if ((lbo < CFG_LBO_LH0) || (lbo > CFG_LBO_E120)) /* error switches to * default */ - { - if (t1) - lbo = CFG_LBO_LH0; /* default T1 waveform table */ - else - lbo = CFG_LBO_E120; /* default E1 waveform table */ - } - return (lbo - 1); /* make index ZERO relative */ + { + if (t1) + lbo = CFG_LBO_LH0; /* default T1 waveform table */ + else + lbo = CFG_LBO_E120; /* default E1 waveform table */ + } + return (lbo - 1); /* make index ZERO relative */ } void init_comet(void *ci, comet_t * comet, u_int32_t port_mode, int clockmaster, - u_int8_t moreParams) + u_int8_t moreParams) { - u_int8_t isT1mode; - u_int8_t tix = CFG_LBO_LH0; /* T1 default */ + u_int8_t isT1mode; + u_int8_t tix = CFG_LBO_LH0; /* T1 default */ - isT1mode = IS_FRAME_ANY_T1 (port_mode); + isT1mode = IS_FRAME_ANY_T1 (port_mode); /* T1 or E1 */ - if (isT1mode) - { - pci_write_32 ((u_int32_t *) &comet->gbl_cfg, 0xa0); /* Select T1 Mode & PIO + if (isT1mode) + { + pci_write_32 ((u_int32_t *) &comet->gbl_cfg, 0xa0); /* Select T1 Mode & PIO * output enabled */ - tix = lbo_tbl_lkup (isT1mode, CFG_LBO_LH0); /* default T1 waveform + tix = lbo_tbl_lkup (isT1mode, CFG_LBO_LH0); /* default T1 waveform * table */ - } else - { - pci_write_32((u_int32_t *) &comet->gbl_cfg, 0x81); /* Select E1 Mode & PIO + } else + { + pci_write_32((u_int32_t *) &comet->gbl_cfg, 0x81); /* Select E1 Mode & PIO * output enabled */ - tix = lbo_tbl_lkup (isT1mode, CFG_LBO_E120); /* default E1 waveform + tix = lbo_tbl_lkup (isT1mode, CFG_LBO_E120); /* default E1 waveform * table */ - } + } - if (moreParams & CFG_LBO_MASK) - tix = lbo_tbl_lkup (isT1mode, moreParams & CFG_LBO_MASK); /* dial-in requested + if (moreParams & CFG_LBO_MASK) + tix = lbo_tbl_lkup (isT1mode, moreParams & CFG_LBO_MASK); /* dial-in requested * waveform table */ /* Tx line Intfc cfg ** Set for analog & no special patterns */ - pci_write_32((u_int32_t *) &comet->tx_line_cfg, 0x00); /* Transmit Line + pci_write_32((u_int32_t *) &comet->tx_line_cfg, 0x00); /* Transmit Line * Interface Config. */ /* master test ** Ignore Test settings for now */ - pci_write_32((u_int32_t *) &comet->mtest, 0x00); /* making sure it's + pci_write_32((u_int32_t *) &comet->mtest, 0x00); /* making sure it's * Default value */ /* Turn on Center (CENT) and everything else off */ - pci_write_32((u_int32_t *) &comet->rjat_cfg, 0x10); /* RJAT cfg */ + pci_write_32((u_int32_t *) &comet->rjat_cfg, 0x10); /* RJAT cfg */ /* Set Jitter Attenuation to recommend T1 values */ - if (isT1mode) - { - pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0x2F); /* RJAT Divider N1 + if (isT1mode) + { + pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0x2F); /* RJAT Divider N1 * Control */ - pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0x2F); /* RJAT Divider N2 + pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0x2F); /* RJAT Divider N2 * Control */ - } else - { - pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0xFF); /* RJAT Divider N1 + } else + { + pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0xFF); /* RJAT Divider N1 * Control */ - pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0xFF); /* RJAT Divider N2 + pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0xFF); /* RJAT Divider N2 * Control */ - } + } /* Turn on Center (CENT) and everything else off */ - pci_write_32((u_int32_t *) &comet->tjat_cfg, 0x10); /* TJAT Config. */ + pci_write_32((u_int32_t *) &comet->tjat_cfg, 0x10); /* TJAT Config. */ /* Do not bypass jitter attenuation and bypass elastic store */ - pci_write_32((u_int32_t *) &comet->rx_opt, 0x00); /* rx opts */ + pci_write_32((u_int32_t *) &comet->rx_opt, 0x00); /* rx opts */ /* TJAT ctrl & TJAT divider ctrl */ /* Set Jitter Attenuation to recommended T1 values */ - if (isT1mode) - { - pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0x2F); /* TJAT Divider N1 + if (isT1mode) + { + pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0x2F); /* TJAT Divider N1 * Control */ - pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0x2F); /* TJAT Divider N2 + pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0x2F); /* TJAT Divider N2 * Control */ - } else - { - pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0xFF); /* TJAT Divider N1 + } else + { + pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0xFF); /* TJAT Divider N1 * Control */ - pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0xFF); /* TJAT Divider N2 + pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0xFF); /* TJAT Divider N2 * Control */ - } + } /* 1c: rx ELST cfg 20: tx ELST cfg 28&38: rx&tx data link ctrl */ - if (isT1mode) - { /* Select 193-bit frame format */ - pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x00); - pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x00); - } else - { /* Select 256-bit frame format */ - pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x03); - pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x03); - pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x00); /* disable T1 data link + if (isT1mode) + { /* Select 193-bit frame format */ + pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x00); + pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x00); + } else + { /* Select 256-bit frame format */ + pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x03); + pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x03); + pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x00); /* disable T1 data link * receive */ - pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x00); /* disable T1 data link + pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x00); /* disable T1 data link * transmit */ - } + } /* the following is a default value */ /* Enable 8 out of 10 validation */ - pci_write_32((u_int32_t *) &comet->t1_rboc_ena, 0x00); /* t1RBOC + pci_write_32((u_int32_t *) &comet->t1_rboc_ena, 0x00); /* t1RBOC * enable(BOC:BitOriented * Code) */ - if (isT1mode) - { + if (isT1mode) + { /* IBCD cfg: aka Inband Code Detection ** loopback code length set to */ - pci_write_32((u_int32_t *) &comet->ibcd_cfg, 0x04); /* 6 bit down, 5 bit up + pci_write_32((u_int32_t *) &comet->ibcd_cfg, 0x04); /* 6 bit down, 5 bit up * (assert) */ pci_write_32((u_int32_t *) &comet->ibcd_act, 0x08); /* line loopback * activate pattern */ pci_write_32((u_int32_t *) &comet->ibcd_deact, 0x24); /* deactivate code * pattern (i.e.001) */ - } + } /* 10: CDRC cfg 28&38: rx&tx data link 1 ctrl 48: t1 frmr cfg */ /* 50: SIGX cfg, COSS (change of signaling state) 54: XBAS cfg */ /* 60: t1 ALMI cfg */ /* Configure Line Coding */ - switch (port_mode) - { - case CFG_FRAME_SF: /* 1 - T1 B8ZS */ - pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0); - pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0); - pci_write_32((u_int32_t *) &comet->sigx_cfg, 0); - pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x20); /* 5:B8ZS */ - pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0); - break; - case CFG_FRAME_ESF: /* 2 - T1 B8ZS */ - pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0); - pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20); /* Bit 5: T1 DataLink + switch (port_mode) + { + case CFG_FRAME_SF: /* 1 - T1 B8ZS */ + pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0); + pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0); + pci_write_32((u_int32_t *) &comet->sigx_cfg, 0); + pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x20); /* 5:B8ZS */ + pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0); + break; + case CFG_FRAME_ESF: /* 2 - T1 B8ZS */ + pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0); + pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20); /* Bit 5: T1 DataLink * Enable */ - pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20); /* 5: T1 DataLink Enable */ - pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30); /* 4:ESF 5:ESFFA */ - pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04); /* 2:ESF */ - pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x30); /* 4:ESF 5:B8ZS */ - pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10); /* 4:ESF */ - break; - case CFG_FRAME_E1PLAIN: /* 3 - HDB3 */ - pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0); - pci_write_32((u_int32_t *) &comet->sigx_cfg, 0); - pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0); - pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40); - break; - case CFG_FRAME_E1CAS: /* 4 - HDB3 */ - pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0); - pci_write_32((u_int32_t *) &comet->sigx_cfg, 0); - pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x60); - pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0); - break; - case CFG_FRAME_E1CRC: /* 5 - HDB3 */ - pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0); - pci_write_32((u_int32_t *) &comet->sigx_cfg, 0); - pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x10); - pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2); - break; - case CFG_FRAME_E1CRC_CAS: /* 6 - HDB3 */ - pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0); - pci_write_32((u_int32_t *) &comet->sigx_cfg, 0); - pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x70); - pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82); - break; - case CFG_FRAME_SF_AMI: /* 7 - T1 AMI */ - pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line + pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20); /* 5: T1 DataLink Enable */ + pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30); /* 4:ESF 5:ESFFA */ + pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04); /* 2:ESF */ + pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x30); /* 4:ESF 5:B8ZS */ + pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10); /* 4:ESF */ + break; + case CFG_FRAME_E1PLAIN: /* 3 - HDB3 */ + pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0); + pci_write_32((u_int32_t *) &comet->sigx_cfg, 0); + pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0); + pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40); + break; + case CFG_FRAME_E1CAS: /* 4 - HDB3 */ + pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0); + pci_write_32((u_int32_t *) &comet->sigx_cfg, 0); + pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x60); + pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0); + break; + case CFG_FRAME_E1CRC: /* 5 - HDB3 */ + pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0); + pci_write_32((u_int32_t *) &comet->sigx_cfg, 0); + pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x10); + pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2); + break; + case CFG_FRAME_E1CRC_CAS: /* 6 - HDB3 */ + pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0); + pci_write_32((u_int32_t *) &comet->sigx_cfg, 0); + pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x70); + pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82); + break; + case CFG_FRAME_SF_AMI: /* 7 - T1 AMI */ + pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line * Decoding */ - pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0); - pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0); - pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0); - pci_write_32((u_int32_t *) &comet->sigx_cfg, 0); - break; - case CFG_FRAME_ESF_AMI: /* 8 - T1 AMI */ - pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line + pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0); + pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0); + pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0); + pci_write_32((u_int32_t *) &comet->sigx_cfg, 0); + break; + case CFG_FRAME_ESF_AMI: /* 8 - T1 AMI */ + pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line * Decoding */ - pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20); /* 5: T1 DataLink Enable */ - pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20); /* 5: T1 DataLink Enable */ - pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30); /* Bit 4:ESF 5:ESFFA */ - pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04); /* 2:ESF */ - pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x10); /* 4:ESF */ - pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10); /* 4:ESF */ - break; - case CFG_FRAME_E1PLAIN_AMI: /* 9 - AMI */ - pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line + pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20); /* 5: T1 DataLink Enable */ + pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20); /* 5: T1 DataLink Enable */ + pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30); /* Bit 4:ESF 5:ESFFA */ + pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04); /* 2:ESF */ + pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x10); /* 4:ESF */ + pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10); /* 4:ESF */ + break; + case CFG_FRAME_E1PLAIN_AMI: /* 9 - AMI */ + pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line * Decoding */ - pci_write_32((u_int32_t *) &comet->sigx_cfg, 0); - pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x80); - pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40); - break; - case CFG_FRAME_E1CAS_AMI: /* 10 - AMI */ - pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line + pci_write_32((u_int32_t *) &comet->sigx_cfg, 0); + pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x80); + pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40); + break; + case CFG_FRAME_E1CAS_AMI: /* 10 - AMI */ + pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line * Decoding */ - pci_write_32((u_int32_t *) &comet->sigx_cfg, 0); - pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xe0); - pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0); - break; - case CFG_FRAME_E1CRC_AMI: /* 11 - AMI */ - pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line + pci_write_32((u_int32_t *) &comet->sigx_cfg, 0); + pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xe0); + pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0); + break; + case CFG_FRAME_E1CRC_AMI: /* 11 - AMI */ + pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line * Decoding */ - pci_write_32((u_int32_t *) &comet->sigx_cfg, 0); - pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x90); - pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2); - break; - case CFG_FRAME_E1CRC_CAS_AMI: /* 12 - AMI */ - pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line + pci_write_32((u_int32_t *) &comet->sigx_cfg, 0); + pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x90); + pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2); + break; + case CFG_FRAME_E1CRC_CAS_AMI: /* 12 - AMI */ + pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line * Decoding */ - pci_write_32((u_int32_t *) &comet->sigx_cfg, 0); - pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xf0); - pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82); - break; - } /* end switch */ + pci_write_32((u_int32_t *) &comet->sigx_cfg, 0); + pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xf0); + pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82); + break; + } /* end switch */ /*** * Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0) @@ -277,68 +277,68 @@ init_comet(void *ci, comet_t * comet, u_int32_t port_mode, int clockmaster, /* 0x30: "BRIF cfg"; 0x20 is 'CMODE', 0x03 is (bit) rate */ /* note "rate bits can only be set once after reset" */ - if (clockmaster) - { /* CMODE == clockMode, 0=clock master (so + if (clockmaster) + { /* CMODE == clockMode, 0=clock master (so * all 3 others should be slave) */ - if (isT1mode) /* rate = 1.544 Mb/s */ - pci_write_32((u_int32_t *) &comet->brif_cfg, 0x00); /* Comet 0 Master + if (isT1mode) /* rate = 1.544 Mb/s */ + pci_write_32((u_int32_t *) &comet->brif_cfg, 0x00); /* Comet 0 Master * Mode(CMODE=0) */ - else /* rate = 2.048 Mb/s */ - pci_write_32((u_int32_t *) &comet->brif_cfg, 0x01); /* Comet 0 Master + else /* rate = 2.048 Mb/s */ + pci_write_32((u_int32_t *) &comet->brif_cfg, 0x01); /* Comet 0 Master * Mode(CMODE=0) */ /* 31: BRIF frame pulse cfg 06: tx timing options */ - pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x00); /* Master Mode + pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x00); /* Master Mode * i.e.FPMODE=0 (@0x20) */ - if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL) - { - if (cxt1e1_log_level >= LOG_SBEBUG12) - pr_info(">> %s: clockmaster internal clock\n", __func__); - pci_write_32((u_int32_t *) &comet->tx_time, 0x0d); /* internal oscillator */ - } else /* external clock source */ - { - if (cxt1e1_log_level >= LOG_SBEBUG12) - pr_info(">> %s: clockmaster external clock\n", __func__); - pci_write_32((u_int32_t *) &comet->tx_time, 0x09); /* loop timing + if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL) + { + if (cxt1e1_log_level >= LOG_SBEBUG12) + pr_info(">> %s: clockmaster internal clock\n", __func__); + pci_write_32((u_int32_t *) &comet->tx_time, 0x0d); /* internal oscillator */ + } else /* external clock source */ + { + if (cxt1e1_log_level >= LOG_SBEBUG12) + pr_info(">> %s: clockmaster external clock\n", __func__); + pci_write_32((u_int32_t *) &comet->tx_time, 0x09); /* loop timing * (external) */ - } + } - } else /* slave */ - { - if (isT1mode) - pci_write_32((u_int32_t *) &comet->brif_cfg, 0x20); /* Slave Mode(CMODE=1, + } else /* slave */ + { + if (isT1mode) + pci_write_32((u_int32_t *) &comet->brif_cfg, 0x20); /* Slave Mode(CMODE=1, * see above) */ - else - pci_write_32((u_int32_t *) &comet->brif_cfg, 0x21); /* Slave Mode (CMODE=1) */ - pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x20); /* Slave Mode i.e. + else + pci_write_32((u_int32_t *) &comet->brif_cfg, 0x21); /* Slave Mode (CMODE=1) */ + pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x20); /* Slave Mode i.e. * FPMODE=1 (@0x20) */ - if (cxt1e1_log_level >= LOG_SBEBUG12) - pr_info(">> %s: clockslave internal clock\n", __func__); - pci_write_32((u_int32_t *) &comet->tx_time, 0x0d); /* oscillator timing */ - } + if (cxt1e1_log_level >= LOG_SBEBUG12) + pr_info(">> %s: clockslave internal clock\n", __func__); + pci_write_32((u_int32_t *) &comet->tx_time, 0x0d); /* oscillator timing */ + } /* 32: BRIF parity F-bit cfg */ /* Totem-pole operation */ - pci_write_32((u_int32_t *) &comet->brif_pfcfg, 0x01); /* Receive Backplane + pci_write_32((u_int32_t *) &comet->brif_pfcfg, 0x01); /* Receive Backplane * Parity/F-bit */ /* dc: RLPS equalizer V ref */ /* Configuration */ - if (isT1mode) - pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x2c); /* RLPS Equalizer + if (isT1mode) + pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x2c); /* RLPS Equalizer * Voltage */ - else - pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x34); /* RLPS Equalizer + else + pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x34); /* RLPS Equalizer * Voltage */ /* Reserved bit set and SQUELCH enabled */ /* f8: RLPS cfg & status f9: RLPS ALOS detect/clear threshold */ - pci_write_32((u_int32_t *) &comet->rlps_cfgsts, 0x11); /* RLPS Configuration + pci_write_32((u_int32_t *) &comet->rlps_cfgsts, 0x11); /* RLPS Configuration * Status */ - if (isT1mode) - pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x55); /* ? */ - else - pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x22); /* ? */ + if (isT1mode) + pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x55); /* ? */ + else + pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x22); /* ? */ /* Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0) */ @@ -347,32 +347,32 @@ init_comet(void *ci, comet_t * comet, u_int32_t port_mode, int clockmaster, /* CMS=0: Use backplane freq, RATE[1:0]=0,0: T1 */ /*** Transmit side is always an Input, Slave Clock*/ /* 40: BTIF cfg 41: BTIF frame pulse cfg */ - if (isT1mode) - pci_write_32((u_int32_t *) &comet->btif_cfg, 0x38); /* BTIF Configuration + if (isT1mode) + pci_write_32((u_int32_t *) &comet->btif_cfg, 0x38); /* BTIF Configuration * Reg. */ - else - pci_write_32((u_int32_t *) &comet->btif_cfg, 0x39); /* BTIF Configuration + else + pci_write_32((u_int32_t *) &comet->btif_cfg, 0x39); /* BTIF Configuration * Reg. */ - pci_write_32((u_int32_t *) &comet->btif_fpcfg, 0x01); /* BTIF Frame Pulse + pci_write_32((u_int32_t *) &comet->btif_fpcfg, 0x01); /* BTIF Frame Pulse * Config. */ /* 0a: master diag 06: tx timing options */ /* if set Comet to loop back */ /* Comets set to normal */ - pci_write_32((u_int32_t *) &comet->mdiag, 0x00); + pci_write_32((u_int32_t *) &comet->mdiag, 0x00); /* BTCLK driven by TCLKI internally (crystal driven) and Xmt Elasted */ /* Store is enabled. */ - WrtXmtWaveformTbl(ci, comet, TWV_table[tix]); - if (isT1mode) - WrtRcvEqualizerTbl((ci_t *) ci, comet, &T1_Equalizer[0]); - else - WrtRcvEqualizerTbl((ci_t *) ci, comet, &E1_Equalizer[0]); - SetPwrLevel (comet); -} + WrtXmtWaveformTbl(ci, comet, TWV_table[tix]); + if (isT1mode) + WrtRcvEqualizerTbl((ci_t *) ci, comet, &T1_Equalizer[0]); + else + WrtRcvEqualizerTbl((ci_t *) ci, comet, &E1_Equalizer[0]); + SetPwrLevel (comet); + } /* ** Name: WrtXmtWaveform @@ -384,13 +384,13 @@ init_comet(void *ci, comet_t * comet, u_int32_t port_mode, int clockmaster, STATIC void WrtXmtWaveform(ci_t * ci, comet_t * comet, u_int32_t sample, u_int32_t unit, u_int8_t data) { - u_int8_t WaveformAddr; + u_int8_t WaveformAddr; - WaveformAddr = (sample << 3) + (unit & 7); - pci_write_32((u_int32_t *) &comet->xlpg_pwave_addr, WaveformAddr); - pci_flush_write (ci); /* for write order preservation when + WaveformAddr = (sample << 3) + (unit & 7); + pci_write_32((u_int32_t *) &comet->xlpg_pwave_addr, WaveformAddr); + pci_flush_write (ci); /* for write order preservation when * Optimizing driver */ - pci_write_32((u_int32_t *) &comet->xlpg_pwave_data, 0x7F & data); + pci_write_32((u_int32_t *) &comet->xlpg_pwave_data, 0x7F & data); } /* @@ -401,18 +401,18 @@ WrtXmtWaveform(ci_t * ci, comet_t * comet, u_int32_t sample, u_int32_t unit, u_i */ STATIC void WrtXmtWaveformTbl(ci_t * ci, comet_t * comet, - u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS]) + u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS]) { - u_int32_t sample, unit; + u_int32_t sample, unit; - for (sample = 0; sample < COMET_NUM_SAMPLES; sample++) - { + for (sample = 0; sample < COMET_NUM_SAMPLES; sample++) + { for (unit = 0; unit < COMET_NUM_UNITS; unit++) - WrtXmtWaveform(ci, comet, sample, unit, table[sample][unit]); - } + WrtXmtWaveform(ci, comet, sample, unit, table[sample][unit]); + } /* Enable transmitter and set output amplitude */ - pci_write_32((u_int32_t *) &comet->xlpg_cfg, table[COMET_NUM_SAMPLES][0]); + pci_write_32((u_int32_t *) &comet->xlpg_cfg, table[COMET_NUM_SAMPLES][0]); } @@ -429,30 +429,30 @@ WrtXmtWaveformTbl(ci_t * ci, comet_t * comet, STATIC void WrtRcvEqualizerTbl(ci_t * ci, comet_t * comet, u_int32_t *table) { - u_int32_t ramaddr; - volatile u_int32_t value; + u_int32_t ramaddr; + volatile u_int32_t value; - for (ramaddr = 0; ramaddr < 256; ramaddr++) - { + for (ramaddr = 0; ramaddr < 256; ramaddr++) + { /*** the following lines are per Errata 7, 2.5 ***/ { - pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0x80); /* Set up for a read + pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0x80); /* Set up for a read * operation */ - pci_flush_write(ci); /* for write order preservation when + pci_flush_write(ci); /* for write order preservation when * Optimizing driver */ - pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr); /* write the addr, + pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr); /* write the addr, * initiate a read */ - pci_flush_write (ci); /* for write order preservation when + pci_flush_write (ci); /* for write order preservation when * Optimizing driver */ /* * wait 3 line rate clock cycles to ensure address bits are * captured by T1/E1 clock */ - OS_uwait(4, "wret"); /* 683ns * 3 = 1366 ns, approx 2us (but + OS_uwait(4, "wret"); /* 683ns * 3 = 1366 ns, approx 2us (but * use 4us) */ - } + } - value = *table++; + value = *table++; pci_write_32((u_int32_t *) &comet->rlps_idata3, (u_int8_t) (value >> 24)); pci_write_32((u_int32_t *) &comet->rlps_idata2, (u_int8_t) (value >> 16)); pci_write_32((u_int32_t *) &comet->rlps_idata1, (u_int8_t) (value >> 8)); @@ -476,9 +476,9 @@ WrtRcvEqualizerTbl(ci_t * ci, comet_t * comet, u_int32_t *table) */ OS_uwait(4, "wret"); /* 683ns * 3 = 1366 ns, approx 2us (but * use 4us) */ - } + } - pci_write_32((u_int32_t *) &comet->rlps_eq_cfg, 0xCB); /* Enable Equalizer & + pci_write_32((u_int32_t *) &comet->rlps_eq_cfg, 0xCB); /* Enable Equalizer & * set it to use 256 * periods */ } @@ -493,7 +493,7 @@ WrtRcvEqualizerTbl(ci_t * ci, comet_t * comet, u_int32_t *table) STATIC void SetPwrLevel(comet_t * comet) { - volatile u_int32_t temp; + volatile u_int32_t temp; /* ** Algorithm to Balance the Power Distribution of Ttip Tring @@ -507,22 +507,22 @@ SetPwrLevel(comet_t * comet) ** Repeat these steps for register F5 ** Write 0x01 to register F6 */ - pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x00); /* XLPG Fuse Data Select */ + pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x00); /* XLPG Fuse Data Select */ - pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01); /* XLPG Analog Test + pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01); /* XLPG Analog Test * Positive control */ - pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01); + pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01); - temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_pctl) & 0xfe; - pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, temp); + temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_pctl) & 0xfe; + pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, temp); - pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01); /* XLPG Analog Test + pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01); /* XLPG Analog Test * Negative control */ - pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01); + pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01); - temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_nctl) & 0xfe; - pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, temp); - pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x01); /* XLPG */ + temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_nctl) & 0xfe; + pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, temp); + pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x01); /* XLPG */ } @@ -537,31 +537,31 @@ SetPwrLevel(comet_t * comet) STATIC void SetCometOps(comet_t * comet) { - volatile u_int8_t rd_value; + volatile u_int8_t rd_value; - if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2)) - { - rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg); /* read the BRIF + if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2)) + { + rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg); /* read the BRIF * Configuration */ - rd_value &= ~0x20; - pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value); + rd_value &= ~0x20; + pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value); - rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg); /* read the BRIF Frame + rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg); /* read the BRIF Frame * Pulse Configuration */ - rd_value &= ~0x20; - pci_write_32((u_int32_t *) &comet->brif_fpcfg, (u_int8_t) rd_value); - } else - { - rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg); /* read the BRIF + rd_value &= ~0x20; + pci_write_32((u_int32_t *) &comet->brif_fpcfg, (u_int8_t) rd_value); + } else + { + rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg); /* read the BRIF * Configuration */ - rd_value |= 0x20; - pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value); + rd_value |= 0x20; + pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value); - rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg); /* read the BRIF Frame + rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg); /* read the BRIF Frame * Pulse Configuration */ - rd_value |= 0x20; - pci_write_32((u_int32_t *) &comet->brif_fpcfg, (u_int8_t) rd_value); - } + rd_value |= 0x20; + pci_write_32((u_int32_t *) &comet->brif_fpcfg, (u_int8_t) rd_value); + } } #endif |