diff options
Diffstat (limited to 'drivers/pinctrl')
54 files changed, 6533 insertions, 738 deletions
diff --git a/drivers/pinctrl/actions/Kconfig b/drivers/pinctrl/actions/Kconfig index 2397cb0f6011..c7ed1d481802 100644 --- a/drivers/pinctrl/actions/Kconfig +++ b/drivers/pinctrl/actions/Kconfig @@ -9,6 +9,12 @@ config PINCTRL_OWL help Say Y here to enable Actions Semi OWL pinctrl driver +config PINCTRL_S700 + bool "Actions Semi S700 pinctrl driver" + depends on PINCTRL_OWL + help + Say Y here to enable Actions Semi S700 pinctrl driver + config PINCTRL_S900 bool "Actions Semi S900 pinctrl driver" depends on PINCTRL_OWL diff --git a/drivers/pinctrl/actions/Makefile b/drivers/pinctrl/actions/Makefile index bd232d28400f..86521ed837dd 100644 --- a/drivers/pinctrl/actions/Makefile +++ b/drivers/pinctrl/actions/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_PINCTRL_OWL) += pinctrl-owl.o +obj-$(CONFIG_PINCTRL_S700) += pinctrl-s700.o obj-$(CONFIG_PINCTRL_S900) += pinctrl-s900.o diff --git a/drivers/pinctrl/actions/pinctrl-owl.c b/drivers/pinctrl/actions/pinctrl-owl.c index 9d18c02f192b..5dfe7188a5f8 100644 --- a/drivers/pinctrl/actions/pinctrl-owl.c +++ b/drivers/pinctrl/actions/pinctrl-owl.c @@ -246,60 +246,6 @@ static int owl_pad_pinconf_reg(const struct owl_padinfo *info, return 0; } -static int owl_pad_pinconf_arg2val(const struct owl_padinfo *info, - unsigned int param, - u32 *arg) -{ - switch (param) { - case PIN_CONFIG_BIAS_BUS_HOLD: - *arg = OWL_PINCONF_PULL_HOLD; - break; - case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: - *arg = OWL_PINCONF_PULL_HIZ; - break; - case PIN_CONFIG_BIAS_PULL_DOWN: - *arg = OWL_PINCONF_PULL_DOWN; - break; - case PIN_CONFIG_BIAS_PULL_UP: - *arg = OWL_PINCONF_PULL_UP; - break; - case PIN_CONFIG_INPUT_SCHMITT_ENABLE: - *arg = (*arg >= 1 ? 1 : 0); - break; - default: - return -ENOTSUPP; - } - - return 0; -} - -static int owl_pad_pinconf_val2arg(const struct owl_padinfo *padinfo, - unsigned int param, - u32 *arg) -{ - switch (param) { - case PIN_CONFIG_BIAS_BUS_HOLD: - *arg = *arg == OWL_PINCONF_PULL_HOLD; - break; - case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: - *arg = *arg == OWL_PINCONF_PULL_HIZ; - break; - case PIN_CONFIG_BIAS_PULL_DOWN: - *arg = *arg == OWL_PINCONF_PULL_DOWN; - break; - case PIN_CONFIG_BIAS_PULL_UP: - *arg = *arg == OWL_PINCONF_PULL_UP; - break; - case PIN_CONFIG_INPUT_SCHMITT_ENABLE: - *arg = *arg == 1; - break; - default: - return -ENOTSUPP; - } - - return 0; -} - static int owl_pin_config_get(struct pinctrl_dev *pctrldev, unsigned int pin, unsigned long *config) @@ -318,7 +264,10 @@ static int owl_pin_config_get(struct pinctrl_dev *pctrldev, arg = owl_read_field(pctrl, reg, bit, width); - ret = owl_pad_pinconf_val2arg(info, param, &arg); + if (!pctrl->soc->padctl_val2arg) + return -ENOTSUPP; + + ret = pctrl->soc->padctl_val2arg(info, param, &arg); if (ret) return ret; @@ -349,7 +298,10 @@ static int owl_pin_config_set(struct pinctrl_dev *pctrldev, if (ret) return ret; - ret = owl_pad_pinconf_arg2val(info, param, &arg); + if (!pctrl->soc->padctl_arg2val) + return -ENOTSUPP; + + ret = pctrl->soc->padctl_arg2val(info, param, &arg); if (ret) return ret; @@ -787,7 +739,7 @@ static void owl_gpio_irq_mask(struct irq_data *data) val = readl_relaxed(gpio_base + port->intc_msk); if (val == 0) owl_gpio_update_reg(gpio_base + port->intc_ctl, - OWL_GPIO_CTLR_ENABLE, false); + OWL_GPIO_CTLR_ENABLE + port->shared_ctl_offset * 5, false); raw_spin_unlock_irqrestore(&pctrl->lock, flags); } @@ -811,7 +763,8 @@ static void owl_gpio_irq_unmask(struct irq_data *data) /* enable port interrupt */ value = readl_relaxed(gpio_base + port->intc_ctl); - value |= BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M); + value |= ((BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M)) + << port->shared_ctl_offset * 5); writel_relaxed(value, gpio_base + port->intc_ctl); /* enable GPIO interrupt */ @@ -849,7 +802,7 @@ static void owl_gpio_irq_ack(struct irq_data *data) raw_spin_lock_irqsave(&pctrl->lock, flags); owl_gpio_update_reg(gpio_base + port->intc_ctl, - OWL_GPIO_CTLR_PENDING, true); + OWL_GPIO_CTLR_PENDING + port->shared_ctl_offset * 5, true); raw_spin_unlock_irqrestore(&pctrl->lock, flags); } diff --git a/drivers/pinctrl/actions/pinctrl-owl.h b/drivers/pinctrl/actions/pinctrl-owl.h index a724d1d406d4..dae2e8363fd5 100644 --- a/drivers/pinctrl/actions/pinctrl-owl.h +++ b/drivers/pinctrl/actions/pinctrl-owl.h @@ -15,12 +15,135 @@ #define OWL_PINCONF_SLEW_SLOW 0 #define OWL_PINCONF_SLEW_FAST 1 -enum owl_pinconf_pull { - OWL_PINCONF_PULL_HIZ, - OWL_PINCONF_PULL_DOWN, - OWL_PINCONF_PULL_UP, - OWL_PINCONF_PULL_HOLD, -}; +#define MUX_PG(group_name, reg, shift, width) \ + { \ + .name = #group_name, \ + .pads = group_name##_pads, \ + .npads = ARRAY_SIZE(group_name##_pads), \ + .funcs = group_name##_funcs, \ + .nfuncs = ARRAY_SIZE(group_name##_funcs), \ + .mfpctl_reg = MFCTL##reg, \ + .mfpctl_shift = shift, \ + .mfpctl_width = width, \ + .drv_reg = -1, \ + .drv_shift = -1, \ + .drv_width = -1, \ + .sr_reg = -1, \ + .sr_shift = -1, \ + .sr_width = -1, \ + } + +#define DRV_PG(group_name, reg, shift, width) \ + { \ + .name = #group_name, \ + .pads = group_name##_pads, \ + .npads = ARRAY_SIZE(group_name##_pads), \ + .mfpctl_reg = -1, \ + .mfpctl_shift = -1, \ + .mfpctl_width = -1, \ + .drv_reg = PAD_DRV##reg, \ + .drv_shift = shift, \ + .drv_width = width, \ + .sr_reg = -1, \ + .sr_shift = -1, \ + .sr_width = -1, \ + } + +#define SR_PG(group_name, reg, shift, width) \ + { \ + .name = #group_name, \ + .pads = group_name##_pads, \ + .npads = ARRAY_SIZE(group_name##_pads), \ + .mfpctl_reg = -1, \ + .mfpctl_shift = -1, \ + .mfpctl_width = -1, \ + .drv_reg = -1, \ + .drv_shift = -1, \ + .drv_width = -1, \ + .sr_reg = PAD_SR##reg, \ + .sr_shift = shift, \ + .sr_width = width, \ + } + +#define FUNCTION(fname) \ + { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +/* PAD PULL UP/DOWN CONFIGURES */ +#define PULLCTL_CONF(pull_reg, pull_sft, pull_wdt) \ + { \ + .reg = PAD_PULLCTL##pull_reg, \ + .shift = pull_sft, \ + .width = pull_wdt, \ + } + +#define PAD_PULLCTL_CONF(pad_name, pull_reg, pull_sft, pull_wdt) \ + struct owl_pullctl pad_name##_pullctl_conf \ + = PULLCTL_CONF(pull_reg, pull_sft, pull_wdt) + +#define ST_CONF(st_reg, st_sft, st_wdt) \ + { \ + .reg = PAD_ST##st_reg, \ + .shift = st_sft, \ + .width = st_wdt, \ + } + +#define PAD_ST_CONF(pad_name, st_reg, st_sft, st_wdt) \ + struct owl_st pad_name##_st_conf \ + = ST_CONF(st_reg, st_sft, st_wdt) + +#define PAD_INFO(name) \ + { \ + .pad = name, \ + .pullctl = NULL, \ + .st = NULL, \ + } + +#define PAD_INFO_ST(name) \ + { \ + .pad = name, \ + .pullctl = NULL, \ + .st = &name##_st_conf, \ + } + +#define PAD_INFO_PULLCTL(name) \ + { \ + .pad = name, \ + .pullctl = &name##_pullctl_conf, \ + .st = NULL, \ + } + +#define PAD_INFO_PULLCTL_ST(name) \ + { \ + .pad = name, \ + .pullctl = &name##_pullctl_conf, \ + .st = &name##_st_conf, \ + } + +#define OWL_GPIO_PORT_A 0 +#define OWL_GPIO_PORT_B 1 +#define OWL_GPIO_PORT_C 2 +#define OWL_GPIO_PORT_D 3 +#define OWL_GPIO_PORT_E 4 +#define OWL_GPIO_PORT_F 5 + +#define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat, _intc_ctl,\ + _intc_pd, _intc_msk, _intc_type, _share) \ + [OWL_GPIO_PORT_##port] = { \ + .offset = base, \ + .pins = count, \ + .outen = _outen, \ + .inen = _inen, \ + .dat = _dat, \ + .intc_ctl = _intc_ctl, \ + .intc_pd = _intc_pd, \ + .intc_msk = _intc_msk, \ + .intc_type = _intc_type, \ + .shared_ctl_offset = _share, \ + } enum owl_pinconf_drv { OWL_PINCONF_DRV_2MA, @@ -148,6 +271,7 @@ struct owl_gpio_port { unsigned int intc_pd; unsigned int intc_msk; unsigned int intc_type; + u8 shared_ctl_offset; }; /** @@ -174,6 +298,12 @@ struct owl_pinctrl_soc_data { unsigned int ngpios; const struct owl_gpio_port *ports; unsigned int nports; + int (*padctl_val2arg)(const struct owl_padinfo *padinfo, + unsigned int param, + u32 *arg); + int (*padctl_arg2val)(const struct owl_padinfo *info, + unsigned int param, + u32 *arg); }; int owl_pinctrl_probe(struct platform_device *pdev, diff --git a/drivers/pinctrl/actions/pinctrl-s700.c b/drivers/pinctrl/actions/pinctrl-s700.c new file mode 100644 index 000000000000..8b8121e35edb --- /dev/null +++ b/drivers/pinctrl/actions/pinctrl-s700.c @@ -0,0 +1,1912 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Actions Semi Owl S700 Pinctrl driver + * + * Copyright (c) 2014 Actions Semi Inc. + * Author: David Liu <liuwei@actions-semi.com> + * + * Author: Pathiban Nallathambi <pn@denx.de> + * Author: Saravanan Sekar <sravanhome@gmail.com> + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include "pinctrl-owl.h" + +/* Pinctrl registers offset */ +#define MFCTL0 (0x0040) +#define MFCTL1 (0x0044) +#define MFCTL2 (0x0048) +#define MFCTL3 (0x004C) +#define PAD_PULLCTL0 (0x0060) +#define PAD_PULLCTL1 (0x0064) +#define PAD_PULLCTL2 (0x0068) +#define PAD_ST0 (0x006C) +#define PAD_ST1 (0x0070) +#define PAD_CTL (0x0074) +#define PAD_DRV0 (0x0080) +#define PAD_DRV1 (0x0084) +#define PAD_DRV2 (0x0088) + +/* + * Most pins affected by the pinmux can also be GPIOs. Define these first. + * These must match how the GPIO driver names/numbers its pins. + */ +#define _GPIOA(offset) (offset) +#define _GPIOB(offset) (32 + (offset)) +#define _GPIOC(offset) (64 + (offset)) +#define _GPIOD(offset) (96 + (offset)) +#define _GPIOE(offset) (128 + (offset)) + +/* All non-GPIO pins follow */ +#define NUM_GPIOS (_GPIOE(7) + 1) +#define _PIN(offset) (NUM_GPIOS + (offset)) + +/* Ethernet MAC */ +#define ETH_TXD0 _GPIOA(14) +#define ETH_TXD1 _GPIOA(15) +#define ETH_TXD2 _GPIOE(4) +#define ETH_TXD3 _GPIOE(5) +#define ETH_TXEN _GPIOA(16) +#define ETH_RXER _GPIOA(17) +#define ETH_CRS_DV _GPIOA(18) +#define ETH_RXD1 _GPIOA(19) +#define ETH_RXD0 _GPIOA(20) +#define ETH_RXD2 _GPIOE(6) +#define ETH_RXD3 _GPIOE(7) +#define ETH_REF_CLK _GPIOA(21) +#define ETH_MDC _GPIOA(22) +#define ETH_MDIO _GPIOA(23) + +/* SIRQ */ +#define SIRQ0 _GPIOA(24) +#define SIRQ1 _GPIOA(25) +#define SIRQ2 _GPIOA(26) + +/* I2S */ +#define I2S_D0 _GPIOA(27) +#define I2S_BCLK0 _GPIOA(28) +#define I2S_LRCLK0 _GPIOA(29) +#define I2S_MCLK0 _GPIOA(30) +#define I2S_D1 _GPIOA(31) +#define I2S_BCLK1 _GPIOB(0) +#define I2S_LRCLK1 _GPIOB(1) +#define I2S_MCLK1 _GPIOB(2) + +/* PCM1 */ +#define PCM1_IN _GPIOD(28) +#define PCM1_CLK _GPIOD(29) +#define PCM1_SYNC _GPIOD(30) +#define PCM1_OUT _GPIOD(31) + +/* KEY */ +#define KS_IN0 _GPIOB(3) +#define KS_IN1 _GPIOB(4) +#define KS_IN2 _GPIOB(5) +#define KS_IN3 _GPIOB(6) +#define KS_OUT0 _GPIOB(7) +#define KS_OUT1 _GPIOB(8) +#define KS_OUT2 _GPIOB(9) + +/* LVDS */ +#define LVDS_OEP _GPIOB(10) +#define LVDS_OEN _GPIOB(11) +#define LVDS_ODP _GPIOB(12) +#define LVDS_ODN _GPIOB(13) +#define LVDS_OCP _GPIOB(14) +#define LVDS_OCN _GPIOB(15) +#define LVDS_OBP _GPIOB(16) +#define LVDS_OBN _GPIOB(17) +#define LVDS_OAP _GPIOB(18) +#define LVDS_OAN _GPIOB(19) +#define LVDS_EEP _GPIOB(20) +#define LVDS_EEN _GPIOB(21) +#define LVDS_EDP _GPIOB(22) +#define LVDS_EDN _GPIOB(23) +#define LVDS_ECP _GPIOB(24) +#define LVDS_ECN _GPIOB(25) +#define LVDS_EBP _GPIOB(26) +#define LVDS_EBN _GPIOB(27) +#define LVDS_EAP _GPIOB(28) +#define LVDS_EAN _GPIOB(29) +#define LCD0_D18 _GPIOB(30) +#define LCD0_D2 _GPIOB(31) + +/* DSI */ +#define DSI_DP3 _GPIOC(0) +#define DSI_DN3 _GPIOC(1) +#define DSI_DP1 _GPIOC(2) +#define DSI_DN1 _GPIOC(3) +#define DSI_CP _GPIOC(4) +#define DSI_CN _GPIOC(5) +#define DSI_DP0 _GPIOC(6) +#define DSI_DN0 _GPIOC(7) +#define DSI_DP2 _GPIOC(8) +#define DSI_DN2 _GPIOC(9) + +/* SD */ +#define SD0_D0 _GPIOC(10) +#define SD0_D1 _GPIOC(11) +#define SD0_D2 _GPIOC(12) +#define SD0_D3 _GPIOC(13) +#define SD0_D4 _GPIOC(14) +#define SD0_D5 _GPIOC(15) +#define SD0_D6 _GPIOC(16) +#define SD0_D7 _GPIOC(17) +#define SD0_CMD _GPIOC(18) +#define SD0_CLK _GPIOC(19) +#define SD1_CMD _GPIOC(20) +#define SD1_CLK _GPIOC(21) +#define SD1_D0 SD0_D4 +#define SD1_D1 SD0_D5 +#define SD1_D2 SD0_D6 +#define SD1_D3 SD0_D7 + +/* SPI */ +#define SPI0_SS _GPIOC(23) +#define SPI0_MISO _GPIOC(24) + +/* UART for console */ +#define UART0_RX _GPIOC(26) +#define UART0_TX _GPIOC(27) + +/* UART for Bluetooth */ +#define UART2_RX _GPIOD(18) +#define UART2_TX _GPIOD(19) +#define UART2_RTSB _GPIOD(20) +#define UART2_CTSB _GPIOD(21) + +/* UART for 3G */ +#define UART3_RX _GPIOD(22) +#define UART3_TX _GPIOD(23) +#define UART3_RTSB _GPIOD(24) +#define UART3_CTSB _GPIOD(25) + +/* I2C */ +#define I2C0_SCLK _GPIOC(28) +#define I2C0_SDATA _GPIOC(29) +#define I2C1_SCLK _GPIOE(0) +#define I2C1_SDATA _GPIOE(1) +#define I2C2_SCLK _GPIOE(2) +#define I2C2_SDATA _GPIOE(3) + +/* CSI*/ +#define CSI_DN0 _PIN(0) +#define CSI_DP0 _PIN(1) +#define CSI_DN1 _PIN(2) +#define CSI_DP1 _PIN(3) +#define CSI_CN _PIN(4) +#define CSI_CP _PIN(5) +#define CSI_DN2 _PIN(6) +#define CSI_DP2 _PIN(7) +#define CSI_DN3 _PIN(8) +#define CSI_DP3 _PIN(9) + +/* Sensor */ +#define SENSOR0_PCLK _GPIOC(31) +#define SENSOR0_CKOUT _GPIOD(10) + +/* NAND (1.8v / 3.3v) */ +#define DNAND_D0 _PIN(10) +#define DNAND_D1 _PIN(11) +#define DNAND_D2 _PIN(12) +#define DNAND_D3 _PIN(13) +#define DNAND_D4 _PIN(14) +#define DNAND_D5 _PIN(15) +#define DNAND_D6 _PIN(16) +#define DNAND_D7 _PIN(17) +#define DNAND_WRB _PIN(18) +#define DNAND_RDB _PIN(19) +#define DNAND_RDBN _PIN(20) +#define DNAND_DQS _GPIOA(12) +#define DNAND_DQSN _GPIOA(13) +#define DNAND_RB0 _PIN(21) +#define DNAND_ALE _GPIOD(12) +#define DNAND_CLE _GPIOD(13) +#define DNAND_CEB0 _GPIOD(14) +#define DNAND_CEB1 _GPIOD(15) +#define DNAND_CEB2 _GPIOD(16) +#define DNAND_CEB3 _GPIOD(17) + +/* System */ +#define PORB _PIN(22) +#define CLKO_25M _PIN(23) +#define BSEL _PIN(24) +#define PKG0 _PIN(25) +#define PKG1 _PIN(26) +#define PKG2 _PIN(27) +#define PKG3 _PIN(28) + +#define _FIRSTPAD _GPIOA(0) +#define _LASTPAD PKG3 +#define NUM_PADS (_PIN(28) + 1) + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc s700_pads[] = { + PINCTRL_PIN(ETH_TXD0, "eth_txd0"), + PINCTRL_PIN(ETH_TXD1, "eth_txd1"), + PINCTRL_PIN(ETH_TXD2, "eth_txd2"), + PINCTRL_PIN(ETH_TXD3, "eth_txd3"), + PINCTRL_PIN(ETH_TXEN, "eth_txen"), + PINCTRL_PIN(ETH_RXER, "eth_rxer"), + PINCTRL_PIN(ETH_CRS_DV, "eth_crs_dv"), + PINCTRL_PIN(ETH_RXD1, "eth_rxd1"), + PINCTRL_PIN(ETH_RXD0, "eth_rxd0"), + PINCTRL_PIN(ETH_RXD2, "eth_rxd2"), + PINCTRL_PIN(ETH_RXD3, "eth_rxd3"), + PINCTRL_PIN(ETH_REF_CLK, "eth_ref_clk"), + PINCTRL_PIN(ETH_MDC, "eth_mdc"), + PINCTRL_PIN(ETH_MDIO, "eth_mdio"), + PINCTRL_PIN(SIRQ0, "sirq0"), + PINCTRL_PIN(SIRQ1, "sirq1"), + PINCTRL_PIN(SIRQ2, "sirq2"), + PINCTRL_PIN(I2S_D0, "i2s_d0"), + PINCTRL_PIN(I2S_BCLK0, "i2s_bclk0"), + PINCTRL_PIN(I2S_LRCLK0, "i2s_lrclk0"), + PINCTRL_PIN(I2S_MCLK0, "i2s_mclk0"), + PINCTRL_PIN(I2S_D1, "i2s_d1"), + PINCTRL_PIN(I2S_BCLK1, "i2s_bclk1"), + PINCTRL_PIN(I2S_LRCLK1, "i2s_lrclk1"), + PINCTRL_PIN(I2S_MCLK1, "i2s_mclk1"), + PINCTRL_PIN(PCM1_IN, "pcm1_in"), + PINCTRL_PIN(PCM1_CLK, "pcm1_clk"), + PINCTRL_PIN(PCM1_SYNC, "pcm1_sync"), + PINCTRL_PIN(PCM1_OUT, "pcm1_out"), + PINCTRL_PIN(KS_IN0, "ks_in0"), + PINCTRL_PIN(KS_IN1, "ks_in1"), + PINCTRL_PIN(KS_IN2, "ks_in2"), + PINCTRL_PIN(KS_IN3, "ks_in3"), + PINCTRL_PIN(KS_OUT0, "ks_out0"), + PINCTRL_PIN(KS_OUT1, "ks_out1"), + PINCTRL_PIN(KS_OUT2, "ks_out2"), + PINCTRL_PIN(LVDS_OEP, "lvds_oep"), + PINCTRL_PIN(LVDS_OEN, "lvds_oen"), + PINCTRL_PIN(LVDS_ODP, "lvds_odp"), + PINCTRL_PIN(LVDS_ODN, "lvds_odn"), + PINCTRL_PIN(LVDS_OCP, "lvds_ocp"), + PINCTRL_PIN(LVDS_OCN, "lvds_ocn"), + PINCTRL_PIN(LVDS_OBP, "lvds_obp"), + PINCTRL_PIN(LVDS_OBN, "lvds_obn"), + PINCTRL_PIN(LVDS_OAP, "lvds_oap"), + PINCTRL_PIN(LVDS_OAN, "lvds_oan"), + PINCTRL_PIN(LVDS_EEP, "lvds_eep"), + PINCTRL_PIN(LVDS_EEN, "lvds_een"), + PINCTRL_PIN(LVDS_EDP, "lvds_edp"), + PINCTRL_PIN(LVDS_EDN, "lvds_edn"), + PINCTRL_PIN(LVDS_ECP, "lvds_ecp"), + PINCTRL_PIN(LVDS_ECN, "lvds_ecn"), + PINCTRL_PIN(LVDS_EBP, "lvds_ebp"), + PINCTRL_PIN(LVDS_EBN, "lvds_ebn"), + PINCTRL_PIN(LVDS_EAP, "lvds_eap"), + PINCTRL_PIN(LVDS_EAN, "lvds_ean"), + PINCTRL_PIN(LCD0_D18, "lcd0_d18"), + PINCTRL_PIN(LCD0_D2, "lcd0_d2"), + PINCTRL_PIN(DSI_DP3, "dsi_dp3"), + PINCTRL_PIN(DSI_DN3, "dsi_dn3"), + PINCTRL_PIN(DSI_DP1, "dsi_dp1"), + PINCTRL_PIN(DSI_DN1, "dsi_dn1"), + PINCTRL_PIN(DSI_CP, "dsi_cp"), + PINCTRL_PIN(DSI_CN, "dsi_cn"), + PINCTRL_PIN(DSI_DP0, "dsi_dp0"), + PINCTRL_PIN(DSI_DN0, "dsi_dn0"), + PINCTRL_PIN(DSI_DP2, "dsi_dp2"), + PINCTRL_PIN(DSI_DN2, "dsi_dn2"), + PINCTRL_PIN(SD0_D0, "sd0_d0"), + PINCTRL_PIN(SD0_D1, "sd0_d1"), + PINCTRL_PIN(SD0_D2, "sd0_d2"), + PINCTRL_PIN(SD0_D3, "sd0_d3"), + PINCTRL_PIN(SD1_D0, "sd1_d0"), + PINCTRL_PIN(SD1_D1, "sd1_d1"), + PINCTRL_PIN(SD1_D2, "sd1_d2"), + PINCTRL_PIN(SD1_D3, "sd1_d3"), + PINCTRL_PIN(SD0_CMD, "sd0_cmd"), + PINCTRL_PIN(SD0_CLK, "sd0_clk"), + PINCTRL_PIN(SD1_CMD, "sd1_cmd"), + PINCTRL_PIN(SD1_CLK, "sd1_clk"), + PINCTRL_PIN(SPI0_SS, "spi0_ss"), + PINCTRL_PIN(SPI0_MISO, "spi0_miso"), + PINCTRL_PIN(UART0_RX, "uart0_rx"), + PINCTRL_PIN(UART0_TX, "uart0_tx"), + PINCTRL_PIN(UART2_RX, "uart2_rx"), + PINCTRL_PIN(UART2_TX, "uart2_tx"), + PINCTRL_PIN(UART2_RTSB, "uart2_rtsb"), + PINCTRL_PIN(UART2_CTSB, "uart2_ctsb"), + PINCTRL_PIN(UART3_RX, "uart3_rx"), + PINCTRL_PIN(UART3_TX, "uart3_tx"), + PINCTRL_PIN(UART3_RTSB, "uart3_rtsb"), + PINCTRL_PIN(UART3_CTSB, "uart3_ctsb"), + PINCTRL_PIN(I2C0_SCLK, "i2c0_sclk"), + PINCTRL_PIN(I2C0_SDATA, "i2c0_sdata"), + PINCTRL_PIN(I2C1_SCLK, "i2c1_sclk"), + PINCTRL_PIN(I2C1_SDATA, "i2c1_sdata"), + PINCTRL_PIN(I2C2_SCLK, "i2c2_sclk"), + PINCTRL_PIN(I2C2_SDATA, "i2c2_sdata"), + PINCTRL_PIN(CSI_DN0, "csi_dn0"), + PINCTRL_PIN(CSI_DP0, "csi_dp0"), + PINCTRL_PIN(CSI_DN1, "csi_dn1"), + PINCTRL_PIN(CSI_DP1, "csi_dp1"), + PINCTRL_PIN(CSI_CN, "csi_cn"), + PINCTRL_PIN(CSI_CP, "csi_cp"), + PINCTRL_PIN(CSI_DN2, "csi_dn2"), + PINCTRL_PIN(CSI_DP2, "csi_dp2"), + PINCTRL_PIN(CSI_DN3, "csi_dn3"), + PINCTRL_PIN(CSI_DP3, "csi_dp3"), + PINCTRL_PIN(SENSOR0_PCLK, "sensor0_pclk"), + PINCTRL_PIN(SENSOR0_CKOUT, "sensor0_ckout"), + PINCTRL_PIN(DNAND_D0, "dnand_d0"), + PINCTRL_PIN(DNAND_D1, "dnand_d1"), + PINCTRL_PIN(DNAND_D2, "dnand_d2"), + PINCTRL_PIN(DNAND_D3, "dnand_d3"), + PINCTRL_PIN(DNAND_D4, "dnand_d4"), + PINCTRL_PIN(DNAND_D5, "dnand_d5"), + PINCTRL_PIN(DNAND_D6, "dnand_d6"), + PINCTRL_PIN(DNAND_D7, "dnand_d7"), + PINCTRL_PIN(DNAND_WRB, "dnand_wrb"), + PINCTRL_PIN(DNAND_RDB, "dnand_rdb"), + PINCTRL_PIN(DNAND_RDBN, "dnand_rdbn"), + PINCTRL_PIN(DNAND_DQS, "dnand_dqs"), + PINCTRL_PIN(DNAND_DQSN, "dnand_dqsn"), + PINCTRL_PIN(DNAND_RB0, "dnand_rb0"), + PINCTRL_PIN(DNAND_ALE, "dnand_ale"), + PINCTRL_PIN(DNAND_CLE, "dnand_cle"), + PINCTRL_PIN(DNAND_CEB0, "dnand_ceb0"), + PINCTRL_PIN(DNAND_CEB1, "dnand_ceb1"), + PINCTRL_PIN(DNAND_CEB2, "dnand_ceb2"), + PINCTRL_PIN(DNAND_CEB3, "dnand_ceb3"), + PINCTRL_PIN(PORB, "porb"), + PINCTRL_PIN(CLKO_25M, "clko_25m"), + PINCTRL_PIN(BSEL, "bsel"), + PINCTRL_PIN(PKG0, "pkg0"), + PINCTRL_PIN(PKG1, "pkg1"), + PINCTRL_PIN(PKG2, "pkg2"), + PINCTRL_PIN(PKG3, "pkg3"), +}; + +enum s700_pinmux_functions { + S700_MUX_NOR, + S700_MUX_ETH_RGMII, + S700_MUX_ETH_SGMII, + S700_MUX_SPI0, + S700_MUX_SPI1, + S700_MUX_SPI2, + S700_MUX_SPI3, + S700_MUX_SENS0, + S700_MUX_SENS1, + S700_MUX_UART0, + S700_MUX_UART1, + S700_MUX_UART2, + S700_MUX_UART3, + S700_MUX_UART4, + S700_MUX_UART5, + S700_MUX_UART6, + S700_MUX_I2S0, + S700_MUX_I2S1, + S700_MUX_PCM1, + S700_MUX_PCM0, + S700_MUX_KS, + S700_MUX_JTAG, + S700_MUX_PWM0, + S700_MUX_PWM1, + S700_MUX_PWM2, + S700_MUX_PWM3, + S700_MUX_PWM4, + S700_MUX_PWM5, + S700_MUX_P0, + S700_MUX_SD0, + S700_MUX_SD1, + S700_MUX_SD2, + S700_MUX_I2C0, + S700_MUX_I2C1, + S700_MUX_I2C2, + S700_MUX_I2C3, + S700_MUX_DSI, + S700_MUX_LVDS, + S700_MUX_USB30, + S700_MUX_CLKO_25M, + S700_MUX_MIPI_CSI, + S700_MUX_NAND, + S700_MUX_SPDIF, + S700_MUX_SIRQ0, + S700_MUX_SIRQ1, + S700_MUX_SIRQ2, + S700_MUX_BT, + S700_MUX_LCD0, + S700_MUX_RESERVED, +}; + +/* mfp0_31_30 reserved */ + +/* rgmii_txd23 */ +static unsigned int rgmii_txd23_mfp_pads[] = { ETH_TXD2, ETH_TXD3}; +static unsigned int rgmii_txd23_mfp_funcs[] = { S700_MUX_ETH_RGMII, + S700_MUX_I2C1, + S700_MUX_UART3 }; +/* rgmii_rxd2 */ +static unsigned int rgmii_rxd2_mfp_pads[] = { ETH_RXD2 }; +static unsigned int rgmii_rxd2_mfp_funcs[] = { S700_MUX_ETH_RGMII, + S700_MUX_PWM0, + S700_MUX_UART3 }; +/* rgmii_rxd3 */ +static unsigned int rgmii_rxd3_mfp_pads[] = { ETH_RXD3}; +static unsigned int rgmii_rxd3_mfp_funcs[] = { S700_MUX_ETH_RGMII, + S700_MUX_PWM2, + S700_MUX_UART3 }; +/* lcd0_d18 */ +static unsigned int lcd0_d18_mfp_pads[] = { LCD0_D18 }; +static unsigned int lcd0_d18_mfp_funcs[] = { S700_MUX_NOR, + S700_MUX_SENS1, + S700_MUX_PWM2, + S700_MUX_PWM4, + S700_MUX_LCD0 }; +/* rgmii_txd01 */ +static unsigned int rgmii_txd01_mfp_pads[] = { ETH_CRS_DV }; +static unsigned int rgmii_txd01_mfp_funcs[] = { S700_MUX_ETH_RGMII, + S700_MUX_RESERVED, + S700_MUX_SPI2, + S700_MUX_UART4, + S700_MUX_PWM4 }; +/* rgmii_txd0 */ +static unsigned int rgmii_txd0_mfp_pads[] = { ETH_TXD0 }; +static unsigned int rgmii_txd0_mfp_funcs[] = { S700_MUX_ETH_RGMII, + S700_MUX_ETH_SGMII, + S700_MUX_SPI2, + S700_MUX_UART6, + S700_MUX_PWM4 }; +/* rgmii_txd1 */ +static unsigned int rgmii_txd1_mfp_pads[] = { ETH_TXD1 }; +static unsigned int rgmii_txd1_mfp_funcs[] = { S700_MUX_ETH_RGMII, + S700_MUX_ETH_SGMII, + S700_MUX_SPI2, + S700_MUX_UART6, + S700_MUX_PWM5 }; +/* rgmii_txen */ +static unsigned int rgmii_txen_mfp_pads[] = { ETH_TXEN }; +static unsigned int rgmii_txen_mfp_funcs[] = { S700_MUX_ETH_RGMII, + S700_MUX_UART2, + S700_MUX_SPI3, + S700_MUX_PWM0 }; +/* rgmii_rxen */ +static unsigned int rgmii_rxen_mfp_pads[] = { ETH_RXER }; +static unsigned int rgmii_rxen_mfp_funcs[] = { S700_MUX_ETH_RGMII, + S700_MUX_UART2, + S700_MUX_SPI3, + S700_MUX_PWM1 }; +/* mfp0_12_11 reserved */ +/* rgmii_rxd1*/ +static unsigned int rgmii_rxd1_mfp_pads[] = { ETH_RXD1 }; +static unsigned int rgmii_rxd1_mfp_funcs[] = { S700_MUX_ETH_RGMII, + S700_MUX_UART2, + S700_MUX_SPI3, + S700_MUX_PWM2, + S700_MUX_UART5, + S700_MUX_ETH_SGMII }; +/* rgmii_rxd0 */ +static unsigned int rgmii_rxd0_mfp_pads[] = { ETH_RXD0 }; +static unsigned int rgmii_rxd0_mfp_funcs[] = { S700_MUX_ETH_RGMII, + S700_MUX_UART2, + S700_MUX_SPI3, + S700_MUX_PWM3, + S700_MUX_UART5, + S700_MUX_ETH_SGMII }; +/* rgmii_ref_clk */ +static unsigned int rgmii_ref_clk_mfp_pads[] = { ETH_REF_CLK }; +static unsigned int rgmii_ref_clk_mfp_funcs[] = { S700_MUX_ETH_RGMII, + S700_MUX_UART4, + S700_MUX_SPI2, + S700_MUX_RESERVED, + S700_MUX_ETH_SGMII }; +/* i2s_d0 */ +static unsigned int i2s_d0_mfp_pads[] = { I2S_D0 }; +static unsigned int i2s_d0_mfp_funcs[] = { S700_MUX_I2S0, + S700_MUX_NOR }; +/* i2s_pcm1 */ +static unsigned int i2s_pcm1_mfp_pads[] = { I2S_LRCLK0, + I2S_MCLK0 }; +static unsigned int i2s_pcm1_mfp_funcs[] = { S700_MUX_I2S0, + S700_MUX_NOR, + S700_MUX_PCM1, + S700_MUX_BT }; +/* i2s0_pcm0 */ +static unsigned int i2s0_pcm0_mfp_pads[] = { I2S_BCLK0 }; +static unsigned int i2s0_pcm0_mfp_funcs[] = { S700_MUX_I2S0, + S700_MUX_NOR, + S700_MUX_PCM0, + S700_MUX_BT }; +/* i2s1_pcm0 */ +static unsigned int i2s1_pcm0_mfp_pads[] = { I2S_BCLK1, + I2S_LRCLK1, + I2S_MCLK1 }; + +static unsigned int i2s1_pcm0_mfp_funcs[] = { S700_MUX_I2S1, + S700_MUX_NOR, + S700_MUX_PCM0, + S700_MUX_BT }; +/* i2s_d1 */ +static unsigned int i2s_d1_mfp_pads[] = { I2S_D1 }; +static unsigned int i2s_d1_mfp_funcs[] = { S700_MUX_I2S1, + S700_MUX_NOR }; +/* ks_in2 */ +static unsigned int ks_in2_mfp_pads[] = { KS_IN2 }; +static unsigned int ks_in2_mfp_funcs[] = { S700_MUX_KS, + S700_MUX_JTAG, + S700_MUX_NOR, + S700_MUX_BT, + S700_MUX_PWM0, + S700_MUX_SENS1, + S700_MUX_PWM0, + S700_MUX_P0 }; +/* ks_in1 */ +static unsigned int ks_in1_mfp_pads[] = { KS_IN1 }; +static unsigned int ks_in1_mfp_funcs[] = { S700_MUX_KS, + S700_MUX_JTAG, + S700_MUX_NOR, + S700_MUX_BT, + S700_MUX_PWM5, + S700_MUX_SENS1, + S700_MUX_PWM1, + S700_MUX_USB30 }; +/* ks_in0 */ +static unsigned int ks_in0_mfp_pads[] = { KS_IN0 }; +static unsigned int ks_in0_mfp_funcs[] = { S700_MUX_KS, + S700_MUX_JTAG, + S700_MUX_NOR, + S700_MUX_BT, + S700_MUX_PWM4, + S700_MUX_SENS1, + S700_MUX_PWM4, + S700_MUX_P0 }; +/* ks_in3 */ +static unsigned int ks_in3_mfp_pads[] = { KS_IN3 }; +static unsigned int ks_in3_mfp_funcs[] = { S700_MUX_KS, + S700_MUX_JTAG, + S700_MUX_NOR, + S700_MUX_PWM1, + S700_MUX_BT, + S700_MUX_SENS1 }; +/* ks_out0 */ +static unsigned int ks_out0_mfp_pads[] = { KS_OUT0 }; +static unsigned int ks_out0_mfp_funcs[] = { S700_MUX_KS, + S700_MUX_UART5, + S700_MUX_NOR, + S700_MUX_PWM2, + S700_MUX_BT, + S700_MUX_SENS1, + S700_MUX_SD0, + S700_MUX_UART4 }; + +/* ks_out1 */ +static unsigned int ks_out1_mfp_pads[] = { KS_OUT1 }; +static unsigned int ks_out1_mfp_funcs[] = { S700_MUX_KS, + S700_MUX_JTAG, + S700_MUX_NOR, + S700_MUX_PWM3, + S700_MUX_BT, + S700_MUX_SENS1, + S700_MUX_SD0, + S700_MUX_UART4 }; +/* ks_out2 */ +static unsigned int ks_out2_mfp_pads[] = { KS_OUT2 }; +static unsigned int ks_out2_mfp_funcs[] = { S700_MUX_SD0, + S700_MUX_KS, + S700_MUX_NOR, + S700_MUX_PWM2, + S700_MUX_UART5, + S700_MUX_SENS1, + S700_MUX_BT }; +/* lvds_o_pn */ +static unsigned int lvds_o_pn_mfp_pads[] = { LVDS_OEP, + LVDS_OEN, + LVDS_ODP, + LVDS_ODN, + LVDS_OCP, + LVDS_OCN, + LVDS_OBP, + LVDS_OBN, + LVDS_OAP, + LVDS_OAN }; + +static unsigned int lvds_o_pn_mfp_funcs[] = { S700_MUX_LVDS, + S700_MUX_BT, + S700_MUX_LCD0 }; + +/* dsi_dn0 */ +static unsigned int dsi_dn0_mfp_pads[] = { DSI_DN0 }; +static unsigned int dsi_dn0_mfp_funcs[] = { S700_MUX_DSI, + S700_MUX_UART2, + S700_MUX_SPI0 }; +/* dsi_dp2 */ +static unsigned int dsi_dp2_mfp_pads[] = { DSI_DP2 }; +static unsigned int dsi_dp2_mfp_funcs[] = { S700_MUX_DSI, + S700_MUX_UART2, + S700_MUX_SPI0, + S700_MUX_SD1 }; +/* lcd0_d2 */ +static unsigned int lcd0_d2_mfp_pads[] = { LCD0_D2 }; +static unsigned int lcd0_d2_mfp_funcs[] = { S700_MUX_NOR, + S700_MUX_SD0, + S700_MUX_RESERVED, + S700_MUX_PWM3, + S700_MUX_LCD0 }; +/* dsi_dp3 */ +static unsigned int dsi_dp3_mfp_pads[] = { DSI_DP3 }; +static unsigned int dsi_dp3_mfp_funcs[] = { S700_MUX_DSI, + S700_MUX_SD0, + S700_MUX_SD1, + S700_MUX_LCD0 }; +/* dsi_dn3 */ +static unsigned int dsi_dn3_mfp_pads[] = { DSI_DN3 }; +static unsigned int dsi_dn3_mfp_funcs[] = { S700_MUX_DSI, + S700_MUX_SD0, + S700_MUX_SD1, + S700_MUX_LCD0 }; +/* dsi_dp0 */ +static unsigned int dsi_dp0_mfp_pads[] = { DSI_DP0 }; +static unsigned int dsi_dp0_mfp_funcs[] = { S700_MUX_DSI, + S700_MUX_RESERVED, + S700_MUX_SD0, + S700_MUX_UART2, + S700_MUX_SPI0 }; +/* lvds_ee_pn */ +static unsigned int lvds_ee_pn_mfp_pads[] = { LVDS_EEP, + LVDS_EEN }; +static unsigned int lvds_ee_pn_mfp_funcs[] = { S700_MUX_LVDS, + S700_MUX_NOR, + S700_MUX_BT, + S700_MUX_LCD0 }; +/* uart2_rx_tx */ +static unsigned int uart2_rx_tx_mfp_pads[] = { UART2_RX, + UART2_TX }; +static unsigned int uart2_rx_tx_mfp_funcs[] = { S700_MUX_UART2, + S700_MUX_NOR, + S700_MUX_SPI0, + S700_MUX_PCM0 }; +/* spi0_i2c_pcm */ +static unsigned int spi0_i2c_pcm_mfp_pads[] = { SPI0_SS, + SPI0_MISO }; +static unsigned int spi0_i2c_pcm_mfp_funcs[] = { S700_MUX_SPI0, + S700_MUX_NOR, + S700_MUX_I2S1, + S700_MUX_PCM1, + S700_MUX_PCM0, + S700_MUX_I2C2 }; +/* mfp2_31 reserved */ + +/* dsi_dnp1_cp_d2 */ +static unsigned int dsi_dnp1_cp_d2_mfp_pads[] = { DSI_DP1, + DSI_CP, + DSI_CN }; +static unsigned int dsi_dnp1_cp_d2_mfp_funcs[] = { S700_MUX_DSI, + S700_MUX_LCD0, + S700_MUX_RESERVED }; +/* dsi_dnp1_cp_d17 */ +static unsigned int dsi_dnp1_cp_d17_mfp_pads[] = { DSI_DP1, + DSI_CP, + DSI_CN }; + +static unsigned int dsi_dnp1_cp_d17_mfp_funcs[] = { S700_MUX_DSI, + S700_MUX_RESERVED, + S700_MUX_LCD0 }; +/* lvds_e_pn */ +static unsigned int lvds_e_pn_mfp_pads[] = { LVDS_EDP, + LVDS_EDN, + LVDS_ECP, + LVDS_ECN, + LVDS_EBP, + LVDS_EBN, + LVDS_EAP, + LVDS_EAN }; + +static unsigned int lvds_e_pn_mfp_funcs[] = { S700_MUX_LVDS, + S700_MUX_NOR, + S700_MUX_LCD0 }; +/* dsi_dn2 */ +static unsigned int dsi_dn2_mfp_pads[] = { DSI_DN2 }; +static unsigned int dsi_dn2_mfp_funcs[] = { S700_MUX_DSI, + S700_MUX_RESERVED, + S700_MUX_SD1, + S700_MUX_UART2, + S700_MUX_SPI0 }; +/* uart2_rtsb */ +static unsigned int uart2_rtsb_mfp_pads[] = { UART2_RTSB }; +static unsigned int uart2_rtsb_mfp_funcs[] = { S700_MUX_UART2, + S700_MUX_UART0 }; + +/* uart2_ctsb */ +static unsigned int uart2_ctsb_mfp_pads[] = { UART2_CTSB }; +static unsigned int uart2_ctsb_mfp_funcs[] = { S700_MUX_UART2, + S700_MUX_UART0 }; +/* uart3_rtsb */ +static unsigned int uart3_rtsb_mfp_pads[] = { UART3_RTSB }; +static unsigned int uart3_rtsb_mfp_funcs[] = { S700_MUX_UART3, + S700_MUX_UART5 }; + +/* uart3_ctsb */ +static unsigned int uart3_ctsb_mfp_pads[] = { UART3_CTSB }; +static unsigned int uart3_ctsb_mfp_funcs[] = { S700_MUX_UART3, + S700_MUX_UART5 }; +/* sd0_d0 */ +static unsigned int sd0_d0_mfp_pads[] = { SD0_D0 }; +static unsigned int sd0_d0_mfp_funcs[] = { S700_MUX_SD0, + S700_MUX_NOR, + S700_MUX_RESERVED, + S700_MUX_JTAG, + S700_MUX_UART2, + S700_MUX_UART5 }; +/* sd0_d1 */ +static unsigned int sd0_d1_mfp_pads[] = { SD0_D1 }; +static unsigned int sd0_d1_mfp_funcs[] = { S700_MUX_SD0, + S700_MUX_NOR, + S700_MUX_RESERVED, + S700_MUX_RESERVED, + S700_MUX_UART2, + S700_MUX_UART5 }; +/* sd0_d2_d3 */ +static unsigned int sd0_d2_d3_mfp_pads[] = { SD0_D2, + SD0_D3 }; +static unsigned int sd0_d2_d3_mfp_funcs[] = { S700_MUX_SD0, + S700_MUX_NOR, + S700_MUX_RESERVED, + S700_MUX_JTAG, + S700_MUX_UART2, + S700_MUX_UART1 }; + +/* sd1_d0_d3 */ +static unsigned int sd1_d0_d3_mfp_pads[] = { SD1_D0, + SD1_D1, + SD1_D2, + SD1_D3 }; +static unsigned int sd1_d0_d3_mfp_funcs[] = { S700_MUX_SD0, + S700_MUX_NOR, + S700_MUX_RESERVED, + S700_MUX_SD1 }; + +/* sd0_cmd */ +static unsigned int sd0_cmd_mfp_pads[] = { SD0_CMD }; +static unsigned int sd0_cmd_mfp_funcs[] = { S700_MUX_SD0, + S700_MUX_NOR, + S700_MUX_RESERVED, + S700_MUX_JTAG }; +/* sd0_clk */ +static unsigned int sd0_clk_mfp_pads[] = { SD0_CLK }; +static unsigned int sd0_clk_mfp_funcs[] = { S700_MUX_SD0, + S700_MUX_RESERVED, + S700_MUX_JTAG }; +/* sd1_cmd */ +static unsigned int sd1_cmd_mfp_pads[] = { SD1_CMD }; +static unsigned int sd1_cmd_mfp_funcs[] = { S700_MUX_SD1, + S700_MUX_NOR }; +/* uart0_rx */ +static unsigned int uart0_rx_mfp_pads[] = { UART0_RX }; +static unsigned int uart0_rx_mfp_funcs[] = { S700_MUX_UART0, + S700_MUX_UART2, + S700_MUX_SPI1, + S700_MUX_I2C0, + S700_MUX_PCM1, + S700_MUX_I2S1 }; +/* dnand_data_wr1 reserved */ + +/* clko_25m */ +static unsigned int clko_25m_mfp_pads[] = { CLKO_25M }; +static unsigned int clko_25m_mfp_funcs[] = { S700_MUX_RESERVED, + S700_MUX_CLKO_25M }; +/* csi_cn_cp */ +static unsigned int csi_cn_cp_mfp_pads[] = { CSI_CN, + CSI_CP }; +static unsigned int csi_cn_cp_mfp_funcs[] = { S700_MUX_MIPI_CSI, + S700_MUX_SENS0 }; +/* dnand_acle_ce07_24 reserved */ + +/* sens0_ckout */ +static unsigned int sens0_ckout_mfp_pads[] = { SENSOR0_CKOUT }; +static unsigned int sens0_ckout_mfp_funcs[] = { S700_MUX_SENS0, + S700_MUX_NOR, + S700_MUX_SENS1, + S700_MUX_PWM1 }; +/* uart0_tx */ +static unsigned int uart0_tx_mfp_pads[] = { UART0_TX }; +static unsigned int uart0_tx_mfp_funcs[] = { S700_MUX_UART0, + S700_MUX_UART2, + S700_MUX_SPI1, + S700_MUX_I2C0, + S700_MUX_SPDIF, + S700_MUX_PCM1, + S700_MUX_I2S1 }; +/* i2c0_mfp */ +static unsigned int i2c0_mfp_pads[] = { I2C0_SCLK, + I2C0_SDATA }; +static unsigned int i2c0_mfp_funcs[] = { S700_MUX_I2C0, + S700_MUX_UART2, + S700_MUX_I2C1, + S700_MUX_UART1, + S700_MUX_SPI1 }; +/* csi_dn_dp */ +static unsigned int csi_dn_dp_mfp_pads[] = { CSI_DN0, + CSI_DN1, + CSI_DN2, + CSI_DN3, + CSI_DP0, + CSI_DP1, + CSI_DP2, + CSI_DP3 }; +static unsigned int csi_dn_dp_mfp_funcs[] = { S700_MUX_MIPI_CSI, + S700_MUX_SENS0 }; +/* sen0_pclk */ +static unsigned int sen0_pclk_mfp_pads[] = { SENSOR0_PCLK }; +static unsigned int sen0_pclk_mfp_funcs[] = { S700_MUX_SENS0, + S700_MUX_NOR, + S700_MUX_PWM0 }; +/* pcm1_in */ +static unsigned int pcm1_in_mfp_pads[] = { PCM1_IN }; +static unsigned int pcm1_in_mfp_funcs[] = { S700_MUX_PCM1, + S700_MUX_SENS1, + S700_MUX_BT, + S700_MUX_PWM4 }; +/* pcm1_clk */ +static unsigned int pcm1_clk_mfp_pads[] = { PCM1_CLK }; +static unsigned int pcm1_clk_mfp_funcs[] = { S700_MUX_PCM1, + S700_MUX_SENS1, + S700_MUX_BT, + S700_MUX_PWM5 }; +/* pcm1_sync */ +static unsigned int pcm1_sync_mfp_pads[] = { PCM1_SYNC }; +static unsigned int pcm1_sync_mfp_funcs[] = { S700_MUX_PCM1, + S700_MUX_SENS1, + S700_MUX_BT, + S700_MUX_I2C3 }; +/* pcm1_out */ +static unsigned int pcm1_out_mfp_pads[] = { PCM1_OUT }; +static unsigned int pcm1_out_mfp_funcs[] = { S700_MUX_PCM1, + S700_MUX_SENS1, + S700_MUX_BT, + S700_MUX_I2C3 }; +/* dnand_data_wr */ +static unsigned int dnand_data_wr_mfp_pads[] = { DNAND_D0, + DNAND_D1, + DNAND_D2, + DNAND_D3, + DNAND_D4, + DNAND_D5, + DNAND_D6, + DNAND_D7, + DNAND_RDB, + DNAND_RDBN }; +static unsigned int dnand_data_wr_mfp_funcs[] = { S700_MUX_NAND, + S700_MUX_SD2 }; +/* dnand_acle_ce0 */ +static unsigned int dnand_acle_ce0_mfp_pads[] = { DNAND_ALE, + DNAND_CLE, + DNAND_CEB0, + DNAND_CEB1 }; +static unsigned int dnand_acle_ce0_mfp_funcs[] = { S700_MUX_NAND, + S700_MUX_SPI2 }; + +/* nand_ceb2 */ +static unsigned int nand_ceb2_mfp_pads[] = { DNAND_CEB2 }; +static unsigned int nand_ceb2_mfp_funcs[] = { S700_MUX_NAND, + S700_MUX_PWM5 }; +/* nand_ceb3 */ +static unsigned int nand_ceb3_mfp_pads[] = { DNAND_CEB3 }; +static unsigned int nand_ceb3_mfp_funcs[] = { S700_MUX_NAND, + S700_MUX_PWM4 }; +/*****End MFP group data****************************/ + +/*****PADDRV group data****************************/ + +/*PAD_DRV0*/ +static unsigned int sirq_drv_pads[] = { SIRQ0, + SIRQ1, + SIRQ2 }; + +static unsigned int rgmii_txd23_drv_pads[] = { ETH_TXD2, + ETH_TXD3 }; + +static unsigned int rgmii_rxd23_drv_pads[] = { ETH_RXD2, + ETH_RXD3 }; + +static unsigned int rgmii_txd01_txen_drv_pads[] = { ETH_TXD0, + ETH_TXD1, + ETH_TXEN }; + +static unsigned int rgmii_rxer_drv_pads[] = { ETH_RXER }; + +static unsigned int rgmii_crs_drv_pads[] = { ETH_CRS_DV }; + +static unsigned int rgmii_rxd10_drv_pads[] = { ETH_RXD0, + ETH_RXD1 }; + +static unsigned int rgmii_ref_clk_drv_pads[] = { ETH_REF_CLK }; + +static unsigned int smi_mdc_mdio_drv_pads[] = { ETH_MDC, + ETH_MDIO }; + +static unsigned int i2s_d0_drv_pads[] = { I2S_D0 }; + +static unsigned int i2s_bclk0_drv_pads[] = { I2S_BCLK0 }; + +static unsigned int i2s3_drv_pads[] = { I2S_LRCLK0, + I2S_MCLK0, + I2S_D1 }; + +static unsigned int i2s13_drv_pads[] = { I2S_BCLK1, + I2S_LRCLK1, + I2S_MCLK1 }; + +static unsigned int pcm1_drv_pads[] = { PCM1_IN, + PCM1_CLK, + PCM1_SYNC, + PCM1_OUT }; + +static unsigned int ks_in_drv_pads[] = { KS_IN0, + KS_IN1, + KS_IN2, + KS_IN3 }; + +/*PAD_DRV1*/ +static unsigned int ks_out_drv_pads[] = { KS_OUT0, + KS_OUT1, + KS_OUT2 }; + +static unsigned int lvds_all_drv_pads[] = { LVDS_OEP, + LVDS_OEN, + LVDS_ODP, + LVDS_ODN, + LVDS_OCP, + LVDS_OCN, + LVDS_OBP, + LVDS_OBN, + LVDS_OAP, + LVDS_OAN, + LVDS_EEP, + LVDS_EEN, + LVDS_EDP, + LVDS_EDN, + LVDS_ECP, + LVDS_ECN, + LVDS_EBP, + LVDS_EBN, + LVDS_EAP, + LVDS_EAN }; + +static unsigned int lcd_d18_d2_drv_pads[] = { LCD0_D18, + LCD0_D2 }; + +static unsigned int dsi_all_drv_pads[] = { DSI_DP0, + DSI_DN0, + DSI_DP2, + DSI_DN2, + DSI_DP3, + DSI_DN3, + DSI_DP1, + DSI_DN1, + DSI_CP, + DSI_CN }; + +static unsigned int sd0_d0_d3_drv_pads[] = { SD0_D0, + SD0_D1, + SD0_D2, + SD0_D3 }; + +static unsigned int sd0_cmd_drv_pads[] = { SD0_CMD }; + +static unsigned int sd0_clk_drv_pads[] = { SD0_CLK }; + +static unsigned int spi0_all_drv_pads[] = { SPI0_SS, + SPI0_MISO }; + +/*PAD_DRV2*/ +static unsigned int uart0_rx_drv_pads[] = { UART0_RX }; + +static unsigned int uart0_tx_drv_pads[] = { UART0_TX }; + +static unsigned int uart2_all_drv_pads[] = { UART2_RX, + UART2_TX, + UART2_RTSB, + UART2_CTSB }; + +static unsigned int i2c0_all_drv_pads[] = { I2C0_SCLK, + I2C0_SDATA }; + +static unsigned int i2c12_all_drv_pads[] = { I2C1_SCLK, + I2C1_SDATA, + I2C2_SCLK, + I2C2_SDATA }; + +static unsigned int sens0_pclk_drv_pads[] = { SENSOR0_PCLK }; + +static unsigned int sens0_ckout_drv_pads[] = { SENSOR0_CKOUT }; + +static unsigned int uart3_all_drv_pads[] = { UART3_RX, + UART3_TX, + UART3_RTSB, + UART3_CTSB }; + +/* all pinctrl groups of S700 board */ +static const struct owl_pingroup s700_groups[] = { + MUX_PG(rgmii_txd23_mfp, 0, 28, 2), + MUX_PG(rgmii_rxd2_mfp, 0, 26, 2), + MUX_PG(rgmii_rxd3_mfp, 0, 26, 2), + MUX_PG(lcd0_d18_mfp, 0, 23, 3), + MUX_PG(rgmii_txd01_mfp, 0, 20, 3), + MUX_PG(rgmii_txd0_mfp, 0, 16, 3), + MUX_PG(rgmii_txd1_mfp, 0, 16, 3), + MUX_PG(rgmii_txen_mfp, 0, 13, 3), + MUX_PG(rgmii_rxen_mfp, 0, 13, 3), + MUX_PG(rgmii_rxd1_mfp, 0, 8, 3), + MUX_PG(rgmii_rxd0_mfp, 0, 8, 3), + MUX_PG(rgmii_ref_clk_mfp, 0, 6, 2), + MUX_PG(i2s_d0_mfp, 0, 5, 1), + MUX_PG(i2s_pcm1_mfp, 0, 3, 2), + MUX_PG(i2s0_pcm0_mfp, 0, 1, 2), + MUX_PG(i2s1_pcm0_mfp, 0, 1, 2), + MUX_PG(i2s_d1_mfp, 0, 0, 1), + MUX_PG(ks_in2_mfp, 1, 29, 3), + MUX_PG(ks_in1_mfp, 1, 29, 3), + MUX_PG(ks_in0_mfp, 1, 29, 3), + MUX_PG(ks_in3_mfp, 1, 26, 3), + MUX_PG(ks_out0_mfp, 1, 26, 3), + MUX_PG(ks_out1_mfp, 1, 26, 3), + MUX_PG(ks_out2_mfp, 1, 23, 3), + MUX_PG(lvds_o_pn_mfp, 1, 21, 2), + MUX_PG(dsi_dn0_mfp, 1, 19, 2), + MUX_PG(dsi_dp2_mfp, 1, 17, 2), + MUX_PG(lcd0_d2_mfp, 1, 14, 3), + MUX_PG(dsi_dp3_mfp, 1, 12, 2), + MUX_PG(dsi_dn3_mfp, 1, 10, 2), + MUX_PG(dsi_dp0_mfp, 1, 7, 3), + MUX_PG(lvds_ee_pn_mfp, 1, 5, 2), + MUX_PG(uart2_rx_tx_mfp, 1, 3, 2), + MUX_PG(spi0_i2c_pcm_mfp, 1, 0, 3), + MUX_PG(dsi_dnp1_cp_d2_mfp, 2, 29, 2), + MUX_PG(dsi_dnp1_cp_d17_mfp, 2, 29, 2), + MUX_PG(lvds_e_pn_mfp, 2, 27, 2), + MUX_PG(dsi_dn2_mfp, 2, 24, 3), + MUX_PG(uart2_rtsb_mfp, 2, 23, 1), + MUX_PG(uart2_ctsb_mfp, 2, 22, 1), + MUX_PG(uart3_rtsb_mfp, 2, 21, 1), + MUX_PG(uart3_ctsb_mfp, 2, 20, 1), + MUX_PG(sd0_d0_mfp, 2, 17, 3), + MUX_PG(sd0_d1_mfp, 2, 14, 3), + MUX_PG(sd0_d2_d3_mfp, 2, 11, 3), + MUX_PG(sd1_d0_d3_mfp, 2, 9, 2), + MUX_PG(sd0_cmd_mfp, 2, 7, 2), + MUX_PG(sd0_clk_mfp, 2, 5, 2), + MUX_PG(sd1_cmd_mfp, 2, 3, 2), + MUX_PG(uart0_rx_mfp, 2, 0, 3), + MUX_PG(clko_25m_mfp, 3, 30, 1), + MUX_PG(csi_cn_cp_mfp, 3, 28, 2), + MUX_PG(sens0_ckout_mfp, 3, 22, 2), + MUX_PG(uart0_tx_mfp, 3, 19, 3), + MUX_PG(i2c0_mfp, 3, 16, 3), + MUX_PG(csi_dn_dp_mfp, 3, 14, 2), + MUX_PG(sen0_pclk_mfp, 3, 12, 2), + MUX_PG(pcm1_in_mfp, 3, 10, 2), + MUX_PG(pcm1_clk_mfp, 3, 8, 2), + MUX_PG(pcm1_sync_mfp, 3, 6, 2), + MUX_PG(pcm1_out_mfp, 3, 4, 2), + MUX_PG(dnand_data_wr_mfp, 3, 3, 1), + MUX_PG(dnand_acle_ce0_mfp, 3, 2, 1), + MUX_PG(nand_ceb2_mfp, 3, 0, 2), + MUX_PG(nand_ceb3_mfp, 3, 0, 2), + + DRV_PG(sirq_drv, 0, 28, 2), + DRV_PG(rgmii_txd23_drv, 0, 26, 2), + DRV_PG(rgmii_rxd23_drv, 0, 24, 2), + DRV_PG(rgmii_txd01_txen_drv, 0, 22, 2), + DRV_PG(rgmii_rxer_drv, 0, 20, 2), + DRV_PG(rgmii_crs_drv, 0, 18, 2), + DRV_PG(rgmii_rxd10_drv, 0, 16, 2), + DRV_PG(rgmii_ref_clk_drv, 0, 14, 2), + DRV_PG(smi_mdc_mdio_drv, 0, 12, 2), + DRV_PG(i2s_d0_drv, 0, 10, 2), + DRV_PG(i2s_bclk0_drv, 0, 8, 2), + DRV_PG(i2s3_drv, 0, 6, 2), + DRV_PG(i2s13_drv, 0, 4, 2), + DRV_PG(pcm1_drv, 0, 2, 2), + DRV_PG(ks_in_drv, 0, 0, 2), + DRV_PG(ks_out_drv, 1, 30, 2), + DRV_PG(lvds_all_drv, 1, 28, 2), + DRV_PG(lcd_d18_d2_drv, 1, 26, 2), + DRV_PG(dsi_all_drv, 1, 24, 2), + DRV_PG(sd0_d0_d3_drv, 1, 22, 2), + DRV_PG(sd0_cmd_drv, 1, 18, 2), + DRV_PG(sd0_clk_drv, 1, 16, 2), + DRV_PG(spi0_all_drv, 1, 10, 2), + DRV_PG(uart0_rx_drv, 2, 30, 2), + DRV_PG(uart0_tx_drv, 2, 28, 2), + DRV_PG(uart2_all_drv, 2, 26, 2), + DRV_PG(i2c0_all_drv, 2, 23, 2), + DRV_PG(i2c12_all_drv, 2, 21, 2), + DRV_PG(sens0_pclk_drv, 2, 18, 2), + DRV_PG(sens0_ckout_drv, 2, 12, 2), + DRV_PG(uart3_all_drv, 2, 2, 2), +}; + +static const char * const nor_groups[] = { + "lcd0_d18", + "i2s_d0", + "i2s0_pcm0", + "i2s1_pcm0", + "i2s_d1", + "ks_in2", + "ks_in1", + "ks_in0", + "ks_in3", + "ks_out0", + "ks_out1", + "ks_out2", + "lcd0_d2", + "lvds_ee_pn", + "uart2_rx_tx", + "spi0_i2c_pcm", + "lvds_e_pn", + "sd0_d0", + "sd0_d1", + "sd0_d2_d3", + "sd1_d0_d3", + "sd0_cmd", + "sd1_cmd", + "sens0_ckout", + "sen0_pclk", +}; + +static const char * const eth_rmii_groups[] = { + "rgmii_txd23", + "rgmii_rxd2", + "rgmii_rxd3", + "rgmii_txd01", + "rgmii_txd0", + "rgmii_txd1", + "rgmii_txen", + "rgmii_rxen", + "rgmii_rxd1", + "rgmii_rxd0", + "rgmii_ref_clk", + "eth_smi_dummy", +}; + +static const char * const eth_smii_groups[] = { + "rgmii_txd0", + "rgmii_txd1", + "rgmii_rxd0", + "rgmii_rxd1", + "rgmii_ref_clk", + "eth_smi_dummy", +}; + +static const char * const spi0_groups[] = { + "dsi_dn0", + "dsi_dp2", + "dsi_dp0", + "uart2_rx_tx", + "spi0_i2c_pcm", + "dsi_dn2", +}; + +static const char * const spi1_groups[] = { + "uart0_rx", + "uart0_tx", + "i2c0_mfp", +}; + +static const char * const spi2_groups[] = { + "rgmii_txd01", + "rgmii_txd0", + "rgmii_txd1", + "rgmii_ref_clk", + "dnand_acle_ce0", +}; + +static const char * const spi3_groups[] = { + "rgmii_txen", + "rgmii_rxen", + "rgmii_rxd1", + "rgmii_rxd0", +}; + +static const char * const sens0_groups[] = { + "csi_cn_cp", + "sens0_ckout", + "csi_dn_dp", + "sen0_pclk", +}; + +static const char * const sens1_groups[] = { + "lcd0_d18", + "ks_in2", + "ks_in1", + "ks_in0", + "ks_in3", + "ks_out0", + "ks_out1", + "ks_out2", + "sens0_ckout", + "pcm1_in", + "pcm1_clk", + "pcm1_sync", + "pcm1_out", +}; + +static const char * const uart0_groups[] = { + "uart2_rtsb", + "uart2_ctsb", + "uart0_rx", + "uart0_tx", +}; + +static const char * const uart1_groups[] = { + "sd0_d2_d3", + "i2c0_mfp", +}; + +static const char * const uart2_groups[] = { + "rgmii_txen", + "rgmii_rxen", + "rgmii_rxd1", + "rgmii_rxd0", + "dsi_dn0", + "dsi_dp2", + "dsi_dp0", + "uart2_rx_tx", + "dsi_dn2", + "uart2_rtsb", + "uart2_ctsb", + "sd0_d0", + "sd0_d1", + "sd0_d2_d3", + "uart0_rx", + "uart0_tx", + "i2c0_mfp", + "uart2_dummy" +}; + +static const char * const uart3_groups[] = { + "rgmii_txd23", + "rgmii_rxd2", + "rgmii_rxd3", + "uart3_rtsb", + "uart3_ctsb", + "uart3_dummy" +}; + +static const char * const uart4_groups[] = { + "rgmii_txd01", + "rgmii_ref_clk", + "ks_out0", + "ks_out1", +}; + +static const char * const uart5_groups[] = { + "rgmii_rxd1", + "rgmii_rxd0", + "ks_out0", + "ks_out2", + "uart3_rtsb", + "uart3_ctsb", + "sd0_d0", + "sd0_d1", +}; + +static const char * const uart6_groups[] = { + "rgmii_txd0", + "rgmii_txd1", +}; + +static const char * const i2s0_groups[] = { + "i2s_d0", + "i2s_pcm1", + "i2s0_pcm0", +}; + +static const char * const i2s1_groups[] = { + "i2s1_pcm0", + "i2s_d1", + "i2s1_dummy", + "spi0_i2c_pcm", + "uart0_rx", + "uart0_tx", +}; + +static const char * const pcm1_groups[] = { + "i2s_pcm1", + "spi0_i2c_pcm", + "uart0_rx", + "uart0_tx", + "pcm1_in", + "pcm1_clk", + "pcm1_sync", + "pcm1_out", +}; + +static const char * const pcm0_groups[] = { + "i2s0_pcm0", + "i2s1_pcm0", + "uart2_rx_tx", + "spi0_i2c_pcm", +}; + +static const char * const ks_groups[] = { + "ks_in2", + "ks_in1", + "ks_in0", + "ks_in3", + "ks_out0", + "ks_out1", + "ks_out2", +}; + +static const char * const jtag_groups[] = { + "ks_in2", + "ks_in1", + "ks_in0", + "ks_in3", + "ks_out1", + "sd0_d0", + "sd0_d2_d3", + "sd0_cmd", + "sd0_clk", +}; + +static const char * const pwm0_groups[] = { + "rgmii_rxd2", + "rgmii_txen", + "ks_in2", + "sen0_pclk", +}; + +static const char * const pwm1_groups[] = { + "rgmii_rxen", + "ks_in1", + "ks_in3", + "sens0_ckout", +}; + +static const char * const pwm2_groups[] = { + "lcd0_d18", + "rgmii_rxd3", + "rgmii_rxd1", + "ks_out0", + "ks_out2", +}; + +static const char * const pwm3_groups[] = { + "rgmii_rxd0", + "ks_out1", + "lcd0_d2", +}; + +static const char * const pwm4_groups[] = { + "lcd0_d18", + "rgmii_txd01", + "rgmii_txd0", + "ks_in0", + "pcm1_in", + "nand_ceb3", +}; + +static const char * const pwm5_groups[] = { + "rgmii_txd1", + "ks_in1", + "pcm1_clk", + "nand_ceb2", +}; + +static const char * const p0_groups[] = { + "ks_in2", + "ks_in0", +}; + +static const char * const sd0_groups[] = { + "ks_out0", + "ks_out1", + "ks_out2", + "lcd0_d2", + "dsi_dp3", + "dsi_dp0", + "sd0_d0", + "sd0_d1", + "sd0_d2_d3", + "sd1_d0_d3", + "sd0_cmd", + "sd0_clk", +}; + +static const char * const sd1_groups[] = { + "dsi_dp2", + "mfp1_16_14", + "lcd0_d2", + "mfp1_16_14_d17", + "dsi_dp3", + "dsi_dn3", + "dsi_dnp1_cp_d2", + "dsi_dnp1_cp_d17", + "dsi_dn2", + "sd1_d0_d3", + "sd1_cmd", + "sd1_dummy", +}; + +static const char * const sd2_groups[] = { + "dnand_data_wr", +}; + +static const char * const i2c0_groups[] = { + "uart0_rx", + "uart0_tx", + "i2c0_mfp", +}; + +static const char * const i2c1_groups[] = { + "i2c0_mfp", + "i2c1_dummy" +}; + +static const char * const i2c2_groups[] = { + "i2c2_dummy" +}; + +static const char * const i2c3_groups[] = { + "uart2_rx_tx", + "pcm1_sync", + "pcm1_out", +}; + +static const char * const lvds_groups[] = { + "lvds_o_pn", + "lvds_ee_pn", + "lvds_e_pn", +}; + +static const char * const bt_groups[] = { + "i2s_pcm1", + "i2s0_pcm0", + "i2s1_pcm0", + "ks_in2", + "ks_in1", + "ks_in0", + "ks_in3", + "ks_out0", + "ks_out1", + "ks_out2", + "lvds_o_pn", + "lvds_ee_pn", + "pcm1_in", + "pcm1_clk", + "pcm1_sync", + "pcm1_out", +}; + +static const char * const lcd0_groups[] = { + "lcd0_d18", + "lcd0_d2", + "mfp1_16_14_d17", + "lvds_o_pn", + "dsi_dp3", + "dsi_dn3", + "lvds_ee_pn", + "dsi_dnp1_cp_d2", + "dsi_dnp1_cp_d17", + "lvds_e_pn", +}; + + +static const char * const usb30_groups[] = { + "ks_in1", +}; + +static const char * const clko_25m_groups[] = { + "clko_25m", +}; + +static const char * const mipi_csi_groups[] = { + "csi_cn_cp", + "csi_dn_dp", +}; + +static const char * const dsi_groups[] = { + "dsi_dn0", + "dsi_dp2", + "dsi_dp3", + "dsi_dn3", + "dsi_dp0", + "dsi_dnp1_cp_d2", + "dsi_dnp1_cp_d17", + "dsi_dn2", + "dsi_dummy", +}; + +static const char * const nand_groups[] = { + "dnand_data_wr", + "dnand_acle_ce0", + "nand_ceb2", + "nand_ceb3", + "nand_dummy", +}; + +static const char * const spdif_groups[] = { + "uart0_tx", +}; + +static const char * const sirq0_groups[] = { + "sirq0_dummy", +}; + +static const char * const sirq1_groups[] = { + "sirq1_dummy", +}; + +static const char * const sirq2_groups[] = { + "sirq2_dummy", +}; + +static const struct owl_pinmux_func s700_functions[] = { + [S700_MUX_NOR] = FUNCTION(nor), + [S700_MUX_ETH_RGMII] = FUNCTION(eth_rmii), + [S700_MUX_ETH_SGMII] = FUNCTION(eth_smii), + [S700_MUX_SPI0] = FUNCTION(spi0), + [S700_MUX_SPI1] = FUNCTION(spi1), + [S700_MUX_SPI2] = FUNCTION(spi2), + [S700_MUX_SPI3] = FUNCTION(spi3), + [S700_MUX_SENS0] = FUNCTION(sens0), + [S700_MUX_SENS1] = FUNCTION(sens1), + [S700_MUX_UART0] = FUNCTION(uart0), + [S700_MUX_UART1] = FUNCTION(uart1), + [S700_MUX_UART2] = FUNCTION(uart2), + [S700_MUX_UART3] = FUNCTION(uart3), + [S700_MUX_UART4] = FUNCTION(uart4), + [S700_MUX_UART5] = FUNCTION(uart5), + [S700_MUX_UART6] = FUNCTION(uart6), + [S700_MUX_I2S0] = FUNCTION(i2s0), + [S700_MUX_I2S1] = FUNCTION(i2s1), + [S700_MUX_PCM1] = FUNCTION(pcm1), + [S700_MUX_PCM0] = FUNCTION(pcm0), + [S700_MUX_KS] = FUNCTION(ks), + [S700_MUX_JTAG] = FUNCTION(jtag), + [S700_MUX_PWM0] = FUNCTION(pwm0), + [S700_MUX_PWM1] = FUNCTION(pwm1), + [S700_MUX_PWM2] = FUNCTION(pwm2), + [S700_MUX_PWM3] = FUNCTION(pwm3), + [S700_MUX_PWM4] = FUNCTION(pwm4), + [S700_MUX_PWM5] = FUNCTION(pwm5), + [S700_MUX_P0] = FUNCTION(p0), + [S700_MUX_SD0] = FUNCTION(sd0), + [S700_MUX_SD1] = FUNCTION(sd1), + [S700_MUX_SD2] = FUNCTION(sd2), + [S700_MUX_I2C0] = FUNCTION(i2c0), + [S700_MUX_I2C1] = FUNCTION(i2c1), + [S700_MUX_I2C2] = FUNCTION(i2c2), + [S700_MUX_I2C3] = FUNCTION(i2c3), + [S700_MUX_DSI] = FUNCTION(dsi), + [S700_MUX_LVDS] = FUNCTION(lvds), + [S700_MUX_USB30] = FUNCTION(usb30), + [S700_MUX_CLKO_25M] = FUNCTION(clko_25m), + [S700_MUX_MIPI_CSI] = FUNCTION(mipi_csi), + [S700_MUX_DSI] = FUNCTION(dsi), + [S700_MUX_NAND] = FUNCTION(nand), + [S700_MUX_SPDIF] = FUNCTION(spdif), + [S700_MUX_SIRQ0] = FUNCTION(sirq0), + [S700_MUX_SIRQ1] = FUNCTION(sirq1), + [S700_MUX_SIRQ2] = FUNCTION(sirq2), + [S700_MUX_BT] = FUNCTION(bt), + [S700_MUX_LCD0] = FUNCTION(lcd0), +}; + +/* PAD_ST0 */ +static PAD_ST_CONF(UART2_TX, 0, 31, 1); +static PAD_ST_CONF(I2C0_SDATA, 0, 30, 1); +static PAD_ST_CONF(UART0_RX, 0, 29, 1); +static PAD_ST_CONF(I2S_MCLK1, 0, 23, 1); +static PAD_ST_CONF(ETH_REF_CLK, 0, 22, 1); +static PAD_ST_CONF(ETH_TXEN, 0, 21, 1); +static PAD_ST_CONF(ETH_TXD0, 0, 20, 1); +static PAD_ST_CONF(I2S_LRCLK1, 0, 19, 1); +static PAD_ST_CONF(DSI_DP0, 0, 16, 1); +static PAD_ST_CONF(DSI_DN0, 0, 15, 1); +static PAD_ST_CONF(UART0_TX, 0, 14, 1); +static PAD_ST_CONF(SD0_CLK, 0, 12, 1); +static PAD_ST_CONF(KS_IN0, 0, 11, 1); +static PAD_ST_CONF(SENSOR0_PCLK, 0, 9, 1); +static PAD_ST_CONF(I2C0_SCLK, 0, 7, 1); +static PAD_ST_CONF(KS_OUT0, 0, 6, 1); +static PAD_ST_CONF(KS_OUT1, 0, 5, 1); +static PAD_ST_CONF(KS_OUT2, 0, 4, 1); +static PAD_ST_CONF(ETH_TXD3, 0, 3, 1); +static PAD_ST_CONF(ETH_TXD2, 0, 2, 1); + +/* PAD_ST1 */ +static PAD_ST_CONF(DSI_DP2, 1, 31, 1); +static PAD_ST_CONF(DSI_DN2, 1, 30, 1); +static PAD_ST_CONF(I2S_LRCLK0, 1, 29, 1); +static PAD_ST_CONF(UART3_CTSB, 1, 27, 1); +static PAD_ST_CONF(UART3_RTSB, 1, 26, 1); +static PAD_ST_CONF(UART3_RX, 1, 25, 1); +static PAD_ST_CONF(UART2_RTSB, 1, 24, 1); +static PAD_ST_CONF(UART2_CTSB, 1, 23, 1); +static PAD_ST_CONF(UART2_RX, 1, 22, 1); +static PAD_ST_CONF(ETH_RXD0, 1, 21, 1); +static PAD_ST_CONF(ETH_RXD1, 1, 20, 1); +static PAD_ST_CONF(ETH_CRS_DV, 1, 19, 1); +static PAD_ST_CONF(ETH_RXER, 1, 18, 1); +static PAD_ST_CONF(ETH_TXD1, 1, 17, 1); +static PAD_ST_CONF(LVDS_OAP, 1, 12, 1); +static PAD_ST_CONF(PCM1_CLK, 1, 11, 1); +static PAD_ST_CONF(PCM1_IN, 1, 10, 1); +static PAD_ST_CONF(PCM1_SYNC, 1, 9, 1); +static PAD_ST_CONF(I2C1_SCLK, 1, 8, 1); +static PAD_ST_CONF(I2C1_SDATA, 1, 7, 1); +static PAD_ST_CONF(I2C2_SCLK, 1, 6, 1); +static PAD_ST_CONF(I2C2_SDATA, 1, 5, 1); + +static PAD_ST_CONF(SPI0_MISO, 1, 3, 1); +static PAD_ST_CONF(SPI0_SS, 1, 2, 1); +static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1); +static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1); + +/* PAD_PULLCTL0 */ +static PAD_PULLCTL_CONF(PCM1_SYNC, 0, 30, 1); +static PAD_PULLCTL_CONF(PCM1_OUT, 0, 29, 1); +static PAD_PULLCTL_CONF(KS_OUT2, 0, 28, 1); +static PAD_PULLCTL_CONF(LCD0_D2, 0, 27, 1); +static PAD_PULLCTL_CONF(DSI_DN3, 0, 26, 1); +static PAD_PULLCTL_CONF(ETH_RXER, 0, 16, 1); +static PAD_PULLCTL_CONF(SIRQ0, 0, 14, 2); +static PAD_PULLCTL_CONF(SIRQ1, 0, 12, 2); +static PAD_PULLCTL_CONF(SIRQ2, 0, 10, 2); +static PAD_PULLCTL_CONF(I2C0_SDATA, 0, 9, 1); +static PAD_PULLCTL_CONF(I2C0_SCLK, 0, 8, 1); +static PAD_PULLCTL_CONF(KS_IN0, 0, 7, 1); +static PAD_PULLCTL_CONF(KS_IN1, 0, 6, 1); +static PAD_PULLCTL_CONF(KS_IN2, 0, 5, 1); +static PAD_PULLCTL_CONF(KS_IN3, 0, 4, 1); +static PAD_PULLCTL_CONF(KS_OUT0, 0, 2, 1); +static PAD_PULLCTL_CONF(KS_OUT1, 0, 1, 1); +static PAD_PULLCTL_CONF(DSI_DP1, 0, 0, 1); + +/* PAD_PULLCTL1 */ +static PAD_PULLCTL_CONF(SD0_D0, 1, 17, 1); +static PAD_PULLCTL_CONF(SD0_D1, 1, 16, 1); +static PAD_PULLCTL_CONF(SD0_D2, 1, 15, 1); +static PAD_PULLCTL_CONF(SD0_D3, 1, 14, 1); +static PAD_PULLCTL_CONF(SD0_CMD, 1, 13, 1); +static PAD_PULLCTL_CONF(SD0_CLK, 1, 12, 1); +static PAD_PULLCTL_CONF(UART0_RX, 1, 2, 1); +static PAD_PULLCTL_CONF(UART0_TX, 1, 1, 1); +static PAD_PULLCTL_CONF(CLKO_25M, 1, 0, 1); + +/* PAD_PULLCTL2 */ +static PAD_PULLCTL_CONF(ETH_TXD2, 2, 18, 1); +static PAD_PULLCTL_CONF(ETH_TXD3, 2, 17, 1); +static PAD_PULLCTL_CONF(SPI0_SS, 2, 16, 1); +static PAD_PULLCTL_CONF(SPI0_MISO, 2, 15, 1); +static PAD_PULLCTL_CONF(I2C1_SDATA, 2, 10, 1); +static PAD_PULLCTL_CONF(I2C1_SCLK, 2, 9, 1); +static PAD_PULLCTL_CONF(I2C2_SDATA, 2, 8, 1); +static PAD_PULLCTL_CONF(I2C2_SCLK, 2, 7, 1); + +/* Pad info table for the pinmux subsystem */ +static struct owl_padinfo s700_padinfo[NUM_PADS] = { + [ETH_TXD0] = PAD_INFO_ST(ETH_TXD0), + [ETH_TXD1] = PAD_INFO_ST(ETH_TXD1), + [ETH_TXEN] = PAD_INFO_ST(ETH_TXEN), + [ETH_RXER] = PAD_INFO_PULLCTL_ST(ETH_RXER), + [ETH_CRS_DV] = PAD_INFO_ST(ETH_CRS_DV), + [ETH_RXD1] = PAD_INFO_ST(ETH_RXD1), + [ETH_RXD0] = PAD_INFO_ST(ETH_RXD0), + [ETH_REF_CLK] = PAD_INFO_ST(ETH_REF_CLK), + [ETH_MDC] = PAD_INFO(ETH_MDC), + [ETH_MDIO] = PAD_INFO(ETH_MDIO), + [SIRQ0] = PAD_INFO_PULLCTL(SIRQ0), + [SIRQ1] = PAD_INFO_PULLCTL(SIRQ1), + [SIRQ2] = PAD_INFO_PULLCTL(SIRQ2), + [I2S_D0] = PAD_INFO(I2S_D0), + [I2S_BCLK0] = PAD_INFO_ST(I2S_BCLK0), + [I2S_LRCLK0] = PAD_INFO_ST(I2S_LRCLK0), + [I2S_MCLK0] = PAD_INFO_ST(I2S_MCLK0), + [I2S_D1] = PAD_INFO(I2S_D1), + [I2S_BCLK1] = PAD_INFO(I2S_BCLK1), + [I2S_LRCLK1] = PAD_INFO_ST(I2S_LRCLK1), + [I2S_MCLK1] = PAD_INFO_ST(I2S_MCLK1), + [KS_IN0] = PAD_INFO_PULLCTL_ST(KS_IN0), + [KS_IN1] = PAD_INFO_PULLCTL(KS_IN1), + [KS_IN2] = PAD_INFO_PULLCTL(KS_IN2), + [KS_IN3] = PAD_INFO_PULLCTL(KS_IN3), + [KS_OUT0] = PAD_INFO_PULLCTL_ST(KS_OUT0), + [KS_OUT1] = PAD_INFO_PULLCTL_ST(KS_OUT1), + [KS_OUT2] = PAD_INFO_PULLCTL_ST(KS_OUT2), + [LVDS_OEP] = PAD_INFO(LVDS_OEP), + [LVDS_OEN] = PAD_INFO(LVDS_OEN), + [LVDS_ODP] = PAD_INFO(LVDS_ODP), + [LVDS_ODN] = PAD_INFO(LVDS_ODN), + [LVDS_OCP] = PAD_INFO(LVDS_OCP), + [LVDS_OCN] = PAD_INFO(LVDS_OCN), + [LVDS_OBP] = PAD_INFO(LVDS_OBP), + [LVDS_OBN] = PAD_INFO(LVDS_OBN), + [LVDS_OAP] = PAD_INFO_ST(LVDS_OAP), + [LVDS_OAN] = PAD_INFO(LVDS_OAN), + [LVDS_EEP] = PAD_INFO(LVDS_EEP), + [LVDS_EEN] = PAD_INFO(LVDS_EEN), + [LVDS_EDP] = PAD_INFO(LVDS_EDP), + [LVDS_EDN] = PAD_INFO(LVDS_EDN), + [LVDS_ECP] = PAD_INFO(LVDS_ECP), + [LVDS_ECN] = PAD_INFO(LVDS_ECN), + [LVDS_EBP] = PAD_INFO(LVDS_EBP), + [LVDS_EBN] = PAD_INFO(LVDS_EBN), + [LVDS_EAP] = PAD_INFO(LVDS_EAP), + [LVDS_EAN] = PAD_INFO(LVDS_EAN), + [LCD0_D18] = PAD_INFO(LCD0_D18), + [LCD0_D2] = PAD_INFO_PULLCTL(LCD0_D2), + [DSI_DP3] = PAD_INFO(DSI_DP3), + [DSI_DN3] = PAD_INFO_PULLCTL(DSI_DN3), + [DSI_DP1] = PAD_INFO_PULLCTL(DSI_DP1), + [DSI_DN1] = PAD_INFO(DSI_DN1), + [DSI_DP0] = PAD_INFO_ST(DSI_DP0), + [DSI_DN0] = PAD_INFO_ST(DSI_DN0), + [DSI_DP2] = PAD_INFO_ST(DSI_DP2), + [DSI_DN2] = PAD_INFO_ST(DSI_DN2), + [SD0_D0] = PAD_INFO_PULLCTL(SD0_D0), + [SD0_D1] = PAD_INFO_PULLCTL(SD0_D1), + [SD0_D2] = PAD_INFO_PULLCTL(SD0_D2), + [SD0_D3] = PAD_INFO_PULLCTL(SD0_D3), + [SD0_CMD] = PAD_INFO_PULLCTL(SD0_CMD), + [SD0_CLK] = PAD_INFO_PULLCTL_ST(SD0_CLK), + [SD1_CLK] = PAD_INFO(SD1_CLK), + [SPI0_SS] = PAD_INFO_PULLCTL_ST(SPI0_SS), + [SPI0_MISO] = PAD_INFO_PULLCTL_ST(SPI0_MISO), + [UART0_RX] = PAD_INFO_PULLCTL_ST(UART0_RX), + [UART0_TX] = PAD_INFO_PULLCTL_ST(UART0_TX), + [I2C0_SCLK] = PAD_INFO_PULLCTL_ST(I2C0_SCLK), + [I2C0_SDATA] = PAD_INFO_PULLCTL_ST(I2C0_SDATA), + [SENSOR0_PCLK] = PAD_INFO_ST(SENSOR0_PCLK), + [SENSOR0_CKOUT] = PAD_INFO(SENSOR0_CKOUT), + [DNAND_ALE] = PAD_INFO(DNAND_ALE), + [DNAND_CLE] = PAD_INFO(DNAND_CLE), + [DNAND_CEB0] = PAD_INFO(DNAND_CEB0), + [DNAND_CEB1] = PAD_INFO(DNAND_CEB1), + [DNAND_CEB2] = PAD_INFO(DNAND_CEB2), + [DNAND_CEB3] = PAD_INFO(DNAND_CEB3), + [UART2_RX] = PAD_INFO_ST(UART2_RX), + [UART2_TX] = PAD_INFO_ST(UART2_TX), + [UART2_RTSB] = PAD_INFO_ST(UART2_RTSB), + [UART2_CTSB] = PAD_INFO_ST(UART2_CTSB), + [UART3_RX] = PAD_INFO_ST(UART3_RX), + [UART3_TX] = PAD_INFO(UART3_TX), + [UART3_RTSB] = PAD_INFO_ST(UART3_RTSB), + [UART3_CTSB] = PAD_INFO_ST(UART3_CTSB), + [PCM1_IN] = PAD_INFO_ST(PCM1_IN), + [PCM1_CLK] = PAD_INFO_ST(PCM1_CLK), + [PCM1_SYNC] = PAD_INFO_PULLCTL_ST(PCM1_SYNC), + [PCM1_OUT] = PAD_INFO_PULLCTL(PCM1_OUT), + [I2C1_SCLK] = PAD_INFO_PULLCTL_ST(I2C1_SCLK), + [I2C1_SDATA] = PAD_INFO_PULLCTL_ST(I2C1_SDATA), + [I2C2_SCLK] = PAD_INFO_PULLCTL_ST(I2C2_SCLK), + [I2C2_SDATA] = PAD_INFO_PULLCTL_ST(I2C2_SDATA), + [CSI_DN0] = PAD_INFO(CSI_DN0), + [CSI_DP0] = PAD_INFO(CSI_DP0), + [CSI_DN1] = PAD_INFO(CSI_DN1), + [CSI_DP1] = PAD_INFO(CSI_DP1), + [CSI_CN] = PAD_INFO(CSI_CN), + [CSI_CP] = PAD_INFO(CSI_CP), + [CSI_DN2] = PAD_INFO(CSI_DN2), + [CSI_DP2] = PAD_INFO(CSI_DP2), + [CSI_DN3] = PAD_INFO(CSI_DN3), + [CSI_DP3] = PAD_INFO(CSI_DP3), + [DNAND_WRB] = PAD_INFO(DNAND_WRB), + [DNAND_RDB] = PAD_INFO(DNAND_RDB), + [DNAND_RB0] = PAD_INFO(DNAND_RB0), + [PORB] = PAD_INFO(PORB), + [CLKO_25M] = PAD_INFO_PULLCTL(CLKO_25M), + [BSEL] = PAD_INFO(BSEL), + [PKG0] = PAD_INFO(PKG0), + [PKG1] = PAD_INFO(PKG1), + [PKG2] = PAD_INFO(PKG2), + [PKG3] = PAD_INFO(PKG3), + [ETH_TXD2] = PAD_INFO_PULLCTL_ST(ETH_TXD2), + [ETH_TXD3] = PAD_INFO_PULLCTL_ST(ETH_TXD3), +}; + +static const struct owl_gpio_port s700_gpio_ports[] = { + OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x230, 0), + OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x204, 0x210, 0x214, 0x238, 1), + OWL_GPIO_PORT(C, 0x0018, 32, 0x0, 0x4, 0x8, 0x204, 0x218, 0x21C, 0x240, 2), + OWL_GPIO_PORT(D, 0x0024, 32, 0x0, 0x4, 0x8, 0x204, 0x220, 0x224, 0x248, 3), + /* 0x24C (INTC_GPIOD_TYPE1) used to tweak the driver to handle generic */ + OWL_GPIO_PORT(E, 0x0030, 8, 0x0, 0x4, 0x8, 0x204, 0x228, 0x22C, 0x24C, 4), +}; + +enum s700_pinconf_pull { + OWL_PINCONF_PULL_DOWN, + OWL_PINCONF_PULL_UP, +}; + +static int s700_pad_pinconf_arg2val(const struct owl_padinfo *info, + unsigned int param, + u32 *arg) +{ + switch (param) { + case PIN_CONFIG_BIAS_PULL_DOWN: + *arg = OWL_PINCONF_PULL_DOWN; + break; + case PIN_CONFIG_BIAS_PULL_UP: + *arg = OWL_PINCONF_PULL_UP; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + *arg = (*arg >= 1 ? 1 : 0); + break; + default: + return -ENOTSUPP; + } + + return 0; +} + +static int s700_pad_pinconf_val2arg(const struct owl_padinfo *padinfo, + unsigned int param, + u32 *arg) +{ + switch (param) { + case PIN_CONFIG_BIAS_PULL_DOWN: + *arg = *arg == OWL_PINCONF_PULL_DOWN; + break; + case PIN_CONFIG_BIAS_PULL_UP: + *arg = *arg == OWL_PINCONF_PULL_UP; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + *arg = *arg == 1; + break; + default: + return -ENOTSUPP; + } + + return 0; +} + +static struct owl_pinctrl_soc_data s700_pinctrl_data = { + .padinfo = s700_padinfo, + .pins = (const struct pinctrl_pin_desc *)s700_pads, + .npins = ARRAY_SIZE(s700_pads), + .functions = s700_functions, + .nfunctions = ARRAY_SIZE(s700_functions), + .groups = s700_groups, + .ngroups = ARRAY_SIZE(s700_groups), + .ngpios = NUM_GPIOS, + .ports = s700_gpio_ports, + .nports = ARRAY_SIZE(s700_gpio_ports), + .padctl_arg2val = s700_pad_pinconf_arg2val, + .padctl_val2arg = s700_pad_pinconf_val2arg, +}; + +static int s700_pinctrl_probe(struct platform_device *pdev) +{ + return owl_pinctrl_probe(pdev, &s700_pinctrl_data); +} + +static const struct of_device_id s700_pinctrl_of_match[] = { + { .compatible = "actions,s700-pinctrl", }, + {} +}; + +static struct platform_driver s700_pinctrl_driver = { + .probe = s700_pinctrl_probe, + .driver = { + .name = "pinctrl-s700", + .of_match_table = of_match_ptr(s700_pinctrl_of_match), + }, +}; + +static int __init s700_pinctrl_init(void) +{ + return platform_driver_register(&s700_pinctrl_driver); +} +arch_initcall(s700_pinctrl_init); + +static void __exit s700_pinctrl_exit(void) +{ + platform_driver_unregister(&s700_pinctrl_driver); +} +module_exit(s700_pinctrl_exit); + +MODULE_AUTHOR("Actions Semi Inc."); +MODULE_DESCRIPTION("Actions Semi S700 Soc Pinctrl Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/actions/pinctrl-s900.c b/drivers/pinctrl/actions/pinctrl-s900.c index ea67b14ef93b..9492b86852e7 100644 --- a/drivers/pinctrl/actions/pinctrl-s900.c +++ b/drivers/pinctrl/actions/pinctrl-s900.c @@ -13,6 +13,7 @@ #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinconf-generic.h> #include "pinctrl-owl.h" /* Pinctrl registers offset */ @@ -33,13 +34,6 @@ #define PAD_SR1 (0x0274) #define PAD_SR2 (0x0278) -#define OWL_GPIO_PORT_A 0 -#define OWL_GPIO_PORT_B 1 -#define OWL_GPIO_PORT_C 2 -#define OWL_GPIO_PORT_D 3 -#define OWL_GPIO_PORT_E 4 -#define OWL_GPIO_PORT_F 5 - #define _GPIOA(offset) (offset) #define _GPIOB(offset) (32 + (offset)) #define _GPIOC(offset) (64 + (offset)) @@ -892,55 +886,6 @@ static unsigned int i2c2_sr_pads[] = { I2C2_SCLK, I2C2_SDATA }; static unsigned int sensor0_sr_pads[] = { SENSOR0_PCLK, SENSOR0_CKOUT }; -#define MUX_PG(group_name, reg, shift, width) \ - { \ - .name = #group_name, \ - .pads = group_name##_pads, \ - .npads = ARRAY_SIZE(group_name##_pads), \ - .funcs = group_name##_funcs, \ - .nfuncs = ARRAY_SIZE(group_name##_funcs), \ - .mfpctl_reg = MFCTL##reg, \ - .mfpctl_shift = shift, \ - .mfpctl_width = width, \ - .drv_reg = -1, \ - .drv_shift = -1, \ - .drv_width = -1, \ - .sr_reg = -1, \ - .sr_shift = -1, \ - .sr_width = -1, \ - } - -#define DRV_PG(group_name, reg, shift, width) \ - { \ - .name = #group_name, \ - .pads = group_name##_pads, \ - .npads = ARRAY_SIZE(group_name##_pads), \ - .mfpctl_reg = -1, \ - .mfpctl_shift = -1, \ - .mfpctl_width = -1, \ - .drv_reg = PAD_DRV##reg, \ - .drv_shift = shift, \ - .drv_width = width, \ - .sr_reg = -1, \ - .sr_shift = -1, \ - .sr_width = -1, \ - } - -#define SR_PG(group_name, reg, shift, width) \ - { \ - .name = #group_name, \ - .pads = group_name##_pads, \ - .npads = ARRAY_SIZE(group_name##_pads), \ - .mfpctl_reg = -1, \ - .mfpctl_shift = -1, \ - .mfpctl_width = -1, \ - .drv_reg = -1, \ - .drv_shift = -1, \ - .drv_width = -1, \ - .sr_reg = PAD_SR##reg, \ - .sr_shift = shift, \ - .sr_width = width, \ - } /* Pinctrl groups */ static const struct owl_pingroup s900_groups[] = { @@ -1442,13 +1387,6 @@ static const char * const sirq2_groups[] = { "sirq2_dummy", }; -#define FUNCTION(fname) \ - { \ - .name = #fname, \ - .groups = fname##_groups, \ - .ngroups = ARRAY_SIZE(fname##_groups), \ - } - static const struct owl_pinmux_func s900_functions[] = { [S900_MUX_ERAM] = FUNCTION(eram), [S900_MUX_ETH_RMII] = FUNCTION(eth_rmii), @@ -1500,28 +1438,6 @@ static const struct owl_pinmux_func s900_functions[] = { [S900_MUX_SIRQ1] = FUNCTION(sirq1), [S900_MUX_SIRQ2] = FUNCTION(sirq2) }; -/* PAD PULL UP/DOWN CONFIGURES */ -#define PULLCTL_CONF(pull_reg, pull_sft, pull_wdt) \ - { \ - .reg = PAD_PULLCTL##pull_reg, \ - .shift = pull_sft, \ - .width = pull_wdt, \ - } - -#define PAD_PULLCTL_CONF(pad_name, pull_reg, pull_sft, pull_wdt) \ - struct owl_pullctl pad_name##_pullctl_conf \ - = PULLCTL_CONF(pull_reg, pull_sft, pull_wdt) - -#define ST_CONF(st_reg, st_sft, st_wdt) \ - { \ - .reg = PAD_ST##st_reg, \ - .shift = st_sft, \ - .width = st_wdt, \ - } - -#define PAD_ST_CONF(pad_name, st_reg, st_sft, st_wdt) \ - struct owl_st pad_name##_st_conf \ - = ST_CONF(st_reg, st_sft, st_wdt) /* PAD_PULLCTL0 */ static PAD_PULLCTL_CONF(ETH_RXER, 0, 18, 2); @@ -1639,34 +1555,6 @@ static PAD_ST_CONF(SPI0_SS, 1, 2, 1); static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1); static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1); -#define PAD_INFO(name) \ - { \ - .pad = name, \ - .pullctl = NULL, \ - .st = NULL, \ - } - -#define PAD_INFO_ST(name) \ - { \ - .pad = name, \ - .pullctl = NULL, \ - .st = &name##_st_conf, \ - } - -#define PAD_INFO_PULLCTL(name) \ - { \ - .pad = name, \ - .pullctl = &name##_pullctl_conf, \ - .st = NULL, \ - } - -#define PAD_INFO_PULLCTL_ST(name) \ - { \ - .pad = name, \ - .pullctl = &name##_pullctl_conf, \ - .st = &name##_st_conf, \ - } - /* Pad info table */ static struct owl_padinfo s900_padinfo[NUM_PADS] = { [ETH_TXD0] = PAD_INFO_ST(ETH_TXD0), @@ -1821,29 +1709,76 @@ static struct owl_padinfo s900_padinfo[NUM_PADS] = { [SGPIO3] = PAD_INFO_PULLCTL_ST(SGPIO3) }; -#define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat, \ - _intc_ctl, _intc_pd, _intc_msk, _intc_type) \ - [OWL_GPIO_PORT_##port] = { \ - .offset = base, \ - .pins = count, \ - .outen = _outen, \ - .inen = _inen, \ - .dat = _dat, \ - .intc_ctl = _intc_ctl, \ - .intc_pd = _intc_pd, \ - .intc_msk = _intc_msk, \ - .intc_type = _intc_type, \ - } - static const struct owl_gpio_port s900_gpio_ports[] = { - OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x240), - OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x534, 0x204, 0x208, 0x23C), - OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8, 0x52C, 0x200, 0x204, 0x238), - OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8, 0x524, 0x1FC, 0x200, 0x234), - OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8, 0x51C, 0x1F8, 0x1FC, 0x230), - OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8, 0x460, 0x140, 0x144, 0x178) + OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x240, 0), + OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x534, 0x204, 0x208, 0x23C, 0), + OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8, 0x52C, 0x200, 0x204, 0x238, 0), + OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8, 0x524, 0x1FC, 0x200, 0x234, 0), + OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8, 0x51C, 0x1F8, 0x1FC, 0x230, 0), + OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8, 0x460, 0x140, 0x144, 0x178, 0) }; +enum s900_pinconf_pull { + OWL_PINCONF_PULL_HIZ, + OWL_PINCONF_PULL_DOWN, + OWL_PINCONF_PULL_UP, + OWL_PINCONF_PULL_HOLD, +}; + +static int s900_pad_pinconf_arg2val(const struct owl_padinfo *info, + unsigned int param, + u32 *arg) +{ + switch (param) { + case PIN_CONFIG_BIAS_BUS_HOLD: + *arg = OWL_PINCONF_PULL_HOLD; + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + *arg = OWL_PINCONF_PULL_HIZ; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + *arg = OWL_PINCONF_PULL_DOWN; + break; + case PIN_CONFIG_BIAS_PULL_UP: + *arg = OWL_PINCONF_PULL_UP; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + *arg = (*arg >= 1 ? 1 : 0); + break; + default: + return -ENOTSUPP; + } + + return 0; +} + +static int s900_pad_pinconf_val2arg(const struct owl_padinfo *padinfo, + unsigned int param, + u32 *arg) +{ + switch (param) { + case PIN_CONFIG_BIAS_BUS_HOLD: + *arg = *arg == OWL_PINCONF_PULL_HOLD; + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + *arg = *arg == OWL_PINCONF_PULL_HIZ; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + *arg = *arg == OWL_PINCONF_PULL_DOWN; + break; + case PIN_CONFIG_BIAS_PULL_UP: + *arg = *arg == OWL_PINCONF_PULL_UP; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + *arg = *arg == 1; + break; + default: + return -ENOTSUPP; + } + + return 0; +} + static struct owl_pinctrl_soc_data s900_pinctrl_data = { .padinfo = s900_padinfo, .pins = (const struct pinctrl_pin_desc *)s900_pads, @@ -1854,7 +1789,9 @@ static struct owl_pinctrl_soc_data s900_pinctrl_data = { .ngroups = ARRAY_SIZE(s900_groups), .ngpios = NUM_GPIOS, .ports = s900_gpio_ports, - .nports = ARRAY_SIZE(s900_gpio_ports) + .nports = ARRAY_SIZE(s900_gpio_ports), + .padctl_arg2val = s900_pad_pinconf_arg2val, + .padctl_val2arg = s900_pad_pinconf_val2arg, }; static int s900_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index fa530913a2c8..f180aa44a422 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO) * @@ -6,16 +7,6 @@ * This driver is inspired by: * pinctrl-nomadik.c, please see original file for copyright information * pinctrl-tegra.c, please see original file for copyright information - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <linux/bitmap.h> @@ -72,10 +63,8 @@ #define GPIO_REG_OFFSET(p) ((p) / 32) #define GPIO_REG_SHIFT(p) ((p) % 32) -enum bcm2835_pinconf_param { - /* argument: bcm2835_pinconf_pull */ - BCM2835_PINCONF_PARAM_PULL = (PIN_CONFIG_END + 1), -}; +/* argument: bcm2835_pinconf_pull */ +#define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1) struct bcm2835_pinctrl { struct device *dev; @@ -90,7 +79,7 @@ struct bcm2835_pinctrl { struct gpio_chip gpio_chip; struct pinctrl_gpio_range gpio_range; - spinlock_t irq_lock[BCM2835_NUM_BANKS]; + raw_spinlock_t irq_lock[BCM2835_NUM_BANKS]; }; /* pins are just named GPIO0..GPIO53 */ @@ -461,10 +450,10 @@ static void bcm2835_gpio_irq_enable(struct irq_data *data) unsigned bank = GPIO_REG_OFFSET(gpio); unsigned long flags; - spin_lock_irqsave(&pc->irq_lock[bank], flags); + raw_spin_lock_irqsave(&pc->irq_lock[bank], flags); set_bit(offset, &pc->enabled_irq_map[bank]); bcm2835_gpio_irq_config(pc, gpio, true); - spin_unlock_irqrestore(&pc->irq_lock[bank], flags); + raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags); } static void bcm2835_gpio_irq_disable(struct irq_data *data) @@ -476,12 +465,12 @@ static void bcm2835_gpio_irq_disable(struct irq_data *data) unsigned bank = GPIO_REG_OFFSET(gpio); unsigned long flags; - spin_lock_irqsave(&pc->irq_lock[bank], flags); + raw_spin_lock_irqsave(&pc->irq_lock[bank], flags); bcm2835_gpio_irq_config(pc, gpio, false); /* Clear events that were latched prior to clearing event sources */ bcm2835_gpio_set_bit(pc, GPEDS0, gpio); clear_bit(offset, &pc->enabled_irq_map[bank]); - spin_unlock_irqrestore(&pc->irq_lock[bank], flags); + raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags); } static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc, @@ -584,7 +573,7 @@ static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type) unsigned long flags; int ret; - spin_lock_irqsave(&pc->irq_lock[bank], flags); + raw_spin_lock_irqsave(&pc->irq_lock[bank], flags); if (test_bit(offset, &pc->enabled_irq_map[bank])) ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type); @@ -596,7 +585,7 @@ static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type) else irq_set_handler_locked(data, handle_level_irq); - spin_unlock_irqrestore(&pc->irq_lock[bank], flags); + raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags); return ret; } @@ -1047,7 +1036,7 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) for_each_set_bit(offset, &events, 32) bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset)); - spin_lock_init(&pc->irq_lock[i]); + raw_spin_lock_init(&pc->irq_lock[i]); } err = gpiochip_add_data(&pc->gpio_chip, pc); diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index dccf64c55498..2d6db434f70a 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -5,6 +5,10 @@ config PINCTRL_IMX select GENERIC_PINCONF select REGMAP +config PINCTRL_IMX_SCU + bool + select PINCTRL_IMX + config PINCTRL_IMX1_CORE bool select PINMUX @@ -124,6 +128,13 @@ config PINCTRL_IMX8MQ help Say Y here to enable the imx8mq pinctrl driver +config PINCTRL_IMX8QXP + bool "IMX8QXP pinctrl driver" + depends on SOC_IMX8QXP + select PINCTRL_IMX_SCU + help + Say Y here to enable the imx8qxp pinctrl driver + config PINCTRL_VF610 bool "Freescale Vybrid VF610 pinctrl driver" depends on SOC_VF610 diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile index 73175b3e7c9c..6ee398a3e406 100644 --- a/drivers/pinctrl/freescale/Makefile +++ b/drivers/pinctrl/freescale/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 # Freescale pin control drivers obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o +obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o obj-$(CONFIG_PINCTRL_IMX21) += pinctrl-imx21.o @@ -18,6 +19,7 @@ obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o +obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 4e8cf0e357c6..188001beb298 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -57,9 +57,11 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, struct pinctrl_map **map, unsigned *num_maps) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info = ipctl->info; const struct group_desc *grp; struct pinctrl_map *new_map; struct device_node *parent; + struct imx_pin *pin; int map_num = 1; int i, j; @@ -73,11 +75,14 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, return -EINVAL; } - for (i = 0; i < grp->num_pins; i++) { - struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; - - if (!(pin->config & IMX_NO_PAD_CTL)) - map_num++; + if (info->flags & IMX_USE_SCU) { + map_num += grp->num_pins; + } else { + for (i = 0; i < grp->num_pins; i++) { + pin = &((struct imx_pin *)(grp->data))[i]; + if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL)) + map_num++; + } } new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map), @@ -102,16 +107,35 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, /* create config map */ new_map++; for (i = j = 0; i < grp->num_pins; i++) { - struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; + pin = &((struct imx_pin *)(grp->data))[i]; - if (!(pin->config & IMX_NO_PAD_CTL)) { - new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; - new_map[j].data.configs.group_or_pin = + /* + * We only create config maps for SCU pads or MMIO pads that + * are not using the default config(a.k.a IMX_NO_PAD_CTL) + */ + if (!(info->flags & IMX_USE_SCU) && + (pin->conf.mmio.config & IMX_NO_PAD_CTL)) + continue; + + new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; + new_map[j].data.configs.group_or_pin = pin_get_name(pctldev, pin->pin); - new_map[j].data.configs.configs = &pin->config; + + if (info->flags & IMX_USE_SCU) { + /* + * For SCU case, we set mux and conf together + * in one IPC call + */ + new_map[j].data.configs.configs = + (unsigned long *)&pin->conf.scu; + new_map[j].data.configs.num_configs = 2; + } else { + new_map[j].data.configs.configs = + &pin->conf.mmio.config; new_map[j].data.configs.num_configs = 1; - j++; } + + j++; } dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", @@ -133,19 +157,96 @@ static const struct pinctrl_ops imx_pctrl_ops = { .pin_dbg_show = imx_pin_dbg_show, .dt_node_to_map = imx_dt_node_to_map, .dt_free_map = imx_dt_free_map, - }; +static int imx_pmx_set_one_pin_mmio(struct imx_pinctrl *ipctl, + struct imx_pin *pin) +{ + const struct imx_pinctrl_soc_info *info = ipctl->info; + struct imx_pin_mmio *pin_mmio = &pin->conf.mmio; + const struct imx_pin_reg *pin_reg; + unsigned int pin_id; + + pin_id = pin->pin; + pin_reg = &ipctl->pin_regs[pin_id]; + + if (pin_reg->mux_reg == -1) { + dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n", + info->pins[pin_id].name); + return 0; + } + + if (info->flags & SHARE_MUX_CONF_REG) { + u32 reg; + + reg = readl(ipctl->base + pin_reg->mux_reg); + reg &= ~info->mux_mask; + reg |= (pin_mmio->mux_mode << info->mux_shift); + writel(reg, ipctl->base + pin_reg->mux_reg); + dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", + pin_reg->mux_reg, reg); + } else { + writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg); + dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", + pin_reg->mux_reg, pin_mmio->mux_mode); + } + + /* + * If the select input value begins with 0xff, it's a quirky + * select input and the value should be interpreted as below. + * 31 23 15 7 0 + * | 0xff | shift | width | select | + * It's used to work around the problem that the select + * input for some pin is not implemented in the select + * input register but in some general purpose register. + * We encode the select input value, width and shift of + * the bit field into input_val cell of pin function ID + * in device tree, and then decode them here for setting + * up the select input bits in general purpose register. + */ + if (pin_mmio->input_val >> 24 == 0xff) { + u32 val = pin_mmio->input_val; + u8 select = val & 0xff; + u8 width = (val >> 8) & 0xff; + u8 shift = (val >> 16) & 0xff; + u32 mask = ((1 << width) - 1) << shift; + /* + * The input_reg[i] here is actually some IOMUXC general + * purpose register, not regular select input register. + */ + val = readl(ipctl->base + pin_mmio->input_reg); + val &= ~mask; + val |= select << shift; + writel(val, ipctl->base + pin_mmio->input_reg); + } else if (pin_mmio->input_reg) { + /* + * Regular select input register can never be at offset + * 0, and we only print register value for regular case. + */ + if (ipctl->input_sel_base) + writel(pin_mmio->input_val, ipctl->input_sel_base + + pin_mmio->input_reg); + else + writel(pin_mmio->input_val, ipctl->base + + pin_mmio->input_reg); + dev_dbg(ipctl->dev, + "==>select_input: offset 0x%x val 0x%x\n", + pin_mmio->input_reg, pin_mmio->input_val); + } + + return 0; +} + static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, unsigned group) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_reg *pin_reg; - unsigned int npins, pin_id; - int i; - struct group_desc *grp = NULL; - struct function_desc *func = NULL; + struct function_desc *func; + struct group_desc *grp; + struct imx_pin *pin; + unsigned int npins; + int i, err; /* * Configure the mux mode for each pin in the group for a specific @@ -165,72 +266,16 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, func->name, grp->name); for (i = 0; i < npins; i++) { - struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; - - pin_id = pin->pin; - pin_reg = &ipctl->pin_regs[pin_id]; - - if (pin_reg->mux_reg == -1) { - dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n", - info->pins[pin_id].name); - continue; - } - - if (info->flags & SHARE_MUX_CONF_REG) { - u32 reg; - reg = readl(ipctl->base + pin_reg->mux_reg); - reg &= ~info->mux_mask; - reg |= (pin->mux_mode << info->mux_shift); - writel(reg, ipctl->base + pin_reg->mux_reg); - dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", - pin_reg->mux_reg, reg); - } else { - writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); - dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", - pin_reg->mux_reg, pin->mux_mode); - } - /* - * If the select input value begins with 0xff, it's a quirky - * select input and the value should be interpreted as below. - * 31 23 15 7 0 - * | 0xff | shift | width | select | - * It's used to work around the problem that the select - * input for some pin is not implemented in the select - * input register but in some general purpose register. - * We encode the select input value, width and shift of - * the bit field into input_val cell of pin function ID - * in device tree, and then decode them here for setting - * up the select input bits in general purpose register. + * For IMX_USE_SCU case, we postpone the mux setting + * until config is set as we can set them together + * in one IPC call */ - if (pin->input_val >> 24 == 0xff) { - u32 val = pin->input_val; - u8 select = val & 0xff; - u8 width = (val >> 8) & 0xff; - u8 shift = (val >> 16) & 0xff; - u32 mask = ((1 << width) - 1) << shift; - /* - * The input_reg[i] here is actually some IOMUXC general - * purpose register, not regular select input register. - */ - val = readl(ipctl->base + pin->input_reg); - val &= ~mask; - val |= select << shift; - writel(val, ipctl->base + pin->input_reg); - } else if (pin->input_reg) { - /* - * Regular select input register can never be at offset - * 0, and we only print register value for regular case. - */ - if (ipctl->input_sel_base) - writel(pin->input_val, ipctl->input_sel_base + - pin->input_reg); - else - writel(pin->input_val, ipctl->base + - pin->input_reg); - dev_dbg(ipctl->dev, - "==>select_input: offset 0x%x val 0x%x\n", - pin->input_reg, pin->input_val); + pin = &((struct imx_pin *)(grp->data))[i]; + if (!(info->flags & IMX_USE_SCU)) { + err = imx_pmx_set_one_pin_mmio(ipctl, pin); + if (err) + return err; } } @@ -300,8 +345,8 @@ static u32 imx_pinconf_parse_generic_config(struct device_node *np, return imx_pinconf_decode_generic_config(ipctl, configs, num_configs); } -static int imx_pinconf_get(struct pinctrl_dev *pctldev, - unsigned pin_id, unsigned long *config) +static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_id, + unsigned long *config) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info = ipctl->info; @@ -321,9 +366,21 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev, return 0; } -static int imx_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin_id, unsigned long *configs, - unsigned num_configs) +static int imx_pinconf_get(struct pinctrl_dev *pctldev, + unsigned pin_id, unsigned long *config) +{ + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info = ipctl->info; + + if (info->flags & IMX_USE_SCU) + return imx_pinconf_get_scu(pctldev, pin_id, config); + else + return imx_pinconf_get_mmio(pctldev, pin_id, config); +} + +static int imx_pinconf_set_mmio(struct pinctrl_dev *pctldev, + unsigned pin_id, unsigned long *configs, + unsigned num_configs) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info = ipctl->info; @@ -358,19 +415,48 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev, return 0; } +static int imx_pinconf_set(struct pinctrl_dev *pctldev, + unsigned pin_id, unsigned long *configs, + unsigned num_configs) +{ + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info = ipctl->info; + + if (info->flags & IMX_USE_SCU) + return imx_pinconf_set_scu(pctldev, pin_id, + configs, num_configs); + else + return imx_pinconf_set_mmio(pctldev, pin_id, + configs, num_configs); +} + static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned pin_id) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id]; + const struct imx_pinctrl_soc_info *info = ipctl->info; + const struct imx_pin_reg *pin_reg; unsigned long config; + int ret; - if (!pin_reg || pin_reg->conf_reg == -1) { - seq_puts(s, "N/A"); - return; + if (info->flags & IMX_USE_SCU) { + ret = imx_pinconf_get_scu(pctldev, pin_id, &config); + if (ret) { + dev_err(ipctl->dev, "failed to get %s pinconf\n", + pin_get_name(pctldev, pin_id)); + seq_puts(s, "N/A"); + return; + } + } else { + pin_reg = &ipctl->pin_regs[pin_id]; + if (!pin_reg || pin_reg->conf_reg == -1) { + seq_puts(s, "N/A"); + return; + } + + config = readl(ipctl->base + pin_reg->conf_reg); } - config = readl(ipctl->base + pin_reg->conf_reg); seq_printf(s, "0x%lx", config); } @@ -418,9 +504,65 @@ static const struct pinconf_ops imx_pinconf_ops = { * <mux_reg conf_reg input_reg mux_mode input_val> * SHARE_MUX_CONF_REG: * <mux_conf_reg input_reg mux_mode input_val> + * IMX_USE_SCU: + * <pin_id mux_mode> */ #define FSL_PIN_SIZE 24 #define FSL_PIN_SHARE_SIZE 20 +#define FSL_SCU_PIN_SIZE 12 + +static void imx_pinctrl_parse_pin_mmio(struct imx_pinctrl *ipctl, + unsigned int *pin_id, struct imx_pin *pin, + const __be32 **list_p, + struct device_node *np) +{ + const struct imx_pinctrl_soc_info *info = ipctl->info; + struct imx_pin_mmio *pin_mmio = &pin->conf.mmio; + struct imx_pin_reg *pin_reg; + const __be32 *list = *list_p; + u32 mux_reg, conf_reg; + u32 config; + + mux_reg = be32_to_cpu(*list++); + + if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) + mux_reg = -1; + + if (info->flags & SHARE_MUX_CONF_REG) { + conf_reg = mux_reg; + } else { + conf_reg = be32_to_cpu(*list++); + if (!conf_reg) + conf_reg = -1; + } + + *pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; + pin_reg = &ipctl->pin_regs[*pin_id]; + pin->pin = *pin_id; + pin_reg->mux_reg = mux_reg; + pin_reg->conf_reg = conf_reg; + pin_mmio->input_reg = be32_to_cpu(*list++); + pin_mmio->mux_mode = be32_to_cpu(*list++); + pin_mmio->input_val = be32_to_cpu(*list++); + + if (info->generic_pinconf) { + /* generic pin config decoded */ + pin_mmio->config = imx_pinconf_parse_generic_config(np, ipctl); + } else { + /* legacy pin config read from devicetree */ + config = be32_to_cpu(*list++); + + /* SION bit is in mux register */ + if (config & IMX_PAD_SION) + pin_mmio->mux_mode |= IOMUXC_CONFIG_SION; + pin_mmio->config = config & ~IMX_PAD_SION; + } + + *list_p = list; + + dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[*pin_id].name, + pin_mmio->mux_mode, pin_mmio->config); +} static int imx_pinctrl_parse_groups(struct device_node *np, struct group_desc *grp, @@ -428,14 +570,16 @@ static int imx_pinctrl_parse_groups(struct device_node *np, u32 index) { const struct imx_pinctrl_soc_info *info = ipctl->info; + struct imx_pin *pin; int size, pin_size; const __be32 *list; int i; - u32 config; dev_dbg(ipctl->dev, "group(%d): %pOFn\n", index, np); - if (info->flags & SHARE_MUX_CONF_REG) + if (info->flags & IMX_USE_SCU) + pin_size = FSL_SCU_PIN_SIZE; + else if (info->flags & SHARE_MUX_CONF_REG) pin_size = FSL_PIN_SHARE_SIZE; else pin_size = FSL_PIN_SIZE; @@ -472,9 +616,6 @@ static int imx_pinctrl_parse_groups(struct device_node *np, return -EINVAL; } - /* first try to parse the generic pin config */ - config = imx_pinconf_parse_generic_config(np, ipctl); - grp->num_pins = size / pin_size; grp->data = devm_kcalloc(ipctl->dev, grp->num_pins, sizeof(struct imx_pin), @@ -486,48 +627,13 @@ static int imx_pinctrl_parse_groups(struct device_node *np, return -ENOMEM; for (i = 0; i < grp->num_pins; i++) { - u32 mux_reg = be32_to_cpu(*list++); - u32 conf_reg; - unsigned int pin_id; - struct imx_pin_reg *pin_reg; - struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; - - if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) - mux_reg = -1; - - if (info->flags & SHARE_MUX_CONF_REG) { - conf_reg = mux_reg; - } else { - conf_reg = be32_to_cpu(*list++); - if (!conf_reg) - conf_reg = -1; - } - - pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; - pin_reg = &ipctl->pin_regs[pin_id]; - pin->pin = pin_id; - grp->pins[i] = pin_id; - pin_reg->mux_reg = mux_reg; - pin_reg->conf_reg = conf_reg; - pin->input_reg = be32_to_cpu(*list++); - pin->mux_mode = be32_to_cpu(*list++); - pin->input_val = be32_to_cpu(*list++); - - if (info->generic_pinconf) { - /* generic pin config decoded */ - pin->config = config; - } else { - /* legacy pin config read from devicetree */ - config = be32_to_cpu(*list++); - - /* SION bit is in mux register */ - if (config & IMX_PAD_SION) - pin->mux_mode |= IOMUXC_CONFIG_SION; - pin->config = config & ~IMX_PAD_SION; - } - - dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name, - pin->mux_mode, pin->config); + pin = &((struct imx_pin *)(grp->data))[i]; + if (info->flags & IMX_USE_SCU) + imx_pinctrl_parse_pin_scu(ipctl, &grp->pins[i], + pin, &list); + else + imx_pinctrl_parse_pin_mmio(ipctl, &grp->pins[i], + pin, &list, np); } return 0; @@ -699,35 +805,37 @@ int imx_pinctrl_probe(struct platform_device *pdev, if (!ipctl) return -ENOMEM; - ipctl->pin_regs = devm_kmalloc_array(&pdev->dev, - info->npins, sizeof(*ipctl->pin_regs), - GFP_KERNEL); - if (!ipctl->pin_regs) - return -ENOMEM; + if (!(info->flags & IMX_USE_SCU)) { + ipctl->pin_regs = devm_kmalloc_array(&pdev->dev, info->npins, + sizeof(*ipctl->pin_regs), + GFP_KERNEL); + if (!ipctl->pin_regs) + return -ENOMEM; - for (i = 0; i < info->npins; i++) { - ipctl->pin_regs[i].mux_reg = -1; - ipctl->pin_regs[i].conf_reg = -1; - } + for (i = 0; i < info->npins; i++) { + ipctl->pin_regs[i].mux_reg = -1; + ipctl->pin_regs[i].conf_reg = -1; + } - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - ipctl->base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(ipctl->base)) - return PTR_ERR(ipctl->base); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + ipctl->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(ipctl->base)) + return PTR_ERR(ipctl->base); - if (of_property_read_bool(dev_np, "fsl,input-sel")) { - np = of_parse_phandle(dev_np, "fsl,input-sel", 0); - if (!np) { - dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n"); - return -EINVAL; - } + if (of_property_read_bool(dev_np, "fsl,input-sel")) { + np = of_parse_phandle(dev_np, "fsl,input-sel", 0); + if (!np) { + dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n"); + return -EINVAL; + } - ipctl->input_sel_base = of_iomap(np, 0); - of_node_put(np); - if (!ipctl->input_sel_base) { - dev_err(&pdev->dev, - "iomuxc input select base address not found\n"); - return -ENOMEM; + ipctl->input_sel_base = of_iomap(np, 0); + of_node_put(np); + if (!ipctl->input_sel_base) { + dev_err(&pdev->dev, + "iomuxc input select base address not found\n"); + return -ENOMEM; + } } } diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h index 4b8225ccb03a..98a4889af4ef 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.h +++ b/drivers/pinctrl/freescale/pinctrl-imx.h @@ -19,16 +19,14 @@ struct platform_device; extern struct pinmux_ops imx_pmx_ops; /** - * struct imx_pin - describes a single i.MX pin - * @pin: the pin_id of this pin + * struct imx_pin_mmio - MMIO pin configurations * @mux_mode: the mux mode for this pin. * @input_reg: the select input register offset for this pin if any * 0 if no select input setting needed. * @input_val: the select input value for this pin. * @configs: the config for this pin. */ -struct imx_pin { - unsigned int pin; +struct imx_pin_mmio { unsigned int mux_mode; u16 input_reg; unsigned int input_val; @@ -36,6 +34,29 @@ struct imx_pin { }; /** + * struct imx_pin_scu - SCU pin configurations + * @mux: the mux mode for this pin. + * @configs: the config for this pin. + */ +struct imx_pin_scu { + unsigned int mux_mode; + unsigned long config; +}; + +/** + * struct imx_pin - describes a single i.MX pin + * @pin: the pin_id of this pin + * @conf: config type of this pin, either mmio or scu + */ +struct imx_pin { + unsigned int pin; + union { + struct imx_pin_mmio mmio; + struct imx_pin_scu scu; + } conf; +}; + +/** * struct imx_pin_reg - describe a pin reg map * @mux_reg: mux register offset * @conf_reg: config register offset @@ -99,8 +120,9 @@ struct imx_pinctrl { #define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \ { .param = p, .mask = m, .shift = o, .invert = true, } -#define SHARE_MUX_CONF_REG 0x1 -#define ZERO_OFFSET_VALID 0x2 +#define SHARE_MUX_CONF_REG BIT(0) +#define ZERO_OFFSET_VALID BIT(1) +#define IMX_USE_SCU BIT(2) #define NO_MUX 0x0 #define NO_PAD 0x0 @@ -113,4 +135,37 @@ struct imx_pinctrl { int imx_pinctrl_probe(struct platform_device *pdev, const struct imx_pinctrl_soc_info *info); + +#ifdef CONFIG_PINCTRL_IMX_SCU +#define BM_PAD_CTL_GP_ENABLE BIT(30) +#define BM_PAD_CTL_IFMUX_ENABLE BIT(31) +#define BP_PAD_CTL_IFMUX 27 + +int imx_pinctrl_sc_ipc_init(struct platform_device *pdev); +int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id, + unsigned long *config); +int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id, + unsigned long *configs, unsigned num_configs); +void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl, + unsigned int *pin_id, struct imx_pin *pin, + const __be32 **list_p); +#else +static inline int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, + unsigned pin_id, unsigned long *config) +{ + return -EINVAL; +} +static inline int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, + unsigned pin_id, unsigned long *configs, + unsigned num_configs) +{ + return -EINVAL; +} +static inline void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl, + unsigned int *pin_id, + struct imx_pin *pin, + const __be32 **list_p) +{ +} +#endif #endif /* __DRIVERS_PINCTRL_IMX_H */ diff --git a/drivers/pinctrl/freescale/pinctrl-imx7ulp.c b/drivers/pinctrl/freescale/pinctrl-imx7ulp.c index f521bdb53f62..922ff73c7087 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx7ulp.c +++ b/drivers/pinctrl/freescale/pinctrl-imx7ulp.c @@ -256,46 +256,8 @@ static const struct pinctrl_pin_desc imx7ulp_pinctrl_pads[] = { #define BM_OBE_ENABLED BIT(17) #define BM_IBE_ENABLED BIT(16) -#define BM_LK_ENABLED BIT(15) #define BM_MUX_MODE 0xf00 #define BP_MUX_MODE 8 -#define BM_PULL_ENABLED BIT(1) - -static const struct imx_cfg_params_decode imx7ulp_cfg_decodes[] = { - IMX_CFG_PARAMS_DECODE(PIN_CONFIG_DRIVE_STRENGTH, BIT(6), 6), - IMX_CFG_PARAMS_DECODE(PIN_CONFIG_DRIVE_PUSH_PULL, BIT(5), 5), - IMX_CFG_PARAMS_DECODE(PIN_CONFIG_SLEW_RATE, BIT(2), 2), - IMX_CFG_PARAMS_DECODE(PIN_CONFIG_BIAS_DISABLE, BIT(1), 1), - IMX_CFG_PARAMS_DECODE(PIN_CONFIG_BIAS_PULL_UP, BIT(0), 0), - - IMX_CFG_PARAMS_DECODE_INVERT(PIN_CONFIG_DRIVE_OPEN_DRAIN, BIT(5), 5), - IMX_CFG_PARAMS_DECODE_INVERT(PIN_CONFIG_BIAS_PULL_DOWN, BIT(0), 0), -}; - -static void imx7ulp_cfg_params_fixup(unsigned long *configs, - unsigned int num_configs, - u32 *raw_config) -{ - enum pin_config_param param; - u32 param_val; - int i; - - /* lock field disabled */ - *raw_config &= ~BM_LK_ENABLED; - - for (i = 0; i < num_configs; i++) { - param = pinconf_to_config_param(configs[i]); - param_val = pinconf_to_config_argument(configs[i]); - - if ((param == PIN_CONFIG_BIAS_PULL_UP) || - (param == PIN_CONFIG_BIAS_PULL_DOWN)) { - /* pull enabled */ - *raw_config |= BM_PULL_ENABLED; - - return; - } - } -} static int imx7ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, @@ -326,10 +288,6 @@ static const struct imx_pinctrl_soc_info imx7ulp_pinctrl_info = { .gpio_set_direction = imx7ulp_pmx_gpio_set_direction, .mux_mask = BM_MUX_MODE, .mux_shift = BP_MUX_MODE, - .generic_pinconf = true, - .decodes = imx7ulp_cfg_decodes, - .num_decodes = ARRAY_SIZE(imx7ulp_cfg_decodes), - .fixup = imx7ulp_cfg_params_fixup, }; static const struct of_device_id imx7ulp_pinctrl_of_match[] = { diff --git a/drivers/pinctrl/freescale/pinctrl-imx8qxp.c b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c new file mode 100644 index 000000000000..1131dc3c084e --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +#include <dt-bindings/pinctrl/pads-imx8qxp.h> +#include <linux/err.h> +#include <linux/firmware/imx/sci.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-imx.h" + +static const struct pinctrl_pin_desc imx8qxp_pinctrl_pads[] = { + IMX_PINCTRL_PIN(IMX8QXP_PCIE_CTRL0_PERST_B), + IMX_PINCTRL_PIN(IMX8QXP_PCIE_CTRL0_CLKREQ_B), + IMX_PINCTRL_PIN(IMX8QXP_PCIE_CTRL0_WAKE_B), + IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_PCIESEP), + IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC0), + IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC1), + IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC2), + IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC3), + IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_3V3_USB3IO), + IMX_PINCTRL_PIN(IMX8QXP_EMMC0_CLK), + IMX_PINCTRL_PIN(IMX8QXP_EMMC0_CMD), + IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA0), + IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA1), + IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA2), + IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA3), + IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX0), + IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA4), + IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA5), + IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA6), + IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA7), + IMX_PINCTRL_PIN(IMX8QXP_EMMC0_STROBE), + IMX_PINCTRL_PIN(IMX8QXP_EMMC0_RESET_B), + IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX1), + IMX_PINCTRL_PIN(IMX8QXP_USDHC1_RESET_B), + IMX_PINCTRL_PIN(IMX8QXP_USDHC1_VSELECT), + IMX_PINCTRL_PIN(IMX8QXP_CTL_NAND_RE_P_N), + IMX_PINCTRL_PIN(IMX8QXP_USDHC1_WP), + IMX_PINCTRL_PIN(IMX8QXP_USDHC1_CD_B), + IMX_PINCTRL_PIN(IMX8QXP_CTL_NAND_DQS_P_N), + IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSELSEP), + IMX_PINCTRL_PIN(IMX8QXP_USDHC1_CLK), + IMX_PINCTRL_PIN(IMX8QXP_USDHC1_CMD), + IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA0), + IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA1), + IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA2), + IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA3), + IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSEL3), + IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXC), + IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TX_CTL), + IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD0), + IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD1), + IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD2), + IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD3), + IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0), + IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXC), + IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RX_CTL), + IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD0), + IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD1), + IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD2), + IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD3), + IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1), + IMX_PINCTRL_PIN(IMX8QXP_ENET0_REFCLK_125M_25M), + IMX_PINCTRL_PIN(IMX8QXP_ENET0_MDIO), + IMX_PINCTRL_PIN(IMX8QXP_ENET0_MDC), + IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOCT), + IMX_PINCTRL_PIN(IMX8QXP_ESAI0_FSR), + IMX_PINCTRL_PIN(IMX8QXP_ESAI0_FST), + IMX_PINCTRL_PIN(IMX8QXP_ESAI0_SCKR), + IMX_PINCTRL_PIN(IMX8QXP_ESAI0_SCKT), + IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX0), + IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX1), + IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX2_RX3), + IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX3_RX2), + IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX4_RX1), + IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX5_RX0), + IMX_PINCTRL_PIN(IMX8QXP_SPDIF0_RX), + IMX_PINCTRL_PIN(IMX8QXP_SPDIF0_TX), + IMX_PINCTRL_PIN(IMX8QXP_SPDIF0_EXT_CLK), + IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB), + IMX_PINCTRL_PIN(IMX8QXP_SPI3_SCK), + IMX_PINCTRL_PIN(IMX8QXP_SPI3_SDO), + IMX_PINCTRL_PIN(IMX8QXP_SPI3_SDI), + IMX_PINCTRL_PIN(IMX8QXP_SPI3_CS0), + IMX_PINCTRL_PIN(IMX8QXP_SPI3_CS1), + IMX_PINCTRL_PIN(IMX8QXP_MCLK_IN1), + IMX_PINCTRL_PIN(IMX8QXP_MCLK_IN0), + IMX_PINCTRL_PIN(IMX8QXP_MCLK_OUT0), + IMX_PINCTRL_PIN(IMX8QXP_UART1_TX), + IMX_PINCTRL_PIN(IMX8QXP_UART1_RX), + IMX_PINCTRL_PIN(IMX8QXP_UART1_RTS_B), + IMX_PINCTRL_PIN(IMX8QXP_UART1_CTS_B), + IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHK), + IMX_PINCTRL_PIN(IMX8QXP_SAI0_TXD), + IMX_PINCTRL_PIN(IMX8QXP_SAI0_TXC), + IMX_PINCTRL_PIN(IMX8QXP_SAI0_RXD), + IMX_PINCTRL_PIN(IMX8QXP_SAI0_TXFS), + IMX_PINCTRL_PIN(IMX8QXP_SAI1_RXD), + IMX_PINCTRL_PIN(IMX8QXP_SAI1_RXC), + IMX_PINCTRL_PIN(IMX8QXP_SAI1_RXFS), + IMX_PINCTRL_PIN(IMX8QXP_SPI2_CS0), + IMX_PINCTRL_PIN(IMX8QXP_SPI2_SDO), + IMX_PINCTRL_PIN(IMX8QXP_SPI2_SDI), + IMX_PINCTRL_PIN(IMX8QXP_SPI2_SCK), + IMX_PINCTRL_PIN(IMX8QXP_SPI0_SCK), + IMX_PINCTRL_PIN(IMX8QXP_SPI0_SDI), + IMX_PINCTRL_PIN(IMX8QXP_SPI0_SDO), + IMX_PINCTRL_PIN(IMX8QXP_SPI0_CS1), + IMX_PINCTRL_PIN(IMX8QXP_SPI0_CS0), + IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHT), + IMX_PINCTRL_PIN(IMX8QXP_ADC_IN1), + IMX_PINCTRL_PIN(IMX8QXP_ADC_IN0), + IMX_PINCTRL_PIN(IMX8QXP_ADC_IN3), + IMX_PINCTRL_PIN(IMX8QXP_ADC_IN2), + IMX_PINCTRL_PIN(IMX8QXP_ADC_IN5), + IMX_PINCTRL_PIN(IMX8QXP_ADC_IN4), + IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN0_RX), + IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN0_TX), + IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN1_RX), + IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN1_TX), + IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN2_RX), + IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN2_TX), + IMX_PINCTRL_PIN(IMX8QXP_UART0_RX), + IMX_PINCTRL_PIN(IMX8QXP_UART0_TX), + IMX_PINCTRL_PIN(IMX8QXP_UART2_TX), + IMX_PINCTRL_PIN(IMX8QXP_UART2_RX), + IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOLH), + IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_I2C0_SCL), + IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_I2C0_SDA), + IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_GPIO0_00), + IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_GPIO0_01), + IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_I2C0_SCL), + IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_I2C0_SDA), + IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_GPIO0_00), + IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_GPIO0_01), + IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO), + IMX_PINCTRL_PIN(IMX8QXP_JTAG_TRST_B), + IMX_PINCTRL_PIN(IMX8QXP_PMIC_I2C_SCL), + IMX_PINCTRL_PIN(IMX8QXP_PMIC_I2C_SDA), + IMX_PINCTRL_PIN(IMX8QXP_PMIC_INT_B), + IMX_PINCTRL_PIN(IMX8QXP_SCU_GPIO0_00), + IMX_PINCTRL_PIN(IMX8QXP_SCU_GPIO0_01), + IMX_PINCTRL_PIN(IMX8QXP_SCU_PMIC_STANDBY), + IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE0), + IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE1), + IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE2), + IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE3), + IMX_PINCTRL_PIN(IMX8QXP_CSI_D00), + IMX_PINCTRL_PIN(IMX8QXP_CSI_D01), + IMX_PINCTRL_PIN(IMX8QXP_CSI_D02), + IMX_PINCTRL_PIN(IMX8QXP_CSI_D03), + IMX_PINCTRL_PIN(IMX8QXP_CSI_D04), + IMX_PINCTRL_PIN(IMX8QXP_CSI_D05), + IMX_PINCTRL_PIN(IMX8QXP_CSI_D06), + IMX_PINCTRL_PIN(IMX8QXP_CSI_D07), + IMX_PINCTRL_PIN(IMX8QXP_CSI_HSYNC), + IMX_PINCTRL_PIN(IMX8QXP_CSI_VSYNC), + IMX_PINCTRL_PIN(IMX8QXP_CSI_PCLK), + IMX_PINCTRL_PIN(IMX8QXP_CSI_MCLK), + IMX_PINCTRL_PIN(IMX8QXP_CSI_EN), + IMX_PINCTRL_PIN(IMX8QXP_CSI_RESET), + IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHD), + IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_MCLK_OUT), + IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_I2C0_SCL), + IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_I2C0_SDA), + IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_GPIO0_01), + IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_GPIO0_00), + IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA0), + IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA1), + IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA2), + IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA3), + IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DQS), + IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_SS0_B), + IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_SS1_B), + IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_SCLK), + IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0A), + IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_SCLK), + IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA0), + IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA1), + IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA2), + IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA3), + IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DQS), + IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_SS0_B), + IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_SS1_B), + IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B), +}; + +static struct imx_pinctrl_soc_info imx8qxp_pinctrl_info = { + .pins = imx8qxp_pinctrl_pads, + .npins = ARRAY_SIZE(imx8qxp_pinctrl_pads), + .flags = IMX_USE_SCU, +}; + +static const struct of_device_id imx8qxp_pinctrl_of_match[] = { + { .compatible = "fsl,imx8qxp-iomuxc", }, + { /* sentinel */ } +}; + +static int imx8qxp_pinctrl_probe(struct platform_device *pdev) +{ + int ret; + + ret = imx_pinctrl_sc_ipc_init(pdev); + if (ret) + return ret; + + return imx_pinctrl_probe(pdev, &imx8qxp_pinctrl_info); +} + +static struct platform_driver imx8qxp_pinctrl_driver = { + .driver = { + .name = "imx8qxp-pinctrl", + .of_match_table = of_match_ptr(imx8qxp_pinctrl_of_match), + .suppress_bind_attrs = true, + }, + .probe = imx8qxp_pinctrl_probe, +}; + +static int __init imx8qxp_pinctrl_init(void) +{ + return platform_driver_register(&imx8qxp_pinctrl_driver); +} +arch_initcall(imx8qxp_pinctrl_init); diff --git a/drivers/pinctrl/freescale/pinctrl-scu.c b/drivers/pinctrl/freescale/pinctrl-scu.c new file mode 100644 index 000000000000..83e69c0f39e6 --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-scu.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +#include <linux/err.h> +#include <linux/firmware/imx/sci.h> +#include <linux/of_address.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> + +#include "../core.h" +#include "pinctrl-imx.h" + +enum pad_func_e { + IMX_SC_PAD_FUNC_SET = 15, + IMX_SC_PAD_FUNC_GET = 16, +}; + +struct imx_sc_msg_req_pad_set { + struct imx_sc_rpc_msg hdr; + u32 val; + u16 pad; +} __packed; + +struct imx_sc_msg_req_pad_get { + struct imx_sc_rpc_msg hdr; + u16 pad; +} __packed; + +struct imx_sc_msg_resp_pad_get { + struct imx_sc_rpc_msg hdr; + u32 val; +} __packed; + +struct imx_sc_ipc *pinctrl_ipc_handle; + +int imx_pinctrl_sc_ipc_init(struct platform_device *pdev) +{ + return imx_scu_get_handle(&pinctrl_ipc_handle); +} + +int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id, + unsigned long *config) +{ + struct imx_sc_msg_req_pad_get msg; + struct imx_sc_msg_resp_pad_get *resp; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + int ret; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_PAD; + hdr->func = IMX_SC_PAD_FUNC_GET; + hdr->size = 2; + + msg.pad = pin_id; + + ret = imx_scu_call_rpc(pinctrl_ipc_handle, &msg, true); + if (ret) + return ret; + + resp = (struct imx_sc_msg_resp_pad_get *)&msg; + *config = resp->val; + + return 0; +} + +int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id, + unsigned long *configs, unsigned num_configs) +{ + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + struct imx_sc_msg_req_pad_set msg; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + unsigned int mux = configs[0]; + unsigned int conf = configs[1]; + unsigned int val; + int ret; + + /* + * Set mux and conf together in one IPC call + */ + WARN_ON(num_configs != 2); + + val = conf | BM_PAD_CTL_IFMUX_ENABLE | BM_PAD_CTL_GP_ENABLE; + val |= mux << BP_PAD_CTL_IFMUX; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_PAD; + hdr->func = IMX_SC_PAD_FUNC_SET; + hdr->size = 3; + + msg.pad = pin_id; + msg.val = val; + + ret = imx_scu_call_rpc(pinctrl_ipc_handle, &msg, true); + + dev_dbg(ipctl->dev, "write: pin_id %u config 0x%x val 0x%x\n", + pin_id, conf, val); + + return ret; +} + +void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl, + unsigned int *pin_id, struct imx_pin *pin, + const __be32 **list_p) +{ + const struct imx_pinctrl_soc_info *info = ipctl->info; + struct imx_pin_scu *pin_scu = &pin->conf.scu; + const __be32 *list = *list_p; + + pin->pin = be32_to_cpu(*list++); + *pin_id = pin->pin; + pin_scu->mux_mode = be32_to_cpu(*list++); + pin_scu->config = be32_to_cpu(*list++); + *list_p = list; + + dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin->pin].name, + pin_scu->mux_mode, pin_scu->config); +} diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 9d142e1da567..d8cb5840724e 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -3,7 +3,7 @@ menu "MediaTek pinctrl drivers" config EINT_MTK bool "MediaTek External Interrupt Support" - depends on PINCTRL_MTK || PINCTRL_MTK_MOORE || COMPILE_TEST + depends on PINCTRL_MTK || PINCTRL_MTK_MOORE || PINCTRL_MTK_PARIS || COMPILE_TEST select GPIOLIB select IRQ_DOMAIN @@ -48,6 +48,12 @@ config PINCTRL_MT7623 depends on PINCTRL_MTK_MOORE default y +config PINCTRL_MT7629 + bool "Mediatek MT7629 pin control" + depends on MACH_MT7629 || COMPILE_TEST + depends on PINCTRL_MTK_MOORE + default y + config PINCTRL_MT8135 bool "Mediatek MT8135 pin control" depends on MACH_MT8135 || COMPILE_TEST @@ -77,6 +83,13 @@ config PINCTRL_MT6765 default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS +config PINCTRL_MT6797 + bool "Mediatek MT6797 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_PARIS + config PINCTRL_MT7622 bool "MediaTek MT7622 pin control" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 70d800054f69..4b4e2eaf6f2d 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -11,8 +11,10 @@ obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o +obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o +obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c index 3133ec0f2e67..aa1068d2867f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-moore.c +++ b/drivers/pinctrl/mediatek/pinctrl-moore.c @@ -310,8 +310,8 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, case PIN_CONFIG_DRIVE_STRENGTH: if (hw->soc->drive_set) { err = hw->soc->drive_set(hw, desc, arg); - if (err) - return err; + if (err) + return err; } else { err = -ENOTSUPP; } diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6797.c b/drivers/pinctrl/mediatek/pinctrl-mt6797.c new file mode 100644 index 000000000000..adebe4333ed9 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt6797.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Based on pinctrl-mt6765.c + * + * Copyright (C) 2018 MediaTek Inc. + * + * Author: ZH Chen <zh.chen@mediatek.com> + * + * Copyright (C) Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + * + */ + +#include "pinctrl-mtk-mt6797.h" +#include "pinctrl-paris.h" + +/* + * MT6797 have multiple bases to program pin configuration listed as the below: + * gpio:0x10005000, iocfg[l]:0x10002000, iocfg[b]:0x10002400, + * iocfg[r]:0x10002800, iocfg[t]:0x10002C00. + * _i_base could be used to indicate what base the pin should be mapped into. + */ + +static const struct mtk_pin_field_calc mt6797_pin_mode_range[] = { + PIN_FIELD(0, 261, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt6797_pin_dir_range[] = { + PIN_FIELD(0, 261, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6797_pin_di_range[] = { + PIN_FIELD(0, 261, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6797_pin_do_range[] = { + PIN_FIELD(0, 261, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_reg_calc mt6797_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6797_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6797_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6797_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6797_pin_do_range), +}; + +static const char * const mt6797_pinctrl_register_base_names[] = { + "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt", +}; + +static const struct mtk_pin_soc mt6797_data = { + .reg_cal = mt6797_reg_cals, + .pins = mtk_pins_mt6797, + .npins = ARRAY_SIZE(mtk_pins_mt6797), + .ngrps = ARRAY_SIZE(mtk_pins_mt6797), + .gpio_m = 0, + .base_names = mt6797_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt6797_pinctrl_register_base_names), +}; + +static const struct of_device_id mt6797_pinctrl_of_match[] = { + { .compatible = "mediatek,mt6797-pinctrl", }, + { } +}; + +static int mt6797_pinctrl_probe(struct platform_device *pdev) +{ + return mtk_paris_pinctrl_probe(pdev, &mt6797_data); +} + +static struct platform_driver mt6797_pinctrl_driver = { + .driver = { + .name = "mt6797-pinctrl", + .of_match_table = mt6797_pinctrl_of_match, + }, + .probe = mt6797_pinctrl_probe, +}; + +static int __init mt6797_pinctrl_init(void) +{ + return platform_driver_register(&mt6797_pinctrl_driver); +} +arch_initcall(mt6797_pinctrl_init); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7629.c b/drivers/pinctrl/mediatek/pinctrl-mt7629.c new file mode 100644 index 000000000000..b5f0fa43245f --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c @@ -0,0 +1,450 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * The MT7629 driver based on Linux generic pinctrl binding. + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee <ryder.lee@mediatek.com> + */ + +#include "pinctrl-moore.h" + +#define MT7629_PIN(_number, _name, _eint_n) \ + MTK_PIN(_number, _name, 0, _eint_n, DRV_GRP1) + +static const struct mtk_pin_field_calc mt7629_pin_mode_range[] = { + PIN_FIELD(0, 78, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt7629_pin_dir_range[] = { + PIN_FIELD(0, 78, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7629_pin_di_range[] = { + PIN_FIELD(0, 78, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7629_pin_do_range[] = { + PIN_FIELD(0, 78, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7629_pin_ies_range[] = { + PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1), + PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1), + PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1), + PIN_FIELD(33, 48, 0x4000, 0x10, 0, 1), + PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1), + PIN_FIELD(51, 69, 0x6000, 0x10, 0, 1), + PIN_FIELD(70, 78, 0x7000, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7629_pin_smt_range[] = { + PIN_FIELD(0, 10, 0x1100, 0x10, 0, 1), + PIN_FIELD(11, 18, 0x2100, 0x10, 0, 1), + PIN_FIELD(19, 32, 0x3100, 0x10, 0, 1), + PIN_FIELD(33, 48, 0x4100, 0x10, 0, 1), + PIN_FIELD(49, 50, 0x5100, 0x10, 0, 1), + PIN_FIELD(51, 69, 0x6100, 0x10, 0, 1), + PIN_FIELD(70, 78, 0x7100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7629_pin_pullen_range[] = { + PIN_FIELD(0, 10, 0x1400, 0x10, 0, 1), + PIN_FIELD(11, 18, 0x2400, 0x10, 0, 1), + PIN_FIELD(19, 32, 0x3400, 0x10, 0, 1), + PIN_FIELD(33, 48, 0x4400, 0x10, 0, 1), + PIN_FIELD(49, 50, 0x5400, 0x10, 0, 1), + PIN_FIELD(51, 69, 0x6400, 0x10, 0, 1), + PIN_FIELD(70, 78, 0x7400, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7629_pin_pullsel_range[] = { + PIN_FIELD(0, 10, 0x1500, 0x10, 0, 1), + PIN_FIELD(11, 18, 0x2500, 0x10, 0, 1), + PIN_FIELD(19, 32, 0x3500, 0x10, 0, 1), + PIN_FIELD(33, 48, 0x4500, 0x10, 0, 1), + PIN_FIELD(49, 50, 0x5500, 0x10, 0, 1), + PIN_FIELD(51, 69, 0x6500, 0x10, 0, 1), + PIN_FIELD(70, 78, 0x7500, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7629_pin_drv_range[] = { + PIN_FIELD(0, 10, 0x1600, 0x10, 0, 4), + PIN_FIELD(11, 18, 0x2600, 0x10, 0, 4), + PIN_FIELD(19, 32, 0x3600, 0x10, 0, 4), + PIN_FIELD(33, 48, 0x4600, 0x10, 0, 4), + PIN_FIELD(49, 50, 0x5600, 0x10, 0, 4), + PIN_FIELD(51, 69, 0x6600, 0x10, 0, 4), + PIN_FIELD(70, 78, 0x7600, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt7629_pin_tdsel_range[] = { + PIN_FIELD(0, 10, 0x1200, 0x10, 0, 4), + PIN_FIELD(11, 18, 0x2200, 0x10, 0, 4), + PIN_FIELD(19, 32, 0x3200, 0x10, 0, 4), + PIN_FIELD(33, 48, 0x4200, 0x10, 0, 4), + PIN_FIELD(49, 50, 0x5200, 0x10, 0, 4), + PIN_FIELD(51, 69, 0x6200, 0x10, 0, 4), + PIN_FIELD(70, 78, 0x7200, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt7629_pin_rdsel_range[] = { + PIN_FIELD(0, 10, 0x1300, 0x10, 0, 4), + PIN_FIELD(11, 18, 0x2300, 0x10, 0, 4), + PIN_FIELD(19, 32, 0x3300, 0x10, 0, 4), + PIN_FIELD(33, 48, 0x4300, 0x10, 0, 4), + PIN_FIELD(49, 50, 0x5300, 0x10, 0, 4), + PIN_FIELD(51, 69, 0x6300, 0x10, 0, 4), + PIN_FIELD(70, 78, 0x7300, 0x10, 0, 4), +}; + +static const struct mtk_pin_reg_calc mt7629_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7629_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7629_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7629_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7629_pin_do_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7629_pin_ies_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7629_pin_smt_range), + [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt7629_pin_pullsel_range), + [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt7629_pin_pullen_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7629_pin_drv_range), + [PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt7629_pin_tdsel_range), + [PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt7629_pin_rdsel_range), +}; + +static const struct mtk_pin_desc mt7629_pins[] = { + MT7629_PIN(0, "TOP_5G_CLK", 53), + MT7629_PIN(1, "TOP_5G_DATA", 54), + MT7629_PIN(2, "WF0_5G_HB0", 55), + MT7629_PIN(3, "WF0_5G_HB1", 56), + MT7629_PIN(4, "WF0_5G_HB2", 57), + MT7629_PIN(5, "WF0_5G_HB3", 58), + MT7629_PIN(6, "WF0_5G_HB4", 59), + MT7629_PIN(7, "WF0_5G_HB5", 60), + MT7629_PIN(8, "WF0_5G_HB6", 61), + MT7629_PIN(9, "XO_REQ", 9), + MT7629_PIN(10, "TOP_RST_N", 10), + MT7629_PIN(11, "SYS_WATCHDOG", 11), + MT7629_PIN(12, "EPHY_LED0_N_JTDO", 12), + MT7629_PIN(13, "EPHY_LED1_N_JTDI", 13), + MT7629_PIN(14, "EPHY_LED2_N_JTMS", 14), + MT7629_PIN(15, "EPHY_LED3_N_JTCLK", 15), + MT7629_PIN(16, "EPHY_LED4_N_JTRST_N", 16), + MT7629_PIN(17, "WF2G_LED_N", 17), + MT7629_PIN(18, "WF5G_LED_N", 18), + MT7629_PIN(19, "I2C_SDA", 19), + MT7629_PIN(20, "I2C_SCL", 20), + MT7629_PIN(21, "GPIO_9", 21), + MT7629_PIN(22, "GPIO_10", 22), + MT7629_PIN(23, "GPIO_11", 23), + MT7629_PIN(24, "GPIO_12", 24), + MT7629_PIN(25, "UART1_TXD", 25), + MT7629_PIN(26, "UART1_RXD", 26), + MT7629_PIN(27, "UART1_CTS", 27), + MT7629_PIN(28, "UART1_RTS", 28), + MT7629_PIN(29, "UART2_TXD", 29), + MT7629_PIN(30, "UART2_RXD", 30), + MT7629_PIN(31, "UART2_CTS", 31), + MT7629_PIN(32, "UART2_RTS", 32), + MT7629_PIN(33, "MDI_TP_P1", 33), + MT7629_PIN(34, "MDI_TN_P1", 34), + MT7629_PIN(35, "MDI_RP_P1", 35), + MT7629_PIN(36, "MDI_RN_P1", 36), + MT7629_PIN(37, "MDI_RP_P2", 37), + MT7629_PIN(38, "MDI_RN_P2", 38), + MT7629_PIN(39, "MDI_TP_P2", 39), + MT7629_PIN(40, "MDI_TN_P2", 40), + MT7629_PIN(41, "MDI_TP_P3", 41), + MT7629_PIN(42, "MDI_TN_P3", 42), + MT7629_PIN(43, "MDI_RP_P3", 43), + MT7629_PIN(44, "MDI_RN_P3", 44), + MT7629_PIN(45, "MDI_RP_P4", 45), + MT7629_PIN(46, "MDI_RN_P4", 46), + MT7629_PIN(47, "MDI_TP_P4", 47), + MT7629_PIN(48, "MDI_TN_P4", 48), + MT7629_PIN(49, "SMI_MDC", 49), + MT7629_PIN(50, "SMI_MDIO", 50), + MT7629_PIN(51, "PCIE_PERESET_N", 51), + MT7629_PIN(52, "PWM_0", 52), + MT7629_PIN(53, "GPIO_0", 0), + MT7629_PIN(54, "GPIO_1", 1), + MT7629_PIN(55, "GPIO_2", 2), + MT7629_PIN(56, "GPIO_3", 3), + MT7629_PIN(57, "GPIO_4", 4), + MT7629_PIN(58, "GPIO_5", 5), + MT7629_PIN(59, "GPIO_6", 6), + MT7629_PIN(60, "GPIO_7", 7), + MT7629_PIN(61, "GPIO_8", 8), + MT7629_PIN(62, "SPI_CLK", 62), + MT7629_PIN(63, "SPI_CS", 63), + MT7629_PIN(64, "SPI_MOSI", 64), + MT7629_PIN(65, "SPI_MISO", 65), + MT7629_PIN(66, "SPI_WP", 66), + MT7629_PIN(67, "SPI_HOLD", 67), + MT7629_PIN(68, "UART0_TXD", 68), + MT7629_PIN(69, "UART0_RXD", 69), + MT7629_PIN(70, "TOP_2G_CLK", 70), + MT7629_PIN(71, "TOP_2G_DATA", 71), + MT7629_PIN(72, "WF0_2G_HB0", 72), + MT7629_PIN(73, "WF0_2G_HB1", 73), + MT7629_PIN(74, "WF0_2G_HB2", 74), + MT7629_PIN(75, "WF0_2G_HB3", 75), + MT7629_PIN(76, "WF0_2G_HB4", 76), + MT7629_PIN(77, "WF0_2G_HB5", 77), + MT7629_PIN(78, "WF0_2G_HB6", 78), +}; + +/* List all groups consisting of these pins dedicated to the enablement of + * certain hardware block and the corresponding mode for all of the pins. + * The hardware probably has multiple combinations of these pinouts. + */ + +/* LED for EPHY */ +static int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, }; +static int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, }; +static int mt7629_ephy_led0_pins[] = { 12, }; +static int mt7629_ephy_led0_funcs[] = { 1, }; +static int mt7629_ephy_led1_pins[] = { 13, }; +static int mt7629_ephy_led1_funcs[] = { 1, }; +static int mt7629_ephy_led2_pins[] = { 14, }; +static int mt7629_ephy_led2_funcs[] = { 1, }; +static int mt7629_ephy_led3_pins[] = { 15, }; +static int mt7629_ephy_led3_funcs[] = { 1, }; +static int mt7629_ephy_led4_pins[] = { 16, }; +static int mt7629_ephy_led4_funcs[] = { 1, }; +static int mt7629_wf2g_led_pins[] = { 17, }; +static int mt7629_wf2g_led_funcs[] = { 1, }; +static int mt7629_wf5g_led_pins[] = { 18, }; +static int mt7629_wf5g_led_funcs[] = { 1, }; + +/* Watchdog */ +static int mt7629_watchdog_pins[] = { 11, }; +static int mt7629_watchdog_funcs[] = { 1, }; + +/* LED for GPHY */ +static int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, }; +static int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, }; +static int mt7629_gphy_led1_0_pins[] = { 21, }; +static int mt7629_gphy_led1_0_funcs[] = { 2, }; +static int mt7629_gphy_led2_0_pins[] = { 22, }; +static int mt7629_gphy_led2_0_funcs[] = { 2, }; +static int mt7629_gphy_led3_0_pins[] = { 23, }; +static int mt7629_gphy_led3_0_funcs[] = { 2, }; +static int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, }; +static int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, }; +static int mt7629_gphy_led1_1_pins[] = { 57, }; +static int mt7629_gphy_led1_1_funcs[] = { 1, }; +static int mt7629_gphy_led2_1_pins[] = { 58, }; +static int mt7629_gphy_led2_1_funcs[] = { 1, }; +static int mt7629_gphy_led3_1_pins[] = { 59, }; +static int mt7629_gphy_led3_1_funcs[] = { 1, }; + +/* I2C */ +static int mt7629_i2c_0_pins[] = { 19, 20, }; +static int mt7629_i2c_0_funcs[] = { 1, 1, }; +static int mt7629_i2c_1_pins[] = { 53, 54, }; +static int mt7629_i2c_1_funcs[] = { 1, 1, }; + +/* SPI */ +static int mt7629_spi_0_pins[] = { 21, 22, 23, 24, }; +static int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, }; +static int mt7629_spi_1_pins[] = { 62, 63, 64, 65, }; +static int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, }; +static int mt7629_spi_wp_pins[] = { 66, }; +static int mt7629_spi_wp_funcs[] = { 1, }; +static int mt7629_spi_hold_pins[] = { 67, }; +static int mt7629_spi_hold_funcs[] = { 1, }; + +/* UART */ +static int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, }; +static int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, }; +static int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, }; +static int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, }; +static int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, }; +static int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, }; +static int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, }; +static int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, }; +static int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, }; +static int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, }; +static int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, }; +static int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, }; +static int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, }; +static int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, }; +static int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, }; +static int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, }; +static int mt7629_uart0_txd_rxd_pins[] = { 68, 69, }; +static int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, }; + +/* MDC/MDIO */ +static int mt7629_mdc_mdio_pins[] = { 49, 50, }; +static int mt7629_mdc_mdio_funcs[] = { 1, 1, }; + +/* PCIE */ +static int mt7629_pcie_pereset_pins[] = { 51, }; +static int mt7629_pcie_pereset_funcs[] = { 1, }; +static int mt7629_pcie_wake_pins[] = { 55, }; +static int mt7629_pcie_wake_funcs[] = { 1, }; +static int mt7629_pcie_clkreq_pins[] = { 56, }; +static int mt7629_pcie_clkreq_funcs[] = { 1, }; + +/* PWM */ +static int mt7629_pwm_0_pins[] = { 52, }; +static int mt7629_pwm_0_funcs[] = { 1, }; +static int mt7629_pwm_1_pins[] = { 61, }; +static int mt7629_pwm_1_funcs[] = { 2, }; + +/* WF 2G */ +static int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, }; +static int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, }; + +/* WF 5G */ +static int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, }; +static int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +/* SNFI */ +static int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 }; +static int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; + +/* SPI NOR */ +static int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 }; +static int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 }; + +static const struct group_desc mt7629_groups[] = { + PINCTRL_PIN_GROUP("ephy_leds", mt7629_ephy_leds), + PINCTRL_PIN_GROUP("ephy_led0", mt7629_ephy_led0), + PINCTRL_PIN_GROUP("ephy_led1", mt7629_ephy_led1), + PINCTRL_PIN_GROUP("ephy_led2", mt7629_ephy_led2), + PINCTRL_PIN_GROUP("ephy_led3", mt7629_ephy_led3), + PINCTRL_PIN_GROUP("ephy_led4", mt7629_ephy_led4), + PINCTRL_PIN_GROUP("wf2g_led", mt7629_wf2g_led), + PINCTRL_PIN_GROUP("wf5g_led", mt7629_wf5g_led), + PINCTRL_PIN_GROUP("watchdog", mt7629_watchdog), + PINCTRL_PIN_GROUP("gphy_leds_0", mt7629_gphy_leds_0), + PINCTRL_PIN_GROUP("gphy_led1_0", mt7629_gphy_led1_0), + PINCTRL_PIN_GROUP("gphy_led2_0", mt7629_gphy_led2_0), + PINCTRL_PIN_GROUP("gphy_led3_0", mt7629_gphy_led3_0), + PINCTRL_PIN_GROUP("gphy_leds_1", mt7629_gphy_leds_1), + PINCTRL_PIN_GROUP("gphy_led1_1", mt7629_gphy_led1_1), + PINCTRL_PIN_GROUP("gphy_led2_1", mt7629_gphy_led2_1), + PINCTRL_PIN_GROUP("gphy_led3_1", mt7629_gphy_led3_1), + PINCTRL_PIN_GROUP("i2c_0", mt7629_i2c_0), + PINCTRL_PIN_GROUP("i2c_1", mt7629_i2c_1), + PINCTRL_PIN_GROUP("spi_0", mt7629_spi_0), + PINCTRL_PIN_GROUP("spi_1", mt7629_spi_1), + PINCTRL_PIN_GROUP("spi_wp", mt7629_spi_wp), + PINCTRL_PIN_GROUP("spi_hold", mt7629_spi_hold), + PINCTRL_PIN_GROUP("uart1_0_txd_rxd", mt7629_uart1_0_txd_rxd), + PINCTRL_PIN_GROUP("uart1_1_txd_rxd", mt7629_uart1_1_txd_rxd), + PINCTRL_PIN_GROUP("uart2_0_txd_rxd", mt7629_uart2_0_txd_rxd), + PINCTRL_PIN_GROUP("uart2_1_txd_rxd", mt7629_uart2_1_txd_rxd), + PINCTRL_PIN_GROUP("uart1_0_cts_rts", mt7629_uart1_0_cts_rts), + PINCTRL_PIN_GROUP("uart1_1_cts_rts", mt7629_uart1_1_cts_rts), + PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7629_uart2_0_cts_rts), + PINCTRL_PIN_GROUP("uart2_1_cts_rts", mt7629_uart2_1_cts_rts), + PINCTRL_PIN_GROUP("uart0_txd_rxd", mt7629_uart0_txd_rxd), + PINCTRL_PIN_GROUP("mdc_mdio", mt7629_mdc_mdio), + PINCTRL_PIN_GROUP("pcie_pereset", mt7629_pcie_pereset), + PINCTRL_PIN_GROUP("pcie_wake", mt7629_pcie_wake), + PINCTRL_PIN_GROUP("pcie_clkreq", mt7629_pcie_clkreq), + PINCTRL_PIN_GROUP("pwm_0", mt7629_pwm_0), + PINCTRL_PIN_GROUP("pwm_1", mt7629_pwm_1), + PINCTRL_PIN_GROUP("wf0_5g", mt7629_wf0_5g), + PINCTRL_PIN_GROUP("wf0_2g", mt7629_wf0_2g), + PINCTRL_PIN_GROUP("snfi", mt7629_snfi), + PINCTRL_PIN_GROUP("spi_nor", mt7629_snor), +}; + +/* Joint those groups owning the same capability in user point of view which + * allows that people tend to use through the device tree. + */ +static const char *mt7629_ethernet_groups[] = { "mdc_mdio", }; +static const char *mt7629_i2c_groups[] = { "i2c_0", "i2c_1", }; +static const char *mt7629_led_groups[] = { "ephy_leds", "ephy_led0", + "ephy_led1", "ephy_led2", + "ephy_led3", "ephy_led4", + "wf2g_led", "wf5g_led", + "gphy_leds_0", "gphy_led1_0", + "gphy_led2_0", "gphy_led3_0", + "gphy_leds_1", "gphy_led1_1", + "gphy_led2_1", "gphy_led3_1",}; +static const char *mt7629_pcie_groups[] = { "pcie_pereset", "pcie_wake", + "pcie_clkreq", }; +static const char *mt7629_pwm_groups[] = { "pwm_0", "pwm_1", }; +static const char *mt7629_spi_groups[] = { "spi_0", "spi_1", "spi_wp", + "spi_hold", }; +static const char *mt7629_uart_groups[] = { "uart1_0_txd_rxd", + "uart1_1_txd_rxd", + "uart2_0_txd_rxd", + "uart2_1_txd_rxd", + "uart1_0_cts_rts", + "uart1_1_cts_rts", + "uart2_0_cts_rts", + "uart2_1_cts_rts", + "uart0_txd_rxd", }; +static const char *mt7629_wdt_groups[] = { "watchdog", }; +static const char *mt7629_wifi_groups[] = { "wf0_5g", "wf0_2g", }; +static const char *mt7629_flash_groups[] = { "snfi", "spi_nor" }; + +static const struct function_desc mt7629_functions[] = { + {"eth", mt7629_ethernet_groups, ARRAY_SIZE(mt7629_ethernet_groups)}, + {"i2c", mt7629_i2c_groups, ARRAY_SIZE(mt7629_i2c_groups)}, + {"led", mt7629_led_groups, ARRAY_SIZE(mt7629_led_groups)}, + {"pcie", mt7629_pcie_groups, ARRAY_SIZE(mt7629_pcie_groups)}, + {"pwm", mt7629_pwm_groups, ARRAY_SIZE(mt7629_pwm_groups)}, + {"spi", mt7629_spi_groups, ARRAY_SIZE(mt7629_spi_groups)}, + {"uart", mt7629_uart_groups, ARRAY_SIZE(mt7629_uart_groups)}, + {"watchdog", mt7629_wdt_groups, ARRAY_SIZE(mt7629_wdt_groups)}, + {"wifi", mt7629_wifi_groups, ARRAY_SIZE(mt7629_wifi_groups)}, + {"flash", mt7629_flash_groups, ARRAY_SIZE(mt7629_flash_groups)}, +}; + +static const struct mtk_eint_hw mt7629_eint_hw = { + .port_mask = 7, + .ports = 7, + .ap_num = ARRAY_SIZE(mt7629_pins), + .db_cnt = 16, +}; + +static struct mtk_pin_soc mt7629_data = { + .reg_cal = mt7629_reg_cals, + .pins = mt7629_pins, + .npins = ARRAY_SIZE(mt7629_pins), + .grps = mt7629_groups, + .ngrps = ARRAY_SIZE(mt7629_groups), + .funcs = mt7629_functions, + .nfuncs = ARRAY_SIZE(mt7629_functions), + .eint_hw = &mt7629_eint_hw, + .gpio_m = 0, + .ies_present = true, + .base_names = mtk_default_register_base_names, + .nbase_names = ARRAY_SIZE(mtk_default_register_base_names), + .bias_disable_set = mtk_pinconf_bias_disable_set_rev1, + .bias_disable_get = mtk_pinconf_bias_disable_get_rev1, + .bias_set = mtk_pinconf_bias_set_rev1, + .bias_get = mtk_pinconf_bias_get_rev1, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, +}; + +static const struct of_device_id mt7629_pinctrl_of_match[] = { + { .compatible = "mediatek,mt7629-pinctrl", }, + {} +}; + +static int mt7629_pinctrl_probe(struct platform_device *pdev) +{ + return mtk_moore_pinctrl_probe(pdev, &mt7629_data); +} + +static struct platform_driver mt7629_pinctrl_driver = { + .driver = { + .name = "mt7629-pinctrl", + .of_match_table = mt7629_pinctrl_of_match, + }, + .probe = mt7629_pinctrl_probe, +}; + +static int __init mt7629_pinctrl_init(void) +{ + return platform_driver_register(&mt7629_pinctrl_driver); +} +arch_initcall(mt7629_pinctrl_init); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6797.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6797.h new file mode 100644 index 000000000000..86ab78e80326 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6797.h @@ -0,0 +1,2429 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Based on pinctrl-mtk-mt6765.h + * + * Copyright (C) 2018 MediaTek Inc. + * + * Author: ZH Chen <zh.chen@mediatek.com> + * + * Copyright (c) 2018 Manivannan Sadhasivam + */ + +#ifndef __PINCTRL_MTK_MT6797_H +#define __PINCTRL_MTK_MT6797_H + +#include "pinctrl-paris.h" + +static const struct mtk_pin_desc mtk_pins_mt6797[] = { + MTK_PIN( + 0, "GPIO0", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "CSI0A_L0P_T0A") + ), + MTK_PIN( + 1, "GPIO1", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "CSI0A_L0N_T0B") + ), + MTK_PIN( + 2, "GPIO2", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "CSI0A_L1P_T0C") + ), + MTK_PIN( + 3, "GPIO3", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "CSI0A_L1N_T1A") + ), + MTK_PIN( + 4, "GPIO4", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "CSI0A_L2P_T1B") + ), + MTK_PIN( + 5, "GPIO5", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "CSI0A_L2N_T1C") + ), + MTK_PIN( + 6, "GPIO6", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "CSI0B_L0P_T0A") + ), + MTK_PIN( + 7, "GPIO7", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "CSI0B_L0N_T0B") + ), + MTK_PIN( + 8, "GPIO8", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "CSI0B_L1P_T0C") + ), + MTK_PIN( + 9, "GPIO9", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "CSI0B_L1N_T1A") + ), + MTK_PIN( + 10, "GPIO10", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "CSI1A_L0P_T0A") + ), + MTK_PIN( + 11, "GPIO11", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "CSI1A_L0N_T0B") + ), + MTK_PIN( + 12, "GPIO12", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "CSI1A_L1P_T0C") + ), + MTK_PIN( + 13, "GPIO13", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "CSI1A_L1N_T1A") + ), + MTK_PIN( + 14, "GPIO14", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "CSI1A_L2P_T1B") + ), + MTK_PIN( + 15, "GPIO15", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "CSI1A_L2N_T1C") + ), + MTK_PIN( + 16, "GPIO16", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "CSI1B_L0P_T0A") + ), + MTK_PIN( + 17, "GPIO17", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "CSI1B_L0N_T0B") + ), + MTK_PIN( + 18, "GPIO18", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "CSI1B_L1P_T0C") + ), + MTK_PIN( + 19, "GPIO19", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "CSI1B_L1N_T1A") + ), + MTK_PIN( + 20, "GPIO20", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "CSI1B_L2P_T1B") + ), + MTK_PIN( + 21, "GPIO21", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "CSI1B_L2N_T1C") + ), + MTK_PIN( + 22, "GPIO22", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "CSI2_L0P_T0A") + ), + MTK_PIN( + 23, "GPIO23", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(1, "CSI2_L0N_T0B") + ), + MTK_PIN( + 24, "GPIO24", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "CSI2_L1P_T0C") + ), + MTK_PIN( + 25, "GPIO25", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "CSI2_L1N_T1A") + ), + MTK_PIN( + 26, "GPIO26", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "CSI2_L2P_T1B") + ), + MTK_PIN( + 27, "GPIO27", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "CSI2_L2N_T1C") + ), + MTK_PIN( + 28, "GPIO28", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "SPI5_CLK_A"), + MTK_FUNCTION(2, "IRTX_OUT"), + MTK_FUNCTION(3, "UDI_TDO"), + MTK_FUNCTION(4, "SCP_JTAG_TDO"), + MTK_FUNCTION(5, "CONN_MCU_TDO"), + MTK_FUNCTION(6, "PWM_A"), + MTK_FUNCTION(7, "C2K_DM_OTDO") + ), + MTK_PIN( + 29, "GPIO29", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "SPI5_MI_A"), + MTK_FUNCTION(2, "DAP_SIB1_SWD"), + MTK_FUNCTION(3, "UDI_TMS"), + MTK_FUNCTION(4, "SCP_JTAG_TMS"), + MTK_FUNCTION(5, "CONN_MCU_TMS"), + MTK_FUNCTION(6, "CONN_MCU_AICE_TMSC"), + MTK_FUNCTION(7, "C2K_DM_OTMS") + ), + MTK_PIN( + 30, "GPIO30", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "CMMCLK0"), + MTK_FUNCTION(7, "MD_CLKM0") + ), + MTK_PIN( + 31, "GPIO31", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "CMMCLK1"), + MTK_FUNCTION(7, "MD_CLKM1") + ), + MTK_PIN( + 32, "GPIO32", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "SPI5_CS_A"), + MTK_FUNCTION(2, "DAP_SIB1_SWCK"), + MTK_FUNCTION(3, "UDI_TCK_XI"), + MTK_FUNCTION(4, "SCP_JTAG_TCK"), + MTK_FUNCTION(5, "CONN_MCU_TCK"), + MTK_FUNCTION(6, "CONN_MCU_AICE_TCKC"), + MTK_FUNCTION(7, "C2K_DM_OTCK") + ), + MTK_PIN( + 33, "GPIO33", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "SPI5_MO_A"), + MTK_FUNCTION(2, "CMFLASH"), + MTK_FUNCTION(3, "UDI_TDI"), + MTK_FUNCTION(4, "SCP_JTAG_TDI"), + MTK_FUNCTION(5, "CONN_MCU_TDI"), + MTK_FUNCTION(6, "MD_URXD0"), + MTK_FUNCTION(7, "C2K_DM_OTDI") + ), + MTK_PIN( + 34, "GPIO34", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "CMFLASH"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "UDI_NTRST"), + MTK_FUNCTION(4, "SCP_JTAG_TRSTN"), + MTK_FUNCTION(5, "CONN_MCU_TRST_B"), + MTK_FUNCTION(6, "MD_UTXD0"), + MTK_FUNCTION(7, "C2K_DM_JTINTP") + ), + MTK_PIN( + 35, "GPIO35", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "CMMCLK3"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "MD_URXD1"), + MTK_FUNCTION(4, "PTA_RXD"), + MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"), + MTK_FUNCTION(6, "PWM_B"), + MTK_FUNCTION(7, "PCC_PPC_IO") + ), + MTK_PIN( + 36, "GPIO36", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "CMMCLK2"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(3, "MD_UTXD1"), + MTK_FUNCTION(4, "PTA_TXD"), + MTK_FUNCTION(5, "CONN_MCU_DBGI_N"), + MTK_FUNCTION(6, "PWM_C"), + MTK_FUNCTION(7, "EXT_FRAME_SYNC") + ), + MTK_PIN( + 37, "GPIO37", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "SCL0_0") + ), + MTK_PIN( + 38, "GPIO38", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "SDA0_0") + ), + MTK_PIN( + 39, "GPIO39", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "DPI_D0"), + MTK_FUNCTION(2, "SPI1_CLK_A"), + MTK_FUNCTION(3, "PCM0_SYNC"), + MTK_FUNCTION(4, "I2S0_LRCK"), + MTK_FUNCTION(5, "CONN_MCU_TRST_B"), + MTK_FUNCTION(6, "URXD3"), + MTK_FUNCTION(7, "C2K_NTRST") + ), + MTK_PIN( + 40, "GPIO40", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "DPI_D1"), + MTK_FUNCTION(2, "SPI1_MI_A"), + MTK_FUNCTION(3, "PCM0_CLK"), + MTK_FUNCTION(4, "I2S0_BCK"), + MTK_FUNCTION(5, "CONN_MCU_TDO"), + MTK_FUNCTION(6, "UTXD3"), + MTK_FUNCTION(7, "C2K_TCK") + ), + MTK_PIN( + 41, "GPIO41", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "DPI_D2"), + MTK_FUNCTION(2, "SPI1_CS_A"), + MTK_FUNCTION(3, "PCM0_DO"), + MTK_FUNCTION(4, "I2S3_DO"), + MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"), + MTK_FUNCTION(6, "URTS3"), + MTK_FUNCTION(7, "C2K_TDI") + ), + MTK_PIN( + 42, "GPIO42", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "DPI_D3"), + MTK_FUNCTION(2, "SPI1_MO_A"), + MTK_FUNCTION(3, "PCM0_DI"), + MTK_FUNCTION(4, "I2S0_DI"), + MTK_FUNCTION(5, "CONN_MCU_TDI"), + MTK_FUNCTION(6, "UCTS3"), + MTK_FUNCTION(7, "C2K_TMS") + ), + MTK_PIN( + 43, "GPIO43", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "DPI_D4"), + MTK_FUNCTION(2, "SPI2_CLK_A"), + MTK_FUNCTION(3, "PCM1_SYNC"), + MTK_FUNCTION(4, "I2S2_LRCK"), + MTK_FUNCTION(5, "CONN_MCU_TMS"), + MTK_FUNCTION(6, "CONN_MCU_AICE_TMSC"), + MTK_FUNCTION(7, "C2K_TDO") + ), + MTK_PIN( + 44, "GPIO44", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "DPI_D5"), + MTK_FUNCTION(2, "SPI2_MI_A"), + MTK_FUNCTION(3, "PCM1_CLK"), + MTK_FUNCTION(4, "I2S2_BCK"), + MTK_FUNCTION(5, "CONN_MCU_TCK"), + MTK_FUNCTION(6, "CONN_MCU_AICE_TCKC"), + MTK_FUNCTION(7, "C2K_RTCK") + ), + MTK_PIN( + 45, "GPIO45", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "DPI_D6"), + MTK_FUNCTION(2, "SPI2_CS_A"), + MTK_FUNCTION(3, "PCM1_DI"), + MTK_FUNCTION(4, "I2S2_DI"), + MTK_FUNCTION(5, "CONN_MCU_DBGI_N"), + MTK_FUNCTION(6, "MD_URXD0") + ), + MTK_PIN( + 46, "GPIO46", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "DPI_D7"), + MTK_FUNCTION(2, "SPI2_MO_A"), + MTK_FUNCTION(3, "PCM1_DO0"), + MTK_FUNCTION(4, "I2S1_DO"), + MTK_FUNCTION(5, "ANT_SEL0"), + MTK_FUNCTION(6, "MD_UTXD0") + ), + MTK_PIN( + 47, "GPIO47", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "DPI_D8"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "PCM1_DO1"), + MTK_FUNCTION(4, "I2S0_MCK"), + MTK_FUNCTION(5, "ANT_SEL1"), + MTK_FUNCTION(6, "PTA_RXD"), + MTK_FUNCTION(7, "C2K_URXD0") + ), + MTK_PIN( + 48, "GPIO48", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "DPI_D9"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "CMFLASH"), + MTK_FUNCTION(4, "I2S2_MCK"), + MTK_FUNCTION(5, "ANT_SEL2"), + MTK_FUNCTION(6, "PTA_TXD"), + MTK_FUNCTION(7, "C2K_UTXD0") + ), + MTK_PIN( + 49, "GPIO49", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "DPI_D10"), + MTK_FUNCTION(2, "MD_INT1_C2K_UIM1_HOT_PLUG_IN"), + MTK_FUNCTION(3, "PWM_C"), + MTK_FUNCTION(4, "IRTX_OUT"), + MTK_FUNCTION(5, "ANT_SEL3"), + MTK_FUNCTION(6, "MD_URXD1") + ), + MTK_PIN( + 50, "GPIO50", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "DPI_D11"), + MTK_FUNCTION(2, "MD_INT2"), + MTK_FUNCTION(3, "PWM_D"), + MTK_FUNCTION(4, "CLKM2"), + MTK_FUNCTION(5, "ANT_SEL4"), + MTK_FUNCTION(6, "MD_UTXD1") + ), + MTK_PIN( + 51, "GPIO51", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "DPI_DE"), + MTK_FUNCTION(2, "SPI4_CLK_A"), + MTK_FUNCTION(3, "IRTX_OUT"), + MTK_FUNCTION(4, "SCL0_1"), + MTK_FUNCTION(5, "ANT_SEL5"), + MTK_FUNCTION(7, "C2K_UTXD1") + ), + MTK_PIN( + 52, "GPIO52", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "DPI_CK"), + MTK_FUNCTION(2, "SPI4_MI_A"), + MTK_FUNCTION(3, "SPI4_MO_A"), + MTK_FUNCTION(4, "SDA0_1"), + MTK_FUNCTION(5, "ANT_SEL6"), + MTK_FUNCTION(7, "C2K_URXD1") + ), + MTK_PIN( + 53, "GPIO53", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "DPI_HSYNC"), + MTK_FUNCTION(2, "SPI4_CS_A"), + MTK_FUNCTION(3, "CMFLASH"), + MTK_FUNCTION(4, "SCL1_1"), + MTK_FUNCTION(5, "ANT_SEL7"), + MTK_FUNCTION(6, "MD_URXD2"), + MTK_FUNCTION(7, "PCC_PPC_IO") + ), + MTK_PIN( + 54, "GPIO54", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "DPI_VSYNC"), + MTK_FUNCTION(2, "SPI4_MO_A"), + MTK_FUNCTION(3, "SPI4_MI_A"), + MTK_FUNCTION(4, "SDA1_1"), + MTK_FUNCTION(5, "PWM_A"), + MTK_FUNCTION(6, "MD_UTXD2"), + MTK_FUNCTION(7, "EXT_FRAME_SYNC") + ), + MTK_PIN( + 55, "GPIO55", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "SCL1_0") + ), + MTK_PIN( + 56, "GPIO56", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "SDA1_0") + ), + MTK_PIN( + 57, "GPIO57", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "SPI0_CLK"), + MTK_FUNCTION(2, "SCL0_2"), + MTK_FUNCTION(3, "PWM_B"), + MTK_FUNCTION(4, "UTXD3"), + MTK_FUNCTION(5, "PCM0_SYNC") + ), + MTK_PIN( + 58, "GPIO58", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "SPI0_MI"), + MTK_FUNCTION(2, "SPI0_MO"), + MTK_FUNCTION(3, "SDA1_2"), + MTK_FUNCTION(4, "URXD3"), + MTK_FUNCTION(5, "PCM0_CLK") + ), + MTK_PIN( + 59, "GPIO59", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "SPI0_MO"), + MTK_FUNCTION(2, "SPI0_MI"), + MTK_FUNCTION(3, "PWM_C"), + MTK_FUNCTION(4, "URTS3"), + MTK_FUNCTION(5, "PCM0_DO") + ), + MTK_PIN( + 60, "GPIO60", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "SPI0_CS"), + MTK_FUNCTION(2, "SDA0_2"), + MTK_FUNCTION(3, "SCL1_2"), + MTK_FUNCTION(4, "UCTS3"), + MTK_FUNCTION(5, "PCM0_DI") + ), + MTK_PIN( + 61, "GPIO61", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "EINT0"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "SPI4_CLK_B"), + MTK_FUNCTION(4, "I2S0_LRCK"), + MTK_FUNCTION(5, "PCM0_SYNC"), + MTK_FUNCTION(7, "C2K_EINT0") + ), + MTK_PIN( + 62, "GPIO62", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "EINT1"), + MTK_FUNCTION(2, "USB_DRVVBUS"), + MTK_FUNCTION(3, "SPI4_MI_B"), + MTK_FUNCTION(4, "I2S0_BCK"), + MTK_FUNCTION(5, "PCM0_CLK"), + MTK_FUNCTION(7, "C2K_EINT1") + ), + MTK_PIN( + 63, "GPIO63", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "EINT2"), + MTK_FUNCTION(2, "IRTX_OUT"), + MTK_FUNCTION(3, "SPI4_MO_B"), + MTK_FUNCTION(4, "I2S0_MCK"), + MTK_FUNCTION(5, "PCM0_DI"), + MTK_FUNCTION(7, "C2K_DM_EINT0") + ), + MTK_PIN( + 64, "GPIO64", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "EINT3"), + MTK_FUNCTION(2, "CMFLASH"), + MTK_FUNCTION(3, "SPI4_CS_B"), + MTK_FUNCTION(4, "I2S0_DI"), + MTK_FUNCTION(5, "PCM0_DO"), + MTK_FUNCTION(7, "C2K_DM_EINT1") + ), + MTK_PIN( + 65, "GPIO65", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "EINT4"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "SPI5_CLK_B"), + MTK_FUNCTION(4, "I2S1_LRCK"), + MTK_FUNCTION(5, "PWM_A"), + MTK_FUNCTION(7, "C2K_DM_EINT2") + ), + MTK_PIN( + 66, "GPIO66", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "EINT5"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "SPI5_MI_B"), + MTK_FUNCTION(4, "I2S1_BCK"), + MTK_FUNCTION(5, "PWM_B"), + MTK_FUNCTION(7, "C2K_DM_EINT3") + ), + MTK_PIN( + 67, "GPIO67", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "EINT6"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(3, "SPI5_MO_B"), + MTK_FUNCTION(4, "I2S1_MCK"), + MTK_FUNCTION(5, "PWM_C"), + MTK_FUNCTION(7, "DBG_MON_A0") + ), + MTK_PIN( + 68, "GPIO68", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "EINT7"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(3, "SPI5_CS_B"), + MTK_FUNCTION(4, "I2S1_DO"), + MTK_FUNCTION(5, "PWM_D"), + MTK_FUNCTION(7, "DBG_MON_A1") + ), + MTK_PIN( + 69, "GPIO69", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "I2S0_LRCK"), + MTK_FUNCTION(2, "I2S3_LRCK"), + MTK_FUNCTION(3, "I2S1_LRCK"), + MTK_FUNCTION(4, "I2S2_LRCK"), + MTK_FUNCTION(7, "DBG_MON_A2") + ), + MTK_PIN( + 70, "GPIO70", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "I2S0_BCK"), + MTK_FUNCTION(2, "I2S3_BCK"), + MTK_FUNCTION(3, "I2S1_BCK"), + MTK_FUNCTION(4, "I2S2_BCK"), + MTK_FUNCTION(7, "DBG_MON_A3") + ), + MTK_PIN( + 71, "GPIO71", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO71"), + MTK_FUNCTION(1, "I2S0_MCK"), + MTK_FUNCTION(2, "I2S3_MCK"), + MTK_FUNCTION(3, "I2S1_MCK"), + MTK_FUNCTION(4, "I2S2_MCK"), + MTK_FUNCTION(7, "DBG_MON_A4") + ), + MTK_PIN( + 72, "GPIO72", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO72"), + MTK_FUNCTION(1, "I2S0_DI"), + MTK_FUNCTION(2, "I2S0_DI"), + MTK_FUNCTION(3, "I2S2_DI"), + MTK_FUNCTION(4, "I2S2_DI"), + MTK_FUNCTION(7, "DBG_MON_A5") + ), + MTK_PIN( + 73, "GPIO73", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO73"), + MTK_FUNCTION(1, "I2S3_DO"), + MTK_FUNCTION(2, "I2S3_DO"), + MTK_FUNCTION(3, "I2S1_DO"), + MTK_FUNCTION(4, "I2S1_DO"), + MTK_FUNCTION(7, "DBG_MON_A6") + ), + MTK_PIN( + 74, "GPIO74", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "SCL3_0"), + MTK_FUNCTION(7, "AUXIF_CLK1") + ), + MTK_PIN( + 75, "GPIO75", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "SDA3_0"), + MTK_FUNCTION(7, "AUXIF_ST1") + ), + MTK_PIN( + 76, "GPIO76", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "CONN_HRST_B"), + MTK_FUNCTION(7, "C2K_DM_EINT0") + ), + MTK_PIN( + 77, "GPIO77", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "CONN_TOP_CLK"), + MTK_FUNCTION(7, "C2K_DM_EINT1") + ), + MTK_PIN( + 78, "GPIO78", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "CONN_TOP_DATA"), + MTK_FUNCTION(7, "C2K_DM_EINT2") + ), + MTK_PIN( + 79, "GPIO79", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "CONN_WB_PTA"), + MTK_FUNCTION(7, "C2K_DM_EINT3") + ), + MTK_PIN( + 80, "GPIO80", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "CONN_WF_HB0"), + MTK_FUNCTION(7, "C2K_EINT0") + ), + MTK_PIN( + 81, "GPIO81", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "CONN_WF_HB1"), + MTK_FUNCTION(7, "C2K_EINT1") + ), + MTK_PIN( + 82, "GPIO82", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "CONN_WF_HB2"), + MTK_FUNCTION(7, "MD_CLKM0") + ), + MTK_PIN( + 83, "GPIO83", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "CONN_BT_CLK"), + MTK_FUNCTION(7, "MD_CLKM1") + ), + MTK_PIN( + 84, "GPIO84", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "CONN_BT_DATA") + ), + MTK_PIN( + 85, "GPIO85", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "EINT8"), + MTK_FUNCTION(2, "I2S1_LRCK"), + MTK_FUNCTION(3, "I2S2_LRCK"), + MTK_FUNCTION(4, "URXD1"), + MTK_FUNCTION(5, "MD_URXD0"), + MTK_FUNCTION(7, "DBG_MON_A7") + ), + MTK_PIN( + 86, "GPIO86", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "EINT9"), + MTK_FUNCTION(2, "I2S1_BCK"), + MTK_FUNCTION(3, "I2S2_BCK"), + MTK_FUNCTION(4, "UTXD1"), + MTK_FUNCTION(5, "MD_UTXD0"), + MTK_FUNCTION(7, "DBG_MON_A8") + ), + MTK_PIN( + 87, "GPIO87", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(1, "EINT10"), + MTK_FUNCTION(2, "I2S1_MCK"), + MTK_FUNCTION(3, "I2S2_MCK"), + MTK_FUNCTION(4, "URTS1"), + MTK_FUNCTION(5, "MD_URXD1"), + MTK_FUNCTION(7, "DBG_MON_A9") + ), + MTK_PIN( + 88, "GPIO88", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "EINT11"), + MTK_FUNCTION(2, "I2S1_DO"), + MTK_FUNCTION(3, "I2S2_DI"), + MTK_FUNCTION(4, "UCTS1"), + MTK_FUNCTION(5, "MD_UTXD1"), + MTK_FUNCTION(7, "DBG_MON_A10") + ), + MTK_PIN( + 89, "GPIO89", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "EINT12"), + MTK_FUNCTION(2, "IRTX_OUT"), + MTK_FUNCTION(3, "CLKM0"), + MTK_FUNCTION(4, "PCM1_SYNC"), + MTK_FUNCTION(5, "URTS0"), + MTK_FUNCTION(7, "DBG_MON_A11") + ), + MTK_PIN( + 90, "GPIO90", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "EINT13"), + MTK_FUNCTION(2, "CMFLASH"), + MTK_FUNCTION(3, "CLKM1"), + MTK_FUNCTION(4, "PCM1_CLK"), + MTK_FUNCTION(5, "UCTS0"), + MTK_FUNCTION(7, "C2K_DM_EINT0") + ), + MTK_PIN( + 91, "GPIO91", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO91"), + MTK_FUNCTION(1, "EINT14"), + MTK_FUNCTION(2, "PWM_A"), + MTK_FUNCTION(3, "CLKM2"), + MTK_FUNCTION(4, "PCM1_DI"), + MTK_FUNCTION(5, "SDA0_3"), + MTK_FUNCTION(7, "C2K_DM_EINT1") + ), + MTK_PIN( + 92, "GPIO92", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO92"), + MTK_FUNCTION(1, "EINT15"), + MTK_FUNCTION(2, "PWM_B"), + MTK_FUNCTION(3, "CLKM3"), + MTK_FUNCTION(4, "PCM1_DO0"), + MTK_FUNCTION(5, "SCL0_3") + ), + MTK_PIN( + 93, "GPIO93", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO93"), + MTK_FUNCTION(1, "EINT16"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "CLKM4"), + MTK_FUNCTION(4, "PCM1_DO1"), + MTK_FUNCTION(5, "MD_INT2"), + MTK_FUNCTION(7, "DROP_ZONE") + ), + MTK_PIN( + 94, "GPIO94", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO94"), + MTK_FUNCTION(1, "USB_DRVVBUS"), + MTK_FUNCTION(2, "PWM_C"), + MTK_FUNCTION(3, "CLKM5") + ), + MTK_PIN( + 95, "GPIO95", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO95"), + MTK_FUNCTION(1, "SDA2_0"), + MTK_FUNCTION(7, "AUXIF_ST0") + ), + MTK_PIN( + 96, "GPIO96", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO96"), + MTK_FUNCTION(1, "SCL2_0"), + MTK_FUNCTION(7, "AUXIF_CLK0") + ), + MTK_PIN( + 97, "GPIO97", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO97"), + MTK_FUNCTION(1, "URXD0"), + MTK_FUNCTION(2, "UTXD0"), + MTK_FUNCTION(3, "MD_URXD0"), + MTK_FUNCTION(4, "MD_URXD1"), + MTK_FUNCTION(5, "MD_URXD2"), + MTK_FUNCTION(6, "C2K_URXD0"), + MTK_FUNCTION(7, "C2K_URXD1") + ), + MTK_PIN( + 98, "GPIO98", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO98"), + MTK_FUNCTION(1, "UTXD0"), + MTK_FUNCTION(2, "URXD0"), + MTK_FUNCTION(3, "MD_UTXD0"), + MTK_FUNCTION(4, "MD_UTXD1"), + MTK_FUNCTION(5, "MD_UTXD2"), + MTK_FUNCTION(6, "C2K_UTXD0"), + MTK_FUNCTION(7, "C2K_UTXD1") + ), + MTK_PIN( + 99, "GPIO99", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO99"), + MTK_FUNCTION(1, "RTC32K_CK") + ), + MTK_PIN( + 100, "GPIO100", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO100"), + MTK_FUNCTION(1, "SRCLKENAI0") + ), + MTK_PIN( + 101, "GPIO101", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO101"), + MTK_FUNCTION(1, "SRCLKENAI1") + ), + MTK_PIN( + 102, "GPIO102", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO102"), + MTK_FUNCTION(1, "SRCLKENA0") + ), + MTK_PIN( + 103, "GPIO103", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO103"), + MTK_FUNCTION(1, "SRCLKENA1") + ), + MTK_PIN( + 104, "GPIO104", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO104"), + MTK_FUNCTION(1, "SYSRSTB") + ), + MTK_PIN( + 105, "GPIO105", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO105"), + MTK_FUNCTION(1, "WATCHDOG") + ), + MTK_PIN( + 106, "GPIO106", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO106"), + MTK_FUNCTION(1, "KPROW0"), + MTK_FUNCTION(2, "CMFLASH"), + MTK_FUNCTION(3, "CLKM4"), + MTK_FUNCTION(4, "TP_GPIO0_AO"), + MTK_FUNCTION(5, "IRTX_OUT") + ), + MTK_PIN( + 107, "GPIO107", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO107"), + MTK_FUNCTION(1, "KPROW1"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "CLKM5"), + MTK_FUNCTION(4, "TP_GPIO1_AO"), + MTK_FUNCTION(5, "I2S1_BCK"), + MTK_FUNCTION(7, "DAP_SIB1_SWD") + ), + MTK_PIN( + 108, "GPIO108", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO108"), + MTK_FUNCTION(1, "KPROW2"), + MTK_FUNCTION(2, "USB_DRVVBUS"), + MTK_FUNCTION(3, "PWM_A"), + MTK_FUNCTION(4, "CMFLASH"), + MTK_FUNCTION(5, "I2S1_LRCK"), + MTK_FUNCTION(7, "DAP_SIB1_SWCK") + ), + MTK_PIN( + 109, "GPIO109", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO109"), + MTK_FUNCTION(1, "KPCOL0") + ), + MTK_PIN( + 110, "GPIO110", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO110"), + MTK_FUNCTION(1, "KPCOL1"), + MTK_FUNCTION(2, "SDA1_3"), + MTK_FUNCTION(3, "PWM_B"), + MTK_FUNCTION(4, "CLKM0"), + MTK_FUNCTION(5, "I2S1_DO"), + MTK_FUNCTION(7, "C2K_DM_EINT3") + ), + MTK_PIN( + 111, "GPIO111", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO111"), + MTK_FUNCTION(1, "KPCOL2"), + MTK_FUNCTION(2, "SCL1_3"), + MTK_FUNCTION(3, "PWM_C"), + MTK_FUNCTION(4, "DISP_PWM"), + MTK_FUNCTION(5, "I2S1_MCK"), + MTK_FUNCTION(7, "C2K_DM_EINT2") + ), + MTK_PIN( + 112, "GPIO112", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO112"), + MTK_FUNCTION(1, "MD_INT1_C2K_UIM1_HOT_PLUG_IN"), + MTK_FUNCTION(7, "C2K_DM_EINT1") + ), + MTK_PIN( + 113, "GPIO113", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO113"), + MTK_FUNCTION(1, "MD_INT0_C2K_UIM0_HOT_PLUG_IN"), + MTK_FUNCTION(7, "C2K_DM_EINT0") + ), + MTK_PIN( + 114, "GPIO114", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO114"), + MTK_FUNCTION(1, "MSDC0_DAT0") + ), + MTK_PIN( + 115, "GPIO115", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO115"), + MTK_FUNCTION(1, "MSDC0_DAT1") + ), + MTK_PIN( + 116, "GPIO116", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO116"), + MTK_FUNCTION(1, "MSDC0_DAT2") + ), + MTK_PIN( + 117, "GPIO117", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "MSDC0_DAT3") + ), + MTK_PIN( + 118, "GPIO118", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(1, "MSDC0_DAT4") + ), + MTK_PIN( + 119, "GPIO119", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "MSDC0_DAT5") + ), + MTK_PIN( + 120, "GPIO120", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "MSDC0_DAT6") + ), + MTK_PIN( + 121, "GPIO121", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "MSDC0_DAT7") + ), + MTK_PIN( + 122, "GPIO122", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "MSDC0_CMD") + ), + MTK_PIN( + 123, "GPIO123", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(1, "MSDC0_CLK") + ), + MTK_PIN( + 124, "GPIO124", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "MSDC0_DSL") + ), + MTK_PIN( + 125, "GPIO125", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO125"), + MTK_FUNCTION(1, "MSDC0_RSTB") + ), + MTK_PIN( + 126, "GPIO126", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "MD1_SIM1_SCLK"), + MTK_FUNCTION(2, "MD1_SIM2_SCLK"), + MTK_FUNCTION(3, "C2K_UIM0_CLK"), + MTK_FUNCTION(4, "C2K_UIM1_CLK") + ), + MTK_PIN( + 127, "GPIO127", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "MD1_SIM1_SRST"), + MTK_FUNCTION(2, "MD1_SIM2_SRST"), + MTK_FUNCTION(3, "C2K_UIM0_RST"), + MTK_FUNCTION(4, "C2K_UIM1_RST") + ), + MTK_PIN( + 128, "GPIO128", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "MD1_SIM1_SIO"), + MTK_FUNCTION(2, "MD1_SIM2_SIO"), + MTK_FUNCTION(3, "C2K_UIM0_IO"), + MTK_FUNCTION(4, "C2K_UIM1_IO") + ), + MTK_PIN( + 129, "GPIO129", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "MSDC1_CMD"), + MTK_FUNCTION(2, "CONN_DSP_JMS"), + MTK_FUNCTION(3, "LTE_JTAG_TMS"), + MTK_FUNCTION(4, "UDI_TMS"), + MTK_FUNCTION(5, "C2K_TMS") + ), + MTK_PIN( + 130, "GPIO130", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(1, "MSDC1_DAT0"), + MTK_FUNCTION(2, "CONN_DSP_JDI"), + MTK_FUNCTION(3, "LTE_JTAG_TDI"), + MTK_FUNCTION(4, "UDI_TDI"), + MTK_FUNCTION(5, "C2K_TDI") + ), + MTK_PIN( + 131, "GPIO131", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "MSDC1_DAT1"), + MTK_FUNCTION(2, "CONN_DSP_JDO"), + MTK_FUNCTION(3, "LTE_JTAG_TDO"), + MTK_FUNCTION(4, "UDI_TDO"), + MTK_FUNCTION(5, "C2K_TDO") + ), + MTK_PIN( + 132, "GPIO132", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "MSDC1_DAT2"), + MTK_FUNCTION(5, "C2K_RTCK") + ), + MTK_PIN( + 133, "GPIO133", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "MSDC1_DAT3"), + MTK_FUNCTION(2, "CONN_DSP_JINTP"), + MTK_FUNCTION(3, "LTE_JTAG_TRSTN"), + MTK_FUNCTION(4, "UDI_NTRST"), + MTK_FUNCTION(5, "C2K_NTRST") + ), + MTK_PIN( + 134, "GPIO134", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "MSDC1_CLK"), + MTK_FUNCTION(2, "CONN_DSP_JCK"), + MTK_FUNCTION(3, "LTE_JTAG_TCK"), + MTK_FUNCTION(4, "UDI_TCK_XI"), + MTK_FUNCTION(5, "C2K_TCK") + ), + MTK_PIN( + 135, "GPIO135", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO135"), + MTK_FUNCTION(1, "TDM_LRCK"), + MTK_FUNCTION(2, "I2S0_LRCK"), + MTK_FUNCTION(3, "CLKM0"), + MTK_FUNCTION(4, "PCM1_SYNC"), + MTK_FUNCTION(5, "PWM_A"), + MTK_FUNCTION(7, "DBG_MON_A12") + ), + MTK_PIN( + 136, "GPIO136", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO136"), + MTK_FUNCTION(1, "TDM_BCK"), + MTK_FUNCTION(2, "I2S0_BCK"), + MTK_FUNCTION(3, "CLKM1"), + MTK_FUNCTION(4, "PCM1_CLK"), + MTK_FUNCTION(5, "PWM_B"), + MTK_FUNCTION(7, "DBG_MON_A13") + ), + MTK_PIN( + 137, "GPIO137", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO137"), + MTK_FUNCTION(1, "TDM_MCK"), + MTK_FUNCTION(2, "I2S0_MCK"), + MTK_FUNCTION(3, "CLKM2"), + MTK_FUNCTION(4, "PCM1_DI"), + MTK_FUNCTION(5, "IRTX_OUT"), + MTK_FUNCTION(7, "DBG_MON_A14") + ), + MTK_PIN( + 138, "GPIO138", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO138"), + MTK_FUNCTION(1, "TDM_DATA0"), + MTK_FUNCTION(2, "I2S0_DI"), + MTK_FUNCTION(3, "CLKM3"), + MTK_FUNCTION(4, "PCM1_DO0"), + MTK_FUNCTION(5, "PWM_C"), + MTK_FUNCTION(6, "SDA3_1"), + MTK_FUNCTION(7, "DBG_MON_A15") + ), + MTK_PIN( + 139, "GPIO139", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO139"), + MTK_FUNCTION(1, "TDM_DATA1"), + MTK_FUNCTION(2, "I2S3_DO"), + MTK_FUNCTION(3, "CLKM4"), + MTK_FUNCTION(4, "PCM1_DO1"), + MTK_FUNCTION(5, "ANT_SEL2"), + MTK_FUNCTION(6, "SCL3_1"), + MTK_FUNCTION(7, "DBG_MON_A16") + ), + MTK_PIN( + 140, "GPIO140", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO140"), + MTK_FUNCTION(1, "TDM_DATA2"), + MTK_FUNCTION(2, "DISP_PWM"), + MTK_FUNCTION(3, "CLKM5"), + MTK_FUNCTION(4, "SDA1_4"), + MTK_FUNCTION(5, "ANT_SEL1"), + MTK_FUNCTION(6, "URXD3"), + MTK_FUNCTION(7, "DBG_MON_A17") + ), + MTK_PIN( + 141, "GPIO141", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO141"), + MTK_FUNCTION(1, "TDM_DATA3"), + MTK_FUNCTION(2, "CMFLASH"), + MTK_FUNCTION(3, "IRTX_OUT"), + MTK_FUNCTION(4, "SCL1_4"), + MTK_FUNCTION(5, "ANT_SEL0"), + MTK_FUNCTION(6, "UTXD3"), + MTK_FUNCTION(7, "DBG_MON_A18") + ), + MTK_PIN( + 142, "GPIO142", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO142"), + MTK_FUNCTION(1, "PWRAP_SPI0_MI"), + MTK_FUNCTION(2, "PWRAP_SPI0_MO") + ), + MTK_PIN( + 143, "GPIO143", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO143"), + MTK_FUNCTION(1, "PWRAP_SPI0_MO"), + MTK_FUNCTION(2, "PWRAP_SPI0_MI") + ), + MTK_PIN( + 144, "GPIO144", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO144"), + MTK_FUNCTION(1, "PWRAP_SPI0_CK") + ), + MTK_PIN( + 145, "GPIO145", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO145"), + MTK_FUNCTION(1, "PWRAP_SPI0_CSN") + ), + MTK_PIN( + 146, "GPIO146", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO146"), + MTK_FUNCTION(1, "AUD_CLK_MOSI") + ), + MTK_PIN( + 147, "GPIO147", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO147"), + MTK_FUNCTION(1, "AUD_DAT_MISO"), + MTK_FUNCTION(2, "AUD_DAT_MOSI"), + MTK_FUNCTION(3, "VOW_DAT_MISO") + ), + MTK_PIN( + 148, "GPIO148", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO148"), + MTK_FUNCTION(1, "AUD_DAT_MOSI"), + MTK_FUNCTION(2, "AUD_DAT_MISO") + ), + MTK_PIN( + 149, "GPIO149", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO149"), + MTK_FUNCTION(1, "VOW_CLK_MISO") + ), + MTK_PIN( + 150, "GPIO150", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO150"), + MTK_FUNCTION(1, "ANC_DAT_MOSI") + ), + MTK_PIN( + 151, "GPIO151", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO151"), + MTK_FUNCTION(1, "SCL6_0") + ), + MTK_PIN( + 152, "GPIO152", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO152"), + MTK_FUNCTION(1, "SDA6_0") + ), + MTK_PIN( + 153, "GPIO153", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO153"), + MTK_FUNCTION(1, "SCL7_0") + ), + MTK_PIN( + 154, "GPIO154", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO154"), + MTK_FUNCTION(1, "SDA7_0") + ), + MTK_PIN( + 155, "GPIO155", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO155"), + MTK_FUNCTION(1, "MD1_SIM2_SCLK"), + MTK_FUNCTION(2, "MD1_SIM1_SCLK"), + MTK_FUNCTION(3, "C2K_UIM0_CLK"), + MTK_FUNCTION(4, "C2K_UIM1_CLK") + ), + MTK_PIN( + 156, "GPIO156", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO156"), + MTK_FUNCTION(1, "MD1_SIM2_SRST"), + MTK_FUNCTION(2, "MD1_SIM1_SRST"), + MTK_FUNCTION(3, "C2K_UIM0_RST"), + MTK_FUNCTION(4, "C2K_UIM1_RST") + ), + MTK_PIN( + 157, "GPIO157", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO157"), + MTK_FUNCTION(1, "MD1_SIM2_SIO"), + MTK_FUNCTION(2, "MD1_SIM1_SIO"), + MTK_FUNCTION(3, "C2K_UIM0_IO"), + MTK_FUNCTION(4, "C2K_UIM1_IO") + ), + MTK_PIN( + 158, "GPIO158", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO158"), + MTK_FUNCTION(1, "MIPI_TDP0") + ), + MTK_PIN( + 159, "GPIO159", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO159"), + MTK_FUNCTION(1, "MIPI_TDN0") + ), + MTK_PIN( + 160, "GPIO160", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO160"), + MTK_FUNCTION(1, "MIPI_TDP1") + ), + MTK_PIN( + 161, "GPIO161", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO161"), + MTK_FUNCTION(1, "MIPI_TDN1") + ), + MTK_PIN( + 162, "GPIO162", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO162"), + MTK_FUNCTION(1, "MIPI_TCP") + ), + MTK_PIN( + 163, "GPIO163", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO163"), + MTK_FUNCTION(1, "MIPI_TCN") + ), + MTK_PIN( + 164, "GPIO164", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO164"), + MTK_FUNCTION(1, "MIPI_TDP2") + ), + MTK_PIN( + 165, "GPIO165", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO165"), + MTK_FUNCTION(1, "MIPI_TDN2") + ), + MTK_PIN( + 166, "GPIO166", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO166"), + MTK_FUNCTION(1, "MIPI_TDP3") + ), + MTK_PIN( + 167, "GPIO167", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO167"), + MTK_FUNCTION(1, "MIPI_TDN3") + ), + MTK_PIN( + 168, "GPIO168", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO168"), + MTK_FUNCTION(1, "MIPI_TDP0_A") + ), + MTK_PIN( + 169, "GPIO169", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO169"), + MTK_FUNCTION(1, "MIPI_TDN0_A") + ), + MTK_PIN( + 170, "GPIO170", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO170"), + MTK_FUNCTION(1, "MIPI_TDP1_A") + ), + MTK_PIN( + 171, "GPIO171", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO171"), + MTK_FUNCTION(1, "MIPI_TDN1_A") + ), + MTK_PIN( + 172, "GPIO172", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO172"), + MTK_FUNCTION(1, "MIPI_TCP_A") + ), + MTK_PIN( + 173, "GPIO173", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO173"), + MTK_FUNCTION(1, "MIPI_TCN_A") + ), + MTK_PIN( + 174, "GPIO174", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO174"), + MTK_FUNCTION(1, "MIPI_TDP2_A") + ), + MTK_PIN( + 175, "GPIO175", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO175"), + MTK_FUNCTION(1, "MIPI_TDN2_A") + ), + MTK_PIN( + 176, "GPIO176", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO176"), + MTK_FUNCTION(1, "MIPI_TDP3_A") + ), + MTK_PIN( + 177, "GPIO177", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO177"), + MTK_FUNCTION(1, "MIPI_TDN3_A") + ), + MTK_PIN( + 178, "GPIO178", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO178"), + MTK_FUNCTION(1, "DISP_PWM"), + MTK_FUNCTION(2, "PWM_D"), + MTK_FUNCTION(3, "CLKM5"), + MTK_FUNCTION(7, "DBG_MON_A19") + ), + MTK_PIN( + 179, "GPIO179", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO179"), + MTK_FUNCTION(1, "DSI_TE0"), + MTK_FUNCTION(7, "DBG_MON_A20") + ), + MTK_PIN( + 180, "GPIO180", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO180"), + MTK_FUNCTION(1, "LCM_RST"), + MTK_FUNCTION(2, "DSI_TE1"), + MTK_FUNCTION(7, "DBG_MON_A21") + ), + MTK_PIN( + 181, "GPIO181", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO181"), + MTK_FUNCTION(1, "IDDIG"), + MTK_FUNCTION(2, "DSI_TE1"), + MTK_FUNCTION(7, "DBG_MON_A22") + ), + MTK_PIN( + 182, "GPIO182", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO182"), + MTK_FUNCTION(1, "TESTMODE") + ), + MTK_PIN( + 183, "GPIO183", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO183"), + MTK_FUNCTION(1, "RFIC0_BSI_CK"), + MTK_FUNCTION(2, "SPM_BSI_CK"), + MTK_FUNCTION(7, "DBG_MON_B27") + ), + MTK_PIN( + 184, "GPIO184", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO184"), + MTK_FUNCTION(1, "RFIC0_BSI_EN"), + MTK_FUNCTION(2, "SPM_BSI_EN"), + MTK_FUNCTION(7, "DBG_MON_B28") + ), + MTK_PIN( + 185, "GPIO185", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO185"), + MTK_FUNCTION(1, "RFIC0_BSI_D0"), + MTK_FUNCTION(2, "SPM_BSI_D0"), + MTK_FUNCTION(7, "DBG_MON_B29") + ), + MTK_PIN( + 186, "GPIO186", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO186"), + MTK_FUNCTION(1, "RFIC0_BSI_D1"), + MTK_FUNCTION(2, "SPM_BSI_D1"), + MTK_FUNCTION(7, "DBG_MON_B30") + ), + MTK_PIN( + 187, "GPIO187", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO187"), + MTK_FUNCTION(1, "RFIC0_BSI_D2"), + MTK_FUNCTION(2, "SPM_BSI_D2"), + MTK_FUNCTION(7, "DBG_MON_B31") + ), + MTK_PIN( + 188, "GPIO188", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO188"), + MTK_FUNCTION(1, "MIPI0_SCLK"), + MTK_FUNCTION(7, "DBG_MON_B32") + ), + MTK_PIN( + 189, "GPIO189", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO189"), + MTK_FUNCTION(1, "MIPI0_SDATA") + ), + MTK_PIN( + 190, "GPIO190", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO190"), + MTK_FUNCTION(1, "MIPI1_SCLK") + ), + MTK_PIN( + 191, "GPIO191", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO191"), + MTK_FUNCTION(1, "MIPI1_SDATA") + ), + MTK_PIN( + 192, "GPIO192", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO192"), + MTK_FUNCTION(1, "BPI_BUS4") + ), + MTK_PIN( + 193, "GPIO193", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO193"), + MTK_FUNCTION(1, "BPI_BUS5"), + MTK_FUNCTION(7, "DBG_MON_B0") + ), + MTK_PIN( + 194, "GPIO194", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO194"), + MTK_FUNCTION(1, "BPI_BUS6"), + MTK_FUNCTION(7, "DBG_MON_B1") + ), + MTK_PIN( + 195, "GPIO195", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO195"), + MTK_FUNCTION(1, "BPI_BUS7"), + MTK_FUNCTION(7, "DBG_MON_B2") + ), + MTK_PIN( + 196, "GPIO196", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO196"), + MTK_FUNCTION(1, "BPI_BUS8"), + MTK_FUNCTION(7, "DBG_MON_B3") + ), + MTK_PIN( + 197, "GPIO197", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO197"), + MTK_FUNCTION(1, "BPI_BUS9"), + MTK_FUNCTION(7, "DBG_MON_B4") + ), + MTK_PIN( + 198, "GPIO198", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO198"), + MTK_FUNCTION(1, "BPI_BUS10"), + MTK_FUNCTION(7, "DBG_MON_B5") + ), + MTK_PIN( + 199, "GPIO199", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO199"), + MTK_FUNCTION(1, "BPI_BUS11"), + MTK_FUNCTION(7, "DBG_MON_B6") + ), + MTK_PIN( + 200, "GPIO200", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO200"), + MTK_FUNCTION(1, "BPI_BUS12"), + MTK_FUNCTION(7, "DBG_MON_B7") + ), + MTK_PIN( + 201, "GPIO201", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO201"), + MTK_FUNCTION(1, "BPI_BUS13"), + MTK_FUNCTION(7, "DBG_MON_B8") + ), + MTK_PIN( + 202, "GPIO202", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO202"), + MTK_FUNCTION(1, "BPI_BUS14"), + MTK_FUNCTION(7, "DBG_MON_B9") + ), + MTK_PIN( + 203, "GPIO203", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO203"), + MTK_FUNCTION(1, "BPI_BUS15"), + MTK_FUNCTION(7, "DBG_MON_B10") + ), + MTK_PIN( + 204, "GPIO204", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO204"), + MTK_FUNCTION(1, "BPI_BUS16"), + MTK_FUNCTION(2, "PA_VM0"), + MTK_FUNCTION(7, "DBG_MON_B11") + ), + MTK_PIN( + 205, "GPIO205", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO205"), + MTK_FUNCTION(1, "BPI_BUS17"), + MTK_FUNCTION(2, "PA_VM1"), + MTK_FUNCTION(7, "DBG_MON_B12") + ), + MTK_PIN( + 206, "GPIO206", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO206"), + MTK_FUNCTION(1, "BPI_BUS18"), + MTK_FUNCTION(2, "TX_SWAP0"), + MTK_FUNCTION(7, "DBG_MON_B13") + ), + MTK_PIN( + 207, "GPIO207", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO207"), + MTK_FUNCTION(1, "BPI_BUS19"), + MTK_FUNCTION(2, "TX_SWAP1"), + MTK_FUNCTION(7, "DBG_MON_B14") + ), + MTK_PIN( + 208, "GPIO208", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO208"), + MTK_FUNCTION(1, "BPI_BUS20"), + MTK_FUNCTION(2, "TX_SWAP2"), + MTK_FUNCTION(7, "DBG_MON_B15") + ), + MTK_PIN( + 209, "GPIO209", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO209"), + MTK_FUNCTION(1, "BPI_BUS21"), + MTK_FUNCTION(2, "TX_SWAP3"), + MTK_FUNCTION(7, "DBG_MON_B16") + ), + MTK_PIN( + 210, "GPIO210", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO210"), + MTK_FUNCTION(1, "BPI_BUS22"), + MTK_FUNCTION(2, "DET_BPI0"), + MTK_FUNCTION(7, "DBG_MON_B17") + ), + MTK_PIN( + 211, "GPIO211", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO211"), + MTK_FUNCTION(1, "BPI_BUS23"), + MTK_FUNCTION(2, "DET_BPI1"), + MTK_FUNCTION(7, "DBG_MON_B18") + ), + MTK_PIN( + 212, "GPIO212", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO212"), + MTK_FUNCTION(1, "BPI_BUS0"), + MTK_FUNCTION(7, "DBG_MON_B19") + ), + MTK_PIN( + 213, "GPIO213", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO213"), + MTK_FUNCTION(1, "BPI_BUS1"), + MTK_FUNCTION(7, "DBG_MON_B20") + ), + MTK_PIN( + 214, "GPIO214", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO214"), + MTK_FUNCTION(1, "BPI_BUS2"), + MTK_FUNCTION(7, "DBG_MON_B21") + ), + MTK_PIN( + 215, "GPIO215", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO215"), + MTK_FUNCTION(1, "BPI_BUS3"), + MTK_FUNCTION(7, "DBG_MON_B22") + ), + MTK_PIN( + 216, "GPIO216", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO216"), + MTK_FUNCTION(1, "MIPI2_SCLK"), + MTK_FUNCTION(7, "DBG_MON_B23") + ), + MTK_PIN( + 217, "GPIO217", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO217"), + MTK_FUNCTION(1, "MIPI2_SDATA"), + MTK_FUNCTION(7, "DBG_MON_B24") + ), + MTK_PIN( + 218, "GPIO218", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO218"), + MTK_FUNCTION(1, "MIPI3_SCLK"), + MTK_FUNCTION(7, "DBG_MON_B25") + ), + MTK_PIN( + 219, "GPIO219", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO219"), + MTK_FUNCTION(1, "MIPI3_SDATA"), + MTK_FUNCTION(7, "DBG_MON_B26") + ), + MTK_PIN( + 220, "GPIO220", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO220"), + MTK_FUNCTION(1, "CONN_WF_IP") + ), + MTK_PIN( + 221, "GPIO221", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO221"), + MTK_FUNCTION(1, "CONN_WF_IN") + ), + MTK_PIN( + 222, "GPIO222", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO222"), + MTK_FUNCTION(1, "CONN_WF_QP") + ), + MTK_PIN( + 223, "GPIO223", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO223"), + MTK_FUNCTION(1, "CONN_WF_QN") + ), + MTK_PIN( + 224, "GPIO224", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO224"), + MTK_FUNCTION(1, "CONN_BT_IP") + ), + MTK_PIN( + 225, "GPIO225", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO225"), + MTK_FUNCTION(1, "CONN_BT_IN") + ), + MTK_PIN( + 226, "GPIO226", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO226"), + MTK_FUNCTION(1, "CONN_BT_QP") + ), + MTK_PIN( + 227, "GPIO227", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO227"), + MTK_FUNCTION(1, "CONN_BT_QN") + ), + MTK_PIN( + 228, "GPIO228", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO228"), + MTK_FUNCTION(1, "CONN_GPS_IP") + ), + MTK_PIN( + 229, "GPIO229", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO229"), + MTK_FUNCTION(1, "CONN_GPS_IN") + ), + MTK_PIN( + 230, "GPIO230", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO230"), + MTK_FUNCTION(1, "CONN_GPS_QP") + ), + MTK_PIN( + 231, "GPIO231", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO231"), + MTK_FUNCTION(1, "CONN_GPS_QN") + ), + MTK_PIN( + 232, "GPIO232", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO232"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "UTXD1"), + MTK_FUNCTION(3, "MD_URXD0"), + MTK_FUNCTION(4, "MD_URXD1"), + MTK_FUNCTION(5, "MD_URXD2"), + MTK_FUNCTION(6, "C2K_URXD0"), + MTK_FUNCTION(7, "C2K_URXD1") + ), + MTK_PIN( + 233, "GPIO233", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO233"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "URXD1"), + MTK_FUNCTION(3, "MD_UTXD0"), + MTK_FUNCTION(4, "MD_UTXD1"), + MTK_FUNCTION(5, "MD_UTXD2"), + MTK_FUNCTION(6, "C2K_UTXD0"), + MTK_FUNCTION(7, "C2K_UTXD1") + ), + MTK_PIN( + 234, "GPIO234", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO234"), + MTK_FUNCTION(1, "SPI1_CLK_B"), + MTK_FUNCTION(2, "TP_UTXD1_AO"), + MTK_FUNCTION(3, "SCL4_1"), + MTK_FUNCTION(4, "UTXD0"), + MTK_FUNCTION(6, "PWM_A"), + MTK_FUNCTION(7, "DBG_MON_A23") + ), + MTK_PIN( + 235, "GPIO235", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO235"), + MTK_FUNCTION(1, "SPI1_MI_B"), + MTK_FUNCTION(2, "SPI1_MO_B"), + MTK_FUNCTION(3, "SDA4_1"), + MTK_FUNCTION(4, "URXD0"), + MTK_FUNCTION(6, "CLKM0"), + MTK_FUNCTION(7, "DBG_MON_A24") + ), + MTK_PIN( + 236, "GPIO236", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO236"), + MTK_FUNCTION(1, "SPI1_MO_B"), + MTK_FUNCTION(2, "SPI1_MI_B"), + MTK_FUNCTION(3, "SCL5_1"), + MTK_FUNCTION(4, "URTS0"), + MTK_FUNCTION(6, "PWM_B"), + MTK_FUNCTION(7, "DBG_MON_A25") + ), + MTK_PIN( + 237, "GPIO237", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO237"), + MTK_FUNCTION(1, "SPI1_CS_B"), + MTK_FUNCTION(2, "TP_URXD1_AO"), + MTK_FUNCTION(3, "SDA5_1"), + MTK_FUNCTION(4, "UCTS0"), + MTK_FUNCTION(6, "CLKM1"), + MTK_FUNCTION(7, "DBG_MON_A26") + ), + MTK_PIN( + 238, "GPIO238", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO238"), + MTK_FUNCTION(1, "SDA4_0") + ), + MTK_PIN( + 239, "GPIO239", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO239"), + MTK_FUNCTION(1, "SCL4_0") + ), + MTK_PIN( + 240, "GPIO240", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO240"), + MTK_FUNCTION(1, "SDA5_0") + ), + MTK_PIN( + 241, "GPIO241", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO241"), + MTK_FUNCTION(1, "SCL5_0") + ), + MTK_PIN( + 242, "GPIO242", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO242"), + MTK_FUNCTION(1, "SPI2_CLK_B"), + MTK_FUNCTION(2, "TP_UTXD2_AO"), + MTK_FUNCTION(3, "SCL4_2"), + MTK_FUNCTION(4, "UTXD1"), + MTK_FUNCTION(5, "URTS3"), + MTK_FUNCTION(6, "PWM_C"), + MTK_FUNCTION(7, "DBG_MON_A27") + ), + MTK_PIN( + 243, "GPIO243", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO243"), + MTK_FUNCTION(1, "SPI2_MI_B"), + MTK_FUNCTION(2, "SPI2_MO_B"), + MTK_FUNCTION(3, "SDA4_2"), + MTK_FUNCTION(4, "URXD1"), + MTK_FUNCTION(5, "UCTS3"), + MTK_FUNCTION(6, "CLKM2"), + MTK_FUNCTION(7, "DBG_MON_A28") + ), + MTK_PIN( + 244, "GPIO244", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO244"), + MTK_FUNCTION(1, "SPI2_MO_B"), + MTK_FUNCTION(2, "SPI2_MI_B"), + MTK_FUNCTION(3, "SCL5_2"), + MTK_FUNCTION(4, "URTS1"), + MTK_FUNCTION(5, "UTXD3"), + MTK_FUNCTION(6, "PWM_D"), + MTK_FUNCTION(7, "DBG_MON_A29") + ), + MTK_PIN( + 245, "GPIO245", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO245"), + MTK_FUNCTION(1, "SPI2_CS_B"), + MTK_FUNCTION(2, "TP_URXD2_AO"), + MTK_FUNCTION(3, "SDA5_2"), + MTK_FUNCTION(4, "UCTS1"), + MTK_FUNCTION(5, "URXD3"), + MTK_FUNCTION(6, "CLKM3"), + MTK_FUNCTION(7, "DBG_MON_A30") + ), + MTK_PIN( + 246, "GPIO246", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO246"), + MTK_FUNCTION(1, "I2S1_LRCK"), + MTK_FUNCTION(2, "I2S2_LRCK"), + MTK_FUNCTION(3, "I2S0_LRCK"), + MTK_FUNCTION(4, "I2S3_LRCK"), + MTK_FUNCTION(5, "PCM0_SYNC"), + MTK_FUNCTION(6, "SPI5_CLK_C"), + MTK_FUNCTION(7, "DBG_MON_A31") + ), + MTK_PIN( + 247, "GPIO247", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO247"), + MTK_FUNCTION(1, "I2S1_BCK"), + MTK_FUNCTION(2, "I2S2_BCK"), + MTK_FUNCTION(3, "I2S0_BCK"), + MTK_FUNCTION(4, "I2S3_BCK"), + MTK_FUNCTION(5, "PCM0_CLK"), + MTK_FUNCTION(6, "SPI5_MI_C"), + MTK_FUNCTION(7, "DBG_MON_A32") + ), + MTK_PIN( + 248, "GPIO248", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO248"), + MTK_FUNCTION(1, "I2S2_DI"), + MTK_FUNCTION(2, "I2S2_DI"), + MTK_FUNCTION(3, "I2S0_DI"), + MTK_FUNCTION(4, "I2S0_DI"), + MTK_FUNCTION(5, "PCM0_DI"), + MTK_FUNCTION(6, "SPI5_CS_C") + ), + MTK_PIN( + 249, "GPIO249", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO249"), + MTK_FUNCTION(1, "I2S1_DO"), + MTK_FUNCTION(2, "I2S1_DO"), + MTK_FUNCTION(3, "I2S3_DO"), + MTK_FUNCTION(4, "I2S3_DO"), + MTK_FUNCTION(5, "PCM0_DO"), + MTK_FUNCTION(6, "SPI5_MO_C"), + MTK_FUNCTION(7, "TRAP_SRAM_PWR_BYPASS") + ), + MTK_PIN( + 250, "GPIO250", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO250"), + MTK_FUNCTION(1, "SPI3_MI"), + MTK_FUNCTION(2, "SPI3_MO"), + MTK_FUNCTION(3, "IRTX_OUT"), + MTK_FUNCTION(6, "TP_URXD1_AO"), + MTK_FUNCTION(7, "DROP_ZONE") + ), + MTK_PIN( + 251, "GPIO251", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO251"), + MTK_FUNCTION(1, "SPI3_MO"), + MTK_FUNCTION(2, "SPI3_MI"), + MTK_FUNCTION(3, "CMFLASH"), + MTK_FUNCTION(6, "TP_UTXD1_AO"), + MTK_FUNCTION(7, "C2K_RTCK") + ), + MTK_PIN( + 252, "GPIO252", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO252"), + MTK_FUNCTION(1, "SPI3_CLK"), + MTK_FUNCTION(2, "SCL0_4"), + MTK_FUNCTION(3, "PWM_D"), + MTK_FUNCTION(7, "C2K_TMS") + ), + MTK_PIN( + 253, "GPIO253", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO253"), + MTK_FUNCTION(1, "SPI3_CS"), + MTK_FUNCTION(2, "SDA0_4"), + MTK_FUNCTION(3, "PWM_A"), + MTK_FUNCTION(7, "C2K_TCK") + ), + MTK_PIN( + 254, "GPIO254", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO254"), + MTK_FUNCTION(1, "I2S1_MCK"), + MTK_FUNCTION(2, "I2S2_MCK"), + MTK_FUNCTION(3, "I2S0_MCK"), + MTK_FUNCTION(4, "I2S3_MCK"), + MTK_FUNCTION(5, "CLKM0"), + MTK_FUNCTION(7, "C2K_TDI") + ), + MTK_PIN( + 255, "GPIO255", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO255"), + MTK_FUNCTION(1, "CLKM1"), + MTK_FUNCTION(2, "DISP_PWM"), + MTK_FUNCTION(3, "PWM_B"), + MTK_FUNCTION(6, "TP_GPIO1_AO"), + MTK_FUNCTION(7, "C2K_TDO") + ), + MTK_PIN( + 256, "GPIO256", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO256"), + MTK_FUNCTION(1, "CLKM2"), + MTK_FUNCTION(2, "IRTX_OUT"), + MTK_FUNCTION(3, "PWM_C"), + MTK_FUNCTION(6, "TP_GPIO0_AO"), + MTK_FUNCTION(7, "C2K_NTRST") + ), + MTK_PIN( + 257, "GPIO257", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO257"), + MTK_FUNCTION(1, "IO_JTAG_TMS"), + MTK_FUNCTION(2, "LTE_JTAG_TMS"), + MTK_FUNCTION(3, "DFD_TMS"), + MTK_FUNCTION(4, "DAP_SIB1_SWD"), + MTK_FUNCTION(5, "ANC_JTAG_TMS"), + MTK_FUNCTION(6, "SCP_JTAG_TMS"), + MTK_FUNCTION(7, "C2K_DM_OTMS") + ), + MTK_PIN( + 258, "GPIO258", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO258"), + MTK_FUNCTION(1, "IO_JTAG_TCK"), + MTK_FUNCTION(2, "LTE_JTAG_TCK"), + MTK_FUNCTION(3, "DFD_TCK_XI"), + MTK_FUNCTION(4, "DAP_SIB1_SWCK"), + MTK_FUNCTION(5, "ANC_JTAG_TCK"), + MTK_FUNCTION(6, "SCP_JTAG_TCK"), + MTK_FUNCTION(7, "C2K_DM_OTCK") + ), + MTK_PIN( + 259, "GPIO259", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO259"), + MTK_FUNCTION(1, "IO_JTAG_TDI"), + MTK_FUNCTION(2, "LTE_JTAG_TDI"), + MTK_FUNCTION(3, "DFD_TDI"), + MTK_FUNCTION(5, "ANC_JTAG_TDI"), + MTK_FUNCTION(6, "SCP_JTAG_TDI"), + MTK_FUNCTION(7, "C2K_DM_OTDI") + ), + MTK_PIN( + 260, "GPIO260", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO260"), + MTK_FUNCTION(1, "IO_JTAG_TDO"), + MTK_FUNCTION(2, "LTE_JTAG_TDO"), + MTK_FUNCTION(3, "DFD_TDO"), + MTK_FUNCTION(5, "ANC_JTAG_TDO"), + MTK_FUNCTION(6, "SCP_JTAG_TDO"), + MTK_FUNCTION(7, "C2K_DM_OTDO") + ), + MTK_PIN( + 261, "GPIO261", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO261"), + MTK_FUNCTION(2, "LTE_JTAG_TRSTN"), + MTK_FUNCTION(3, "DFD_NTRST"), + MTK_FUNCTION(5, "ANC_JTAG_TRSTN"), + MTK_FUNCTION(6, "SCP_JTAG_TRSTN"), + MTK_FUNCTION(7, "C2K_DM_JTINTP") + ), +}; + +#endif /* __PINCTRL_MTK_MT6797_H */ diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index d2179028f134..b59e10852bfb 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -282,8 +282,8 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, case PIN_CONFIG_DRIVE_STRENGTH: if (hw->soc->drive_set) { err = hw->soc->drive_set(hw, desc, arg); - if (err) - return err; + if (err) + return err; } else { return -ENOTSUPP; } @@ -419,8 +419,8 @@ static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, pins = of_find_property(node, "pinmux", NULL); if (!pins) { - dev_err(hw->dev, "missing pins property in node %s .\n", - node->name); + dev_err(hw->dev, "missing pins property in node %pOFn .\n", + node); return -EINVAL; } diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c index 7dae1d7bf6b0..3277d17711b0 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c @@ -239,13 +239,9 @@ static const unsigned int eth_link_led_pins[] = { GPIOZ_14 }; static const unsigned int eth_act_led_pins[] = { GPIOZ_15 }; static const unsigned int tsin_a_d0_pins[] = { GPIODV_0 }; -static const unsigned int tsin_a_d0_x_pins[] = { GPIOX_10 }; static const unsigned int tsin_a_clk_pins[] = { GPIODV_8 }; -static const unsigned int tsin_a_clk_x_pins[] = { GPIOX_11 }; static const unsigned int tsin_a_sop_pins[] = { GPIODV_9 }; -static const unsigned int tsin_a_sop_x_pins[] = { GPIOX_8 }; static const unsigned int tsin_a_d_valid_pins[] = { GPIODV_10 }; -static const unsigned int tsin_a_d_valid_x_pins[] = { GPIOX_9 }; static const unsigned int tsin_a_fail_pins[] = { GPIODV_11 }; static const unsigned int tsin_a_dp_pins[] = { GPIODV_1, GPIODV_2, GPIODV_3, GPIODV_4, GPIODV_5, GPIODV_6, GPIODV_7, @@ -432,10 +428,6 @@ static struct meson_pmx_group meson_gxl_periphs_groups[] = { GROUP(spi_miso, 5, 2), GROUP(spi_ss0, 5, 1), GROUP(spi_sclk, 5, 0), - GROUP(tsin_a_sop_x, 6, 3), - GROUP(tsin_a_d_valid_x, 6, 2), - GROUP(tsin_a_d0_x, 6, 1), - GROUP(tsin_a_clk_x, 6, 0), /* Bank Z */ GROUP(eth_mdio, 4, 23), @@ -698,8 +690,8 @@ static const char * const eth_led_groups[] = { }; static const char * const tsin_a_groups[] = { - "tsin_a_clk", "tsin_a_clk_x", "tsin_a_sop", "tsin_a_sop_x", - "tsin_a_d_valid", "tsin_a_d_valid_x", "tsin_a_d0", "tsin_a_d0_x", + "tsin_a_clk", "tsin_a_sop", + "tsin_a_d_valid", "tsin_a_d0", "tsin_a_dp", "tsin_a_fail", }; diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c index 7ad50d9268aa..17f909d8b63a 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -1799,19 +1799,12 @@ static int npcm7xx_config_set_one(struct npcm7xx_pinctrl *npcm, npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); break; case PIN_CONFIG_INPUT_ENABLE: - if (arg) { - iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC); - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_IEM, - gpio); - } else - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_IEM, - gpio); + iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC); + bank->direction_input(&bank->gc, pin % bank->gc.ngpio); break; case PIN_CONFIG_OUTPUT: - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_IEM, gpio); - iowrite32(gpio, arg ? bank->base + NPCM7XX_GP_N_DOS : - bank->base + NPCM7XX_GP_N_DOC); iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES); + bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg); break; case PIN_CONFIG_DRIVE_PUSH_PULL: npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio); @@ -1932,6 +1925,9 @@ static int npcm7xx_gpio_of(struct npcm7xx_pinctrl *pctrl) pctrl->gpio_bank[id].gc.label = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOF", np); + if (pctrl->gpio_bank[id].gc.label == NULL) + return -ENOMEM; + pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show; pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].gc.direction_input; diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c index d3fe14394b73..2c7229380f08 100644 --- a/drivers/pinctrl/pinconf.c +++ b/drivers/pinctrl/pinconf.c @@ -366,29 +366,8 @@ static int pinconf_groups_show(struct seq_file *s, void *what) return 0; } -static int pinconf_pins_open(struct inode *inode, struct file *file) -{ - return single_open(file, pinconf_pins_show, inode->i_private); -} - -static int pinconf_groups_open(struct inode *inode, struct file *file) -{ - return single_open(file, pinconf_groups_show, inode->i_private); -} - -static const struct file_operations pinconf_pins_ops = { - .open = pinconf_pins_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static const struct file_operations pinconf_groups_ops = { - .open = pinconf_groups_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; +DEFINE_SHOW_ATTRIBUTE(pinconf_pins); +DEFINE_SHOW_ATTRIBUTE(pinconf_groups); #define MAX_NAME_LEN 15 @@ -613,9 +592,9 @@ void pinconf_init_device_debugfs(struct dentry *devroot, struct pinctrl_dev *pctldev) { debugfs_create_file("pinconf-pins", S_IFREG | S_IRUGO, - devroot, pctldev, &pinconf_pins_ops); + devroot, pctldev, &pinconf_pins_fops); debugfs_create_file("pinconf-groups", S_IFREG | S_IRUGO, - devroot, pctldev, &pinconf_groups_ops); + devroot, pctldev, &pinconf_groups_fops); debugfs_create_file("pinconf-config", (S_IRUGO | S_IWUSR | S_IWGRP), devroot, pctldev, &pinconf_dbg_pinconfig_fops); } diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 67718b0f978d..2a7d638978d8 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -791,8 +791,7 @@ static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) static int amd_gpio_suspend(struct device *dev) { - struct platform_device *pdev = to_platform_device(dev); - struct amd_gpio *gpio_dev = platform_get_drvdata(pdev); + struct amd_gpio *gpio_dev = dev_get_drvdata(dev); struct pinctrl_desc *desc = gpio_dev->pctrl->desc; int i; @@ -810,8 +809,7 @@ static int amd_gpio_suspend(struct device *dev) static int amd_gpio_resume(struct device *dev) { - struct platform_device *pdev = to_platform_device(dev); - struct amd_gpio *gpio_dev = platform_get_drvdata(pdev); + struct amd_gpio *gpio_dev = dev_get_drvdata(dev); struct pinctrl_desc *desc = gpio_dev->pctrl->desc; int i; diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 5a850491a5cb..4ee135d7b883 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -868,8 +868,7 @@ static struct pinctrl_desc atmel_pinctrl_desc = { static int __maybe_unused atmel_pctrl_suspend(struct device *dev) { - struct platform_device *pdev = to_platform_device(dev); - struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev); + struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev); int i, j; /* @@ -897,8 +896,7 @@ static int __maybe_unused atmel_pctrl_suspend(struct device *dev) static int __maybe_unused atmel_pctrl_resume(struct device *dev) { - struct platform_device *pdev = to_platform_device(dev); - struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev); + struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev); int i, j; for (i = 0; i < atmel_pioctrl->nbanks; i++) { diff --git a/drivers/pinctrl/pinctrl-lpc18xx.c b/drivers/pinctrl/pinctrl-lpc18xx.c index a14bc5e5fc24..06be55dab341 100644 --- a/drivers/pinctrl/pinctrl-lpc18xx.c +++ b/drivers/pinctrl/pinctrl-lpc18xx.c @@ -630,14 +630,8 @@ static const struct pinctrl_pin_desc lpc18xx_pins[] = { LPC18XX_PIN(i2c0_sda, PIN_I2C0_SDA), }; -/** - * enum lpc18xx_pin_config_param - possible pin configuration parameters - * @PIN_CONFIG_GPIO_PIN_INT: route gpio to the gpio pin interrupt - * controller. - */ -enum lpc18xx_pin_config_param { - PIN_CONFIG_GPIO_PIN_INT = PIN_CONFIG_END + 1, -}; +/* PIN_CONFIG_GPIO_PIN_INT: route gpio to the gpio pin interrupt controller */ +#define PIN_CONFIG_GPIO_PIN_INT (PIN_CONFIG_END + 1) static const struct pinconf_generic_params lpc18xx_params[] = { {"nxp,gpio-pin-interrupt", PIN_CONFIG_GPIO_PIN_INT, 0}, diff --git a/drivers/pinctrl/pinctrl-max77620.c b/drivers/pinctrl/pinctrl-max77620.c index a7f37063518e..3d05bc1937d4 100644 --- a/drivers/pinctrl/pinctrl-max77620.c +++ b/drivers/pinctrl/pinctrl-max77620.c @@ -34,14 +34,12 @@ enum max77620_pin_ppdrv { MAX77620_PIN_PP_DRV, }; -enum max77620_pinconf_param { - MAX77620_ACTIVE_FPS_SOURCE = PIN_CONFIG_END + 1, - MAX77620_ACTIVE_FPS_POWER_ON_SLOTS, - MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS, - MAX77620_SUSPEND_FPS_SOURCE, - MAX77620_SUSPEND_FPS_POWER_ON_SLOTS, - MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS, -}; +#define MAX77620_ACTIVE_FPS_SOURCE (PIN_CONFIG_END + 1) +#define MAX77620_ACTIVE_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 2) +#define MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS (PIN_CONFIG_END + 3) +#define MAX77620_SUSPEND_FPS_SOURCE (PIN_CONFIG_END + 4) +#define MAX77620_SUSPEND_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 5) +#define MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS (PIN_CONFIG_END + 6) struct max77620_pin_function { const char *name; diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 95e4a06de019..16bf21bf69a2 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -307,6 +307,12 @@ struct rockchip_mux_recalced_data { u8 mask; }; +enum rockchip_mux_route_location { + ROCKCHIP_ROUTE_SAME = 0, + ROCKCHIP_ROUTE_PMU, + ROCKCHIP_ROUTE_GRF, +}; + /** * struct rockchip_mux_recalced_data: represent a pin iomux data. * @bank_num: bank number. @@ -319,6 +325,7 @@ struct rockchip_mux_route_data { u8 bank_num; u8 pin; u8 func; + enum rockchip_mux_route_location route_location; u32 route_offset; u32 route_val; }; @@ -815,6 +822,26 @@ static struct rockchip_mux_route_data rk3128_mux_route_data[] = { }, }; +static struct rockchip_mux_route_data rk3188_mux_route_data[] = { + { + /* non-iomuxed emmc/flash pins on flash-dqs */ + .bank_num = 0, + .pin = 24, + .func = 1, + .route_location = ROCKCHIP_ROUTE_GRF, + .route_offset = 0xa0, + .route_val = BIT(16 + 11), + }, { + /* non-iomuxed emmc/flash pins on emmc-clk */ + .bank_num = 0, + .pin = 24, + .func = 2, + .route_location = ROCKCHIP_ROUTE_GRF, + .route_offset = 0xa0, + .route_val = BIT(16 + 11) | BIT(11), + }, +}; + static struct rockchip_mux_route_data rk3228_mux_route_data[] = { { /* pwm0-0 */ @@ -1091,7 +1118,7 @@ static struct rockchip_mux_route_data rk3399_mux_route_data[] = { }; static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, - int mux, u32 *reg, u32 *value) + int mux, u32 *loc, u32 *reg, u32 *value) { struct rockchip_pinctrl *info = bank->drvdata; struct rockchip_pin_ctrl *ctrl = info->ctrl; @@ -1108,6 +1135,7 @@ static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, if (i >= ctrl->niomux_routes) return false; + *loc = data->route_location; *reg = data->route_offset; *value = data->route_val; @@ -1210,7 +1238,7 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) struct regmap *regmap; int reg, ret, mask, mux_type; u8 bit; - u32 data, rmask, route_reg, route_val; + u32 data, rmask, route_location, route_reg, route_val; ret = rockchip_verify_mux(bank, pin, mux); if (ret < 0) @@ -1247,9 +1275,21 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); if (bank->route_mask & BIT(pin)) { - if (rockchip_get_mux_route(bank, pin, mux, &route_reg, - &route_val)) { - ret = regmap_write(regmap, route_reg, route_val); + if (rockchip_get_mux_route(bank, pin, mux, &route_location, + &route_reg, &route_val)) { + struct regmap *route_regmap = regmap; + + /* handle special locations */ + switch (route_location) { + case ROCKCHIP_ROUTE_PMU: + route_regmap = info->regmap_pmu; + break; + case ROCKCHIP_ROUTE_GRF: + route_regmap = info->regmap_base; + break; + } + + ret = regmap_write(route_regmap, route_reg, route_val); if (ret) return ret; } @@ -3606,6 +3646,8 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = { .label = "RK3188-GPIO", .type = RK3188, .grf_mux_offset = 0x60, + .iomux_routes = rk3188_mux_route_data, + .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data), .pull_calc_reg = rk3188_calc_pull_reg_and_bit, }; diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c index cbf58a10113d..4d87d75b9c6e 100644 --- a/drivers/pinctrl/pinctrl-sx150x.c +++ b/drivers/pinctrl/pinctrl-sx150x.c @@ -1166,7 +1166,6 @@ static int sx150x_probe(struct i2c_client *client, } /* Register GPIO controller */ - pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL); pctl->gpio.base = -1; pctl->gpio.ngpio = pctl->data->npins; pctl->gpio.get_direction = sx150x_gpio_get_direction; @@ -1180,6 +1179,10 @@ static int sx150x_probe(struct i2c_client *client, pctl->gpio.of_node = dev->of_node; #endif pctl->gpio.can_sleep = true; + pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL); + if (!pctl->gpio.label) + return -ENOMEM; + /* * Setting multiple pins is not safe when all pins are not * handled by the same regmap register. The oscio pin (present @@ -1200,13 +1203,15 @@ static int sx150x_probe(struct i2c_client *client, /* Add Interrupt support if an irq is specified */ if (client->irq > 0) { - pctl->irq_chip.name = devm_kstrdup(dev, client->name, - GFP_KERNEL); pctl->irq_chip.irq_mask = sx150x_irq_mask; pctl->irq_chip.irq_unmask = sx150x_irq_unmask; pctl->irq_chip.irq_set_type = sx150x_irq_set_type; pctl->irq_chip.irq_bus_lock = sx150x_irq_bus_lock; pctl->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock; + pctl->irq_chip.name = devm_kstrdup(dev, client->name, + GFP_KERNEL); + if (!pctl->irq_chip.name) + return -ENOMEM; pctl->irq.masked = ~0; pctl->irq.sense = 0; diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c index a0daf27042bd..90fd37e8207b 100644 --- a/drivers/pinctrl/pinctrl-zynq.c +++ b/drivers/pinctrl/pinctrl-zynq.c @@ -971,15 +971,12 @@ enum zynq_io_standards { zynq_iostd_max }; -/** - * enum zynq_pin_config_param - possible pin configuration parameters - * @PIN_CONFIG_IOSTANDARD: if the pin can select an IO standard, the argument to +/* + * PIN_CONFIG_IOSTANDARD: if the pin can select an IO standard, the argument to * this parameter (on a custom format) tells the driver which alternative * IO standard to use. */ -enum zynq_pin_config_param { - PIN_CONFIG_IOSTANDARD = PIN_CONFIG_END + 1, -}; +#define PIN_CONFIG_IOSTANDARD (PIN_CONFIG_END + 1) static const struct pinconf_generic_params zynq_dt_params[] = { {"io-standard", PIN_CONFIG_IOSTANDARD, zynq_iostd_lvcmos18}, diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index 5780442c068b..4d0cc1889dd9 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -644,37 +644,16 @@ void pinmux_show_setting(struct seq_file *s, setting->data.mux.func); } -static int pinmux_functions_open(struct inode *inode, struct file *file) -{ - return single_open(file, pinmux_functions_show, inode->i_private); -} - -static int pinmux_pins_open(struct inode *inode, struct file *file) -{ - return single_open(file, pinmux_pins_show, inode->i_private); -} - -static const struct file_operations pinmux_functions_ops = { - .open = pinmux_functions_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static const struct file_operations pinmux_pins_ops = { - .open = pinmux_pins_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; +DEFINE_SHOW_ATTRIBUTE(pinmux_functions); +DEFINE_SHOW_ATTRIBUTE(pinmux_pins); void pinmux_init_device_debugfs(struct dentry *devroot, struct pinctrl_dev *pctldev) { debugfs_create_file("pinmux-functions", S_IFREG | S_IRUGO, - devroot, pctldev, &pinmux_functions_ops); + devroot, pctldev, &pinmux_functions_fops); debugfs_create_file("pinmux-pins", S_IFREG | S_IRUGO, - devroot, pctldev, &pinmux_pins_ops); + devroot, pctldev, &pinmux_pins_fops); } #endif /* CONFIG_DEBUG_FS */ diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 7c7d083e2c0d..87cbebe217fd 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -1072,6 +1072,25 @@ static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) } } +static int msm_pinctrl_suspend(struct device *dev) +{ + struct msm_pinctrl *pctrl = dev_get_drvdata(dev); + + return pinctrl_force_sleep(pctrl->pctrl); +} + +static int msm_pinctrl_resume(struct device *dev) +{ + struct msm_pinctrl *pctrl = dev_get_drvdata(dev); + + return pinctrl_force_default(pctrl->pctrl); +} + +SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend, + msm_pinctrl_resume); + +EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops); + int msm_pinctrl_probe(struct platform_device *pdev, const struct msm_pinctrl_soc_data *soc_data) { diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index 29172fdf5882..c12048e54a6f 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -123,6 +123,8 @@ struct msm_pinctrl_soc_data { unsigned int ntiles; }; +extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops; + int msm_pinctrl_probe(struct platform_device *pdev, const struct msm_pinctrl_soc_data *soc_data); int msm_pinctrl_remove(struct platform_device *pdev); diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index 2ab7a8885757..c97f20fca5fd 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -1300,6 +1300,7 @@ static const struct of_device_id sdm845_pinctrl_of_match[] = { static struct platform_driver sdm845_pinctrl_driver = { .driver = { .name = "sdm845-pinctrl", + .pm = &msm_pinctrl_dev_pm_ops, .of_match_table = sdm845_pinctrl_of_match, }, .probe = sdm845_pinctrl_probe, diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index a29efbe08f48..4458d44dfcf6 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1028,10 +1028,23 @@ static int pmic_gpio_probe(struct platform_device *pdev) return ret; } - ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins); - if (ret) { - dev_err(dev, "failed to add pin range\n"); - goto err_range; + /* + * For DeviceTree-supported systems, the gpio core checks the + * pinctrl's device node for the "gpio-ranges" property. + * If it is present, it takes care of adding the pin ranges + * for the driver. In this case the driver can skip ahead. + * + * In order to remain compatible with older, existing DeviceTree + * files which don't set the "gpio-ranges" property or systems that + * utilize ACPI the driver has to call gpiochip_add_pin_range(). + */ + if (!of_property_read_bool(dev->of_node, "gpio-ranges")) { + ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, + npins); + if (ret) { + dev_err(dev, "failed to add pin range\n"); + goto err_range; + } } return 0; @@ -1055,6 +1068,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */ { .compatible = "qcom,pmi8994-gpio" }, /* 10 GPIO's */ { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */ + { .compatible = "qcom,pms405-gpio" }, /* 12 GPIO's, holes on 1 9 10 */ { .compatible = "qcom,spmi-gpio" }, /* Generic */ { }, }; diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c index 6b30bef829ab..ded7d765af2e 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c @@ -762,12 +762,23 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev) return ret; } - ret = gpiochip_add_pin_range(&pctrl->chip, - dev_name(pctrl->dev), - 0, 0, pctrl->chip.ngpio); - if (ret) { - dev_err(pctrl->dev, "failed to add pin range\n"); - goto unregister_gpiochip; + /* + * For DeviceTree-supported systems, the gpio core checks the + * pinctrl's device node for the "gpio-ranges" property. + * If it is present, it takes care of adding the pin ranges + * for the driver. In this case the driver can skip ahead. + * + * In order to remain compatible with older, existing DeviceTree + * files which don't set the "gpio-ranges" property or systems that + * utilize ACPI the driver has to call gpiochip_add_pin_range(). + */ + if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { + ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), + 0, 0, pctrl->chip.ngpio); + if (ret) { + dev_err(pctrl->dev, "failed to add pin range\n"); + goto unregister_gpiochip; + } } platform_set_drvdata(pdev, pctrl); diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.c b/drivers/pinctrl/sprd/pinctrl-sprd.c index 4537b5453996..7d9a44bd0047 100644 --- a/drivers/pinctrl/sprd/pinctrl-sprd.c +++ b/drivers/pinctrl/sprd/pinctrl-sprd.c @@ -159,10 +159,8 @@ struct sprd_pinctrl { struct sprd_pinctrl_soc_info *info; }; -enum sprd_pinconf_params { - SPRD_PIN_CONFIG_CONTROL = PIN_CONFIG_END + 1, - SPRD_PIN_CONFIG_SLEEP_MODE = PIN_CONFIG_END + 2, -}; +#define SPRD_PIN_CONFIG_CONTROL (PIN_CONFIG_END + 1) +#define SPRD_PIN_CONFIG_SLEEP_MODE (PIN_CONFIG_END + 2) static int sprd_pinctrl_get_id_by_name(struct sprd_pinctrl *sprd_pctl, const char *name) diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 0fbfcc9ea07c..813eccbb9aaf 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -8,6 +8,7 @@ */ #include <linux/clk.h> #include <linux/gpio/driver.h> +#include <linux/hwspinlock.h> #include <linux/io.h> #include <linux/irq.h> #include <linux/mfd/syscon.h> @@ -51,6 +52,8 @@ #define gpio_range_to_bank(chip) \ container_of(chip, struct stm32_gpio_bank, range) +#define HWSPINLOCK_TIMEOUT 5 /* msec */ + static const char * const stm32_gpio_functions[] = { "gpio", "af0", "af1", "af2", "af3", "af4", @@ -91,6 +94,7 @@ struct stm32_pinctrl { struct irq_domain *domain; struct regmap *regmap; struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK]; + struct hwspinlock *hwlock; }; static inline int stm32_gpio_pin(int gpio) @@ -576,14 +580,24 @@ static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev, static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank, int pin, u32 mode, u32 alt) { + struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); u32 val; int alt_shift = (pin % 8) * 4; int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; unsigned long flags; + int err = 0; clk_enable(bank->clk); spin_lock_irqsave(&bank->lock, flags); + if (pctl->hwlock) + err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT); + + if (err) { + dev_err(pctl->dev, "Can't get hwspinlock\n"); + goto unlock; + } + val = readl_relaxed(bank->base + alt_offset); val &= ~GENMASK(alt_shift + 3, alt_shift); val |= (alt << alt_shift); @@ -594,6 +608,10 @@ static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank, val |= mode << (pin * 2); writel_relaxed(val, bank->base + STM32_GPIO_MODER); + if (pctl->hwlock) + hwspin_unlock(pctl->hwlock); + +unlock: spin_unlock_irqrestore(&bank->lock, flags); clk_disable(bank->clk); } @@ -683,17 +701,31 @@ static const struct pinmux_ops stm32_pmx_ops = { static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank, unsigned offset, u32 drive) { + struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); unsigned long flags; u32 val; + int err = 0; clk_enable(bank->clk); spin_lock_irqsave(&bank->lock, flags); + if (pctl->hwlock) + err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT); + + if (err) { + dev_err(pctl->dev, "Can't get hwspinlock\n"); + goto unlock; + } + val = readl_relaxed(bank->base + STM32_GPIO_TYPER); val &= ~BIT(offset); val |= drive << offset; writel_relaxed(val, bank->base + STM32_GPIO_TYPER); + if (pctl->hwlock) + hwspin_unlock(pctl->hwlock); + +unlock: spin_unlock_irqrestore(&bank->lock, flags); clk_disable(bank->clk); } @@ -719,17 +751,31 @@ static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank, unsigned offset, u32 speed) { + struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); unsigned long flags; u32 val; + int err = 0; clk_enable(bank->clk); spin_lock_irqsave(&bank->lock, flags); + if (pctl->hwlock) + err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT); + + if (err) { + dev_err(pctl->dev, "Can't get hwspinlock\n"); + goto unlock; + } + val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); val &= ~GENMASK(offset * 2 + 1, offset * 2); val |= speed << (offset * 2); writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); + if (pctl->hwlock) + hwspin_unlock(pctl->hwlock); + +unlock: spin_unlock_irqrestore(&bank->lock, flags); clk_disable(bank->clk); } @@ -755,17 +801,31 @@ static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank, unsigned offset, u32 bias) { + struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); unsigned long flags; u32 val; + int err = 0; clk_enable(bank->clk); spin_lock_irqsave(&bank->lock, flags); + if (pctl->hwlock) + err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT); + + if (err) { + dev_err(pctl->dev, "Can't get hwspinlock\n"); + goto unlock; + } + val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); val &= ~GENMASK(offset * 2 + 1, offset * 2); val |= bias << (offset * 2); writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); + if (pctl->hwlock) + hwspin_unlock(pctl->hwlock); + +unlock: spin_unlock_irqrestore(&bank->lock, flags); clk_disable(bank->clk); } @@ -1140,7 +1200,7 @@ int stm32_pctl_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct stm32_pinctrl *pctl; struct pinctrl_pin_desc *pins; - int i, ret, banks = 0; + int i, ret, hwlock_id, banks = 0; if (!np) return -EINVAL; @@ -1160,6 +1220,15 @@ int stm32_pctl_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pctl); + /* hwspinlock is optional */ + hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0); + if (hwlock_id < 0) { + if (hwlock_id == -EPROBE_DEFER) + return hwlock_id; + } else { + pctl->hwlock = hwspin_lock_request_specific(hwlock_id); + } + pctl->dev = dev; pctl->match_data = match->data; ret = stm32_pctrl_build_state(pdev); diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 95282cda6cee..a731fc966b63 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -6,6 +6,10 @@ config PINCTRL_SUNXI select GENERIC_PINCONF select GPIOLIB +config PINCTRL_SUNIV_F1C100S + def_bool MACH_SUNIV + select PINCTRL_SUNXI + config PINCTRL_SUN4I_A10 def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I select PINCTRL_SUNXI diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index adb8443aa55c..fafcdae8134f 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -3,6 +3,7 @@ obj-y += pinctrl-sunxi.o # SoC Drivers +obj-$(CONFIG_PINCTRL_SUNIV_F1C100S) += pinctrl-suniv-f1c100s.o obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o obj-$(CONFIG_PINCTRL_SUN5I) += pinctrl-sun5i.o obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c index f5f77432ce6f..7b83d3755a0e 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c @@ -323,71 +323,71 @@ static const struct sunxi_desc_pin a64_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "csi0"), /* PCK */ - SUNXI_FUNCTION(0x4, "ts0")), /* CLK */ + SUNXI_FUNCTION(0x2, "csi"), /* PCK */ + SUNXI_FUNCTION(0x4, "ts")), /* CLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "csi0"), /* CK */ - SUNXI_FUNCTION(0x4, "ts0")), /* ERR */ + SUNXI_FUNCTION(0x2, "csi"), /* CK */ + SUNXI_FUNCTION(0x4, "ts")), /* ERR */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "csi0"), /* HSYNC */ - SUNXI_FUNCTION(0x4, "ts0")), /* SYNC */ + SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ + SUNXI_FUNCTION(0x4, "ts")), /* SYNC */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "csi0"), /* VSYNC */ - SUNXI_FUNCTION(0x4, "ts0")), /* DVLD */ + SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ + SUNXI_FUNCTION(0x4, "ts")), /* DVLD */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "csi0"), /* D0 */ - SUNXI_FUNCTION(0x4, "ts0")), /* D0 */ + SUNXI_FUNCTION(0x2, "csi"), /* D0 */ + SUNXI_FUNCTION(0x4, "ts")), /* D0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "csi0"), /* D1 */ - SUNXI_FUNCTION(0x4, "ts0")), /* D1 */ + SUNXI_FUNCTION(0x2, "csi"), /* D1 */ + SUNXI_FUNCTION(0x4, "ts")), /* D1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "csi0"), /* D2 */ - SUNXI_FUNCTION(0x4, "ts0")), /* D2 */ + SUNXI_FUNCTION(0x2, "csi"), /* D2 */ + SUNXI_FUNCTION(0x4, "ts")), /* D2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "csi0"), /* D3 */ - SUNXI_FUNCTION(0x4, "ts0")), /* D3 */ + SUNXI_FUNCTION(0x2, "csi"), /* D3 */ + SUNXI_FUNCTION(0x4, "ts")), /* D3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "csi0"), /* D4 */ - SUNXI_FUNCTION(0x4, "ts0")), /* D4 */ + SUNXI_FUNCTION(0x2, "csi"), /* D4 */ + SUNXI_FUNCTION(0x4, "ts")), /* D4 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "csi0"), /* D5 */ - SUNXI_FUNCTION(0x4, "ts0")), /* D5 */ + SUNXI_FUNCTION(0x2, "csi"), /* D5 */ + SUNXI_FUNCTION(0x4, "ts")), /* D5 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "csi0"), /* D6 */ - SUNXI_FUNCTION(0x4, "ts0")), /* D6 */ + SUNXI_FUNCTION(0x2, "csi"), /* D6 */ + SUNXI_FUNCTION(0x4, "ts")), /* D6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "csi0"), /* D7 */ - SUNXI_FUNCTION(0x4, "ts0")), /* D7 */ + SUNXI_FUNCTION(0x2, "csi"), /* D7 */ + SUNXI_FUNCTION(0x4, "ts")), /* D7 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "csi0")), /* SCK */ + SUNXI_FUNCTION(0x2, "csi")), /* SCK */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "csi0")), /* SDA */ + SUNXI_FUNCTION(0x2, "csi")), /* SDA */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), diff --git a/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c b/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c new file mode 100644 index 000000000000..2801ca706273 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c @@ -0,0 +1,416 @@ +/* + * Allwinner new F-series F1C100s SoC (suniv) pinctrl driver. + * + * Copyright (C) 2018 Icenowy Zheng + * + * Icenowy Zheng <icenowy@aosc.io> + * + * Copyright (C) 2014 Jackie Hwang + * + * Jackie Hwang <huangshr@allwinnertech.com> + * + * Copyright (C) 2014 Chen-Yu Tsai + * + * Chen-Yu Tsai <wens@csie.org> + * + * Copyright (C) 2014 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-sunxi.h" +static const struct sunxi_desc_pin suniv_f1c100s_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "rtp"), /* X1 */ + SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */ + SUNXI_FUNCTION(0x5, "uart1"), /* RTS */ + SUNXI_FUNCTION(0x6, "spi1")), /* CS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "rtp"), /* X2 */ + SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */ + SUNXI_FUNCTION(0x5, "uart1"), /* CTS */ + SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "rtp"), /* Y1 */ + SUNXI_FUNCTION(0x3, "pwm0"), /* PWM0 */ + SUNXI_FUNCTION(0x4, "i2s"), /* IN */ + SUNXI_FUNCTION(0x5, "uart1"), /* RX */ + SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "rtp"), /* Y2 */ + SUNXI_FUNCTION(0x3, "ir0"), /* RX */ + SUNXI_FUNCTION(0x4, "i2s"), /* OUT */ + SUNXI_FUNCTION(0x5, "uart1"), /* TX */ + SUNXI_FUNCTION(0x6, "spi1")), /* MISO */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dram"), /* DQS0 */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */ + SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */ + SUNXI_FUNCTION(0x5, "uart1"), /* RTS */ + SUNXI_FUNCTION(0x6, "spi1")), /* CS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dram"), /* DQS1 */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */ + SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */ + SUNXI_FUNCTION(0x5, "uart1"), /* CTS */ + SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dram"), /* CKE */ + SUNXI_FUNCTION(0x3, "pwm0"), /* PWM0 */ + SUNXI_FUNCTION(0x4, "i2s"), /* IN */ + SUNXI_FUNCTION(0x5, "uart1"), /* RX */ + SUNXI_FUNCTION(0x6, "spi1")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dram"), /* DDR_REF_D */ + SUNXI_FUNCTION(0x3, "ir0"), /* RX */ + SUNXI_FUNCTION(0x4, "i2s"), /* OUT */ + SUNXI_FUNCTION(0x5, "uart1"), /* TX */ + SUNXI_FUNCTION(0x6, "spi1")), /* MISO */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ + SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CS */ + SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ + SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ + SUNXI_FUNCTION(0x3, "uart0")), /* TX */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D2 */ + SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */ + SUNXI_FUNCTION(0x4, "rsb"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart1"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D4*/ + SUNXI_FUNCTION(0x3, "uart1"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D5 */ + SUNXI_FUNCTION(0x3, "uart1"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D6 */ + SUNXI_FUNCTION(0x3, "uart1"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D7 */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D10 */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D11 */ + SUNXI_FUNCTION(0x3, "i2s"), /* MCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D12 */ + SUNXI_FUNCTION(0x3, "i2s"), /* BCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D13 */ + SUNXI_FUNCTION(0x3, "i2s"), /* LRCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D14 */ + SUNXI_FUNCTION(0x3, "i2s"), /* IN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D15 */ + SUNXI_FUNCTION(0x3, "i2s"), /* OUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D18 */ + SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */ + SUNXI_FUNCTION(0x4, "rsb"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D19 */ + SUNXI_FUNCTION(0x3, "uart2"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D20 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D21 */ + SUNXI_FUNCTION(0x3, "uart2"), /* RTS */ + SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D22 */ + SUNXI_FUNCTION(0x3, "uart2"), /* CTS */ + SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D23 */ + SUNXI_FUNCTION(0x3, "spdif"), /* OUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* CLK */ + SUNXI_FUNCTION(0x3, "spi0"), /* CS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* DE */ + SUNXI_FUNCTION(0x3, "spi0"), /* MOSI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* HYSNC */ + SUNXI_FUNCTION(0x3, "spi0"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "spi0"), /* MISO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "lcd"), /* D0 */ + SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */ + SUNXI_FUNCTION(0x5, "uart0"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "lcd"), /* D1 */ + SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */ + SUNXI_FUNCTION(0x5, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ + SUNXI_FUNCTION(0x3, "lcd"), /* D8 */ + SUNXI_FUNCTION(0x4, "clk"), /* OUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D0 */ + SUNXI_FUNCTION(0x3, "lcd"), /* D9 */ + SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */ + SUNXI_FUNCTION(0x5, "rsb"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D1 */ + SUNXI_FUNCTION(0x3, "lcd"), /* D16 */ + SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */ + SUNXI_FUNCTION(0x5, "rsb"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D2 */ + SUNXI_FUNCTION(0x3, "lcd"), /* D17 */ + SUNXI_FUNCTION(0x4, "i2s"), /* IN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D3 */ + SUNXI_FUNCTION(0x3, "pwm1"), /* PWM1 */ + SUNXI_FUNCTION(0x4, "i2s"), /* OUT */ + SUNXI_FUNCTION(0x5, "spdif"), /* OUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D4 */ + SUNXI_FUNCTION(0x3, "uart2"), /* TX */ + SUNXI_FUNCTION(0x4, "spi1"), /* CS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D5 */ + SUNXI_FUNCTION(0x3, "uart2"), /* RX */ + SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D6 */ + SUNXI_FUNCTION(0x3, "uart2"), /* RTS */ + SUNXI_FUNCTION(0x4, "spi1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D7 */ + SUNXI_FUNCTION(0x3, "uart2"), /* CTS */ + SUNXI_FUNCTION(0x4, "spi1"), /* MISO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "clk0"), /* OUT */ + SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */ + SUNXI_FUNCTION(0x4, "ir"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */ + SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */ + SUNXI_FUNCTION(0x4, "pwm0"), /* PWM0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), + + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x3, "jtag"), /* MS */ + SUNXI_FUNCTION(0x4, "ir0"), /* MS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x3, "dgb0"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x3, "jtag"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x3, "jtag"), /* CK */ + SUNXI_FUNCTION(0x4, "pwm1"), /* PWM1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), +}; + +static const struct sunxi_pinctrl_desc suniv_f1c100s_pinctrl_data = { + .pins = suniv_f1c100s_pins, + .npins = ARRAY_SIZE(suniv_f1c100s_pins), + .irq_banks = 3, +}; + +static int suniv_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &suniv_f1c100s_pinctrl_data); +} + +static const struct of_device_id suniv_f1c100s_pinctrl_match[] = { + { .compatible = "allwinner,suniv-f1c100s-pinctrl", }, + {} +}; + +static struct platform_driver suniv_f1c100s_pinctrl_driver = { + .probe = suniv_pinctrl_probe, + .driver = { + .name = "suniv-f1c100s-pinctrl", + .of_match_table = suniv_f1c100s_pinctrl_match, + }, +}; +builtin_platform_driver(suniv_f1c100s_pinctrl_driver); diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c index add8e870667b..b2412f1f2b25 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -1,17 +1,7 @@ -/* - * Copyright (C) 2015-2017 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2015-2017 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <linux/list.h> #include <linux/mfd/syscon.h> diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c index 280dca725d6e..ce7cde099bff 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c @@ -1,17 +1,7 @@ -/* - * Copyright (C) 2016-2017 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2016-2017 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <linux/kernel.h> #include <linux/init.h> diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c index d2d56c985c83..916709133a00 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c @@ -1,17 +1,7 @@ -/* - * Copyright (C) 2016-2017 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2016-2017 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <linux/kernel.h> #include <linux/init.h> diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c index 03d87ad82726..4e7a99fe947b 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c @@ -1,17 +1,7 @@ -/* - * Copyright (C) 2015-2017 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2015-2017 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <linux/kernel.h> #include <linux/init.h> diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c index 31f36ea53911..2b089d118c4e 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c @@ -1,17 +1,7 @@ -/* - * Copyright (C) 2015-2017 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2015-2017 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <linux/kernel.h> #include <linux/init.h> diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c index 4326f5c3683c..583a2cdb5e5e 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c @@ -1,17 +1,7 @@ -/* - * Copyright (C) 2015-2017 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program5 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2015-2017 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <linux/kernel.h> #include <linux/init.h> diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c index ae7981530141..92d85cc2e204 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c @@ -1,17 +1,7 @@ -/* - * Copyright (C) 2015-2017 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program5 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2015-2017 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <linux/kernel.h> #include <linux/init.h> diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c index 7975bd7f99c8..436e23cda615 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c @@ -1,17 +1,7 @@ -/* - * Copyright (C) 2015-2017 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2015-2017 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <linux/kernel.h> #include <linux/init.h> diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c index b16ce283695b..91d77c1de6c2 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c @@ -1,17 +1,7 @@ -/* - * Copyright (C) 2017 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2017 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <linux/init.h> #include <linux/kernel.h> diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c index cb44568fcbbc..8b17f23d3c03 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c @@ -1,17 +1,7 @@ -/* - * Copyright (C) 2015-2017 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2015-2017 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <linux/kernel.h> #include <linux/init.h> diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h index c63e3c8b97cd..3b30ca023605 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h @@ -1,16 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2015-2017 Socionext Inc. * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef __PINCTRL_UNIPHIER_H__ |