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path: root/drivers/net/ethernet/freescale/xgmac_mdio.c
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Diffstat (limited to 'drivers/net/ethernet/freescale/xgmac_mdio.c')
-rw-r--r--drivers/net/ethernet/freescale/xgmac_mdio.c98
1 files changed, 69 insertions, 29 deletions
diff --git a/drivers/net/ethernet/freescale/xgmac_mdio.c b/drivers/net/ethernet/freescale/xgmac_mdio.c
index 3a83bc2c613c..7b8fe866f603 100644
--- a/drivers/net/ethernet/freescale/xgmac_mdio.c
+++ b/drivers/net/ethernet/freescale/xgmac_mdio.c
@@ -46,17 +46,43 @@ struct tgec_mdio_controller {
#define MDIO_DATA(x) (x & 0xffff)
#define MDIO_DATA_BSY BIT(31)
+struct mdio_fsl_priv {
+ struct tgec_mdio_controller __iomem *mdio_base;
+ bool is_little_endian;
+};
+
+static u32 xgmac_read32(void __iomem *regs,
+ bool is_little_endian)
+{
+ if (is_little_endian)
+ return ioread32(regs);
+ else
+ return ioread32be(regs);
+}
+
+static void xgmac_write32(u32 value,
+ void __iomem *regs,
+ bool is_little_endian)
+{
+ if (is_little_endian)
+ iowrite32(value, regs);
+ else
+ iowrite32be(value, regs);
+}
+
/*
* Wait until the MDIO bus is free
*/
static int xgmac_wait_until_free(struct device *dev,
- struct tgec_mdio_controller __iomem *regs)
+ struct tgec_mdio_controller __iomem *regs,
+ bool is_little_endian)
{
unsigned int timeout;
/* Wait till the bus is free */
timeout = TIMEOUT;
- while ((ioread32be(&regs->mdio_stat) & MDIO_STAT_BSY) && timeout) {
+ while ((xgmac_read32(&regs->mdio_stat, is_little_endian) &
+ MDIO_STAT_BSY) && timeout) {
cpu_relax();
timeout--;
}
@@ -73,13 +99,15 @@ static int xgmac_wait_until_free(struct device *dev,
* Wait till the MDIO read or write operation is complete
*/
static int xgmac_wait_until_done(struct device *dev,
- struct tgec_mdio_controller __iomem *regs)
+ struct tgec_mdio_controller __iomem *regs,
+ bool is_little_endian)
{
unsigned int timeout;
/* Wait till the MDIO write is complete */
timeout = TIMEOUT;
- while ((ioread32be(&regs->mdio_data) & MDIO_DATA_BSY) && timeout) {
+ while ((xgmac_read32(&regs->mdio_stat, is_little_endian) &
+ MDIO_STAT_BSY) && timeout) {
cpu_relax();
timeout--;
}
@@ -99,12 +127,14 @@ static int xgmac_wait_until_done(struct device *dev,
*/
static int xgmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value)
{
- struct tgec_mdio_controller __iomem *regs = bus->priv;
+ struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
+ struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
uint16_t dev_addr;
u32 mdio_ctl, mdio_stat;
int ret;
+ bool endian = priv->is_little_endian;
- mdio_stat = ioread32be(&regs->mdio_stat);
+ mdio_stat = xgmac_read32(&regs->mdio_stat, endian);
if (regnum & MII_ADDR_C45) {
/* Clause 45 (ie 10G) */
dev_addr = (regnum >> 16) & 0x1f;
@@ -115,29 +145,29 @@ static int xgmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 val
mdio_stat &= ~MDIO_STAT_ENC;
}
- iowrite32be(mdio_stat, &regs->mdio_stat);
+ xgmac_write32(mdio_stat, &regs->mdio_stat, endian);
- ret = xgmac_wait_until_free(&bus->dev, regs);
+ ret = xgmac_wait_until_free(&bus->dev, regs, endian);
if (ret)
return ret;
/* Set the port and dev addr */
mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
- iowrite32be(mdio_ctl, &regs->mdio_ctl);
+ xgmac_write32(mdio_ctl, &regs->mdio_ctl, endian);
/* Set the register address */
if (regnum & MII_ADDR_C45) {
- iowrite32be(regnum & 0xffff, &regs->mdio_addr);
+ xgmac_write32(regnum & 0xffff, &regs->mdio_addr, endian);
- ret = xgmac_wait_until_free(&bus->dev, regs);
+ ret = xgmac_wait_until_free(&bus->dev, regs, endian);
if (ret)
return ret;
}
/* Write the value to the register */
- iowrite32be(MDIO_DATA(value), &regs->mdio_data);
+ xgmac_write32(MDIO_DATA(value), &regs->mdio_data, endian);
- ret = xgmac_wait_until_done(&bus->dev, regs);
+ ret = xgmac_wait_until_done(&bus->dev, regs, endian);
if (ret)
return ret;
@@ -151,14 +181,16 @@ static int xgmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 val
*/
static int xgmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
{
- struct tgec_mdio_controller __iomem *regs = bus->priv;
+ struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
+ struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
uint16_t dev_addr;
uint32_t mdio_stat;
uint32_t mdio_ctl;
uint16_t value;
int ret;
+ bool endian = priv->is_little_endian;
- mdio_stat = ioread32be(&regs->mdio_stat);
+ mdio_stat = xgmac_read32(&regs->mdio_stat, endian);
if (regnum & MII_ADDR_C45) {
dev_addr = (regnum >> 16) & 0x1f;
mdio_stat |= MDIO_STAT_ENC;
@@ -167,41 +199,41 @@ static int xgmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
mdio_stat &= ~MDIO_STAT_ENC;
}
- iowrite32be(mdio_stat, &regs->mdio_stat);
+ xgmac_write32(mdio_stat, &regs->mdio_stat, endian);
- ret = xgmac_wait_until_free(&bus->dev, regs);
+ ret = xgmac_wait_until_free(&bus->dev, regs, endian);
if (ret)
return ret;
/* Set the Port and Device Addrs */
mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
- iowrite32be(mdio_ctl, &regs->mdio_ctl);
+ xgmac_write32(mdio_ctl, &regs->mdio_ctl, endian);
/* Set the register address */
if (regnum & MII_ADDR_C45) {
- iowrite32be(regnum & 0xffff, &regs->mdio_addr);
+ xgmac_write32(regnum & 0xffff, &regs->mdio_addr, endian);
- ret = xgmac_wait_until_free(&bus->dev, regs);
+ ret = xgmac_wait_until_free(&bus->dev, regs, endian);
if (ret)
return ret;
}
/* Initiate the read */
- iowrite32be(mdio_ctl | MDIO_CTL_READ, &regs->mdio_ctl);
+ xgmac_write32(mdio_ctl | MDIO_CTL_READ, &regs->mdio_ctl, endian);
- ret = xgmac_wait_until_done(&bus->dev, regs);
+ ret = xgmac_wait_until_done(&bus->dev, regs, endian);
if (ret)
return ret;
/* Return all Fs if nothing was there */
- if (ioread32be(&regs->mdio_stat) & MDIO_STAT_RD_ER) {
+ if (xgmac_read32(&regs->mdio_stat, endian) & MDIO_STAT_RD_ER) {
dev_err(&bus->dev,
"Error while reading PHY%d reg at %d.%hhu\n",
phy_id, dev_addr, regnum);
return 0xffff;
}
- value = ioread32be(&regs->mdio_data) & 0xffff;
+ value = xgmac_read32(&regs->mdio_data, endian) & 0xffff;
dev_dbg(&bus->dev, "read %04x\n", value);
return value;
@@ -212,6 +244,7 @@ static int xgmac_mdio_probe(struct platform_device *pdev)
struct device_node *np = pdev->dev.of_node;
struct mii_bus *bus;
struct resource res;
+ struct mdio_fsl_priv *priv;
int ret;
ret = of_address_to_resource(np, 0, &res);
@@ -220,7 +253,7 @@ static int xgmac_mdio_probe(struct platform_device *pdev)
return ret;
}
- bus = mdiobus_alloc();
+ bus = mdiobus_alloc_size(sizeof(struct mdio_fsl_priv));
if (!bus)
return -ENOMEM;
@@ -231,12 +264,19 @@ static int xgmac_mdio_probe(struct platform_device *pdev)
snprintf(bus->id, MII_BUS_ID_SIZE, "%llx", (unsigned long long)res.start);
/* Set the PHY base address */
- bus->priv = of_iomap(np, 0);
- if (!bus->priv) {
+ priv = bus->priv;
+ priv->mdio_base = of_iomap(np, 0);
+ if (!priv->mdio_base) {
ret = -ENOMEM;
goto err_ioremap;
}
+ if (of_get_property(pdev->dev.of_node,
+ "little-endian", NULL))
+ priv->is_little_endian = true;
+ else
+ priv->is_little_endian = false;
+
ret = of_mdiobus_register(bus, np);
if (ret) {
dev_err(&pdev->dev, "cannot register MDIO bus\n");
@@ -248,7 +288,7 @@ static int xgmac_mdio_probe(struct platform_device *pdev)
return 0;
err_registration:
- iounmap(bus->priv);
+ iounmap(priv->mdio_base);
err_ioremap:
mdiobus_free(bus);
@@ -267,7 +307,7 @@ static int xgmac_mdio_remove(struct platform_device *pdev)
return 0;
}
-static struct of_device_id xgmac_mdio_match[] = {
+static const struct of_device_id xgmac_mdio_match[] = {
{
.compatible = "fsl,fman-xmdio",
},
generated by cgit v1.2.3 (git 2.39.1) at 2024-10-31 15:44:18 +0000