summaryrefslogtreecommitdiffstats
path: root/drivers/mtd/nand/raw/marvell_nand.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/mtd/nand/raw/marvell_nand.c')
-rw-r--r--drivers/mtd/nand/raw/marvell_nand.c34
1 files changed, 28 insertions, 6 deletions
diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c
index 528a8e0342bd..3d84f4252af4 100644
--- a/drivers/mtd/nand/raw/marvell_nand.c
+++ b/drivers/mtd/nand/raw/marvell_nand.c
@@ -308,6 +308,7 @@ struct marvell_nfc_caps {
* @dev: Parent device (used to print error messages)
* @regs: NAND controller registers
* @ecc_clk: ECC block clock, two times the NAND controller clock
+ * @reg_clk: Regiters clock
* @complete: Completion object to wait for NAND controller events
* @assigned_cs: Bitmask describing already assigned CS lines
* @chips: List containing all the NAND chips attached to
@@ -321,6 +322,7 @@ struct marvell_nfc {
struct device *dev;
void __iomem *regs;
struct clk *ecc_clk;
+ struct clk *reg_clk;
struct completion complete;
unsigned long assigned_cs;
struct list_head chips;
@@ -2757,7 +2759,12 @@ static int marvell_nfc_probe(struct platform_device *pdev)
return irq;
}
- nfc->ecc_clk = devm_clk_get(&pdev->dev, NULL);
+ nfc->ecc_clk = devm_clk_get(&pdev->dev, "core");
+
+ /* Managed the legacy case (when the first clock was not named) */
+ if (nfc->ecc_clk == ERR_PTR(-ENOENT))
+ nfc->ecc_clk = devm_clk_get(&pdev->dev, NULL);
+
if (IS_ERR(nfc->ecc_clk))
return PTR_ERR(nfc->ecc_clk);
@@ -2765,12 +2772,24 @@ static int marvell_nfc_probe(struct platform_device *pdev)
if (ret)
return ret;
+ nfc->reg_clk = devm_clk_get(&pdev->dev, "reg");
+ if (PTR_ERR(nfc->reg_clk) != -ENOENT) {
+ if (!IS_ERR(nfc->reg_clk)) {
+ ret = clk_prepare_enable(nfc->reg_clk);
+ if (ret)
+ goto unprepare_ecc_clk;
+ } else {
+ ret = PTR_ERR(nfc->reg_clk);
+ goto unprepare_ecc_clk;
+ }
+ }
+
marvell_nfc_disable_int(nfc, NDCR_ALL_INT);
marvell_nfc_clear_int(nfc, NDCR_ALL_INT);
ret = devm_request_irq(dev, irq, marvell_nfc_isr,
0, "marvell-nfc", nfc);
if (ret)
- goto unprepare_clk;
+ goto unprepare_reg_clk;
/* Get NAND controller capabilities */
if (pdev->id_entry)
@@ -2781,23 +2800,25 @@ static int marvell_nfc_probe(struct platform_device *pdev)
if (!nfc->caps) {
dev_err(dev, "Could not retrieve NFC caps\n");
ret = -EINVAL;
- goto unprepare_clk;
+ goto unprepare_reg_clk;
}
/* Init the controller and then probe the chips */
ret = marvell_nfc_init(nfc);
if (ret)
- goto unprepare_clk;
+ goto unprepare_reg_clk;
platform_set_drvdata(pdev, nfc);
ret = marvell_nand_chips_init(dev, nfc);
if (ret)
- goto unprepare_clk;
+ goto unprepare_reg_clk;
return 0;
-unprepare_clk:
+unprepare_reg_clk:
+ clk_disable_unprepare(nfc->reg_clk);
+unprepare_ecc_clk:
clk_disable_unprepare(nfc->ecc_clk);
return ret;
@@ -2814,6 +2835,7 @@ static int marvell_nfc_remove(struct platform_device *pdev)
dma_release_channel(nfc->dma_chan);
}
+ clk_disable_unprepare(nfc->reg_clk);
clk_disable_unprepare(nfc->ecc_clk);
return 0;