diff options
Diffstat (limited to 'drivers/gpu/drm/i915/display/vlv_dsi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/vlv_dsi.c | 440 |
1 files changed, 239 insertions, 201 deletions
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c index 4514529ff6f3..d07cfad8ce6f 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c @@ -85,7 +85,7 @@ void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port), mask, 100)) - DRM_ERROR("DPI FIFOs are not empty\n"); + drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n"); } static void write_data(struct drm_i915_private *dev_priv, @@ -100,7 +100,7 @@ static void write_data(struct drm_i915_private *dev_priv, for (j = 0; j < min_t(u32, len - i, 4); j++) val |= *data++ << 8 * j; - I915_WRITE(reg, val); + intel_de_write(dev_priv, reg, val); } } @@ -111,7 +111,7 @@ static void read_data(struct drm_i915_private *dev_priv, u32 i, j; for (i = 0; i < len; i += 4) { - u32 val = I915_READ(reg); + u32 val = intel_de_read(dev_priv, reg); for (j = 0; j < min_t(u32, len - i, 4); j++) *data++ = val >> 8 * j; @@ -154,29 +154,34 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, if (packet.payload_length) { if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), data_mask, 50)) - DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); + drm_err(&dev_priv->drm, + "Timeout waiting for HS/LP DATA FIFO !full\n"); write_data(dev_priv, data_reg, packet.payload, packet.payload_length); } if (msg->rx_len) { - I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); + intel_de_write(dev_priv, MIPI_INTR_STAT(port), + GEN_READ_DATA_AVAIL); } if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), ctrl_mask, 50)) { - DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); + drm_err(&dev_priv->drm, + "Timeout waiting for HS/LP CTRL FIFO !full\n"); } - I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); + intel_de_write(dev_priv, ctrl_reg, + header[2] << 16 | header[1] << 8 | header[0]); /* ->rx_len is set only for reads */ if (msg->rx_len) { data_mask = GEN_READ_DATA_AVAIL; if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), data_mask, 50)) - DRM_ERROR("Timeout waiting for read data.\n"); + drm_err(&dev_priv->drm, + "Timeout waiting for read data.\n"); read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); } @@ -223,17 +228,19 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, cmd |= DPI_LP_MODE; /* clear bit */ - I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); + intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); /* XXX: old code skips write if control unchanged */ - if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) - DRM_DEBUG_KMS("Same special packet %02x twice in a row.\n", cmd); + if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port))) + drm_dbg_kms(&dev_priv->drm, + "Same special packet %02x twice in a row.\n", cmd); - I915_WRITE(MIPI_DPI_CONTROL(port), cmd); + intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd); mask = SPL_PKT_SENT_INTERRUPT; if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100)) - DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); + drm_err(&dev_priv->drm, + "Video mode command 0x%08x send failed.\n", cmd); return 0; } @@ -265,7 +272,7 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder, struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; int ret; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; if (fixed_mode) { @@ -328,36 +335,37 @@ static bool glk_dsi_enable_io(struct intel_encoder *encoder) * Power ON MIPI IO first and then write into IO reset and LP wake bits */ for_each_dsi_port(port, intel_dsi->ports) { - tmp = I915_READ(MIPI_CTRL(port)); - I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE); + tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); + intel_de_write(dev_priv, MIPI_CTRL(port), + tmp | GLK_MIPIIO_ENABLE); } /* Put the IO into reset */ - tmp = I915_READ(MIPI_CTRL(PORT_A)); + tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); tmp &= ~GLK_MIPIIO_RESET_RELEASED; - I915_WRITE(MIPI_CTRL(PORT_A), tmp); + intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp); /* Program LP Wake */ for_each_dsi_port(port, intel_dsi->ports) { - tmp = I915_READ(MIPI_CTRL(port)); - if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) + tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); + if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) tmp &= ~GLK_LP_WAKE; else tmp |= GLK_LP_WAKE; - I915_WRITE(MIPI_CTRL(port), tmp); + intel_de_write(dev_priv, MIPI_CTRL(port), tmp); } /* Wait for Pwr ACK */ for_each_dsi_port(port, intel_dsi->ports) { if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED, 20)) - DRM_ERROR("MIPIO port is powergated\n"); + drm_err(&dev_priv->drm, "MIPIO port is powergated\n"); } /* Check for cold boot scenario */ for_each_dsi_port(port, intel_dsi->ports) { cold_boot |= - !(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY); + !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY); } return cold_boot; @@ -374,48 +382,49 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder) for_each_dsi_port(port, intel_dsi->ports) { if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY, 20)) - DRM_ERROR("PHY is not ON\n"); + drm_err(&dev_priv->drm, "PHY is not ON\n"); } /* Get IO out of reset */ - val = I915_READ(MIPI_CTRL(PORT_A)); - I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED); + val = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); + intel_de_write(dev_priv, MIPI_CTRL(PORT_A), + val | GLK_MIPIIO_RESET_RELEASED); /* Get IO out of Low power state*/ for_each_dsi_port(port, intel_dsi->ports) { - if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) { - val = I915_READ(MIPI_DEVICE_READY(port)); + if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) { + val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); val &= ~ULPS_STATE_MASK; val |= DEVICE_READY; - I915_WRITE(MIPI_DEVICE_READY(port), val); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); usleep_range(10, 15); } else { /* Enter ULPS */ - val = I915_READ(MIPI_DEVICE_READY(port)); + val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); val &= ~ULPS_STATE_MASK; val |= (ULPS_STATE_ENTER | DEVICE_READY); - I915_WRITE(MIPI_DEVICE_READY(port), val); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); /* Wait for ULPS active */ if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 20)) - DRM_ERROR("ULPS not active\n"); + drm_err(&dev_priv->drm, "ULPS not active\n"); /* Exit ULPS */ - val = I915_READ(MIPI_DEVICE_READY(port)); + val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); val &= ~ULPS_STATE_MASK; val |= (ULPS_STATE_EXIT | DEVICE_READY); - I915_WRITE(MIPI_DEVICE_READY(port), val); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); /* Enter Normal Mode */ - val = I915_READ(MIPI_DEVICE_READY(port)); + val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); val &= ~ULPS_STATE_MASK; val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); - I915_WRITE(MIPI_DEVICE_READY(port), val); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); - val = I915_READ(MIPI_CTRL(port)); + val = intel_de_read(dev_priv, MIPI_CTRL(port)); val &= ~GLK_LP_WAKE; - I915_WRITE(MIPI_CTRL(port), val); + intel_de_write(dev_priv, MIPI_CTRL(port), val); } } @@ -423,14 +432,16 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder) for_each_dsi_port(port, intel_dsi->ports) { if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE, 20)) - DRM_ERROR("Date lane not in STOP state\n"); + drm_err(&dev_priv->drm, + "Date lane not in STOP state\n"); } /* Wait for AFE LATCH */ for_each_dsi_port(port, intel_dsi->ports) { if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT, 20)) - DRM_ERROR("D-PHY not entering LP-11 state\n"); + drm_err(&dev_priv->drm, + "D-PHY not entering LP-11 state\n"); } } @@ -441,23 +452,24 @@ static void bxt_dsi_device_ready(struct intel_encoder *encoder) enum port port; u32 val; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); /* Enable MIPI PHY transparent latch */ for_each_dsi_port(port, intel_dsi->ports) { - val = I915_READ(BXT_MIPI_PORT_CTRL(port)); - I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); + val = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); + intel_de_write(dev_priv, BXT_MIPI_PORT_CTRL(port), + val | LP_OUTPUT_HOLD); usleep_range(2000, 2500); } /* Clear ULPS and set device ready */ for_each_dsi_port(port, intel_dsi->ports) { - val = I915_READ(MIPI_DEVICE_READY(port)); + val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); val &= ~ULPS_STATE_MASK; - I915_WRITE(MIPI_DEVICE_READY(port), val); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); usleep_range(2000, 2500); val |= DEVICE_READY; - I915_WRITE(MIPI_DEVICE_READY(port), val); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); } } @@ -468,7 +480,7 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder) enum port port; u32 val; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); vlv_flisdsi_get(dev_priv); /* program rcomp for compliance, reduce from 50 ohms to 45 ohms @@ -481,21 +493,25 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder) for_each_dsi_port(port, intel_dsi->ports) { - I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), + ULPS_STATE_ENTER); usleep_range(2500, 3000); /* Enable MIPI PHY transparent latch * Common bit for both MIPI Port A & MIPI Port C * No similar bit in MIPI Port C reg */ - val = I915_READ(MIPI_PORT_CTRL(PORT_A)); - I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); + val = intel_de_read(dev_priv, MIPI_PORT_CTRL(PORT_A)); + intel_de_write(dev_priv, MIPI_PORT_CTRL(PORT_A), + val | LP_OUTPUT_HOLD); usleep_range(1000, 1500); - I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), + ULPS_STATE_EXIT); usleep_range(2500, 3000); - I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), + DEVICE_READY); usleep_range(2500, 3000); } } @@ -521,24 +537,25 @@ static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) /* Enter ULPS */ for_each_dsi_port(port, intel_dsi->ports) { - val = I915_READ(MIPI_DEVICE_READY(port)); + val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); val &= ~ULPS_STATE_MASK; val |= (ULPS_STATE_ENTER | DEVICE_READY); - I915_WRITE(MIPI_DEVICE_READY(port), val); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); } /* Wait for MIPI PHY status bit to unset */ for_each_dsi_port(port, intel_dsi->ports) { if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY, 20)) - DRM_ERROR("PHY is not turning OFF\n"); + drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); } /* Wait for Pwr ACK bit to unset */ for_each_dsi_port(port, intel_dsi->ports) { if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED, 20)) - DRM_ERROR("MIPI IO Port is not powergated\n"); + drm_err(&dev_priv->drm, + "MIPI IO Port is not powergated\n"); } } @@ -550,22 +567,22 @@ static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) u32 tmp; /* Put the IO into reset */ - tmp = I915_READ(MIPI_CTRL(PORT_A)); + tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); tmp &= ~GLK_MIPIIO_RESET_RELEASED; - I915_WRITE(MIPI_CTRL(PORT_A), tmp); + intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp); /* Wait for MIPI PHY status bit to unset */ for_each_dsi_port(port, intel_dsi->ports) { if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY, 20)) - DRM_ERROR("PHY is not turning OFF\n"); + drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); } /* Clear MIPI mode */ for_each_dsi_port(port, intel_dsi->ports) { - tmp = I915_READ(MIPI_CTRL(port)); + tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); tmp &= ~GLK_MIPIIO_ENABLE; - I915_WRITE(MIPI_CTRL(port), tmp); + intel_de_write(dev_priv, MIPI_CTRL(port), tmp); } } @@ -581,23 +598,23 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum port port; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); for_each_dsi_port(port, intel_dsi->ports) { /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); u32 val; - I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | - ULPS_STATE_ENTER); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), + DEVICE_READY | ULPS_STATE_ENTER); usleep_range(2000, 2500); - I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | - ULPS_STATE_EXIT); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), + DEVICE_READY | ULPS_STATE_EXIT); usleep_range(2000, 2500); - I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | - ULPS_STATE_ENTER); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), + DEVICE_READY | ULPS_STATE_ENTER); usleep_range(2000, 2500); /* @@ -607,14 +624,14 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) if ((IS_GEN9_LP(dev_priv) || port == PORT_A) && intel_de_wait_for_clear(dev_priv, port_ctrl, AFE_LATCHOUT, 30)) - DRM_ERROR("DSI LP not going Low\n"); + drm_err(&dev_priv->drm, "DSI LP not going Low\n"); /* Disable MIPI PHY transparent latch */ - val = I915_READ(port_ctrl); - I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD); + val = intel_de_read(dev_priv, port_ctrl); + intel_de_write(dev_priv, port_ctrl, val & ~LP_OUTPUT_HOLD); usleep_range(1000, 1500); - I915_WRITE(MIPI_DEVICE_READY(port), 0x00); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00); usleep_range(2000, 2500); } } @@ -631,18 +648,20 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, u32 temp; if (IS_GEN9_LP(dev_priv)) { for_each_dsi_port(port, intel_dsi->ports) { - temp = I915_READ(MIPI_CTRL(port)); + temp = intel_de_read(dev_priv, + MIPI_CTRL(port)); temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK | intel_dsi->pixel_overlap << BXT_PIXEL_OVERLAP_CNT_SHIFT; - I915_WRITE(MIPI_CTRL(port), temp); + intel_de_write(dev_priv, MIPI_CTRL(port), + temp); } } else { - temp = I915_READ(VLV_CHICKEN_3); + temp = intel_de_read(dev_priv, VLV_CHICKEN_3); temp &= ~PIXEL_OVERLAP_CNT_MASK | intel_dsi->pixel_overlap << PIXEL_OVERLAP_CNT_SHIFT; - I915_WRITE(VLV_CHICKEN_3, temp); + intel_de_write(dev_priv, VLV_CHICKEN_3, temp); } } @@ -651,7 +670,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); u32 temp; - temp = I915_READ(port_ctrl); + temp = intel_de_read(dev_priv, port_ctrl); temp &= ~LANE_CONFIGURATION_MASK; temp &= ~DUAL_LINK_MODE_MASK; @@ -671,8 +690,8 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, temp |= DITHERING_ENABLE; /* assert ip_tg_enable signal */ - I915_WRITE(port_ctrl, temp | DPI_ENABLE); - POSTING_READ(port_ctrl); + intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE); + intel_de_posting_read(dev_priv, port_ctrl); } } @@ -689,9 +708,9 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder) u32 temp; /* de-assert ip_tg_enable signal */ - temp = I915_READ(port_ctrl); - I915_WRITE(port_ctrl, temp & ~DPI_ENABLE); - POSTING_READ(port_ctrl); + temp = intel_de_read(dev_priv, port_ctrl); + intel_de_write(dev_priv, port_ctrl, temp & ~DPI_ENABLE); + intel_de_posting_read(dev_priv, port_ctrl); } } @@ -753,7 +772,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, u32 val; bool glk_cold_boot = false; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); @@ -771,22 +790,22 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, if (IS_BROXTON(dev_priv)) { /* Add MIPI IO reset programming for modeset */ - val = I915_READ(BXT_P_CR_GT_DISP_PWRON); - I915_WRITE(BXT_P_CR_GT_DISP_PWRON, - val | MIPIO_RST_CTRL); + val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); + intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, + val | MIPIO_RST_CTRL); /* Power up DSI regulator */ - I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); - I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0); + intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); + intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0); } if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { u32 val; /* Disable DPOunit clock gating, can stall pipe */ - val = I915_READ(DSPCLK_GATE_D); + val = intel_de_read(dev_priv, DSPCLK_GATE_D); val |= DPOUNIT_CLOCK_GATE_DISABLE; - I915_WRITE(DSPCLK_GATE_D, val); + intel_de_write(dev_priv, DSPCLK_GATE_D, val); } if (!IS_GEMINILAKE(dev_priv)) @@ -820,7 +839,8 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, * recommendation, port should be enabled befor plane & pipe */ if (is_cmd_mode(intel_dsi)) { for_each_dsi_port(port, intel_dsi->ports) - I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); + intel_de_write(dev_priv, + MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON); intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); } else { @@ -838,6 +858,15 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); } +static void bxt_dsi_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state) +{ + WARN_ON(crtc_state->has_pch_encoder); + + intel_crtc_vblank_on(crtc_state); +} + /* * DSI port disable has to be done after pipe and plane disable, so we do it in * the post_disable hook. @@ -886,7 +915,7 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder, enum port port; u32 val; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); if (IS_GEN9_LP(dev_priv)) { intel_crtc_vblank_off(old_crtc_state); @@ -917,13 +946,14 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder, if (IS_BROXTON(dev_priv)) { /* Power down DSI regulator to save power */ - I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); - I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT); + intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); + intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, + HS_IO_CTRL_SELECT); /* Add MIPI IO reset programming for modeset */ - val = I915_READ(BXT_P_CR_GT_DISP_PWRON); - I915_WRITE(BXT_P_CR_GT_DISP_PWRON, - val & ~MIPIO_RST_CTRL); + val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); + intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, + val & ~MIPIO_RST_CTRL); } if (IS_GEN9_LP(dev_priv)) { @@ -933,9 +963,9 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder, vlv_dsi_pll_disable(encoder); - val = I915_READ(DSPCLK_GATE_D); + val = intel_de_read(dev_priv, DSPCLK_GATE_D); val &= ~DPOUNIT_CLOCK_GATE_DISABLE; - I915_WRITE(DSPCLK_GATE_D, val); + intel_de_write(dev_priv, DSPCLK_GATE_D, val); } /* Assert reset */ @@ -960,7 +990,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, enum port port; bool active = false; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); wakeref = intel_display_power_get_if_enabled(dev_priv, encoder->power_domain); @@ -979,7 +1009,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, for_each_dsi_port(port, intel_dsi->ports) { i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ? BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); - bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE; + bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE; /* * Due to some hardware limitations on VLV/CHV, the DPI enable @@ -988,26 +1018,27 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, */ if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && port == PORT_C) - enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; + enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; /* Try command mode if video mode not enabled */ if (!enabled) { - u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port)); + u32 tmp = intel_de_read(dev_priv, + MIPI_DSI_FUNC_PRG(port)); enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; } if (!enabled) continue; - if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) + if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) continue; if (IS_GEN9_LP(dev_priv)) { - u32 tmp = I915_READ(MIPI_CTRL(port)); + u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); tmp &= BXT_PIPE_SELECT_MASK; tmp >>= BXT_PIPE_SELECT_SHIFT; - if (WARN_ON(tmp > PIPE_C)) + if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C)) continue; *pipe = tmp; @@ -1051,11 +1082,11 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, * encoder->get_hw_state() returns true. */ for_each_dsi_port(port, intel_dsi->ports) { - if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) + if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) break; } - fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; + fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; bpp = mipi_dsi_pixel_format_to_bpp( pixel_format_from_register_bits(fmt)); @@ -1067,21 +1098,24 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, /* In terms of pixels */ adjusted_mode->crtc_hdisplay = - I915_READ(BXT_MIPI_TRANS_HACTIVE(port)); + intel_de_read(dev_priv, + BXT_MIPI_TRANS_HACTIVE(port)); adjusted_mode->crtc_vdisplay = - I915_READ(BXT_MIPI_TRANS_VACTIVE(port)); + intel_de_read(dev_priv, + BXT_MIPI_TRANS_VACTIVE(port)); adjusted_mode->crtc_vtotal = - I915_READ(BXT_MIPI_TRANS_VTOTAL(port)); + intel_de_read(dev_priv, + BXT_MIPI_TRANS_VTOTAL(port)); hactive = adjusted_mode->crtc_hdisplay; - hfp = I915_READ(MIPI_HFP_COUNT(port)); + hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port)); /* * Meaningful for video mode non-burst sync pulse mode only, * can be zero for non-burst sync events and burst modes */ - hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port)); - hbp = I915_READ(MIPI_HBP_COUNT(port)); + hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port)); + hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port)); /* harizontal values are in terms of high speed byte clock */ hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, @@ -1098,9 +1132,9 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, } /* vertical values are in terms of lines */ - vfp = I915_READ(MIPI_VFP_COUNT(port)); - vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port)); - vbp = I915_READ(MIPI_VBP_COUNT(port)); + vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port)); + vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port)); + vbp = intel_de_read(dev_priv, MIPI_VBP_COUNT(port)); adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; @@ -1191,7 +1225,7 @@ static void intel_dsi_get_config(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u32 pclk; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); @@ -1268,26 +1302,29 @@ static void set_dsi_timings(struct drm_encoder *encoder, * vactive, as they are calculated per channel basis, * whereas these values should be based on resolution. */ - I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port), - adjusted_mode->crtc_hdisplay); - I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port), - adjusted_mode->crtc_vdisplay); - I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port), - adjusted_mode->crtc_vtotal); + intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port), + adjusted_mode->crtc_hdisplay); + intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port), + adjusted_mode->crtc_vdisplay); + intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port), + adjusted_mode->crtc_vtotal); } - I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); - I915_WRITE(MIPI_HFP_COUNT(port), hfp); + intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port), + hactive); + intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp); /* meaningful for video mode non-burst sync pulse mode only, * can be zero for non-burst sync events and burst modes */ - I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); - I915_WRITE(MIPI_HBP_COUNT(port), hbp); + intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port), + hsync); + intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp); /* vertical values are in terms of lines */ - I915_WRITE(MIPI_VFP_COUNT(port), vfp); - I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); - I915_WRITE(MIPI_VBP_COUNT(port), vbp); + intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp); + intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port), + vsync); + intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp); } } @@ -1322,7 +1359,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder, u32 val, tmp; u16 mode_hdisplay; - DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); + drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(intel_crtc->pipe)); mode_hdisplay = adjusted_mode->crtc_hdisplay; @@ -1338,35 +1375,35 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder, * escape clock divider, 20MHz, shared for A and C. * device ready must be off when doing this! txclkesc? */ - tmp = I915_READ(MIPI_CTRL(PORT_A)); + tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; - I915_WRITE(MIPI_CTRL(PORT_A), tmp | - ESCAPE_CLOCK_DIVIDER_1); + intel_de_write(dev_priv, MIPI_CTRL(PORT_A), + tmp | ESCAPE_CLOCK_DIVIDER_1); /* read request priority is per pipe */ - tmp = I915_READ(MIPI_CTRL(port)); + tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); tmp &= ~READ_REQUEST_PRIORITY_MASK; - I915_WRITE(MIPI_CTRL(port), tmp | - READ_REQUEST_PRIORITY_HIGH); + intel_de_write(dev_priv, MIPI_CTRL(port), + tmp | READ_REQUEST_PRIORITY_HIGH); } else if (IS_GEN9_LP(dev_priv)) { enum pipe pipe = intel_crtc->pipe; - tmp = I915_READ(MIPI_CTRL(port)); + tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); tmp &= ~BXT_PIPE_SELECT_MASK; tmp |= BXT_PIPE_SELECT(pipe); - I915_WRITE(MIPI_CTRL(port), tmp); + intel_de_write(dev_priv, MIPI_CTRL(port), tmp); } /* XXX: why here, why like this? handling in irq handler?! */ - I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); - I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); + intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff); + intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff); - I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); + intel_de_write(dev_priv, MIPI_DPHY_PARAM(port), + intel_dsi->dphy_reg); - I915_WRITE(MIPI_DPI_RESOLUTION(port), - adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | - mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); + intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port), + adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); } set_dsi_timings(encoder, adjusted_mode); @@ -1393,7 +1430,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder, } for_each_dsi_port(port, intel_dsi->ports) { - I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); + intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val); /* timeouts for recovery. one frame IIUC. if counter expires, * EOT and stop state. */ @@ -1414,28 +1451,24 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder, if (is_vid_mode(intel_dsi) && intel_dsi->video_mode_format == VIDEO_MODE_BURST) { - I915_WRITE(MIPI_HS_TX_TIMEOUT(port), - txbyteclkhs(adjusted_mode->crtc_htotal, bpp, - intel_dsi->lane_count, - intel_dsi->burst_mode_ratio) + 1); + intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), + txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); } else { - I915_WRITE(MIPI_HS_TX_TIMEOUT(port), - txbyteclkhs(adjusted_mode->crtc_vtotal * - adjusted_mode->crtc_htotal, - bpp, intel_dsi->lane_count, - intel_dsi->burst_mode_ratio) + 1); + intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), + txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); } - I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); - I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), - intel_dsi->turn_arnd_val); - I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), - intel_dsi->rst_timer_val); + intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port), + intel_dsi->lp_rx_timeout); + intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port), + intel_dsi->turn_arnd_val); + intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port), + intel_dsi->rst_timer_val); /* dphy stuff */ /* in terms of low power clock */ - I915_WRITE(MIPI_INIT_COUNT(port), - txclkesc(intel_dsi->escape_clk_div, 100)); + intel_de_write(dev_priv, MIPI_INIT_COUNT(port), + txclkesc(intel_dsi->escape_clk_div, 100)); if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) { /* @@ -1444,24 +1477,25 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder, * getting used. So write the other port * if not in dual link mode. */ - I915_WRITE(MIPI_INIT_COUNT(port == - PORT_A ? PORT_C : PORT_A), - intel_dsi->init_count); + intel_de_write(dev_priv, + MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A), + intel_dsi->init_count); } /* recovery disables */ - I915_WRITE(MIPI_EOT_DISABLE(port), tmp); + intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp); /* in terms of low power clock */ - I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); + intel_de_write(dev_priv, MIPI_INIT_COUNT(port), + intel_dsi->init_count); /* in terms of txbyteclkhs. actual high to low switch + * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. * * XXX: write MIPI_STOP_STATE_STALL? */ - I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), - intel_dsi->hs_to_lp_count); + intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port), + intel_dsi->hs_to_lp_count); /* XXX: low power clock equivalence in terms of byte clock. * the number of byte clocks occupied in one low power clock. @@ -1469,14 +1503,15 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder, * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL * ) / 105.??? */ - I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); + intel_de_write(dev_priv, MIPI_LP_BYTECLK(port), + intel_dsi->lp_byte_clk); if (IS_GEMINILAKE(dev_priv)) { - I915_WRITE(MIPI_TLPX_TIME_COUNT(port), - intel_dsi->lp_byte_clk); + intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port), + intel_dsi->lp_byte_clk); /* Shadow of DPHY reg */ - I915_WRITE(MIPI_CLK_LANE_TIMING(port), - intel_dsi->dphy_reg); + intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port), + intel_dsi->dphy_reg); } /* the bw essential for transmitting 16 long packets containing @@ -1484,21 +1519,18 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder, * this register in terms of byte clocks. based on dsi transfer * rate and the number of lanes configured the time taken to * transmit 16 long packets in a dsi stream varies. */ - I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); + intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port), + intel_dsi->bw_timer); - I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), - intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | - intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); + intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port), + intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); if (is_vid_mode(intel_dsi)) /* Some panels might have resolution which is not a * multiple of 64 like 1366 x 768. Enable RANDOM * resolution support for such panels by default */ - I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), - intel_dsi->video_frmt_cfg_bits | - intel_dsi->video_mode_format | - IP_TG_CONFIG | - RANDOM_DPI_DISPLAY_RESOLUTION); + intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port), + intel_dsi->video_frmt_cfg_bits | intel_dsi->video_mode_format | IP_TG_CONFIG | RANDOM_DPI_DISPLAY_RESOLUTION); } } @@ -1514,19 +1546,19 @@ static void intel_dsi_unprepare(struct intel_encoder *encoder) for_each_dsi_port(port, intel_dsi->ports) { /* Panel commands can be sent when clock is in LP11 */ - I915_WRITE(MIPI_DEVICE_READY(port), 0x0); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0); if (IS_GEN9_LP(dev_priv)) bxt_dsi_reset_clocks(encoder, port); else vlv_dsi_reset_clocks(encoder, port); - I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); + intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); - val = I915_READ(MIPI_DSI_FUNC_PRG(port)); + val = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)); val &= ~VID_MODE_FORMAT_MASK; - I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); + intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val); - I915_WRITE(MIPI_DEVICE_READY(port), 0x1); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1); } } @@ -1563,7 +1595,7 @@ static enum drm_panel_orientation vlv_dsi_get_hw_panel_orientation(struct intel_connector *connector) { struct drm_i915_private *dev_priv = to_i915(connector->base.dev); - struct intel_encoder *encoder = connector->encoder; + struct intel_encoder *encoder = intel_attached_encoder(connector); enum intel_display_power_domain power_domain; enum drm_panel_orientation orientation; struct intel_plane *plane; @@ -1583,7 +1615,7 @@ vlv_dsi_get_hw_panel_orientation(struct intel_connector *connector) if (!wakeref) return DRM_MODE_PANEL_ORIENTATION_UNKNOWN; - val = I915_READ(DSPCNTR(plane->i9xx_plane)); + val = intel_de_read(dev_priv, DSPCNTR(plane->i9xx_plane)); if (!(val & DISPLAY_PLANE_ENABLE)) orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN; @@ -1702,7 +1734,8 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul); if (prepare_cnt > PREPARE_CNT_MAX) { - DRM_DEBUG_KMS("prepare count too high %u\n", prepare_cnt); + drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n", + prepare_cnt); prepare_cnt = PREPARE_CNT_MAX; } @@ -1722,7 +1755,8 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) exit_zero_cnt += 1; if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) { - DRM_DEBUG_KMS("exit zero count too high %u\n", exit_zero_cnt); + drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n", + exit_zero_cnt); exit_zero_cnt = EXIT_ZERO_CNT_MAX; } @@ -1732,7 +1766,8 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) * ui_den, ui_num * mul); if (clk_zero_cnt > CLK_ZERO_CNT_MAX) { - DRM_DEBUG_KMS("clock zero count too high %u\n", clk_zero_cnt); + drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n", + clk_zero_cnt); clk_zero_cnt = CLK_ZERO_CNT_MAX; } @@ -1741,7 +1776,8 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul); if (trail_cnt > TRAIL_CNT_MAX) { - DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt); + drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n", + trail_cnt); trail_cnt = TRAIL_CNT_MAX; } @@ -1816,7 +1852,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) enum port port; enum pipe pipe; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); /* There is no detection method for MIPI so rely on VBT */ if (!intel_bios_is_dsi_present(dev_priv, &port)) @@ -1848,6 +1884,8 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) intel_encoder->compute_config = intel_dsi_compute_config; intel_encoder->pre_enable = intel_dsi_pre_enable; + if (IS_GEN9_LP(dev_priv)) + intel_encoder->enable = bxt_dsi_enable; intel_encoder->disable = intel_dsi_disable; intel_encoder->post_disable = intel_dsi_post_disable; intel_encoder->get_hw_state = intel_dsi_get_hw_state; @@ -1893,18 +1931,18 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) } if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { - DRM_DEBUG_KMS("no device found\n"); + drm_dbg_kms(&dev_priv->drm, "no device found\n"); goto err; } /* Use clock read-back from current hw-state for fastboot */ current_mode = intel_encoder_current_mode(intel_encoder); if (current_mode) { - DRM_DEBUG_KMS("Calculated pclk %d GOP %d\n", - intel_dsi->pclk, current_mode->clock); + drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n", + intel_dsi->pclk, current_mode->clock); if (intel_fuzzy_clock_check(intel_dsi->pclk, current_mode->clock)) { - DRM_DEBUG_KMS("Using GOP pclk\n"); + drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n"); intel_dsi->pclk = current_mode->clock; } @@ -1932,7 +1970,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) mutex_unlock(&dev->mode_config.mutex); if (!fixed_mode) { - DRM_DEBUG_KMS("no fixed mode\n"); + drm_dbg_kms(&dev_priv->drm, "no fixed mode\n"); goto err_cleanup_connector; } |