diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 18 |
1 files changed, 7 insertions, 11 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index 04cac0bb5900..729d3232f0ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -698,12 +698,11 @@ static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev) | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT - | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT - | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); + | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, - UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF, ret); + UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF, ret); } else { data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT @@ -714,10 +713,9 @@ static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev) | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT - | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT - | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); + | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); - SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF, ret); + SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF, ret); } /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS, @@ -754,8 +752,7 @@ static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev) | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT - | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT - | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); + | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); @@ -768,9 +765,8 @@ static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev) | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT - | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT - | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT); - SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF, ret); + | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT); + SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF, ret); } } |