summaryrefslogtreecommitdiffstats
path: root/drivers/edac
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/edac')
-rw-r--r--drivers/edac/Kconfig2
-rw-r--r--drivers/edac/cpc925_edac.c2
-rw-r--r--drivers/edac/edac_core.h8
-rw-r--r--drivers/edac/edac_device.c4
-rw-r--r--drivers/edac/edac_device_sysfs.c4
-rw-r--r--drivers/edac/edac_mc.c2
-rw-r--r--drivers/edac/edac_mc_sysfs.c2
-rw-r--r--drivers/edac/edac_pci_sysfs.c4
-rw-r--r--drivers/edac/i5000_edac.c2
-rw-r--r--drivers/edac/i5100_edac.c2
-rw-r--r--drivers/edac/i5400_edac.c4
-rw-r--r--drivers/edac/i7300_edac.c2
-rw-r--r--drivers/edac/i7core_edac.c2
-rw-r--r--drivers/edac/i82443bxgx_edac.c4
-rw-r--r--drivers/edac/mce_amd_inj.c2
-rw-r--r--drivers/edac/r82600_edac.c6
16 files changed, 26 insertions, 26 deletions
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index fac1a2002e67..af1a17d42bd7 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -45,7 +45,7 @@ config EDAC_DECODE_MCE
default y
---help---
Enable this option if you want to decode Machine Check Exceptions
- occuring on your machine in human-readable form.
+ occurring on your machine in human-readable form.
You should definitely say Y here in case you want to decode MCEs
which occur really early upon boot, before the module infrastructure
diff --git a/drivers/edac/cpc925_edac.c b/drivers/edac/cpc925_edac.c
index b9a781c47e3c..837ad8f85b48 100644
--- a/drivers/edac/cpc925_edac.c
+++ b/drivers/edac/cpc925_edac.c
@@ -817,7 +817,7 @@ static void cpc925_del_edac_devices(void)
}
}
-/* Convert current back-ground scrub rate into byte/sec bandwith */
+/* Convert current back-ground scrub rate into byte/sec bandwidth */
static int cpc925_get_sdram_scrub_rate(struct mem_ctl_info *mci)
{
struct cpc925_mc_pdata *pdata = mci->pvt_info;
diff --git a/drivers/edac/edac_core.h b/drivers/edac/edac_core.h
index 3d965347a673..eefa3501916b 100644
--- a/drivers/edac/edac_core.h
+++ b/drivers/edac/edac_core.h
@@ -164,7 +164,7 @@ enum mem_type {
/* chipset Error Detection and Correction capabilities and mode */
enum edac_type {
EDAC_UNKNOWN = 0, /* Unknown if ECC is available */
- EDAC_NONE, /* Doesnt support ECC */
+ EDAC_NONE, /* Doesn't support ECC */
EDAC_RESERVED, /* Reserved ECC type */
EDAC_PARITY, /* Detects parity errors */
EDAC_EC, /* Error Checking - no correction */
@@ -233,7 +233,7 @@ enum scrub_type {
* of these in parallel provides 64 bits which is common
* for a memory stick.
*
- * Memory Stick: A printed circuit board that agregates multiple
+ * Memory Stick: A printed circuit board that aggregates multiple
* memory devices in parallel. This is the atomic
* memory component that is purchaseable by Joe consumer
* and loaded into a memory socket.
@@ -385,7 +385,7 @@ struct mem_ctl_info {
/* Get the current sdram memory scrub rate from the internal
representation and converts it to the closest matching
- bandwith in bytes/sec.
+ bandwidth in bytes/sec.
*/
int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
@@ -823,7 +823,7 @@ extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
* There are a limited number of error logging registers that can
* be exausted. When all registers are exhausted and an additional
* error occurs then an error overflow register records that an
- * error occured and the type of error, but doesn't have any
+ * error occurred and the type of error, but doesn't have any
* further information. The ce/ue versions make for cleaner
* reporting logic and function interface - reduces conditional
* statement clutter and extra function arguments.
diff --git a/drivers/edac/edac_device.c b/drivers/edac/edac_device.c
index d5e13c94714f..a7408cf86f37 100644
--- a/drivers/edac/edac_device.c
+++ b/drivers/edac/edac_device.c
@@ -672,7 +672,7 @@ void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
block->counters.ce_count++;
}
- /* Propogate the count up the 'totals' tree */
+ /* Propagate the count up the 'totals' tree */
instance->counters.ce_count++;
edac_dev->counters.ce_count++;
@@ -718,7 +718,7 @@ void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
block->counters.ue_count++;
}
- /* Propogate the count up the 'totals' tree */
+ /* Propagate the count up the 'totals' tree */
instance->counters.ue_count++;
edac_dev->counters.ue_count++;
diff --git a/drivers/edac/edac_device_sysfs.c b/drivers/edac/edac_device_sysfs.c
index 400de071cabc..86649df00285 100644
--- a/drivers/edac/edac_device_sysfs.c
+++ b/drivers/edac/edac_device_sysfs.c
@@ -533,7 +533,7 @@ static int edac_device_create_block(struct edac_device_ctl_info *edac_dev,
memset(&block->kobj, 0, sizeof(struct kobject));
/* bump the main kobject's reference count for this controller
- * and this instance is dependant on the main
+ * and this instance is dependent on the main
*/
main_kobj = kobject_get(&edac_dev->kobj);
if (!main_kobj) {
@@ -635,7 +635,7 @@ static int edac_device_create_instance(struct edac_device_ctl_info *edac_dev,
instance->ctl = edac_dev;
/* bump the main kobject's reference count for this controller
- * and this instance is dependant on the main
+ * and this instance is dependent on the main
*/
main_kobj = kobject_get(&edac_dev->kobj);
if (!main_kobj) {
diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c
index a4e9db2d6524..1d8056049072 100644
--- a/drivers/edac/edac_mc.c
+++ b/drivers/edac/edac_mc.c
@@ -724,7 +724,7 @@ void edac_mc_handle_ce(struct mem_ctl_info *mci,
* Some MC's can remap memory so that it is still available
* at a different address when PCI devices map into memory.
* MC's that can't do this lose the memory where PCI devices
- * are mapped. This mapping is MC dependant and so we call
+ * are mapped. This mapping is MC dependent and so we call
* back into the MC driver for it to map the MC page to
* a physical (CPU) page which can then be mapped to a virtual
* page - which can then be scrubbed.
diff --git a/drivers/edac/edac_mc_sysfs.c b/drivers/edac/edac_mc_sysfs.c
index 73196f7b7229..26343fd46596 100644
--- a/drivers/edac/edac_mc_sysfs.c
+++ b/drivers/edac/edac_mc_sysfs.c
@@ -850,7 +850,7 @@ static void edac_remove_mci_instance_attributes(struct mem_ctl_info *mci,
/*
* loop if there are attributes and until we hit a NULL entry
- * Remove first all the atributes
+ * Remove first all the attributes
*/
while (sysfs_attrib) {
debugf4("%s() sysfs_attrib = %p\n",__func__, sysfs_attrib);
diff --git a/drivers/edac/edac_pci_sysfs.c b/drivers/edac/edac_pci_sysfs.c
index 023b01cb5175..495198ad059c 100644
--- a/drivers/edac/edac_pci_sysfs.c
+++ b/drivers/edac/edac_pci_sysfs.c
@@ -352,7 +352,7 @@ static int edac_pci_main_kobj_setup(void)
return 0;
/* First time, so create the main kobject and its
- * controls and atributes
+ * controls and attributes
*/
edac_class = edac_get_sysfs_class();
if (edac_class == NULL) {
@@ -551,7 +551,7 @@ static void edac_pci_dev_parity_clear(struct pci_dev *dev)
/*
* PCI Parity polling
*
- * Fucntion to retrieve the current parity status
+ * Function to retrieve the current parity status
* and decode it
*
*/
diff --git a/drivers/edac/i5000_edac.c b/drivers/edac/i5000_edac.c
index a5cefab8d65d..87f427c2ce5c 100644
--- a/drivers/edac/i5000_edac.c
+++ b/drivers/edac/i5000_edac.c
@@ -1372,7 +1372,7 @@ static int i5000_probe1(struct pci_dev *pdev, int dev_idx)
* actual number of slots/dimms per channel, we thus utilize the
* resource as specified by the chipset. Thus, we might have
* have more DIMMs per channel than actually on the mobo, but this
- * allows the driver to support upto the chipset max, without
+ * allows the driver to support up to the chipset max, without
* some fancy mobo determination.
*/
i5000_get_dimm_and_channel_counts(pdev, &num_dimms_per_channel,
diff --git a/drivers/edac/i5100_edac.c b/drivers/edac/i5100_edac.c
index 0448da0af75d..bcbdeeca48b8 100644
--- a/drivers/edac/i5100_edac.c
+++ b/drivers/edac/i5100_edac.c
@@ -11,7 +11,7 @@
*
* The intel 5100 has two independent channels. EDAC core currently
* can not reflect this configuration so instead the chip-select
- * rows for each respective channel are layed out one after another,
+ * rows for each respective channel are laid out one after another,
* the first half belonging to channel 0, the second half belonging
* to channel 1.
*/
diff --git a/drivers/edac/i5400_edac.c b/drivers/edac/i5400_edac.c
index 38a9be9e1c7c..80a465efbae8 100644
--- a/drivers/edac/i5400_edac.c
+++ b/drivers/edac/i5400_edac.c
@@ -648,7 +648,7 @@ static void i5400_process_nonfatal_error_info(struct mem_ctl_info *mci,
return;
}
- /* Miscelaneous errors */
+ /* Miscellaneous errors */
errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
branch = extract_fbdchan_indx(info->ferr_nf_fbd);
@@ -1240,7 +1240,7 @@ static int i5400_probe1(struct pci_dev *pdev, int dev_idx)
* actual number of slots/dimms per channel, we thus utilize the
* resource as specified by the chipset. Thus, we might have
* have more DIMMs per channel than actually on the mobo, but this
- * allows the driver to support upto the chipset max, without
+ * allows the driver to support up to the chipset max, without
* some fancy mobo determination.
*/
num_dimms_per_channel = MAX_DIMMS_PER_CHANNEL;
diff --git a/drivers/edac/i7300_edac.c b/drivers/edac/i7300_edac.c
index 76d1f576cdc8..363cc1602944 100644
--- a/drivers/edac/i7300_edac.c
+++ b/drivers/edac/i7300_edac.c
@@ -1065,7 +1065,7 @@ static int __devinit i7300_init_one(struct pci_dev *pdev,
* actual number of slots/dimms per channel, we thus utilize the
* resource as specified by the chipset. Thus, we might have
* have more DIMMs per channel than actually on the mobo, but this
- * allows the driver to support upto the chipset max, without
+ * allows the driver to support up to the chipset max, without
* some fancy mobo determination.
*/
num_dimms_per_channel = MAX_SLOTS;
diff --git a/drivers/edac/i7core_edac.c b/drivers/edac/i7core_edac.c
index 81154ab296b6..465cbc25149f 100644
--- a/drivers/edac/i7core_edac.c
+++ b/drivers/edac/i7core_edac.c
@@ -1772,7 +1772,7 @@ static void i7core_check_error(struct mem_ctl_info *mci)
/*
* MCE first step: Copy all mce errors into a temporary buffer
* We use a double buffering here, to reduce the risk of
- * loosing an error.
+ * losing an error.
*/
smp_rmb();
count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
diff --git a/drivers/edac/i82443bxgx_edac.c b/drivers/edac/i82443bxgx_edac.c
index 678405ab04e4..4329d39f902c 100644
--- a/drivers/edac/i82443bxgx_edac.c
+++ b/drivers/edac/i82443bxgx_edac.c
@@ -203,7 +203,7 @@ static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
row_high_limit = ((u32) drbar << 23);
/* find the DRAM Chip Select Base address and mask */
debugf1("MC%d: %s: %s() Row=%d, "
- "Boundry Address=%#0x, Last = %#0x\n",
+ "Boundary Address=%#0x, Last = %#0x\n",
mci->mc_idx, __FILE__, __func__, index, row_high_limit,
row_high_limit_last);
@@ -305,7 +305,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
i82443bxgx_init_csrows(mci, pdev, edac_mode, mtype);
/* Many BIOSes don't clear error flags on boot, so do this
- * here, or we get "phantom" errors occuring at module-load
+ * here, or we get "phantom" errors occurring at module-load
* time. */
pci_write_bits32(pdev, I82443BXGX_EAP,
(I82443BXGX_EAP_OFFSET_SBE |
diff --git a/drivers/edac/mce_amd_inj.c b/drivers/edac/mce_amd_inj.c
index 733a7e7a8d6f..a4987e03f59e 100644
--- a/drivers/edac/mce_amd_inj.c
+++ b/drivers/edac/mce_amd_inj.c
@@ -90,7 +90,7 @@ static ssize_t edac_inject_bank_store(struct kobject *kobj,
if (value > 5)
if (boot_cpu_data.x86 != 0x15 || value > 6) {
- printk(KERN_ERR "Non-existant MCE bank: %lu\n", value);
+ printk(KERN_ERR "Non-existent MCE bank: %lu\n", value);
return -EINVAL;
}
diff --git a/drivers/edac/r82600_edac.c b/drivers/edac/r82600_edac.c
index 6a822c631ef5..678513738c33 100644
--- a/drivers/edac/r82600_edac.c
+++ b/drivers/edac/r82600_edac.c
@@ -120,7 +120,7 @@
* write 0=NOP
*/
-#define R82600_DRBA 0x60 /* + 0x60..0x63 SDRAM Row Boundry Address
+#define R82600_DRBA 0x60 /* + 0x60..0x63 SDRAM Row Boundary Address
* Registers
*
* 7:0 Address lines 30:24 - upper limit of
@@ -217,7 +217,7 @@ static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
{
struct csrow_info *csrow;
int index;
- u8 drbar; /* SDRAM Row Boundry Address Register */
+ u8 drbar; /* SDRAM Row Boundary Address Register */
u32 row_high_limit, row_high_limit_last;
u32 reg_sdram, ecc_on, row_base;
@@ -236,7 +236,7 @@ static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
row_high_limit = ((u32) drbar << 24);
/* row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */
- debugf1("%s() Row=%d, Boundry Address=%#0x, Last = %#0x\n",
+ debugf1("%s() Row=%d, Boundary Address=%#0x, Last = %#0x\n",
__func__, index, row_high_limit, row_high_limit_last);
/* Empty row [p.57] */
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 22:49:46 +0000