diff options
Diffstat (limited to 'drivers/clk')
87 files changed, 5051 insertions, 584 deletions
diff --git a/drivers/clk/at91/at91rm9200.c b/drivers/clk/at91/at91rm9200.c index b174f727a8ef..16870943a13e 100644 --- a/drivers/clk/at91/at91rm9200.c +++ b/drivers/clk/at91/at91rm9200.c @@ -40,7 +40,7 @@ static const struct clk_pll_characteristics rm9200_pll_characteristics = { }; static const struct sck at91rm9200_systemck[] = { - { .n = "udpck", .p = "usbck", .id = 2 }, + { .n = "udpck", .p = "usbck", .id = 1 }, { .n = "uhpck", .p = "usbck", .id = 4 }, { .n = "pck0", .p = "prog0", .id = 8 }, { .n = "pck1", .p = "prog1", .id = 9 }, diff --git a/drivers/clk/clk-bulk.c b/drivers/clk/clk-bulk.c index e9e16425c739..826b3ff99433 100644 --- a/drivers/clk/clk-bulk.c +++ b/drivers/clk/clk-bulk.c @@ -96,9 +96,9 @@ static int __clk_bulk_get(struct device *dev, int num_clks, if (ret == -ENOENT && optional) continue; - if (ret != -EPROBE_DEFER) - dev_err(dev, "Failed to get clk '%s': %d\n", - clks[i].id, ret); + dev_err_probe(dev, ret, + "Failed to get clk '%s'\n", + clks[i].id); goto err; } } diff --git a/drivers/clk/clk-cdce925.c b/drivers/clk/clk-cdce925.c index ef9a2d44e40c..6350682f7e6d 100644 --- a/drivers/clk/clk-cdce925.c +++ b/drivers/clk/clk-cdce925.c @@ -603,28 +603,15 @@ of_clk_cdce925_get(struct of_phandle_args *clkspec, void *_data) return &data->clk[idx].hw; } -static void cdce925_regulator_disable(void *regulator) -{ - regulator_disable(regulator); -} - static int cdce925_regulator_enable(struct device *dev, const char *name) { - struct regulator *regulator; int err; - regulator = devm_regulator_get(dev, name); - if (IS_ERR(regulator)) - return PTR_ERR(regulator); - - err = regulator_enable(regulator); - if (err) { - dev_err(dev, "Failed to enable %s: %d\n", name, err); - return err; - } + err = devm_regulator_get_enable(dev, name); + if (err) + dev_err_probe(dev, err, "Failed to enable %s:\n", name); - return devm_add_action_or_reset(dev, cdce925_regulator_disable, - regulator); + return err; } /* The CDCE925 uses a funky way to read/write registers. Bulk mode is diff --git a/drivers/clk/clk-lmk04832.c b/drivers/clk/clk-lmk04832.c index f416f8bc2898..57485356de4c 100644 --- a/drivers/clk/clk-lmk04832.c +++ b/drivers/clk/clk-lmk04832.c @@ -12,12 +12,10 @@ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/clk-provider.h> -#include <linux/debugfs.h> #include <linux/device.h> #include <linux/gcd.h> #include <linux/gpio/consumer.h> #include <linux/module.h> -#include <linux/uaccess.h> #include <linux/regmap.h> #include <linux/spi/spi.h> @@ -177,14 +175,14 @@ enum lmk04832_device_types { }; /** - * lmk04832_device_info - Holds static device information that is specific to - * the chip revision + * struct lmk04832_device_info - Holds static device information that is + * specific to the chip revision * - * pid: Product Identifier - * maskrev: IC version identifier - * num_channels: Number of available output channels (clkout count) - * vco0_range: {min, max} of the VCO0 operating range (in MHz) - * vco1_range: {min, max} of the VCO1 operating range (in MHz) + * @pid: Product Identifier + * @maskrev: IC version identifier + * @num_channels: Number of available output channels (clkout count) + * @vco0_range: {min, max} of the VCO0 operating range (in MHz) + * @vco1_range: {min, max} of the VCO1 operating range (in MHz) */ struct lmk04832_device_info { u16 pid; @@ -282,7 +280,7 @@ static bool lmk04832_regmap_rd_regs(struct device *dev, unsigned int reg) default: return false; }; -}; +} static bool lmk04832_regmap_wr_regs(struct device *dev, unsigned int reg) { @@ -305,7 +303,7 @@ static bool lmk04832_regmap_wr_regs(struct device *dev, unsigned int reg) default: return false; }; -}; +} static const struct regmap_config regmap_config = { .name = "lmk04832", @@ -371,7 +369,7 @@ static unsigned long lmk04832_vco_recalc_rate(struct clk_hw *hw, unsigned long prate) { struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco); - unsigned int pll2_p[] = {8, 2, 2, 3, 4, 5, 6, 7}; + const unsigned int pll2_p[] = {8, 2, 2, 3, 4, 5, 6, 7}; unsigned int pll2_n, p, pll2_r; unsigned int pll2_misc; unsigned long vco_rate; @@ -403,7 +401,7 @@ static unsigned long lmk04832_vco_recalc_rate(struct clk_hw *hw, pll2_misc)) * pll2_n * pll2_p[p] / pll2_r; return vco_rate; -}; +} /** * lmk04832_check_vco_ranges - Check requested VCO frequency against VCO ranges @@ -414,7 +412,7 @@ static unsigned long lmk04832_vco_recalc_rate(struct clk_hw *hw, * The LMK04832 has 2 internal VCO, each with independent operating ranges. * Use the device_info structure to determine which VCO to use based on rate. * - * Returns VCO_MUX value or negative errno. + * Returns: VCO_MUX value or negative errno. */ static int lmk04832_check_vco_ranges(struct lmk04832 *lmk, unsigned long rate) { @@ -451,7 +449,7 @@ static int lmk04832_check_vco_ranges(struct lmk04832 *lmk, unsigned long rate) * * VCO = OSCin * 2 * PLL2_N * PLL2_P / PLL2_R * - * Returns vco rate or negative errno. + * Returns: vco rate or negative errno. */ static long lmk04832_calc_pll2_params(unsigned long prate, unsigned long rate, unsigned int *n, unsigned int *p, @@ -509,7 +507,7 @@ static long lmk04832_vco_round_rate(struct clk_hw *hw, unsigned long rate, return -EINVAL; return vco_rate; -}; +} static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) @@ -568,7 +566,7 @@ static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate, return regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_2, FIELD_GET(0x0000ff, n)); -}; +} static const struct clk_ops lmk04832_vco_ops = { .is_enabled = lmk04832_vco_is_enabled, @@ -633,7 +631,7 @@ static int lmk04832_register_vco(struct lmk04832 *lmk) static int lmk04832_clkout_set_ddly(struct lmk04832 *lmk, int id) { - int dclk_div_adj[] = {0, 0, -2, -2, 0, 3, -1, 0}; + const int dclk_div_adj[] = {0, 0, -2, -2, 0, 3, -1, 0}; unsigned int sclkx_y_ddly = 10; unsigned int dclkx_y_ddly; unsigned int dclkx_y_div; @@ -1063,7 +1061,7 @@ static unsigned long lmk04832_dclk_recalc_rate(struct clk_hw *hw, rate = DIV_ROUND_CLOSEST(prate, dclk_div); return rate; -}; +} static long lmk04832_dclk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) @@ -1085,7 +1083,7 @@ static long lmk04832_dclk_round_rate(struct clk_hw *hw, unsigned long rate, return -EINVAL; return dclk_rate; -}; +} static int lmk04832_dclk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) @@ -1147,7 +1145,7 @@ static int lmk04832_dclk_set_rate(struct clk_hw *hw, unsigned long rate, dev_err(lmk->dev, "SYNC sequence failed\n"); return ret; -}; +} static const struct clk_ops lmk04832_dclk_ops = { .is_enabled = lmk04832_dclk_is_enabled, @@ -1551,6 +1549,7 @@ static void lmk04832_remove(struct spi_device *spi) clk_disable_unprepare(lmk->oscin); of_clk_del_provider(spi->dev.of_node); } + static const struct spi_device_id lmk04832_id[] = { { "lmk04832", LMK04832 }, {} diff --git a/drivers/clk/clk-nomadik.c b/drivers/clk/clk-nomadik.c index 71fbe687fa7b..06245681dac7 100644 --- a/drivers/clk/clk-nomadik.c +++ b/drivers/clk/clk-nomadik.c @@ -138,7 +138,7 @@ out_put: } /** - * struct clk_pll1 - Nomadik PLL1 clock + * struct clk_pll - Nomadik PLL clock * @hw: corresponding clock hardware entry * @id: PLL instance: 1 or 2 */ diff --git a/drivers/clk/clk-renesas-pcie.c b/drivers/clk/clk-renesas-pcie.c index 4f5df1fc74b4..e6247141d0c0 100644 --- a/drivers/clk/clk-renesas-pcie.c +++ b/drivers/clk/clk-renesas-pcie.c @@ -90,13 +90,66 @@ static const struct regmap_access_table rs9_writeable_table = { .n_yes_ranges = ARRAY_SIZE(rs9_writeable_ranges), }; +static int rs9_regmap_i2c_write(void *context, + unsigned int reg, unsigned int val) +{ + struct i2c_client *i2c = context; + const u8 data[3] = { reg, 1, val }; + const int count = ARRAY_SIZE(data); + int ret; + + ret = i2c_master_send(i2c, data, count); + if (ret == count) + return 0; + else if (ret < 0) + return ret; + else + return -EIO; +} + +static int rs9_regmap_i2c_read(void *context, + unsigned int reg, unsigned int *val) +{ + struct i2c_client *i2c = context; + struct i2c_msg xfer[2]; + u8 txdata = reg; + u8 rxdata[2]; + int ret; + + xfer[0].addr = i2c->addr; + xfer[0].flags = 0; + xfer[0].len = 1; + xfer[0].buf = (void *)&txdata; + + xfer[1].addr = i2c->addr; + xfer[1].flags = I2C_M_RD; + xfer[1].len = 2; + xfer[1].buf = (void *)rxdata; + + ret = i2c_transfer(i2c->adapter, xfer, 2); + if (ret < 0) + return ret; + if (ret != 2) + return -EIO; + + /* + * Byte 0 is transfer length, which is always 1 due + * to BCP register programming to 1 in rs9_probe(), + * ignore it and use data from Byte 1. + */ + *val = rxdata[1]; + return 0; +} + static const struct regmap_config rs9_regmap_config = { .reg_bits = 8, .val_bits = 8, - .cache_type = REGCACHE_FLAT, - .max_register = 0x8, + .cache_type = REGCACHE_NONE, + .max_register = RS9_REG_BCP, .rd_table = &rs9_readable_table, .wr_table = &rs9_writeable_table, + .reg_write = rs9_regmap_i2c_write, + .reg_read = rs9_regmap_i2c_read, }; static int rs9_get_output_config(struct rs9_driver_data *rs9, int idx) @@ -242,11 +295,17 @@ static int rs9_probe(struct i2c_client *client) return ret; } - rs9->regmap = devm_regmap_init_i2c(client, &rs9_regmap_config); + rs9->regmap = devm_regmap_init(&client->dev, NULL, + client, &rs9_regmap_config); if (IS_ERR(rs9->regmap)) return dev_err_probe(&client->dev, PTR_ERR(rs9->regmap), "Failed to allocate register map\n"); + /* Always read back 1 Byte via I2C */ + ret = regmap_write(rs9->regmap, RS9_REG_BCP, 1); + if (ret < 0) + return ret; + /* Register clock */ for (i = 0; i < rs9->chip_info->num_clks; i++) { snprintf(name, 5, "DIF%d", i); diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c index 7ad2e6203bae..01e5a466897f 100644 --- a/drivers/clk/clk-stm32mp1.c +++ b/drivers/clk/clk-stm32mp1.c @@ -155,7 +155,7 @@ static const char * const eth_src[] = { "pll4_p", "pll3_q" }; -const struct clk_parent_data ethrx_src[] = { +static const struct clk_parent_data ethrx_src[] = { { .name = "ethck_k", .fw_name = "ETH_RX_CLK/ETH_REF_CLK" }, }; diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c index 88689415aff9..e9737969170e 100644 --- a/drivers/clk/clk-versaclock5.c +++ b/drivers/clk/clk-versaclock5.c @@ -20,7 +20,6 @@ #include <linux/module.h> #include <linux/of.h> #include <linux/of_platform.h> -#include <linux/rational.h> #include <linux/regmap.h> #include <linux/slab.h> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index c3c3f8c07258..57b83665e5c3 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -1459,10 +1459,14 @@ static void clk_core_init_rate_req(struct clk_core * const core, { struct clk_core *parent; - if (WARN_ON(!core || !req)) + if (WARN_ON(!req)) return; memset(req, 0, sizeof(*req)); + req->max_rate = ULONG_MAX; + + if (!core) + return; req->rate = rate; clk_core_get_boundaries(core, &req->min_rate, &req->max_rate); diff --git a/drivers/clk/imx/clk-imx6sll.c b/drivers/clk/imx/clk-imx6sll.c index 31d777f30039..1c9351649eab 100644 --- a/drivers/clk/imx/clk-imx6sll.c +++ b/drivers/clk/imx/clk-imx6sll.c @@ -91,12 +91,12 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node) hws[IMX6SLL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); - hws[IMX6SLL_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil"); - hws[IMX6SLL_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc"); + hws[IMX6SLL_CLK_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil"); + hws[IMX6SLL_CLK_OSC] = imx_get_clk_hw_by_name(ccm_node, "osc"); /* ipp_di clock is external input */ - hws[IMX6SLL_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0"); - hws[IMX6SLL_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1"); + hws[IMX6SLL_CLK_IPP_DI0] = imx_get_clk_hw_by_name(ccm_node, "ipp_di0"); + hws[IMX6SLL_CLK_IPP_DI1] = imx_get_clk_hw_by_name(ccm_node, "ipp_di1"); np = of_find_compatible_node(NULL, NULL, "fsl,imx6sll-anatop"); base = of_iomap(np, 0); diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c index 598f3cf4eba4..b378531240e6 100644 --- a/drivers/clk/imx/clk-imx6sx.c +++ b/drivers/clk/imx/clk-imx6sx.c @@ -132,16 +132,16 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) hws[IMX6SX_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); - hws[IMX6SX_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil"); - hws[IMX6SX_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc"); + hws[IMX6SX_CLK_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil"); + hws[IMX6SX_CLK_OSC] = imx_get_clk_hw_by_name(ccm_node, "osc"); /* ipp_di clock is external input */ - hws[IMX6SX_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0"); - hws[IMX6SX_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1"); + hws[IMX6SX_CLK_IPP_DI0] = imx_get_clk_hw_by_name(ccm_node, "ipp_di0"); + hws[IMX6SX_CLK_IPP_DI1] = imx_get_clk_hw_by_name(ccm_node, "ipp_di1"); /* Clock source from external clock via CLK1/2 PAD */ - hws[IMX6SX_CLK_ANACLK1] = imx_obtain_fixed_clk_hw(ccm_node, "anaclk1"); - hws[IMX6SX_CLK_ANACLK2] = imx_obtain_fixed_clk_hw(ccm_node, "anaclk2"); + hws[IMX6SX_CLK_ANACLK1] = imx_get_clk_hw_by_name(ccm_node, "anaclk1"); + hws[IMX6SX_CLK_ANACLK2] = imx_get_clk_hw_by_name(ccm_node, "anaclk2"); np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop"); base = of_iomap(np, 0); diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c index 520b100bff4b..67a7a77ca540 100644 --- a/drivers/clk/imx/clk-imx6ul.c +++ b/drivers/clk/imx/clk-imx6ul.c @@ -126,12 +126,12 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) hws[IMX6UL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); - hws[IMX6UL_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil"); - hws[IMX6UL_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc"); + hws[IMX6UL_CLK_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil"); + hws[IMX6UL_CLK_OSC] = imx_get_clk_hw_by_name(ccm_node, "osc"); /* ipp_di clock is external input */ - hws[IMX6UL_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0"); - hws[IMX6UL_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1"); + hws[IMX6UL_CLK_IPP_DI0] = imx_get_clk_hw_by_name(ccm_node, "ipp_di0"); + hws[IMX6UL_CLK_IPP_DI1] = imx_get_clk_hw_by_name(ccm_node, "ipp_di1"); np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-anatop"); base = of_iomap(np, 0); diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index cbf8131c63f7..d681b6c4b29a 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -391,8 +391,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) hws = clk_hw_data->hws; hws[IMX7D_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); - hws[IMX7D_OSC_24M_CLK] = imx_obtain_fixed_clk_hw(ccm_node, "osc"); - hws[IMX7D_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil"); + hws[IMX7D_OSC_24M_CLK] = imx_get_clk_hw_by_name(ccm_node, "osc"); + hws[IMX7D_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil"); np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-anatop"); base = of_iomap(np, 0); diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c index b6e45e77ee39..208a0ab80d5e 100644 --- a/drivers/clk/imx/clk-imx7ulp.c +++ b/drivers/clk/imx/clk-imx7ulp.c @@ -59,11 +59,11 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np) hws[IMX7ULP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); - hws[IMX7ULP_CLK_ROSC] = imx_obtain_fixed_clk_hw(np, "rosc"); - hws[IMX7ULP_CLK_SOSC] = imx_obtain_fixed_clk_hw(np, "sosc"); - hws[IMX7ULP_CLK_SIRC] = imx_obtain_fixed_clk_hw(np, "sirc"); - hws[IMX7ULP_CLK_FIRC] = imx_obtain_fixed_clk_hw(np, "firc"); - hws[IMX7ULP_CLK_UPLL] = imx_obtain_fixed_clk_hw(np, "upll"); + hws[IMX7ULP_CLK_ROSC] = imx_get_clk_hw_by_name(np, "rosc"); + hws[IMX7ULP_CLK_SOSC] = imx_get_clk_hw_by_name(np, "sosc"); + hws[IMX7ULP_CLK_SIRC] = imx_get_clk_hw_by_name(np, "sirc"); + hws[IMX7ULP_CLK_FIRC] = imx_get_clk_hw_by_name(np, "firc"); + hws[IMX7ULP_CLK_UPLL] = imx_get_clk_hw_by_name(np, "upll"); /* SCG1 */ base = of_iomap(np, 0); diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index b6d275855b36..cb44e8148e53 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -312,12 +312,12 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) hws = clk_hw_data->hws; hws[IMX8MM_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); - hws[IMX8MM_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m"); - hws[IMX8MM_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k"); - hws[IMX8MM_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1"); - hws[IMX8MM_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2"); - hws[IMX8MM_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3"); - hws[IMX8MM_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4"); + hws[IMX8MM_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m"); + hws[IMX8MM_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k"); + hws[IMX8MM_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1"); + hws[IMX8MM_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2"); + hws[IMX8MM_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3"); + hws[IMX8MM_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4"); np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop"); base = of_iomap(np, 0); diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index d37c45b676ab..af256ade554f 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -27,10 +27,10 @@ static u32 share_count_nand; static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", }; -static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", }; +static const char * const video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", }; static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; -static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", }; +static const char * const m7_alt_pll_bypass_sels[] = {"m7_alt_pll", "m7_alt_pll_ref_sel", }; static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; @@ -40,24 +40,24 @@ static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pl static const char * const imx8mn_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", }; -static const char * const imx8mn_m7_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", "vpu_pll_out", - "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", }; +static const char * const imx8mn_m7_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", "m7_alt_pll_out", + "sys_pll1_800m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", }; static const char * const imx8mn_gpu_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; static const char * const imx8mn_gpu_shader_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; static const char * const imx8mn_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "sys_pll1_100m",}; + "video_pll_out", "sys_pll1_100m",}; static const char * const imx8mn_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", - "video_pll1_out", "sys_pll3_out", }; + "video_pll_out", "sys_pll3_out", }; static const char * const imx8mn_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", @@ -77,23 +77,23 @@ static const char * const imx8mn_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", " static const char * const imx8mn_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; static const char * const imx8mn_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; static const char * const imx8mn_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; static const char * const imx8mn_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", - "audio_pll1_out", "video_pll1_out", }; + "audio_pll1_out", "video_pll_out", }; static const char * const imx8mn_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out", - "audio_pll1_out", "video_pll1_out", }; + "audio_pll1_out", "video_pll_out", }; static const char * const imx8mn_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out", @@ -103,49 +103,49 @@ static const char * const imx8mn_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char * const imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out", +static const char * const imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll_out", "audio_pll2_out", "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", }; static const char * const imx8mn_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", - "clk_ext3", "clk_ext4", }; + "video_pll_out", "sys_pll1_133m", "dummy", + "clk_ext2", "clk_ext3", }; static const char * const imx8mn_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "dummy", "clk_ext3", "clk_ext4", }; static const char * const imx8mn_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "dummy", "clk_ext2", "clk_ext3", }; static const char * const imx8mn_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "dummy", "clk_ext3", "clk_ext4", }; static const char * const imx8mn_sai7_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "dummy", "clk_ext3", "clk_ext4", }; static const char * const imx8mn_spdif1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "dummy", "clk_ext2", "clk_ext3", }; static const char * const imx8mn_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", - "video_pll1_out", "clk_ext4", }; + "video_pll_out", "clk_ext4", }; static const char * const imx8mn_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", "clk_ext3", - "clk_ext4", "video_pll1_out", }; + "clk_ext4", "video_pll_out", }; static const char * const imx8mn_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m", - "sys_pll2_200m", "sys_pll2_500m", "video_pll1_out", - "audio_pll2_out", }; + "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out", + "video_pll_out", "audio_pll2_out", }; static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out", "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out", - "sys_pll2_250m", "video_pll1_out", }; + "sys_pll2_250m", "video_pll_out", }; static const char * const imx8mn_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", @@ -160,19 +160,19 @@ static const char * const imx8mn_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "s "audio_pll2_out", "sys_pll1_100m", }; static const char * const imx8mn_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; static const char * const imx8mn_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; static const char * const imx8mn_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; static const char * const imx8mn_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; static const char * const imx8mn_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", @@ -213,63 +213,63 @@ static const char * const imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "s static const char * const imx8mn_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; static const char * const imx8mn_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; static const char * const imx8mn_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; static const char * const imx8mn_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; static const char * const imx8mn_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1", }; static const char * const imx8mn_gpt2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1", }; static const char * const imx8mn_gpt3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1", }; static const char * const imx8mn_gpt4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1", }; static const char * const imx8mn_gpt5_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1", }; static const char * const imx8mn_gpt6_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1", }; static const char * const imx8mn_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", - "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out", + "m7_alt_pll_out", "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }; -static const char * const imx8mn_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "vpu_pll_out", +static const char * const imx8mn_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "m7_alt_pll_out", "sys_pll3_out", "sys_pll2_200m", "sys_pll1_266m", "sys_pll2_500m", "sys_pll1_100m", }; static const char * const imx8mn_dsi_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", - "audio_pll2_out", "video_pll1_out", }; + "audio_pll2_out", "video_pll_out", }; static const char * const imx8mn_dsi_phy_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2", - "audio_pll2_out", "video_pll1_out", }; + "audio_pll2_out", "video_pll_out", }; static const char * const imx8mn_dsi_dbi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", - "audio_pll2_out", "video_pll1_out", }; + "audio_pll2_out", "video_pll_out", }; static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", @@ -277,15 +277,15 @@ static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "s static const char * const imx8mn_camera_pixel_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", - "audio_pll2_out", "video_pll1_out", }; + "audio_pll2_out", "video_pll_out", }; static const char * const imx8mn_csi1_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2", - "audio_pll2_out", "video_pll1_out", }; + "audio_pll2_out", "video_pll_out", }; static const char * const imx8mn_csi2_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2", - "audio_pll2_out", "video_pll1_out", }; + "audio_pll2_out", "video_pll_out", }; static const char * const imx8mn_csi2_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", @@ -306,9 +306,9 @@ static const char * const imx8mn_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "du "dummy", "sys_pll1_80m", }; static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "osc_32k", }; + "video_pll_out", "osc_32k", }; -static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out", +static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out", "dummy", "dummy", "gpu_pll_out", "dummy", "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; @@ -332,12 +332,12 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) hws = clk_hw_data->hws; hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); - hws[IMX8MN_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m"); - hws[IMX8MN_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k"); - hws[IMX8MN_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1"); - hws[IMX8MN_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2"); - hws[IMX8MN_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3"); - hws[IMX8MN_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4"); + hws[IMX8MN_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m"); + hws[IMX8MN_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k"); + hws[IMX8MN_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1"); + hws[IMX8MN_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2"); + hws[IMX8MN_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3"); + hws[IMX8MN_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4"); np = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop"); base = of_iomap(np, 0); @@ -349,19 +349,19 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_M7_ALT_PLL_REF_SEL] = imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll); hws[IMX8MN_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll); - hws[IMX8MN_VIDEO_PLL1] = imx_clk_hw_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll); + hws[IMX8MN_VIDEO_PLL] = imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", base + 0x28, &imx_1443x_pll); hws[IMX8MN_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll); hws[IMX8MN_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll); - hws[IMX8MN_VPU_PLL] = imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll); + hws[IMX8MN_M7_ALT_PLL] = imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_ref_sel", base + 0x74, &imx_1416x_pll); hws[IMX8MN_ARM_PLL] = imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll); hws[IMX8MN_SYS_PLL1] = imx_clk_hw_fixed("sys_pll1", 800000000); hws[IMX8MN_SYS_PLL2] = imx_clk_hw_fixed("sys_pll2", 1000000000); @@ -370,20 +370,20 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) /* PLL bypass out */ hws[IMX8MN_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT); hws[IMX8MN_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux_flags("video_pll1_bypass", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT); + hws[IMX8MN_VIDEO_PLL_BYPASS] = imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sels), CLK_SET_RATE_PARENT); hws[IMX8MN_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT); hws[IMX8MN_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_VPU_PLL_BYPASS] = imx_clk_hw_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT); + hws[IMX8MN_M7_ALT_PLL_BYPASS] = imx_clk_hw_mux_flags("m7_alt_pll_bypass", base + 0x74, 28, 1, m7_alt_pll_bypass_sels, ARRAY_SIZE(m7_alt_pll_bypass_sels), CLK_SET_RATE_PARENT); hws[IMX8MN_ARM_PLL_BYPASS] = imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT); hws[IMX8MN_SYS_PLL3_BYPASS] = imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT); /* PLL out gate */ hws[IMX8MN_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", base, 13); hws[IMX8MN_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13); - hws[IMX8MN_VIDEO_PLL1_OUT] = imx_clk_hw_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13); + hws[IMX8MN_VIDEO_PLL_OUT] = imx_clk_hw_gate("video_pll_out", "video_pll_bypass", base + 0x28, 13); hws[IMX8MN_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13); hws[IMX8MN_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11); - hws[IMX8MN_VPU_PLL_OUT] = imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11); + hws[IMX8MN_M7_ALT_PLL_OUT] = imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_pll_bypass", base + 0x74, 11); hws[IMX8MN_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11); hws[IMX8MN_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11); diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 652ae58c2735..a57d877d393d 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -17,6 +17,8 @@ static u32 share_count_nand; static u32 share_count_media; +static u32 share_count_usb; +static u32 share_count_audio; static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; @@ -436,12 +438,12 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws = clk_hw_data->hws; hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); - hws[IMX8MP_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m"); - hws[IMX8MP_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k"); - hws[IMX8MP_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1"); - hws[IMX8MP_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2"); - hws[IMX8MP_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3"); - hws[IMX8MP_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4"); + hws[IMX8MP_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m"); + hws[IMX8MP_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k"); + hws[IMX8MP_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1"); + hws[IMX8MP_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2"); + hws[IMX8MP_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3"); + hws[IMX8MP_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4"); hws[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", anatop_base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", anatop_base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); @@ -673,7 +675,8 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", ccm_base + 0x44a0, 0); hws[IMX8MP_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", ccm_base + 0x44b0, 0); hws[IMX8MP_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk", "uart4", ccm_base + 0x44c0, 0); - hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate4("usb_root_clk", "hsio_axi", ccm_base + 0x44d0, 0); + hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate2_shared2("usb_root_clk", "hsio_axi", ccm_base + 0x44d0, 0, &share_count_usb); + hws[IMX8MP_CLK_USB_SUSP] = imx_clk_hw_gate2_shared2("usb_suspend_clk", "osc_32k", ccm_base + 0x44d0, 0, &share_count_usb); hws[IMX8MP_CLK_USB_PHY_ROOT] = imx_clk_hw_gate4("usb_phy_root_clk", "usb_phy_ref", ccm_base + 0x44f0, 0); hws[IMX8MP_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk", "usdhc1", ccm_base + 0x4510, 0); hws[IMX8MP_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk", "usdhc2", ccm_base + 0x4520, 0); @@ -699,7 +702,16 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_CLK_HDMI_ROOT] = imx_clk_hw_gate4("hdmi_root_clk", "hdmi_axi", ccm_base + 0x45f0, 0); hws[IMX8MP_CLK_TSENSOR_ROOT] = imx_clk_hw_gate4("tsensor_root_clk", "ipg_root", ccm_base + 0x4620, 0); hws[IMX8MP_CLK_VPU_ROOT] = imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", ccm_base + 0x4630, 0); - hws[IMX8MP_CLK_AUDIO_ROOT] = imx_clk_hw_gate4("audio_root_clk", "audio_ahb", ccm_base + 0x4650, 0); + + hws[IMX8MP_CLK_AUDIO_AHB_ROOT] = imx_clk_hw_gate2_shared2("audio_ahb_root", "audio_ahb", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_AUDIO_AXI_ROOT] = imx_clk_hw_gate2_shared2("audio_axi_root", "audio_axi", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI1_ROOT] = imx_clk_hw_gate2_shared2("sai1_root", "sai1", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI2_ROOT] = imx_clk_hw_gate2_shared2("sai2_root", "sai2", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI3_ROOT] = imx_clk_hw_gate2_shared2("sai3_root", "sai3", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI5_ROOT] = imx_clk_hw_gate2_shared2("sai5_root", "sai5", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root", "sai6", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI7_ROOT] = imx_clk_hw_gate2_shared2("sai7_root", "sai7", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_PDM_ROOT] = imx_clk_hw_gate2_shared2("pdm_root", "pdm", ccm_base + 0x4650, 0, &share_count_audio); hws[IMX8MP_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core", hws[IMX8MP_CLK_A53_CORE]->clk, diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 882dcad4817d..2bcaec19a999 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -297,13 +297,13 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) hws = clk_hw_data->hws; hws[IMX8MQ_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); - hws[IMX8MQ_CLK_32K] = imx_obtain_fixed_clk_hw(np, "ckil"); - hws[IMX8MQ_CLK_25M] = imx_obtain_fixed_clk_hw(np, "osc_25m"); - hws[IMX8MQ_CLK_27M] = imx_obtain_fixed_clk_hw(np, "osc_27m"); - hws[IMX8MQ_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1"); - hws[IMX8MQ_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2"); - hws[IMX8MQ_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3"); - hws[IMX8MQ_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4"); + hws[IMX8MQ_CLK_32K] = imx_get_clk_hw_by_name(np, "ckil"); + hws[IMX8MQ_CLK_25M] = imx_get_clk_hw_by_name(np, "osc_25m"); + hws[IMX8MQ_CLK_27M] = imx_get_clk_hw_by_name(np, "osc_27m"); + hws[IMX8MQ_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1"); + hws[IMX8MQ_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2"); + hws[IMX8MQ_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3"); + hws[IMX8MQ_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4"); np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop"); base = of_iomap(np, 0); diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index 99cff1fd108b..e464d9e71fbc 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -64,13 +64,9 @@ static const struct imx93_clk_root { { IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, }, { IMX93_CLK_FLEXIO1, "flexio1_root", 0x0500, LOW_SPEED_IO_SEL, }, { IMX93_CLK_FLEXIO2, "flexio2_root", 0x0580, LOW_SPEED_IO_SEL, }, - { IMX93_CLK_LPIT1, "lpit1_root", 0x0600, LOW_SPEED_IO_SEL, }, - { IMX93_CLK_LPIT2, "lpit2_root", 0x0680, LOW_SPEED_IO_SEL, }, { IMX93_CLK_LPTMR1, "lptmr1_root", 0x0700, LOW_SPEED_IO_SEL, }, { IMX93_CLK_LPTMR2, "lptmr2_root", 0x0780, LOW_SPEED_IO_SEL, }, - { IMX93_CLK_TPM1, "tpm1_root", 0x0800, TPM_SEL, }, { IMX93_CLK_TPM2, "tpm2_root", 0x0880, TPM_SEL, }, - { IMX93_CLK_TPM3, "tpm3_root", 0x0900, TPM_SEL, }, { IMX93_CLK_TPM4, "tpm4_root", 0x0980, TPM_SEL, }, { IMX93_CLK_TPM5, "tpm5_root", 0x0a00, TPM_SEL, }, { IMX93_CLK_TPM6, "tpm6_root", 0x0a80, TPM_SEL, }, @@ -113,7 +109,11 @@ static const struct imx93_clk_root { { IMX93_CLK_CCM_CKO2, "ccm_cko2_root", 0x1d00, CKO2_SEL, }, { IMX93_CLK_CCM_CKO3, "ccm_cko3_root", 0x1d80, CKO1_SEL, }, { IMX93_CLK_CCM_CKO4, "ccm_cko4_root", 0x1e00, CKO2_SEL, }, - { IMX93_CLK_HSIO, "hsio_root", 0x1e80, LOW_SPEED_IO_SEL, }, + /* + * Critical because clk is used for handshake between HSIOMIX and NICMIX when + * NICMIX power down/on during system suspend/resume + */ + { IMX93_CLK_HSIO, "hsio_root", 0x1e80, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL}, { IMX93_CLK_HSIO_USB_TEST_60M, "hsio_usb_test_60m_root", 0x1f00, LOW_SPEED_IO_SEL, }, { IMX93_CLK_HSIO_ACSCAN_80M, "hsio_acscan_80m_root", 0x1f80, LOW_SPEED_IO_SEL, }, { IMX93_CLK_HSIO_ACSCAN_480M, "hsio_acscan_480m_root", 0x2000, MISC_SEL, }, @@ -170,20 +170,20 @@ static const struct imx93_clk_ccgr { { IMX93_CLK_MU2_B_GATE, "mu2_b", "bus_wakeup_root", 0x8500, 0, &share_count_mub }, { IMX93_CLK_EDMA1_GATE, "edma1", "m33_root", 0x8540, }, { IMX93_CLK_EDMA2_GATE, "edma2", "wakeup_axi_root", 0x8580, }, - { IMX93_CLK_FLEXSPI1_GATE, "flexspi", "flexspi_root", 0x8640, }, + { IMX93_CLK_FLEXSPI1_GATE, "flexspi1", "flexspi1_root", 0x8640, }, { IMX93_CLK_GPIO1_GATE, "gpio1", "m33_root", 0x8880, }, { IMX93_CLK_GPIO2_GATE, "gpio2", "bus_wakeup_root", 0x88c0, }, { IMX93_CLK_GPIO3_GATE, "gpio3", "bus_wakeup_root", 0x8900, }, { IMX93_CLK_GPIO4_GATE, "gpio4", "bus_wakeup_root", 0x8940, }, { IMX93_CLK_FLEXIO1_GATE, "flexio1", "flexio1_root", 0x8980, }, { IMX93_CLK_FLEXIO2_GATE, "flexio2", "flexio2_root", 0x89c0, }, - { IMX93_CLK_LPIT1_GATE, "lpit1", "lpit1_root", 0x8a00, }, - { IMX93_CLK_LPIT2_GATE, "lpit2", "lpit2_root", 0x8a40, }, + { IMX93_CLK_LPIT1_GATE, "lpit1", "bus_aon_root", 0x8a00, }, + { IMX93_CLK_LPIT2_GATE, "lpit2", "bus_wakeup_root", 0x8a40, }, { IMX93_CLK_LPTMR1_GATE, "lptmr1", "lptmr1_root", 0x8a80, }, { IMX93_CLK_LPTMR2_GATE, "lptmr2", "lptmr2_root", 0x8ac0, }, - { IMX93_CLK_TPM1_GATE, "tpm1", "tpm1_root", 0x8b00, }, + { IMX93_CLK_TPM1_GATE, "tpm1", "bus_aon_root", 0x8b00, }, { IMX93_CLK_TPM2_GATE, "tpm2", "tpm2_root", 0x8b40, }, - { IMX93_CLK_TPM3_GATE, "tpm3", "tpm3_root", 0x8b80, }, + { IMX93_CLK_TPM3_GATE, "tpm3", "bus_wakeup_root", 0x8b80, }, { IMX93_CLK_TPM4_GATE, "tpm4", "tpm4_root", 0x8bc0, }, { IMX93_CLK_TPM5_GATE, "tpm5", "tpm5_root", 0x8c00, }, { IMX93_CLK_TPM6_GATE, "tpm6", "tpm6_root", 0x8c40, }, @@ -240,9 +240,10 @@ static const struct imx93_clk_ccgr { { IMX93_CLK_AUD_XCVR_GATE, "aud_xcvr", "audio_xcvr_root", 0x9b80, }, { IMX93_CLK_SPDIF_GATE, "spdif", "spdif_root", 0x9c00, }, { IMX93_CLK_HSIO_32K_GATE, "hsio_32k", "osc_32k", 0x9dc0, }, - { IMX93_CLK_ENET1_GATE, "enet1", "enet_root", 0x9e00, }, + { IMX93_CLK_ENET1_GATE, "enet1", "wakeup_axi_root", 0x9e00, }, { IMX93_CLK_ENET_QOS_GATE, "enet_qos", "wakeup_axi_root", 0x9e40, }, - { IMX93_CLK_SYS_CNT_GATE, "sys_cnt", "osc_24m", 0x9e80, }, + /* Critical because clk accessed during CPU idle */ + { IMX93_CLK_SYS_CNT_GATE, "sys_cnt", "osc_24m", 0x9e80, CLK_IS_CRITICAL}, { IMX93_CLK_TSTMR1_GATE, "tstmr1", "bus_aon_root", 0x9ec0, }, { IMX93_CLK_TSTMR2_GATE, "tstmr2", "bus_wakeup_root", 0x9f00, }, { IMX93_CLK_TMC_GATE, "tmc", "osc_24m", 0x9f40, }, @@ -258,7 +259,7 @@ static int imx93_clocks_probe(struct platform_device *pdev) struct device_node *np = dev->of_node; const struct imx93_clk_root *root; const struct imx93_clk_ccgr *ccgr; - void __iomem *base = NULL; + void __iomem *base, *anatop_base; int i, ret; clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, @@ -270,9 +271,9 @@ static int imx93_clocks_probe(struct platform_device *pdev) clks = clk_hw_data->hws; clks[IMX93_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); - clks[IMX93_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m"); - clks[IMX93_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k"); - clks[IMX93_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1"); + clks[IMX93_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m"); + clks[IMX93_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k"); + clks[IMX93_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1"); clks[IMX93_CLK_SYS_PLL_PFD0] = imx_clk_hw_fixed("sys_pll_pfd0", 1000000000); clks[IMX93_CLK_SYS_PLL_PFD0_DIV2] = imx_clk_hw_fixed_factor("sys_pll_pfd0_div2", @@ -285,20 +286,22 @@ static int imx93_clocks_probe(struct platform_device *pdev) "sys_pll_pfd2", 1, 2); np = of_find_compatible_node(NULL, NULL, "fsl,imx93-anatop"); - base = of_iomap(np, 0); + anatop_base = of_iomap(np, 0); of_node_put(np); - if (WARN_ON(!base)) + if (WARN_ON(!anatop_base)) return -ENOMEM; - clks[IMX93_CLK_AUDIO_PLL] = imx_clk_fracn_gppll("audio_pll", "osc_24m", base + 0x1200, + clks[IMX93_CLK_AUDIO_PLL] = imx_clk_fracn_gppll("audio_pll", "osc_24m", anatop_base + 0x1200, &imx_fracn_gppll); - clks[IMX93_CLK_VIDEO_PLL] = imx_clk_fracn_gppll("video_pll", "osc_24m", base + 0x1400, + clks[IMX93_CLK_VIDEO_PLL] = imx_clk_fracn_gppll("video_pll", "osc_24m", anatop_base + 0x1400, &imx_fracn_gppll); np = dev->of_node; base = devm_platform_ioremap_resource(pdev, 0); - if (WARN_ON(IS_ERR(base))) + if (WARN_ON(IS_ERR(base))) { + iounmap(anatop_base); return PTR_ERR(base); + } for (i = 0; i < ARRAY_SIZE(root_array); i++) { root = &root_array[i]; @@ -327,6 +330,7 @@ static int imx93_clocks_probe(struct platform_device *pdev) unregister_hws: imx_unregister_hw_clocks(clks, IMX93_CLK_END); + iounmap(anatop_base); return ret; } diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c index 9539d35588ee..e972abd299a8 100644 --- a/drivers/clk/imx/clk-imxrt1050.c +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -50,7 +50,7 @@ static int imxrt1050_clocks_probe(struct platform_device *pdev) clk_hw_data->num = IMXRT1050_CLK_END; hws = clk_hw_data->hws; - hws[IMXRT1050_CLK_OSC] = imx_obtain_fixed_clk_hw(np, "osc"); + hws[IMXRT1050_CLK_OSC] = imx_get_clk_hw_by_name(np, "osc"); anp = of_find_compatible_node(NULL, NULL, "fsl,imxrt-anatop"); pll_base = of_iomap(anp, 0); @@ -140,7 +140,8 @@ static int imxrt1050_clocks_probe(struct platform_device *pdev) hws[IMXRT1050_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1", "usdhc1_podf", ccm_base + 0x80, 2); hws[IMXRT1050_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf", ccm_base + 0x80, 4); hws[IMXRT1050_CLK_LPUART1] = imx_clk_hw_gate2("lpuart1", "lpuart_podf", ccm_base + 0x7c, 24); - hws[IMXRT1050_CLK_LCDIF_APB] = imx_clk_hw_gate2("lcdif", "lcdif_podf", ccm_base + 0x74, 10); + hws[IMXRT1050_CLK_LCDIF_APB] = imx_clk_hw_gate2("lcdif", "lcdif_podf", ccm_base + 0x70, 28); + hws[IMXRT1050_CLK_LCDIF_PIX] = imx_clk_hw_gate2("lcdif_pix", "lcdif", ccm_base + 0x74, 10); hws[IMXRT1050_CLK_DMA] = imx_clk_hw_gate("dma", "ipg", ccm_base + 0x7C, 6); hws[IMXRT1050_CLK_DMA_MUX] = imx_clk_hw_gate("dmamux0", "ipg", ccm_base + 0x7C, 7); imx_check_clk_hws(hws, IMXRT1050_CLK_END); diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 1d0f79e9c346..828336873a98 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -54,7 +54,9 @@ static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = { PLL_1416X_RATE(800000000U, 200, 3, 1), PLL_1416X_RATE(750000000U, 250, 2, 2), PLL_1416X_RATE(700000000U, 350, 3, 2), + PLL_1416X_RATE(640000000U, 320, 3, 2), PLL_1416X_RATE(600000000U, 300, 3, 2), + PLL_1416X_RATE(320000000U, 160, 3, 2), }; static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = { diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c index 5582f18dd632..b636cc099d96 100644 --- a/drivers/clk/imx/clk.c +++ b/drivers/clk/imx/clk.c @@ -110,8 +110,7 @@ struct clk_hw *imx_obtain_fixed_clock_hw( return __clk_get_hw(clk); } -struct clk_hw * imx_obtain_fixed_clk_hw(struct device_node *np, - const char *name) +struct clk_hw *imx_get_clk_hw_by_name(struct device_node *np, const char *name) { struct clk *clk; @@ -121,7 +120,7 @@ struct clk_hw * imx_obtain_fixed_clk_hw(struct device_node *np, return __clk_get_hw(clk); } -EXPORT_SYMBOL_GPL(imx_obtain_fixed_clk_hw); +EXPORT_SYMBOL_GPL(imx_get_clk_hw_by_name); /* * This fixups the register CCM_CSCMR1 write value. diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index dd49f90110e8..689b3ad927c0 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -288,8 +288,7 @@ struct clk * imx_obtain_fixed_clock( struct clk_hw *imx_obtain_fixed_clock_hw( const char *name, unsigned long rate); -struct clk_hw *imx_obtain_fixed_clk_hw(struct device_node *np, - const char *name); +struct clk_hw *imx_get_clk_hw_by_name(struct device_node *np, const char *name); struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent, void __iomem *reg, u8 shift, u32 exclusive_mask); diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig index 898f1bc478c9..f80ac4f2992b 100644 --- a/drivers/clk/ingenic/Kconfig +++ b/drivers/clk/ingenic/Kconfig @@ -15,6 +15,16 @@ config INGENIC_CGU_JZ4740 If building for a JZ4740 SoC, you want to say Y here. +config INGENIC_CGU_JZ4755 + bool "Ingenic JZ4755 CGU driver" + default MACH_JZ4755 + select INGENIC_CGU_COMMON + help + Support the clocks provided by the CGU hardware on Ingenic JZ4755 + and compatible SoCs. + + If building for a JZ4755 SoC, you want to say Y here. + config INGENIC_CGU_JZ4725B bool "Ingenic JZ4725B CGU driver" default MACH_JZ4725B diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile index 9edfaf4610b9..81d8e23c2636 100644 --- a/drivers/clk/ingenic/Makefile +++ b/drivers/clk/ingenic/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_INGENIC_CGU_COMMON) += cgu.o pm.o obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o +obj-$(CONFIG_INGENIC_CGU_JZ4755) += jz4755-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4760) += jz4760-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index 861c50d6cb24..1f7ba30f5a1b 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -83,7 +83,7 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); struct ingenic_cgu *cgu = ingenic_clk->cgu; const struct ingenic_cgu_pll_info *pll_info; - unsigned m, n, od_enc, od; + unsigned m, n, od, od_enc = 0; bool bypass; u32 ctl; @@ -96,8 +96,11 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) m += pll_info->m_offset; n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0); n += pll_info->n_offset; - od_enc = ctl >> pll_info->od_shift; - od_enc &= GENMASK(pll_info->od_bits - 1, 0); + + if (pll_info->od_bits > 0) { + od_enc = ctl >> pll_info->od_shift; + od_enc &= GENMASK(pll_info->od_bits - 1, 0); + } if (pll_info->bypass_bit >= 0) { ctl = readl(cgu->base + pll_info->bypass_reg); @@ -108,11 +111,15 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) return parent_rate; } - for (od = 0; od < pll_info->od_max; od++) { + for (od = 0; od < pll_info->od_max; od++) if (pll_info->od_encoding[od] == od_enc) break; - } - BUG_ON(od == pll_info->od_max); + + /* if od_max = 0, od_bits should be 0 and od is fixed to 1. */ + if (pll_info->od_max == 0) + BUG_ON(pll_info->od_bits != 0); + else + BUG_ON(od == pll_info->od_max); od++; return div_u64((u64)parent_rate * m * pll_info->rate_multiplier, @@ -182,6 +189,9 @@ static inline int ingenic_pll_check_stable(struct ingenic_cgu *cgu, { u32 ctl; + if (pll_info->stable_bit < 0) + return 0; + return readl_poll_timeout(cgu->base + pll_info->reg, ctl, ctl & BIT(pll_info->stable_bit), 0, 100 * USEC_PER_MSEC); @@ -215,13 +225,18 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate, ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift); ctl |= (n - pll_info->n_offset) << pll_info->n_shift; - ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift); - ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift; + if (pll_info->od_bits > 0) { + ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift); + ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift; + } writel(ctl, cgu->base + pll_info->reg); + if (pll_info->set_rate_hook) + pll_info->set_rate_hook(pll_info, rate, parent_rate); + /* If the PLL is enabled, verify that it's stable */ - if (ctl & BIT(pll_info->enable_bit)) + if (pll_info->enable_bit >= 0 && (ctl & BIT(pll_info->enable_bit))) ret = ingenic_pll_check_stable(cgu, pll_info); spin_unlock_irqrestore(&cgu->lock, flags); @@ -239,6 +254,9 @@ static int ingenic_pll_enable(struct clk_hw *hw) int ret; u32 ctl; + if (pll_info->enable_bit < 0) + return 0; + spin_lock_irqsave(&cgu->lock, flags); if (pll_info->bypass_bit >= 0) { ctl = readl(cgu->base + pll_info->bypass_reg); @@ -269,6 +287,9 @@ static void ingenic_pll_disable(struct clk_hw *hw) unsigned long flags; u32 ctl; + if (pll_info->enable_bit < 0) + return; + spin_lock_irqsave(&cgu->lock, flags); ctl = readl(cgu->base + pll_info->reg); @@ -286,6 +307,9 @@ static int ingenic_pll_is_enabled(struct clk_hw *hw) const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; u32 ctl; + if (pll_info->enable_bit < 0) + return true; + ctl = readl(cgu->base + pll_info->reg); return !!(ctl & BIT(pll_info->enable_bit)); diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index 147b7df0d657..99da9bd86e63 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -33,7 +33,8 @@ * @od_shift: the number of bits to shift the post-VCO divider value by (ie. * the index of the lowest bit of the post-VCO divider value in * the PLL's control register) - * @od_bits: the size of the post-VCO divider field in bits + * @od_bits: the size of the post-VCO divider field in bits, or 0 if no + * OD field exists (then the OD is fixed to 1) * @od_max: the maximum post-VCO divider value * @od_encoding: a pointer to an array mapping post-VCO divider values to * their encoded values in the PLL control register, or -1 for @@ -41,8 +42,12 @@ * @bypass_reg: the offset of the bypass control register within the CGU * @bypass_bit: the index of the bypass bit in the PLL control register, or * -1 if there is no bypass bit - * @enable_bit: the index of the enable bit in the PLL control register - * @stable_bit: the index of the stable bit in the PLL control register + * @enable_bit: the index of the enable bit in the PLL control register, or + * -1 if there is no enable bit (ie, the PLL is always on) + * @stable_bit: the index of the stable bit in the PLL control register, or + * -1 if there is no stable bit + * @set_rate_hook: hook called immediately after updating the CGU register, + * before releasing the spinlock */ struct ingenic_cgu_pll_info { unsigned reg; @@ -53,11 +58,13 @@ struct ingenic_cgu_pll_info { u8 od_shift, od_bits, od_max; unsigned bypass_reg; s8 bypass_bit; - u8 enable_bit; - u8 stable_bit; + s8 enable_bit; + s8 stable_bit; void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info, unsigned long rate, unsigned long parent_rate, unsigned int *m, unsigned int *n, unsigned int *od); + void (*set_rate_hook)(const struct ingenic_cgu_pll_info *pll_info, + unsigned long rate, unsigned long parent_rate); }; /** diff --git a/drivers/clk/ingenic/jz4755-cgu.c b/drivers/clk/ingenic/jz4755-cgu.c new file mode 100644 index 000000000000..f2c2d848dab7 --- /dev/null +++ b/drivers/clk/ingenic/jz4755-cgu.c @@ -0,0 +1,346 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Ingenic JZ4755 SoC CGU driver + * Heavily based on JZ4725b CGU driver + * + * Copyright (C) 2022 Siarhei Volkau + * Author: Siarhei Volkau <lis8215@gmail.com> + */ + +#include <linux/clk-provider.h> +#include <linux/delay.h> +#include <linux/of.h> + +#include <dt-bindings/clock/ingenic,jz4755-cgu.h> + +#include "cgu.h" +#include "pm.h" + +/* CGU register offsets */ +#define CGU_REG_CPCCR 0x00 +#define CGU_REG_CPPCR 0x10 +#define CGU_REG_CLKGR 0x20 +#define CGU_REG_OPCR 0x24 +#define CGU_REG_I2SCDR 0x60 +#define CGU_REG_LPCDR 0x64 +#define CGU_REG_MSCCDR 0x68 +#define CGU_REG_SSICDR 0x74 +#define CGU_REG_CIMCDR 0x7C + +static struct ingenic_cgu *cgu; + +static const s8 pll_od_encoding[4] = { + 0x0, 0x1, -1, 0x3, +}; + +static const u8 jz4755_cgu_cpccr_div_table[] = { + 1, 2, 3, 4, 6, 8, +}; + +static const u8 jz4755_cgu_pll_half_div_table[] = { + 2, 1, +}; + +static const struct ingenic_cgu_clk_info jz4755_cgu_clocks[] = { + + /* External clocks */ + + [JZ4755_CLK_EXT] = { "ext", CGU_CLK_EXT }, + [JZ4755_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT }, + + [JZ4755_CLK_PLL] = { + "pll", CGU_CLK_PLL, + .parents = { JZ4755_CLK_EXT, }, + .pll = { + .reg = CGU_REG_CPPCR, + .rate_multiplier = 1, + .m_shift = 23, + .m_bits = 9, + .m_offset = 2, + .n_shift = 18, + .n_bits = 5, + .n_offset = 2, + .od_shift = 16, + .od_bits = 2, + .od_max = 4, + .od_encoding = pll_od_encoding, + .stable_bit = 10, + .bypass_reg = CGU_REG_CPPCR, + .bypass_bit = 9, + .enable_bit = 8, + }, + }, + + /* Muxes & dividers */ + + [JZ4755_CLK_PLL_HALF] = { + "pll half", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, }, + .div = { + CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0, + jz4755_cgu_pll_half_div_table, + }, + }, + + [JZ4755_CLK_EXT_HALF] = { + "ext half", CGU_CLK_DIV, + .parents = { JZ4755_CLK_EXT, }, + .div = { + CGU_REG_CPCCR, 30, 1, 1, -1, -1, -1, 0, + NULL, + }, + }, + + [JZ4755_CLK_CCLK] = { + "cclk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, }, + .div = { + CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_H0CLK] = { + "hclk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, }, + .div = { + CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_PCLK] = { + "pclk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, }, + .div = { + CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_MCLK] = { + "mclk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, }, + .div = { + CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_H1CLK] = { + "h1clk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, }, + .div = { + CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_UDC] = { + "udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, }, + .mux = { CGU_REG_CPCCR, 29, 1 }, + .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 10 }, + }, + + [JZ4755_CLK_LCD] = { + "lcd", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4755_CLK_PLL_HALF, }, + .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 9 }, + }, + + [JZ4755_CLK_MMC] = { + "mmc", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL_HALF, }, + .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 }, + }, + + [JZ4755_CLK_I2S] = { + "i2s", CGU_CLK_MUX | CGU_CLK_DIV, + .parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, }, + .mux = { CGU_REG_CPCCR, 31, 1 }, + .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 }, + }, + + [JZ4755_CLK_SPI] = { + "spi", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4755_CLK_PLL_HALF, }, + .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 4 }, + }, + + [JZ4755_CLK_TVE] = { + "tve", CGU_CLK_MUX | CGU_CLK_GATE, + .parents = { JZ4755_CLK_LCD, JZ4755_CLK_EXT, }, + .mux = { CGU_REG_LPCDR, 31, 1 }, + .gate = { CGU_REG_CLKGR, 18 }, + }, + + [JZ4755_CLK_RTC] = { + "rtc", CGU_CLK_MUX | CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT512, JZ4755_CLK_OSC32K, }, + .mux = { CGU_REG_OPCR, 2, 1}, + .gate = { CGU_REG_CLKGR, 2 }, + }, + + [JZ4755_CLK_CIM] = { + "cim", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4755_CLK_PLL_HALF, }, + .div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 8 }, + }, + + /* Gate-only clocks */ + + [JZ4755_CLK_UART0] = { + "uart0", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, }, + .gate = { CGU_REG_CLKGR, 0 }, + }, + + [JZ4755_CLK_UART1] = { + "uart1", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, }, + .gate = { CGU_REG_CLKGR, 14 }, + }, + + [JZ4755_CLK_UART2] = { + "uart2", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, }, + .gate = { CGU_REG_CLKGR, 15 }, + }, + + [JZ4755_CLK_ADC] = { + "adc", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, }, + .gate = { CGU_REG_CLKGR, 7 }, + }, + + [JZ4755_CLK_AIC] = { + "aic", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, }, + .gate = { CGU_REG_CLKGR, 5 }, + }, + + [JZ4755_CLK_I2C] = { + "i2c", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, }, + .gate = { CGU_REG_CLKGR, 3 }, + }, + + [JZ4755_CLK_BCH] = { + "bch", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, }, + .gate = { CGU_REG_CLKGR, 11 }, + }, + + [JZ4755_CLK_TCU] = { + "tcu", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT, }, + .gate = { CGU_REG_CLKGR, 1 }, + }, + + [JZ4755_CLK_DMA] = { + "dma", CGU_CLK_GATE, + .parents = { JZ4755_CLK_PCLK, }, + .gate = { CGU_REG_CLKGR, 12 }, + }, + + [JZ4755_CLK_MMC0] = { + "mmc0", CGU_CLK_GATE, + .parents = { JZ4755_CLK_MMC, }, + .gate = { CGU_REG_CLKGR, 6 }, + }, + + [JZ4755_CLK_MMC1] = { + "mmc1", CGU_CLK_GATE, + .parents = { JZ4755_CLK_MMC, }, + .gate = { CGU_REG_CLKGR, 16 }, + }, + + [JZ4755_CLK_AUX_CPU] = { + "aux_cpu", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, }, + .gate = { CGU_REG_CLKGR, 24 }, + }, + + [JZ4755_CLK_AHB1] = { + "ahb1", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, }, + .gate = { CGU_REG_CLKGR, 23 }, + }, + + [JZ4755_CLK_IDCT] = { + "idct", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, }, + .gate = { CGU_REG_CLKGR, 22 }, + }, + + [JZ4755_CLK_DB] = { + "db", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, }, + .gate = { CGU_REG_CLKGR, 21 }, + }, + + [JZ4755_CLK_ME] = { + "me", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, }, + .gate = { CGU_REG_CLKGR, 20 }, + }, + + [JZ4755_CLK_MC] = { + "mc", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, }, + .gate = { CGU_REG_CLKGR, 19 }, + }, + + [JZ4755_CLK_TSSI] = { + "tssi", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF/* not sure */, }, + .gate = { CGU_REG_CLKGR, 17 }, + }, + + [JZ4755_CLK_IPU] = { + "ipu", CGU_CLK_GATE, + .parents = { JZ4755_CLK_PLL_HALF/* not sure */, }, + .gate = { CGU_REG_CLKGR, 13 }, + }, + + [JZ4755_CLK_EXT512] = { + "ext/512", CGU_CLK_FIXDIV, + .parents = { JZ4755_CLK_EXT, }, + + .fixdiv = { 512 }, + }, + + [JZ4755_CLK_UDC_PHY] = { + "udc_phy", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, }, + .gate = { CGU_REG_OPCR, 6, true }, + }, +}; + +static void __init jz4755_cgu_init(struct device_node *np) +{ + int retval; + + cgu = ingenic_cgu_new(jz4755_cgu_clocks, + ARRAY_SIZE(jz4755_cgu_clocks), np); + if (!cgu) { + pr_err("%s: failed to initialise CGU\n", __func__); + return; + } + + retval = ingenic_cgu_register_clocks(cgu); + if (retval) + pr_err("%s: failed to register CGU Clocks\n", __func__); + + ingenic_cgu_register_syscore_ops(cgu); +} +/* + * CGU has some children devices, this is useful for probing children devices + * in the case where the device node is compatible with "simple-mfd". + */ +CLK_OF_DECLARE_DRIVER(jz4755_cgu, "ingenic,jz4755-cgu", jz4755_cgu_init); diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c index b2ce3fb83f54..feb03eed4fe8 100644 --- a/drivers/clk/ingenic/x1000-cgu.c +++ b/drivers/clk/ingenic/x1000-cgu.c @@ -8,6 +8,7 @@ #include <linux/delay.h> #include <linux/io.h> #include <linux/of.h> +#include <linux/rational.h> #include <dt-bindings/clock/ingenic,x1000-cgu.h> @@ -168,6 +169,38 @@ static const struct clk_ops x1000_otg_phy_ops = { .is_enabled = x1000_usb_phy_is_enabled, }; +static void +x1000_i2spll_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info, + unsigned long rate, unsigned long parent_rate, + unsigned int *pm, unsigned int *pn, unsigned int *pod) +{ + const unsigned long m_max = GENMASK(pll_info->m_bits - 1, 0); + const unsigned long n_max = GENMASK(pll_info->n_bits - 1, 0); + unsigned long m, n; + + rational_best_approximation(rate, parent_rate, m_max, n_max, &m, &n); + + /* n should not be less than 2*m */ + if (n < 2 * m) + n = 2 * m; + + *pm = m; + *pn = n; + *pod = 1; +} + +static void +x1000_i2spll_set_rate_hook(const struct ingenic_cgu_pll_info *pll_info, + unsigned long rate, unsigned long parent_rate) +{ + /* + * Writing 0 causes I2SCDR1.I2SDIV_D to be automatically recalculated + * based on the current value of I2SCDR.I2SDIV_N, which is needed for + * the divider to function correctly. + */ + writel(0, cgu->base + CGU_REG_I2SCDR1); +} + static const s8 pll_od_encoding[8] = { 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3, }; @@ -183,7 +216,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_APLL] = { "apll", CGU_CLK_PLL, - .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, + .parents = { X1000_CLK_EXCLK }, .pll = { .reg = CGU_REG_APLL, .rate_multiplier = 1, @@ -206,7 +239,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_MPLL] = { "mpll", CGU_CLK_PLL, - .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, + .parents = { X1000_CLK_EXCLK }, .pll = { .reg = CGU_REG_MPLL, .rate_multiplier = 1, @@ -256,7 +289,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { * system; mark it critical. */ .flags = CLK_IS_CRITICAL, - .parents = { X1000_CLK_CPUMUX, -1, -1, -1 }, + .parents = { X1000_CLK_CPUMUX }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 }, .gate = { CGU_REG_CLKGR, 30 }, }, @@ -268,7 +301,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { * disabling it or any parent clocks will hang the system. */ .flags = CLK_IS_CRITICAL, - .parents = { X1000_CLK_CPUMUX, -1, -1, -1 }, + .parents = { X1000_CLK_CPUMUX }, .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 }, }, @@ -287,13 +320,13 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_AHB2] = { "ahb2", CGU_CLK_DIV, - .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 }, + .parents = { X1000_CLK_AHB2PMUX }, .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 }, }, [X1000_CLK_PCLK] = { "pclk", CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 }, + .parents = { X1000_CLK_AHB2PMUX }, .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 }, .gate = { CGU_REG_CLKGR, 28 }, }, @@ -319,6 +352,37 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { .gate = { CGU_REG_CLKGR, 25 }, }, + [X1000_CLK_I2SPLLMUX] = { + "i2s_pll_mux", CGU_CLK_MUX, + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL }, + .mux = { CGU_REG_I2SCDR, 31, 1 }, + }, + + [X1000_CLK_I2SPLL] = { + "i2s_pll", CGU_CLK_PLL, + .parents = { X1000_CLK_I2SPLLMUX }, + .pll = { + .reg = CGU_REG_I2SCDR, + .rate_multiplier = 1, + .m_shift = 13, + .m_bits = 9, + .n_shift = 0, + .n_bits = 13, + .calc_m_n_od = x1000_i2spll_calc_m_n_od, + .set_rate_hook = x1000_i2spll_set_rate_hook, + }, + }, + + [X1000_CLK_I2S] = { + "i2s", CGU_CLK_MUX, + .parents = { X1000_CLK_EXCLK, -1, -1, X1000_CLK_I2SPLL }, + /* + * NOTE: the mux is at bit 30; bit 29 enables the M/N divider. + * Therefore, the divider is disabled when EXCLK is selected. + */ + .mux = { CGU_REG_I2SCDR, 29, 2 }, + }, + [X1000_CLK_LCD] = { "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL }, @@ -329,13 +393,13 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_MSCMUX] = { "msc_mux", CGU_CLK_MUX, - .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL}, + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL }, .mux = { CGU_REG_MSC0CDR, 31, 1 }, }, [X1000_CLK_MSC0] = { "msc0", CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { X1000_CLK_MSCMUX, -1, -1, -1 }, + .parents = { X1000_CLK_MSCMUX }, .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 }, .gate = { CGU_REG_CLKGR, 4 }, }, @@ -349,8 +413,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_OTG] = { "otg", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, - .parents = { X1000_CLK_EXCLK, -1, - X1000_CLK_APLL, X1000_CLK_MPLL }, + .parents = { X1000_CLK_EXCLK, -1, X1000_CLK_APLL, X1000_CLK_MPLL }, .mux = { CGU_REG_USBCDR, 30, 2 }, .div = { CGU_REG_USBCDR, 0, 1, 8, 29, 28, 27 }, .gate = { CGU_REG_CLKGR, 3 }, @@ -358,7 +421,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_SSIPLL] = { "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV, - .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 }, + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL }, .mux = { CGU_REG_SSICDR, 31, 1 }, .div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 }, }, @@ -371,7 +434,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_SSIMUX] = { "ssi_mux", CGU_CLK_MUX, - .parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL_DIV2, -1, -1 }, + .parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL_DIV2 }, .mux = { CGU_REG_SSICDR, 30, 1 }, }, @@ -392,79 +455,85 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_EMC] = { "emc", CGU_CLK_GATE, - .parents = { X1000_CLK_AHB2, -1, -1, -1 }, + .parents = { X1000_CLK_AHB2 }, .gate = { CGU_REG_CLKGR, 0 }, }, [X1000_CLK_EFUSE] = { "efuse", CGU_CLK_GATE, - .parents = { X1000_CLK_AHB2, -1, -1, -1 }, + .parents = { X1000_CLK_AHB2 }, .gate = { CGU_REG_CLKGR, 1 }, }, [X1000_CLK_SFC] = { "sfc", CGU_CLK_GATE, - .parents = { X1000_CLK_SSIPLL, -1, -1, -1 }, + .parents = { X1000_CLK_SSIPLL }, .gate = { CGU_REG_CLKGR, 2 }, }, [X1000_CLK_I2C0] = { "i2c0", CGU_CLK_GATE, - .parents = { X1000_CLK_PCLK, -1, -1, -1 }, + .parents = { X1000_CLK_PCLK }, .gate = { CGU_REG_CLKGR, 7 }, }, [X1000_CLK_I2C1] = { "i2c1", CGU_CLK_GATE, - .parents = { X1000_CLK_PCLK, -1, -1, -1 }, + .parents = { X1000_CLK_PCLK }, .gate = { CGU_REG_CLKGR, 8 }, }, [X1000_CLK_I2C2] = { "i2c2", CGU_CLK_GATE, - .parents = { X1000_CLK_PCLK, -1, -1, -1 }, + .parents = { X1000_CLK_PCLK }, .gate = { CGU_REG_CLKGR, 9 }, }, + [X1000_CLK_AIC] = { + "aic", CGU_CLK_GATE, + .parents = { X1000_CLK_EXCLK }, + .gate = { CGU_REG_CLKGR, 11 }, + }, + [X1000_CLK_UART0] = { "uart0", CGU_CLK_GATE, - .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, + .parents = { X1000_CLK_EXCLK }, .gate = { CGU_REG_CLKGR, 14 }, }, [X1000_CLK_UART1] = { "uart1", CGU_CLK_GATE, - .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, + .parents = { X1000_CLK_EXCLK}, .gate = { CGU_REG_CLKGR, 15 }, }, [X1000_CLK_UART2] = { "uart2", CGU_CLK_GATE, - .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, + .parents = { X1000_CLK_EXCLK }, .gate = { CGU_REG_CLKGR, 16 }, }, [X1000_CLK_TCU] = { "tcu", CGU_CLK_GATE, - .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, + .parents = { X1000_CLK_EXCLK }, .gate = { CGU_REG_CLKGR, 18 }, }, [X1000_CLK_SSI] = { "ssi", CGU_CLK_GATE, - .parents = { X1000_CLK_SSIMUX, -1, -1, -1 }, + .parents = { X1000_CLK_SSIMUX }, .gate = { CGU_REG_CLKGR, 19 }, }, [X1000_CLK_OST] = { "ost", CGU_CLK_GATE, - .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, + .parents = { X1000_CLK_EXCLK }, .gate = { CGU_REG_CLKGR, 20 }, }, [X1000_CLK_PDMA] = { "pdma", CGU_CLK_GATE, - .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, + .parents = { X1000_CLK_EXCLK }, .gate = { CGU_REG_CLKGR, 21 }, }, }; diff --git a/drivers/clk/keystone/syscon-clk.c b/drivers/clk/keystone/syscon-clk.c index 19198325b909..5d7cc83682da 100644 --- a/drivers/clk/keystone/syscon-clk.c +++ b/drivers/clk/keystone/syscon-clk.c @@ -102,12 +102,9 @@ static int ti_syscon_gate_clk_probe(struct platform_device *pdev) return -EINVAL; regmap = syscon_node_to_regmap(dev->of_node); - if (IS_ERR(regmap)) { - if (PTR_ERR(regmap) == -EPROBE_DEFER) - return -EPROBE_DEFER; - dev_err(dev, "failed to find parent regmap\n"); - return PTR_ERR(regmap); - } + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), + "failed to find parent regmap\n"); num_clks = 0; for (p = data; p->name; p++) diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/mediatek/clk-mt8195-topckgen.c index 8cbab5ca2e58..1e016329c1d2 100644 --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c @@ -1270,8 +1270,10 @@ static int clk_mt8195_topck_probe(struct platform_device *pdev) hw = devm_clk_hw_register_mux(&pdev->dev, "mfg_ck_fast_ref", mfg_fast_parents, ARRAY_SIZE(mfg_fast_parents), CLK_SET_RATE_PARENT, (base + 0x250), 8, 1, 0, &mt8195_clk_lock); - if (IS_ERR(hw)) + if (IS_ERR(hw)) { + r = PTR_ERR(hw); goto unregister_muxes; + } top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF] = hw; r = clk_mt8195_reg_mfg_mux_notifier(&pdev->dev, diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 9e55617bc3b4..afefeba6e458 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -32,7 +32,6 @@ #include <linux/io.h> #include <linux/math64.h> #include <linux/module.h> -#include <linux/rational.h> #include "clk-regmap.h" #include "clk-pll.h" @@ -277,15 +276,15 @@ static int meson_clk_pll_wait_lock(struct clk_hw *hw) { struct clk_regmap *clk = to_clk_regmap(hw); struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); - int delay = 24000000; + int delay = 5000; do { - /* Is the clock locked now ? */ + /* Is the clock locked now ? Time out after 100ms. */ if (meson_parm_read(clk->map, &pll->l)) return 0; - delay--; - } while (delay > 0); + udelay(20); + } while (--delay); return -ETIMEDOUT; } @@ -320,12 +319,16 @@ static int meson_clk_pll_is_enabled(struct clk_hw *hw) static int meson_clk_pcie_pll_enable(struct clk_hw *hw) { - meson_clk_pll_init(hw); + int retries = 10; - if (meson_clk_pll_wait_lock(hw)) - return -EIO; + do { + meson_clk_pll_init(hw); + if (!meson_clk_pll_wait_lock(hw)) + return 0; + pr_info("Retry enabling PCIe PLL clock\n"); + } while (--retries); - return 0; + return -EIO; } static int meson_clk_pll_enable(struct clk_hw *hw) diff --git a/drivers/clk/mstar/Kconfig b/drivers/clk/mstar/Kconfig index de37e1bce2d2..b9bcb5e02814 100644 --- a/drivers/clk/mstar/Kconfig +++ b/drivers/clk/mstar/Kconfig @@ -1,4 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-only +config MSTAR_MSC313_CPUPLL + bool "MStar CPUPLL driver" + depends on ARCH_MSTARV7 || COMPILE_TEST + default ARCH_MSTARV7 + help + Support for the CPU PLL present on MStar/Sigmastar SoCs. + config MSTAR_MSC313_MPLL bool "MStar MPLL driver" depends on ARCH_MSTARV7 || COMPILE_TEST diff --git a/drivers/clk/mstar/Makefile b/drivers/clk/mstar/Makefile index f8dcd25ede1d..17d97eedcd36 100644 --- a/drivers/clk/mstar/Makefile +++ b/drivers/clk/mstar/Makefile @@ -3,4 +3,5 @@ # Makefile for mstar specific clk # +obj-$(CONFIG_MSTAR_MSC313_CPUPLL) += clk-msc313-cpupll.o obj-$(CONFIG_MSTAR_MSC313_MPLL) += clk-msc313-mpll.o diff --git a/drivers/clk/mstar/clk-msc313-cpupll.c b/drivers/clk/mstar/clk-msc313-cpupll.c new file mode 100644 index 000000000000..a93e2dba09d3 --- /dev/null +++ b/drivers/clk/mstar/clk-msc313-cpupll.c @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Daniel Palmer <daniel@thingy.jp> + */ + +#include <linux/clk-provider.h> +#include <linux/device.h> +#include <linux/kernel.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> + +/* + * This IP is not documented outside of the messy vendor driver. + * Below is what we think the registers look like based on looking at + * the vendor code and poking at the hardware: + * + * 0x140 -- LPF low. Seems to store one half of the clock transition + * 0x144 / + * 0x148 -- LPF high. Seems to store one half of the clock transition + * 0x14c / + * 0x150 -- vendor code says "toggle lpf enable" + * 0x154 -- mu? + * 0x15c -- lpf_update_count? + * 0x160 -- vendor code says "switch to LPF". Clock source config? Register bank? + * 0x164 -- vendor code says "from low to high" which seems to mean transition from LPF low to + * LPF high. + * 0x174 -- Seems to be the PLL lock status bit + * 0x180 -- Seems to be the current frequency, this might need to be populated by software? + * 0x184 / The vendor driver uses these to set the initial value of LPF low + * + * Frequency seems to be calculated like this: + * (parent clock (432mhz) / register_magic_value) * 16 * 524288 + * Only the lower 24 bits of the resulting value will be used. In addition, the + * PLL doesn't seem to be able to lock on frequencies lower than 220 MHz, as + * divisor 0xfb586f (220 MHz) works but 0xfb7fff locks up. + * + * Vendor values: + * frequency - register value + * + * 400000000 - 0x0067AE14 + * 600000000 - 0x00451EB8, + * 800000000 - 0x0033D70A, + * 1000000000 - 0x002978d4, + */ + +#define REG_LPF_LOW_L 0x140 +#define REG_LPF_LOW_H 0x144 +#define REG_LPF_HIGH_BOTTOM 0x148 +#define REG_LPF_HIGH_TOP 0x14c +#define REG_LPF_TOGGLE 0x150 +#define REG_LPF_MYSTERYTWO 0x154 +#define REG_LPF_UPDATE_COUNT 0x15c +#define REG_LPF_MYSTERYONE 0x160 +#define REG_LPF_TRANSITIONCTRL 0x164 +#define REG_LPF_LOCK 0x174 +#define REG_CURRENT 0x180 + +#define LPF_LOCK_TIMEOUT 100000000 + +#define MULTIPLIER_1 16 +#define MULTIPLIER_2 524288 +#define MULTIPLIER (MULTIPLIER_1 * MULTIPLIER_2) + +struct msc313_cpupll { + void __iomem *base; + struct clk_hw clk_hw; +}; + +#define to_cpupll(_hw) container_of(_hw, struct msc313_cpupll, clk_hw) + +static u32 msc313_cpupll_reg_read32(struct msc313_cpupll *cpupll, unsigned int reg) +{ + u32 value; + + value = ioread16(cpupll->base + reg + 4) << 16; + value |= ioread16(cpupll->base + reg); + + return value; +} + +static void msc313_cpupll_reg_write32(struct msc313_cpupll *cpupll, unsigned int reg, u32 value) +{ + u16 l = value & 0xffff, h = (value >> 16) & 0xffff; + + iowrite16(l, cpupll->base + reg); + iowrite16(h, cpupll->base + reg + 4); +} + +static void msc313_cpupll_setfreq(struct msc313_cpupll *cpupll, u32 regvalue) +{ + ktime_t timeout; + + msc313_cpupll_reg_write32(cpupll, REG_LPF_HIGH_BOTTOM, regvalue); + + iowrite16(0x1, cpupll->base + REG_LPF_MYSTERYONE); + iowrite16(0x6, cpupll->base + REG_LPF_MYSTERYTWO); + iowrite16(0x8, cpupll->base + REG_LPF_UPDATE_COUNT); + iowrite16(BIT(12), cpupll->base + REG_LPF_TRANSITIONCTRL); + + iowrite16(0, cpupll->base + REG_LPF_TOGGLE); + iowrite16(1, cpupll->base + REG_LPF_TOGGLE); + + timeout = ktime_add_ns(ktime_get(), LPF_LOCK_TIMEOUT); + while (!(ioread16(cpupll->base + REG_LPF_LOCK))) { + if (ktime_after(ktime_get(), timeout)) { + pr_err("timeout waiting for LPF_LOCK\n"); + return; + } + cpu_relax(); + } + + iowrite16(0, cpupll->base + REG_LPF_TOGGLE); + + msc313_cpupll_reg_write32(cpupll, REG_LPF_LOW_L, regvalue); +} + +static unsigned long msc313_cpupll_frequencyforreg(u32 reg, unsigned long parent_rate) +{ + unsigned long long prescaled = ((unsigned long long)parent_rate) * MULTIPLIER; + + if (prescaled == 0 || reg == 0) + return 0; + return DIV_ROUND_DOWN_ULL(prescaled, reg); +} + +static u32 msc313_cpupll_regforfrequecy(unsigned long rate, unsigned long parent_rate) +{ + unsigned long long prescaled = ((unsigned long long)parent_rate) * MULTIPLIER; + + if (prescaled == 0 || rate == 0) + return 0; + return DIV_ROUND_UP_ULL(prescaled, rate); +} + +static unsigned long msc313_cpupll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + struct msc313_cpupll *cpupll = to_cpupll(hw); + + return msc313_cpupll_frequencyforreg(msc313_cpupll_reg_read32(cpupll, REG_LPF_LOW_L), + parent_rate); +} + +static long msc313_cpupll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + u32 reg = msc313_cpupll_regforfrequecy(rate, *parent_rate); + long rounded = msc313_cpupll_frequencyforreg(reg, *parent_rate); + + /* + * This is my poor attempt at making sure the resulting + * rate doesn't overshoot the requested rate. + */ + for (; rounded >= rate && reg > 0; reg--) + rounded = msc313_cpupll_frequencyforreg(reg, *parent_rate); + + return rounded; +} + +static int msc313_cpupll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) +{ + struct msc313_cpupll *cpupll = to_cpupll(hw); + u32 reg = msc313_cpupll_regforfrequecy(rate, parent_rate); + + msc313_cpupll_setfreq(cpupll, reg); + + return 0; +} + +static const struct clk_ops msc313_cpupll_ops = { + .recalc_rate = msc313_cpupll_recalc_rate, + .round_rate = msc313_cpupll_round_rate, + .set_rate = msc313_cpupll_set_rate, +}; + +static const struct of_device_id msc313_cpupll_of_match[] = { + { .compatible = "mstar,msc313-cpupll" }, + {} +}; + +static int msc313_cpupll_probe(struct platform_device *pdev) +{ + struct clk_init_data clk_init = {}; + struct clk_parent_data cpupll_parent = { .index = 0 }; + struct device *dev = &pdev->dev; + struct msc313_cpupll *cpupll; + int ret; + + cpupll = devm_kzalloc(&pdev->dev, sizeof(*cpupll), GFP_KERNEL); + if (!cpupll) + return -ENOMEM; + + cpupll->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(cpupll->base)) + return PTR_ERR(cpupll->base); + + /* LPF might not contain the current frequency so fix that up */ + msc313_cpupll_reg_write32(cpupll, REG_LPF_LOW_L, + msc313_cpupll_reg_read32(cpupll, REG_CURRENT)); + + clk_init.name = dev_name(dev); + clk_init.ops = &msc313_cpupll_ops; + clk_init.parent_data = &cpupll_parent; + clk_init.num_parents = 1; + cpupll->clk_hw.init = &clk_init; + + ret = devm_clk_hw_register(dev, &cpupll->clk_hw); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_simple_get, &cpupll->clk_hw); +} + +static struct platform_driver msc313_cpupll_driver = { + .driver = { + .name = "mstar-msc313-cpupll", + .of_match_table = msc313_cpupll_of_match, + }, + .probe = msc313_cpupll_probe, +}; +builtin_platform_driver(msc313_cpupll_driver); diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c index 8afb7575e712..46d41ebce2b0 100644 --- a/drivers/clk/qcom/gcc-sc7280.c +++ b/drivers/clk/qcom/gcc-sc7280.c @@ -3467,6 +3467,7 @@ static int gcc_sc7280_probe(struct platform_device *pdev) regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); regmap_update_bits(regmap, 0x28014, BIT(0), BIT(0)); regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x7100C, BIT(13), BIT(13)); ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c index a18ed88f3b82..b3198784e1c3 100644 --- a/drivers/clk/qcom/gcc-sc8280xp.c +++ b/drivers/clk/qcom/gcc-sc8280xp.c @@ -5364,6 +5364,8 @@ static struct clk_branch gcc_ufs_1_card_clkref_clk = { .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_1_card_clkref_clk", + .parent_data = &gcc_parent_data_tcxo, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -5432,6 +5434,8 @@ static struct clk_branch gcc_ufs_card_clkref_clk = { .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_card_clkref_clk", + .parent_data = &gcc_parent_data_tcxo, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -5848,6 +5852,8 @@ static struct clk_branch gcc_ufs_ref_clkref_clk = { .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_ref_clkref_clk", + .parent_data = &gcc_parent_data_tcxo, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 7cf5e130e92f..0f21a8a767ac 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -11,7 +11,6 @@ #include <linux/kernel.h> #include <linux/ktime.h> #include <linux/pm_domain.h> -#include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> #include <linux/reset-controller.h> @@ -56,22 +55,6 @@ enum gdsc_status { GDSC_ON }; -static int gdsc_pm_runtime_get(struct gdsc *sc) -{ - if (!sc->dev) - return 0; - - return pm_runtime_resume_and_get(sc->dev); -} - -static int gdsc_pm_runtime_put(struct gdsc *sc) -{ - if (!sc->dev) - return 0; - - return pm_runtime_put_sync(sc->dev); -} - /* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */ static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status) { @@ -271,8 +254,9 @@ static void gdsc_retain_ff_on(struct gdsc *sc) regmap_update_bits(sc->regmap, sc->gdscr, mask, mask); } -static int _gdsc_enable(struct gdsc *sc) +static int gdsc_enable(struct generic_pm_domain *domain) { + struct gdsc *sc = domain_to_gdsc(domain); int ret; if (sc->pwrsts == PWRSTS_ON) @@ -328,22 +312,11 @@ static int _gdsc_enable(struct gdsc *sc) return 0; } -static int gdsc_enable(struct generic_pm_domain *domain) +static int gdsc_disable(struct generic_pm_domain *domain) { struct gdsc *sc = domain_to_gdsc(domain); int ret; - ret = gdsc_pm_runtime_get(sc); - if (ret) - return ret; - - return _gdsc_enable(sc); -} - -static int _gdsc_disable(struct gdsc *sc) -{ - int ret; - if (sc->pwrsts == PWRSTS_ON) return gdsc_assert_reset(sc); @@ -388,18 +361,6 @@ static int _gdsc_disable(struct gdsc *sc) return 0; } -static int gdsc_disable(struct generic_pm_domain *domain) -{ - struct gdsc *sc = domain_to_gdsc(domain); - int ret; - - ret = _gdsc_disable(sc); - - gdsc_pm_runtime_put(sc); - - return ret; -} - static int gdsc_init(struct gdsc *sc) { u32 mask, val; @@ -447,11 +408,6 @@ static int gdsc_init(struct gdsc *sc) return ret; } - /* ...and the power-domain */ - ret = gdsc_pm_runtime_get(sc); - if (ret) - goto err_disable_supply; - /* * Votable GDSCs can be ON due to Vote from other masters. * If a Votable GDSC is ON, make sure we have a Vote. @@ -459,14 +415,14 @@ static int gdsc_init(struct gdsc *sc) if (sc->flags & VOTABLE) { ret = gdsc_update_collapse_bit(sc, false); if (ret) - goto err_put_rpm; + goto err_disable_supply; } /* Turn on HW trigger mode if supported */ if (sc->flags & HW_CTRL) { ret = gdsc_hwctrl(sc, true); if (ret < 0) - goto err_put_rpm; + goto err_disable_supply; } /* @@ -496,13 +452,10 @@ static int gdsc_init(struct gdsc *sc) ret = pm_genpd_init(&sc->pd, NULL, !on); if (ret) - goto err_put_rpm; + goto err_disable_supply; return 0; -err_put_rpm: - if (on) - gdsc_pm_runtime_put(sc); err_disable_supply: if (on && sc->rsupply) regulator_disable(sc->rsupply); @@ -541,8 +494,6 @@ int gdsc_register(struct gdsc_desc *desc, for (i = 0; i < num; i++) { if (!scs[i]) continue; - if (pm_runtime_enabled(dev)) - scs[i]->dev = dev; scs[i]->regmap = regmap; scs[i]->rcdev = rcdev; ret = gdsc_init(scs[i]); diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index 981a12c8502d..803512688336 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -30,7 +30,6 @@ struct reset_controller_dev; * @resets: ids of resets associated with this gdsc * @reset_count: number of @resets * @rcdev: reset controller - * @dev: the device holding the GDSC, used for pm_runtime calls */ struct gdsc { struct generic_pm_domain pd; @@ -74,7 +73,6 @@ struct gdsc { const char *supply; struct regulator *rsupply; - struct device *dev; }; struct gdsc_desc { diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc7280.c index 9a832f2bcf49..1490cd45a654 100644 --- a/drivers/clk/qcom/gpucc-sc7280.c +++ b/drivers/clk/qcom/gpucc-sc7280.c @@ -463,6 +463,7 @@ static int gpu_cc_sc7280_probe(struct platform_device *pdev) */ regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0)); regmap_update_bits(regmap, 0x1098, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x1098, BIT(13), BIT(13)); return qcom_cc_really_probe(pdev, &gpu_cc_sc7280_desc, regmap); } diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index d74d46833012..e02542ca24a0 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -116,7 +116,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { DEF_FIXED("cp", R8A779A0_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cl16mck", R8A779A0_CLK_CL16MCK, CLK_PLL1_DIV2, 64, 1), - DEF_GEN4_SDH("sdh0", R8A779A0_CLK_SD0H, CLK_SDSRC, 0x870), + DEF_GEN4_SDH("sd0h", R8A779A0_CLK_SD0H, CLK_SDSRC, 0x870), DEF_GEN4_SD("sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, 0x870), DEF_BASE("rpc", R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index 4baf355e26d8..f721835c7e21 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -42,6 +42,7 @@ enum clk_ids { CLK_PLL5_DIV4, CLK_PLL6_DIV2, CLK_S0, + CLK_SASYNCPER, CLK_SDSRC, CLK_RPCSRC, CLK_OCO, @@ -71,6 +72,7 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1), DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".sasyncper", CLK_SASYNCPER, CLK_PLL5_DIV4, 3, 1), DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5), DEF_RATE(".oco", CLK_OCO, 32768), @@ -109,11 +111,11 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { DEF_FIXED("cpex", R8A779F0_CLK_CPEX, CLK_EXTAL, 2, 1), DEF_FIXED("sasyncrt", R8A779F0_CLK_SASYNCRT, CLK_PLL5_DIV4, 48, 1), - DEF_FIXED("sasyncperd1", R8A779F0_CLK_SASYNCPERD1, CLK_PLL5_DIV4, 3, 1), - DEF_FIXED("sasyncperd2", R8A779F0_CLK_SASYNCPERD2, R8A779F0_CLK_SASYNCPERD1, 2, 1), - DEF_FIXED("sasyncperd4", R8A779F0_CLK_SASYNCPERD4, R8A779F0_CLK_SASYNCPERD1, 4, 1), + DEF_FIXED("sasyncperd1",R8A779F0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1), + DEF_FIXED("sasyncperd2",R8A779F0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1), + DEF_FIXED("sasyncperd4",R8A779F0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1), - DEF_GEN4_SDH("sdh0", R8A779F0_CLK_SD0H, CLK_SDSRC, 0x870), + DEF_GEN4_SDH("sd0h", R8A779F0_CLK_SD0H, CLK_SDSRC, 0x870), DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, R8A779F0_CLK_SD0H, 0x870), DEF_BASE("rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), @@ -126,10 +128,10 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { - DEF_MOD("hscif0", 514, R8A779F0_CLK_S0D3), - DEF_MOD("hscif1", 515, R8A779F0_CLK_S0D3), - DEF_MOD("hscif2", 516, R8A779F0_CLK_S0D3), - DEF_MOD("hscif3", 517, R8A779F0_CLK_S0D3), + DEF_MOD("hscif0", 514, R8A779F0_CLK_SASYNCPERD1), + DEF_MOD("hscif1", 515, R8A779F0_CLK_SASYNCPERD1), + DEF_MOD("hscif2", 516, R8A779F0_CLK_SASYNCPERD1), + DEF_MOD("hscif3", 517, R8A779F0_CLK_SASYNCPERD1), DEF_MOD("i2c0", 518, R8A779F0_CLK_S0D6_PER), DEF_MOD("i2c1", 519, R8A779F0_CLK_S0D6_PER), DEF_MOD("i2c2", 520, R8A779F0_CLK_S0D6_PER), @@ -142,10 +144,10 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { DEF_MOD("msiof3", 621, R8A779F0_CLK_MSO), DEF_MOD("pcie0", 624, R8A779F0_CLK_S0D2), DEF_MOD("pcie1", 625, R8A779F0_CLK_S0D2), - DEF_MOD("scif0", 702, R8A779F0_CLK_S0D12_PER), - DEF_MOD("scif1", 703, R8A779F0_CLK_S0D12_PER), - DEF_MOD("scif3", 704, R8A779F0_CLK_S0D12_PER), - DEF_MOD("scif4", 705, R8A779F0_CLK_S0D12_PER), + DEF_MOD("scif0", 702, R8A779F0_CLK_SASYNCPERD4), + DEF_MOD("scif1", 703, R8A779F0_CLK_SASYNCPERD4), + DEF_MOD("scif3", 704, R8A779F0_CLK_SASYNCPERD4), + DEF_MOD("scif4", 705, R8A779F0_CLK_SASYNCPERD4), DEF_MOD("sdhi0", 706, R8A779F0_CLK_SD0), DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER), DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER), @@ -161,6 +163,8 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { DEF_MOD("cmt3", 913, R8A779F0_CLK_R), DEF_MOD("pfc0", 915, R8A779F0_CLK_CL16M), DEF_MOD("tsc", 919, R8A779F0_CLK_CL16M), + DEF_MOD("rswitch2", 1505, R8A779F0_CLK_RSW2), + DEF_MOD("ether-serdes", 1506, R8A779F0_CLK_S0D2_HSC), DEF_MOD("ufs", 1514, R8A779F0_CLK_S0D4_HSC), }; diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c index 9641122133b5..c6337a408e5e 100644 --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c @@ -47,6 +47,7 @@ enum clk_ids { CLK_S0_VIO, CLK_S0_VC, CLK_S0_HSC, + CLK_SASYNCPER, CLK_SV_VIP, CLK_SV_IR, CLK_SDSRC, @@ -84,16 +85,18 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { DEF_FIXED(".s0_vio", CLK_S0_VIO, CLK_PLL1_DIV2, 2, 1), DEF_FIXED(".s0_vc", CLK_S0_VC, CLK_PLL1_DIV2, 2, 1), DEF_FIXED(".s0_hsc", CLK_S0_HSC, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".sasyncper", CLK_SASYNCPER, CLK_PLL5_DIV4, 3, 1), DEF_FIXED(".sv_vip", CLK_SV_VIP, CLK_PLL1, 5, 1), DEF_FIXED(".sv_ir", CLK_SV_IR, CLK_PLL1, 5, 1), DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5), DEF_RATE(".oco", CLK_OCO, 32768), - DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5), DEF_FIXED(".vio", CLK_VIO, CLK_PLL5_DIV2, 3, 1), DEF_FIXED(".vc", CLK_VC, CLK_PLL5_DIV2, 3, 1), /* Core Clock Outputs */ + DEF_GEN4_Z("z0", R8A779G0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 0), DEF_FIXED("s0d2", R8A779G0_CLK_S0D2, CLK_S0, 2, 1), DEF_FIXED("s0d3", R8A779G0_CLK_S0D3, CLK_S0, 3, 1), DEF_FIXED("s0d4", R8A779G0_CLK_S0D4, CLK_S0, 4, 1), @@ -128,6 +131,10 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { DEF_FIXED("s0d4_hsc", R8A779G0_CLK_S0D4_HSC, CLK_S0_HSC, 4, 1), DEF_FIXED("cl16m_hsc", R8A779G0_CLK_CL16M_HSC, CLK_S0_HSC, 48, 1), DEF_FIXED("s0d2_cc", R8A779G0_CLK_S0D2_CC, CLK_S0, 2, 1), + DEF_FIXED("sasyncrt", R8A779G0_CLK_SASYNCRT, CLK_PLL5_DIV4, 48, 1), + DEF_FIXED("sasyncperd1",R8A779G0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1), + DEF_FIXED("sasyncperd2",R8A779G0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1), + DEF_FIXED("sasyncperd4",R8A779G0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1), DEF_FIXED("svd1_ir", R8A779G0_CLK_SVD1_IR, CLK_SV_IR, 1, 1), DEF_FIXED("svd2_ir", R8A779G0_CLK_SVD2_IR, CLK_SV_IR, 2, 1), DEF_FIXED("svd1_vip", R8A779G0_CLK_SVD1_VIP, CLK_SV_VIP, 1, 1), @@ -139,7 +146,8 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1), DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1), - DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, CLK_SDSRC, 0x870), + DEF_GEN4_SDH("sd0h", R8A779G0_CLK_SD0H, CLK_SDSRC, 0x870), + DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, R8A779G0_CLK_SD0H, 0x870), DEF_DIV6P1("mso", R8A779G0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), DEF_BASE("rpc", R8A779G0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), @@ -153,17 +161,43 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC), DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC), DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC), - DEF_MOD("hscif0", 514, R8A779G0_CLK_S0D3_PER), - DEF_MOD("hscif1", 515, R8A779G0_CLK_S0D3_PER), - DEF_MOD("hscif2", 516, R8A779G0_CLK_S0D3_PER), - DEF_MOD("hscif3", 517, R8A779G0_CLK_S0D3_PER), + DEF_MOD("hscif0", 514, R8A779G0_CLK_SASYNCPERD1), + DEF_MOD("hscif1", 515, R8A779G0_CLK_SASYNCPERD1), + DEF_MOD("hscif2", 516, R8A779G0_CLK_SASYNCPERD1), + DEF_MOD("hscif3", 517, R8A779G0_CLK_SASYNCPERD1), DEF_MOD("i2c0", 518, R8A779G0_CLK_S0D6_PER), DEF_MOD("i2c1", 519, R8A779G0_CLK_S0D6_PER), DEF_MOD("i2c2", 520, R8A779G0_CLK_S0D6_PER), DEF_MOD("i2c3", 521, R8A779G0_CLK_S0D6_PER), DEF_MOD("i2c4", 522, R8A779G0_CLK_S0D6_PER), DEF_MOD("i2c5", 523, R8A779G0_CLK_S0D6_PER), + DEF_MOD("irqc", 611, R8A779G0_CLK_CL16M), + DEF_MOD("msi0", 618, R8A779G0_CLK_MSO), + DEF_MOD("msi1", 619, R8A779G0_CLK_MSO), + DEF_MOD("msi2", 620, R8A779G0_CLK_MSO), + DEF_MOD("msi3", 621, R8A779G0_CLK_MSO), + DEF_MOD("msi4", 622, R8A779G0_CLK_MSO), + DEF_MOD("msi5", 623, R8A779G0_CLK_MSO), + DEF_MOD("pwm", 628, R8A779G0_CLK_SASYNCPERD4), + DEF_MOD("rpc-if", 629, R8A779G0_CLK_RPCD2), + DEF_MOD("scif0", 702, R8A779G0_CLK_SASYNCPERD4), + DEF_MOD("scif1", 703, R8A779G0_CLK_SASYNCPERD4), + DEF_MOD("scif3", 704, R8A779G0_CLK_SASYNCPERD4), + DEF_MOD("scif4", 705, R8A779G0_CLK_SASYNCPERD4), + DEF_MOD("sdhi", 706, R8A779G0_CLK_SD0), + DEF_MOD("sydm0", 709, R8A779G0_CLK_S0D6_PER), + DEF_MOD("sydm1", 710, R8A779G0_CLK_S0D6_PER), + DEF_MOD("tmu0", 713, R8A779G0_CLK_SASYNCRT), + DEF_MOD("tmu1", 714, R8A779G0_CLK_SASYNCPERD2), + DEF_MOD("tmu2", 715, R8A779G0_CLK_SASYNCPERD2), + DEF_MOD("tmu3", 716, R8A779G0_CLK_SASYNCPERD2), + DEF_MOD("tmu4", 717, R8A779G0_CLK_SASYNCPERD2), + DEF_MOD("tpu0", 718, R8A779G0_CLK_SASYNCPERD4), DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R), + DEF_MOD("cmt0", 910, R8A779G0_CLK_R), + DEF_MOD("cmt1", 911, R8A779G0_CLK_R), + DEF_MOD("cmt2", 912, R8A779G0_CLK_R), + DEF_MOD("cmt3", 913, R8A779G0_CLK_R), DEF_MOD("pfc0", 915, R8A779G0_CLK_CL16M), DEF_MOD("pfc1", 916, R8A779G0_CLK_CL16M), DEF_MOD("pfc2", 917, R8A779G0_CLK_CL16M), diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c index 1488c9d6e639..983faa5707b9 100644 --- a/drivers/clk/renesas/r9a06g032-clocks.c +++ b/drivers/clk/renesas/r9a06g032-clocks.c @@ -412,7 +412,7 @@ static int r9a06g032_attach_dev(struct generic_pm_domain *pd, int error; int index; - while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, + while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i++, &clkspec)) { if (clkspec.np != pd->dev.of_node) continue; @@ -425,7 +425,6 @@ static int r9a06g032_attach_dev(struct generic_pm_domain *pd, if (error) return error; } - i++; } return 0; diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 37475465100d..99f72bf590fa 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -158,10 +158,6 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x548, 0), DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK, 0x548, 1), - DEF_MOD("wdt2_pclk", R9A07G043_WDT2_PCLK, R9A07G043_CLK_P0, - 0x548, 4), - DEF_MOD("wdt2_clk", R9A07G043_WDT2_CLK, R9A07G043_OSCCLK, - 0x548, 5), DEF_MOD("spi_clk2", R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1, 0x550, 0), DEF_MOD("spi_clk", R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0, @@ -269,7 +265,6 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1), DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2), DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0), - DEF_RST(R9A07G043_WDT2_PRESETN, 0x848, 2), DEF_RST(R9A07G043_SPI_RST, 0x850, 0), DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0), DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1), diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 02a4fc41bb6e..f5550fccb029 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -182,7 +182,7 @@ static const struct { }; static const struct { - struct rzg2l_mod_clk common[76]; + struct rzg2l_mod_clk common[75]; #ifdef CONFIG_CLK_R9A07G054 struct rzg2l_mod_clk drp[0]; #endif @@ -204,6 +204,8 @@ static const struct { 0x534, 1), DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0, 0x534, 2), + DEF_MOD("mtu_x_mck", R9A07G044_MTU_X_MCK_MTU3, R9A07G044_CLK_P0, + 0x538, 0), DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0, 0x540, 0), DEF_MOD("poeg_a_clkp", R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0, @@ -222,10 +224,6 @@ static const struct { 0x548, 2), DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK, 0x548, 3), - DEF_MOD("wdt2_pclk", R9A07G044_WDT2_PCLK, R9A07G044_CLK_P0, - 0x548, 4), - DEF_MOD("wdt2_clk", R9A07G044_WDT2_CLK, R9A07G044_OSCCLK, - 0x548, 5), DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1, 0x550, 0), DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0, @@ -356,6 +354,7 @@ static struct rzg2l_reset r9a07g044_resets[] = { DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0), DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1), DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2), + DEF_RST(R9A07G044_MTU_X_PRESET_MTU3, 0x838, 0), DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0), DEF_RST(R9A07G044_POEG_A_RST, 0x844, 0), DEF_RST(R9A07G044_POEG_B_RST, 0x844, 1), @@ -363,7 +362,6 @@ static struct rzg2l_reset r9a07g044_resets[] = { DEF_RST(R9A07G044_POEG_D_RST, 0x844, 3), DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0), DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1), - DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2), DEF_RST(R9A07G044_SPI_RST, 0x850, 0), DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0), DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1), diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 3ff6ecd61756..4bf40f6ccd1d 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -95,7 +95,8 @@ struct rzg2l_pll5_mux_dsi_div_param { * @num_resets: Number of Module Resets in info->resets[] * @last_dt_core_clk: ID of the last Core Clock exported to DT * @info: Pointer to platform data - * @pll5_mux_dsi_div_params: pll5 mux and dsi div parameters + * @genpd: PM domain + * @mux_dsi_div_params: pll5 mux and dsi div parameters */ struct rzg2l_cpg_priv { struct reset_controller_dev rcdev; @@ -111,6 +112,8 @@ struct rzg2l_cpg_priv { const struct rzg2l_cpg_info *info; + struct generic_pm_domain genpd; + struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params; }; @@ -182,7 +185,7 @@ rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core, static int rzg2l_cpg_sd_clk_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { - return clk_mux_determine_rate_flags(hw, req, 0); + return clk_mux_determine_rate_flags(hw, req, CLK_MUX_ROUND_CLOSEST); } static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) @@ -1014,8 +1017,8 @@ static const struct clk_ops rzg2l_mod_clock_ops = { }; static struct mstp_clock -*rzg2l_mod_clock__get_sibling(struct mstp_clock *clock, - struct rzg2l_cpg_priv *priv) +*rzg2l_mod_clock_get_sibling(struct mstp_clock *clock, + struct rzg2l_cpg_priv *priv) { struct clk_hw *hw; unsigned int i; @@ -1101,7 +1104,7 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod, struct mstp_clock *sibling; clock->enabled = rzg2l_mod_clock_is_enabled(&clock->hw); - sibling = rzg2l_mod_clock__get_sibling(clock, priv); + sibling = rzg2l_mod_clock_get_sibling(clock, priv); if (sibling) { clock->sibling = sibling; sibling->sibling = clock; @@ -1223,22 +1226,31 @@ static int rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv) return devm_reset_controller_register(priv->dev, &priv->rcdev); } -static bool rzg2l_cpg_is_pm_clk(const struct of_phandle_args *clkspec) +static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv, + const struct of_phandle_args *clkspec) { + const struct rzg2l_cpg_info *info = priv->info; + unsigned int id; + unsigned int i; + if (clkspec->args_count != 2) return false; - switch (clkspec->args[0]) { - case CPG_MOD: - return true; - - default: + if (clkspec->args[0] != CPG_MOD) return false; + + id = clkspec->args[1] + info->num_total_core_clks; + for (i = 0; i < info->num_no_pm_mod_clks; i++) { + if (info->no_pm_mod_clks[i] == id) + return false; } + + return true; } -static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused, struct device *dev) +static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev) { + struct rzg2l_cpg_priv *priv = container_of(domain, struct rzg2l_cpg_priv, genpd); struct device_node *np = dev->of_node; struct of_phandle_args clkspec; bool once = true; @@ -1248,7 +1260,7 @@ static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused, struct device while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, &clkspec)) { - if (rzg2l_cpg_is_pm_clk(&clkspec)) { + if (rzg2l_cpg_is_pm_clk(priv, &clkspec)) { if (once) { once = false; error = pm_clk_create(dev); @@ -1298,16 +1310,13 @@ static void rzg2l_cpg_genpd_remove(void *data) pm_genpd_remove(data); } -static int __init rzg2l_cpg_add_clk_domain(struct device *dev) +static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv) { + struct device *dev = priv->dev; struct device_node *np = dev->of_node; - struct generic_pm_domain *genpd; + struct generic_pm_domain *genpd = &priv->genpd; int ret; - genpd = devm_kzalloc(dev, sizeof(*genpd), GFP_KERNEL); - if (!genpd) - return -ENOMEM; - genpd->name = np->name; genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON | GENPD_FLAG_ACTIVE_WAKEUP; @@ -1377,7 +1386,7 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev) if (error) return error; - error = rzg2l_cpg_add_clk_domain(dev); + error = rzg2l_cpg_add_clk_domain(priv); if (error) return error; diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index cecbdf5e4f93..eee780276a9e 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -256,6 +256,10 @@ struct rzg2l_cpg_info { unsigned int num_mod_clks; unsigned int num_hw_mod_clks; + /* No PM Module Clocks */ + const unsigned int *no_pm_mod_clks; + unsigned int num_no_pm_mod_clks; + /* Resets */ const struct rzg2l_reset *resets; unsigned int num_resets; diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig index 345a5d2a457c..9aad86925cd2 100644 --- a/drivers/clk/rockchip/Kconfig +++ b/drivers/clk/rockchip/Kconfig @@ -99,4 +99,12 @@ config CLK_RK3568 default y help Build the driver for RK3568 Clock Driver. + +config CLK_RK3588 + bool "Rockchip RK3588 clock controller support" + depends on ARM64 || COMPILE_TEST + default y + help + Build the driver for RK3588 Clock Driver. + endif diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index e8543876c056..36894f6a7022 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -28,3 +28,4 @@ obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o +obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o rst-rk3588.o diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c index 47288197c9d7..6ea7fba9f9e5 100644 --- a/drivers/clk/rockchip/clk-cpu.c +++ b/drivers/clk/rockchip/clk-cpu.c @@ -113,6 +113,42 @@ static void rockchip_cpuclk_set_dividers(struct rockchip_cpuclk *cpuclk, } } +static void rockchip_cpuclk_set_pre_muxs(struct rockchip_cpuclk *cpuclk, + const struct rockchip_cpuclk_rate_table *rate) +{ + int i; + + /* alternate parent is active now. set the pre_muxs */ + for (i = 0; i < ARRAY_SIZE(rate->pre_muxs); i++) { + const struct rockchip_cpuclk_clksel *clksel = &rate->pre_muxs[i]; + + if (!clksel->reg) + break; + + pr_debug("%s: setting reg 0x%x to 0x%x\n", + __func__, clksel->reg, clksel->val); + writel(clksel->val, cpuclk->reg_base + clksel->reg); + } +} + +static void rockchip_cpuclk_set_post_muxs(struct rockchip_cpuclk *cpuclk, + const struct rockchip_cpuclk_rate_table *rate) +{ + int i; + + /* alternate parent is active now. set the muxs */ + for (i = 0; i < ARRAY_SIZE(rate->post_muxs); i++) { + const struct rockchip_cpuclk_clksel *clksel = &rate->post_muxs[i]; + + if (!clksel->reg) + break; + + pr_debug("%s: setting reg 0x%x to 0x%x\n", + __func__, clksel->reg, clksel->val); + writel(clksel->val, cpuclk->reg_base + clksel->reg); + } +} + static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, struct clk_notifier_data *ndata) { @@ -165,11 +201,20 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, cpuclk->reg_base + reg_data->core_reg[i]); } } + + rockchip_cpuclk_set_pre_muxs(cpuclk, rate); + /* select alternate parent */ - writel(HIWORD_UPDATE(reg_data->mux_core_alt, - reg_data->mux_core_mask, - reg_data->mux_core_shift), - cpuclk->reg_base + reg_data->core_reg[0]); + if (reg_data->mux_core_reg) + writel(HIWORD_UPDATE(reg_data->mux_core_alt, + reg_data->mux_core_mask, + reg_data->mux_core_shift), + cpuclk->reg_base + reg_data->mux_core_reg); + else + writel(HIWORD_UPDATE(reg_data->mux_core_alt, + reg_data->mux_core_mask, + reg_data->mux_core_shift), + cpuclk->reg_base + reg_data->core_reg[0]); spin_unlock_irqrestore(cpuclk->lock, flags); return 0; @@ -202,10 +247,18 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk, * primary parent by the extra dividers that were needed for the alt. */ - writel(HIWORD_UPDATE(reg_data->mux_core_main, - reg_data->mux_core_mask, - reg_data->mux_core_shift), - cpuclk->reg_base + reg_data->core_reg[0]); + if (reg_data->mux_core_reg) + writel(HIWORD_UPDATE(reg_data->mux_core_main, + reg_data->mux_core_mask, + reg_data->mux_core_shift), + cpuclk->reg_base + reg_data->mux_core_reg); + else + writel(HIWORD_UPDATE(reg_data->mux_core_main, + reg_data->mux_core_mask, + reg_data->mux_core_shift), + cpuclk->reg_base + reg_data->core_reg[0]); + + rockchip_cpuclk_set_post_muxs(cpuclk, rate); /* remove dividers */ for (i = 0; i < reg_data->num_cores; i++) { diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index f7827b3b7fc1..2d42eb628926 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -843,6 +843,213 @@ static const struct clk_ops rockchip_rk3399_pll_clk_ops = { }; /* + * PLL used in RK3588 + */ + +#define RK3588_PLLCON(i) (i * 0x4) +#define RK3588_PLLCON0_M_MASK 0x3ff +#define RK3588_PLLCON0_M_SHIFT 0 +#define RK3588_PLLCON1_P_MASK 0x3f +#define RK3588_PLLCON1_P_SHIFT 0 +#define RK3588_PLLCON1_S_MASK 0x7 +#define RK3588_PLLCON1_S_SHIFT 6 +#define RK3588_PLLCON2_K_MASK 0xffff +#define RK3588_PLLCON2_K_SHIFT 0 +#define RK3588_PLLCON1_PWRDOWN BIT(13) +#define RK3588_PLLCON6_LOCK_STATUS BIT(15) + +static int rockchip_rk3588_pll_wait_lock(struct rockchip_clk_pll *pll) +{ + u32 pllcon; + int ret; + + /* + * Lock time typical 250, max 500 input clock cycles @24MHz + * So define a very safe maximum of 1000us, meaning 24000 cycles. + */ + ret = readl_relaxed_poll_timeout(pll->reg_base + RK3588_PLLCON(6), + pllcon, + pllcon & RK3588_PLLCON6_LOCK_STATUS, + 0, 1000); + if (ret) + pr_err("%s: timeout waiting for pll to lock\n", __func__); + + return ret; +} + +static void rockchip_rk3588_pll_get_params(struct rockchip_clk_pll *pll, + struct rockchip_pll_rate_table *rate) +{ + u32 pllcon; + + pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(0)); + rate->m = ((pllcon >> RK3588_PLLCON0_M_SHIFT) & RK3588_PLLCON0_M_MASK); + + pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(1)); + rate->p = ((pllcon >> RK3588_PLLCON1_P_SHIFT) & RK3588_PLLCON1_P_MASK); + rate->s = ((pllcon >> RK3588_PLLCON1_S_SHIFT) & RK3588_PLLCON1_S_MASK); + + pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(2)); + rate->k = ((pllcon >> RK3588_PLLCON2_K_SHIFT) & RK3588_PLLCON2_K_MASK); +} + +static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, unsigned long prate) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + struct rockchip_pll_rate_table cur; + u64 rate64 = prate, postdiv; + + rockchip_rk3588_pll_get_params(pll, &cur); + + rate64 *= cur.m; + do_div(rate64, cur.p); + + if (cur.k) { + /* fractional mode */ + u64 frac_rate64 = prate * cur.k; + + postdiv = cur.p * 65535; + do_div(frac_rate64, postdiv); + rate64 += frac_rate64; + } + rate64 = rate64 >> cur.s; + + return (unsigned long)rate64; +} + +static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll, + const struct rockchip_pll_rate_table *rate) +{ + const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; + struct clk_mux *pll_mux = &pll->pll_mux; + struct rockchip_pll_rate_table cur; + int rate_change_remuxed = 0; + int cur_parent; + int ret; + + pr_debug("%s: rate settings for %lu p: %d, m: %d, s: %d, k: %d\n", + __func__, rate->rate, rate->p, rate->m, rate->s, rate->k); + + rockchip_rk3588_pll_get_params(pll, &cur); + cur.rate = 0; + + if (pll->type == pll_rk3588) { + cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); + if (cur_parent == PLL_MODE_NORM) { + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); + rate_change_remuxed = 1; + } + } + + /* set pll power down */ + writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN, + RK3588_PLLCON1_PWRDOWN, 0), + pll->reg_base + RK3399_PLLCON(1)); + + /* update pll values */ + writel_relaxed(HIWORD_UPDATE(rate->m, RK3588_PLLCON0_M_MASK, RK3588_PLLCON0_M_SHIFT), + pll->reg_base + RK3399_PLLCON(0)); + + writel_relaxed(HIWORD_UPDATE(rate->p, RK3588_PLLCON1_P_MASK, RK3588_PLLCON1_P_SHIFT) | + HIWORD_UPDATE(rate->s, RK3588_PLLCON1_S_MASK, RK3588_PLLCON1_S_SHIFT), + pll->reg_base + RK3399_PLLCON(1)); + + writel_relaxed(HIWORD_UPDATE(rate->k, RK3588_PLLCON2_K_MASK, RK3588_PLLCON2_K_SHIFT), + pll->reg_base + RK3399_PLLCON(2)); + + /* set pll power up */ + writel(HIWORD_UPDATE(0, RK3588_PLLCON1_PWRDOWN, 0), + pll->reg_base + RK3588_PLLCON(1)); + + /* wait for the pll to lock */ + ret = rockchip_rk3588_pll_wait_lock(pll); + if (ret) { + pr_warn("%s: pll update unsuccessful, trying to restore old params\n", + __func__); + rockchip_rk3588_pll_set_params(pll, &cur); + } + + if ((pll->type == pll_rk3588) && rate_change_remuxed) + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); + + return ret; +} + +static int rockchip_rk3588_pll_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + const struct rockchip_pll_rate_table *rate; + + pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", + __func__, __clk_get_name(hw->clk), drate, prate); + + /* Get required rate settings from table */ + rate = rockchip_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, __clk_get_name(hw->clk)); + return -EINVAL; + } + + return rockchip_rk3588_pll_set_params(pll, rate); +} + +static int rockchip_rk3588_pll_enable(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + + writel(HIWORD_UPDATE(0, RK3588_PLLCON1_PWRDOWN, 0), + pll->reg_base + RK3588_PLLCON(1)); + rockchip_rk3588_pll_wait_lock(pll); + + return 0; +} + +static void rockchip_rk3588_pll_disable(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + + writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN, RK3588_PLLCON1_PWRDOWN, 0), + pll->reg_base + RK3588_PLLCON(1)); +} + +static int rockchip_rk3588_pll_is_enabled(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + u32 pllcon = readl(pll->reg_base + RK3588_PLLCON(1)); + + return !(pllcon & RK3588_PLLCON1_PWRDOWN); +} + +static int rockchip_rk3588_pll_init(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + + if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) + return 0; + + return 0; +} + +static const struct clk_ops rockchip_rk3588_pll_clk_norate_ops = { + .recalc_rate = rockchip_rk3588_pll_recalc_rate, + .enable = rockchip_rk3588_pll_enable, + .disable = rockchip_rk3588_pll_disable, + .is_enabled = rockchip_rk3588_pll_is_enabled, +}; + +static const struct clk_ops rockchip_rk3588_pll_clk_ops = { + .recalc_rate = rockchip_rk3588_pll_recalc_rate, + .round_rate = rockchip_pll_round_rate, + .set_rate = rockchip_rk3588_pll_set_rate, + .enable = rockchip_rk3588_pll_enable, + .disable = rockchip_rk3588_pll_disable, + .is_enabled = rockchip_rk3588_pll_is_enabled, + .init = rockchip_rk3588_pll_init, +}; + +/* * Common registering of pll clocks */ @@ -890,7 +1097,8 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, if (pll_type == pll_rk3036 || pll_type == pll_rk3066 || pll_type == pll_rk3328 || - pll_type == pll_rk3399) + pll_type == pll_rk3399 || + pll_type == pll_rk3588) pll_mux->flags |= CLK_MUX_HIWORD_MASK; /* the actual muxing is xin24m, pll-output, xin32k */ @@ -957,6 +1165,14 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, else init.ops = &rockchip_rk3399_pll_clk_ops; break; + case pll_rk3588: + case pll_rk3588_core: + if (!pll->rate_table) + init.ops = &rockchip_rk3588_pll_clk_norate_ops; + else + init.ops = &rockchip_rk3588_pll_clk_ops; + init.flags = flags; + break; default: pr_warn("%s: Unknown pll type for pll clk %s\n", __func__, name); @@ -981,6 +1197,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, return mux_clk; err_pll: + kfree(pll->rate_table); clk_unregister(mux_clk); mux_clk = pll_clk; err_mux: diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c new file mode 100644 index 000000000000..b7ce3fbd6fa6 --- /dev/null +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -0,0 +1,2533 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang <zhangqing@rock-chips.com> + */ + +#include <linux/clk-provider.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/syscore_ops.h> +#include <dt-bindings/clock/rockchip,rk3588-cru.h> +#include "clk.h" + +/* + * GATE with additional linked clock. Downstream enables the linked clock + * (via runtime PM) whenever the gate is enabled. The downstream implementation + * does this via separate clock nodes for each of the linked gate clocks, + * which leaks parts of the clock tree into DT. It is unclear why this is + * actually needed and things work without it for simple use cases. Thus + * the linked clock is ignored for now. + */ +#define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \ + GATE(_id, cname, pname, f, o, b, gf) + + +#define RK3588_GRF_SOC_STATUS0 0x600 +#define RK3588_PHYREF_ALT_GATE 0xc38 + +enum rk3588_plls { + b0pll, b1pll, lpll, v0pll, aupll, cpll, gpll, npll, ppll, +}; + +static struct rockchip_pll_rate_table rk3588_pll_rates[] = { + /* _mhz, _p, _m, _s, _k */ + RK3588_PLL_RATE(2520000000, 2, 210, 0, 0), + RK3588_PLL_RATE(2496000000, 2, 208, 0, 0), + RK3588_PLL_RATE(2472000000, 2, 206, 0, 0), + RK3588_PLL_RATE(2448000000, 2, 204, 0, 0), + RK3588_PLL_RATE(2424000000, 2, 202, 0, 0), + RK3588_PLL_RATE(2400000000, 2, 200, 0, 0), + RK3588_PLL_RATE(2376000000, 2, 198, 0, 0), + RK3588_PLL_RATE(2352000000, 2, 196, 0, 0), + RK3588_PLL_RATE(2328000000, 2, 194, 0, 0), + RK3588_PLL_RATE(2304000000, 2, 192, 0, 0), + RK3588_PLL_RATE(2280000000, 2, 190, 0, 0), + RK3588_PLL_RATE(2256000000, 2, 376, 1, 0), + RK3588_PLL_RATE(2232000000, 2, 372, 1, 0), + RK3588_PLL_RATE(2208000000, 2, 368, 1, 0), + RK3588_PLL_RATE(2184000000, 2, 364, 1, 0), + RK3588_PLL_RATE(2160000000, 2, 360, 1, 0), + RK3588_PLL_RATE(2136000000, 2, 356, 1, 0), + RK3588_PLL_RATE(2112000000, 2, 352, 1, 0), + RK3588_PLL_RATE(2088000000, 2, 348, 1, 0), + RK3588_PLL_RATE(2064000000, 2, 344, 1, 0), + RK3588_PLL_RATE(2040000000, 2, 340, 1, 0), + RK3588_PLL_RATE(2016000000, 2, 336, 1, 0), + RK3588_PLL_RATE(1992000000, 2, 332, 1, 0), + RK3588_PLL_RATE(1968000000, 2, 328, 1, 0), + RK3588_PLL_RATE(1944000000, 2, 324, 1, 0), + RK3588_PLL_RATE(1920000000, 2, 320, 1, 0), + RK3588_PLL_RATE(1896000000, 2, 316, 1, 0), + RK3588_PLL_RATE(1872000000, 2, 312, 1, 0), + RK3588_PLL_RATE(1848000000, 2, 308, 1, 0), + RK3588_PLL_RATE(1824000000, 2, 304, 1, 0), + RK3588_PLL_RATE(1800000000, 2, 300, 1, 0), + RK3588_PLL_RATE(1776000000, 2, 296, 1, 0), + RK3588_PLL_RATE(1752000000, 2, 292, 1, 0), + RK3588_PLL_RATE(1728000000, 2, 288, 1, 0), + RK3588_PLL_RATE(1704000000, 2, 284, 1, 0), + RK3588_PLL_RATE(1680000000, 2, 280, 1, 0), + RK3588_PLL_RATE(1656000000, 2, 276, 1, 0), + RK3588_PLL_RATE(1632000000, 2, 272, 1, 0), + RK3588_PLL_RATE(1608000000, 2, 268, 1, 0), + RK3588_PLL_RATE(1584000000, 2, 264, 1, 0), + RK3588_PLL_RATE(1560000000, 2, 260, 1, 0), + RK3588_PLL_RATE(1536000000, 2, 256, 1, 0), + RK3588_PLL_RATE(1512000000, 2, 252, 1, 0), + RK3588_PLL_RATE(1488000000, 2, 248, 1, 0), + RK3588_PLL_RATE(1464000000, 2, 244, 1, 0), + RK3588_PLL_RATE(1440000000, 2, 240, 1, 0), + RK3588_PLL_RATE(1416000000, 2, 236, 1, 0), + RK3588_PLL_RATE(1392000000, 2, 232, 1, 0), + RK3588_PLL_RATE(1320000000, 2, 220, 1, 0), + RK3588_PLL_RATE(1200000000, 2, 200, 1, 0), + RK3588_PLL_RATE(1188000000, 2, 198, 1, 0), + RK3588_PLL_RATE(1100000000, 3, 550, 2, 0), + RK3588_PLL_RATE(1008000000, 2, 336, 2, 0), + RK3588_PLL_RATE(1000000000, 3, 500, 2, 0), + RK3588_PLL_RATE(983040000, 4, 655, 2, 23592), + RK3588_PLL_RATE(955520000, 3, 477, 2, 49806), + RK3588_PLL_RATE(903168000, 6, 903, 2, 11009), + RK3588_PLL_RATE(900000000, 2, 300, 2, 0), + RK3588_PLL_RATE(850000000, 3, 425, 2, 0), + RK3588_PLL_RATE(816000000, 2, 272, 2, 0), + RK3588_PLL_RATE(786432000, 2, 262, 2, 9437), + RK3588_PLL_RATE(786000000, 1, 131, 2, 0), + RK3588_PLL_RATE(785560000, 3, 392, 2, 51117), + RK3588_PLL_RATE(722534400, 8, 963, 2, 24850), + RK3588_PLL_RATE(600000000, 2, 200, 2, 0), + RK3588_PLL_RATE(594000000, 2, 198, 2, 0), + RK3588_PLL_RATE(408000000, 2, 272, 3, 0), + RK3588_PLL_RATE(312000000, 2, 208, 3, 0), + RK3588_PLL_RATE(216000000, 2, 288, 4, 0), + RK3588_PLL_RATE(100000000, 3, 400, 5, 0), + RK3588_PLL_RATE(96000000, 2, 256, 5, 0), + { /* sentinel */ }, +}; + +#define RK3588_CLK_CORE_B0_SEL_CLEAN_MASK 0x3 +#define RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT 13 +#define RK3588_CLK_CORE_B1_SEL_CLEAN_MASK 0x3 +#define RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT 5 +#define RK3588_CLK_CORE_B0_GPLL_DIV_MASK 0x1f +#define RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT 1 +#define RK3588_CLK_CORE_L_SEL_CLEAN_MASK 0x3 +#define RK3588_CLK_CORE_L1_SEL_CLEAN_SHIFT 12 +#define RK3588_CLK_CORE_L0_SEL_CLEAN_SHIFT 5 +#define RK3588_CLK_DSU_SEL_DF_MASK 0x1 +#define RK3588_CLK_DSU_SEL_DF_SHIFT 15 +#define RK3588_CLK_DSU_DF_SRC_MASK 0x3 +#define RK3588_CLK_DSU_DF_SRC_SHIFT 12 +#define RK3588_CLK_DSU_DF_DIV_MASK 0x1f +#define RK3588_CLK_DSU_DF_DIV_SHIFT 7 +#define RK3588_ACLKM_DSU_DIV_MASK 0x1f +#define RK3588_ACLKM_DSU_DIV_SHIFT 1 +#define RK3588_ACLKS_DSU_DIV_MASK 0x1f +#define RK3588_ACLKS_DSU_DIV_SHIFT 6 +#define RK3588_ACLKMP_DSU_DIV_MASK 0x1f +#define RK3588_ACLKMP_DSU_DIV_SHIFT 11 +#define RK3588_PERIPH_DSU_DIV_MASK 0x1f +#define RK3588_PERIPH_DSU_DIV_SHIFT 0 +#define RK3588_ATCLK_DSU_DIV_MASK 0x1f +#define RK3588_ATCLK_DSU_DIV_SHIFT 0 +#define RK3588_GICCLK_DSU_DIV_MASK 0x1f +#define RK3588_GICCLK_DSU_DIV_SHIFT 5 + +#define RK3588_CORE_B0_SEL(_apllcore) \ +{ \ + .reg = RK3588_BIGCORE0_CLKSEL_CON(0), \ + .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \ + RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT) | \ + HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \ + RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT), \ +} + +#define RK3588_CORE_B1_SEL(_apllcore) \ +{ \ + .reg = RK3588_BIGCORE0_CLKSEL_CON(1), \ + .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \ + RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT), \ +} + +#define RK3588_CORE_B2_SEL(_apllcore) \ +{ \ + .reg = RK3588_BIGCORE1_CLKSEL_CON(0), \ + .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \ + RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT) | \ + HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \ + RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT), \ +} + +#define RK3588_CORE_B3_SEL(_apllcore) \ +{ \ + .reg = RK3588_BIGCORE1_CLKSEL_CON(1), \ + .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \ + RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT), \ +} + +#define RK3588_CORE_L_SEL0(_offs, _apllcore) \ +{ \ + .reg = RK3588_DSU_CLKSEL_CON(6 + _offs), \ + .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \ + RK3588_CLK_CORE_L0_SEL_CLEAN_SHIFT) | \ + HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \ + RK3588_CLK_CORE_L1_SEL_CLEAN_SHIFT), \ +} + +#define RK3588_CORE_L_SEL1(_seldsu, _divdsu) \ +{ \ + .reg = RK3588_DSU_CLKSEL_CON(0), \ + .val = HIWORD_UPDATE(_seldsu, RK3588_CLK_DSU_DF_SRC_MASK, \ + RK3588_CLK_DSU_DF_SRC_SHIFT) | \ + HIWORD_UPDATE(_divdsu - 1, RK3588_CLK_DSU_DF_DIV_MASK, \ + RK3588_CLK_DSU_DF_DIV_SHIFT), \ +} + +#define RK3588_CORE_L_SEL2(_aclkm, _aclkmp, _aclks) \ +{ \ + .reg = RK3588_DSU_CLKSEL_CON(1), \ + .val = HIWORD_UPDATE(_aclkm - 1, RK3588_ACLKM_DSU_DIV_MASK, \ + RK3588_ACLKM_DSU_DIV_SHIFT) | \ + HIWORD_UPDATE(_aclkmp - 1, RK3588_ACLKMP_DSU_DIV_MASK, \ + RK3588_ACLKMP_DSU_DIV_SHIFT) | \ + HIWORD_UPDATE(_aclks - 1, RK3588_ACLKS_DSU_DIV_MASK, \ + RK3588_ACLKS_DSU_DIV_SHIFT), \ +} + +#define RK3588_CORE_L_SEL3(_periph) \ +{ \ + .reg = RK3588_DSU_CLKSEL_CON(2), \ + .val = HIWORD_UPDATE(_periph - 1, RK3588_PERIPH_DSU_DIV_MASK, \ + RK3588_PERIPH_DSU_DIV_SHIFT), \ +} + +#define RK3588_CORE_L_SEL4(_gicclk, _atclk) \ +{ \ + .reg = RK3588_DSU_CLKSEL_CON(3), \ + .val = HIWORD_UPDATE(_gicclk - 1, RK3588_GICCLK_DSU_DIV_MASK, \ + RK3588_GICCLK_DSU_DIV_SHIFT) | \ + HIWORD_UPDATE(_atclk - 1, RK3588_ATCLK_DSU_DIV_MASK, \ + RK3588_ATCLK_DSU_DIV_SHIFT), \ +} + +#define RK3588_CPUB01CLK_RATE(_prate, _apllcore) \ +{ \ + .prate = _prate##U, \ + .pre_muxs = { \ + RK3588_CORE_B0_SEL(0), \ + RK3588_CORE_B1_SEL(0), \ + }, \ + .post_muxs = { \ + RK3588_CORE_B0_SEL(_apllcore), \ + RK3588_CORE_B1_SEL(_apllcore), \ + }, \ +} + +#define RK3588_CPUB23CLK_RATE(_prate, _apllcore) \ +{ \ + .prate = _prate##U, \ + .pre_muxs = { \ + RK3588_CORE_B2_SEL(0), \ + RK3588_CORE_B3_SEL(0), \ + }, \ + .post_muxs = { \ + RK3588_CORE_B2_SEL(_apllcore), \ + RK3588_CORE_B3_SEL(_apllcore), \ + }, \ +} + +#define RK3588_CPULCLK_RATE(_prate, _apllcore, _seldsu, _divdsu) \ +{ \ + .prate = _prate##U, \ + .pre_muxs = { \ + RK3588_CORE_L_SEL0(0, 0), \ + RK3588_CORE_L_SEL0(1, 0), \ + RK3588_CORE_L_SEL1(3, 2), \ + RK3588_CORE_L_SEL2(2, 3, 3), \ + RK3588_CORE_L_SEL3(4), \ + RK3588_CORE_L_SEL4(4, 4), \ + }, \ + .post_muxs = { \ + RK3588_CORE_L_SEL0(0, _apllcore), \ + RK3588_CORE_L_SEL0(1, _apllcore), \ + RK3588_CORE_L_SEL1(_seldsu, _divdsu), \ + }, \ +} + +static struct rockchip_cpuclk_rate_table rk3588_cpub0clk_rates[] __initdata = { + RK3588_CPUB01CLK_RATE(2496000000, 1), + RK3588_CPUB01CLK_RATE(2400000000, 1), + RK3588_CPUB01CLK_RATE(2304000000, 1), + RK3588_CPUB01CLK_RATE(2208000000, 1), + RK3588_CPUB01CLK_RATE(2184000000, 1), + RK3588_CPUB01CLK_RATE(2088000000, 1), + RK3588_CPUB01CLK_RATE(2040000000, 1), + RK3588_CPUB01CLK_RATE(2016000000, 1), + RK3588_CPUB01CLK_RATE(1992000000, 1), + RK3588_CPUB01CLK_RATE(1896000000, 1), + RK3588_CPUB01CLK_RATE(1800000000, 1), + RK3588_CPUB01CLK_RATE(1704000000, 0), + RK3588_CPUB01CLK_RATE(1608000000, 0), + RK3588_CPUB01CLK_RATE(1584000000, 0), + RK3588_CPUB01CLK_RATE(1560000000, 0), + RK3588_CPUB01CLK_RATE(1536000000, 0), + RK3588_CPUB01CLK_RATE(1512000000, 0), + RK3588_CPUB01CLK_RATE(1488000000, 0), + RK3588_CPUB01CLK_RATE(1464000000, 0), + RK3588_CPUB01CLK_RATE(1440000000, 0), + RK3588_CPUB01CLK_RATE(1416000000, 0), + RK3588_CPUB01CLK_RATE(1392000000, 0), + RK3588_CPUB01CLK_RATE(1368000000, 0), + RK3588_CPUB01CLK_RATE(1344000000, 0), + RK3588_CPUB01CLK_RATE(1320000000, 0), + RK3588_CPUB01CLK_RATE(1296000000, 0), + RK3588_CPUB01CLK_RATE(1272000000, 0), + RK3588_CPUB01CLK_RATE(1248000000, 0), + RK3588_CPUB01CLK_RATE(1224000000, 0), + RK3588_CPUB01CLK_RATE(1200000000, 0), + RK3588_CPUB01CLK_RATE(1104000000, 0), + RK3588_CPUB01CLK_RATE(1008000000, 0), + RK3588_CPUB01CLK_RATE(912000000, 0), + RK3588_CPUB01CLK_RATE(816000000, 0), + RK3588_CPUB01CLK_RATE(696000000, 0), + RK3588_CPUB01CLK_RATE(600000000, 0), + RK3588_CPUB01CLK_RATE(408000000, 0), + RK3588_CPUB01CLK_RATE(312000000, 0), + RK3588_CPUB01CLK_RATE(216000000, 0), + RK3588_CPUB01CLK_RATE(96000000, 0), +}; + +static const struct rockchip_cpuclk_reg_data rk3588_cpub0clk_data = { + .core_reg[0] = RK3588_BIGCORE0_CLKSEL_CON(0), + .div_core_shift[0] = 8, + .div_core_mask[0] = 0x1f, + .core_reg[1] = RK3588_BIGCORE0_CLKSEL_CON(1), + .div_core_shift[1] = 0, + .div_core_mask[1] = 0x1f, + .num_cores = 2, + .mux_core_alt = 1, + .mux_core_main = 2, + .mux_core_shift = 6, + .mux_core_mask = 0x3, +}; + +static struct rockchip_cpuclk_rate_table rk3588_cpub1clk_rates[] __initdata = { + RK3588_CPUB23CLK_RATE(2496000000, 1), + RK3588_CPUB23CLK_RATE(2400000000, 1), + RK3588_CPUB23CLK_RATE(2304000000, 1), + RK3588_CPUB23CLK_RATE(2208000000, 1), + RK3588_CPUB23CLK_RATE(2184000000, 1), + RK3588_CPUB23CLK_RATE(2088000000, 1), + RK3588_CPUB23CLK_RATE(2040000000, 1), + RK3588_CPUB23CLK_RATE(2016000000, 1), + RK3588_CPUB23CLK_RATE(1992000000, 1), + RK3588_CPUB23CLK_RATE(1896000000, 1), + RK3588_CPUB23CLK_RATE(1800000000, 1), + RK3588_CPUB23CLK_RATE(1704000000, 0), + RK3588_CPUB23CLK_RATE(1608000000, 0), + RK3588_CPUB23CLK_RATE(1584000000, 0), + RK3588_CPUB23CLK_RATE(1560000000, 0), + RK3588_CPUB23CLK_RATE(1536000000, 0), + RK3588_CPUB23CLK_RATE(1512000000, 0), + RK3588_CPUB23CLK_RATE(1488000000, 0), + RK3588_CPUB23CLK_RATE(1464000000, 0), + RK3588_CPUB23CLK_RATE(1440000000, 0), + RK3588_CPUB23CLK_RATE(1416000000, 0), + RK3588_CPUB23CLK_RATE(1392000000, 0), + RK3588_CPUB23CLK_RATE(1368000000, 0), + RK3588_CPUB23CLK_RATE(1344000000, 0), + RK3588_CPUB23CLK_RATE(1320000000, 0), + RK3588_CPUB23CLK_RATE(1296000000, 0), + RK3588_CPUB23CLK_RATE(1272000000, 0), + RK3588_CPUB23CLK_RATE(1248000000, 0), + RK3588_CPUB23CLK_RATE(1224000000, 0), + RK3588_CPUB23CLK_RATE(1200000000, 0), + RK3588_CPUB23CLK_RATE(1104000000, 0), + RK3588_CPUB23CLK_RATE(1008000000, 0), + RK3588_CPUB23CLK_RATE(912000000, 0), + RK3588_CPUB23CLK_RATE(816000000, 0), + RK3588_CPUB23CLK_RATE(696000000, 0), + RK3588_CPUB23CLK_RATE(600000000, 0), + RK3588_CPUB23CLK_RATE(408000000, 0), + RK3588_CPUB23CLK_RATE(312000000, 0), + RK3588_CPUB23CLK_RATE(216000000, 0), + RK3588_CPUB23CLK_RATE(96000000, 0), +}; + +static const struct rockchip_cpuclk_reg_data rk3588_cpub1clk_data = { + .core_reg[0] = RK3588_BIGCORE1_CLKSEL_CON(0), + .div_core_shift[0] = 8, + .div_core_mask[0] = 0x1f, + .core_reg[1] = RK3588_BIGCORE1_CLKSEL_CON(1), + .div_core_shift[1] = 0, + .div_core_mask[1] = 0x1f, + .num_cores = 2, + .mux_core_alt = 1, + .mux_core_main = 2, + .mux_core_shift = 6, + .mux_core_mask = 0x3, +}; + +static struct rockchip_cpuclk_rate_table rk3588_cpulclk_rates[] __initdata = { + RK3588_CPULCLK_RATE(2208000000, 1, 3, 1), + RK3588_CPULCLK_RATE(2184000000, 1, 3, 1), + RK3588_CPULCLK_RATE(2088000000, 1, 3, 1), + RK3588_CPULCLK_RATE(2040000000, 1, 3, 1), + RK3588_CPULCLK_RATE(2016000000, 1, 3, 1), + RK3588_CPULCLK_RATE(1992000000, 1, 3, 1), + RK3588_CPULCLK_RATE(1896000000, 1, 3, 1), + RK3588_CPULCLK_RATE(1800000000, 1, 3, 1), + RK3588_CPULCLK_RATE(1704000000, 0, 3, 1), + RK3588_CPULCLK_RATE(1608000000, 0, 3, 1), + RK3588_CPULCLK_RATE(1584000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1560000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1536000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1512000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1488000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1464000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1440000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1416000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1392000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1368000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1344000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1320000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1296000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1272000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1248000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1224000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1200000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1104000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1008000000, 0, 2, 1), + RK3588_CPULCLK_RATE(912000000, 0, 2, 1), + RK3588_CPULCLK_RATE(816000000, 0, 2, 1), + RK3588_CPULCLK_RATE(696000000, 0, 2, 1), + RK3588_CPULCLK_RATE(600000000, 0, 2, 1), + RK3588_CPULCLK_RATE(408000000, 0, 2, 1), + RK3588_CPULCLK_RATE(312000000, 0, 2, 1), + RK3588_CPULCLK_RATE(216000000, 0, 2, 1), + RK3588_CPULCLK_RATE(96000000, 0, 2, 1), +}; + +static const struct rockchip_cpuclk_reg_data rk3588_cpulclk_data = { + .core_reg[0] = RK3588_DSU_CLKSEL_CON(6), + .div_core_shift[0] = 0, + .div_core_mask[0] = 0x1f, + .core_reg[1] = RK3588_DSU_CLKSEL_CON(6), + .div_core_shift[1] = 7, + .div_core_mask[1] = 0x1f, + .core_reg[2] = RK3588_DSU_CLKSEL_CON(7), + .div_core_shift[2] = 0, + .div_core_mask[2] = 0x1f, + .core_reg[3] = RK3588_DSU_CLKSEL_CON(7), + .div_core_shift[3] = 7, + .div_core_mask[3] = 0x1f, + .num_cores = 4, + .mux_core_reg = RK3588_DSU_CLKSEL_CON(5), + .mux_core_alt = 1, + .mux_core_main = 2, + .mux_core_shift = 14, + .mux_core_mask = 0x3, +}; + +PNAME(mux_pll_p) = { "xin24m", "xin32k" }; +PNAME(mux_armclkl_p) = { "xin24m", "gpll", "lpll" }; +PNAME(mux_armclkb01_p) = { "xin24m", "gpll", "b0pll",}; +PNAME(mux_armclkb23_p) = { "xin24m", "gpll", "b1pll",}; +PNAME(b0pll_b1pll_lpll_gpll_p) = { "b0pll", "b1pll", "lpll", "gpll" }; +PNAME(gpll_24m_p) = { "gpll", "xin24m" }; +PNAME(gpll_aupll_p) = { "gpll", "aupll" }; +PNAME(gpll_lpll_p) = { "gpll", "lpll" }; +PNAME(gpll_cpll_p) = { "gpll", "cpll" }; +PNAME(gpll_spll_p) = { "gpll", "spll" }; +PNAME(gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m"}; +PNAME(gpll_cpll_aupll_p) = { "gpll", "cpll", "aupll"}; +PNAME(gpll_cpll_npll_p) = { "gpll", "cpll", "npll"}; +PNAME(gpll_cpll_npll_v0pll_p) = { "gpll", "cpll", "npll", "v0pll"}; +PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" }; +PNAME(gpll_cpll_aupll_spll_p) = { "gpll", "cpll", "aupll", "spll" }; +PNAME(gpll_cpll_aupll_npll_p) = { "gpll", "cpll", "aupll", "npll" }; +PNAME(gpll_cpll_v0pll_aupll_p) = { "gpll", "cpll", "v0pll", "aupll" }; +PNAME(gpll_cpll_v0pll_spll_p) = { "gpll", "cpll", "v0pll", "spll" }; +PNAME(gpll_cpll_aupll_npll_spll_p) = { "gpll", "cpll", "aupll", "npll", "spll" }; +PNAME(gpll_cpll_dmyaupll_npll_spll_p) = { "gpll", "cpll", "dummy_aupll", "npll", "spll" }; +PNAME(gpll_cpll_npll_aupll_spll_p) = { "gpll", "cpll", "npll", "aupll", "spll" }; +PNAME(gpll_cpll_npll_1000m_p) = { "gpll", "cpll", "npll", "clk_1000m_src" }; +PNAME(mux_24m_spll_gpll_cpll_p) = { "xin24m", "spll", "gpll", "cpll" }; +PNAME(mux_24m_32k_p) = { "xin24m", "xin32k" }; +PNAME(mux_24m_100m_p) = { "xin24m", "clk_100m_src" }; +PNAME(mux_200m_100m_p) = { "clk_200m_src", "clk_100m_src" }; +PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", "xin24m" }; +PNAME(mux_150m_50m_24m_p) = { "clk_150m_src", "clk_50m_src", "xin24m" }; +PNAME(mux_150m_100m_24m_p) = { "clk_150m_src", "clk_100m_src", "xin24m" }; +PNAME(mux_200m_150m_24m_p) = { "clk_200m_src", "clk_150m_src", "xin24m" }; +PNAME(mux_150m_100m_50m_24m_p) = { "clk_150m_src", "clk_100m_src", "clk_50m_src", "xin24m" }; +PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m" }; +PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m" }; +PNAME(mux_700m_400m_200m_24m_p) = { "clk_700m_src", "clk_400m_src", "clk_200m_src", "xin24m" }; +PNAME(mux_500m_250m_100m_24m_p) = { "clk_500m_src", "clk_250m_src", "clk_100m_src", "xin24m" }; +PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin24m" }; +PNAME(mux_400m_200m_100m_24m_p) = { "clk_400m_src", "clk_200m_src", "clk_100m_src", "xin24m" }; +PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin12m" }; +PNAME(i2s2_2ch_mclkout_p) = { "mclk_i2s2_2ch", "xin12m" }; +PNAME(clk_i2s3_2ch_p) = { "clk_i2s3_2ch_src", "clk_i2s3_2ch_frac", "i2s3_mclkin", "xin12m" }; +PNAME(i2s3_2ch_mclkout_p) = { "mclk_i2s3_2ch", "xin12m" }; +PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin12m" }; +PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin12m" }; +PNAME(i2s0_8ch_mclkout_p) = { "mclk_i2s0_8ch_tx", "mclk_i2s0_8ch_rx", "xin12m" }; +PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin12m" }; +PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin12m" }; +PNAME(i2s1_8ch_mclkout_p) = { "mclk_i2s1_8ch_tx", "mclk_i2s1_8ch_rx", "xin12m" }; +PNAME(clk_i2s4_8ch_tx_p) = { "clk_i2s4_8ch_tx_src", "clk_i2s4_8ch_tx_frac", "i2s4_mclkin", "xin12m" }; +PNAME(clk_i2s5_8ch_tx_p) = { "clk_i2s5_8ch_tx_src", "clk_i2s5_8ch_tx_frac", "i2s5_mclkin", "xin12m" }; +PNAME(clk_i2s6_8ch_tx_p) = { "clk_i2s6_8ch_tx_src", "clk_i2s6_8ch_tx_frac", "i2s6_mclkin", "xin12m" }; +PNAME(clk_i2s6_8ch_rx_p) = { "clk_i2s6_8ch_rx_src", "clk_i2s6_8ch_rx_frac", "i2s6_mclkin", "xin12m" }; +PNAME(i2s6_8ch_mclkout_p) = { "mclk_i2s6_8ch_tx", "mclk_i2s6_8ch_rx", "xin12m" }; +PNAME(clk_i2s7_8ch_rx_p) = { "clk_i2s7_8ch_rx_src", "clk_i2s7_8ch_rx_frac", "i2s7_mclkin", "xin12m" }; +PNAME(clk_i2s8_8ch_tx_p) = { "clk_i2s8_8ch_tx_src", "clk_i2s8_8ch_tx_frac", "i2s8_mclkin", "xin12m" }; +PNAME(clk_i2s9_8ch_rx_p) = { "clk_i2s9_8ch_rx_src", "clk_i2s9_8ch_rx_frac", "i2s9_mclkin", "xin12m" }; +PNAME(clk_i2s10_8ch_rx_p) = { "clk_i2s10_8ch_rx_src", "clk_i2s10_8ch_rx_frac", "i2s10_mclkin", "xin12m" }; +PNAME(clk_spdif0_p) = { "clk_spdif0_src", "clk_spdif0_frac", "xin12m" }; +PNAME(clk_spdif1_p) = { "clk_spdif1_src", "clk_spdif1_frac", "xin12m" }; +PNAME(clk_spdif2_dp0_p) = { "clk_spdif2_dp0_src", "clk_spdif2_dp0_frac", "xin12m" }; +PNAME(clk_spdif3_p) = { "clk_spdif3_src", "clk_spdif3_frac", "xin12m" }; +PNAME(clk_spdif4_p) = { "clk_spdif4_src", "clk_spdif4_frac", "xin12m" }; +PNAME(clk_spdif5_dp1_p) = { "clk_spdif5_dp1_src", "clk_spdif5_dp1_frac", "xin12m" }; +PNAME(clk_uart0_p) = { "clk_uart0_src", "clk_uart0_frac", "xin24m" }; +PNAME(clk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" }; +PNAME(clk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" }; +PNAME(clk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" }; +PNAME(clk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" }; +PNAME(clk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" }; +PNAME(clk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" }; +PNAME(clk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" }; +PNAME(clk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" }; +PNAME(clk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" }; +PNAME(clk_gmac0_ptp_ref_p) = { "cpll", "clk_gmac0_ptpref_io" }; +PNAME(clk_gmac1_ptp_ref_p) = { "cpll", "clk_gmac1_ptpref_io" }; +PNAME(clk_hdmirx_aud_p) = { "clk_hdmirx_aud_src", "clk_hdmirx_aud_frac" }; +PNAME(aclk_hdcp1_root_p) = { "gpll", "cpll", "clk_hdmitrx_refsrc" }; +PNAME(aclk_vop_sub_src_p) = { "aclk_vop_root", "aclk_vop_div2_src" }; +PNAME(dclk_vop0_p) = { "dclk_vop0_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" }; +PNAME(dclk_vop1_p) = { "dclk_vop1_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" }; +PNAME(dclk_vop2_p) = { "dclk_vop2_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" }; +PNAME(pmu_200m_100m_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src" }; +PNAME(pmu_300m_24m_p) = { "clk_300m_src", "xin24m" }; +PNAME(pmu_400m_24m_p) = { "clk_400m_src", "xin24m" }; +PNAME(pmu_100m_50m_24m_src_p) = { "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" }; +PNAME(pmu_24m_32k_100m_src_p) = { "xin24m", "32k", "clk_pmu1_100m_src" }; +PNAME(hclk_pmu1_root_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" }; +PNAME(hclk_pmu_cm0_root_p) = { "clk_pmu1_400m_src", "clk_pmu1_200m_src", "clk_pmu1_100m_src", "xin24m" }; +PNAME(mclk_pdm0_p) = { "clk_pmu1_300m_src", "clk_pmu1_200m_src" }; +PNAME(mux_24m_ppll_spll_p) = { "xin24m", "ppll", "spll" }; +PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" }; +PNAME(clk_ref_pipe_phy0_p) = { "clk_ref_pipe_phy0_osc_src", "clk_ref_pipe_phy0_pll_src" }; +PNAME(clk_ref_pipe_phy1_p) = { "clk_ref_pipe_phy1_osc_src", "clk_ref_pipe_phy1_pll_src" }; +PNAME(clk_ref_pipe_phy2_p) = { "clk_ref_pipe_phy2_osc_src", "clk_ref_pipe_phy2_pll_src" }; + +#define MFLAGS CLK_MUX_HIWORD_MASK +#define DFLAGS CLK_DIVIDER_HIWORD_MASK +#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) + +static struct rockchip_clk_branch rk3588_i2s0_8ch_tx_fracmux __initdata = + MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(26), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s0_8ch_rx_fracmux __initdata = + MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(28), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s1_8ch_tx_fracmux __initdata = + MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT, + RK3588_PMU_CLKSEL_CON(7), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s1_8ch_rx_fracmux __initdata = + MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT, + RK3588_PMU_CLKSEL_CON(9), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s2_2ch_fracmux __initdata = + MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(30), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s3_2ch_fracmux __initdata = + MUX(CLK_I2S3_2CH, "clk_i2s3_2ch", clk_i2s3_2ch_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(32), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s4_8ch_tx_fracmux __initdata = + MUX(CLK_I2S4_8CH_TX, "clk_i2s4_8ch_tx", clk_i2s4_8ch_tx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(120), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s5_8ch_tx_fracmux __initdata = + MUX(CLK_I2S5_8CH_TX, "clk_i2s5_8ch_tx", clk_i2s5_8ch_tx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(142), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s6_8ch_tx_fracmux __initdata = + MUX(CLK_I2S6_8CH_TX, "clk_i2s6_8ch_tx", clk_i2s6_8ch_tx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(146), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s6_8ch_rx_fracmux __initdata = + MUX(CLK_I2S6_8CH_RX, "clk_i2s6_8ch_rx", clk_i2s6_8ch_rx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(148), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s7_8ch_rx_fracmux __initdata = + MUX(CLK_I2S7_8CH_RX, "clk_i2s7_8ch_rx", clk_i2s7_8ch_rx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(131), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s8_8ch_tx_fracmux __initdata = + MUX(CLK_I2S8_8CH_TX, "clk_i2s8_8ch_tx", clk_i2s8_8ch_tx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(122), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s9_8ch_rx_fracmux __initdata = + MUX(CLK_I2S9_8CH_RX, "clk_i2s9_8ch_rx", clk_i2s9_8ch_rx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(155), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s10_8ch_rx_fracmux __initdata = + MUX(CLK_I2S10_8CH_RX, "clk_i2s10_8ch_rx", clk_i2s10_8ch_rx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(157), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_spdif0_fracmux __initdata = + MUX(CLK_SPDIF0, "clk_spdif0", clk_spdif0_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(34), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_spdif1_fracmux __initdata = + MUX(CLK_SPDIF1, "clk_spdif1", clk_spdif1_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(36), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_spdif2_dp0_fracmux __initdata = + MUX(CLK_SPDIF2_DP0, "clk_spdif2_dp0", clk_spdif2_dp0_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(124), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_spdif3_fracmux __initdata = + MUX(CLK_SPDIF3, "clk_spdif3", clk_spdif3_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(150), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_spdif4_fracmux __initdata = + MUX(CLK_SPDIF4, "clk_spdif4", clk_spdif4_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(152), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_spdif5_dp1_fracmux __initdata = + MUX(CLK_SPDIF5_DP1, "clk_spdif5_dp1", clk_spdif5_dp1_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(126), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart0_fracmux __initdata = + MUX(CLK_UART0, "clk_uart0", clk_uart0_p, CLK_SET_RATE_PARENT, + RK3588_PMU_CLKSEL_CON(5), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart1_fracmux __initdata = + MUX(CLK_UART1, "clk_uart1", clk_uart1_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(43), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart2_fracmux __initdata = + MUX(CLK_UART2, "clk_uart2", clk_uart2_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(45), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart3_fracmux __initdata = + MUX(CLK_UART3, "clk_uart3", clk_uart3_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(47), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart4_fracmux __initdata = + MUX(CLK_UART4, "clk_uart4", clk_uart4_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(49), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart5_fracmux __initdata = + MUX(CLK_UART5, "clk_uart5", clk_uart5_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(51), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart6_fracmux __initdata = + MUX(CLK_UART6, "clk_uart6", clk_uart6_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(53), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart7_fracmux __initdata = + MUX(CLK_UART7, "clk_uart7", clk_uart7_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(55), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart8_fracmux __initdata = + MUX(CLK_UART8, "clk_uart8", clk_uart8_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(57), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart9_fracmux __initdata = + MUX(CLK_UART9, "clk_uart9", clk_uart9_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(59), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_hdmirx_aud_fracmux __initdata = + MUX(CLK_HDMIRX_AUD_P_MUX, "clk_hdmirx_aud_mux", clk_hdmirx_aud_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(140), 0, 1, MFLAGS); + +static struct rockchip_pll_clock rk3588_pll_clks[] __initdata = { + [b0pll] = PLL(pll_rk3588_core, PLL_B0PLL, "b0pll", mux_pll_p, + CLK_IGNORE_UNUSED, RK3588_B0_PLL_CON(0), + RK3588_B0_PLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates), + [b1pll] = PLL(pll_rk3588_core, PLL_B1PLL, "b1pll", mux_pll_p, + CLK_IGNORE_UNUSED, RK3588_B1_PLL_CON(8), + RK3588_B1_PLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates), + [lpll] = PLL(pll_rk3588_core, PLL_LPLL, "lpll", mux_pll_p, + CLK_IGNORE_UNUSED, RK3588_LPLL_CON(16), + RK3588_LPLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates), + [v0pll] = PLL(pll_rk3588, PLL_V0PLL, "v0pll", mux_pll_p, + 0, RK3588_PLL_CON(88), + RK3588_MODE_CON0, 4, 15, 0, rk3588_pll_rates), + [aupll] = PLL(pll_rk3588, PLL_AUPLL, "aupll", mux_pll_p, + 0, RK3588_PLL_CON(96), + RK3588_MODE_CON0, 6, 15, 0, rk3588_pll_rates), + [cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p, + CLK_IGNORE_UNUSED, RK3588_PLL_CON(104), + RK3588_MODE_CON0, 8, 15, 0, rk3588_pll_rates), + [gpll] = PLL(pll_rk3588, PLL_GPLL, "gpll", mux_pll_p, + CLK_IGNORE_UNUSED, RK3588_PLL_CON(112), + RK3588_MODE_CON0, 2, 15, 0, rk3588_pll_rates), + [npll] = PLL(pll_rk3588, PLL_NPLL, "npll", mux_pll_p, + 0, RK3588_PLL_CON(120), + RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates), + [ppll] = PLL(pll_rk3588_core, PLL_PPLL, "ppll", mux_pll_p, + CLK_IGNORE_UNUSED, RK3588_PMU_PLL_CON(128), + RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates), +}; + +static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { + /* + * CRU Clock-Architecture + */ + /* fixed */ + FACTOR(0, "xin12m", "xin24m", 0, 1, 2), + + /* top */ + COMPOSITE(CLK_50M_SRC, "clk_50m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 0, GFLAGS), + COMPOSITE(CLK_100M_SRC, "clk_100m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 1, GFLAGS), + COMPOSITE(CLK_150M_SRC, "clk_150m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 2, GFLAGS), + COMPOSITE(CLK_200M_SRC, "clk_200m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 3, GFLAGS), + COMPOSITE(CLK_250M_SRC, "clk_250m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 4, GFLAGS), + COMPOSITE(CLK_300M_SRC, "clk_300m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 5, GFLAGS), + COMPOSITE(CLK_350M_SRC, "clk_350m_src", gpll_spll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(3), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 6, GFLAGS), + COMPOSITE(CLK_400M_SRC, "clk_400m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 7, GFLAGS), + COMPOSITE_HALFDIV(CLK_450M_SRC, "clk_450m_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(4), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 8, GFLAGS), + COMPOSITE(CLK_500M_SRC, "clk_500m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 9, GFLAGS), + COMPOSITE(CLK_600M_SRC, "clk_600m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 10, GFLAGS), + COMPOSITE(CLK_650M_SRC, "clk_650m_src", gpll_lpll_p, 0, + RK3588_CLKSEL_CON(5), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 11, GFLAGS), + COMPOSITE(CLK_700M_SRC, "clk_700m_src", gpll_spll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(6), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 12, GFLAGS), + COMPOSITE(CLK_800M_SRC, "clk_800m_src", gpll_aupll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(6), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 13, GFLAGS), + COMPOSITE_HALFDIV(CLK_1000M_SRC, "clk_1000m_src", gpll_cpll_npll_v0pll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(7), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 14, GFLAGS), + COMPOSITE(CLK_1200M_SRC, "clk_1200m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(7), 12, 1, MFLAGS, 7, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 15, GFLAGS), + COMPOSITE_NODIV(ACLK_TOP_M300_ROOT, "aclk_top_m300_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(9), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(1), 10, GFLAGS), + COMPOSITE_NODIV(ACLK_TOP_M500_ROOT, "aclk_top_m500_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(9), 2, 2, MFLAGS, + RK3588_CLKGATE_CON(1), 11, GFLAGS), + COMPOSITE_NODIV(ACLK_TOP_M400_ROOT, "aclk_top_m400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(9), 4, 2, MFLAGS, + RK3588_CLKGATE_CON(1), 12, GFLAGS), + COMPOSITE_NODIV(ACLK_TOP_S200_ROOT, "aclk_top_s200_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(9), 6, 2, MFLAGS, + RK3588_CLKGATE_CON(1), 13, GFLAGS), + COMPOSITE_NODIV(ACLK_TOP_S400_ROOT, "aclk_top_s400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(9), 8, 2, MFLAGS, + RK3588_CLKGATE_CON(1), 14, GFLAGS), + COMPOSITE(ACLK_TOP_ROOT, "aclk_top_root", gpll_cpll_aupll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(8), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(1), 0, GFLAGS), + COMPOSITE_NODIV(PCLK_TOP_ROOT, "pclk_top_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(8), 7, 2, MFLAGS, + RK3588_CLKGATE_CON(1), 1, GFLAGS), + COMPOSITE(ACLK_LOW_TOP_ROOT, "aclk_low_top_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(8), 14, 1, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(1), 2, GFLAGS), + COMPOSITE(CLK_MIPI_CAMARAOUT_M0, "clk_mipi_camaraout_m0", mux_24m_spll_gpll_cpll_p, 0, + RK3588_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(5), 9, GFLAGS), + COMPOSITE(CLK_MIPI_CAMARAOUT_M1, "clk_mipi_camaraout_m1", mux_24m_spll_gpll_cpll_p, 0, + RK3588_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(5), 10, GFLAGS), + COMPOSITE(CLK_MIPI_CAMARAOUT_M2, "clk_mipi_camaraout_m2", mux_24m_spll_gpll_cpll_p, 0, + RK3588_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(5), 11, GFLAGS), + COMPOSITE(CLK_MIPI_CAMARAOUT_M3, "clk_mipi_camaraout_m3", mux_24m_spll_gpll_cpll_p, 0, + RK3588_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(5), 12, GFLAGS), + COMPOSITE(CLK_MIPI_CAMARAOUT_M4, "clk_mipi_camaraout_m4", mux_24m_spll_gpll_cpll_p, 0, + RK3588_CLKSEL_CON(22), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(5), 13, GFLAGS), + COMPOSITE(MCLK_GMAC0_OUT, "mclk_gmac0_out", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(15), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(5), 3, GFLAGS), + COMPOSITE(REFCLKO25M_ETH0_OUT, "refclko25m_eth0_out", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(15), 15, 1, MFLAGS, 8, 7, DFLAGS, + RK3588_CLKGATE_CON(5), 4, GFLAGS), + COMPOSITE(REFCLKO25M_ETH1_OUT, "refclko25m_eth1_out", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(16), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(5), 5, GFLAGS), + COMPOSITE(CLK_CIFOUT_OUT, "clk_cifout_out", gpll_cpll_24m_spll_p, 0, + RK3588_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(5), 6, GFLAGS), + GATE(PCLK_MIPI_DCPHY0, "pclk_mipi_dcphy0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(3), 14, GFLAGS), + GATE(PCLK_MIPI_DCPHY1, "pclk_mipi_dcphy1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(4), 3, GFLAGS), + GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(1), 6, GFLAGS), + GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(1), 8, GFLAGS), + GATE(PCLK_CRU, "pclk_cru", "pclk_top_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(5), 0, GFLAGS), + + /* bigcore0 */ + COMPOSITE_NODIV(PCLK_BIGCORE0_ROOT, "pclk_bigcore0_root", mux_100m_50m_24m_p, + CLK_IS_CRITICAL, + RK3588_BIGCORE0_CLKSEL_CON(2), 0, 2, MFLAGS, + RK3588_BIGCORE0_CLKGATE_CON(0), 14, GFLAGS), + GATE(PCLK_BIGCORE0_PVTM, "pclk_bigcore0_pvtm", "pclk_bigcore0_root", 0, + RK3588_BIGCORE0_CLKGATE_CON(1), 0, GFLAGS), + GATE(CLK_BIGCORE0_PVTM, "clk_bigcore0_pvtm", "xin24m", 0, + RK3588_BIGCORE0_CLKGATE_CON(0), 12, GFLAGS), + GATE(CLK_CORE_BIGCORE0_PVTM, "clk_core_bigcore0_pvtm", "armclk_b01", 0, + RK3588_BIGCORE0_CLKGATE_CON(0), 13, GFLAGS), + + /* bigcore1 */ + COMPOSITE_NODIV(PCLK_BIGCORE1_ROOT, "pclk_bigcore1_root", mux_100m_50m_24m_p, + CLK_IS_CRITICAL, + RK3588_BIGCORE1_CLKSEL_CON(2), 0, 2, MFLAGS, + RK3588_BIGCORE1_CLKGATE_CON(0), 14, GFLAGS), + GATE(PCLK_BIGCORE1_PVTM, "pclk_bigcore1_pvtm", "pclk_bigcore1_root", 0, + RK3588_BIGCORE1_CLKGATE_CON(1), 0, GFLAGS), + GATE(CLK_BIGCORE1_PVTM, "clk_bigcore1_pvtm", "xin24m", 0, + RK3588_BIGCORE1_CLKGATE_CON(0), 12, GFLAGS), + GATE(CLK_CORE_BIGCORE1_PVTM, "clk_core_bigcore1_pvtm", "armclk_b23", 0, + RK3588_BIGCORE1_CLKGATE_CON(0), 13, GFLAGS), + + /* dsu */ + COMPOSITE(0, "sclk_dsu", b0pll_b1pll_lpll_gpll_p, CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(0), 12, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_DSU_CLKGATE_CON(0), 4, GFLAGS), + COMPOSITE_NOMUX(0, "atclk_dsu", "sclk_dsu", CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3588_DSU_CLKGATE_CON(1), 0, GFLAGS), + COMPOSITE_NOMUX(0, "gicclk_dsu", "sclk_dsu", CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(3), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3588_DSU_CLKGATE_CON(1), 1, GFLAGS), + COMPOSITE_NOMUX(0, "aclkmp_dsu", "sclk_dsu", CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(1), 11, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3588_DSU_CLKGATE_CON(0), 12, GFLAGS), + COMPOSITE_NOMUX(0, "aclkm_dsu", "sclk_dsu", CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(1), 1, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3588_DSU_CLKGATE_CON(0), 8, GFLAGS), + COMPOSITE_NOMUX(0, "aclks_dsu", "sclk_dsu", CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(1), 6, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3588_DSU_CLKGATE_CON(0), 9, GFLAGS), + COMPOSITE_NOMUX(0, "periph_dsu", "sclk_dsu", CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(2), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3588_DSU_CLKGATE_CON(0), 13, GFLAGS), + COMPOSITE_NOMUX(0, "cntclk_dsu", "periph_dsu", CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(2), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3588_DSU_CLKGATE_CON(0), 14, GFLAGS), + COMPOSITE_NOMUX(0, "tsclk_dsu", "periph_dsu", CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(2), 10, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3588_DSU_CLKGATE_CON(0), 15, GFLAGS), + COMPOSITE_NODIV(PCLK_DSU_S_ROOT, "pclk_dsu_s_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(4), 11, 2, MFLAGS, + RK3588_DSU_CLKGATE_CON(2), 2, GFLAGS), + COMPOSITE(PCLK_DSU_ROOT, "pclk_dsu_root", b0pll_b1pll_lpll_gpll_p, CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(4), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_DSU_CLKGATE_CON(1), 3, GFLAGS), + COMPOSITE_NODIV(PCLK_DSU_NS_ROOT, "pclk_dsu_ns_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(4), 7, 2, MFLAGS, + RK3588_DSU_CLKGATE_CON(1), 4, GFLAGS), + GATE(PCLK_LITCORE_PVTM, "pclk_litcore_pvtm", "pclk_dsu_ns_root", 0, + RK3588_DSU_CLKGATE_CON(2), 6, GFLAGS), + GATE(PCLK_DBG, "pclk_dbg", "pclk_dsu_root", CLK_IS_CRITICAL, + RK3588_DSU_CLKGATE_CON(1), 7, GFLAGS), + GATE(PCLK_DSU, "pclk_dsu", "pclk_dsu_root", CLK_IS_CRITICAL, + RK3588_DSU_CLKGATE_CON(1), 6, GFLAGS), + GATE(PCLK_S_DAPLITE, "pclk_s_daplite", "pclk_dsu_ns_root", CLK_IGNORE_UNUSED, + RK3588_DSU_CLKGATE_CON(1), 8, GFLAGS), + GATE(PCLK_M_DAPLITE, "pclk_m_daplite", "pclk_dsu_root", CLK_IGNORE_UNUSED, + RK3588_DSU_CLKGATE_CON(1), 9, GFLAGS), + GATE(CLK_LITCORE_PVTM, "clk_litcore_pvtm", "xin24m", 0, + RK3588_DSU_CLKGATE_CON(2), 0, GFLAGS), + GATE(CLK_CORE_LITCORE_PVTM, "clk_core_litcore_pvtm", "armclk_l", 0, + RK3588_DSU_CLKGATE_CON(2), 1, GFLAGS), + + /* audio */ + COMPOSITE_NODIV(HCLK_AUDIO_ROOT, "hclk_audio_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(24), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(7), 0, GFLAGS), + COMPOSITE_NODIV(PCLK_AUDIO_ROOT, "pclk_audio_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(24), 2, 2, MFLAGS, + RK3588_CLKGATE_CON(7), 1, GFLAGS), + GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_audio_root", 0, + RK3588_CLKGATE_CON(7), 12, GFLAGS), + GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_audio_root", 0, + RK3588_CLKGATE_CON(7), 13, GFLAGS), + COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(28), 9, 1, MFLAGS, 4, 5, DFLAGS, + RK3588_CLKGATE_CON(7), 14, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(29), 0, + RK3588_CLKGATE_CON(7), 15, GFLAGS, + &rk3588_i2s2_2ch_fracmux), + GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0, + RK3588_CLKGATE_CON(8), 0, GFLAGS), + MUX(I2S2_2CH_MCLKOUT, "i2s2_2ch_mclkout", i2s2_2ch_mclkout_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(30), 2, 1, MFLAGS), + + COMPOSITE(CLK_I2S3_2CH_SRC, "clk_i2s3_2ch_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(30), 8, 1, MFLAGS, 3, 5, DFLAGS, + RK3588_CLKGATE_CON(8), 1, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S3_2CH_FRAC, "clk_i2s3_2ch_frac", "clk_i2s3_2ch_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(31), 0, + RK3588_CLKGATE_CON(8), 2, GFLAGS, + &rk3588_i2s3_2ch_fracmux), + GATE(MCLK_I2S3_2CH, "mclk_i2s3_2ch", "clk_i2s3_2ch", 0, + RK3588_CLKGATE_CON(8), 3, GFLAGS), + GATE(CLK_DAC_ACDCDIG, "clk_dac_acdcdig", "mclk_i2s3_2ch", 0, + RK3588_CLKGATE_CON(8), 4, GFLAGS), + MUX(I2S3_2CH_MCLKOUT, "i2s3_2ch_mclkout", i2s3_2ch_mclkout_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(32), 2, 1, MFLAGS), + GATE(PCLK_ACDCDIG, "pclk_acdcdig", "pclk_audio_root", 0, + RK3588_CLKGATE_CON(7), 11, GFLAGS), + GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio_root", 0, + RK3588_CLKGATE_CON(7), 4, GFLAGS), + + COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(24), 9, 1, MFLAGS, 4, 5, DFLAGS, + RK3588_CLKGATE_CON(7), 5, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(25), 0, + RK3588_CLKGATE_CON(7), 6, GFLAGS, + &rk3588_i2s0_8ch_tx_fracmux), + GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0, + RK3588_CLKGATE_CON(7), 7, GFLAGS), + + COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(26), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(7), 8, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(27), 0, + RK3588_CLKGATE_CON(7), 9, GFLAGS, + &rk3588_i2s0_8ch_rx_fracmux), + GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0, + RK3588_CLKGATE_CON(7), 10, GFLAGS), + MUX(I2S0_8CH_MCLKOUT, "i2s0_8ch_mclkout", i2s0_8ch_mclkout_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(28), 2, 2, MFLAGS), + + GATE(HCLK_PDM1, "hclk_pdm1", "hclk_audio_root", 0, + RK3588_CLKGATE_CON(9), 6, GFLAGS), + COMPOSITE(MCLK_PDM1, "mclk_pdm1", gpll_cpll_aupll_p, 0, + RK3588_CLKSEL_CON(36), 7, 2, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(9), 7, GFLAGS), + + GATE(HCLK_SPDIF0, "hclk_spdif0", "hclk_audio_root", 0, + RK3588_CLKGATE_CON(8), 14, GFLAGS), + COMPOSITE(CLK_SPDIF0_SRC, "clk_spdif0_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(32), 8, 1, MFLAGS, 3, 5, DFLAGS, + RK3588_CLKGATE_CON(8), 15, GFLAGS), + COMPOSITE_FRACMUX(CLK_SPDIF0_FRAC, "clk_spdif0_frac", "clk_spdif0_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(33), 0, + RK3588_CLKGATE_CON(9), 0, GFLAGS, + &rk3588_spdif0_fracmux), + GATE(MCLK_SPDIF0, "mclk_spdif0", "clk_spdif0", 0, + RK3588_CLKGATE_CON(9), 1, GFLAGS), + + GATE(HCLK_SPDIF1, "hclk_spdif1", "hclk_audio_root", 0, + RK3588_CLKGATE_CON(9), 2, GFLAGS), + COMPOSITE(CLK_SPDIF1_SRC, "clk_spdif1_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(34), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(9), 3, GFLAGS), + COMPOSITE_FRACMUX(CLK_SPDIF1_FRAC, "clk_spdif1_frac", "clk_spdif1_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(35), 0, + RK3588_CLKGATE_CON(9), 4, GFLAGS, + &rk3588_spdif1_fracmux), + GATE(MCLK_SPDIF1, "mclk_spdif1", "clk_spdif1", 0, + RK3588_CLKGATE_CON(9), 5, GFLAGS), + + COMPOSITE(ACLK_AV1_ROOT, "aclk_av1_root", gpll_cpll_aupll_p, 0, + RK3588_CLKSEL_CON(163), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(68), 0, GFLAGS), + COMPOSITE_NODIV(PCLK_AV1_ROOT, "pclk_av1_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(163), 7, 2, MFLAGS, + RK3588_CLKGATE_CON(68), 3, GFLAGS), + + /* bus */ + COMPOSITE(ACLK_BUS_ROOT, "aclk_bus_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(10), 0, GFLAGS), + + GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(16), 11, GFLAGS), + GATE(PCLK_MAILBOX1, "pclk_mailbox1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(16), 12, GFLAGS), + GATE(PCLK_MAILBOX2, "pclk_mailbox2", "pclk_top_root", 0, + RK3588_CLKGATE_CON(16), 13, GFLAGS), + GATE(PCLK_PMU2, "pclk_pmu2", "pclk_top_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(19), 3, GFLAGS), + GATE(PCLK_PMUCM0_INTMUX, "pclk_pmucm0_intmux", "pclk_top_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(19), 4, GFLAGS), + GATE(PCLK_DDRCM0_INTMUX, "pclk_ddrcm0_intmux", "pclk_top_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(19), 5, GFLAGS), + + GATE(PCLK_PWM1, "pclk_pwm1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(15), 3, GFLAGS), + COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(59), 12, 2, MFLAGS, + RK3588_CLKGATE_CON(15), 4, GFLAGS), + GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0, + RK3588_CLKGATE_CON(15), 5, GFLAGS), + GATE(PCLK_PWM2, "pclk_pwm2", "pclk_top_root", 0, + RK3588_CLKGATE_CON(15), 6, GFLAGS), + COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(59), 14, 2, MFLAGS, + RK3588_CLKGATE_CON(15), 7, GFLAGS), + GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0, + RK3588_CLKGATE_CON(15), 8, GFLAGS), + GATE(PCLK_PWM3, "pclk_pwm3", "pclk_top_root", 0, + RK3588_CLKGATE_CON(15), 9, GFLAGS), + COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(60), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(15), 10, GFLAGS), + GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0, + RK3588_CLKGATE_CON(15), 11, GFLAGS), + + GATE(PCLK_BUSTIMER0, "pclk_bustimer0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(15), 12, GFLAGS), + GATE(PCLK_BUSTIMER1, "pclk_bustimer1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(15), 13, GFLAGS), + COMPOSITE_NODIV(CLK_BUS_TIMER_ROOT, "clk_bus_timer_root", mux_24m_100m_p, 0, + RK3588_CLKSEL_CON(60), 2, 1, MFLAGS, + RK3588_CLKGATE_CON(15), 14, GFLAGS), + GATE(CLK_BUSTIMER0, "clk_bustimer0", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(15), 15, GFLAGS), + GATE(CLK_BUSTIMER1, "clk_bustimer1", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 0, GFLAGS), + GATE(CLK_BUSTIMER2, "clk_bustimer2", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 1, GFLAGS), + GATE(CLK_BUSTIMER3, "clk_bustimer3", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 2, GFLAGS), + GATE(CLK_BUSTIMER4, "clk_bustimer4", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 3, GFLAGS), + GATE(CLK_BUSTIMER5, "clk_bustimer5", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 4, GFLAGS), + GATE(CLK_BUSTIMER6, "clk_bustimer6", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 5, GFLAGS), + GATE(CLK_BUSTIMER7, "clk_bustimer7", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 6, GFLAGS), + GATE(CLK_BUSTIMER8, "clk_bustimer8", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 7, GFLAGS), + GATE(CLK_BUSTIMER9, "clk_bustimer9", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 8, GFLAGS), + GATE(CLK_BUSTIMER10, "clk_bustimer10", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 9, GFLAGS), + GATE(CLK_BUSTIMER11, "clk_bustimer11", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 10, GFLAGS), + + GATE(PCLK_WDT0, "pclk_wdt0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(15), 0, GFLAGS), + GATE(TCLK_WDT0, "tclk_wdt0", "xin24m", 0, + RK3588_CLKGATE_CON(15), 1, GFLAGS), + + GATE(PCLK_CAN0, "pclk_can0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(11), 8, GFLAGS), + COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(39), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(11), 9, GFLAGS), + GATE(PCLK_CAN1, "pclk_can1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(11), 10, GFLAGS), + COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(39), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(11), 11, GFLAGS), + GATE(PCLK_CAN2, "pclk_can2", "pclk_top_root", 0, + RK3588_CLKGATE_CON(11), 12, GFLAGS), + COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(40), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(11), 13, GFLAGS), + + GATE(ACLK_DECOM, "aclk_decom", "aclk_bus_root", 0, + RK3588_CLKGATE_CON(17), 6, GFLAGS), + GATE(PCLK_DECOM, "pclk_decom", "pclk_top_root", 0, + RK3588_CLKGATE_CON(17), 7, GFLAGS), + COMPOSITE(DCLK_DECOM, "dclk_decom", gpll_spll_p, 0, + RK3588_CLKSEL_CON(62), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(17), 8, GFLAGS), + GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus_root", 0, + RK3588_CLKGATE_CON(10), 5, GFLAGS), + GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus_root", 0, + RK3588_CLKGATE_CON(10), 6, GFLAGS), + GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_bus_root", 0, + RK3588_CLKGATE_CON(10), 7, GFLAGS), + GATE(ACLK_GIC, "aclk_gic", "aclk_bus_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(10), 3, GFLAGS), + + GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(16), 14, GFLAGS), + COMPOSITE(DBCLK_GPIO1, "dbclk_gpio1", mux_24m_32k_p, 0, + RK3588_CLKSEL_CON(60), 8, 1, MFLAGS, 3, 5, DFLAGS, + RK3588_CLKGATE_CON(16), 15, GFLAGS), + GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_top_root", 0, + RK3588_CLKGATE_CON(17), 0, GFLAGS), + COMPOSITE(DBCLK_GPIO2, "dbclk_gpio2", mux_24m_32k_p, 0, + RK3588_CLKSEL_CON(60), 14, 1, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(17), 1, GFLAGS), + GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_top_root", 0, + RK3588_CLKGATE_CON(17), 2, GFLAGS), + COMPOSITE(DBCLK_GPIO3, "dbclk_gpio3", mux_24m_32k_p, 0, + RK3588_CLKSEL_CON(61), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(17), 3, GFLAGS), + GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_top_root", 0, + RK3588_CLKGATE_CON(17), 4, GFLAGS), + COMPOSITE(DBCLK_GPIO4, "dbclk_gpio4", mux_24m_32k_p, 0, + RK3588_CLKSEL_CON(61), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(17), 5, GFLAGS), + + GATE(PCLK_I2C1, "pclk_i2c1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(10), 8, GFLAGS), + GATE(PCLK_I2C2, "pclk_i2c2", "pclk_top_root", 0, + RK3588_CLKGATE_CON(10), 9, GFLAGS), + GATE(PCLK_I2C3, "pclk_i2c3", "pclk_top_root", 0, + RK3588_CLKGATE_CON(10), 10, GFLAGS), + GATE(PCLK_I2C4, "pclk_i2c4", "pclk_top_root", 0, + RK3588_CLKGATE_CON(10), 11, GFLAGS), + GATE(PCLK_I2C5, "pclk_i2c5", "pclk_top_root", 0, + RK3588_CLKGATE_CON(10), 12, GFLAGS), + GATE(PCLK_I2C6, "pclk_i2c6", "pclk_top_root", 0, + RK3588_CLKGATE_CON(10), 13, GFLAGS), + GATE(PCLK_I2C7, "pclk_i2c7", "pclk_top_root", 0, + RK3588_CLKGATE_CON(10), 14, GFLAGS), + GATE(PCLK_I2C8, "pclk_i2c8", "pclk_top_root", 0, + RK3588_CLKGATE_CON(10), 15, GFLAGS), + COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_p, 0, + RK3588_CLKSEL_CON(38), 6, 1, MFLAGS, + RK3588_CLKGATE_CON(11), 0, GFLAGS), + COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", mux_200m_100m_p, 0, + RK3588_CLKSEL_CON(38), 7, 1, MFLAGS, + RK3588_CLKGATE_CON(11), 1, GFLAGS), + COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_p, 0, + RK3588_CLKSEL_CON(38), 8, 1, MFLAGS, + RK3588_CLKGATE_CON(11), 2, GFLAGS), + COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_p, 0, + RK3588_CLKSEL_CON(38), 9, 1, MFLAGS, + RK3588_CLKGATE_CON(11), 3, GFLAGS), + COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_p, 0, + RK3588_CLKSEL_CON(38), 10, 1, MFLAGS, + RK3588_CLKGATE_CON(11), 4, GFLAGS), + COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_p, 0, + RK3588_CLKSEL_CON(38), 11, 1, MFLAGS, + RK3588_CLKGATE_CON(11), 5, GFLAGS), + COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_p, 0, + RK3588_CLKSEL_CON(38), 12, 1, MFLAGS, + RK3588_CLKGATE_CON(11), 6, GFLAGS), + COMPOSITE_NODIV(CLK_I2C8, "clk_i2c8", mux_200m_100m_p, 0, + RK3588_CLKSEL_CON(38), 13, 1, MFLAGS, + RK3588_CLKGATE_CON(11), 7, GFLAGS), + + GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_top_root", 0, + RK3588_CLKGATE_CON(18), 9, GFLAGS), + GATE(CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 0, + RK3588_CLKGATE_CON(18), 10, GFLAGS), + GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0, + RK3588_CLKGATE_CON(18), 11, GFLAGS), + GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0, + RK3588_CLKGATE_CON(18), 13, GFLAGS), + GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0, + RK3588_CLKGATE_CON(18), 12, GFLAGS), + + GATE(PCLK_SARADC, "pclk_saradc", "pclk_top_root", 0, + RK3588_CLKGATE_CON(11), 14, GFLAGS), + COMPOSITE(CLK_SARADC, "clk_saradc", gpll_24m_p, 0, + RK3588_CLKSEL_CON(40), 14, 1, MFLAGS, 6, 8, DFLAGS, + RK3588_CLKGATE_CON(11), 15, GFLAGS), + + GATE(PCLK_SPI0, "pclk_spi0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(14), 6, GFLAGS), + GATE(PCLK_SPI1, "pclk_spi1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(14), 7, GFLAGS), + GATE(PCLK_SPI2, "pclk_spi2", "pclk_top_root", 0, + RK3588_CLKGATE_CON(14), 8, GFLAGS), + GATE(PCLK_SPI3, "pclk_spi3", "pclk_top_root", 0, + RK3588_CLKGATE_CON(14), 9, GFLAGS), + GATE(PCLK_SPI4, "pclk_spi4", "pclk_top_root", 0, + RK3588_CLKGATE_CON(14), 10, GFLAGS), + COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_150m_24m_p, 0, + RK3588_CLKSEL_CON(59), 2, 2, MFLAGS, + RK3588_CLKGATE_CON(14), 11, GFLAGS), + COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_150m_24m_p, 0, + RK3588_CLKSEL_CON(59), 4, 2, MFLAGS, + RK3588_CLKGATE_CON(14), 12, GFLAGS), + COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_150m_24m_p, 0, + RK3588_CLKSEL_CON(59), 6, 2, MFLAGS, + RK3588_CLKGATE_CON(14), 13, GFLAGS), + COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", mux_200m_150m_24m_p, 0, + RK3588_CLKSEL_CON(59), 8, 2, MFLAGS, + RK3588_CLKGATE_CON(14), 14, GFLAGS), + COMPOSITE_NODIV(CLK_SPI4, "clk_spi4", mux_200m_150m_24m_p, 0, + RK3588_CLKSEL_CON(59), 10, 2, MFLAGS, + RK3588_CLKGATE_CON(14), 15, GFLAGS), + + GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(18), 6, GFLAGS), + GATE(PCLK_TSADC, "pclk_tsadc", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 0, GFLAGS), + COMPOSITE(CLK_TSADC, "clk_tsadc", gpll_24m_p, 0, + RK3588_CLKSEL_CON(41), 8, 1, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(12), 1, GFLAGS), + + GATE(PCLK_UART1, "pclk_uart1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 2, GFLAGS), + GATE(PCLK_UART2, "pclk_uart2", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 3, GFLAGS), + GATE(PCLK_UART3, "pclk_uart3", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 4, GFLAGS), + GATE(PCLK_UART4, "pclk_uart4", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 5, GFLAGS), + GATE(PCLK_UART5, "pclk_uart5", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 6, GFLAGS), + GATE(PCLK_UART6, "pclk_uart6", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 7, GFLAGS), + GATE(PCLK_UART7, "pclk_uart7", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 8, GFLAGS), + GATE(PCLK_UART8, "pclk_uart8", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 9, GFLAGS), + GATE(PCLK_UART9, "pclk_uart9", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 10, GFLAGS), + + COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(41), 14, 1, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(12), 11, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(42), 0, + RK3588_CLKGATE_CON(12), 12, GFLAGS, + &rk3588_uart1_fracmux), + GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0, + RK3588_CLKGATE_CON(12), 13, GFLAGS), + COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(43), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(12), 14, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(44), 0, + RK3588_CLKGATE_CON(12), 15, GFLAGS, + &rk3588_uart2_fracmux), + GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0, + RK3588_CLKGATE_CON(13), 0, GFLAGS), + COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(45), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(13), 1, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(46), 0, + RK3588_CLKGATE_CON(13), 2, GFLAGS, + &rk3588_uart3_fracmux), + GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0, + RK3588_CLKGATE_CON(13), 3, GFLAGS), + COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(47), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(13), 4, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(48), 0, + RK3588_CLKGATE_CON(13), 5, GFLAGS, + &rk3588_uart4_fracmux), + GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0, + RK3588_CLKGATE_CON(13), 6, GFLAGS), + COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(49), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(13), 7, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(50), 0, + RK3588_CLKGATE_CON(13), 8, GFLAGS, + &rk3588_uart5_fracmux), + GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0, + RK3588_CLKGATE_CON(13), 9, GFLAGS), + COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(51), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(13), 10, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(52), 0, + RK3588_CLKGATE_CON(13), 11, GFLAGS, + &rk3588_uart6_fracmux), + GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0, + RK3588_CLKGATE_CON(13), 12, GFLAGS), + COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(53), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(13), 13, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(54), 0, + RK3588_CLKGATE_CON(13), 14, GFLAGS, + &rk3588_uart7_fracmux), + GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0, + RK3588_CLKGATE_CON(13), 15, GFLAGS), + COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(55), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(14), 0, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(56), 0, + RK3588_CLKGATE_CON(14), 1, GFLAGS, + &rk3588_uart8_fracmux), + GATE(SCLK_UART8, "sclk_uart8", "clk_uart8", 0, + RK3588_CLKGATE_CON(14), 2, GFLAGS), + COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(57), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(14), 3, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(58), 0, + RK3588_CLKGATE_CON(14), 4, GFLAGS, + &rk3588_uart9_fracmux), + GATE(SCLK_UART9, "sclk_uart9", "clk_uart9", 0, + RK3588_CLKGATE_CON(14), 5, GFLAGS), + + /* center */ + COMPOSITE_NODIV(ACLK_CENTER_ROOT, "aclk_center_root", mux_700m_400m_200m_24m_p, + CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(165), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(69), 0, GFLAGS), + COMPOSITE_NODIV(ACLK_CENTER_LOW_ROOT, "aclk_center_low_root", mux_500m_250m_100m_24m_p, + CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(165), 2, 2, MFLAGS, + RK3588_CLKGATE_CON(69), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_CENTER_ROOT, "hclk_center_root", mux_400m_200m_100m_24m_p, + CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(165), 4, 2, MFLAGS, + RK3588_CLKGATE_CON(69), 2, GFLAGS), + COMPOSITE_NODIV(PCLK_CENTER_ROOT, "pclk_center_root", mux_200m_100m_50m_24m_p, + CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(165), 6, 2, MFLAGS | CLK_MUX_READ_ONLY, + RK3588_CLKGATE_CON(69), 3, GFLAGS), + GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_center_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(69), 5, GFLAGS), + GATE(ACLK_DDR_SHAREMEM, "aclk_ddr_sharemem", "aclk_center_low_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(69), 6, GFLAGS), + COMPOSITE_NODIV(ACLK_CENTER_S200_ROOT, "aclk_center_s200_root", mux_200m_100m_50m_24m_p, + CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(165), 8, 2, MFLAGS, + RK3588_CLKGATE_CON(69), 8, GFLAGS), + COMPOSITE_NODIV(ACLK_CENTER_S400_ROOT, "aclk_center_s400_root", mux_400m_200m_100m_24m_p, + CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(165), 10, 2, MFLAGS, + RK3588_CLKGATE_CON(69), 9, GFLAGS), + GATE(FCLK_DDR_CM0_CORE, "fclk_ddr_cm0_core", "hclk_center_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(69), 14, GFLAGS), + COMPOSITE_NODIV(CLK_DDR_TIMER_ROOT, "clk_ddr_timer_root", mux_24m_100m_p, CLK_IGNORE_UNUSED, + RK3588_CLKSEL_CON(165), 12, 1, MFLAGS, + RK3588_CLKGATE_CON(69), 15, GFLAGS), + GATE(CLK_DDR_TIMER0, "clk_ddr_timer0", "clk_ddr_timer_root", 0, + RK3588_CLKGATE_CON(70), 0, GFLAGS), + GATE(CLK_DDR_TIMER1, "clk_ddr_timer1", "clk_ddr_timer_root", 0, + RK3588_CLKGATE_CON(70), 1, GFLAGS), + GATE(TCLK_WDT_DDR, "tclk_wdt_ddr", "xin24m", 0, + RK3588_CLKGATE_CON(70), 2, GFLAGS), + COMPOSITE(CLK_DDR_CM0_RTC, "clk_ddr_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(166), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(70), 4, GFLAGS), + GATE(PCLK_WDT, "pclk_wdt", "pclk_center_root", 0, + RK3588_CLKGATE_CON(70), 7, GFLAGS), + GATE(PCLK_TIMER, "pclk_timer", "pclk_center_root", 0, + RK3588_CLKGATE_CON(70), 8, GFLAGS), + GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_center_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(70), 9, GFLAGS), + GATE(PCLK_SHAREMEM, "pclk_sharemem", "pclk_center_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(70), 10, GFLAGS), + + /* gpu */ + COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", gpll_cpll_aupll_npll_spll_p, 0, + RK3588_CLKSEL_CON(158), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(66), 1, GFLAGS), + GATE(CLK_GPU, "clk_gpu", "clk_gpu_src", 0, + RK3588_CLKGATE_CON(66), 4, GFLAGS), + GATE(CLK_GPU_COREGROUP, "clk_gpu_coregroup", "clk_gpu_src", 0, + RK3588_CLKGATE_CON(66), 6, GFLAGS), + COMPOSITE_NOMUX(CLK_GPU_STACKS, "clk_gpu_stacks", "clk_gpu_src", 0, + RK3588_CLKSEL_CON(159), 0, 5, DFLAGS, + RK3588_CLKGATE_CON(66), 7, GFLAGS), + GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0, + RK3588_CLKGATE_CON(67), 0, GFLAGS), + GATE(CLK_CORE_GPU_PVTM, "clk_core_gpu_pvtm", "clk_gpu_src", 0, + RK3588_CLKGATE_CON(67), 1, GFLAGS), + + /* isp1 */ + COMPOSITE(ACLK_ISP1_ROOT, "aclk_isp1_root", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(67), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(26), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_ISP1_ROOT, "hclk_isp1_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(67), 7, 2, MFLAGS, + RK3588_CLKGATE_CON(26), 1, GFLAGS), + COMPOSITE(CLK_ISP1_CORE, "clk_isp1_core", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(67), 14, 2, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(26), 2, GFLAGS), + GATE(CLK_ISP1_CORE_MARVIN, "clk_isp1_core_marvin", "clk_isp1_core", 0, + RK3588_CLKGATE_CON(26), 3, GFLAGS), + GATE(CLK_ISP1_CORE_VICAP, "clk_isp1_core_vicap", "clk_isp1_core", 0, + RK3588_CLKGATE_CON(26), 4, GFLAGS), + + /* npu */ + COMPOSITE_NODIV(HCLK_NPU_ROOT, "hclk_npu_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(73), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(29), 0, GFLAGS), + COMPOSITE(CLK_NPU_DSU0, "clk_npu_dsu0", gpll_cpll_aupll_npll_spll_p, 0, + RK3588_CLKSEL_CON(73), 7, 3, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(29), 1, GFLAGS), + COMPOSITE_NODIV(PCLK_NPU_ROOT, "pclk_npu_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(74), 1, 2, MFLAGS, + RK3588_CLKGATE_CON(29), 4, GFLAGS), + GATE(ACLK_NPU1, "aclk_npu1", "clk_npu_dsu0", 0, + RK3588_CLKGATE_CON(27), 0, GFLAGS), + GATE(HCLK_NPU1, "hclk_npu1", "hclk_npu_root", 0, + RK3588_CLKGATE_CON(27), 2, GFLAGS), + GATE(ACLK_NPU2, "aclk_npu2", "clk_npu_dsu0", 0, + RK3588_CLKGATE_CON(28), 0, GFLAGS), + GATE(HCLK_NPU2, "hclk_npu2", "hclk_npu_root", 0, + RK3588_CLKGATE_CON(28), 2, GFLAGS), + COMPOSITE_NODIV(HCLK_NPU_CM0_ROOT, "hclk_npu_cm0_root", mux_400m_200m_100m_24m_p, 0, + RK3588_CLKSEL_CON(74), 5, 2, MFLAGS, + RK3588_CLKGATE_CON(30), 1, GFLAGS), + GATE(FCLK_NPU_CM0_CORE, "fclk_npu_cm0_core", "hclk_npu_cm0_root", 0, + RK3588_CLKGATE_CON(30), 3, GFLAGS), + COMPOSITE(CLK_NPU_CM0_RTC, "clk_npu_cm0_rtc", mux_24m_32k_p, 0, + RK3588_CLKSEL_CON(74), 12, 1, MFLAGS, 7, 5, DFLAGS, + RK3588_CLKGATE_CON(30), 5, GFLAGS), + GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_root", 0, + RK3588_CLKGATE_CON(29), 12, GFLAGS), + GATE(PCLK_NPU_GRF, "pclk_npu_grf", "pclk_npu_root", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(29), 13, GFLAGS), + GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0, + RK3588_CLKGATE_CON(29), 14, GFLAGS), + GATE(CLK_CORE_NPU_PVTM, "clk_core_npu_pvtm", "clk_npu_dsu0", 0, + RK3588_CLKGATE_CON(29), 15, GFLAGS), + GATE(ACLK_NPU0, "aclk_npu0", "clk_npu_dsu0", 0, + RK3588_CLKGATE_CON(30), 6, GFLAGS), + GATE(HCLK_NPU0, "hclk_npu0", "hclk_npu_root", 0, + RK3588_CLKGATE_CON(30), 8, GFLAGS), + GATE(PCLK_NPU_TIMER, "pclk_npu_timer", "pclk_npu_root", 0, + RK3588_CLKGATE_CON(29), 6, GFLAGS), + COMPOSITE_NODIV(CLK_NPUTIMER_ROOT, "clk_nputimer_root", mux_24m_100m_p, 0, + RK3588_CLKSEL_CON(74), 3, 1, MFLAGS, + RK3588_CLKGATE_CON(29), 7, GFLAGS), + GATE(CLK_NPUTIMER0, "clk_nputimer0", "clk_nputimer_root", 0, + RK3588_CLKGATE_CON(29), 8, GFLAGS), + GATE(CLK_NPUTIMER1, "clk_nputimer1", "clk_nputimer_root", 0, + RK3588_CLKGATE_CON(29), 9, GFLAGS), + GATE(PCLK_NPU_WDT, "pclk_npu_wdt", "pclk_npu_root", 0, + RK3588_CLKGATE_CON(29), 10, GFLAGS), + GATE(TCLK_NPU_WDT, "tclk_npu_wdt", "xin24m", 0, + RK3588_CLKGATE_CON(29), 11, GFLAGS), + + /* nvm */ + COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(77), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(31), 0, GFLAGS), + COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(31), 1, GFLAGS), + GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0, + RK3588_CLKGATE_CON(31), 5, GFLAGS), + COMPOSITE(CCLK_EMMC, "cclk_emmc", gpll_cpll_24m_p, 0, + RK3588_CLKSEL_CON(77), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3588_CLKGATE_CON(31), 6, GFLAGS), + COMPOSITE(BCLK_EMMC, "bclk_emmc", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(78), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(31), 7, GFLAGS), + GATE(TMCLK_EMMC, "tmclk_emmc", "xin24m", 0, + RK3588_CLKGATE_CON(31), 8, GFLAGS), + + COMPOSITE(SCLK_SFC, "sclk_sfc", gpll_cpll_24m_p, 0, + RK3588_CLKSEL_CON(78), 12, 2, MFLAGS, 6, 6, DFLAGS, + RK3588_CLKGATE_CON(31), 9, GFLAGS), + + /* php */ + COMPOSITE(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac0_ptp_ref_p, 0, + RK3588_CLKSEL_CON(81), 6, 1, MFLAGS, 0, 6, DFLAGS, + RK3588_CLKGATE_CON(34), 10, GFLAGS), + COMPOSITE(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac1_ptp_ref_p, 0, + RK3588_CLKSEL_CON(81), 13, 1, MFLAGS, 7, 6, DFLAGS, + RK3588_CLKGATE_CON(34), 11, GFLAGS), + COMPOSITE(CLK_GMAC_125M, "clk_gmac_125m", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(83), 15, 1, MFLAGS, 8, 7, DFLAGS, + RK3588_CLKGATE_CON(35), 5, GFLAGS), + COMPOSITE(CLK_GMAC_50M, "clk_gmac_50m", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(84), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(35), 6, GFLAGS), + + COMPOSITE(ACLK_PCIE_ROOT, "aclk_pcie_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(80), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(32), 6, GFLAGS), + COMPOSITE(ACLK_PHP_ROOT, "aclk_php_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(80), 13, 1, MFLAGS, 8, 5, DFLAGS, + RK3588_CLKGATE_CON(32), 7, GFLAGS), + COMPOSITE_NODIV(PCLK_PHP_ROOT, "pclk_php_root", mux_150m_50m_24m_p, 0, + RK3588_CLKSEL_CON(80), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(32), 0, GFLAGS), + GATE(ACLK_PHP_GIC_ITS, "aclk_php_gic_its", "aclk_pcie_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(34), 6, GFLAGS), + GATE(ACLK_PCIE_BRIDGE, "aclk_pcie_bridge", "aclk_pcie_root", 0, + RK3588_CLKGATE_CON(32), 8, GFLAGS), + GATE(ACLK_MMU_PCIE, "aclk_mmu_pcie", "aclk_pcie_bridge", 0, + RK3588_CLKGATE_CON(34), 7, GFLAGS), + GATE(ACLK_MMU_PHP, "aclk_mmu_php", "aclk_php_root", 0, + RK3588_CLKGATE_CON(34), 8, GFLAGS), + GATE(ACLK_PCIE_4L_DBI, "aclk_pcie_4l_dbi", "aclk_php_root", 0, + RK3588_CLKGATE_CON(32), 13, GFLAGS), + GATE(ACLK_PCIE_2L_DBI, "aclk_pcie_2l_dbi", "aclk_php_root", 0, + RK3588_CLKGATE_CON(32), 14, GFLAGS), + GATE(ACLK_PCIE_1L0_DBI, "aclk_pcie_1l0_dbi", "aclk_php_root", 0, + RK3588_CLKGATE_CON(32), 15, GFLAGS), + GATE(ACLK_PCIE_1L1_DBI, "aclk_pcie_1l1_dbi", "aclk_php_root", 0, + RK3588_CLKGATE_CON(33), 0, GFLAGS), + GATE(ACLK_PCIE_1L2_DBI, "aclk_pcie_1l2_dbi", "aclk_php_root", 0, + RK3588_CLKGATE_CON(33), 1, GFLAGS), + GATE(ACLK_PCIE_4L_MSTR, "aclk_pcie_4l_mstr", "aclk_mmu_pcie", 0, + RK3588_CLKGATE_CON(33), 2, GFLAGS), + GATE(ACLK_PCIE_2L_MSTR, "aclk_pcie_2l_mstr", "aclk_mmu_pcie", 0, + RK3588_CLKGATE_CON(33), 3, GFLAGS), + GATE(ACLK_PCIE_1L0_MSTR, "aclk_pcie_1l0_mstr", "aclk_mmu_pcie", 0, + RK3588_CLKGATE_CON(33), 4, GFLAGS), + GATE(ACLK_PCIE_1L1_MSTR, "aclk_pcie_1l1_mstr", "aclk_mmu_pcie", 0, + RK3588_CLKGATE_CON(33), 5, GFLAGS), + GATE(ACLK_PCIE_1L2_MSTR, "aclk_pcie_1l2_mstr", "aclk_mmu_pcie", 0, + RK3588_CLKGATE_CON(33), 6, GFLAGS), + GATE(ACLK_PCIE_4L_SLV, "aclk_pcie_4l_slv", "aclk_php_root", 0, + RK3588_CLKGATE_CON(33), 7, GFLAGS), + GATE(ACLK_PCIE_2L_SLV, "aclk_pcie_2l_slv", "aclk_php_root", 0, + RK3588_CLKGATE_CON(33), 8, GFLAGS), + GATE(ACLK_PCIE_1L0_SLV, "aclk_pcie_1l0_slv", "aclk_php_root", 0, + RK3588_CLKGATE_CON(33), 9, GFLAGS), + GATE(ACLK_PCIE_1L1_SLV, "aclk_pcie_1l1_slv", "aclk_php_root", 0, + RK3588_CLKGATE_CON(33), 10, GFLAGS), + GATE(ACLK_PCIE_1L2_SLV, "aclk_pcie_1l2_slv", "aclk_php_root", 0, + RK3588_CLKGATE_CON(33), 11, GFLAGS), + GATE(PCLK_PCIE_4L, "pclk_pcie_4l", "pclk_php_root", 0, + RK3588_CLKGATE_CON(33), 12, GFLAGS), + GATE(PCLK_PCIE_2L, "pclk_pcie_2l", "pclk_php_root", 0, + RK3588_CLKGATE_CON(33), 13, GFLAGS), + GATE(PCLK_PCIE_1L0, "pclk_pcie_1l0", "pclk_php_root", 0, + RK3588_CLKGATE_CON(33), 14, GFLAGS), + GATE(PCLK_PCIE_1L1, "pclk_pcie_1l1", "pclk_php_root", 0, + RK3588_CLKGATE_CON(33), 15, GFLAGS), + GATE(PCLK_PCIE_1L2, "pclk_pcie_1l2", "pclk_php_root", 0, + RK3588_CLKGATE_CON(34), 0, GFLAGS), + GATE(CLK_PCIE_AUX0, "clk_pcie_aux0", "xin24m", 0, + RK3588_CLKGATE_CON(34), 1, GFLAGS), + GATE(CLK_PCIE_AUX1, "clk_pcie_aux1", "xin24m", 0, + RK3588_CLKGATE_CON(34), 2, GFLAGS), + GATE(CLK_PCIE_AUX2, "clk_pcie_aux2", "xin24m", 0, + RK3588_CLKGATE_CON(34), 3, GFLAGS), + GATE(CLK_PCIE_AUX3, "clk_pcie_aux3", "xin24m", 0, + RK3588_CLKGATE_CON(34), 4, GFLAGS), + GATE(CLK_PCIE_AUX4, "clk_pcie_aux4", "xin24m", 0, + RK3588_CLKGATE_CON(34), 5, GFLAGS), + GATE(CLK_PIPEPHY0_REF, "clk_pipephy0_ref", "xin24m", 0, + RK3588_CLKGATE_CON(37), 0, GFLAGS), + GATE(CLK_PIPEPHY1_REF, "clk_pipephy1_ref", "xin24m", 0, + RK3588_CLKGATE_CON(37), 1, GFLAGS), + GATE(CLK_PIPEPHY2_REF, "clk_pipephy2_ref", "xin24m", 0, + RK3588_CLKGATE_CON(37), 2, GFLAGS), + GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php_root", 0, + RK3588_CLKGATE_CON(32), 3, GFLAGS), + GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_php_root", 0, + RK3588_CLKGATE_CON(32), 4, GFLAGS), + GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_mmu_php", 0, + RK3588_CLKGATE_CON(32), 10, GFLAGS), + GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_mmu_php", 0, + RK3588_CLKGATE_CON(32), 11, GFLAGS), + GATE(CLK_PMALIVE0, "clk_pmalive0", "xin24m", 0, + RK3588_CLKGATE_CON(37), 4, GFLAGS), + GATE(CLK_PMALIVE1, "clk_pmalive1", "xin24m", 0, + RK3588_CLKGATE_CON(37), 5, GFLAGS), + GATE(CLK_PMALIVE2, "clk_pmalive2", "xin24m", 0, + RK3588_CLKGATE_CON(37), 6, GFLAGS), + GATE(ACLK_SATA0, "aclk_sata0", "aclk_mmu_php", 0, + RK3588_CLKGATE_CON(37), 7, GFLAGS), + GATE(ACLK_SATA1, "aclk_sata1", "aclk_mmu_php", 0, + RK3588_CLKGATE_CON(37), 8, GFLAGS), + GATE(ACLK_SATA2, "aclk_sata2", "aclk_mmu_php", 0, + RK3588_CLKGATE_CON(37), 9, GFLAGS), + COMPOSITE(CLK_RXOOB0, "clk_rxoob0", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(82), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(37), 10, GFLAGS), + COMPOSITE(CLK_RXOOB1, "clk_rxoob1", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(82), 15, 1, MFLAGS, 8, 7, DFLAGS, + RK3588_CLKGATE_CON(37), 11, GFLAGS), + COMPOSITE(CLK_RXOOB2, "clk_rxoob2", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(83), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(37), 12, GFLAGS), + GATE(ACLK_USB3OTG2, "aclk_usb3otg2", "aclk_mmu_php", 0, + RK3588_CLKGATE_CON(35), 7, GFLAGS), + GATE(SUSPEND_CLK_USB3OTG2, "suspend_clk_usb3otg2", "xin24m", 0, + RK3588_CLKGATE_CON(35), 8, GFLAGS), + GATE(REF_CLK_USB3OTG2, "ref_clk_usb3otg2", "xin24m", 0, + RK3588_CLKGATE_CON(35), 9, GFLAGS), + COMPOSITE(CLK_UTMI_OTG2, "clk_utmi_otg2", mux_150m_50m_24m_p, 0, + RK3588_CLKSEL_CON(84), 12, 2, MFLAGS, 8, 4, DFLAGS, + RK3588_CLKGATE_CON(35), 10, GFLAGS), + GATE(PCLK_PCIE_COMBO_PIPE_PHY0, "pclk_pcie_combo_pipe_phy0", "pclk_top_root", 0, + RK3588_PHP_CLKGATE_CON(0), 5, GFLAGS), + GATE(PCLK_PCIE_COMBO_PIPE_PHY1, "pclk_pcie_combo_pipe_phy1", "pclk_top_root", 0, + RK3588_PHP_CLKGATE_CON(0), 6, GFLAGS), + GATE(PCLK_PCIE_COMBO_PIPE_PHY2, "pclk_pcie_combo_pipe_phy2", "pclk_top_root", 0, + RK3588_PHP_CLKGATE_CON(0), 7, GFLAGS), + GATE(PCLK_PCIE_COMBO_PIPE_PHY, "pclk_pcie_combo_pipe_phy", "pclk_top_root", 0, + RK3588_PHP_CLKGATE_CON(0), 8, GFLAGS), + + /* rga */ + COMPOSITE(CLK_RGA3_1_CORE, "clk_rga3_1_core", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(174), 14, 2, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(76), 6, GFLAGS), + COMPOSITE(ACLK_RGA3_ROOT, "aclk_rga3_root", gpll_cpll_aupll_p, 0, + RK3588_CLKSEL_CON(174), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(76), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_RGA3_ROOT, "hclk_rga3_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(174), 7, 2, MFLAGS, + RK3588_CLKGATE_CON(76), 1, GFLAGS), + GATE(HCLK_RGA3_1, "hclk_rga3_1", "hclk_rga3_root", 0, + RK3588_CLKGATE_CON(76), 4, GFLAGS), + GATE(ACLK_RGA3_1, "aclk_rga3_1", "aclk_rga3_root", 0, + RK3588_CLKGATE_CON(76), 5, GFLAGS), + + /* vdec */ + COMPOSITE_NODIV(0, "hclk_rkvdec0_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(89), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(40), 0, GFLAGS), + COMPOSITE(0, "aclk_rkvdec0_root", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(89), 7, 2, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(40), 1, GFLAGS), + COMPOSITE(ACLK_RKVDEC_CCU, "aclk_rkvdec_ccu", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(89), 14, 2, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(40), 2, GFLAGS), + COMPOSITE(CLK_RKVDEC0_CA, "clk_rkvdec0_ca", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(90), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(40), 7, GFLAGS), + COMPOSITE(CLK_RKVDEC0_HEVC_CA, "clk_rkvdec0_hevc_ca", gpll_cpll_npll_1000m_p, 0, + RK3588_CLKSEL_CON(90), 11, 2, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(40), 8, GFLAGS), + COMPOSITE(CLK_RKVDEC0_CORE, "clk_rkvdec0_core", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(91), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(40), 9, GFLAGS), + COMPOSITE_NODIV(0, "hclk_rkvdec1_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(93), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(41), 0, GFLAGS), + COMPOSITE(0, "aclk_rkvdec1_root", gpll_cpll_aupll_npll_p, 0, + RK3588_CLKSEL_CON(93), 7, 2, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(41), 1, GFLAGS), + COMPOSITE(CLK_RKVDEC1_CA, "clk_rkvdec1_ca", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(93), 14, 1, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(41), 6, GFLAGS), + COMPOSITE(CLK_RKVDEC1_HEVC_CA, "clk_rkvdec1_hevc_ca", gpll_cpll_npll_1000m_p, 0, + RK3588_CLKSEL_CON(94), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(41), 7, GFLAGS), + COMPOSITE(CLK_RKVDEC1_CORE, "clk_rkvdec1_core", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(94), 12, 1, MFLAGS, 7, 5, DFLAGS, + RK3588_CLKGATE_CON(41), 8, GFLAGS), + + /* sdio */ + COMPOSITE_NODIV(0, "hclk_sdio_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(172), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(75), 0, GFLAGS), + COMPOSITE(CCLK_SRC_SDIO, "cclk_src_sdio", gpll_cpll_24m_p, 0, + RK3588_CLKSEL_CON(172), 8, 2, MFLAGS, 2, 6, DFLAGS, + RK3588_CLKGATE_CON(75), 3, GFLAGS), + MMC(SCLK_SDIO_DRV, "sdio_drv", "cclk_src_sdio", RK3588_SDIO_CON0, 1), + MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "cclk_src_sdio", RK3588_SDIO_CON1, 1), + + /* usb */ + COMPOSITE(ACLK_USB_ROOT, "aclk_usb_root", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(96), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(42), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_USB_ROOT, "hclk_usb_root", mux_150m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(96), 6, 2, MFLAGS, + RK3588_CLKGATE_CON(42), 1, GFLAGS), + GATE(SUSPEND_CLK_USB3OTG0, "suspend_clk_usb3otg0", "xin24m", 0, + RK3588_CLKGATE_CON(42), 5, GFLAGS), + GATE(REF_CLK_USB3OTG0, "ref_clk_usb3otg0", "xin24m", 0, + RK3588_CLKGATE_CON(42), 6, GFLAGS), + GATE(SUSPEND_CLK_USB3OTG1, "suspend_clk_usb3otg1", "xin24m", 0, + RK3588_CLKGATE_CON(42), 8, GFLAGS), + GATE(REF_CLK_USB3OTG1, "ref_clk_usb3otg1", "xin24m", 0, + RK3588_CLKGATE_CON(42), 9, GFLAGS), + + /* vdpu */ + COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0, + RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(44), 0, GFLAGS), + COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0, + RK3588_CLKSEL_CON(98), 7, 2, MFLAGS, + RK3588_CLKGATE_CON(44), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(98), 9, 2, MFLAGS, + RK3588_CLKGATE_CON(44), 2, GFLAGS), + COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(99), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(44), 3, GFLAGS), + GATE(HCLK_IEP2P0, "hclk_iep2p0", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(45), 4, GFLAGS), + COMPOSITE(CLK_IEP2P0_CORE, "clk_iep2p0_core", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(99), 12, 1, MFLAGS, 7, 5, DFLAGS, + RK3588_CLKGATE_CON(45), 6, GFLAGS), + GATE(HCLK_JPEG_ENCODER0, "hclk_jpeg_encoder0", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(44), 11, GFLAGS), + GATE(HCLK_JPEG_ENCODER1, "hclk_jpeg_encoder1", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(44), 13, GFLAGS), + GATE(HCLK_JPEG_ENCODER2, "hclk_jpeg_encoder2", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(44), 15, GFLAGS), + GATE(HCLK_JPEG_ENCODER3, "hclk_jpeg_encoder3", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(45), 1, GFLAGS), + GATE(HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(45), 3, GFLAGS), + GATE(HCLK_RGA2, "hclk_rga2", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(45), 7, GFLAGS), + GATE(ACLK_RGA2, "aclk_rga2", "aclk_vdpu_root", 0, + RK3588_CLKGATE_CON(45), 8, GFLAGS), + COMPOSITE(CLK_RGA2_CORE, "clk_rga2_core", gpll_cpll_npll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(100), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(45), 9, GFLAGS), + GATE(HCLK_RGA3_0, "hclk_rga3_0", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(45), 10, GFLAGS), + GATE(ACLK_RGA3_0, "aclk_rga3_0", "aclk_vdpu_root", 0, + RK3588_CLKGATE_CON(45), 11, GFLAGS), + COMPOSITE(CLK_RGA3_0_CORE, "clk_rga3_0_core", gpll_cpll_npll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(100), 13, 3, MFLAGS, 8, 5, DFLAGS, + RK3588_CLKGATE_CON(45), 12, GFLAGS), + GATE(HCLK_VPU, "hclk_vpu", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(44), 9, GFLAGS), + + /* venc */ + COMPOSITE_NODIV(HCLK_RKVENC1_ROOT, "hclk_rkvenc1_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(104), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(48), 0, GFLAGS), + COMPOSITE(ACLK_RKVENC1_ROOT, "aclk_rkvenc1_root", gpll_cpll_npll_p, 0, + RK3588_CLKSEL_CON(104), 7, 2, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(48), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_RKVENC0_ROOT, "hclk_rkvenc0_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(102), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(47), 0, GFLAGS), + COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0, + RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(47), 1, GFLAGS), + GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0, + RK3588_CLKGATE_CON(47), 4, GFLAGS), + GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0, + RK3588_CLKGATE_CON(47), 5, GFLAGS), + COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0, + RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(47), 6, GFLAGS), + COMPOSITE(CLK_RKVENC1_CORE, "clk_rkvenc1_core", gpll_cpll_aupll_npll_p, 0, + RK3588_CLKSEL_CON(104), 14, 2, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(48), 6, GFLAGS), + + /* vi */ + COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(49), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(106), 8, 2, MFLAGS, + RK3588_CLKGATE_CON(49), 1, GFLAGS), + COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(106), 10, 2, MFLAGS, + RK3588_CLKGATE_CON(49), 2, GFLAGS), + COMPOSITE_NODIV(ICLK_CSIHOST01, "iclk_csihost01", mux_400m_200m_100m_24m_p, 0, + RK3588_CLKSEL_CON(108), 14, 2, MFLAGS, + RK3588_CLKGATE_CON(51), 10, GFLAGS), + GATE(ICLK_CSIHOST0, "iclk_csihost0", "iclk_csihost01", 0, + RK3588_CLKGATE_CON(51), 11, GFLAGS), + GATE(ICLK_CSIHOST1, "iclk_csihost1", "iclk_csihost01", 0, + RK3588_CLKGATE_CON(51), 12, GFLAGS), + GATE(PCLK_CSI_HOST_0, "pclk_csi_host_0", "pclk_vi_root", 0, + RK3588_CLKGATE_CON(50), 4, GFLAGS), + GATE(PCLK_CSI_HOST_1, "pclk_csi_host_1", "pclk_vi_root", 0, + RK3588_CLKGATE_CON(50), 5, GFLAGS), + GATE(PCLK_CSI_HOST_2, "pclk_csi_host_2", "pclk_vi_root", 0, + RK3588_CLKGATE_CON(50), 6, GFLAGS), + GATE(PCLK_CSI_HOST_3, "pclk_csi_host_3", "pclk_vi_root", 0, + RK3588_CLKGATE_CON(50), 7, GFLAGS), + GATE(PCLK_CSI_HOST_4, "pclk_csi_host_4", "pclk_vi_root", 0, + RK3588_CLKGATE_CON(50), 8, GFLAGS), + GATE(PCLK_CSI_HOST_5, "pclk_csi_host_5", "pclk_vi_root", 0, + RK3588_CLKGATE_CON(50), 9, GFLAGS), + GATE(ACLK_FISHEYE0, "aclk_fisheye0", "aclk_vi_root", 0, + RK3588_CLKGATE_CON(49), 14, GFLAGS), + GATE(HCLK_FISHEYE0, "hclk_fisheye0", "hclk_vi_root", 0, + RK3588_CLKGATE_CON(49), 15, GFLAGS), + COMPOSITE(CLK_FISHEYE0_CORE, "clk_fisheye0_core", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(108), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(50), 0, GFLAGS), + GATE(ACLK_FISHEYE1, "aclk_fisheye1", "aclk_vi_root", 0, + RK3588_CLKGATE_CON(50), 1, GFLAGS), + GATE(HCLK_FISHEYE1, "hclk_fisheye1", "hclk_vi_root", 0, + RK3588_CLKGATE_CON(50), 2, GFLAGS), + COMPOSITE(CLK_FISHEYE1_CORE, "clk_fisheye1_core", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(108), 12, 2, MFLAGS, 7, 5, DFLAGS, + RK3588_CLKGATE_CON(50), 3, GFLAGS), + COMPOSITE(CLK_ISP0_CORE, "clk_isp0_core", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(107), 11, 2, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(49), 9, GFLAGS), + GATE(CLK_ISP0_CORE_MARVIN, "clk_isp0_core_marvin", "clk_isp0_core", 0, + RK3588_CLKGATE_CON(49), 10, GFLAGS), + GATE(CLK_ISP0_CORE_VICAP, "clk_isp0_core_vicap", "clk_isp0_core", 0, + RK3588_CLKGATE_CON(49), 11, GFLAGS), + GATE(ACLK_ISP0, "aclk_isp0", "aclk_vi_root", 0, + RK3588_CLKGATE_CON(49), 12, GFLAGS), + GATE(HCLK_ISP0, "hclk_isp0", "hclk_vi_root", 0, + RK3588_CLKGATE_CON(49), 13, GFLAGS), + COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(107), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(49), 6, GFLAGS), + GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0, + RK3588_CLKGATE_CON(49), 7, GFLAGS), + GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0, + RK3588_CLKGATE_CON(49), 8, GFLAGS), + + /* vo0 */ + COMPOSITE(ACLK_VO0_ROOT, "aclk_vo0_root", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(116), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(55), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_VO0_ROOT, "hclk_vo0_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(116), 6, 2, MFLAGS, + RK3588_CLKGATE_CON(55), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_VO0_S_ROOT, "hclk_vo0_s_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(116), 8, 2, MFLAGS, + RK3588_CLKGATE_CON(55), 2, GFLAGS), + COMPOSITE_NODIV(PCLK_VO0_ROOT, "pclk_vo0_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(116), 10, 2, MFLAGS, + RK3588_CLKGATE_CON(55), 3, GFLAGS), + COMPOSITE_NODIV(PCLK_VO0_S_ROOT, "pclk_vo0_s_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(116), 12, 2, MFLAGS, + RK3588_CLKGATE_CON(55), 4, GFLAGS), + GATE(PCLK_DP0, "pclk_dp0", "pclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 4, GFLAGS), + GATE(PCLK_DP1, "pclk_dp1", "pclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 5, GFLAGS), + GATE(PCLK_S_DP0, "pclk_s_dp0", "pclk_vo0_s_root", 0, + RK3588_CLKGATE_CON(56), 6, GFLAGS), + GATE(PCLK_S_DP1, "pclk_s_dp1", "pclk_vo0_s_root", 0, + RK3588_CLKGATE_CON(56), 7, GFLAGS), + GATE(CLK_DP0, "clk_dp0", "aclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 8, GFLAGS), + GATE(CLK_DP1, "clk_dp1", "aclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 9, GFLAGS), + GATE(HCLK_HDCP_KEY0, "hclk_hdcp_key0", "hclk_vo0_s_root", 0, + RK3588_CLKGATE_CON(55), 11, GFLAGS), + GATE(PCLK_HDCP0, "pclk_hdcp0", "pclk_vo0_root", 0, + RK3588_CLKGATE_CON(55), 14, GFLAGS), + GATE(ACLK_TRNG0, "aclk_trng0", "aclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 0, GFLAGS), + GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 1, GFLAGS), + GATE(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(55), 10, GFLAGS), + COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(56), 11, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S4_8CH_TX_FRAC, "clk_i2s4_8ch_tx_frac", "clk_i2s4_8ch_tx_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(119), 0, + RK3588_CLKGATE_CON(56), 12, GFLAGS, + &rk3588_i2s4_8ch_tx_fracmux), + GATE(MCLK_I2S4_8CH_TX, "mclk_i2s4_8ch_tx", "clk_i2s4_8ch_tx", 0, + RK3588_CLKGATE_CON(56), 13, GFLAGS), + COMPOSITE(CLK_I2S8_8CH_TX_SRC, "clk_i2s8_8ch_tx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(120), 8, 1, MFLAGS, 3, 5, DFLAGS, + RK3588_CLKGATE_CON(56), 15, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S8_8CH_TX_FRAC, "clk_i2s8_8ch_tx_frac", "clk_i2s8_8ch_tx_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(121), 0, + RK3588_CLKGATE_CON(57), 0, GFLAGS, + &rk3588_i2s8_8ch_tx_fracmux), + GATE(MCLK_I2S8_8CH_TX, "mclk_i2s8_8ch_tx", "clk_i2s8_8ch_tx", 0, + RK3588_CLKGATE_CON(57), 1, GFLAGS), + COMPOSITE(CLK_SPDIF2_DP0_SRC, "clk_spdif2_dp0_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(122), 8, 1, MFLAGS, 3, 5, DFLAGS, + RK3588_CLKGATE_CON(57), 3, GFLAGS), + COMPOSITE_FRACMUX(CLK_SPDIF2_DP0_FRAC, "clk_spdif2_dp0_frac", "clk_spdif2_dp0_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(123), 0, + RK3588_CLKGATE_CON(57), 4, GFLAGS, + &rk3588_spdif2_dp0_fracmux), + GATE(MCLK_SPDIF2_DP0, "mclk_spdif2_dp0", "clk_spdif2_dp0", 0, + RK3588_CLKGATE_CON(57), 5, GFLAGS), + GATE(MCLK_SPDIF2, "mclk_spdif2", "clk_spdif2_dp0", 0, + RK3588_CLKGATE_CON(57), 6, GFLAGS), + COMPOSITE(CLK_SPDIF5_DP1_SRC, "clk_spdif5_dp1_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(124), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(57), 8, GFLAGS), + COMPOSITE_FRACMUX(CLK_SPDIF5_DP1_FRAC, "clk_spdif5_dp1_frac", "clk_spdif5_dp1_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(125), 0, + RK3588_CLKGATE_CON(57), 9, GFLAGS, + &rk3588_spdif5_dp1_fracmux), + GATE(MCLK_SPDIF5_DP1, "mclk_spdif5_dp1", "clk_spdif5_dp1", 0, + RK3588_CLKGATE_CON(57), 10, GFLAGS), + GATE(MCLK_SPDIF5, "mclk_spdif5", "clk_spdif5_dp1", 0, + RK3588_CLKGATE_CON(57), 11, GFLAGS), + COMPOSITE_NOMUX(CLK_AUX16M_0, "clk_aux16m_0", "gpll", 0, + RK3588_CLKSEL_CON(117), 0, 8, DFLAGS, + RK3588_CLKGATE_CON(56), 2, GFLAGS), + COMPOSITE_NOMUX(CLK_AUX16M_1, "clk_aux16m_1", "gpll", 0, + RK3588_CLKSEL_CON(117), 8, 8, DFLAGS, + RK3588_CLKGATE_CON(56), 3, GFLAGS), + + /* vo1 */ + COMPOSITE_HALFDIV(CLK_HDMITRX_REFSRC, "clk_hdmitrx_refsrc", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(157), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(65), 9, GFLAGS), + COMPOSITE(ACLK_HDCP1_ROOT, "aclk_hdcp1_root", aclk_hdcp1_root_p, 0, + RK3588_CLKSEL_CON(128), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(59), 0, GFLAGS), + COMPOSITE(ACLK_HDMIRX_ROOT, "aclk_hdmirx_root", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(128), 12, 1, MFLAGS, 7, 5, DFLAGS, + RK3588_CLKGATE_CON(59), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_VO1_ROOT, "hclk_vo1_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(128), 13, 2, MFLAGS, + RK3588_CLKGATE_CON(59), 2, GFLAGS), + COMPOSITE_NODIV(HCLK_VO1_S_ROOT, "hclk_vo1_s_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(129), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(59), 3, GFLAGS), + COMPOSITE_NODIV(PCLK_VO1_ROOT, "pclk_vo1_root", mux_150m_100m_24m_p, 0, + RK3588_CLKSEL_CON(129), 2, 2, MFLAGS, + RK3588_CLKGATE_CON(59), 4, GFLAGS), + COMPOSITE_NODIV(PCLK_VO1_S_ROOT, "pclk_vo1_s_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(129), 4, 2, MFLAGS, + RK3588_CLKGATE_CON(59), 5, GFLAGS), + COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0, + RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(52), 0, GFLAGS), + COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0, + RK3588_CLKSEL_CON(110), 8, 2, MFLAGS, + RK3588_CLKGATE_CON(52), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(110), 10, 2, MFLAGS, + RK3588_CLKGATE_CON(52), 2, GFLAGS), + COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(110), 12, 2, MFLAGS, + RK3588_CLKGATE_CON(52), 3, GFLAGS), + COMPOSITE(ACLK_VO1USB_TOP_ROOT, "aclk_vo1usb_top_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(170), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(74), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_VO1USB_TOP_ROOT, "hclk_vo1usb_top_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(170), 6, 2, MFLAGS, + RK3588_CLKGATE_CON(74), 2, GFLAGS), + MUX(ACLK_VOP_SUB_SRC, "aclk_vop_sub_src", aclk_vop_sub_src_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(115), 9, 1, MFLAGS), + GATE(PCLK_EDP0, "pclk_edp0", "pclk_vo1_root", 0, + RK3588_CLKGATE_CON(62), 0, GFLAGS), + GATE(CLK_EDP0_24M, "clk_edp0_24m", "xin24m", 0, + RK3588_CLKGATE_CON(62), 1, GFLAGS), + COMPOSITE_NODIV(CLK_EDP0_200M, "clk_edp0_200m", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(140), 1, 2, MFLAGS, + RK3588_CLKGATE_CON(62), 2, GFLAGS), + GATE(PCLK_EDP1, "pclk_edp1", "pclk_vo1_root", 0, + RK3588_CLKGATE_CON(62), 3, GFLAGS), + GATE(CLK_EDP1_24M, "clk_edp1_24m", "xin24m", 0, + RK3588_CLKGATE_CON(62), 4, GFLAGS), + COMPOSITE_NODIV(CLK_EDP1_200M, "clk_edp1_200m", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(140), 3, 2, MFLAGS, + RK3588_CLKGATE_CON(62), 5, GFLAGS), + GATE(HCLK_HDCP_KEY1, "hclk_hdcp_key1", "hclk_vo1_s_root", 0, + RK3588_CLKGATE_CON(60), 4, GFLAGS), + GATE(PCLK_HDCP1, "pclk_hdcp1", "pclk_vo1_root", 0, + RK3588_CLKGATE_CON(60), 7, GFLAGS), + GATE(ACLK_HDMIRX, "aclk_hdmirx", "aclk_hdmirx_root", 0, + RK3588_CLKGATE_CON(61), 9, GFLAGS), + GATE(PCLK_HDMIRX, "pclk_hdmirx", "pclk_vo1_root", 0, + RK3588_CLKGATE_CON(61), 10, GFLAGS), + GATE(CLK_HDMIRX_REF, "clk_hdmirx_ref", "aclk_hdcp1_root", 0, + RK3588_CLKGATE_CON(61), 11, GFLAGS), + COMPOSITE(CLK_HDMIRX_AUD_SRC, "clk_hdmirx_aud_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(138), 8, 1, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(61), 12, GFLAGS), + COMPOSITE_FRACMUX(CLK_HDMIRX_AUD_FRAC, "clk_hdmirx_aud_frac", "clk_hdmirx_aud_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(139), 0, + RK3588_CLKGATE_CON(61), 13, GFLAGS, + &rk3588_hdmirx_aud_fracmux), + GATE(CLK_HDMIRX_AUD, "clk_hdmirx_aud", "clk_hdmirx_aud_mux", 0, + RK3588_CLKGATE_CON(61), 14, GFLAGS), + GATE(PCLK_HDMITX0, "pclk_hdmitx0", "pclk_vo1_root", 0, + RK3588_CLKGATE_CON(60), 11, GFLAGS), + COMPOSITE(CLK_HDMITX0_EARC, "clk_hdmitx0_earc", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(133), 6, 1, MFLAGS, 1, 5, DFLAGS, + RK3588_CLKGATE_CON(60), 15, GFLAGS), + GATE(CLK_HDMITX0_REF, "clk_hdmitx0_ref", "aclk_hdcp1_root", 0, + RK3588_CLKGATE_CON(61), 0, GFLAGS), + GATE(PCLK_HDMITX1, "pclk_hdmitx1", "pclk_vo1_root", 0, + RK3588_CLKGATE_CON(61), 2, GFLAGS), + COMPOSITE(CLK_HDMITX1_EARC, "clk_hdmitx1_earc", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(136), 6, 1, MFLAGS, 1, 5, DFLAGS, + RK3588_CLKGATE_CON(61), 6, GFLAGS), + GATE(CLK_HDMITX1_REF, "clk_hdmitx1_ref", "aclk_hdcp1_root", 0, + RK3588_CLKGATE_CON(61), 7, GFLAGS), + GATE(ACLK_TRNG1, "aclk_trng1", "aclk_hdcp1_root", 0, + RK3588_CLKGATE_CON(60), 9, GFLAGS), + GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0, + RK3588_CLKGATE_CON(60), 10, GFLAGS), + GATE(0, "pclk_vo1grf", "pclk_vo1_root", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(59), 12, GFLAGS), + GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0, + RK3588_CLKGATE_CON(59), 14, GFLAGS), + GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0, + RK3588_CLKGATE_CON(59), 15, GFLAGS), + GATE(PCLK_S_HDMIRX, "pclk_s_hdmirx", "pclk_vo1_s_root", 0, + RK3588_CLKGATE_CON(65), 8, GFLAGS), + COMPOSITE(CLK_I2S10_8CH_RX_SRC, "clk_i2s10_8ch_rx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(155), 8, 1, MFLAGS, 3, 5, DFLAGS, + RK3588_CLKGATE_CON(65), 5, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S10_8CH_RX_FRAC, "clk_i2s10_8ch_rx_frac", "clk_i2s10_8ch_rx_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(156), 0, + RK3588_CLKGATE_CON(65), 6, GFLAGS, + &rk3588_i2s10_8ch_rx_fracmux), + GATE(MCLK_I2S10_8CH_RX, "mclk_i2s10_8ch_rx", "clk_i2s10_8ch_rx", 0, + RK3588_CLKGATE_CON(65), 7, GFLAGS), + COMPOSITE(CLK_I2S7_8CH_RX_SRC, "clk_i2s7_8ch_rx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(129), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(60), 1, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S7_8CH_RX_FRAC, "clk_i2s7_8ch_rx_frac", "clk_i2s7_8ch_rx_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(130), 0, + RK3588_CLKGATE_CON(60), 2, GFLAGS, + &rk3588_i2s7_8ch_rx_fracmux), + GATE(MCLK_I2S7_8CH_RX, "mclk_i2s7_8ch_rx", "clk_i2s7_8ch_rx", 0, + RK3588_CLKGATE_CON(60), 3, GFLAGS), + COMPOSITE(CLK_I2S9_8CH_RX_SRC, "clk_i2s9_8ch_rx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(153), 12, 1, MFLAGS, 7, 5, DFLAGS, + RK3588_CLKGATE_CON(65), 1, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S9_8CH_RX_FRAC, "clk_i2s9_8ch_rx_frac", "clk_i2s9_8ch_rx_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(154), 0, + RK3588_CLKGATE_CON(65), 2, GFLAGS, + &rk3588_i2s9_8ch_rx_fracmux), + GATE(MCLK_I2S9_8CH_RX, "mclk_i2s9_8ch_rx", "clk_i2s9_8ch_rx", 0, + RK3588_CLKGATE_CON(65), 3, GFLAGS), + COMPOSITE(CLK_I2S5_8CH_TX_SRC, "clk_i2s5_8ch_tx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(140), 10, 1, MFLAGS, 5, 5, DFLAGS, + RK3588_CLKGATE_CON(62), 6, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S5_8CH_TX_FRAC, "clk_i2s5_8ch_tx_frac", "clk_i2s5_8ch_tx_src", 0, + RK3588_CLKSEL_CON(141), 0, + RK3588_CLKGATE_CON(62), 7, GFLAGS, + &rk3588_i2s5_8ch_tx_fracmux), + GATE(MCLK_I2S5_8CH_TX, "mclk_i2s5_8ch_tx", "clk_i2s5_8ch_tx", 0, + RK3588_CLKGATE_CON(62), 8, GFLAGS), + COMPOSITE(CLK_I2S6_8CH_TX_SRC, "clk_i2s6_8ch_tx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(144), 8, 1, MFLAGS, 3, 5, DFLAGS, + RK3588_CLKGATE_CON(62), 13, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S6_8CH_TX_FRAC, "clk_i2s6_8ch_tx_frac", "clk_i2s6_8ch_tx_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(145), 0, + RK3588_CLKGATE_CON(62), 14, GFLAGS, + &rk3588_i2s6_8ch_tx_fracmux), + GATE(MCLK_I2S6_8CH_TX, "mclk_i2s6_8ch_tx", "clk_i2s6_8ch_tx", 0, + RK3588_CLKGATE_CON(62), 15, GFLAGS), + COMPOSITE(CLK_I2S6_8CH_RX_SRC, "clk_i2s6_8ch_rx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(146), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(63), 0, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S6_8CH_RX_FRAC, "clk_i2s6_8ch_rx_frac", "clk_i2s6_8ch_rx_src", 0, + RK3588_CLKSEL_CON(147), 0, + RK3588_CLKGATE_CON(63), 1, GFLAGS, + &rk3588_i2s6_8ch_rx_fracmux), + GATE(MCLK_I2S6_8CH_RX, "mclk_i2s6_8ch_rx", "clk_i2s6_8ch_rx", 0, + RK3588_CLKGATE_CON(63), 2, GFLAGS), + MUX(I2S6_8CH_MCLKOUT, "i2s6_8ch_mclkout", i2s6_8ch_mclkout_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(148), 2, 2, MFLAGS), + COMPOSITE(CLK_SPDIF3_SRC, "clk_spdif3_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(148), 9, 1, MFLAGS, 4, 5, DFLAGS, + RK3588_CLKGATE_CON(63), 5, GFLAGS), + COMPOSITE_FRACMUX(CLK_SPDIF3_FRAC, "clk_spdif3_frac", "clk_spdif3_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(149), 0, + RK3588_CLKGATE_CON(63), 6, GFLAGS, + &rk3588_spdif3_fracmux), + GATE(MCLK_SPDIF3, "mclk_spdif3", "clk_spdif3", 0, + RK3588_CLKGATE_CON(63), 7, GFLAGS), + COMPOSITE(CLK_SPDIF4_SRC, "clk_spdif4_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(150), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(63), 9, GFLAGS), + COMPOSITE_FRACMUX(CLK_SPDIF4_FRAC, "clk_spdif4_frac", "clk_spdif4_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(151), 0, + RK3588_CLKGATE_CON(63), 10, GFLAGS, + &rk3588_spdif4_fracmux), + GATE(MCLK_SPDIF4, "mclk_spdif4", "clk_spdif4", 0, + RK3588_CLKGATE_CON(63), 11, GFLAGS), + COMPOSITE(MCLK_SPDIFRX0, "mclk_spdifrx0", gpll_cpll_aupll_p, 0, + RK3588_CLKSEL_CON(152), 7, 2, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(63), 13, GFLAGS), + COMPOSITE(MCLK_SPDIFRX1, "mclk_spdifrx1", gpll_cpll_aupll_p, 0, + RK3588_CLKSEL_CON(152), 14, 2, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(63), 15, GFLAGS), + COMPOSITE(MCLK_SPDIFRX2, "mclk_spdifrx2", gpll_cpll_aupll_p, 0, + RK3588_CLKSEL_CON(153), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(64), 1, GFLAGS), + GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0, + RK3588_CLKGATE_CON(73), 12, GFLAGS), + GATE(CLK_HDMIHDP1, "clk_hdmihdp1", "xin24m", 0, + RK3588_CLKGATE_CON(73), 13, GFLAGS), + GATE(PCLK_HDPTX0, "pclk_hdptx0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(72), 5, GFLAGS), + GATE(PCLK_HDPTX1, "pclk_hdptx1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(72), 6, GFLAGS), + GATE(PCLK_USBDPPHY0, "pclk_usbdpphy0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(72), 2, GFLAGS), + GATE(PCLK_USBDPPHY1, "pclk_usbdpphy1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(72), 4, GFLAGS), + GATE(HCLK_VOP, "hclk_vop", "hclk_vop_root", 0, + RK3588_CLKGATE_CON(52), 8, GFLAGS), + GATE(ACLK_VOP, "aclk_vop", "aclk_vop_sub_src", 0, + RK3588_CLKGATE_CON(52), 9, GFLAGS), + COMPOSITE(DCLK_VOP0_SRC, "dclk_vop0_src", gpll_cpll_v0pll_aupll_p, 0, + RK3588_CLKSEL_CON(111), 7, 2, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(52), 10, GFLAGS), + COMPOSITE(DCLK_VOP1_SRC, "dclk_vop1_src", gpll_cpll_v0pll_aupll_p, 0, + RK3588_CLKSEL_CON(111), 14, 2, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(52), 11, GFLAGS), + COMPOSITE(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3588_CLKSEL_CON(112), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(52), 12, GFLAGS), + COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3588_CLKSEL_CON(112), 7, 2, MFLAGS, + RK3588_CLKGATE_CON(52), 13, GFLAGS), + COMPOSITE_NODIV(DCLK_VOP1, "dclk_vop1", dclk_vop1_p, + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3588_CLKSEL_CON(112), 9, 2, MFLAGS, + RK3588_CLKGATE_CON(53), 0, GFLAGS), + COMPOSITE_NODIV(DCLK_VOP2, "dclk_vop2", dclk_vop2_p, + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3588_CLKSEL_CON(112), 11, 2, MFLAGS, + RK3588_CLKGATE_CON(53), 1, GFLAGS), + COMPOSITE(DCLK_VOP3, "dclk_vop3", gpll_cpll_v0pll_aupll_p, 0, + RK3588_CLKSEL_CON(113), 7, 2, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(53), 2, GFLAGS), + GATE(PCLK_DSIHOST0, "pclk_dsihost0", "pclk_vop_root", 0, + RK3588_CLKGATE_CON(53), 4, GFLAGS), + GATE(PCLK_DSIHOST1, "pclk_dsihost1", "pclk_vop_root", 0, + RK3588_CLKGATE_CON(53), 5, GFLAGS), + COMPOSITE(CLK_DSIHOST0, "clk_dsihost0", gpll_cpll_v0pll_spll_p, 0, + RK3588_CLKSEL_CON(114), 7, 2, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(53), 6, GFLAGS), + COMPOSITE(CLK_DSIHOST1, "clk_dsihost1", gpll_cpll_v0pll_spll_p, 0, + RK3588_CLKSEL_CON(115), 7, 2, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(53), 7, GFLAGS), + GATE(CLK_VOP_PMU, "clk_vop_pmu", "xin24m", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(53), 8, GFLAGS), + GATE(ACLK_VOP_DOBY, "aclk_vop_doby", "aclk_vop_root", 0, + RK3588_CLKGATE_CON(53), 10, GFLAGS), + GATE(CLK_USBDP_PHY0_IMMORTAL, "clk_usbdp_phy0_immortal", "xin24m", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(2), 8, GFLAGS), + GATE(CLK_USBDP_PHY1_IMMORTAL, "clk_usbdp_phy1_immortal", "xin24m", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(2), 15, GFLAGS), + + GATE(CLK_REF_PIPE_PHY0_OSC_SRC, "clk_ref_pipe_phy0_osc_src", "xin24m", 0, + RK3588_CLKGATE_CON(77), 0, GFLAGS), + GATE(CLK_REF_PIPE_PHY1_OSC_SRC, "clk_ref_pipe_phy1_osc_src", "xin24m", 0, + RK3588_CLKGATE_CON(77), 1, GFLAGS), + GATE(CLK_REF_PIPE_PHY2_OSC_SRC, "clk_ref_pipe_phy2_osc_src", "xin24m", 0, + RK3588_CLKGATE_CON(77), 2, GFLAGS), + COMPOSITE_NOMUX(CLK_REF_PIPE_PHY0_PLL_SRC, "clk_ref_pipe_phy0_pll_src", "ppll", 0, + RK3588_CLKSEL_CON(176), 0, 6, DFLAGS, + RK3588_CLKGATE_CON(77), 3, GFLAGS), + COMPOSITE_NOMUX(CLK_REF_PIPE_PHY1_PLL_SRC, "clk_ref_pipe_phy1_pll_src", "ppll", 0, + RK3588_CLKSEL_CON(176), 6, 6, DFLAGS, + RK3588_CLKGATE_CON(77), 4, GFLAGS), + COMPOSITE_NOMUX(CLK_REF_PIPE_PHY2_PLL_SRC, "clk_ref_pipe_phy2_pll_src", "ppll", 0, + RK3588_CLKSEL_CON(177), 0, 6, DFLAGS, + RK3588_CLKGATE_CON(77), 5, GFLAGS), + MUX(CLK_REF_PIPE_PHY0, "clk_ref_pipe_phy0", clk_ref_pipe_phy0_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(177), 6, 1, MFLAGS), + MUX(CLK_REF_PIPE_PHY1, "clk_ref_pipe_phy1", clk_ref_pipe_phy1_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(177), 7, 1, MFLAGS), + MUX(CLK_REF_PIPE_PHY2, "clk_ref_pipe_phy2", clk_ref_pipe_phy2_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(177), 8, 1, MFLAGS), + + /* pmu */ + COMPOSITE(CLK_PMU1_300M_SRC, "clk_pmu1_300m_src", pmu_300m_24m_p, 0, + RK3588_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 10, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(0), 3, GFLAGS), + COMPOSITE(CLK_PMU1_400M_SRC, "clk_pmu1_400m_src", pmu_400m_24m_p, 0, + RK3588_PMU_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(0), 4, GFLAGS), + COMPOSITE_NOMUX(CLK_PMU1_50M_SRC, "clk_pmu1_50m_src", "clk_pmu1_400m_src", 0, + RK3588_PMU_CLKSEL_CON(0), 0, 4, DFLAGS, + RK3588_PMU_CLKGATE_CON(0), 0, GFLAGS), + COMPOSITE_NOMUX(CLK_PMU1_100M_SRC, "clk_pmu1_100m_src", "clk_pmu1_400m_src", 0, + RK3588_PMU_CLKSEL_CON(0), 4, 3, DFLAGS, + RK3588_PMU_CLKGATE_CON(0), 1, GFLAGS), + COMPOSITE_NOMUX(CLK_PMU1_200M_SRC, "clk_pmu1_200m_src", "clk_pmu1_400m_src", 0, + RK3588_PMU_CLKSEL_CON(0), 7, 3, DFLAGS, + RK3588_PMU_CLKGATE_CON(0), 2, GFLAGS), + COMPOSITE_NODIV(HCLK_PMU1_ROOT, "hclk_pmu1_root", hclk_pmu1_root_p, CLK_IS_CRITICAL, + RK3588_PMU_CLKSEL_CON(1), 6, 2, MFLAGS, + RK3588_PMU_CLKGATE_CON(0), 5, GFLAGS), + COMPOSITE_NODIV(PCLK_PMU1_ROOT, "pclk_pmu1_root", pmu_100m_50m_24m_src_p, CLK_IS_CRITICAL, + RK3588_PMU_CLKSEL_CON(1), 8, 2, MFLAGS, + RK3588_PMU_CLKGATE_CON(0), 7, GFLAGS), + GATE(PCLK_PMU0_ROOT, "pclk_pmu0_root", "pclk_pmu1_root", CLK_IS_CRITICAL, + RK3588_PMU_CLKGATE_CON(5), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_PMU_CM0_ROOT, "hclk_pmu_cm0_root", hclk_pmu_cm0_root_p, CLK_IS_CRITICAL, + RK3588_PMU_CLKSEL_CON(1), 10, 2, MFLAGS, + RK3588_PMU_CLKGATE_CON(0), 8, GFLAGS), + GATE(CLK_PMU0, "clk_pmu0", "xin24m", CLK_IS_CRITICAL, + RK3588_PMU_CLKGATE_CON(5), 1, GFLAGS), + GATE(PCLK_PMU0, "pclk_pmu0", "pclk_pmu0_root", CLK_IS_CRITICAL, + RK3588_PMU_CLKGATE_CON(5), 2, GFLAGS), + GATE(PCLK_PMU0IOC, "pclk_pmu0ioc", "pclk_pmu0_root", CLK_IS_CRITICAL, + RK3588_PMU_CLKGATE_CON(5), 4, GFLAGS), + GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu0_root", 0, + RK3588_PMU_CLKGATE_CON(5), 5, GFLAGS), + COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0, + RK3588_PMU_CLKSEL_CON(17), 0, 1, MFLAGS, + RK3588_PMU_CLKGATE_CON(5), 6, GFLAGS), + GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pmu0_root", 0, + RK3588_PMU_CLKGATE_CON(2), 1, GFLAGS), + COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", pmu_200m_100m_p, 0, + RK3588_PMU_CLKSEL_CON(3), 6, 1, MFLAGS, + RK3588_PMU_CLKGATE_CON(2), 2, GFLAGS), + GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_pmu1_root", 0, + RK3588_PMU_CLKGATE_CON(2), 7, GFLAGS), + COMPOSITE_NOMUX(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", "cpll", 0, + RK3588_PMU_CLKSEL_CON(5), 2, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(2), 8, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", + CLK_SET_RATE_PARENT, + RK3588_PMU_CLKSEL_CON(6), 0, + RK3588_PMU_CLKGATE_CON(2), 9, GFLAGS, + &rk3588_i2s1_8ch_tx_fracmux), + GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0, + RK3588_PMU_CLKGATE_CON(2), 10, GFLAGS), + COMPOSITE_NOMUX(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", "cpll", 0, + RK3588_PMU_CLKSEL_CON(7), 2, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(2), 11, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", + CLK_SET_RATE_PARENT, + RK3588_PMU_CLKSEL_CON(8), 0, + RK3588_PMU_CLKGATE_CON(2), 12, GFLAGS, + &rk3588_i2s1_8ch_rx_fracmux), + GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0, + RK3588_PMU_CLKGATE_CON(2), 13, GFLAGS), + MUX(I2S1_8CH_MCLKOUT, "i2s1_8ch_mclkout", i2s1_8ch_mclkout_p, CLK_SET_RATE_PARENT, + RK3588_PMU_CLKSEL_CON(9), 2, 2, MFLAGS), + GATE(PCLK_PMU1, "pclk_pmu1", "pclk_pmu0_root", CLK_IS_CRITICAL, + RK3588_PMU_CLKGATE_CON(1), 0, GFLAGS), + GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "clk_pmu0", CLK_IGNORE_UNUSED, + RK3588_PMU_CLKGATE_CON(1), 1, GFLAGS), + GATE(CLK_PMU1, "clk_pmu1", "clk_pmu0", CLK_IS_CRITICAL, + RK3588_PMU_CLKGATE_CON(1), 3, GFLAGS), + GATE(HCLK_PDM0, "hclk_pdm0", "hclk_pmu1_root", 0, + RK3588_PMU_CLKGATE_CON(2), 14, GFLAGS), + COMPOSITE_NODIV(MCLK_PDM0, "mclk_pdm0", mclk_pdm0_p, 0, + RK3588_PMU_CLKSEL_CON(9), 4, 1, MFLAGS, + RK3588_PMU_CLKGATE_CON(2), 15, GFLAGS), + GATE(HCLK_VAD, "hclk_vad", "hclk_pmu1_root", 0, + RK3588_PMU_CLKGATE_CON(3), 0, GFLAGS), + GATE(FCLK_PMU_CM0_CORE, "fclk_pmu_cm0_core", "hclk_pmu_cm0_root", CLK_IS_CRITICAL, + RK3588_PMU_CLKGATE_CON(0), 13, GFLAGS), + COMPOSITE(CLK_PMU_CM0_RTC, "clk_pmu_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITICAL, + RK3588_PMU_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(0), 15, GFLAGS), + GATE(PCLK_PMU1_IOC, "pclk_pmu1_ioc", "pclk_pmu0_root", CLK_IGNORE_UNUSED, + RK3588_PMU_CLKGATE_CON(1), 5, GFLAGS), + GATE(PCLK_PMU1PWM, "pclk_pmu1pwm", "pclk_pmu0_root", 0, + RK3588_PMU_CLKGATE_CON(1), 12, GFLAGS), + COMPOSITE_NODIV(CLK_PMU1PWM, "clk_pmu1pwm", pmu_100m_50m_24m_src_p, 0, + RK3588_PMU_CLKSEL_CON(2), 9, 2, MFLAGS, + RK3588_PMU_CLKGATE_CON(1), 13, GFLAGS), + GATE(CLK_PMU1PWM_CAPTURE, "clk_pmu1pwm_capture", "xin24m", 0, + RK3588_PMU_CLKGATE_CON(1), 14, GFLAGS), + GATE(PCLK_PMU1TIMER, "pclk_pmu1timer", "pclk_pmu0_root", 0, + RK3588_PMU_CLKGATE_CON(1), 8, GFLAGS), + COMPOSITE_NODIV(CLK_PMU1TIMER_ROOT, "clk_pmu1timer_root", pmu_24m_32k_100m_src_p, 0, + RK3588_PMU_CLKSEL_CON(2), 7, 2, MFLAGS, + RK3588_PMU_CLKGATE_CON(1), 9, GFLAGS), + GATE(CLK_PMU1TIMER0, "clk_pmu1timer0", "clk_pmu1timer_root", 0, + RK3588_PMU_CLKGATE_CON(1), 10, GFLAGS), + GATE(CLK_PMU1TIMER1, "clk_pmu1timer1", "clk_pmu1timer_root", 0, + RK3588_PMU_CLKGATE_CON(1), 11, GFLAGS), + COMPOSITE_NOMUX(CLK_UART0_SRC, "clk_uart0_src", "cpll", 0, + RK3588_PMU_CLKSEL_CON(3), 7, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(2), 3, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT, + RK3588_PMU_CLKSEL_CON(4), 0, + RK3588_PMU_CLKGATE_CON(2), 4, GFLAGS, + &rk3588_uart0_fracmux), + GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0, + RK3588_PMU_CLKGATE_CON(2), 5, GFLAGS), + GATE(PCLK_UART0, "pclk_uart0", "pclk_pmu0_root", 0, + RK3588_PMU_CLKGATE_CON(2), 6, GFLAGS), + GATE(PCLK_PMU1WDT, "pclk_pmu1wdt", "pclk_pmu0_root", 0, + RK3588_PMU_CLKGATE_CON(1), 6, GFLAGS), + COMPOSITE_NODIV(TCLK_PMU1WDT, "tclk_pmu1wdt", mux_24m_32k_p, 0, + RK3588_PMU_CLKSEL_CON(2), 6, 1, MFLAGS, + RK3588_PMU_CLKGATE_CON(1), 7, GFLAGS), + COMPOSITE(CLK_CR_PARA, "clk_cr_para", mux_24m_ppll_spll_p, 0, + RK3588_PMU_CLKSEL_CON(15), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(4), 11, GFLAGS), + COMPOSITE(CLK_USB2PHY_HDPTXRXPHY_REF, "clk_usb2phy_hdptxrxphy_ref", mux_24m_ppll_p, + CLK_IS_CRITICAL, + RK3588_PMU_CLKSEL_CON(14), 14, 1, MFLAGS, 9, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(4), 7, GFLAGS), + COMPOSITE(CLK_USBDPPHY_MIPIDCPPHY_REF, "clk_usbdpphy_mipidcpphy_ref", mux_24m_ppll_spll_p, + CLK_IS_CRITICAL, + RK3588_PMU_CLKSEL_CON(14), 7, 2, MFLAGS, 0, 7, DFLAGS, + RK3588_PMU_CLKGATE_CON(4), 3, GFLAGS), + + GATE(CLK_PHY0_REF_ALT_P, "clk_phy0_ref_alt_p", "ppll", 0, + RK3588_PHYREF_ALT_GATE, 0, GFLAGS), + GATE(CLK_PHY0_REF_ALT_M, "clk_phy0_ref_alt_m", "ppll", 0, + RK3588_PHYREF_ALT_GATE, 1, GFLAGS), + GATE(CLK_PHY1_REF_ALT_P, "clk_phy1_ref_alt_p", "ppll", 0, + RK3588_PHYREF_ALT_GATE, 2, GFLAGS), + GATE(CLK_PHY1_REF_ALT_M, "clk_phy1_ref_alt_m", "ppll", 0, + RK3588_PHYREF_ALT_GATE, 3, GFLAGS), + + GATE(HCLK_SPDIFRX0, "hclk_spdifrx0", "hclk_vo1", 0, + RK3588_CLKGATE_CON(63), 12, GFLAGS), + GATE(HCLK_SPDIFRX1, "hclk_spdifrx1", "hclk_vo1", 0, + RK3588_CLKGATE_CON(63), 14, GFLAGS), + GATE(HCLK_SPDIFRX2, "hclk_spdifrx2", "hclk_vo1", 0, + RK3588_CLKGATE_CON(64), 0, GFLAGS), + GATE(HCLK_SPDIF4, "hclk_spdif4", "hclk_vo1", 0, + RK3588_CLKGATE_CON(63), 8, GFLAGS), + GATE(HCLK_SPDIF3, "hclk_spdif3", "hclk_vo1", 0, + RK3588_CLKGATE_CON(63), 4, GFLAGS), + GATE(HCLK_I2S6_8CH, "hclk_i2s6_8ch", "hclk_vo1", 0, + RK3588_CLKGATE_CON(63), 3, GFLAGS), + GATE(HCLK_I2S5_8CH, "hclk_i2s5_8ch", "hclk_vo1", 0, + RK3588_CLKGATE_CON(62), 12, GFLAGS), + GATE(HCLK_I2S9_8CH, "hclk_i2s9_8ch", "hclk_vo1", 0, + RK3588_CLKGATE_CON(65), 0, GFLAGS), + GATE(HCLK_I2S7_8CH, "hclk_i2s7_8ch", "hclk_vo1", 0, + RK3588_CLKGATE_CON(60), 0, GFLAGS), + GATE(HCLK_I2S10_8CH, "hclk_i2s10_8ch", "hclk_vo1", 0, + RK3588_CLKGATE_CON(65), 4, GFLAGS), + GATE(ACLK_HDCP1, "aclk_hdcp1", "aclk_hdcp1_pre", 0, + RK3588_CLKGATE_CON(60), 5, GFLAGS), + GATE(HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1", 0, + RK3588_CLKGATE_CON(60), 6, GFLAGS), + GATE(HCLK_SPDIF5_DP1, "hclk_spdif5_dp1", "hclk_vo0", 0, + RK3588_CLKGATE_CON(57), 7, GFLAGS), + GATE(HCLK_SPDIF2_DP0, "hclk_spdif2_dp0", "hclk_vo0", 0, + RK3588_CLKGATE_CON(57), 2, GFLAGS), + GATE(HCLK_I2S8_8CH, "hclk_i2s8_8ch", "hclk_vo0", 0, + RK3588_CLKGATE_CON(56), 14, GFLAGS), + GATE(HCLK_I2S4_8CH, "hclk_i2s4_8ch", "hclk_vo0", 0, + RK3588_CLKGATE_CON(56), 10, GFLAGS), + GATE(ACLK_HDCP0, "aclk_hdcp0", "aclk_hdcp0_pre", 0, + RK3588_CLKGATE_CON(55), 12, GFLAGS), + GATE(HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0", 0, + RK3588_CLKGATE_CON(55), 13, GFLAGS), + GATE(HCLK_RKVENC1, "hclk_rkvenc1", "hclk_rkvenc1_pre", 0, + RK3588_CLKGATE_CON(48), 4, GFLAGS), + GATE(ACLK_RKVENC1, "aclk_rkvenc1", "aclk_rkvenc1_pre", 0, + RK3588_CLKGATE_CON(48), 5, GFLAGS), + GATE(ACLK_VPU, "aclk_vpu", "aclk_vdpu_low_pre", 0, + RK3588_CLKGATE_CON(44), 8, GFLAGS), + GATE(ACLK_IEP2P0, "aclk_iep2p0", "aclk_vdpu_low_pre", 0, + RK3588_CLKGATE_CON(45), 5, GFLAGS), + GATE(ACLK_JPEG_ENCODER0, "aclk_jpeg_encoder0", "aclk_vdpu_low_pre", 0, + RK3588_CLKGATE_CON(44), 10, GFLAGS), + GATE(ACLK_JPEG_ENCODER1, "aclk_jpeg_encoder1", "aclk_vdpu_low_pre", 0, + RK3588_CLKGATE_CON(44), 12, GFLAGS), + GATE(ACLK_JPEG_ENCODER2, "aclk_jpeg_encoder2", "aclk_vdpu_low_pre", 0, + RK3588_CLKGATE_CON(44), 14, GFLAGS), + GATE(ACLK_JPEG_ENCODER3, "aclk_jpeg_encoder3", "aclk_vdpu_low_pre", 0, + RK3588_CLKGATE_CON(45), 0, GFLAGS), + GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_decoder_pre", 0, + RK3588_CLKGATE_CON(45), 2, GFLAGS), + GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb", 0, + RK3588_CLKGATE_CON(42), 7, GFLAGS), + GATE(HCLK_HOST0, "hclk_host0", "hclk_usb", 0, + RK3588_CLKGATE_CON(42), 10, GFLAGS), + GATE(HCLK_HOST_ARB0, "hclk_host_arb0", "hclk_usb", 0, + RK3588_CLKGATE_CON(42), 11, GFLAGS), + GATE(HCLK_HOST1, "hclk_host1", "hclk_usb", 0, + RK3588_CLKGATE_CON(42), 12, GFLAGS), + GATE(HCLK_HOST_ARB1, "hclk_host_arb1", "hclk_usb", 0, + RK3588_CLKGATE_CON(42), 13, GFLAGS), + GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb", 0, + RK3588_CLKGATE_CON(42), 4, GFLAGS), + MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "scmi_cclk_sd", RK3588_SDMMC_CON0, 1), + MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "scmi_cclk_sd", RK3588_SDMMC_CON1, 1), + GATE(HCLK_SDIO, "hclk_sdio", "hclk_sdio_pre", 0, + RK3588_CLKGATE_CON(75), 2, GFLAGS), + GATE(HCLK_RKVDEC1, "hclk_rkvdec1", "hclk_rkvdec1_pre", 0, + RK3588_CLKGATE_CON(41), 2, GFLAGS), + GATE(ACLK_RKVDEC1, "aclk_rkvdec1", "aclk_rkvdec1_pre", 0, + RK3588_CLKGATE_CON(41), 3, GFLAGS), + GATE(HCLK_RKVDEC0, "hclk_rkvdec0", "hclk_rkvdec0_pre", 0, + RK3588_CLKGATE_CON(40), 3, GFLAGS), + GATE(ACLK_RKVDEC0, "aclk_rkvdec0", "aclk_rkvdec0_pre", 0, + RK3588_CLKGATE_CON(40), 4, GFLAGS), + GATE(CLK_PCIE4L_PIPE, "clk_pcie4l_pipe", "clk_pipe30phy_pipe0_i", 0, + RK3588_CLKGATE_CON(39), 0, GFLAGS), + GATE(CLK_PCIE2L_PIPE, "clk_pcie2l_pipe", "clk_pipe30phy_pipe2_i", 0, + RK3588_CLKGATE_CON(39), 1, GFLAGS), + GATE(CLK_PIPEPHY0_PIPE_G, "clk_pipephy0_pipe_g", "clk_pipephy0_pipe_i", 0, + RK3588_CLKGATE_CON(38), 3, GFLAGS), + GATE(CLK_PIPEPHY1_PIPE_G, "clk_pipephy1_pipe_g", "clk_pipephy1_pipe_i", 0, + RK3588_CLKGATE_CON(38), 4, GFLAGS), + GATE(CLK_PIPEPHY2_PIPE_G, "clk_pipephy2_pipe_g", "clk_pipephy2_pipe_i", 0, + RK3588_CLKGATE_CON(38), 5, GFLAGS), + GATE(CLK_PIPEPHY0_PIPE_ASIC_G, "clk_pipephy0_pipe_asic_g", "clk_pipephy0_pipe_i", 0, + RK3588_CLKGATE_CON(38), 6, GFLAGS), + GATE(CLK_PIPEPHY1_PIPE_ASIC_G, "clk_pipephy1_pipe_asic_g", "clk_pipephy1_pipe_i", 0, + RK3588_CLKGATE_CON(38), 7, GFLAGS), + GATE(CLK_PIPEPHY2_PIPE_ASIC_G, "clk_pipephy2_pipe_asic_g", "clk_pipephy2_pipe_i", 0, + RK3588_CLKGATE_CON(38), 8, GFLAGS), + GATE(CLK_PIPEPHY2_PIPE_U3_G, "clk_pipephy2_pipe_u3_g", "clk_pipephy2_pipe_i", 0, + RK3588_CLKGATE_CON(38), 9, GFLAGS), + GATE(CLK_PCIE1L2_PIPE, "clk_pcie1l2_pipe", "clk_pipephy0_pipe_g", 0, + RK3588_CLKGATE_CON(38), 13, GFLAGS), + GATE(CLK_PCIE1L0_PIPE, "clk_pcie1l0_pipe", "clk_pipephy1_pipe_g", 0, + RK3588_CLKGATE_CON(38), 14, GFLAGS), + GATE(CLK_PCIE1L1_PIPE, "clk_pcie1l1_pipe", "clk_pipephy2_pipe_g", 0, + RK3588_CLKGATE_CON(38), 15, GFLAGS), + GATE(HCLK_SFC, "hclk_sfc", "hclk_nvm", 0, + RK3588_CLKGATE_CON(31), 10, GFLAGS), + GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_nvm", 0, + RK3588_CLKGATE_CON(31), 11, GFLAGS), + GATE(HCLK_EMMC, "hclk_emmc", "hclk_nvm", 0, + RK3588_CLKGATE_CON(31), 4, GFLAGS), + GATE(ACLK_ISP1, "aclk_isp1", "aclk_isp1_pre", 0, + RK3588_CLKGATE_CON(26), 5, GFLAGS), + GATE(HCLK_ISP1, "hclk_isp1", "hclk_isp1_pre", 0, + RK3588_CLKGATE_CON(26), 7, GFLAGS), + GATE(PCLK_AV1, "pclk_av1", "pclk_av1_pre", 0, + RK3588_CLKGATE_CON(68), 5, GFLAGS), + GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0, + RK3588_CLKGATE_CON(68), 2, GFLAGS), + + GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS), + GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS), + GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", 0, RK3588_CLKGATE_CON(31), 2, GFLAGS), + GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS), + GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS), + GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS), + GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 5, GFLAGS), + GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", "aclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 3, GFLAGS), + GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", "hclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 2, GFLAGS), + GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 5, GFLAGS), + GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 6, GFLAGS), + GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS), + GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS), + GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS), + GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", 0, RK3588_CLKGATE_CON(55), 5, GFLAGS), + GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS), + GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 9, GFLAGS), + GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS), + GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS), + GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS), +}; + +static void __init rk3588_clk_init(struct device_node *np) +{ + struct rockchip_clk_provider *ctx; + void __iomem *reg_base; + + reg_base = of_iomap(np, 0); + if (!reg_base) { + pr_err("%s: could not map cru region\n", __func__); + return; + } + + ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); + if (IS_ERR(ctx)) { + pr_err("%s: rockchip clk init failed\n", __func__); + iounmap(reg_base); + return; + } + + rockchip_clk_register_plls(ctx, rk3588_pll_clks, + ARRAY_SIZE(rk3588_pll_clks), + RK3588_GRF_SOC_STATUS0); + + rockchip_clk_register_armclk(ctx, ARMCLK_L, "armclk_l", + mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p), + &rk3588_cpulclk_data, rk3588_cpulclk_rates, + ARRAY_SIZE(rk3588_cpulclk_rates)); + rockchip_clk_register_armclk(ctx, ARMCLK_B01, "armclk_b01", + mux_armclkb01_p, ARRAY_SIZE(mux_armclkb01_p), + &rk3588_cpub0clk_data, rk3588_cpub0clk_rates, + ARRAY_SIZE(rk3588_cpub0clk_rates)); + rockchip_clk_register_armclk(ctx, ARMCLK_B23, "armclk_b23", + mux_armclkb23_p, ARRAY_SIZE(mux_armclkb23_p), + &rk3588_cpub1clk_data, rk3588_cpub1clk_rates, + ARRAY_SIZE(rk3588_cpub1clk_rates)); + + rockchip_clk_register_branches(ctx, rk3588_clk_branches, + ARRAY_SIZE(rk3588_clk_branches)); + + rk3588_rst_init(np, reg_base); + + rockchip_register_restart_notifier(ctx, RK3588_GLB_SRST_FST, NULL); + + rockchip_clk_of_add_provider(np, ctx); +} + +CLK_OF_DECLARE(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_init); + +struct clk_rk3588_inits { + void (*inits)(struct device_node *np); +}; + +static const struct clk_rk3588_inits clk_3588_cru_init = { + .inits = rk3588_clk_init, +}; + +static const struct of_device_id clk_rk3588_match_table[] = { + { + .compatible = "rockchip,rk3588-cru", + .data = &clk_3588_cru_init, + }, + { } +}; + +static int __init clk_rk3588_probe(struct platform_device *pdev) +{ + const struct clk_rk3588_inits *init_data; + struct device *dev = &pdev->dev; + + init_data = device_get_match_data(dev); + if (!init_data) + return -EINVAL; + + if (init_data->inits) + init_data->inits(dev->of_node); + + return 0; +} + +static struct platform_driver clk_rk3588_driver = { + .driver = { + .name = "clk-rk3588", + .of_match_table = clk_rk3588_match_table, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver_probe(clk_rk3588_driver, clk_rk3588_probe); diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index e63d4f20b479..a8646794575a 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -21,7 +21,6 @@ #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include <linux/reboot.h> -#include <linux/rational.h> #include "../clk-fractional-divider.h" #include "clk.h" @@ -198,6 +197,12 @@ static void rockchip_fractional_approximation(struct clk_hw *hw, clk_fractional_divider_general_approximation(hw, rate, parent_rate, m, n); } +static void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, + struct clk *clk, unsigned int id) +{ + ctx->clk_data.clks[id] = clk; +} + static struct clk *rockchip_clk_register_frac_branch( struct rockchip_clk_provider *ctx, const char *name, const char *const *parent_names, u8 num_parents, @@ -401,14 +406,6 @@ void rockchip_clk_of_add_provider(struct device_node *np, } EXPORT_SYMBOL_GPL(rockchip_clk_of_add_provider); -void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, - struct clk *clk, unsigned int id) -{ - if (ctx->clk_data.clks && id) - ctx->clk_data.clks[id] = clk; -} -EXPORT_SYMBOL_GPL(rockchip_clk_add_lookup); - void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx, struct rockchip_pll_clock *list, unsigned int nr_pll, int grf_lock_offset) diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index ee01739e4a7c..758ebaf2236b 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -235,11 +235,58 @@ struct clk; #define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180) #define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200) +#define RK3588_PHP_CRU_BASE 0x8000 +#define RK3588_PMU_CRU_BASE 0x30000 +#define RK3588_BIGCORE0_CRU_BASE 0x50000 +#define RK3588_BIGCORE1_CRU_BASE 0x52000 +#define RK3588_DSU_CRU_BASE 0x58000 + +#define RK3588_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3588_MODE_CON0 0x280 +#define RK3588_B0_PLL_MODE_CON0 (RK3588_BIGCORE0_CRU_BASE + 0x280) +#define RK3588_B1_PLL_MODE_CON0 (RK3588_BIGCORE1_CRU_BASE + 0x280) +#define RK3588_LPLL_MODE_CON0 (RK3588_DSU_CRU_BASE + 0x280) +#define RK3588_CLKSEL_CON(x) ((x) * 0x4 + 0x300) +#define RK3588_CLKGATE_CON(x) ((x) * 0x4 + 0x800) +#define RK3588_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) +#define RK3588_GLB_CNT_TH 0xc00 +#define RK3588_GLB_SRST_FST 0xc08 +#define RK3588_GLB_SRST_SND 0xc0c +#define RK3588_GLB_RST_CON 0xc10 +#define RK3588_GLB_RST_ST 0xc04 +#define RK3588_SDIO_CON0 0xC24 +#define RK3588_SDIO_CON1 0xC28 +#define RK3588_SDMMC_CON0 0xC30 +#define RK3588_SDMMC_CON1 0xC34 + +#define RK3588_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800) +#define RK3588_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0xa00) + +#define RK3588_PMU_PLL_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE) +#define RK3588_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x300) +#define RK3588_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800) +#define RK3588_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0xa00) + +#define RK3588_B0_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE) +#define RK3588_BIGCORE0_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x300) +#define RK3588_BIGCORE0_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800) +#define RK3588_BIGCORE0_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0xa00) +#define RK3588_B1_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE) +#define RK3588_BIGCORE1_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x300) +#define RK3588_BIGCORE1_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800) +#define RK3588_BIGCORE1_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0xa00) +#define RK3588_LPLL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE) +#define RK3588_DSU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x300) +#define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800) +#define RK3588_DSU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00) + enum rockchip_pll_type { pll_rk3036, pll_rk3066, pll_rk3328, pll_rk3399, + pll_rk3588, + pll_rk3588_core, }; #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ @@ -272,6 +319,15 @@ enum rockchip_pll_type { .nb = _nb, \ } +#define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \ +{ \ + .rate = _rate##U, \ + .p = _p, \ + .m = _m, \ + .s = _s, \ + .k = _k, \ +} + /** * struct rockchip_clk_provider - information about clock provider * @reg_base: virtual address for the register base. @@ -307,6 +363,13 @@ struct rockchip_pll_rate_table { unsigned int dsmpd; unsigned int frac; }; + struct { + /* for RK3588 */ + unsigned int m; + unsigned int p; + unsigned int s; + unsigned int k; + }; }; }; @@ -376,11 +439,13 @@ struct rockchip_cpuclk_clksel { u32 val; }; -#define ROCKCHIP_CPUCLK_NUM_DIVIDERS 5 +#define ROCKCHIP_CPUCLK_NUM_DIVIDERS 6 #define ROCKCHIP_CPUCLK_MAX_CORES 4 struct rockchip_cpuclk_rate_table { unsigned long prate; struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; + struct rockchip_cpuclk_clksel pre_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; + struct rockchip_cpuclk_clksel post_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; }; /** @@ -389,6 +454,8 @@ struct rockchip_cpuclk_rate_table { * @div_core_shift[]: cores divider offset used to divide the pll value * @div_core_mask[]: cores divider mask * @num_cores: number of cpu cores + * @mux_core_reg: register offset of the cores select parent + * @mux_core_alt: mux value to select alternate parent * @mux_core_main: mux value to select main parent of core * @mux_core_shift: offset of the core multiplexer * @mux_core_mask: core multiplexer mask @@ -398,6 +465,7 @@ struct rockchip_cpuclk_reg_data { u8 div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES]; u32 div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES]; int num_cores; + int mux_core_reg; u8 mux_core_alt; u8 mux_core_main; u8 mux_core_shift; @@ -905,8 +973,6 @@ struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, void __iomem *base, unsigned long nr_clks); void rockchip_clk_of_add_provider(struct device_node *np, struct rockchip_clk_provider *ctx); -void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, - struct clk *clk, unsigned int id); void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, struct rockchip_clk_branch *list, unsigned int nr_clk); @@ -937,15 +1003,26 @@ struct clk *rockchip_clk_register_halfdiv(const char *name, spinlock_t *lock); #ifdef CONFIG_RESET_CONTROLLER -void rockchip_register_softrst(struct device_node *np, - unsigned int num_regs, - void __iomem *base, u8 flags); +void rockchip_register_softrst_lut(struct device_node *np, + const int *lookup_table, + unsigned int num_regs, + void __iomem *base, u8 flags); #else -static inline void rockchip_register_softrst(struct device_node *np, - unsigned int num_regs, - void __iomem *base, u8 flags) +static inline void rockchip_register_softrst_lut(struct device_node *np, + const int *lookup_table, + unsigned int num_regs, + void __iomem *base, u8 flags) { } #endif +static inline void rockchip_register_softrst(struct device_node *np, + unsigned int num_regs, + void __iomem *base, u8 flags) +{ + return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags); +} + +void rk3588_rst_init(struct device_node *np, void __iomem *reg_base); + #endif diff --git a/drivers/clk/rockchip/rst-rk3588.c b/drivers/clk/rockchip/rst-rk3588.c new file mode 100644 index 000000000000..e855bb8d5413 --- /dev/null +++ b/drivers/clk/rockchip/rst-rk3588.c @@ -0,0 +1,857 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Collabora Ltd. + * Author: Sebastian Reichel <sebastian.reichel@collabora.com> + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <dt-bindings/reset/rockchip,rk3588-cru.h> +#include "clk.h" + +/* 0xFD7C0000 + 0x0A00 */ +#define RK3588_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit) + +/* 0xFD7C8000 + 0x0A00 */ +#define RK3588_PHPTOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit) + +/* 0xFD7D0000 + 0x0A00 */ +#define RK3588_SECURECRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit) + +/* 0xFD7F0000 + 0x0A00 */ +#define RK3588_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit) + +/* mapping table for reset ID to register offset */ +static const int rk3588_register_offset[] = { + /* SOFTRST_CON01 */ + RK3588_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_TOP_BIU, 1, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_CSIPHY0, 1, 6), + RK3588_CRU_RESET_OFFSET(SRST_CSIPHY0, 1, 7), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_P_CSIPHY1, 1, 8), + RK3588_CRU_RESET_OFFSET(SRST_CSIPHY1, 1, 9), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M500_BIU, 1, 15), + + /* SOFTRST_CON02 */ + RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M400_BIU, 2, 0), + RK3588_CRU_RESET_OFFSET(SRST_A_TOP_S200_BIU, 2, 1), + RK3588_CRU_RESET_OFFSET(SRST_A_TOP_S400_BIU, 2, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M300_BIU, 2, 3), + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_INIT, 2, 8), + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_CMN, 2, 9), + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_LANE, 2, 10), + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_PCS, 2, 11), + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_INIT, 2, 15), + + /* SOFTRST_CON03 */ + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_CMN, 3, 0), + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_LANE, 3, 1), + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_PCS, 3, 2), + RK3588_CRU_RESET_OFFSET(SRST_DCPHY0, 3, 11), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY0, 3, 14), + RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY0_GRF, 3, 15), + + /* SOFTRST_CON04 */ + RK3588_CRU_RESET_OFFSET(SRST_DCPHY1, 4, 0), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY1, 4, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY1_GRF, 4, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CDPHY, 4, 5), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CSIPHY, 4, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO3_5, 4, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO6, 4, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_EMMCIO, 4, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_TOP, 4, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_RIGHT, 4, 11), + + /* SOFTRST_CON05 */ + RK3588_CRU_RESET_OFFSET(SRST_P_CRU, 5, 0), + RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2VO1USB, 5, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2CENTER, 5, 8), + RK3588_CRU_RESET_OFFSET(SRST_H_CHANNEL_SECURE2VO1USB, 5, 14), + RK3588_CRU_RESET_OFFSET(SRST_H_CHANNEL_SECURE2CENTER, 5, 15), + + /* SOFTRST_CON06 */ + RK3588_CRU_RESET_OFFSET(SRST_P_CHANNEL_SECURE2VO1USB, 6, 0), + RK3588_CRU_RESET_OFFSET(SRST_P_CHANNEL_SECURE2CENTER, 6, 1), + + /* SOFTRST_CON07 */ + RK3588_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_AUDIO_BIU, 7, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_I2S0_8CH, 7, 4), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_TX, 7, 7), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_RX, 7, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_ACDCDIG, 7, 11), + RK3588_CRU_RESET_OFFSET(SRST_H_I2S2_2CH, 7, 12), + RK3588_CRU_RESET_OFFSET(SRST_H_I2S3_2CH, 7, 13), + + /* SOFTRST_CON08 */ + RK3588_CRU_RESET_OFFSET(SRST_M_I2S2_2CH, 8, 0), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S3_2CH, 8, 3), + RK3588_CRU_RESET_OFFSET(SRST_DAC_ACDCDIG, 8, 4), + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF0, 8, 14), + + /* SOFTRST_CON09 */ + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF0, 9, 1), + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF1, 9, 2), + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF1, 9, 5), + RK3588_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 6), + RK3588_CRU_RESET_OFFSET(SRST_PDM1, 9, 7), + + /* SOFTRST_CON10 */ + RK3588_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 10, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 10, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_GIC, 10, 3), + RK3588_CRU_RESET_OFFSET(SRST_A_GIC_DBG, 10, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_DMAC0, 10, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_DMAC1, 10, 6), + RK3588_CRU_RESET_OFFSET(SRST_A_DMAC2, 10, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_I2C1, 10, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_I2C2, 10, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_I2C3, 10, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_I2C4, 10, 11), + RK3588_CRU_RESET_OFFSET(SRST_P_I2C5, 10, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_I2C6, 10, 13), + RK3588_CRU_RESET_OFFSET(SRST_P_I2C7, 10, 14), + RK3588_CRU_RESET_OFFSET(SRST_P_I2C8, 10, 15), + + /* SOFTRST_CON11 */ + RK3588_CRU_RESET_OFFSET(SRST_I2C1, 11, 0), + RK3588_CRU_RESET_OFFSET(SRST_I2C2, 11, 1), + RK3588_CRU_RESET_OFFSET(SRST_I2C3, 11, 2), + RK3588_CRU_RESET_OFFSET(SRST_I2C4, 11, 3), + RK3588_CRU_RESET_OFFSET(SRST_I2C5, 11, 4), + RK3588_CRU_RESET_OFFSET(SRST_I2C6, 11, 5), + RK3588_CRU_RESET_OFFSET(SRST_I2C7, 11, 6), + RK3588_CRU_RESET_OFFSET(SRST_I2C8, 11, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_CAN0, 11, 8), + RK3588_CRU_RESET_OFFSET(SRST_CAN0, 11, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_CAN1, 11, 10), + RK3588_CRU_RESET_OFFSET(SRST_CAN1, 11, 11), + RK3588_CRU_RESET_OFFSET(SRST_P_CAN2, 11, 12), + RK3588_CRU_RESET_OFFSET(SRST_CAN2, 11, 13), + RK3588_CRU_RESET_OFFSET(SRST_P_SARADC, 11, 14), + + /* SOFTRST_CON12 */ + RK3588_CRU_RESET_OFFSET(SRST_P_TSADC, 12, 0), + RK3588_CRU_RESET_OFFSET(SRST_TSADC, 12, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_UART1, 12, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_UART2, 12, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_UART3, 12, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_UART4, 12, 5), + RK3588_CRU_RESET_OFFSET(SRST_P_UART5, 12, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_UART6, 12, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_UART7, 12, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_UART8, 12, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_UART9, 12, 10), + RK3588_CRU_RESET_OFFSET(SRST_S_UART1, 12, 13), + + /* SOFTRST_CON13 */ + RK3588_CRU_RESET_OFFSET(SRST_S_UART2, 13, 0), + RK3588_CRU_RESET_OFFSET(SRST_S_UART3, 13, 3), + RK3588_CRU_RESET_OFFSET(SRST_S_UART4, 13, 6), + RK3588_CRU_RESET_OFFSET(SRST_S_UART5, 13, 9), + RK3588_CRU_RESET_OFFSET(SRST_S_UART6, 13, 12), + RK3588_CRU_RESET_OFFSET(SRST_S_UART7, 13, 15), + + /* SOFTRST_CON14 */ + RK3588_CRU_RESET_OFFSET(SRST_S_UART8, 14, 2), + RK3588_CRU_RESET_OFFSET(SRST_S_UART9, 14, 5), + RK3588_CRU_RESET_OFFSET(SRST_P_SPI0, 14, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_SPI1, 14, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_SPI2, 14, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_SPI3, 14, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_SPI4, 14, 10), + RK3588_CRU_RESET_OFFSET(SRST_SPI0, 14, 11), + RK3588_CRU_RESET_OFFSET(SRST_SPI1, 14, 12), + RK3588_CRU_RESET_OFFSET(SRST_SPI2, 14, 13), + RK3588_CRU_RESET_OFFSET(SRST_SPI3, 14, 14), + RK3588_CRU_RESET_OFFSET(SRST_SPI4, 14, 15), + + /* SOFTRST_CON15 */ + RK3588_CRU_RESET_OFFSET(SRST_P_WDT0, 15, 0), + RK3588_CRU_RESET_OFFSET(SRST_T_WDT0, 15, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 15, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_PWM1, 15, 3), + RK3588_CRU_RESET_OFFSET(SRST_PWM1, 15, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_PWM2, 15, 6), + RK3588_CRU_RESET_OFFSET(SRST_PWM2, 15, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_PWM3, 15, 9), + RK3588_CRU_RESET_OFFSET(SRST_PWM3, 15, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_BUSTIMER0, 15, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_BUSTIMER1, 15, 13), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER0, 15, 15), + + /* SOFTRST_CON16 */ + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER1, 16, 0), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER2, 16, 1), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER3, 16, 2), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER4, 16, 3), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER5, 16, 4), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER6, 16, 5), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER7, 16, 6), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER8, 16, 7), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER9, 16, 8), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER10, 16, 9), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER11, 16, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX0, 16, 11), + RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX1, 16, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX2, 16, 13), + RK3588_CRU_RESET_OFFSET(SRST_P_GPIO1, 16, 14), + RK3588_CRU_RESET_OFFSET(SRST_GPIO1, 16, 15), + + /* SOFTRST_CON17 */ + RK3588_CRU_RESET_OFFSET(SRST_P_GPIO2, 17, 0), + RK3588_CRU_RESET_OFFSET(SRST_GPIO2, 17, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_GPIO3, 17, 2), + RK3588_CRU_RESET_OFFSET(SRST_GPIO3, 17, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_GPIO4, 17, 4), + RK3588_CRU_RESET_OFFSET(SRST_GPIO4, 17, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_DECOM, 17, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_DECOM, 17, 7), + RK3588_CRU_RESET_OFFSET(SRST_D_DECOM, 17, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_TOP, 17, 9), + RK3588_CRU_RESET_OFFSET(SRST_A_GICADB_GIC2CORE_BUS, 17, 11), + RK3588_CRU_RESET_OFFSET(SRST_P_DFT2APB, 17, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_TOP, 17, 13), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_CDPHY, 17, 14), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_BOT_RIGHT, 17, 15), + + /* SOFTRST_CON18 */ + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_IOC_TOP, 18, 0), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_IOC_RIGHT, 18, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_CSIPHY, 18, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_VCCIO3_5, 18, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_VCCIO6, 18, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_EMMCIO, 18, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 18, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 18, 9), + RK3588_CRU_RESET_OFFSET(SRST_OTPC_NS, 18, 10), + RK3588_CRU_RESET_OFFSET(SRST_OTPC_ARB, 18, 11), + + /* SOFTRST_CON19 */ + RK3588_CRU_RESET_OFFSET(SRST_P_BUSIOC, 19, 0), + RK3588_CRU_RESET_OFFSET(SRST_P_PMUCM0_INTMUX, 19, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_DDRCM0_INTMUX, 19, 5), + + /* SOFTRST_CON20 */ + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH0, 20, 0), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH0, 20, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH0, 20, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH0, 20, 3), + RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH0, 20, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_GRF_CH01, 20, 5), + RK3588_CRU_RESET_OFFSET(SRST_DFI_CH0, 20, 6), + RK3588_CRU_RESET_OFFSET(SRST_SBR_CH0, 20, 7), + RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH0, 20, 8), + RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH0, 20, 9), + RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH0, 20, 10), + RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH0, 20, 11), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH0, 20, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH1, 20, 13), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH1, 20, 14), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH1, 20, 15), + + /* SOFTRST_CON21 */ + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH1, 21, 0), + RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH1, 21, 1), + RK3588_CRU_RESET_OFFSET(SRST_DFI_CH1, 21, 2), + RK3588_CRU_RESET_OFFSET(SRST_SBR_CH1, 21, 3), + RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH1, 21, 4), + RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH1, 21, 5), + RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH1, 21, 6), + RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH1, 21, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH1, 21, 8), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH0, 21, 13), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_RS_MSCH0, 21, 14), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_MSCH0, 21, 15), + + /* SOFTRST_CON22 */ + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_SCRAMBLE0, 22, 0), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_SCRAMBLE0, 22, 1), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH1, 22, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_RS_MSCH1, 22, 3), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_MSCH1, 22, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_SCRAMBLE1, 22, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_SCRAMBLE1, 22, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH0, 22, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH1, 22, 8), + + /* SOFTRST_CON23 */ + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH2, 23, 0), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH2, 23, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH2, 23, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH2, 23, 3), + RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH2, 23, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_GRF_CH23, 23, 5), + RK3588_CRU_RESET_OFFSET(SRST_DFI_CH2, 23, 6), + RK3588_CRU_RESET_OFFSET(SRST_SBR_CH2, 23, 7), + RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH2, 23, 8), + RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH2, 23, 9), + RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH2, 23, 10), + RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH2, 23, 11), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH2, 23, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH3, 23, 13), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH3, 23, 14), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH3, 23, 15), + + /* SOFTRST_CON24 */ + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH3, 24, 0), + RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH3, 24, 1), + RK3588_CRU_RESET_OFFSET(SRST_DFI_CH3, 24, 2), + RK3588_CRU_RESET_OFFSET(SRST_SBR_CH3, 24, 3), + RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH3, 24, 4), + RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH3, 24, 5), + RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH3, 24, 6), + RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH3, 24, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH3, 24, 8), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_MSCH2, 24, 13), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_RS_MSCH2, 24, 14), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_MSCH2, 24, 15), + + /* SOFTRST_CON25 */ + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_SCRAMBLE2, 25, 0), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_SCRAMBLE2, 25, 1), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_MSCH3, 25, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_RS_MSCH3, 25, 3), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_MSCH3, 25, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_SCRAMBLE3, 25, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_SCRAMBLE3, 25, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR23_MSCH2, 25, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR23_MSCH3, 25, 8), + + /* SOFTRST_CON26 */ + RK3588_CRU_RESET_OFFSET(SRST_ISP1, 26, 3), + RK3588_CRU_RESET_OFFSET(SRST_ISP1_VICAP, 26, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_ISP1_BIU, 26, 6), + RK3588_CRU_RESET_OFFSET(SRST_H_ISP1_BIU, 26, 8), + + /* SOFTRST_CON27 */ + RK3588_CRU_RESET_OFFSET(SRST_A_RKNN1, 27, 0), + RK3588_CRU_RESET_OFFSET(SRST_A_RKNN1_BIU, 27, 1), + RK3588_CRU_RESET_OFFSET(SRST_H_RKNN1, 27, 2), + RK3588_CRU_RESET_OFFSET(SRST_H_RKNN1_BIU, 27, 3), + + /* SOFTRST_CON28 */ + RK3588_CRU_RESET_OFFSET(SRST_A_RKNN2, 28, 0), + RK3588_CRU_RESET_OFFSET(SRST_A_RKNN2_BIU, 28, 1), + RK3588_CRU_RESET_OFFSET(SRST_H_RKNN2, 28, 2), + RK3588_CRU_RESET_OFFSET(SRST_H_RKNN2_BIU, 28, 3), + + /* SOFTRST_CON29 */ + RK3588_CRU_RESET_OFFSET(SRST_A_RKNN_DSU0, 29, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 29, 5), + RK3588_CRU_RESET_OFFSET(SRST_P_NPU_TIMER, 29, 6), + RK3588_CRU_RESET_OFFSET(SRST_NPUTIMER0, 29, 8), + RK3588_CRU_RESET_OFFSET(SRST_NPUTIMER1, 29, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_NPU_WDT, 29, 10), + RK3588_CRU_RESET_OFFSET(SRST_T_NPU_WDT, 29, 11), + RK3588_CRU_RESET_OFFSET(SRST_P_NPU_PVTM, 29, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_NPU_GRF, 29, 13), + RK3588_CRU_RESET_OFFSET(SRST_NPU_PVTM, 29, 14), + + /* SOFTRST_CON30 */ + RK3588_CRU_RESET_OFFSET(SRST_NPU_PVTPLL, 30, 0), + RK3588_CRU_RESET_OFFSET(SRST_H_NPU_CM0_BIU, 30, 2), + RK3588_CRU_RESET_OFFSET(SRST_F_NPU_CM0_CORE, 30, 3), + RK3588_CRU_RESET_OFFSET(SRST_T_NPU_CM0_JTAG, 30, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_RKNN0, 30, 6), + RK3588_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 30, 7), + RK3588_CRU_RESET_OFFSET(SRST_H_RKNN0, 30, 8), + RK3588_CRU_RESET_OFFSET(SRST_H_RKNN0_BIU, 30, 9), + + /* SOFTRST_CON31 */ + RK3588_CRU_RESET_OFFSET(SRST_H_NVM_BIU, 31, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_NVM_BIU, 31, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_EMMC, 31, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_EMMC, 31, 5), + RK3588_CRU_RESET_OFFSET(SRST_C_EMMC, 31, 6), + RK3588_CRU_RESET_OFFSET(SRST_B_EMMC, 31, 7), + RK3588_CRU_RESET_OFFSET(SRST_T_EMMC, 31, 8), + RK3588_CRU_RESET_OFFSET(SRST_S_SFC, 31, 9), + RK3588_CRU_RESET_OFFSET(SRST_H_SFC, 31, 10), + RK3588_CRU_RESET_OFFSET(SRST_H_SFC_XIP, 31, 11), + + /* SOFTRST_CON32 */ + RK3588_CRU_RESET_OFFSET(SRST_P_GRF, 32, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_DEC_BIU, 32, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 32, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_PCIE_GRIDGE, 32, 8), + RK3588_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 32, 9), + RK3588_CRU_RESET_OFFSET(SRST_A_GMAC0, 32, 10), + RK3588_CRU_RESET_OFFSET(SRST_A_GMAC1, 32, 11), + RK3588_CRU_RESET_OFFSET(SRST_A_PCIE_BIU, 32, 12), + RK3588_CRU_RESET_OFFSET(SRST_PCIE0_POWER_UP, 32, 13), + RK3588_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 32, 14), + RK3588_CRU_RESET_OFFSET(SRST_PCIE2_POWER_UP, 32, 15), + + /* SOFTRST_CON33 */ + RK3588_CRU_RESET_OFFSET(SRST_PCIE3_POWER_UP, 33, 0), + RK3588_CRU_RESET_OFFSET(SRST_PCIE4_POWER_UP, 33, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_PCIE0, 33, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_PCIE1, 33, 13), + RK3588_CRU_RESET_OFFSET(SRST_P_PCIE2, 33, 14), + RK3588_CRU_RESET_OFFSET(SRST_P_PCIE3, 33, 15), + + /* SOFTRST_CON34 */ + RK3588_CRU_RESET_OFFSET(SRST_P_PCIE4, 34, 0), + RK3588_CRU_RESET_OFFSET(SRST_A_PHP_GIC_ITS, 34, 6), + RK3588_CRU_RESET_OFFSET(SRST_A_MMU_PCIE, 34, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_MMU_PHP, 34, 8), + RK3588_CRU_RESET_OFFSET(SRST_A_MMU_BIU, 34, 9), + + /* SOFTRST_CON35 */ + RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG2, 35, 7), + + /* SOFTRST_CON37 */ + RK3588_CRU_RESET_OFFSET(SRST_PMALIVE0, 37, 4), + RK3588_CRU_RESET_OFFSET(SRST_PMALIVE1, 37, 5), + RK3588_CRU_RESET_OFFSET(SRST_PMALIVE2, 37, 6), + RK3588_CRU_RESET_OFFSET(SRST_A_SATA0, 37, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_SATA1, 37, 8), + RK3588_CRU_RESET_OFFSET(SRST_A_SATA2, 37, 9), + RK3588_CRU_RESET_OFFSET(SRST_RXOOB0, 37, 10), + RK3588_CRU_RESET_OFFSET(SRST_RXOOB1, 37, 11), + RK3588_CRU_RESET_OFFSET(SRST_RXOOB2, 37, 12), + RK3588_CRU_RESET_OFFSET(SRST_ASIC0, 37, 13), + RK3588_CRU_RESET_OFFSET(SRST_ASIC1, 37, 14), + RK3588_CRU_RESET_OFFSET(SRST_ASIC2, 37, 15), + + /* SOFTRST_CON40 */ + RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC_CCU, 40, 2), + RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC0, 40, 3), + RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC0, 40, 4), + RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC0_BIU, 40, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC0_BIU, 40, 6), + RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_CA, 40, 7), + RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_HEVC_CA, 40, 8), + RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_CORE, 40, 9), + + /* SOFTRST_CON41 */ + RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC1, 41, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC1, 41, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC1_BIU, 41, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC1_BIU, 41, 5), + RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_CA, 41, 6), + RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_HEVC_CA, 41, 7), + RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_CORE, 41, 8), + + /* SOFTRST_CON42 */ + RK3588_CRU_RESET_OFFSET(SRST_A_USB_BIU, 42, 2), + RK3588_CRU_RESET_OFFSET(SRST_H_USB_BIU, 42, 3), + RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG0, 42, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG1, 42, 7), + RK3588_CRU_RESET_OFFSET(SRST_H_HOST0, 42, 10), + RK3588_CRU_RESET_OFFSET(SRST_H_HOST_ARB0, 42, 11), + RK3588_CRU_RESET_OFFSET(SRST_H_HOST1, 42, 12), + RK3588_CRU_RESET_OFFSET(SRST_H_HOST_ARB1, 42, 13), + RK3588_CRU_RESET_OFFSET(SRST_A_USB_GRF, 42, 14), + RK3588_CRU_RESET_OFFSET(SRST_C_USB2P0_HOST0, 42, 15), + + /* SOFTRST_CON43 */ + RK3588_CRU_RESET_OFFSET(SRST_C_USB2P0_HOST1, 43, 0), + RK3588_CRU_RESET_OFFSET(SRST_HOST_UTMI0, 43, 1), + RK3588_CRU_RESET_OFFSET(SRST_HOST_UTMI1, 43, 2), + + /* SOFTRST_CON44 */ + RK3588_CRU_RESET_OFFSET(SRST_A_VDPU_BIU, 44, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_VDPU_LOW_BIU, 44, 5), + RK3588_CRU_RESET_OFFSET(SRST_H_VDPU_BIU, 44, 6), + RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER_BIU, 44, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_VPU, 44, 8), + RK3588_CRU_RESET_OFFSET(SRST_H_VPU, 44, 9), + RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER0, 44, 10), + RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER0, 44, 11), + RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER1, 44, 12), + RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER1, 44, 13), + RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER2, 44, 14), + RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER2, 44, 15), + + /* SOFTRST_CON45 */ + RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER3, 45, 0), + RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER3, 45, 1), + RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER, 45, 2), + RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_DECODER, 45, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_IEP2P0, 45, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_IEP2P0, 45, 5), + RK3588_CRU_RESET_OFFSET(SRST_IEP2P0_CORE, 45, 6), + RK3588_CRU_RESET_OFFSET(SRST_H_RGA2, 45, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_RGA2, 45, 8), + RK3588_CRU_RESET_OFFSET(SRST_RGA2_CORE, 45, 9), + RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_0, 45, 10), + RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_0, 45, 11), + RK3588_CRU_RESET_OFFSET(SRST_RGA3_0_CORE, 45, 12), + + /* SOFTRST_CON47 */ + RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC0_BIU, 47, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC0_BIU, 47, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC0, 47, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC0, 47, 5), + RK3588_CRU_RESET_OFFSET(SRST_RKVENC0_CORE, 47, 6), + + /* SOFTRST_CON48 */ + RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC1_BIU, 48, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC1_BIU, 48, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC1, 48, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC1, 48, 5), + RK3588_CRU_RESET_OFFSET(SRST_RKVENC1_CORE, 48, 6), + + /* SOFTRST_CON49 */ + RK3588_CRU_RESET_OFFSET(SRST_A_VI_BIU, 49, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_VI_BIU, 49, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_VI_BIU, 49, 5), + RK3588_CRU_RESET_OFFSET(SRST_D_VICAP, 49, 6), + RK3588_CRU_RESET_OFFSET(SRST_A_VICAP, 49, 7), + RK3588_CRU_RESET_OFFSET(SRST_H_VICAP, 49, 8), + RK3588_CRU_RESET_OFFSET(SRST_ISP0, 49, 10), + RK3588_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 49, 11), + + /* SOFTRST_CON50 */ + RK3588_CRU_RESET_OFFSET(SRST_FISHEYE0, 50, 0), + RK3588_CRU_RESET_OFFSET(SRST_FISHEYE1, 50, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_0, 50, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_1, 50, 5), + RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_2, 50, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 50, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_4, 50, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_5, 50, 9), + + /* SOFTRST_CON51 */ + RK3588_CRU_RESET_OFFSET(SRST_CSIHOST0_VICAP, 51, 4), + RK3588_CRU_RESET_OFFSET(SRST_CSIHOST1_VICAP, 51, 5), + RK3588_CRU_RESET_OFFSET(SRST_CSIHOST2_VICAP, 51, 6), + RK3588_CRU_RESET_OFFSET(SRST_CSIHOST3_VICAP, 51, 7), + RK3588_CRU_RESET_OFFSET(SRST_CSIHOST4_VICAP, 51, 8), + RK3588_CRU_RESET_OFFSET(SRST_CSIHOST5_VICAP, 51, 9), + RK3588_CRU_RESET_OFFSET(SRST_CIFIN, 51, 13), + + /* SOFTRST_CON52 */ + RK3588_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 52, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_VOP_LOW_BIU, 52, 5), + RK3588_CRU_RESET_OFFSET(SRST_H_VOP_BIU, 52, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 52, 7), + RK3588_CRU_RESET_OFFSET(SRST_H_VOP, 52, 8), + RK3588_CRU_RESET_OFFSET(SRST_A_VOP, 52, 9), + RK3588_CRU_RESET_OFFSET(SRST_D_VOP0, 52, 13), + RK3588_CRU_RESET_OFFSET(SRST_D_VOP2HDMI_BRIDGE0, 52, 14), + RK3588_CRU_RESET_OFFSET(SRST_D_VOP2HDMI_BRIDGE1, 52, 15), + + /* SOFTRST_CON53 */ + RK3588_CRU_RESET_OFFSET(SRST_D_VOP1, 53, 0), + RK3588_CRU_RESET_OFFSET(SRST_D_VOP2, 53, 1), + RK3588_CRU_RESET_OFFSET(SRST_D_VOP3, 53, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_VOPGRF, 53, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_DSIHOST0, 53, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_DSIHOST1, 53, 5), + RK3588_CRU_RESET_OFFSET(SRST_DSIHOST0, 53, 6), + RK3588_CRU_RESET_OFFSET(SRST_DSIHOST1, 53, 7), + RK3588_CRU_RESET_OFFSET(SRST_VOP_PMU, 53, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_VOP_CHANNEL_BIU, 53, 9), + + /* SOFTRST_CON55 */ + RK3588_CRU_RESET_OFFSET(SRST_H_VO0_BIU, 55, 5), + RK3588_CRU_RESET_OFFSET(SRST_H_VO0_S_BIU, 55, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 55, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_VO0_S_BIU, 55, 8), + RK3588_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 55, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_VO0GRF, 55, 10), + RK3588_CRU_RESET_OFFSET(SRST_H_HDCP_KEY0, 55, 11), + RK3588_CRU_RESET_OFFSET(SRST_A_HDCP0, 55, 12), + RK3588_CRU_RESET_OFFSET(SRST_H_HDCP0, 55, 13), + RK3588_CRU_RESET_OFFSET(SRST_HDCP0, 55, 15), + + /* SOFTRST_CON56 */ + RK3588_CRU_RESET_OFFSET(SRST_P_TRNG0, 56, 1), + RK3588_CRU_RESET_OFFSET(SRST_DP0, 56, 8), + RK3588_CRU_RESET_OFFSET(SRST_DP1, 56, 9), + RK3588_CRU_RESET_OFFSET(SRST_H_I2S4_8CH, 56, 10), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S4_8CH_TX, 56, 13), + RK3588_CRU_RESET_OFFSET(SRST_H_I2S8_8CH, 56, 14), + + /* SOFTRST_CON57 */ + RK3588_CRU_RESET_OFFSET(SRST_M_I2S8_8CH_TX, 57, 1), + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF2_DP0, 57, 2), + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF2_DP0, 57, 6), + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF5_DP1, 57, 7), + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF5_DP1, 57, 11), + + /* SOFTRST_CON59 */ + RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 59, 6), + RK3588_CRU_RESET_OFFSET(SRST_A_VO1_BIU, 59, 8), + RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_BIU, 59, 9), + RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_S_BIU, 59, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_VOP1_BIU, 59, 11), + RK3588_CRU_RESET_OFFSET(SRST_P_VO1GRF, 59, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_VO1_S_BIU, 59, 13), + + /* SOFTRST_CON60 */ + RK3588_CRU_RESET_OFFSET(SRST_H_I2S7_8CH, 60, 0), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S7_8CH_RX, 60, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_HDCP_KEY1, 60, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1, 60, 5), + RK3588_CRU_RESET_OFFSET(SRST_H_HDCP1, 60, 6), + RK3588_CRU_RESET_OFFSET(SRST_HDCP1, 60, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_TRNG1, 60, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_HDMITX0, 60, 11), + + /* SOFTRST_CON61 */ + RK3588_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 61, 0), + RK3588_CRU_RESET_OFFSET(SRST_P_HDMITX1, 61, 2), + RK3588_CRU_RESET_OFFSET(SRST_HDMITX1_REF, 61, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_HDMIRX, 61, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_HDMIRX, 61, 10), + RK3588_CRU_RESET_OFFSET(SRST_HDMIRX_REF, 61, 11), + + /* SOFTRST_CON62 */ + RK3588_CRU_RESET_OFFSET(SRST_P_EDP0, 62, 0), + RK3588_CRU_RESET_OFFSET(SRST_EDP0_24M, 62, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_EDP1, 62, 3), + RK3588_CRU_RESET_OFFSET(SRST_EDP1_24M, 62, 4), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S5_8CH_TX, 62, 8), + RK3588_CRU_RESET_OFFSET(SRST_H_I2S5_8CH, 62, 12), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S6_8CH_TX, 62, 15), + + /* SOFTRST_CON63 */ + RK3588_CRU_RESET_OFFSET(SRST_M_I2S6_8CH_RX, 63, 2), + RK3588_CRU_RESET_OFFSET(SRST_H_I2S6_8CH, 63, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF3, 63, 4), + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF3, 63, 7), + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF4, 63, 8), + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF4, 63, 11), + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX0, 63, 12), + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX0, 63, 13), + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX1, 63, 14), + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX1, 63, 15), + + /* SOFTRST_CON64 */ + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX2, 64, 0), + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX2, 64, 1), + RK3588_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY0, 64, 12), + RK3588_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY1, 64, 13), + RK3588_CRU_RESET_OFFSET(SRST_VO1_BRIDGE0, 64, 14), + RK3588_CRU_RESET_OFFSET(SRST_VO1_BRIDGE1, 64, 15), + + /* SOFTRST_CON65 */ + RK3588_CRU_RESET_OFFSET(SRST_H_I2S9_8CH, 65, 0), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S9_8CH_RX, 65, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_I2S10_8CH, 65, 4), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S10_8CH_RX, 65, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_S_HDMIRX, 65, 8), + + /* SOFTRST_CON66 */ + RK3588_CRU_RESET_OFFSET(SRST_GPU, 66, 4), + RK3588_CRU_RESET_OFFSET(SRST_SYS_GPU, 66, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_S_GPU_BIU, 66, 8), + RK3588_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 66, 9), + RK3588_CRU_RESET_OFFSET(SRST_A_M1_GPU_BIU, 66, 10), + RK3588_CRU_RESET_OFFSET(SRST_A_M2_GPU_BIU, 66, 11), + RK3588_CRU_RESET_OFFSET(SRST_A_M3_GPU_BIU, 66, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 66, 14), + RK3588_CRU_RESET_OFFSET(SRST_P_GPU_PVTM, 66, 15), + + /* SOFTRST_CON67 */ + RK3588_CRU_RESET_OFFSET(SRST_GPU_PVTM, 67, 0), + RK3588_CRU_RESET_OFFSET(SRST_P_GPU_GRF, 67, 2), + RK3588_CRU_RESET_OFFSET(SRST_GPU_PVTPLL, 67, 3), + RK3588_CRU_RESET_OFFSET(SRST_GPU_JTAG, 67, 4), + + /* SOFTRST_CON68 */ + RK3588_CRU_RESET_OFFSET(SRST_A_AV1_BIU, 68, 1), + RK3588_CRU_RESET_OFFSET(SRST_A_AV1, 68, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_AV1_BIU, 68, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_AV1, 68, 5), + + /* SOFTRST_CON69 */ + RK3588_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 69, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 69, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM, 69, 6), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 69, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S200_BIU, 69, 10), + RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S400_BIU, 69, 11), + RK3588_CRU_RESET_OFFSET(SRST_H_AHB2APB, 69, 12), + RK3588_CRU_RESET_OFFSET(SRST_H_CENTER_BIU, 69, 13), + RK3588_CRU_RESET_OFFSET(SRST_F_DDR_CM0_CORE, 69, 14), + + /* SOFTRST_CON70 */ + RK3588_CRU_RESET_OFFSET(SRST_DDR_TIMER0, 70, 0), + RK3588_CRU_RESET_OFFSET(SRST_DDR_TIMER1, 70, 1), + RK3588_CRU_RESET_OFFSET(SRST_T_WDT_DDR, 70, 2), + RK3588_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 70, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 70, 5), + RK3588_CRU_RESET_OFFSET(SRST_P_AHB2APB, 70, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_WDT, 70, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_TIMER, 70, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 70, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_SHAREMEM, 70, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_BIU, 70, 11), + RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_CHANNEL_BIU, 70, 12), + + /* SOFTRST_CON72 */ + RK3588_CRU_RESET_OFFSET(SRST_P_USBDPGRF0, 72, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_USBDPPHY0, 72, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_USBDPGRF1, 72, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_USBDPPHY1, 72, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_HDPTX0, 72, 5), + RK3588_CRU_RESET_OFFSET(SRST_P_HDPTX1, 72, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_BOT_RIGHT, 72, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U3_0_GRF0, 72, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U3_1_GRF0, 72, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U2_0_GRF0, 72, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U2_1_GRF0, 72, 11), + RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_ROPLL, 72, 12), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_LCPLL, 72, 13), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_HDPTX0, 72, 14), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_HDPTX1_ROPLL, 72, 15), // missing in TRM + + /* SOFTRST_CON73 */ + RK3588_CRU_RESET_OFFSET(SRST_HDPTX1_LCPLL, 73, 0), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_HDPTX1, 73, 1), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_HDMIRXPHY_SET, 73, 2), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0, 73, 3), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_LCPLL, 73, 4), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_ROPLL, 73, 5), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_PCS_HS, 73, 6), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1, 73, 7), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_LCPLL, 73, 8), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_ROPLL, 73, 9), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_PCS_HS, 73, 10), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_HDMIHDP0, 73, 12), + RK3588_CRU_RESET_OFFSET(SRST_HDMIHDP1, 73, 13), + + /* SOFTRST_CON74 */ + RK3588_CRU_RESET_OFFSET(SRST_A_VO1USB_TOP_BIU, 74, 1), + RK3588_CRU_RESET_OFFSET(SRST_H_VO1USB_TOP_BIU, 74, 3), + + /* SOFTRST_CON75 */ + RK3588_CRU_RESET_OFFSET(SRST_H_SDIO_BIU, 75, 1), + RK3588_CRU_RESET_OFFSET(SRST_H_SDIO, 75, 2), + RK3588_CRU_RESET_OFFSET(SRST_SDIO, 75, 3), + + /* SOFTRST_CON76 */ + RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_BIU, 76, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_BIU, 76, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_1, 76, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_1, 76, 5), + RK3588_CRU_RESET_OFFSET(SRST_RGA3_1_CORE, 76, 6), + + /* SOFTRST_CON77 */ + RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY0, 77, 6), + RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY1, 77, 7), + RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY2, 77, 8), + + /* PHPTOPCRU_SOFTRST_CON00 */ + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PHPTOP_CRU, 0, 1), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF0, 0, 2), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF1, 0, 3), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF2, 0, 4), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY0, 0, 5), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY1, 0, 6), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY2, 0, 7), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE3_PHY, 0, 8), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 9), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_PCIE30_PHY, 0, 10), + + /* PMU1CRU_SOFTRST_CON00 */ + RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 0, 10), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_BIU, 0, 11), + RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 0, 12), + RK3588_PMU1CRU_RESET_OFFSET(SRST_F_PMU_CM0_CORE, 0, 13), + RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1_CM0_JTAG, 0, 14), + + /* PMU1CRU_SOFTRST_CON01 */ + RK3588_PMU1CRU_RESET_OFFSET(SRST_DDR_FAIL_SAFE, 1, 1), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 1, 2), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_GRF, 1, 4), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_IOC, 1, 5), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1WDT, 1, 6), + RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 1, 7), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1TIMER, 1, 8), + RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER0, 1, 10), + RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER1, 1, 11), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1PWM, 1, 12), + RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1PWM, 1, 13), + + /* PMU1CRU_SOFTRST_CON02 */ + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_I2C0, 2, 1), + RK3588_PMU1CRU_RESET_OFFSET(SRST_I2C0, 2, 2), + RK3588_PMU1CRU_RESET_OFFSET(SRST_S_UART0, 2, 5), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_UART0, 2, 6), + RK3588_PMU1CRU_RESET_OFFSET(SRST_H_I2S1_8CH, 2, 7), + RK3588_PMU1CRU_RESET_OFFSET(SRST_M_I2S1_8CH_TX, 2, 10), + RK3588_PMU1CRU_RESET_OFFSET(SRST_M_I2S1_8CH_RX, 2, 13), + RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 2, 14), + RK3588_PMU1CRU_RESET_OFFSET(SRST_PDM0, 2, 15), + + /* PMU1CRU_SOFTRST_CON03 */ + RK3588_PMU1CRU_RESET_OFFSET(SRST_H_VAD, 3, 0), + RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_INIT, 3, 11), + RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_CMN, 3, 12), + RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_LANE, 3, 13), + RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_INIT, 3, 15), + + /* PMU1CRU_SOFTRST_CON04 */ + RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_CMN, 4, 0), + RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_LANE, 4, 1), + RK3588_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY0, 4, 3), + RK3588_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY0, 4, 4), + RK3588_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY1, 4, 5), + RK3588_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY1, 4, 6), + RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U3_0, 4, 7), + RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U3_1, 4, 8), + RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U2_0, 4, 9), + RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U2_1, 4, 10), + + /* PMU1CRU_SOFTRST_CON05 */ + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0GRF, 5, 3), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 5, 4), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 5, 5), + RK3588_PMU1CRU_RESET_OFFSET(SRST_GPIO0, 5, 6), + + /* SECURECRU_SOFTRST_CON00 */ + RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_NS_BIU, 0, 10), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_NS_BIU, 0, 11), + RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_S_BIU, 0, 12), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_S_BIU, 0, 13), + RK3588_SECURECRU_RESET_OFFSET(SRST_P_SECURE_S_BIU, 0, 14), + RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_CORE, 0, 15), + + /* SECURECRU_SOFTRST_CON01 */ + RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_PKA, 1, 0), + RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_RNG, 1, 1), + RK3588_SECURECRU_RESET_OFFSET(SRST_A_CRYPTO, 1, 2), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_CRYPTO, 1, 3), + RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_CORE, 1, 9), + RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_RNG, 1, 10), + RK3588_SECURECRU_RESET_OFFSET(SRST_A_KEYLADDER, 1, 11), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_KEYLADDER, 1, 12), + RK3588_SECURECRU_RESET_OFFSET(SRST_P_OTPC_S, 1, 13), + RK3588_SECURECRU_RESET_OFFSET(SRST_OTPC_S, 1, 14), + RK3588_SECURECRU_RESET_OFFSET(SRST_WDT_S, 1, 15), + + /* SECURECRU_SOFTRST_CON02 */ + RK3588_SECURECRU_RESET_OFFSET(SRST_T_WDT_S, 2, 0), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM, 2, 1), + RK3588_SECURECRU_RESET_OFFSET(SRST_A_DCF, 2, 2), + RK3588_SECURECRU_RESET_OFFSET(SRST_P_DCF, 2, 3), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM_NS, 2, 5), + RK3588_SECURECRU_RESET_OFFSET(SRST_P_KEYLADDER, 2, 14), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_S, 2, 15), + + /* SECURECRU_SOFTRST_CON03 */ + RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_NS, 3, 0), + RK3588_SECURECRU_RESET_OFFSET(SRST_D_SDMMC_BUFFER, 3, 1), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC, 3, 2), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC_BUFFER, 3, 3), + RK3588_SECURECRU_RESET_OFFSET(SRST_SDMMC, 3, 4), + RK3588_SECURECRU_RESET_OFFSET(SRST_P_TRNG_CHK, 3, 5), + RK3588_SECURECRU_RESET_OFFSET(SRST_TRNG_S, 3, 6), +}; + +void rk3588_rst_init(struct device_node *np, void __iomem *reg_base) +{ + rockchip_register_softrst_lut(np, + rk3588_register_offset, + ARRAY_SIZE(rk3588_register_offset), + reg_base + RK3588_SOFTRST_CON(0), + ROCKCHIP_SOFTRST_HIWORD_MASK); +} diff --git a/drivers/clk/rockchip/softrst.c b/drivers/clk/rockchip/softrst.c index 5d07266745b8..fd56aaefe6d1 100644 --- a/drivers/clk/rockchip/softrst.c +++ b/drivers/clk/rockchip/softrst.c @@ -12,6 +12,7 @@ struct rockchip_softrst { struct reset_controller_dev rcdev; + const int *lut; void __iomem *reg_base; int num_regs; int num_per_reg; @@ -25,8 +26,13 @@ static int rockchip_softrst_assert(struct reset_controller_dev *rcdev, struct rockchip_softrst *softrst = container_of(rcdev, struct rockchip_softrst, rcdev); - int bank = id / softrst->num_per_reg; - int offset = id % softrst->num_per_reg; + int bank, offset; + + if (softrst->lut) + id = softrst->lut[id]; + + bank = id / softrst->num_per_reg; + offset = id % softrst->num_per_reg; if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) { writel(BIT(offset) | (BIT(offset) << 16), @@ -52,8 +58,13 @@ static int rockchip_softrst_deassert(struct reset_controller_dev *rcdev, struct rockchip_softrst *softrst = container_of(rcdev, struct rockchip_softrst, rcdev); - int bank = id / softrst->num_per_reg; - int offset = id % softrst->num_per_reg; + int bank, offset; + + if (softrst->lut) + id = softrst->lut[id]; + + bank = id / softrst->num_per_reg; + offset = id % softrst->num_per_reg; if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) { writel((BIT(offset) << 16), softrst->reg_base + (bank * 4)); @@ -77,9 +88,10 @@ static const struct reset_control_ops rockchip_softrst_ops = { .deassert = rockchip_softrst_deassert, }; -void rockchip_register_softrst(struct device_node *np, - unsigned int num_regs, - void __iomem *base, u8 flags) +void rockchip_register_softrst_lut(struct device_node *np, + const int *lookup_table, + unsigned int num_regs, + void __iomem *base, u8 flags) { struct rockchip_softrst *softrst; int ret; @@ -91,13 +103,17 @@ void rockchip_register_softrst(struct device_node *np, spin_lock_init(&softrst->lock); softrst->reg_base = base; + softrst->lut = lookup_table; softrst->flags = flags; softrst->num_regs = num_regs; softrst->num_per_reg = (flags & ROCKCHIP_SOFTRST_HIWORD_MASK) ? 16 : 32; softrst->rcdev.owner = THIS_MODULE; - softrst->rcdev.nr_resets = num_regs * softrst->num_per_reg; + if (lookup_table) + softrst->rcdev.nr_resets = num_regs; + else + softrst->rcdev.nr_resets = num_regs * softrst->num_per_reg; softrst->rcdev.ops = &rockchip_softrst_ops; softrst->rcdev.of_node = np; ret = reset_controller_register(&softrst->rcdev); @@ -107,4 +123,4 @@ void rockchip_register_softrst(struct device_node *np, kfree(softrst); } }; -EXPORT_SYMBOL_GPL(rockchip_register_softrst); +EXPORT_SYMBOL_GPL(rockchip_register_softrst_lut); diff --git a/drivers/clk/samsung/clk-exynos-clkout.c b/drivers/clk/samsung/clk-exynos-clkout.c index 273f77d54dab..e6d6cbf8c4e6 100644 --- a/drivers/clk/samsung/clk-exynos-clkout.c +++ b/drivers/clk/samsung/clk-exynos-clkout.c @@ -81,17 +81,19 @@ MODULE_DEVICE_TABLE(of, exynos_clkout_ids); static int exynos_clkout_match_parent_dev(struct device *dev, u32 *mux_mask) { const struct exynos_clkout_variant *variant; + const struct of_device_id *match; if (!dev->parent) { dev_err(dev, "not instantiated from MFD\n"); return -EINVAL; } - variant = of_device_get_match_data(dev->parent); - if (!variant) { + match = of_match_device(exynos_clkout_ids, dev->parent); + if (!match) { dev_err(dev, "cannot match parent device\n"); return -EINVAL; } + variant = match->data; *mux_mask = variant->mux_mask; diff --git a/drivers/clk/samsung/clk-exynos5-subcmu.c b/drivers/clk/samsung/clk-exynos5-subcmu.c index 65c82d922b05..96d74bc250e5 100644 --- a/drivers/clk/samsung/clk-exynos5-subcmu.c +++ b/drivers/clk/samsung/clk-exynos5-subcmu.c @@ -47,10 +47,10 @@ static void exynos5_subcmu_defer_gate(struct samsung_clk_provider *ctx, /* * Pass the needed clock provider context and register sub-CMU clocks * - * NOTE: This function has to be called from the main, OF_CLK_DECLARE- + * NOTE: This function has to be called from the main, CLK_OF_DECLARE- * initialized clock provider driver. This happens very early during boot * process. Then this driver, during core_initcall registers two platform - * drivers: one which binds to the same device-tree node as OF_CLK_DECLARE + * drivers: one which binds to the same device-tree node as CLK_OF_DECLARE * driver and second, for handling its per-domain child-devices. Those * platform drivers are bound to their devices a bit later in arch_initcall, * when OF-core populates all device-tree nodes. diff --git a/drivers/clk/samsung/clk-exynos7885.c b/drivers/clk/samsung/clk-exynos7885.c index 62ce6814f141..0d2a950ed184 100644 --- a/drivers/clk/samsung/clk-exynos7885.c +++ b/drivers/clk/samsung/clk-exynos7885.c @@ -231,7 +231,7 @@ static const struct samsung_div_clock top_div_clks[] __initconst = { CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "fout_shared0_pll", CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), - DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "fout_shared0_pll", + DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2", CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "fout_shared0_pll", CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3), @@ -239,7 +239,7 @@ static const struct samsung_div_clock top_div_clks[] __initconst = { CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "fout_shared1_pll", CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), - DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "fout_shared1_pll", + DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2", CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), /* CORE */ diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index fe383471c5f0..0ff28938943f 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -1583,6 +1583,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, if (ret) { pr_err("%s: failed to register pll clock %s : %d\n", __func__, pll_clk->name, ret); + kfree(pll->rate_table); kfree(pll); return; } diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig index 9132c3c4aa86..b7fde0aadfcb 100644 --- a/drivers/clk/sifive/Kconfig +++ b/drivers/clk/sifive/Kconfig @@ -2,7 +2,8 @@ menuconfig CLK_SIFIVE bool "SiFive SoC driver support" - depends on RISCV || COMPILE_TEST + depends on SOC_SIFIVE || COMPILE_TEST + default SOC_SIFIVE help SoC drivers for SiFive Linux-capable SoCs. @@ -10,6 +11,7 @@ if CLK_SIFIVE config CLK_SIFIVE_PRCI bool "PRCI driver for SiFive SoCs" + default SOC_SIFIVE select RESET_CONTROLLER select RESET_SIMPLE select CLK_ANALOGBITS_WRPLL_CLN28HPC diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c index 53d6e3ec4309..c94b59b80dd4 100644 --- a/drivers/clk/socfpga/clk-gate.c +++ b/drivers/clk/socfpga/clk-gate.c @@ -188,8 +188,10 @@ void __init socfpga_gate_init(struct device_node *node) return; ops = kmemdup(&gateclk_ops, sizeof(gateclk_ops), GFP_KERNEL); - if (WARN_ON(!ops)) + if (WARN_ON(!ops)) { + kfree(socfpga_clk); return; + } rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2); if (rc) @@ -243,6 +245,7 @@ void __init socfpga_gate_init(struct device_node *node) err = clk_hw_register(NULL, hw_clk); if (err) { + kfree(ops); kfree(socfpga_clk); return; } diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c index c192a9141b86..adfa118520c3 100644 --- a/drivers/clk/spear/spear6xx_clock.c +++ b/drivers/clk/spear/spear6xx_clock.c @@ -207,7 +207,7 @@ void __init spear6xx_clk_init(void __iomem *misc_base) clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0, PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "clcd"); + clk_register_clkdev(clk, NULL, "fc200000.clcd"); /* gpt clocks */ clk = clk_register_gpt("gpt0_1_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, @@ -326,13 +326,13 @@ void __init spear6xx_clk_init(void __iomem *misc_base) clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB, SSP0_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "ssp-pl022.0"); + clk_register_clkdev(clk, NULL, "d0100000.spi"); clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB, SSP1_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "ssp-pl022.1"); + clk_register_clkdev(clk, NULL, "d0180000.spi"); clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB, SSP2_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "ssp-pl022.2"); + clk_register_clkdev(clk, NULL, "d8180000.spi"); } diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c index d820292a381d..40df1db102a7 100644 --- a/drivers/clk/st/clkgen-fsyn.c +++ b/drivers/clk/st/clkgen-fsyn.c @@ -1020,9 +1020,10 @@ static void __init st_of_quadfs_setup(struct device_node *np, clk = st_clk_register_quadfs_pll(pll_name, clk_parent_name, datac->data, reg, lock); - if (IS_ERR(clk)) + if (IS_ERR(clk)) { + kfree(lock); goto err_exit; - else + } else pr_debug("%s: parent %s rate %u\n", __clk_get_name(clk), __clk_get_name(clk_get_parent(clk)), diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h index 108eeeedcbf7..345cdbbab362 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h @@ -6,8 +6,8 @@ * Copyright (c) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> */ -#ifndef _CCU_SUN8I_H3_H_ -#define _CCU_SUN8I_H3_H_ +#ifndef _CCU_SUN8I_V3S_H_ +#define _CCU_SUN8I_V3S_H_ #include <dt-bindings/clock/sun8i-v3s-ccu.h> #include <dt-bindings/reset/sun8i-v3s-ccu.h> @@ -51,4 +51,4 @@ #define CLK_PLL_DDR1 74 -#endif /* _CCU_SUN8I_H3_H_ */ +#endif /* _CCU_SUN8I_V3S_H_ */ diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c index ed097c4f780f..0d5b60b123b7 100644 --- a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c +++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c @@ -239,7 +239,14 @@ static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_spdif_parents, static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_spdif_parents, 0x0b4, 16, 2, BIT(31), 0); -/* The BSP header file has a CIR_CFG, but no mod clock uses this definition */ +static const char * const ir_parents[] = { "osc32k", "osc24M" }; +static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir", + ir_parents, 0x0b8, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0x0cc, BIT(1), 0); @@ -355,6 +362,7 @@ static struct ccu_common *suniv_ccu_clks[] = { &mmc1_output_clk.common, &i2s_clk.common, &spdif_clk.common, + &ir_clk.common, &usb_phy0_clk.common, &dram_ve_clk.common, &dram_csi_clk.common, @@ -446,6 +454,7 @@ static struct clk_hw_onecell_data suniv_hw_clks = { [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, [CLK_I2S] = &i2s_clk.common.hw, [CLK_SPDIF] = &spdif_clk.common.hw, + [CLK_IR] = &ir_clk.common.hw, [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, [CLK_DRAM_VE] = &dram_ve_clk.common.hw, [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h index b22484f1bb9a..d56a4316289d 100644 --- a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h +++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h @@ -29,6 +29,6 @@ /* All bus gates, DRAM gates and mod clocks are exported */ -#define CLK_NUMBER (CLK_AVS + 1) +#define CLK_NUMBER (CLK_IR + 1) #endif /* _CCU_SUNIV_F1C100S_H_ */ diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c index dd0709c9c249..93183287c58d 100644 --- a/drivers/clk/ti/apll.c +++ b/drivers/clk/ti/apll.c @@ -160,7 +160,7 @@ static void __init omap_clk_register_apll(void *user, ad->clk_bypass = __clk_get_hw(clk); name = ti_dt_clk_name(node); - clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); + clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name); if (!IS_ERR(clk)) { of_clk_add_provider(node, of_clk_src_simple_get, clk); kfree(init->parent_names); @@ -400,7 +400,7 @@ static void __init of_omap2_apll_setup(struct device_node *node) goto cleanup; name = ti_dt_clk_name(node); - clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); + clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name); if (!IS_ERR(clk)) { of_clk_add_provider(node, of_clk_src_simple_get, clk); kfree(init); diff --git a/drivers/clk/ti/clk-dra7-atl.c b/drivers/clk/ti/clk-dra7-atl.c index ff4d6a951681..d964e3affd42 100644 --- a/drivers/clk/ti/clk-dra7-atl.c +++ b/drivers/clk/ti/clk-dra7-atl.c @@ -163,8 +163,8 @@ static const struct clk_ops atl_clk_ops = { static void __init of_dra7_atl_clock_setup(struct device_node *node) { struct dra7_atl_desc *clk_hw = NULL; + struct clk_parent_data pdata = { .index = 0 }; struct clk_init_data init = { NULL }; - const char **parent_names = NULL; const char *name; struct clk *clk; @@ -188,24 +188,14 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node) goto cleanup; } - parent_names = kzalloc(sizeof(char *), GFP_KERNEL); - - if (!parent_names) - goto cleanup; - - parent_names[0] = of_clk_get_parent_name(node, 0); - - init.parent_names = parent_names; - - clk = ti_clk_register(NULL, &clk_hw->hw, name); + init.parent_data = &pdata; + clk = of_ti_clk_register(node, &clk_hw->hw, name); if (!IS_ERR(clk)) { of_clk_add_provider(node, of_clk_src_simple_get, clk); - kfree(parent_names); return; } cleanup: - kfree(parent_names); kfree(clk_hw); } CLK_OF_DECLARE(dra7_atl_clock, "ti,dra7-atl-clock", of_dra7_atl_clock_setup); diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c index 1dc2f15fb75b..3d636938a739 100644 --- a/drivers/clk/ti/clk.c +++ b/drivers/clk/ti/clk.c @@ -263,7 +263,7 @@ static LIST_HEAD(retry_list); /** * ti_clk_retry_init - retries a failed clock init at later phase - * @node: device not for the clock + * @node: device node for the clock * @user: user data pointer * @func: init function to be called for the clock * @@ -475,7 +475,7 @@ void __init ti_clk_add_aliases(void) clkspec.np = np; clk = of_clk_get_from_provider(&clkspec); - ti_clk_add_alias(NULL, clk, ti_dt_clk_name(np)); + ti_clk_add_alias(clk, ti_dt_clk_name(np)); } } @@ -528,7 +528,6 @@ void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) /** * ti_clk_add_alias - add a clock alias for a TI clock - * @dev: device alias for this clock * @clk: clock handle to create alias for * @con: connection ID for this clock * @@ -536,7 +535,7 @@ void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) * and assigns the data to it. Returns 0 if successful, negative error * value otherwise. */ -int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con) +int ti_clk_add_alias(struct clk *clk, const char *con) { struct clk_lookup *cl; @@ -550,8 +549,6 @@ int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con) if (!cl) return -ENOMEM; - if (dev) - cl->dev_id = dev_name(dev); cl->con_id = con; cl->clk = clk; @@ -561,8 +558,8 @@ int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con) } /** - * ti_clk_register - register a TI clock to the common clock framework - * @dev: device for this clock + * of_ti_clk_register - register a TI clock to the common clock framework + * @node: device node for this clock * @hw: hardware clock handle * @con: connection ID for this clock * @@ -570,17 +567,18 @@ int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con) * alias for it. Returns a handle to the registered clock if successful, * ERR_PTR value in failure. */ -struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw, - const char *con) +struct clk *of_ti_clk_register(struct device_node *node, struct clk_hw *hw, + const char *con) { struct clk *clk; int ret; - clk = clk_register(dev, hw); - if (IS_ERR(clk)) - return clk; + ret = of_clk_hw_register(node, hw); + if (ret) + return ERR_PTR(ret); - ret = ti_clk_add_alias(dev, clk, con); + clk = hw->clk; + ret = ti_clk_add_alias(clk, con); if (ret) { clk_unregister(clk); return ERR_PTR(ret); @@ -590,8 +588,8 @@ struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw, } /** - * ti_clk_register_omap_hw - register a clk_hw_omap to the clock framework - * @dev: device for this clock + * of_ti_clk_register_omap_hw - register a clk_hw_omap to the clock framework + * @node: device node for this clock * @hw: hardware clock handle * @con: connection ID for this clock * @@ -600,13 +598,13 @@ struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw, * Returns a handle to the registered clock if successful, ERR_PTR value * in failure. */ -struct clk *ti_clk_register_omap_hw(struct device *dev, struct clk_hw *hw, - const char *con) +struct clk *of_ti_clk_register_omap_hw(struct device_node *node, + struct clk_hw *hw, const char *con) { struct clk *clk; struct clk_hw_omap *oclk; - clk = ti_clk_register(dev, hw, con); + clk = of_ti_clk_register(node, hw, con); if (IS_ERR(clk)) return clk; diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c index ae5862879417..f73f402ff7de 100644 --- a/drivers/clk/ti/clkctrl.c +++ b/drivers/clk/ti/clkctrl.c @@ -305,7 +305,7 @@ _ti_clkctrl_clk_register(struct omap_clkctrl_provider *provider, init.ops = ops; init.flags = 0; - clk = ti_clk_register(NULL, clk_hw, init.name); + clk = of_ti_clk_register(node, clk_hw, init.name); if (IS_ERR_OR_NULL(clk)) { ret = -EINVAL; goto cleanup; @@ -682,7 +682,7 @@ clkdm_found: init.ops = &omap4_clkctrl_clk_ops; hw->hw.init = &init; - clk = ti_clk_register_omap_hw(NULL, &hw->hw, init.name); + clk = of_ti_clk_register_omap_hw(node, &hw->hw, init.name); if (IS_ERR_OR_NULL(clk)) goto cleanup; diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index 37ab53339a9b..16a9f7c2280a 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -199,12 +199,12 @@ extern const struct omap_clkctrl_data dm816_clkctrl_data[]; typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *); -struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw, - const char *con); -struct clk *ti_clk_register_omap_hw(struct device *dev, struct clk_hw *hw, - const char *con); +struct clk *of_ti_clk_register(struct device_node *node, struct clk_hw *hw, + const char *con); +struct clk *of_ti_clk_register_omap_hw(struct device_node *node, + struct clk_hw *hw, const char *con); const char *ti_dt_clk_name(struct device_node *np); -int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con); +int ti_clk_add_alias(struct clk *clk, const char *con); void ti_clk_add_aliases(void); void ti_clk_latch(struct clk_omap_reg *reg, s8 shift); diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c index 77b771dd050a..b85382c370f7 100644 --- a/drivers/clk/ti/composite.c +++ b/drivers/clk/ti/composite.c @@ -176,7 +176,7 @@ static void __init _register_composite(void *user, &ti_composite_gate_ops, 0); if (!IS_ERR(clk)) { - ret = ti_clk_add_alias(NULL, clk, name); + ret = ti_clk_add_alias(clk, name); if (ret) { clk_unregister(clk); goto cleanup; diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c index 488d3da60c31..768a1f3398b4 100644 --- a/drivers/clk/ti/divider.c +++ b/drivers/clk/ti/divider.c @@ -326,7 +326,7 @@ static struct clk *_register_divider(struct device_node *node, div->hw.init = &init; /* register the clock */ - clk = ti_clk_register(NULL, &div->hw, name); + clk = of_ti_clk_register(node, &div->hw, name); if (IS_ERR(clk)) kfree(div); diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c index 8ed43bc6b7cc..403ec81f561b 100644 --- a/drivers/clk/ti/dpll.c +++ b/drivers/clk/ti/dpll.c @@ -187,7 +187,7 @@ static void __init _register_dpll(void *user, /* register the clock */ name = ti_dt_clk_name(node); - clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); + clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name); if (!IS_ERR(clk)) { of_clk_add_provider(node, of_clk_src_simple_get, clk); @@ -259,7 +259,7 @@ static void _register_dpll_x2(struct device_node *node, #endif /* register the clock */ - clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); + clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name); if (IS_ERR(clk)) kfree(clk_hw); diff --git a/drivers/clk/ti/fixed-factor.c b/drivers/clk/ti/fixed-factor.c index c80cee0f5d3d..c102c5320168 100644 --- a/drivers/clk/ti/fixed-factor.c +++ b/drivers/clk/ti/fixed-factor.c @@ -54,7 +54,7 @@ static void __init of_ti_fixed_factor_clk_setup(struct device_node *node) if (!IS_ERR(clk)) { of_clk_add_provider(node, of_clk_src_simple_get, clk); of_ti_clk_autoidle_setup(node); - ti_clk_add_alias(NULL, clk, clk_name); + ti_clk_add_alias(clk, clk_name); } } CLK_OF_DECLARE(ti_fixed_factor_clk, "ti,fixed-factor-clock", diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c index 307702921431..8e477d50d0fd 100644 --- a/drivers/clk/ti/gate.c +++ b/drivers/clk/ti/gate.c @@ -85,7 +85,7 @@ static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *hw) return ret; } -static struct clk *_register_gate(struct device *dev, const char *name, +static struct clk *_register_gate(struct device_node *node, const char *name, const char *parent_name, unsigned long flags, struct clk_omap_reg *reg, u8 bit_idx, u8 clk_gate_flags, const struct clk_ops *ops, @@ -115,7 +115,7 @@ static struct clk *_register_gate(struct device *dev, const char *name, init.flags = flags; - clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); + clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name); if (IS_ERR(clk)) kfree(clk_hw); @@ -158,7 +158,7 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node, clk_gate_flags |= INVERT_ENABLE; name = ti_dt_clk_name(node); - clk = _register_gate(NULL, name, parent_name, flags, ®, + clk = _register_gate(node, name, parent_name, flags, ®, enable_bit, clk_gate_flags, ops, hw_ops); if (!IS_ERR(clk)) diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c index f47beeea211e..172301c646f8 100644 --- a/drivers/clk/ti/interface.c +++ b/drivers/clk/ti/interface.c @@ -24,7 +24,8 @@ static const struct clk_ops ti_interface_clk_ops = { .is_enabled = &omap2_dflt_clk_is_enabled, }; -static struct clk *_register_interface(struct device *dev, const char *name, +static struct clk *_register_interface(struct device_node *node, + const char *name, const char *parent_name, struct clk_omap_reg *reg, u8 bit_idx, const struct clk_hw_omap_ops *ops) @@ -49,7 +50,7 @@ static struct clk *_register_interface(struct device *dev, const char *name, init.num_parents = 1; init.parent_names = &parent_name; - clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); + clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name); if (IS_ERR(clk)) kfree(clk_hw); @@ -80,7 +81,7 @@ static void __init _of_ti_interface_clk_setup(struct device_node *node, } name = ti_dt_clk_name(node); - clk = _register_interface(NULL, name, parent_name, ®, + clk = _register_interface(node, name, parent_name, ®, enable_bit, ops); if (!IS_ERR(clk)) diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c index 46b45b3e8319..1ebafa386be6 100644 --- a/drivers/clk/ti/mux.c +++ b/drivers/clk/ti/mux.c @@ -118,7 +118,7 @@ const struct clk_ops ti_clk_mux_ops = { .restore_context = clk_mux_restore_context, }; -static struct clk *_register_mux(struct device *dev, const char *name, +static struct clk *_register_mux(struct device_node *node, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, struct clk_omap_reg *reg, u8 shift, u32 mask, @@ -148,7 +148,7 @@ static struct clk *_register_mux(struct device *dev, const char *name, mux->table = table; mux->hw.init = &init; - clk = ti_clk_register(dev, &mux->hw, name); + clk = of_ti_clk_register(node, &mux->hw, name); if (IS_ERR(clk)) kfree(mux); @@ -207,7 +207,7 @@ static void of_mux_clk_setup(struct device_node *node) mask = (1 << fls(mask)) - 1; name = ti_dt_clk_name(node); - clk = _register_mux(NULL, name, parent_names, num_parents, + clk = _register_mux(node, name, parent_names, num_parents, flags, ®, shift, mask, latch, clk_mux_flags, NULL); diff --git a/drivers/clk/visconti/pll.c b/drivers/clk/visconti/pll.c index a484cb945d67..1f3234f22667 100644 --- a/drivers/clk/visconti/pll.c +++ b/drivers/clk/visconti/pll.c @@ -277,6 +277,7 @@ static struct clk_hw *visconti_register_pll(struct visconti_pll_provider *ctx, ret = clk_hw_register(NULL, &pll->hw); if (ret) { pr_err("failed to register pll clock %s : %d\n", name, ret); + kfree(pll->rate_table); kfree(pll); pll_hw_clk = ERR_PTR(ret); } diff --git a/drivers/clk/x86/Kconfig b/drivers/clk/x86/Kconfig index 69642e15fcc1..ced99e082e3d 100644 --- a/drivers/clk/x86/Kconfig +++ b/drivers/clk/x86/Kconfig @@ -1,8 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-only config CLK_LGM_CGU depends on OF && HAS_IOMEM && (X86 || COMPILE_TEST) + select MFD_SYSCON select OF_EARLY_FLATTREE bool "Clock driver for Lightning Mountain(LGM) platform" help - Clock Generation Unit(CGU) driver for Intel Lightning Mountain(LGM) - network processor SoC. + Clock Generation Unit(CGU) driver for MaxLinear's x86 based + Lightning Mountain(LGM) network processor SoC. diff --git a/drivers/clk/x86/clk-cgu-pll.c b/drivers/clk/x86/clk-cgu-pll.c index 3179557b5f78..409dbf55f4ca 100644 --- a/drivers/clk/x86/clk-cgu-pll.c +++ b/drivers/clk/x86/clk-cgu-pll.c @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* + * Copyright (C) 2020-2022 MaxLinear, Inc. * Copyright (C) 2020 Intel Corporation. - * Zhu YiXin <yixin.zhu@intel.com> - * Rahul Tanwar <rahul.tanwar@intel.com> + * Zhu Yixin <yzhu@maxlinear.com> + * Rahul Tanwar <rtanwar@maxlinear.com> */ #include <linux/clk-provider.h> @@ -40,13 +41,10 @@ static unsigned long lgm_pll_recalc_rate(struct clk_hw *hw, unsigned long prate) { struct lgm_clk_pll *pll = to_lgm_clk_pll(hw); unsigned int div, mult, frac; - unsigned long flags; - spin_lock_irqsave(&pll->lock, flags); mult = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12); div = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 18, 6); frac = lgm_get_clk_val(pll->membase, pll->reg, 2, 24); - spin_unlock_irqrestore(&pll->lock, flags); if (pll->type == TYPE_LJPLL) div *= 4; @@ -57,12 +55,9 @@ static unsigned long lgm_pll_recalc_rate(struct clk_hw *hw, unsigned long prate) static int lgm_pll_is_enabled(struct clk_hw *hw) { struct lgm_clk_pll *pll = to_lgm_clk_pll(hw); - unsigned long flags; unsigned int ret; - spin_lock_irqsave(&pll->lock, flags); ret = lgm_get_clk_val(pll->membase, pll->reg, 0, 1); - spin_unlock_irqrestore(&pll->lock, flags); return ret; } @@ -70,15 +65,13 @@ static int lgm_pll_is_enabled(struct clk_hw *hw) static int lgm_pll_enable(struct clk_hw *hw) { struct lgm_clk_pll *pll = to_lgm_clk_pll(hw); - unsigned long flags; u32 val; int ret; - spin_lock_irqsave(&pll->lock, flags); lgm_set_clk_val(pll->membase, pll->reg, 0, 1, 1); - ret = readl_poll_timeout_atomic(pll->membase + pll->reg, - val, (val & 0x1), 1, 100); - spin_unlock_irqrestore(&pll->lock, flags); + ret = regmap_read_poll_timeout_atomic(pll->membase, pll->reg, + val, (val & 0x1), 1, 100); + return ret; } @@ -86,11 +79,8 @@ static int lgm_pll_enable(struct clk_hw *hw) static void lgm_pll_disable(struct clk_hw *hw) { struct lgm_clk_pll *pll = to_lgm_clk_pll(hw); - unsigned long flags; - spin_lock_irqsave(&pll->lock, flags); lgm_set_clk_val(pll->membase, pll->reg, 0, 1, 0); - spin_unlock_irqrestore(&pll->lock, flags); } static const struct clk_ops lgm_pll_ops = { @@ -121,7 +111,6 @@ lgm_clk_register_pll(struct lgm_clk_provider *ctx, return ERR_PTR(-ENOMEM); pll->membase = ctx->membase; - pll->lock = ctx->lock; pll->reg = list->reg; pll->flags = list->flags; pll->type = list->type; diff --git a/drivers/clk/x86/clk-cgu.c b/drivers/clk/x86/clk-cgu.c index 33de600e0c38..89b53f280aee 100644 --- a/drivers/clk/x86/clk-cgu.c +++ b/drivers/clk/x86/clk-cgu.c @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* + * Copyright (C) 2020-2022 MaxLinear, Inc. * Copyright (C) 2020 Intel Corporation. - * Zhu YiXin <yixin.zhu@intel.com> - * Rahul Tanwar <rahul.tanwar@intel.com> + * Zhu Yixin <yzhu@maxlinear.com> + * Rahul Tanwar <rtanwar@maxlinear.com> */ #include <linux/clk-provider.h> #include <linux/device.h> @@ -24,14 +25,10 @@ static struct clk_hw *lgm_clk_register_fixed(struct lgm_clk_provider *ctx, const struct lgm_clk_branch *list) { - unsigned long flags; - if (list->div_flags & CLOCK_FLAG_VAL_INIT) { - spin_lock_irqsave(&ctx->lock, flags); + if (list->div_flags & CLOCK_FLAG_VAL_INIT) lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, list->div_width, list->div_val); - spin_unlock_irqrestore(&ctx->lock, flags); - } return clk_hw_register_fixed_rate(NULL, list->name, list->parent_data[0].name, @@ -41,33 +38,27 @@ static struct clk_hw *lgm_clk_register_fixed(struct lgm_clk_provider *ctx, static u8 lgm_clk_mux_get_parent(struct clk_hw *hw) { struct lgm_clk_mux *mux = to_lgm_clk_mux(hw); - unsigned long flags; u32 val; - spin_lock_irqsave(&mux->lock, flags); if (mux->flags & MUX_CLK_SW) val = mux->reg; else val = lgm_get_clk_val(mux->membase, mux->reg, mux->shift, mux->width); - spin_unlock_irqrestore(&mux->lock, flags); return clk_mux_val_to_index(hw, NULL, mux->flags, val); } static int lgm_clk_mux_set_parent(struct clk_hw *hw, u8 index) { struct lgm_clk_mux *mux = to_lgm_clk_mux(hw); - unsigned long flags; u32 val; val = clk_mux_index_to_val(NULL, mux->flags, index); - spin_lock_irqsave(&mux->lock, flags); if (mux->flags & MUX_CLK_SW) mux->reg = val; else lgm_set_clk_val(mux->membase, mux->reg, mux->shift, mux->width, val); - spin_unlock_irqrestore(&mux->lock, flags); return 0; } @@ -90,7 +81,7 @@ static struct clk_hw * lgm_clk_register_mux(struct lgm_clk_provider *ctx, const struct lgm_clk_branch *list) { - unsigned long flags, cflags = list->mux_flags; + unsigned long cflags = list->mux_flags; struct device *dev = ctx->dev; u8 shift = list->mux_shift; u8 width = list->mux_width; @@ -111,7 +102,6 @@ lgm_clk_register_mux(struct lgm_clk_provider *ctx, init.num_parents = list->num_parents; mux->membase = ctx->membase; - mux->lock = ctx->lock; mux->reg = reg; mux->shift = shift; mux->width = width; @@ -123,11 +113,8 @@ lgm_clk_register_mux(struct lgm_clk_provider *ctx, if (ret) return ERR_PTR(ret); - if (cflags & CLOCK_FLAG_VAL_INIT) { - spin_lock_irqsave(&mux->lock, flags); + if (cflags & CLOCK_FLAG_VAL_INIT) lgm_set_clk_val(mux->membase, reg, shift, width, list->mux_val); - spin_unlock_irqrestore(&mux->lock, flags); - } return hw; } @@ -136,13 +123,10 @@ static unsigned long lgm_clk_divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct lgm_clk_divider *divider = to_lgm_clk_divider(hw); - unsigned long flags; unsigned int val; - spin_lock_irqsave(÷r->lock, flags); val = lgm_get_clk_val(divider->membase, divider->reg, divider->shift, divider->width); - spin_unlock_irqrestore(÷r->lock, flags); return divider_recalc_rate(hw, parent_rate, val, divider->table, divider->flags, divider->width); @@ -163,7 +147,6 @@ lgm_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) { struct lgm_clk_divider *divider = to_lgm_clk_divider(hw); - unsigned long flags; int value; value = divider_get_val(rate, prate, divider->table, @@ -171,10 +154,8 @@ lgm_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, if (value < 0) return value; - spin_lock_irqsave(÷r->lock, flags); lgm_set_clk_val(divider->membase, divider->reg, divider->shift, divider->width, value); - spin_unlock_irqrestore(÷r->lock, flags); return 0; } @@ -182,12 +163,10 @@ lgm_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, static int lgm_clk_divider_enable_disable(struct clk_hw *hw, int enable) { struct lgm_clk_divider *div = to_lgm_clk_divider(hw); - unsigned long flags; - spin_lock_irqsave(&div->lock, flags); - lgm_set_clk_val(div->membase, div->reg, div->shift_gate, - div->width_gate, enable); - spin_unlock_irqrestore(&div->lock, flags); + if (div->flags != DIV_CLK_NO_MASK) + lgm_set_clk_val(div->membase, div->reg, div->shift_gate, + div->width_gate, enable); return 0; } @@ -213,7 +192,7 @@ static struct clk_hw * lgm_clk_register_divider(struct lgm_clk_provider *ctx, const struct lgm_clk_branch *list) { - unsigned long flags, cflags = list->div_flags; + unsigned long cflags = list->div_flags; struct device *dev = ctx->dev; struct lgm_clk_divider *div; struct clk_init_data init = {}; @@ -236,7 +215,6 @@ lgm_clk_register_divider(struct lgm_clk_provider *ctx, init.num_parents = 1; div->membase = ctx->membase; - div->lock = ctx->lock; div->reg = reg; div->shift = shift; div->width = width; @@ -251,11 +229,8 @@ lgm_clk_register_divider(struct lgm_clk_provider *ctx, if (ret) return ERR_PTR(ret); - if (cflags & CLOCK_FLAG_VAL_INIT) { - spin_lock_irqsave(&div->lock, flags); + if (cflags & CLOCK_FLAG_VAL_INIT) lgm_set_clk_val(div->membase, reg, shift, width, list->div_val); - spin_unlock_irqrestore(&div->lock, flags); - } return hw; } @@ -264,7 +239,6 @@ static struct clk_hw * lgm_clk_register_fixed_factor(struct lgm_clk_provider *ctx, const struct lgm_clk_branch *list) { - unsigned long flags; struct clk_hw *hw; hw = clk_hw_register_fixed_factor(ctx->dev, list->name, @@ -273,12 +247,9 @@ lgm_clk_register_fixed_factor(struct lgm_clk_provider *ctx, if (IS_ERR(hw)) return ERR_CAST(hw); - if (list->div_flags & CLOCK_FLAG_VAL_INIT) { - spin_lock_irqsave(&ctx->lock, flags); + if (list->div_flags & CLOCK_FLAG_VAL_INIT) lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, list->div_width, list->div_val); - spin_unlock_irqrestore(&ctx->lock, flags); - } return hw; } @@ -286,13 +257,10 @@ lgm_clk_register_fixed_factor(struct lgm_clk_provider *ctx, static int lgm_clk_gate_enable(struct clk_hw *hw) { struct lgm_clk_gate *gate = to_lgm_clk_gate(hw); - unsigned long flags; unsigned int reg; - spin_lock_irqsave(&gate->lock, flags); reg = GATE_HW_REG_EN(gate->reg); lgm_set_clk_val(gate->membase, reg, gate->shift, 1, 1); - spin_unlock_irqrestore(&gate->lock, flags); return 0; } @@ -300,25 +268,19 @@ static int lgm_clk_gate_enable(struct clk_hw *hw) static void lgm_clk_gate_disable(struct clk_hw *hw) { struct lgm_clk_gate *gate = to_lgm_clk_gate(hw); - unsigned long flags; unsigned int reg; - spin_lock_irqsave(&gate->lock, flags); reg = GATE_HW_REG_DIS(gate->reg); lgm_set_clk_val(gate->membase, reg, gate->shift, 1, 1); - spin_unlock_irqrestore(&gate->lock, flags); } static int lgm_clk_gate_is_enabled(struct clk_hw *hw) { struct lgm_clk_gate *gate = to_lgm_clk_gate(hw); unsigned int reg, ret; - unsigned long flags; - spin_lock_irqsave(&gate->lock, flags); reg = GATE_HW_REG_STAT(gate->reg); ret = lgm_get_clk_val(gate->membase, reg, gate->shift, 1); - spin_unlock_irqrestore(&gate->lock, flags); return ret; } @@ -333,7 +295,7 @@ static struct clk_hw * lgm_clk_register_gate(struct lgm_clk_provider *ctx, const struct lgm_clk_branch *list) { - unsigned long flags, cflags = list->gate_flags; + unsigned long cflags = list->gate_flags; const char *pname = list->parent_data[0].name; struct device *dev = ctx->dev; u8 shift = list->gate_shift; @@ -354,7 +316,6 @@ lgm_clk_register_gate(struct lgm_clk_provider *ctx, init.num_parents = pname ? 1 : 0; gate->membase = ctx->membase; - gate->lock = ctx->lock; gate->reg = reg; gate->shift = shift; gate->flags = cflags; @@ -366,9 +327,7 @@ lgm_clk_register_gate(struct lgm_clk_provider *ctx, return ERR_PTR(ret); if (cflags & CLOCK_FLAG_VAL_INIT) { - spin_lock_irqsave(&gate->lock, flags); lgm_set_clk_val(gate->membase, reg, shift, 1, list->gate_val); - spin_unlock_irqrestore(&gate->lock, flags); } return hw; @@ -396,8 +355,22 @@ int lgm_clk_register_branches(struct lgm_clk_provider *ctx, hw = lgm_clk_register_fixed_factor(ctx, list); break; case CLK_TYPE_GATE: - hw = lgm_clk_register_gate(ctx, list); + if (list->gate_flags & GATE_CLK_HW) { + hw = lgm_clk_register_gate(ctx, list); + } else { + /* + * GATE_CLKs can be controlled either from + * CGU clk driver i.e. this driver or directly + * from power management driver/daemon. It is + * dependent on the power policy/profile requirements + * of the end product. To override control of gate + * clks from this driver, provide NULL for this index + * of gate clk provider. + */ + hw = NULL; + } break; + default: dev_err(ctx->dev, "invalid clk type\n"); return -EINVAL; @@ -443,24 +416,18 @@ lgm_clk_ddiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) static int lgm_clk_ddiv_enable(struct clk_hw *hw) { struct lgm_clk_ddiv *ddiv = to_lgm_clk_ddiv(hw); - unsigned long flags; - spin_lock_irqsave(&ddiv->lock, flags); lgm_set_clk_val(ddiv->membase, ddiv->reg, ddiv->shift_gate, ddiv->width_gate, 1); - spin_unlock_irqrestore(&ddiv->lock, flags); return 0; } static void lgm_clk_ddiv_disable(struct clk_hw *hw) { struct lgm_clk_ddiv *ddiv = to_lgm_clk_ddiv(hw); - unsigned long flags; - spin_lock_irqsave(&ddiv->lock, flags); lgm_set_clk_val(ddiv->membase, ddiv->reg, ddiv->shift_gate, ddiv->width_gate, 0); - spin_unlock_irqrestore(&ddiv->lock, flags); } static int @@ -497,32 +464,25 @@ lgm_clk_ddiv_set_rate(struct clk_hw *hw, unsigned long rate, { struct lgm_clk_ddiv *ddiv = to_lgm_clk_ddiv(hw); u32 div, ddiv1, ddiv2; - unsigned long flags; div = DIV_ROUND_CLOSEST_ULL((u64)prate, rate); - spin_lock_irqsave(&ddiv->lock, flags); if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) { div = DIV_ROUND_CLOSEST_ULL((u64)div, 5); div = div * 2; } - if (div <= 0) { - spin_unlock_irqrestore(&ddiv->lock, flags); + if (div <= 0) return -EINVAL; - } - if (lgm_clk_get_ddiv_val(div, &ddiv1, &ddiv2)) { - spin_unlock_irqrestore(&ddiv->lock, flags); + if (lgm_clk_get_ddiv_val(div, &ddiv1, &ddiv2)) return -EINVAL; - } lgm_set_clk_val(ddiv->membase, ddiv->reg, ddiv->shift0, ddiv->width0, ddiv1 - 1); lgm_set_clk_val(ddiv->membase, ddiv->reg, ddiv->shift1, ddiv->width1, ddiv2 - 1); - spin_unlock_irqrestore(&ddiv->lock, flags); return 0; } @@ -533,18 +493,15 @@ lgm_clk_ddiv_round_rate(struct clk_hw *hw, unsigned long rate, { struct lgm_clk_ddiv *ddiv = to_lgm_clk_ddiv(hw); u32 div, ddiv1, ddiv2; - unsigned long flags; u64 rate64; div = DIV_ROUND_CLOSEST_ULL((u64)*prate, rate); /* if predivide bit is enabled, modify div by factor of 2.5 */ - spin_lock_irqsave(&ddiv->lock, flags); if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) { div = div * 2; div = DIV_ROUND_CLOSEST_ULL((u64)div, 5); } - spin_unlock_irqrestore(&ddiv->lock, flags); if (div <= 0) return *prate; @@ -558,12 +515,10 @@ lgm_clk_ddiv_round_rate(struct clk_hw *hw, unsigned long rate, do_div(rate64, ddiv2); /* if predivide bit is enabled, modify rounded rate by factor of 2.5 */ - spin_lock_irqsave(&ddiv->lock, flags); if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) { rate64 = rate64 * 2; rate64 = DIV_ROUND_CLOSEST_ULL(rate64, 5); } - spin_unlock_irqrestore(&ddiv->lock, flags); return rate64; } @@ -600,7 +555,6 @@ int lgm_clk_register_ddiv(struct lgm_clk_provider *ctx, init.num_parents = 1; ddiv->membase = ctx->membase; - ddiv->lock = ctx->lock; ddiv->reg = list->reg; ddiv->shift0 = list->shift0; ddiv->width0 = list->width0; diff --git a/drivers/clk/x86/clk-cgu.h b/drivers/clk/x86/clk-cgu.h index 4e22bfb22312..bcaf8aec94e5 100644 --- a/drivers/clk/x86/clk-cgu.h +++ b/drivers/clk/x86/clk-cgu.h @@ -1,28 +1,28 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright(c) 2020 Intel Corporation. - * Zhu YiXin <yixin.zhu@intel.com> - * Rahul Tanwar <rahul.tanwar@intel.com> + * Copyright (C) 2020-2022 MaxLinear, Inc. + * Copyright (C) 2020 Intel Corporation. + * Zhu Yixin <yzhu@maxlinear.com> + * Rahul Tanwar <rtanwar@maxlinear.com> */ #ifndef __CLK_CGU_H #define __CLK_CGU_H -#include <linux/io.h> +#include <linux/regmap.h> struct lgm_clk_mux { struct clk_hw hw; - void __iomem *membase; + struct regmap *membase; unsigned int reg; u8 shift; u8 width; unsigned long flags; - spinlock_t lock; }; struct lgm_clk_divider { struct clk_hw hw; - void __iomem *membase; + struct regmap *membase; unsigned int reg; u8 shift; u8 width; @@ -30,12 +30,11 @@ struct lgm_clk_divider { u8 width_gate; unsigned long flags; const struct clk_div_table *table; - spinlock_t lock; }; struct lgm_clk_ddiv { struct clk_hw hw; - void __iomem *membase; + struct regmap *membase; unsigned int reg; u8 shift0; u8 width0; @@ -48,16 +47,14 @@ struct lgm_clk_ddiv { unsigned int mult; unsigned int div; unsigned long flags; - spinlock_t lock; }; struct lgm_clk_gate { struct clk_hw hw; - void __iomem *membase; + struct regmap *membase; unsigned int reg; u8 shift; unsigned long flags; - spinlock_t lock; }; enum lgm_clk_type { @@ -77,11 +74,10 @@ enum lgm_clk_type { * @clk_data: array of hw clocks and clk number. */ struct lgm_clk_provider { - void __iomem *membase; + struct regmap *membase; struct device_node *np; struct device *dev; struct clk_hw_onecell_data clk_data; - spinlock_t lock; }; enum pll_type { @@ -92,11 +88,10 @@ enum pll_type { struct lgm_clk_pll { struct clk_hw hw; - void __iomem *membase; + struct regmap *membase; unsigned int reg; unsigned long flags; enum pll_type type; - spinlock_t lock; }; /** @@ -202,6 +197,8 @@ struct lgm_clk_branch { /* clock flags definition */ #define CLOCK_FLAG_VAL_INIT BIT(16) #define MUX_CLK_SW BIT(17) +#define GATE_CLK_HW BIT(18) +#define DIV_CLK_NO_MASK BIT(19) #define LGM_MUX(_id, _name, _pdata, _f, _reg, \ _shift, _width, _cf, _v) \ @@ -300,29 +297,32 @@ struct lgm_clk_branch { .div = _d, \ } -static inline void lgm_set_clk_val(void __iomem *membase, u32 reg, +static inline void lgm_set_clk_val(struct regmap *membase, u32 reg, u8 shift, u8 width, u32 set_val) { u32 mask = (GENMASK(width - 1, 0) << shift); - u32 regval; - regval = readl(membase + reg); - regval = (regval & ~mask) | ((set_val << shift) & mask); - writel(regval, membase + reg); + regmap_update_bits(membase, reg, mask, set_val << shift); } -static inline u32 lgm_get_clk_val(void __iomem *membase, u32 reg, +static inline u32 lgm_get_clk_val(struct regmap *membase, u32 reg, u8 shift, u8 width) { u32 mask = (GENMASK(width - 1, 0) << shift); u32 val; - val = readl(membase + reg); + if (regmap_read(membase, reg, &val)) { + WARN_ONCE(1, "Failed to read clk reg: 0x%x\n", reg); + return 0; + } + val = (val & mask) >> shift; return val; } + + int lgm_clk_register_branches(struct lgm_clk_provider *ctx, const struct lgm_clk_branch *list, unsigned int nr_clk); diff --git a/drivers/clk/x86/clk-lgm.c b/drivers/clk/x86/clk-lgm.c index 020f4e83a5cc..f69455dd1c98 100644 --- a/drivers/clk/x86/clk-lgm.c +++ b/drivers/clk/x86/clk-lgm.c @@ -1,10 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 /* + * Copyright (C) 2020-2022 MaxLinear, Inc. * Copyright (C) 2020 Intel Corporation. - * Zhu YiXin <yixin.zhu@intel.com> - * Rahul Tanwar <rahul.tanwar@intel.com> + * Zhu Yixin <yzhu@maxlinear.com> + * Rahul Tanwar <rtanwar@maxlinear.com> */ #include <linux/clk-provider.h> +#include <linux/mfd/syscon.h> #include <linux/of.h> #include <linux/platform_device.h> #include <dt-bindings/clock/intel,lgm-clk.h> @@ -253,8 +255,8 @@ static const struct lgm_clk_branch lgm_branch_clks[] = { LGM_FIXED(LGM_CLK_SLIC, "slic", NULL, 0, CGU_IF_CLK1, 8, 2, CLOCK_FLAG_VAL_INIT, 8192000, 2), LGM_FIXED(LGM_CLK_DOCSIS, "v_docsis", NULL, 0, 0, 0, 0, 0, 16000000, 0), - LGM_DIV(LGM_CLK_DCL, "dcl", "v_ifclk", 0, CGU_PCMCR, - 25, 3, 0, 0, 0, 0, dcl_div), + LGM_DIV(LGM_CLK_DCL, "dcl", "v_ifclk", CLK_SET_RATE_PARENT, CGU_PCMCR, + 25, 3, 0, 0, DIV_CLK_NO_MASK, 0, dcl_div), LGM_MUX(LGM_CLK_PCM, "pcm", pcm_p, 0, CGU_C55_PCMCR, 0, 1, CLK_MUX_ROUND_CLOSEST, 0), LGM_FIXED_FACTOR(LGM_CLK_DDR_PHY, "ddr_phy", "ddr", @@ -433,13 +435,15 @@ static int lgm_cgu_probe(struct platform_device *pdev) ctx->clk_data.num = CLK_NR_CLKS; - ctx->membase = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(ctx->membase)) + ctx->membase = syscon_node_to_regmap(np); + if (IS_ERR(ctx->membase)) { + dev_err(dev, "Failed to get clk CGU iomem\n"); return PTR_ERR(ctx->membase); + } + ctx->np = np; ctx->dev = dev; - spin_lock_init(&ctx->lock); ret = lgm_clk_register_plls(ctx, lgm_pll_clks, ARRAY_SIZE(lgm_pll_clks)); diff --git a/drivers/clk/xilinx/Kconfig b/drivers/clk/xilinx/Kconfig index f205522c40ff..051756953558 100644 --- a/drivers/clk/xilinx/Kconfig +++ b/drivers/clk/xilinx/Kconfig @@ -2,7 +2,7 @@ config XILINX_VCU tristate "Xilinx VCU logicoreIP Init" - depends on HAS_IOMEM && COMMON_CLK + depends on HAS_IOMEM select REGMAP_MMIO help Provides the driver to enable and disable the isolation between the @@ -19,7 +19,7 @@ config XILINX_VCU config COMMON_CLK_XLNX_CLKWZRD tristate "Xilinx Clocking Wizard" - depends on COMMON_CLK && OF + depends on OF depends on HAS_IOMEM help Support for the Xilinx Clocking Wizard IP core clock generator. |