diff options
Diffstat (limited to 'drivers/clk')
-rw-r--r-- | drivers/clk/clk-bcm2835.c | 8 | ||||
-rw-r--r-- | drivers/clk/clk-highbank.c | 10 | ||||
-rw-r--r-- | drivers/clk/clk-nomadik.c | 182 | ||||
-rw-r--r-- | drivers/clk/clk-prima2.c | 29 | ||||
-rw-r--r-- | drivers/clk/clk-vt8500.c | 34 | ||||
-rw-r--r-- | drivers/clk/mvebu/armada-370.c | 4 | ||||
-rw-r--r-- | drivers/clk/mxs/clk-imx23.c | 15 | ||||
-rw-r--r-- | drivers/clk/mxs/clk-imx28.c | 16 | ||||
-rw-r--r-- | drivers/clk/samsung/Makefile | 2 | ||||
-rw-r--r-- | drivers/clk/socfpga/clk.c | 2 | ||||
-rw-r--r-- | drivers/clk/sunxi/clk-sunxi.c | 11 | ||||
-rw-r--r-- | drivers/clk/ux500/Makefile | 1 | ||||
-rw-r--r-- | drivers/clk/ux500/u8500_of_clk.c | 559 | ||||
-rw-r--r-- | drivers/clk/ux500/u8540_clk.c | 2 | ||||
-rw-r--r-- | drivers/clk/versatile/clk-icst.c | 2 |
15 files changed, 720 insertions, 157 deletions
diff --git a/drivers/clk/clk-bcm2835.c b/drivers/clk/clk-bcm2835.c index 5fb4ff53d088..6b950ca8b711 100644 --- a/drivers/clk/clk-bcm2835.c +++ b/drivers/clk/clk-bcm2835.c @@ -20,14 +20,8 @@ #include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/clk/bcm2835.h> -#include <linux/clk-provider.h> #include <linux/of.h> -static const struct of_device_id clk_match[] __initconst = { - { .compatible = "fixed-clock", .data = of_fixed_clk_setup, }, - { } -}; - /* * These are fixed clocks. They're probably not all root clocks and it may * be possible to turn them on and off but until this is mapped out better @@ -63,6 +57,4 @@ void __init bcm2835_init_clocks(void) ret = clk_register_clkdev(clk, NULL, "20215000.uart"); if (ret) pr_err("uart1_pclk alias not registered\n"); - - of_clk_init(clk_match); } diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c index 2e08cb001936..2e7e9d9798cb 100644 --- a/drivers/clk/clk-highbank.c +++ b/drivers/clk/clk-highbank.c @@ -20,8 +20,7 @@ #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/of.h> - -extern void __iomem *sregs_base; +#include <linux/of_address.h> #define HB_PLL_LOCK_500 0x20000000 #define HB_PLL_LOCK 0x10000000 @@ -280,6 +279,7 @@ static __init struct clk *hb_clk_init(struct device_node *node, const struct clk const char *clk_name = node->name; const char *parent_name; struct clk_init_data init; + struct device_node *srnp; int rc; rc = of_property_read_u32(node, "reg", ®); @@ -290,7 +290,11 @@ static __init struct clk *hb_clk_init(struct device_node *node, const struct clk if (WARN_ON(!hb_clk)) return NULL; - hb_clk->reg = sregs_base + reg; + /* Map system registers */ + srnp = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs"); + hb_clk->reg = of_iomap(srnp, 0); + BUG_ON(!hb_clk->reg); + hb_clk->reg += reg; of_property_read_string(node, "clock-output-names", &clk_name); diff --git a/drivers/clk/clk-nomadik.c b/drivers/clk/clk-nomadik.c index 51410c2ac2cb..6a934a5296bd 100644 --- a/drivers/clk/clk-nomadik.c +++ b/drivers/clk/clk-nomadik.c @@ -27,6 +27,14 @@ */ #define SRC_CR 0x00U +#define SRC_CR_T0_ENSEL BIT(15) +#define SRC_CR_T1_ENSEL BIT(17) +#define SRC_CR_T2_ENSEL BIT(19) +#define SRC_CR_T3_ENSEL BIT(21) +#define SRC_CR_T4_ENSEL BIT(23) +#define SRC_CR_T5_ENSEL BIT(25) +#define SRC_CR_T6_ENSEL BIT(27) +#define SRC_CR_T7_ENSEL BIT(29) #define SRC_XTALCR 0x0CU #define SRC_XTALCR_XTALTIMEN BIT(20) #define SRC_XTALCR_SXTALDIS BIT(19) @@ -54,6 +62,79 @@ static DEFINE_SPINLOCK(src_lock); /* Base address of the SRC */ static void __iomem *src_base; +static int nomadik_clk_reboot_handler(struct notifier_block *this, + unsigned long code, + void *unused) +{ + u32 val; + + /* The main chrystal need to be enabled for reboot to work */ + val = readl(src_base + SRC_XTALCR); + val &= ~SRC_XTALCR_MXTALOVER; + val |= SRC_XTALCR_MXTALEN; + pr_crit("force-enabling MXTALO\n"); + writel(val, src_base + SRC_XTALCR); + return NOTIFY_OK; +} + +static struct notifier_block nomadik_clk_reboot_notifier = { + .notifier_call = nomadik_clk_reboot_handler, +}; + +static const struct of_device_id nomadik_src_match[] __initconst = { + { .compatible = "stericsson,nomadik-src" }, + { /* sentinel */ } +}; + +static void __init nomadik_src_init(void) +{ + struct device_node *np; + u32 val; + + np = of_find_matching_node(NULL, nomadik_src_match); + if (!np) { + pr_crit("no matching node for SRC, aborting clock init\n"); + return; + } + src_base = of_iomap(np, 0); + if (!src_base) { + pr_err("%s: must have src parent node with REGS (%s)\n", + __func__, np->name); + return; + } + + /* Set all timers to use the 2.4 MHz TIMCLK */ + val = readl(src_base + SRC_CR); + val |= SRC_CR_T0_ENSEL; + val |= SRC_CR_T1_ENSEL; + val |= SRC_CR_T2_ENSEL; + val |= SRC_CR_T3_ENSEL; + val |= SRC_CR_T4_ENSEL; + val |= SRC_CR_T5_ENSEL; + val |= SRC_CR_T6_ENSEL; + val |= SRC_CR_T7_ENSEL; + writel(val, src_base + SRC_CR); + + val = readl(src_base + SRC_XTALCR); + pr_info("SXTALO is %s\n", + (val & SRC_XTALCR_SXTALDIS) ? "disabled" : "enabled"); + pr_info("MXTAL is %s\n", + (val & SRC_XTALCR_MXTALSTAT) ? "enabled" : "disabled"); + if (of_property_read_bool(np, "disable-sxtalo")) { + /* The machine uses an external oscillator circuit */ + val |= SRC_XTALCR_SXTALDIS; + pr_info("disabling SXTALO\n"); + } + if (of_property_read_bool(np, "disable-mxtalo")) { + /* Disable this too: also run by external oscillator */ + val |= SRC_XTALCR_MXTALOVER; + val &= ~SRC_XTALCR_MXTALEN; + pr_info("disabling MXTALO\n"); + } + writel(val, src_base + SRC_XTALCR); + register_reboot_notifier(&nomadik_clk_reboot_notifier); +} + /** * struct clk_pll1 - Nomadik PLL1 clock * @hw: corresponding clock hardware entry @@ -431,6 +512,9 @@ static void __init of_nomadik_pll_setup(struct device_node *np) const char *parent_name; u32 pll_id; + if (!src_base) + nomadik_src_init(); + if (of_property_read_u32(np, "pll-id", &pll_id)) { pr_err("%s: PLL \"%s\" missing pll-id property\n", __func__, clk_name); @@ -441,6 +525,8 @@ static void __init of_nomadik_pll_setup(struct device_node *np) if (!IS_ERR(clk)) of_clk_add_provider(np, of_clk_src_simple_get, clk); } +CLK_OF_DECLARE(nomadik_pll_clk, + "st,nomadik-pll-clock", of_nomadik_pll_setup); static void __init of_nomadik_hclk_setup(struct device_node *np) { @@ -448,6 +534,9 @@ static void __init of_nomadik_hclk_setup(struct device_node *np) const char *clk_name = np->name; const char *parent_name; + if (!src_base) + nomadik_src_init(); + parent_name = of_clk_get_parent_name(np, 0); /* * The HCLK divides PLL1 with 1 (passthru), 2, 3 or 4. @@ -460,6 +549,8 @@ static void __init of_nomadik_hclk_setup(struct device_node *np) if (!IS_ERR(clk)) of_clk_add_provider(np, of_clk_src_simple_get, clk); } +CLK_OF_DECLARE(nomadik_hclk_clk, + "st,nomadik-hclk-clock", of_nomadik_hclk_setup); static void __init of_nomadik_src_clk_setup(struct device_node *np) { @@ -468,6 +559,9 @@ static void __init of_nomadik_src_clk_setup(struct device_node *np) const char *parent_name; u32 clk_id; + if (!src_base) + nomadik_src_init(); + if (of_property_read_u32(np, "clock-id", &clk_id)) { pr_err("%s: SRC clock \"%s\" missing clock-id property\n", __func__, clk_name); @@ -478,89 +572,5 @@ static void __init of_nomadik_src_clk_setup(struct device_node *np) if (!IS_ERR(clk)) of_clk_add_provider(np, of_clk_src_simple_get, clk); } - -static const struct of_device_id nomadik_src_match[] __initconst = { - { .compatible = "stericsson,nomadik-src" }, - { /* sentinel */ } -}; - -static const struct of_device_id nomadik_src_clk_match[] __initconst = { - { - .compatible = "fixed-clock", - .data = of_fixed_clk_setup, - }, - { - .compatible = "fixed-factor-clock", - .data = of_fixed_factor_clk_setup, - }, - { - .compatible = "st,nomadik-pll-clock", - .data = of_nomadik_pll_setup, - }, - { - .compatible = "st,nomadik-hclk-clock", - .data = of_nomadik_hclk_setup, - }, - { - .compatible = "st,nomadik-src-clock", - .data = of_nomadik_src_clk_setup, - }, - { /* sentinel */ } -}; - -static int nomadik_clk_reboot_handler(struct notifier_block *this, - unsigned long code, - void *unused) -{ - u32 val; - - /* The main chrystal need to be enabled for reboot to work */ - val = readl(src_base + SRC_XTALCR); - val &= ~SRC_XTALCR_MXTALOVER; - val |= SRC_XTALCR_MXTALEN; - pr_crit("force-enabling MXTALO\n"); - writel(val, src_base + SRC_XTALCR); - return NOTIFY_OK; -} - -static struct notifier_block nomadik_clk_reboot_notifier = { - .notifier_call = nomadik_clk_reboot_handler, -}; - -void __init nomadik_clk_init(void) -{ - struct device_node *np; - u32 val; - - np = of_find_matching_node(NULL, nomadik_src_match); - if (!np) { - pr_crit("no matching node for SRC, aborting clock init\n"); - return; - } - src_base = of_iomap(np, 0); - if (!src_base) { - pr_err("%s: must have src parent node with REGS (%s)\n", - __func__, np->name); - return; - } - val = readl(src_base + SRC_XTALCR); - pr_info("SXTALO is %s\n", - (val & SRC_XTALCR_SXTALDIS) ? "disabled" : "enabled"); - pr_info("MXTAL is %s\n", - (val & SRC_XTALCR_MXTALSTAT) ? "enabled" : "disabled"); - if (of_property_read_bool(np, "disable-sxtalo")) { - /* The machine uses an external oscillator circuit */ - val |= SRC_XTALCR_SXTALDIS; - pr_info("disabling SXTALO\n"); - } - if (of_property_read_bool(np, "disable-mxtalo")) { - /* Disable this too: also run by external oscillator */ - val |= SRC_XTALCR_MXTALOVER; - val &= ~SRC_XTALCR_MXTALEN; - pr_info("disabling MXTALO\n"); - } - writel(val, src_base + SRC_XTALCR); - register_reboot_notifier(&nomadik_clk_reboot_notifier); - - of_clk_init(nomadik_src_clk_match); -} +CLK_OF_DECLARE(nomadik_src_clk, + "st,nomadik-src-clock", of_nomadik_src_clk_setup); diff --git a/drivers/clk/clk-prima2.c b/drivers/clk/clk-prima2.c index 5ab95f1ad579..6c15e3316137 100644 --- a/drivers/clk/clk-prima2.c +++ b/drivers/clk/clk-prima2.c @@ -1015,16 +1015,6 @@ static struct clk_std clk_usb1 = { }, }; -static struct of_device_id clkc_ids[] = { - { .compatible = "sirf,prima2-clkc" }, - {}, -}; - -static struct of_device_id rsc_ids[] = { - { .compatible = "sirf,prima2-rsc" }, - {}, -}; - enum prima2_clk_index { /* 0 1 2 3 4 5 6 7 8 9 */ rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, @@ -1082,24 +1072,16 @@ static struct clk_hw *prima2_clk_hw_array[maxclk] __initdata = { static struct clk *prima2_clks[maxclk]; static struct clk_onecell_data clk_data; -void __init sirfsoc_of_clk_init(void) +static void __init sirfsoc_clk_init(struct device_node *np) { - struct device_node *np; + struct device_node *rscnp; int i; - np = of_find_matching_node(NULL, rsc_ids); - if (!np) - panic("unable to find compatible rsc node in dtb\n"); - - sirfsoc_rsc_vbase = of_iomap(np, 0); + rscnp = of_find_compatible_node(NULL, NULL, "sirf,prima2-rsc"); + sirfsoc_rsc_vbase = of_iomap(rscnp, 0); if (!sirfsoc_rsc_vbase) panic("unable to map rsc registers\n"); - - of_node_put(np); - - np = of_find_matching_node(NULL, clkc_ids); - if (!np) - return; + of_node_put(rscnp); sirfsoc_clk_vbase = of_iomap(np, 0); if (!sirfsoc_clk_vbase) @@ -1124,3 +1106,4 @@ void __init sirfsoc_of_clk_init(void) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); } +CLK_OF_DECLARE(sirfsoc_clk, "sirf,prima2-clkc", sirfsoc_clk_init); diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c index 82306f5fb9c2..7fd5c5e9e25d 100644 --- a/drivers/clk/clk-vt8500.c +++ b/drivers/clk/clk-vt8500.c @@ -15,11 +15,14 @@ #include <linux/io.h> #include <linux/of.h> +#include <linux/of_address.h> #include <linux/slab.h> #include <linux/bitops.h> #include <linux/clkdev.h> #include <linux/clk-provider.h> +#define LEGACY_PMC_BASE 0xD8130000 + /* All clocks share the same lock as none can be changed concurrently */ static DEFINE_SPINLOCK(_lock); @@ -53,6 +56,21 @@ struct clk_pll { static void __iomem *pmc_base; +static __init void vtwm_set_pmc_base(void) +{ + struct device_node *np = + of_find_compatible_node(NULL, NULL, "via,vt8500-pmc"); + + if (np) + pmc_base = of_iomap(np, 0); + else + pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000); + of_node_put(np); + + if (!pmc_base) + pr_err("%s:of_iomap(pmc) failed\n", __func__); +} + #define to_clk_device(_hw) container_of(_hw, struct clk_device, hw) #define VT8500_PMC_BUSY_MASK 0x18 @@ -222,6 +240,9 @@ static __init void vtwm_device_clk_init(struct device_node *node) int rc; int clk_init_flags = 0; + if (!pmc_base) + vtwm_set_pmc_base(); + dev_clk = kzalloc(sizeof(*dev_clk), GFP_KERNEL); if (WARN_ON(!dev_clk)) return; @@ -636,6 +657,9 @@ static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type) struct clk_init_data init; int rc; + if (!pmc_base) + vtwm_set_pmc_base(); + rc = of_property_read_u32(node, "reg", ®); if (WARN_ON(rc)) return; @@ -694,13 +718,3 @@ static void __init wm8850_pll_init(struct device_node *node) vtwm_pll_clk_init(node, PLL_TYPE_WM8850); } CLK_OF_DECLARE(wm8850_pll, "wm,wm8850-pll-clock", wm8850_pll_init); - -void __init vtwm_clk_init(void __iomem *base) -{ - if (!base) - return; - - pmc_base = base; - - of_clk_init(NULL); -} diff --git a/drivers/clk/mvebu/armada-370.c b/drivers/clk/mvebu/armada-370.c index fc777bdc1886..81a202d12a7a 100644 --- a/drivers/clk/mvebu/armada-370.c +++ b/drivers/clk/mvebu/armada-370.c @@ -39,8 +39,8 @@ static const struct coreclk_ratio a370_coreclk_ratios[] __initconst = { }; static const u32 a370_tclk_freqs[] __initconst = { - 16600000, - 20000000, + 166000000, + 200000000, }; static u32 __init a370_get_tclk_freq(void __iomem *sar) diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c index c396fe361589..9fc9359f5133 100644 --- a/drivers/clk/mxs/clk-imx23.c +++ b/drivers/clk/mxs/clk-imx23.c @@ -12,6 +12,7 @@ #include <linux/clk.h> #include <linux/clk/mxs.h> #include <linux/clkdev.h> +#include <linux/clk-provider.h> #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> @@ -100,16 +101,16 @@ static enum imx23_clk clks_init_on[] __initdata = { cpu, hbus, xbus, emi, uart, }; -int __init mx23_clocks_init(void) +static void __init mx23_clocks_init(struct device_node *np) { - struct device_node *np; + struct device_node *dcnp; u32 i; - np = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl"); - digctrl = of_iomap(np, 0); + dcnp = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl"); + digctrl = of_iomap(dcnp, 0); WARN_ON(!digctrl); + of_node_put(dcnp); - np = of_find_compatible_node(NULL, NULL, "fsl,imx23-clkctrl"); clkctrl = of_iomap(np, 0); WARN_ON(!clkctrl); @@ -162,7 +163,7 @@ int __init mx23_clocks_init(void) if (IS_ERR(clks[i])) { pr_err("i.MX23 clk %d: register failed with %ld\n", i, PTR_ERR(clks[i])); - return PTR_ERR(clks[i]); + return; } clk_data.clks = clks; @@ -172,5 +173,5 @@ int __init mx23_clocks_init(void) for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) clk_prepare_enable(clks[clks_init_on[i]]); - return 0; } +CLK_OF_DECLARE(imx23_clkctrl, "fsl,imx23-clkctrl", mx23_clocks_init); diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c index 4faf0afc44cd..a6c35010e4e5 100644 --- a/drivers/clk/mxs/clk-imx28.c +++ b/drivers/clk/mxs/clk-imx28.c @@ -12,6 +12,7 @@ #include <linux/clk.h> #include <linux/clk/mxs.h> #include <linux/clkdev.h> +#include <linux/clk-provider.h> #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> @@ -154,16 +155,16 @@ static enum imx28_clk clks_init_on[] __initdata = { cpu, hbus, xbus, emi, uart, }; -int __init mx28_clocks_init(void) +static void __init mx28_clocks_init(struct device_node *np) { - struct device_node *np; + struct device_node *dcnp; u32 i; - np = of_find_compatible_node(NULL, NULL, "fsl,imx28-digctl"); - digctrl = of_iomap(np, 0); + dcnp = of_find_compatible_node(NULL, NULL, "fsl,imx28-digctl"); + digctrl = of_iomap(dcnp, 0); WARN_ON(!digctrl); + of_node_put(dcnp); - np = of_find_compatible_node(NULL, NULL, "fsl,imx28-clkctrl"); clkctrl = of_iomap(np, 0); WARN_ON(!clkctrl); @@ -239,7 +240,7 @@ int __init mx28_clocks_init(void) if (IS_ERR(clks[i])) { pr_err("i.MX28 clk %d: register failed with %ld\n", i, PTR_ERR(clks[i])); - return PTR_ERR(clks[i]); + return; } clk_data.clks = clks; @@ -250,6 +251,5 @@ int __init mx28_clocks_init(void) for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) clk_prepare_enable(clks[clks_init_on[i]]); - - return 0; } +CLK_OF_DECLARE(imx28_clkctrl, "fsl,imx28-clkctrl", mx28_clocks_init); diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 3413380086d5..8eb4799237f0 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -8,6 +8,4 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o -ifdef CONFIG_COMMON_CLK obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o -endif diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c index 5bb848cac6ec..81dd31a686df 100644 --- a/drivers/clk/socfpga/clk.c +++ b/drivers/clk/socfpga/clk.c @@ -49,7 +49,7 @@ #define SOCFPGA_L4_SP_CLK "l4_sp_clk" #define SOCFPGA_NAND_CLK "nand_clk" #define SOCFPGA_NAND_X_CLK "nand_x_clk" -#define SOCFPGA_MMC_CLK "mmc_clk" +#define SOCFPGA_MMC_CLK "sdmmc_clk" #define SOCFPGA_DB_CLK "gpio_db_clk" #define div_mask(width) ((1 << (width)) - 1) diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index 34ee69f4d50c..9bbd03514540 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -16,7 +16,6 @@ #include <linux/clk-provider.h> #include <linux/clkdev.h> -#include <linux/clk/sunxi.h> #include <linux/of.h> #include <linux/of_address.h> @@ -617,11 +616,8 @@ static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_mat } } -void __init sunxi_init_clocks(void) +static void __init sunxi_init_clocks(struct device_node *np) { - /* Register all the simple and basic clocks on DT */ - of_clk_init(NULL); - /* Register factor clocks */ of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup); @@ -634,3 +630,8 @@ void __init sunxi_init_clocks(void) /* Register gate clocks */ of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup); } +CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sunxi_init_clocks); +CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sunxi_init_clocks); +CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sunxi_init_clocks); +CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sunxi_init_clocks); +CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sunxi_init_clocks); diff --git a/drivers/clk/ux500/Makefile b/drivers/clk/ux500/Makefile index c6a806ed0e8c..521483f0ba33 100644 --- a/drivers/clk/ux500/Makefile +++ b/drivers/clk/ux500/Makefile @@ -8,6 +8,7 @@ obj-y += clk-prcmu.o obj-y += clk-sysctrl.o # Clock definitions +obj-y += u8500_of_clk.o obj-y += u8500_clk.o obj-y += u9540_clk.o obj-y += u8540_clk.o diff --git a/drivers/clk/ux500/u8500_of_clk.c b/drivers/clk/ux500/u8500_of_clk.c new file mode 100644 index 000000000000..cdeff299de26 --- /dev/null +++ b/drivers/clk/ux500/u8500_of_clk.c @@ -0,0 +1,559 @@ +/* + * Clock definitions for u8500 platform. + * + * Copyright (C) 2012 ST-Ericsson SA + * Author: Ulf Hansson <ulf.hansson@linaro.org> + * + * License terms: GNU General Public License (GPL) version 2 + */ + +#include <linux/of.h> +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/clk-provider.h> +#include <linux/mfd/dbx500-prcmu.h> +#include <linux/platform_data/clk-ux500.h> +#include "clk.h" + +#define PRCC_NUM_PERIPH_CLUSTERS 6 +#define PRCC_PERIPHS_PER_CLUSTER 32 + +static struct clk *prcmu_clk[PRCMU_NUM_CLKS]; +static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; +static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; + +#define PRCC_SHOW(clk, base, bit) \ + clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] +#define PRCC_PCLK_STORE(clk, base, bit) \ + prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk +#define PRCC_KCLK_STORE(clk, base, bit) \ + prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk + +struct clk *ux500_twocell_get(struct of_phandle_args *clkspec, void *data) +{ + struct clk **clk_data = data; + unsigned int base, bit; + + if (clkspec->args_count != 2) + return ERR_PTR(-EINVAL); + + base = clkspec->args[0]; + bit = clkspec->args[1]; + + if (base != 1 && base != 2 && base != 3 && base != 5 && base != 6) { + pr_err("%s: invalid PRCC base %d\n", __func__, base); + return ERR_PTR(-EINVAL); + } + + return PRCC_SHOW(clk_data, base, bit); +} + +static const struct of_device_id u8500_clk_of_match[] = { + { .compatible = "stericsson,u8500-clks", }, + { }, +}; + +void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, + u32 clkrst5_base, u32 clkrst6_base) +{ + struct prcmu_fw_version *fw_version; + struct device_node *np = NULL; + struct device_node *child = NULL; + const char *sgaclk_parent = NULL; + struct clk *clk, *rtc_clk, *twd_clk; + + if (of_have_populated_dt()) + np = of_find_matching_node(NULL, u8500_clk_of_match); + if (!np) { + pr_err("Either DT or U8500 Clock node not found\n"); + return; + } + + /* Clock sources */ + clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0, + CLK_IS_ROOT|CLK_IGNORE_UNUSED); + prcmu_clk[PRCMU_PLLSOC0] = clk; + + clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1, + CLK_IS_ROOT|CLK_IGNORE_UNUSED); + prcmu_clk[PRCMU_PLLSOC1] = clk; + + clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR, + CLK_IS_ROOT|CLK_IGNORE_UNUSED); + prcmu_clk[PRCMU_PLLDDR] = clk; + + /* FIXME: Add sys, ulp and int clocks here. */ + + rtc_clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL", + CLK_IS_ROOT|CLK_IGNORE_UNUSED, + 32768); + + /* PRCMU clocks */ + fw_version = prcmu_get_fw_version(); + if (fw_version != NULL) { + switch (fw_version->project) { + case PRCMU_FW_PROJECT_U8500_C2: + case PRCMU_FW_PROJECT_U8520: + case PRCMU_FW_PROJECT_U8420: + sgaclk_parent = "soc0_pll"; + break; + default: + break; + } + } + + if (sgaclk_parent) + clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent, + PRCMU_SGACLK, 0); + else + clk = clk_reg_prcmu_gate("sgclk", NULL, + PRCMU_SGACLK, CLK_IS_ROOT); + prcmu_clk[PRCMU_SGACLK] = clk; + + clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT); + prcmu_clk[PRCMU_UARTCLK] = clk; + + clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT); + prcmu_clk[PRCMU_MSP02CLK] = clk; + + clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT); + prcmu_clk[PRCMU_MSP1CLK] = clk; + + clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT); + prcmu_clk[PRCMU_I2CCLK] = clk; + + clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT); + prcmu_clk[PRCMU_SLIMCLK] = clk; + + clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT); + prcmu_clk[PRCMU_PER1CLK] = clk; + + clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT); + prcmu_clk[PRCMU_PER2CLK] = clk; + + clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT); + prcmu_clk[PRCMU_PER3CLK] = clk; + + clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT); + prcmu_clk[PRCMU_PER5CLK] = clk; + + clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT); + prcmu_clk[PRCMU_PER6CLK] = clk; + + clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT); + prcmu_clk[PRCMU_PER7CLK] = clk; + + clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0, + CLK_IS_ROOT|CLK_SET_RATE_GATE); + prcmu_clk[PRCMU_LCDCLK] = clk; + + clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT); + prcmu_clk[PRCMU_BMLCLK] = clk; + + clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0, + CLK_IS_ROOT|CLK_SET_RATE_GATE); + prcmu_clk[PRCMU_HSITXCLK] = clk; + + clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0, + CLK_IS_ROOT|CLK_SET_RATE_GATE); + prcmu_clk[PRCMU_HSIRXCLK] = clk; + + clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0, + CLK_IS_ROOT|CLK_SET_RATE_GATE); + prcmu_clk[PRCMU_HDMICLK] = clk; + + clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT); + prcmu_clk[PRCMU_APEATCLK] = clk; + + clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK, + CLK_IS_ROOT); + prcmu_clk[PRCMU_APETRACECLK] = clk; + + clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT); + prcmu_clk[PRCMU_MCDECLK] = clk; + + clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, + CLK_IS_ROOT); + prcmu_clk[PRCMU_IPI2CCLK] = clk; + + clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, + CLK_IS_ROOT); + prcmu_clk[PRCMU_DSIALTCLK] = clk; + + clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT); + prcmu_clk[PRCMU_DMACLK] = clk; + + clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT); + prcmu_clk[PRCMU_B2R2CLK] = clk; + + clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0, + CLK_IS_ROOT|CLK_SET_RATE_GATE); + prcmu_clk[PRCMU_TVCLK] = clk; + + clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT); + prcmu_clk[PRCMU_SSPCLK] = clk; + + clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT); + prcmu_clk[PRCMU_RNGCLK] = clk; + + clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT); + prcmu_clk[PRCMU_UICCCLK] = clk; + + clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT); + prcmu_clk[PRCMU_TIMCLK] = clk; + + clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK, + 100000000, + CLK_IS_ROOT|CLK_SET_RATE_GATE); + prcmu_clk[PRCMU_SDMMCCLK] = clk; + + clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk", + PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE); + prcmu_clk[PRCMU_PLLDSI] = clk; + + clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll", + PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE); + prcmu_clk[PRCMU_DSI0CLK] = clk; + + clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll", + PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE); + prcmu_clk[PRCMU_DSI1CLK] = clk; + + clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk", + PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE); + prcmu_clk[PRCMU_DSI0ESCCLK] = clk; + + clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk", + PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE); + prcmu_clk[PRCMU_DSI1ESCCLK] = clk; + + clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk", + PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE); + prcmu_clk[PRCMU_DSI2ESCCLK] = clk; + + clk = clk_reg_prcmu_scalable_rate("armss", NULL, + PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED); + prcmu_clk[PRCMU_ARMSS] = clk; + + twd_clk = clk_register_fixed_factor(NULL, "smp_twd", "armss", + CLK_IGNORE_UNUSED, 1, 2); + + /* + * FIXME: Add special handled PRCMU clocks here: + * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl. + * 2. ab9540_clkout1yuv, see clkout0yuv + */ + + /* PRCC P-clocks */ + clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base, + BIT(0), 0); + PRCC_PCLK_STORE(clk, 1, 0); + + clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base, + BIT(1), 0); + PRCC_PCLK_STORE(clk, 1, 1); + + clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base, + BIT(2), 0); + PRCC_PCLK_STORE(clk, 1, 2); + + clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", clkrst1_base, + BIT(3), 0); + PRCC_PCLK_STORE(clk, 1, 3); + + clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", clkrst1_base, + BIT(4), 0); + PRCC_PCLK_STORE(clk, 1, 4); + + clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", clkrst1_base, + BIT(5), 0); + PRCC_PCLK_STORE(clk, 1, 5); + + clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", clkrst1_base, + BIT(6), 0); + PRCC_PCLK_STORE(clk, 1, 6); + + clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", clkrst1_base, + BIT(7), 0); + PRCC_PCLK_STORE(clk, 1, 7); + + clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", clkrst1_base, + BIT(8), 0); + PRCC_PCLK_STORE(clk, 1, 8); + + clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", clkrst1_base, + BIT(9), 0); + PRCC_PCLK_STORE(clk, 1, 9); + + clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", clkrst1_base, + BIT(10), 0); + PRCC_PCLK_STORE(clk, 1, 10); + + clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", clkrst1_base, + BIT(11), 0); + PRCC_PCLK_STORE(clk, 1, 11); + + clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", clkrst2_base, + BIT(0), 0); + PRCC_PCLK_STORE(clk, 2, 0); + + clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", clkrst2_base, + BIT(1), 0); + PRCC_PCLK_STORE(clk, 2, 1); + + clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", clkrst2_base, + BIT(2), 0); + PRCC_PCLK_STORE(clk, 2, 2); + + clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", clkrst2_base, + BIT(3), 0); + PRCC_PCLK_STORE(clk, 2, 3); + + clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", clkrst2_base, + BIT(4), 0); + PRCC_PCLK_STORE(clk, 2, 4); + + clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", clkrst2_base, + BIT(5), 0); + PRCC_PCLK_STORE(clk, 2, 5); + + clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", clkrst2_base, + BIT(6), 0); + PRCC_PCLK_STORE(clk, 2, 6); + + clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", clkrst2_base, + BIT(7), 0); + PRCC_PCLK_STORE(clk, 2, 7); + + clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", clkrst2_base, + BIT(8), 0); + PRCC_PCLK_STORE(clk, 2, 8); + + clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", clkrst2_base, + BIT(9), 0); + PRCC_PCLK_STORE(clk, 2, 9); + + clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", clkrst2_base, + BIT(10), 0); + PRCC_PCLK_STORE(clk, 2, 10); + + clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base, + BIT(11), 0); + PRCC_PCLK_STORE(clk, 2, 11); + + clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base, + BIT(12), 0); + PRCC_PCLK_STORE(clk, 2, 12); + + clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base, + BIT(0), 0); + PRCC_PCLK_STORE(clk, 3, 0); + + clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base, + BIT(1), 0); + PRCC_PCLK_STORE(clk, 3, 1); + + clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base, + BIT(2), 0); + PRCC_PCLK_STORE(clk, 3, 2); + + clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base, + BIT(3), 0); + PRCC_PCLK_STORE(clk, 3, 3); + + clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base, + BIT(4), 0); + PRCC_PCLK_STORE(clk, 3, 4); + + clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base, + BIT(5), 0); + PRCC_PCLK_STORE(clk, 3, 5); + + clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base, + BIT(6), 0); + PRCC_PCLK_STORE(clk, 3, 6); + + clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base, + BIT(7), 0); + PRCC_PCLK_STORE(clk, 3, 7); + + clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base, + BIT(8), 0); + PRCC_PCLK_STORE(clk, 3, 8); + + clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", clkrst5_base, + BIT(0), 0); + PRCC_PCLK_STORE(clk, 5, 0); + + clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", clkrst5_base, + BIT(1), 0); + PRCC_PCLK_STORE(clk, 5, 1); + + clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", clkrst6_base, + BIT(0), 0); + PRCC_PCLK_STORE(clk, 6, 0); + + clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", clkrst6_base, + BIT(1), 0); + PRCC_PCLK_STORE(clk, 6, 1); + + clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", clkrst6_base, + BIT(2), 0); + PRCC_PCLK_STORE(clk, 6, 2); + + clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", clkrst6_base, + BIT(3), 0); + PRCC_PCLK_STORE(clk, 6, 3); + + clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", clkrst6_base, + BIT(4), 0); + PRCC_PCLK_STORE(clk, 6, 4); + + clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", clkrst6_base, + BIT(5), 0); + PRCC_PCLK_STORE(clk, 6, 5); + + clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", clkrst6_base, + BIT(6), 0); + PRCC_PCLK_STORE(clk, 6, 6); + + clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", clkrst6_base, + BIT(7), 0); + PRCC_PCLK_STORE(clk, 6, 7); + + /* PRCC K-clocks + * + * FIXME: Some drivers requires PERPIH[n| to be automatically enabled + * by enabling just the K-clock, even if it is not a valid parent to + * the K-clock. Until drivers get fixed we might need some kind of + * "parent muxed join". + */ + + /* Periph1 */ + clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk", + clkrst1_base, BIT(0), CLK_SET_RATE_GATE); + PRCC_KCLK_STORE(clk, 1, 0); + + clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk", + clkrst1_base, BIT(1), CLK_SET_RATE_GATE); + PRCC_KCLK_STORE(clk, 1, 1); + + clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk", + clkrst1_base, BIT(2), CLK_SET_RATE_GATE); + PRCC_KCLK_STORE(clk, 1, 2); + + clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk", + clkrst1_base, BIT(3), CLK_SET_RATE_GATE); + PRCC_KCLK_STORE(clk, 1, 3); + + clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk", + clkrst1_base, BIT(4), CLK_SET_RATE_GATE); + PRCC_KCLK_STORE(clk, 1, 4); + + clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk", + clkrst1_base, BIT(5), CLK_SET_RATE_GATE); + PRCC_KCLK_STORE(clk, 1, 5); + + clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk", + clkrst1_base, BIT(6), CLK_SET_RATE_GATE); + PRCC_KCLK_STORE(clk, 1, 6); + + clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk", + clkrst1_base, BIT(8), CLK_SET_RATE_GATE); + PRCC_KCLK_STORE(clk, 1, 8); + + clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk", + clkrst1_base, BIT(9), CLK_SET_RATE_GATE); + PRCC_KCLK_STORE(clk, 1, 9); + + clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk", + clkrst1_base, BIT(10), CLK_SET_RATE_GATE); + PRCC_KCLK_STORE(clk, 1, 10); + + /* Periph2 */ + clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk", + clkrst2_base, BIT(0), CLK_SET_RATE_GATE); + PRCC_KCLK_STORE(clk, 2, 0); + + clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk", + clkrst2_base, BIT(2), CLK_SET_RATE_GATE); + PRCC_KCLK_STORE(clk, 2, 2); + + clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk", + clkrst2_base, BIT(3), CLK_SET_RATE_GATE); + PRCC_KCLK_STORE(clk, 2, 3); + + clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk", + clkrst2_base, BIT(4), CLK_SET_RATE_GATE); + PRCC_KCLK_STORE(clk, 2, 4); + + clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk", + clkrst2_base, BIT(5), CLK_SET_RATE_GATE); + PRCC_KCLK_STORE(clk, 2, 5); + + /* Note that rate is received from parent. */ + clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk", + clkrst2_base, BIT(6), + CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); + PRCC_KCLK_STORE(clk, 2, 6); + + clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk", + clkrst2_base, BIT(7), + CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); + PRCC_KCLK_STORE(clk, 2, 7); + + /* Periph3 */ + clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk", + clkrst3_base, BIT(1), CLK_SET_RATE_GATE); + PRCC_KCLK_STORE(clk, 3, 1); + + clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk", + clkrst3_base, BIT(2), CLK_SET_RATE_GATE); + PRCC_KCLK_STORE(clk, 3, 2); + + clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk", + clkrst3_base, BIT(3), CLK_SET_RATE_GATE); + PRCC_KCLK_STORE(clk, 3, 3); + + clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk", + clkrst3_base, BIT(4), CLK_SET_RATE_GATE); + PRCC_KCLK_STORE(clk, 3, 4); + + clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k", + clkrst3_base, BIT(5), CLK_SET_RATE_GATE); + PRCC_KCLK_STORE(clk, 3, 5); + + clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk", + clkrst3_base, BIT(6), CLK_SET_RATE_GATE); + PRCC_KCLK_STORE(clk, 3, 6); + + clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk", + clkrst3_base, BIT(7), CLK_SET_RATE_GATE); + PRCC_KCLK_STORE(clk, 3, 7); + + /* Periph6 */ + clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk", + clkrst6_base, BIT(0), CLK_SET_RATE_GATE); + PRCC_KCLK_STORE(clk, 6, 0); + + for_each_child_of_node(np, child) { + static struct clk_onecell_data clk_data; + + if (!of_node_cmp(child->name, "prcmu-clock")) { + clk_data.clks = prcmu_clk; + clk_data.clk_num = ARRAY_SIZE(prcmu_clk); + of_clk_add_provider(child, of_clk_src_onecell_get, &clk_data); + } + if (!of_node_cmp(child->name, "prcc-periph-clock")) + of_clk_add_provider(child, ux500_twocell_get, prcc_pclk); + + if (!of_node_cmp(child->name, "prcc-kernel-clock")) + of_clk_add_provider(child, ux500_twocell_get, prcc_kclk); + + if (!of_node_cmp(child->name, "rtc32k-clock")) + of_clk_add_provider(child, of_clk_src_simple_get, rtc_clk); + + if (!of_node_cmp(child->name, "smp-twd-clock")) + of_clk_add_provider(child, of_clk_src_simple_get, twd_clk); + } +} diff --git a/drivers/clk/ux500/u8540_clk.c b/drivers/clk/ux500/u8540_clk.c index f26258869deb..20c8add90d11 100644 --- a/drivers/clk/ux500/u8540_clk.c +++ b/drivers/clk/ux500/u8540_clk.c @@ -83,7 +83,7 @@ void u8540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, clk_register_clkdev(clk, NULL, "lcd"); clk_register_clkdev(clk, "lcd", "mcde"); - clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BML8580CLK, + clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "bml"); diff --git a/drivers/clk/versatile/clk-icst.c b/drivers/clk/versatile/clk-icst.c index 67ccf4aa7277..f5e4c21b301f 100644 --- a/drivers/clk/versatile/clk-icst.c +++ b/drivers/clk/versatile/clk-icst.c @@ -107,7 +107,7 @@ static int icst_set_rate(struct clk_hw *hw, unsigned long rate, vco = icst_hz_to_vco(icst->params, rate); icst->rate = icst_hz(icst->params, vco); - vco_set(icst->vcoreg, icst->lockreg, vco); + vco_set(icst->lockreg, icst->vcoreg, vco); return 0; } |