diff options
Diffstat (limited to 'drivers/clk/socfpga/clk-agilex.c')
-rw-r--r-- | drivers/clk/socfpga/clk-agilex.c | 117 |
1 files changed, 62 insertions, 55 deletions
diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c index 7689bdd0a914..92a6d740a799 100644 --- a/drivers/clk/socfpga/clk-agilex.c +++ b/drivers/clk/socfpga/clk-agilex.c @@ -303,18 +303,18 @@ static const struct stratix10_gate_clock agilex_gate_clks[] = { static int n5x_clk_register_c_perip(const struct n5x_perip_c_clock *clks, int nums, struct stratix10_clock_data *data) { - struct clk *clk; + struct clk_hw *hw_clk; void __iomem *base = data->base; int i; for (i = 0; i < nums; i++) { - clk = n5x_register_periph(&clks[i], base); - if (IS_ERR(clk)) { + hw_clk = n5x_register_periph(&clks[i], base); + if (IS_ERR(hw_clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); continue; } - data->clk_data.clks[clks[i].id] = clk; + data->clk_data.hws[clks[i].id] = hw_clk; } return 0; } @@ -322,18 +322,18 @@ static int n5x_clk_register_c_perip(const struct n5x_perip_c_clock *clks, static int agilex_clk_register_c_perip(const struct stratix10_perip_c_clock *clks, int nums, struct stratix10_clock_data *data) { - struct clk *clk; + struct clk_hw *hw_clk; void __iomem *base = data->base; int i; for (i = 0; i < nums; i++) { - clk = s10_register_periph(&clks[i], base); - if (IS_ERR(clk)) { + hw_clk = s10_register_periph(&clks[i], base); + if (IS_ERR(hw_clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); continue; } - data->clk_data.clks[clks[i].id] = clk; + data->clk_data.hws[clks[i].id] = hw_clk; } return 0; } @@ -341,37 +341,38 @@ static int agilex_clk_register_c_perip(const struct stratix10_perip_c_clock *clk static int agilex_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks, int nums, struct stratix10_clock_data *data) { - struct clk *clk; + struct clk_hw *hw_clk; void __iomem *base = data->base; int i; for (i = 0; i < nums; i++) { - clk = s10_register_cnt_periph(&clks[i], base); - if (IS_ERR(clk)) { + hw_clk = s10_register_cnt_periph(&clks[i], base); + if (IS_ERR(hw_clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); continue; } - data->clk_data.clks[clks[i].id] = clk; + data->clk_data.hws[clks[i].id] = hw_clk; } return 0; } -static int agilex_clk_register_gate(const struct stratix10_gate_clock *clks, int nums, struct stratix10_clock_data *data) +static int agilex_clk_register_gate(const struct stratix10_gate_clock *clks, + int nums, struct stratix10_clock_data *data) { - struct clk *clk; + struct clk_hw *hw_clk; void __iomem *base = data->base; int i; for (i = 0; i < nums; i++) { - clk = s10_register_gate(&clks[i], base); - if (IS_ERR(clk)) { + hw_clk = s10_register_gate(&clks[i], base); + if (IS_ERR(hw_clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); continue; } - data->clk_data.clks[clks[i].id] = clk; + data->clk_data.hws[clks[i].id] = hw_clk; } return 0; @@ -380,18 +381,18 @@ static int agilex_clk_register_gate(const struct stratix10_gate_clock *clks, static int agilex_clk_register_pll(const struct stratix10_pll_clock *clks, int nums, struct stratix10_clock_data *data) { - struct clk *clk; + struct clk_hw *hw_clk; void __iomem *base = data->base; int i; for (i = 0; i < nums; i++) { - clk = agilex_register_pll(&clks[i], base); - if (IS_ERR(clk)) { + hw_clk = agilex_register_pll(&clks[i], base); + if (IS_ERR(hw_clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); continue; } - data->clk_data.clks[clks[i].id] = clk; + data->clk_data.hws[clks[i].id] = hw_clk; } return 0; @@ -400,64 +401,49 @@ static int agilex_clk_register_pll(const struct stratix10_pll_clock *clks, static int n5x_clk_register_pll(const struct stratix10_pll_clock *clks, int nums, struct stratix10_clock_data *data) { - struct clk *clk; + struct clk_hw *hw_clk; void __iomem *base = data->base; int i; for (i = 0; i < nums; i++) { - clk = n5x_register_pll(&clks[i], base); - if (IS_ERR(clk)) { + hw_clk = n5x_register_pll(&clks[i], base); + if (IS_ERR(hw_clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); continue; } - data->clk_data.clks[clks[i].id] = clk; + data->clk_data.hws[clks[i].id] = hw_clk; } return 0; } -static struct stratix10_clock_data *__socfpga_agilex_clk_init(struct platform_device *pdev, - int nr_clks) +static int agilex_clkmgr_init(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct device *dev = &pdev->dev; struct stratix10_clock_data *clk_data; - struct clk **clk_table; struct resource *res; void __iomem *base; - int ret; + int i, num_clks; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); base = devm_ioremap_resource(dev, res); if (IS_ERR(base)) - return ERR_CAST(base); - - clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL); - if (!clk_data) - return ERR_PTR(-ENOMEM); + return PTR_ERR(base); - clk_data->base = base; - clk_table = devm_kcalloc(dev, nr_clks, sizeof(*clk_table), GFP_KERNEL); - if (!clk_table) - return ERR_PTR(-ENOMEM); - - clk_data->clk_data.clks = clk_table; - clk_data->clk_data.clk_num = nr_clks; - ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data); - if (ret) - return ERR_PTR(ret); + num_clks = AGILEX_NUM_CLKS; - return clk_data; -} + clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws, + num_clks), GFP_KERNEL); + if (!clk_data) + return -ENOMEM; -static int agilex_clkmgr_init(struct platform_device *pdev) -{ - struct stratix10_clock_data *clk_data; + for (i = 0; i < num_clks; i++) + clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT); - clk_data = __socfpga_agilex_clk_init(pdev, AGILEX_NUM_CLKS); - if (IS_ERR(clk_data)) - return PTR_ERR(clk_data); + clk_data->base = base; + clk_data->clk_data.num = num_clks; agilex_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks), clk_data); @@ -470,16 +456,36 @@ static int agilex_clkmgr_init(struct platform_device *pdev) agilex_clk_register_gate(agilex_gate_clks, ARRAY_SIZE(agilex_gate_clks), clk_data); + of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data); return 0; } static int n5x_clkmgr_init(struct platform_device *pdev) { + struct device_node *np = pdev->dev.of_node; + struct device *dev = &pdev->dev; struct stratix10_clock_data *clk_data; + struct resource *res; + void __iomem *base; + int i, num_clks; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + num_clks = AGILEX_NUM_CLKS; + + clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws, + num_clks), GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + for (i = 0; i < num_clks; i++) + clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT); - clk_data = __socfpga_agilex_clk_init(pdev, AGILEX_NUM_CLKS); - if (IS_ERR(clk_data)) - return PTR_ERR(clk_data); + clk_data->base = base; + clk_data->clk_data.num = num_clks; n5x_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks), clk_data); @@ -492,6 +498,7 @@ static int n5x_clkmgr_init(struct platform_device *pdev) agilex_clk_register_gate(agilex_gate_clks, ARRAY_SIZE(agilex_gate_clks), clk_data); + of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data); return 0; } |