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-rw-r--r--drivers/clk/imx/clk-imx7ulp.c31
1 files changed, 31 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
index 42e4667f22fd..2022d9bead91 100644
--- a/drivers/clk/imx/clk-imx7ulp.c
+++ b/drivers/clk/imx/clk-imx7ulp.c
@@ -42,6 +42,19 @@ static const struct clk_div_table ulp_div_table[] = {
{ .val = 7, .div = 64, },
};
+static const int pcc2_uart_clk_ids[] __initconst = {
+ IMX7ULP_CLK_LPUART4,
+ IMX7ULP_CLK_LPUART5,
+};
+
+static const int pcc3_uart_clk_ids[] __initconst = {
+ IMX7ULP_CLK_LPUART6,
+ IMX7ULP_CLK_LPUART7,
+};
+
+static struct clk **pcc2_uart_clks[ARRAY_SIZE(pcc2_uart_clk_ids) + 1] __initdata;
+static struct clk **pcc3_uart_clks[ARRAY_SIZE(pcc3_uart_clk_ids) + 1] __initdata;
+
static void __init imx7ulp_clk_scg1_init(struct device_node *np)
{
struct clk_hw_onecell_data *clk_data;
@@ -135,6 +148,7 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np)
struct clk_hw_onecell_data *clk_data;
struct clk_hw **clks;
void __iomem *base;
+ int i;
clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC2_END),
GFP_KERNEL);
@@ -173,6 +187,14 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np)
imx_check_clk_hws(clks, clk_data->num);
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
+
+ for (i = 0; i < ARRAY_SIZE(pcc2_uart_clk_ids); i++) {
+ int index = pcc2_uart_clk_ids[i];
+
+ pcc2_uart_clks[i] = &clks[index]->clk;
+ }
+
+ imx_register_uart_clocks(pcc2_uart_clks);
}
CLK_OF_DECLARE(imx7ulp_clk_pcc2, "fsl,imx7ulp-pcc2", imx7ulp_clk_pcc2_init);
@@ -181,6 +203,7 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np)
struct clk_hw_onecell_data *clk_data;
struct clk_hw **clks;
void __iomem *base;
+ int i;
clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC3_END),
GFP_KERNEL);
@@ -218,6 +241,14 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np)
imx_check_clk_hws(clks, clk_data->num);
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
+
+ for (i = 0; i < ARRAY_SIZE(pcc3_uart_clk_ids); i++) {
+ int index = pcc3_uart_clk_ids[i];
+
+ pcc3_uart_clks[i] = &clks[index]->clk;
+ }
+
+ imx_register_uart_clocks(pcc3_uart_clks);
}
CLK_OF_DECLARE(imx7ulp_clk_pcc3, "fsl,imx7ulp-pcc3", imx7ulp_clk_pcc3_init);