diff options
Diffstat (limited to 'arch')
1035 files changed, 41107 insertions, 16138 deletions
diff --git a/arch/alpha/include/asm/fcntl.h b/arch/alpha/include/asm/fcntl.h index 70145cbb21cb..1b71ca70c9f6 100644 --- a/arch/alpha/include/asm/fcntl.h +++ b/arch/alpha/include/asm/fcntl.h @@ -31,6 +31,8 @@ #define __O_SYNC 020000000 #define O_SYNC (__O_SYNC|O_DSYNC) +#define O_PATH 040000000 + #define F_GETLK 7 #define F_SETLK 8 #define F_SETLKW 9 diff --git a/arch/alpha/include/asm/futex.h b/arch/alpha/include/asm/futex.h index 945de222ab91..e8a761aee088 100644 --- a/arch/alpha/include/asm/futex.h +++ b/arch/alpha/include/asm/futex.h @@ -29,7 +29,7 @@ : "r" (uaddr), "r"(oparg) \ : "memory") -static inline int futex_atomic_op_inuser (int encoded_op, int __user *uaddr) +static inline int futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr) { int op = (encoded_op >> 28) & 7; int cmp = (encoded_op >> 24) & 15; @@ -39,7 +39,7 @@ static inline int futex_atomic_op_inuser (int encoded_op, int __user *uaddr) if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) oparg = 1 << oparg; - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; pagefault_disable(); @@ -81,21 +81,23 @@ static inline int futex_atomic_op_inuser (int encoded_op, int __user *uaddr) } static inline int -futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) +futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) { - int prev, cmp; + int ret = 0, cmp; + u32 prev; - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; __asm__ __volatile__ ( __ASM_SMP_MB - "1: ldl_l %0,0(%2)\n" - " cmpeq %0,%3,%1\n" - " beq %1,3f\n" - " mov %4,%1\n" - "2: stl_c %1,0(%2)\n" - " beq %1,4f\n" + "1: ldl_l %1,0(%3)\n" + " cmpeq %1,%4,%2\n" + " beq %2,3f\n" + " mov %5,%2\n" + "2: stl_c %2,0(%3)\n" + " beq %2,4f\n" "3: .subsection 2\n" "4: br 1b\n" " .previous\n" @@ -105,11 +107,12 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) " .long 2b-.\n" " lda $31,3b-2b(%0)\n" " .previous\n" - : "=&r"(prev), "=&r"(cmp) + : "+r"(ret), "=&r"(prev), "=&r"(cmp) : "r"(uaddr), "r"((long)oldval), "r"(newval) : "memory"); - return prev; + *uval = prev; + return ret; } #endif /* __KERNEL__ */ diff --git a/arch/alpha/include/asm/ioctls.h b/arch/alpha/include/asm/ioctls.h index 034b6cf5d9f3..80e1cee90f1f 100644 --- a/arch/alpha/include/asm/ioctls.h +++ b/arch/alpha/include/asm/ioctls.h @@ -94,6 +94,7 @@ #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ #define TIOCGDEV _IOR('T',0x32, unsigned int) /* Get primary device node of /dev/console */ #define TIOCSIG _IOW('T',0x36, int) /* Generate signal on Pty slave */ +#define TIOCVHANGUP 0x5437 #define TIOCSERCONFIG 0x5453 #define TIOCSERGWILD 0x5454 diff --git a/arch/alpha/include/asm/rwsem.h b/arch/alpha/include/asm/rwsem.h index 1570c0b54336..a83bbea62c67 100644 --- a/arch/alpha/include/asm/rwsem.h +++ b/arch/alpha/include/asm/rwsem.h @@ -13,44 +13,13 @@ #ifdef __KERNEL__ #include <linux/compiler.h> -#include <linux/list.h> -#include <linux/spinlock.h> -struct rwsem_waiter; - -extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem); -extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem); -extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *); -extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem); - -/* - * the semaphore definition - */ -struct rw_semaphore { - long count; #define RWSEM_UNLOCKED_VALUE 0x0000000000000000L #define RWSEM_ACTIVE_BIAS 0x0000000000000001L #define RWSEM_ACTIVE_MASK 0x00000000ffffffffL #define RWSEM_WAITING_BIAS (-0x0000000100000000L) #define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS #define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS) - spinlock_t wait_lock; - struct list_head wait_list; -}; - -#define __RWSEM_INITIALIZER(name) \ - { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \ - LIST_HEAD_INIT((name).wait_list) } - -#define DECLARE_RWSEM(name) \ - struct rw_semaphore name = __RWSEM_INITIALIZER(name) - -static inline void init_rwsem(struct rw_semaphore *sem) -{ - sem->count = RWSEM_UNLOCKED_VALUE; - spin_lock_init(&sem->wait_lock); - INIT_LIST_HEAD(&sem->wait_list); -} static inline void __down_read(struct rw_semaphore *sem) { @@ -250,10 +219,5 @@ static inline long rwsem_atomic_update(long val, struct rw_semaphore *sem) #endif } -static inline int rwsem_is_locked(struct rw_semaphore *sem) -{ - return (sem->count != 0); -} - #endif /* __KERNEL__ */ #endif /* _ALPHA_RWSEM_H */ diff --git a/arch/alpha/kernel/osf_sys.c b/arch/alpha/kernel/osf_sys.c index fe698b5045e9..376f22130791 100644 --- a/arch/alpha/kernel/osf_sys.c +++ b/arch/alpha/kernel/osf_sys.c @@ -230,44 +230,24 @@ linux_to_osf_statfs(struct kstatfs *linux_stat, struct osf_statfs __user *osf_st return copy_to_user(osf_stat, &tmp_stat, bufsiz) ? -EFAULT : 0; } -static int -do_osf_statfs(struct path *path, struct osf_statfs __user *buffer, - unsigned long bufsiz) +SYSCALL_DEFINE3(osf_statfs, const char __user *, pathname, + struct osf_statfs __user *, buffer, unsigned long, bufsiz) { struct kstatfs linux_stat; - int error = vfs_statfs(path, &linux_stat); + int error = user_statfs(pathname, &linux_stat); if (!error) error = linux_to_osf_statfs(&linux_stat, buffer, bufsiz); return error; } -SYSCALL_DEFINE3(osf_statfs, const char __user *, pathname, - struct osf_statfs __user *, buffer, unsigned long, bufsiz) -{ - struct path path; - int retval; - - retval = user_path(pathname, &path); - if (!retval) { - retval = do_osf_statfs(&path, buffer, bufsiz); - path_put(&path); - } - return retval; -} - SYSCALL_DEFINE3(osf_fstatfs, unsigned long, fd, struct osf_statfs __user *, buffer, unsigned long, bufsiz) { - struct file *file; - int retval; - - retval = -EBADF; - file = fget(fd); - if (file) { - retval = do_osf_statfs(&file->f_path, buffer, bufsiz); - fput(file); - } - return retval; + struct kstatfs linux_stat; + int error = fd_statfs(fd, &linux_stat); + if (!error) + error = linux_to_osf_statfs(&linux_stat, buffer, bufsiz); + return error; } /* diff --git a/arch/alpha/kernel/time.c b/arch/alpha/kernel/time.c index c1f3e7cb82a4..a58e84f1a63b 100644 --- a/arch/alpha/kernel/time.c +++ b/arch/alpha/kernel/time.c @@ -159,7 +159,7 @@ void read_persistent_clock(struct timespec *ts) /* * timer_interrupt() needs to keep up the real-time clock, - * as well as call the "do_timer()" routine every clocktick + * as well as call the "xtime_update()" routine every clocktick */ irqreturn_t timer_interrupt(int irq, void *dev) { @@ -172,8 +172,6 @@ irqreturn_t timer_interrupt(int irq, void *dev) profile_tick(CPU_PROFILING); #endif - write_seqlock(&xtime_lock); - /* * Calculate how many ticks have passed since the last update, * including any previous partial leftover. Save any resulting @@ -187,9 +185,7 @@ irqreturn_t timer_interrupt(int irq, void *dev) nticks = delta >> FIX_SHIFT; if (nticks) - do_timer(nticks); - - write_sequnlock(&xtime_lock); + xtime_update(nticks); if (test_irq_work_pending()) { clear_irq_work_pending(); diff --git a/arch/alpha/kernel/vmlinux.lds.S b/arch/alpha/kernel/vmlinux.lds.S index 003ef4c02585..433be2a24f31 100644 --- a/arch/alpha/kernel/vmlinux.lds.S +++ b/arch/alpha/kernel/vmlinux.lds.S @@ -1,5 +1,6 @@ #include <asm-generic/vmlinux.lds.h> #include <asm/thread_info.h> +#include <asm/cache.h> #include <asm/page.h> OUTPUT_FORMAT("elf64-alpha") @@ -38,7 +39,7 @@ SECTIONS __init_begin = ALIGN(PAGE_SIZE); INIT_TEXT_SECTION(PAGE_SIZE) INIT_DATA_SECTION(16) - PERCPU(PAGE_SIZE) + PERCPU(L1_CACHE_BYTES, PAGE_SIZE) /* Align to THREAD_SIZE rather than PAGE_SIZE here so any padding page needed for the THREAD_SIZE aligned init_task gets freed after init */ . = ALIGN(THREAD_SIZE); @@ -46,7 +47,7 @@ SECTIONS /* Freed after init ends here */ _data = .; - RW_DATA_SECTION(64, PAGE_SIZE, THREAD_SIZE) + RW_DATA_SECTION(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE) .got : { *(.got) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 166efa2a19cd..e34bf0272da4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -7,7 +7,7 @@ config ARM select HAVE_MEMBLOCK select RTC_LIB select SYS_SUPPORTS_APM_EMULATION - select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI) + select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI) select HAVE_OPROFILE if (HAVE_PERF_EVENTS) select HAVE_ARCH_KGDB select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL) @@ -24,7 +24,7 @@ config ARM select HAVE_PERF_EVENTS select PERF_USE_VMALLOC select HAVE_REGS_AND_STACK_ACCESS_API - select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7)) + select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) select HAVE_C_RECORDMCOUNT select HAVE_GENERIC_HARDIRQS select HAVE_SPARSE_IRQ @@ -63,6 +63,10 @@ config GENERIC_CLOCKEVENTS_BROADCAST depends on GENERIC_CLOCKEVENTS default y if SMP +config KTIME_SCALAR + bool + default y + config HAVE_TCM bool select GENERIC_ALLOCATOR @@ -178,11 +182,6 @@ config FIQ config ARCH_MTD_XIP bool -config ARM_L1_CACHE_SHIFT_6 - bool - help - Setting ARM L1 cache line size to 64 Bytes. - config VECTORS_BASE hex default 0xffff0000 if MMU || CPU_HIGH_VECTOR @@ -191,6 +190,22 @@ config VECTORS_BASE help The base address of exception vectors. +config ARM_PATCH_PHYS_VIRT + bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)" + depends on EXPERIMENTAL + depends on !XIP_KERNEL && MMU + depends on !ARCH_REALVIEW || !SPARSEMEM + help + Patch phys-to-virt translation functions at runtime according to + the position of the kernel in system memory. + + This can only be used with non-XIP with MMU kernels where + the base of physical memory is at a 16MB boundary. + +config ARM_PATCH_PHYS_VIRT_16BIT + def_bool y + depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM + source "init/Kconfig" source "kernel/Kconfig.freezer" @@ -212,15 +227,6 @@ choice prompt "ARM system type" default ARCH_VERSATILE -config ARCH_AAEC2000 - bool "Agilent AAEC-2000 based" - select CPU_ARM920T - select ARM_AMBA - select HAVE_CLK - select ARCH_USES_GETTIMEOFFSET - help - This enables support for systems based on the Agilent AAEC-2000 - config ARCH_INTEGRATOR bool "ARM Ltd. Integrator family" select ARM_AMBA @@ -346,7 +352,7 @@ config ARCH_FOOTBRIDGE bool "FootBridge" select CPU_SA110 select FOOTBRIDGE - select ARCH_USES_GETTIMEOFFSET + select GENERIC_CLOCKEVENTS help Support for systems based on the DC21285 companion chip ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. @@ -457,6 +463,7 @@ config ARCH_IXP4XX config ARCH_DOVE bool "Marvell Dove" + select CPU_V6K select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS @@ -795,17 +802,6 @@ config ARCH_TCC_926 help Support for Telechips TCC ARM926-based systems. -config ARCH_LH7A40X - bool "Sharp LH7A40X" - select CPU_ARM922T - select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM - select ARCH_USES_GETTIMEOFFSET - help - Say Y here for systems based on one of the Sharp LH7A40X - System on a Chip processors. These CPUs include an ARM922T - core with a wide array of integrated devices for - hand-held and low-power applications. - config ARCH_U300 bool "ST-Ericsson U300 Series" depends on MMU @@ -875,6 +871,16 @@ config PLAT_SPEAR help Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). +config ARCH_VT8500 + bool "VIA/WonderMedia 85xx" + select CPU_ARM926T + select GENERIC_GPIO + select ARCH_HAS_CPUFREQ + select GENERIC_CLOCKEVENTS + select ARCH_REQUIRE_GPIOLIB + select HAVE_PWM + help + Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. endchoice # @@ -882,8 +888,6 @@ endchoice # Kconfigs may be included either alphabetically (according to the # plat- suffix) or along side the corresponding mach-* source. # -source "arch/arm/mach-aaec2000/Kconfig" - source "arch/arm/mach-at91/Kconfig" source "arch/arm/mach-bcmring/Kconfig" @@ -922,8 +926,6 @@ source "arch/arm/mach-kirkwood/Kconfig" source "arch/arm/mach-ks8695/Kconfig" -source "arch/arm/mach-lh7a40x/Kconfig" - source "arch/arm/mach-loki/Kconfig" source "arch/arm/mach-lpc32xx/Kconfig" @@ -1007,6 +1009,8 @@ source "arch/arm/mach-versatile/Kconfig" source "arch/arm/mach-vexpress/Kconfig" +source "arch/arm/mach-vt8500/Kconfig" + source "arch/arm/mach-w90x900/Kconfig" # Definitions to make life easier @@ -1048,7 +1052,7 @@ config XSCALE_PMU default y config CPU_HAS_PMU - depends on (CPU_V6 || CPU_V7 || XSCALE_PMU) && \ + depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \ (!ARCH_OMAP3 || OMAP3_EMU) default y bool @@ -1064,7 +1068,7 @@ endif config ARM_ERRATA_411920 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" - depends on CPU_V6 + depends on CPU_V6 || CPU_V6K help Invalidation of the Instruction Cache operation can fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. @@ -1140,7 +1144,7 @@ config ARM_ERRATA_742231 config PL310_ERRATA_588369 bool "Clean & Invalidate maintenance operations do not invalidate clean lines" - depends on CACHE_L2X0 && ARCH_OMAP4 + depends on CACHE_L2X0 help The PL310 L2 cache controller implements three types of Clean & Invalidate maintenance operations: by Physical Address @@ -1149,8 +1153,7 @@ config PL310_ERRATA_588369 clean operation followed immediately by an invalidate operation, both performing to the same memory location. This functionality is not correctly implemented in PL310 as clean lines are not - invalidated as a result of these operations. Note that this errata - uses Texas Instrument's secure monitor api. + invalidated as a result of these operations. config ARM_ERRATA_720789 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" @@ -1164,6 +1167,17 @@ config ARM_ERRATA_720789 tables. The workaround changes the TLB flushing routines to invalidate entries regardless of the ASID. +config PL310_ERRATA_727915 + bool "Background Clean & Invalidate by Way operation can cause data corruption" + depends on CACHE_L2X0 + help + PL310 implements the Clean & Invalidate by Way L2 cache maintenance + operation (offset 0x7FC). This operation runs in background so that + PL310 can handle normal accesses while it is in progress. Under very + rare circumstances, due to this erratum, write data can be lost when + PL310 treats a cacheable write transaction during a Clean & + Invalidate by Way operation. + config ARM_ERRATA_743622 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" depends on CPU_V7 @@ -1202,6 +1216,28 @@ config ARM_ERRATA_753970 This has the same effect as the cache sync operation: store buffer drain and waiting for all buffers empty. +config ARM_ERRATA_754322 + bool "ARM errata: possible faulty MMU translations following an ASID switch" + depends on CPU_V7 + help + This option enables the workaround for the 754322 Cortex-A9 (r2p*, + r3p*) erratum. A speculative memory access may cause a page table walk + which starts prior to an ASID switch but completes afterwards. This + can populate the micro-TLB with a stale entry which may be hit with + the new ASID. This workaround places two dsb instructions in the mm + switching code so that no page table walks can cross the ASID switch. + +config ARM_ERRATA_754327 + bool "ARM errata: no automatic Store Buffer drain" + depends on CPU_V7 && SMP + help + This option enables the workaround for the 754327 Cortex-A9 (prior to + r2p0) erratum. The Store Buffer does not have any automatic draining + mechanism and therefore a livelock may occur if an external agent + continuously polls a memory location waiting to observe an update. + This workaround defines cpu_relax() as smp_mb(), preventing correctly + written polling loops from denying visibility of updates to memory. + endmenu source "arch/arm/common/Kconfig" @@ -1275,6 +1311,7 @@ source "kernel/time/Kconfig" config SMP bool "Symmetric Multi-Processing (EXPERIMENTAL)" depends on EXPERIMENTAL + depends on CPU_V6K || CPU_V7 depends on GENERIC_CLOCKEVENTS depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \ MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \ @@ -1386,7 +1423,7 @@ config HZ config THUMB2_KERNEL bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)" - depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL + depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL select AEABI select ARM_ASM_UNIFIED help @@ -1396,6 +1433,37 @@ config THUMB2_KERNEL If unsure, say N. +config THUMB2_AVOID_R_ARM_THM_JUMP11 + bool "Work around buggy Thumb-2 short branch relocations in gas" + depends on THUMB2_KERNEL && MODULES + default y + help + Various binutils versions can resolve Thumb-2 branches to + locally-defined, preemptible global symbols as short-range "b.n" + branch instructions. + + This is a problem, because there's no guarantee the final + destination of the symbol, or any candidate locations for a + trampoline, are within range of the branch. For this reason, the + kernel does not support fixing up the R_ARM_THM_JUMP11 (102) + relocation in modules at all, and it makes little sense to add + support. + + The symptom is that the kernel fails with an "unsupported + relocation" error when loading some modules. + + Until fixed tools are available, passing + -fno-optimize-sibling-calls to gcc should prevent gcc generating + code which hits this problem, at the cost of a bit of extra runtime + stack usage in some cases. + + The problem is described in more detail at: + https://bugs.launchpad.net/binutils-linaro/+bug/725126 + + Only Thumb-2 kernels are affected. + + Unless you are sure your tools don't have this problem, say Y. + config ARM_ASM_UNIFIED bool @@ -1644,6 +1712,18 @@ config ZBOOT_ROM Say Y here if you intend to execute your compressed kernel image (zImage) directly from ROM or flash. If unsure, say N. +config ZBOOT_ROM_MMCIF + bool "Include MMCIF loader in zImage (EXPERIMENTAL)" + depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL + help + Say Y here to include experimental MMCIF loading code in the + ROM-able zImage. With this enabled it is possible to write the + the ROM-able zImage kernel image to an MMC card and boot the + kernel straight from the reset vector. At reset the processor + Mask ROM will load the first part of the the ROM-able zImage + which in turn loads the rest the kernel image to RAM using the + MMCIF hardware block. + config CMDLINE string "Default kernel command string" default "" @@ -1877,7 +1957,7 @@ config FPE_FASTFPE config VFP bool "VFP-format floating point maths" - depends on CPU_V6 || CPU_ARM926T || CPU_V7 || CPU_FEROCEON + depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON help Say Y to include VFP support code in the kernel. This is needed if your hardware includes a VFP unit. diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 6f7b29294c80..5c7114bb8a25 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -89,6 +89,7 @@ tune-$(CONFIG_CPU_XSCALE) :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) tune-$(CONFIG_CPU_XSC3) :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale tune-$(CONFIG_CPU_FEROCEON) :=$(call cc-option,-mtune=marvell-f,-mtune=xscale) tune-$(CONFIG_CPU_V6) :=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm) +tune-$(CONFIG_CPU_V6K) :=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm) ifeq ($(CONFIG_AEABI),y) CFLAGS_ABI :=-mabi=aapcs-linux -mno-thumb-interwork @@ -105,6 +106,10 @@ AFLAGS_AUTOIT :=$(call as-option,-Wa$(comma)-mimplicit-it=always,-Wa$(comma)-mau AFLAGS_NOWARN :=$(call as-option,-Wa$(comma)-mno-warn-deprecated,-Wa$(comma)-W) CFLAGS_THUMB2 :=-mthumb $(AFLAGS_AUTOIT) $(AFLAGS_NOWARN) AFLAGS_THUMB2 :=$(CFLAGS_THUMB2) -Wa$(comma)-mthumb +# Work around buggy relocation from gas if requested: +ifeq ($(CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11),y) +CFLAGS_MODULE +=-fno-optimize-sibling-calls +endif endif # Need -Uarm for gcc < 3.x @@ -126,7 +131,6 @@ endif # Machine directory name. This list is sorted alphanumerically # by CONFIG_* macro name. -machine-$(CONFIG_ARCH_AAEC2000) := aaec2000 machine-$(CONFIG_ARCH_AT91) := at91 machine-$(CONFIG_ARCH_BCMRING) := bcmring machine-$(CONFIG_ARCH_CLPS711X) := clps711x @@ -146,7 +150,6 @@ machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood machine-$(CONFIG_ARCH_KS8695) := ks8695 -machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x machine-$(CONFIG_ARCH_LOKI) := loki machine-$(CONFIG_ARCH_LPC32XX) := lpc32xx machine-$(CONFIG_ARCH_MMP) := mmp @@ -190,6 +193,7 @@ machine-$(CONFIG_ARCH_U300) := u300 machine-$(CONFIG_ARCH_U8500) := ux500 machine-$(CONFIG_ARCH_VERSATILE) := versatile machine-$(CONFIG_ARCH_VEXPRESS) := vexpress +machine-$(CONFIG_ARCH_VT8500) := vt8500 machine-$(CONFIG_ARCH_W90X900) := w90x900 machine-$(CONFIG_ARCH_NUC93X) := nuc93x machine-$(CONFIG_FOOTBRIDGE) := footbridge @@ -280,7 +284,7 @@ bzImage: zImage zImage Image xipImage bootpImage uImage: vmlinux $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@ -zinstall install: vmlinux +zinstall uinstall install: vmlinux $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@ # We use MRPROPER_FILES and CLEAN_FILES now @@ -301,6 +305,7 @@ define archhelp echo ' (supply initrd image via make variable INITRD=<path>)' echo ' install - Install uncompressed kernel' echo ' zinstall - Install compressed kernel' + echo ' uinstall - Install U-Boot wrapped compressed kernel' echo ' Install using (your) ~/bin/$(INSTALLKERNEL) or' echo ' (distribution) /sbin/$(INSTALLKERNEL) or' echo ' install to $$(INSTALL_PATH) and run lilo' diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile index 4d26f2c52a75..9128fddf1109 100644 --- a/arch/arm/boot/Makefile +++ b/arch/arm/boot/Makefile @@ -99,6 +99,10 @@ zinstall: $(obj)/zImage $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \ $(obj)/zImage System.map "$(INSTALL_PATH)" +uinstall: $(obj)/uImage + $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \ + $(obj)/uImage System.map "$(INSTALL_PATH)" + zi: $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \ $(obj)/zImage System.map "$(INSTALL_PATH)" diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 0a8f748e506a..f9f77c65dff3 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -4,9 +4,20 @@ # create a compressed vmlinuz image from the original vmlinux # +OBJS = + +# Ensure that mmcif loader code appears early in the image +# to minimise that number of bocks that have to be read in +# order to load it. +ifeq ($(CONFIG_ZBOOT_ROM_MMCIF),y) +ifeq ($(CONFIG_ARCH_SH7372),y) +OBJS += mmcif-sh7372.o +endif +endif + AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET) HEAD = head.o -OBJS = misc.o decompress.o +OBJS += misc.o decompress.o FONTC = $(srctree)/drivers/video/console/font_acorn_8x8.c # @@ -29,6 +40,10 @@ ifeq ($(CONFIG_ARCH_SA1100),y) OBJS += head-sa1100.o endif +ifeq ($(CONFIG_ARCH_VT8500),y) +OBJS += head-vt8500.o +endif + ifeq ($(CONFIG_CPU_XSCALE),y) OBJS += head-xscale.o endif @@ -83,9 +98,11 @@ endif EXTRA_CFLAGS := -fpic -fno-builtin EXTRA_AFLAGS := -Wa,-march=all +# Provide size of uncompressed kernel to the decompressor via a linker symbol. +LDFLAGS_vmlinux = --defsym _image_size=$(shell stat -c "%s" $(obj)/../Image) # Supply ZRELADDR to the decompressor via a linker symbol. ifneq ($(CONFIG_AUTO_ZRELADDR),y) -LDFLAGS_vmlinux := --defsym zreladdr=$(ZRELADDR) +LDFLAGS_vmlinux += --defsym zreladdr=$(ZRELADDR) endif ifeq ($(CONFIG_CPU_ENDIAN_BE8),y) LDFLAGS_vmlinux += --be8 diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S index 30973b76e6ae..c943d2e7da9d 100644 --- a/arch/arm/boot/compressed/head-shmobile.S +++ b/arch/arm/boot/compressed/head-shmobile.S @@ -25,6 +25,36 @@ /* load board-specific initialization code */ #include <mach/zboot.h> +#ifdef CONFIG_ZBOOT_ROM_MMCIF + /* Load image from MMC */ + adr sp, __tmp_stack + 128 + ldr r0, __image_start + ldr r1, __image_end + subs r1, r1, r0 + ldr r0, __load_base + bl mmcif_loader + + /* Jump to loaded code */ + ldr r0, __loaded + ldr r1, __image_start + sub r0, r0, r1 + ldr r1, __load_base + add pc, r0, r1 + +__image_start: + .long _start +__image_end: + .long _got_end +__load_base: + .long CONFIG_MEMORY_START + 0x02000000 @ Load at 32Mb into SDRAM +__loaded: + .long __continue + .align +__tmp_stack: + .space 128 +__continue: +#endif /* CONFIG_ZBOOT_ROM_MMCIF */ + b 1f __atags:@ tag #1 .long 12 @ tag->hdr.size = tag_size(tag_core); diff --git a/arch/arm/boot/compressed/head-vt8500.S b/arch/arm/boot/compressed/head-vt8500.S new file mode 100644 index 000000000000..1dc1e21a3be3 --- /dev/null +++ b/arch/arm/boot/compressed/head-vt8500.S @@ -0,0 +1,46 @@ +/* + * linux/arch/arm/boot/compressed/head-vt8500.S + * + * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> + * + * VIA VT8500 specific tweaks. This is merged into head.S by the linker. + * + */ + +#include <linux/linkage.h> +#include <asm/mach-types.h> + + .section ".start", "ax" + +__VT8500_start: + @ Compare the SCC ID register against a list of known values + ldr r1, .SCCID + ldr r3, [r1] + + @ VT8500 override + ldr r4, .VT8500SCC + cmp r3, r4 + ldreq r7, .ID_BV07 + beq .Lendvt8500 + + @ WM8505 override + ldr r4, .WM8505SCC + cmp r3, r4 + ldreq r7, .ID_8505 + beq .Lendvt8500 + + @ Otherwise, leave the bootloader's machine id untouched + +.SCCID: + .word 0xd8120000 +.VT8500SCC: + .word 0x34000102 +.WM8505SCC: + .word 0x34260103 + +.ID_BV07: + .word MACH_TYPE_BV07 +.ID_8505: + .word MACH_TYPE_WM8505_7IN_NETBOOK + +.Lendvt8500: diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 7193884ed8b0..84ac4d656310 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -21,7 +21,7 @@ #if defined(CONFIG_DEBUG_ICEDCC) -#ifdef CONFIG_CPU_V6 +#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) .macro loadsp, rb, tmp .endm .macro writeb, ch, rb @@ -128,14 +128,14 @@ wait: mrc p14, 0, pc, c0, c1, 0 .arm @ Always enter in ARM state start: .type start,#function - THUMB( adr r12, BSYM(1f) ) - THUMB( bx r12 ) - THUMB( .rept 6 ) - ARM( .rept 8 ) + .rept 7 mov r0, r0 .endr + ARM( mov r0, r0 ) + ARM( b 1f ) + THUMB( adr r12, BSYM(1f) ) + THUMB( bx r12 ) - b 1f .word 0x016f2818 @ Magic numbers to help the loader .word start @ absolute load/run zImage address .word _edata @ zImage end address @@ -174,9 +174,7 @@ not_angel: */ .text - adr r0, LC0 - ldmia r0, {r1, r2, r3, r5, r6, r11, ip} - ldr sp, [r0, #28] + #ifdef CONFIG_AUTO_ZRELADDR @ determine final kernel image address mov r4, pc @@ -185,35 +183,108 @@ not_angel: #else ldr r4, =zreladdr #endif - subs r0, r0, r1 @ calculate the delta offset - @ if delta is zero, we are - beq not_relocated @ running at the address we - @ were linked at. + bl cache_on + +restart: adr r0, LC0 + ldmia r0, {r1, r2, r3, r5, r6, r9, r11, r12} + ldr sp, [r0, #32] + + /* + * We might be running at a different address. We need + * to fix up various pointers. + */ + sub r0, r0, r1 @ calculate the delta offset + add r5, r5, r0 @ _start + add r6, r6, r0 @ _edata +#ifndef CONFIG_ZBOOT_ROM + /* malloc space is above the relocated stack (64k max) */ + add sp, sp, r0 + add r10, sp, #0x10000 +#else /* - * We're running at a different address. We need to fix - * up various pointers: - * r5 - zImage base address (_start) - * r6 - size of decompressed image - * r11 - GOT start - * ip - GOT end + * With ZBOOT_ROM the bss/stack is non relocatable, + * but someone could still run this code from RAM, + * in which case our reference is _edata. */ - add r5, r5, r0 + mov r10, r6 +#endif + +/* + * Check to see if we will overwrite ourselves. + * r4 = final kernel address + * r5 = start of this image + * r9 = size of decompressed image + * r10 = end of this image, including bss/stack/malloc space if non XIP + * We basically want: + * r4 >= r10 -> OK + * r4 + image length <= r5 -> OK + */ + cmp r4, r10 + bhs wont_overwrite + add r10, r4, r9 + cmp r10, r5 + bls wont_overwrite + +/* + * Relocate ourselves past the end of the decompressed kernel. + * r5 = start of this image + * r6 = _edata + * r10 = end of the decompressed kernel + * Because we always copy ahead, we need to do it from the end and go + * backward in case the source and destination overlap. + */ + /* Round up to next 256-byte boundary. */ + add r10, r10, #256 + bic r10, r10, #255 + + sub r9, r6, r5 @ size to copy + add r9, r9, #31 @ rounded up to a multiple + bic r9, r9, #31 @ ... of 32 bytes + add r6, r9, r5 + add r9, r9, r10 + +1: ldmdb r6!, {r0 - r3, r10 - r12, lr} + cmp r6, r5 + stmdb r9!, {r0 - r3, r10 - r12, lr} + bhi 1b + + /* Preserve offset to relocated code. */ + sub r6, r9, r6 + + bl cache_clean_flush + + adr r0, BSYM(restart) + add r0, r0, r6 + mov pc, r0 + +wont_overwrite: +/* + * If delta is zero, we are running at the address we were linked at. + * r0 = delta + * r2 = BSS start + * r3 = BSS end + * r4 = kernel execution address + * r7 = architecture ID + * r8 = atags pointer + * r11 = GOT start + * r12 = GOT end + * sp = stack pointer + */ + teq r0, #0 + beq not_relocated add r11, r11, r0 - add ip, ip, r0 + add r12, r12, r0 #ifndef CONFIG_ZBOOT_ROM /* * If we're running fully PIC === CONFIG_ZBOOT_ROM = n, * we need to fix up pointers into the BSS region. - * r2 - BSS start - * r3 - BSS end - * sp - stack pointer + * Note that the stack pointer has already been fixed up. */ add r2, r2, r0 add r3, r3, r0 - add sp, sp, r0 /* * Relocate all entries in the GOT table. @@ -221,7 +292,7 @@ not_angel: 1: ldr r1, [r11, #0] @ relocate entries in the GOT add r1, r1, r0 @ table. This fixes up the str r1, [r11], #4 @ C references. - cmp r11, ip + cmp r11, r12 blo 1b #else @@ -234,7 +305,7 @@ not_angel: cmphs r3, r1 @ _end < entry addlo r1, r1, r0 @ table. This fixes up the str r1, [r11], #4 @ C references. - cmp r11, ip + cmp r11, r12 blo 1b #endif @@ -246,76 +317,24 @@ not_relocated: mov r0, #0 cmp r2, r3 blo 1b - /* - * The C runtime environment should now be setup - * sufficiently. Turn the cache on, set up some - * pointers, and start decompressing. - */ - bl cache_on - - mov r1, sp @ malloc space above stack - add r2, sp, #0x10000 @ 64k max - /* - * Check to see if we will overwrite ourselves. - * r4 = final kernel address - * r5 = start of this image - * r6 = size of decompressed image - * r2 = end of malloc space (and therefore this image) - * We basically want: - * r4 >= r2 -> OK - * r4 + image length <= r5 -> OK + * The C runtime environment should now be setup sufficiently. + * Set up some pointers, and start decompressing. + * r4 = kernel execution address + * r7 = architecture ID + * r8 = atags pointer */ - cmp r4, r2 - bhs wont_overwrite - add r0, r4, r6 - cmp r0, r5 - bls wont_overwrite - - mov r5, r2 @ decompress after malloc space - mov r0, r5 + mov r0, r4 + mov r1, sp @ malloc space above stack + add r2, sp, #0x10000 @ 64k max mov r3, r7 bl decompress_kernel - - add r0, r0, #127 + 128 @ alignment + stack - bic r0, r0, #127 @ align the kernel length -/* - * r0 = decompressed kernel length - * r1-r3 = unused - * r4 = kernel execution address - * r5 = decompressed kernel start - * r7 = architecture ID - * r8 = atags pointer - * r9-r12,r14 = corrupted - */ - add r1, r5, r0 @ end of decompressed kernel - adr r2, reloc_start - ldr r3, LC1 - add r3, r2, r3 -1: ldmia r2!, {r9 - r12, r14} @ copy relocation code - stmia r1!, {r9 - r12, r14} - ldmia r2!, {r9 - r12, r14} - stmia r1!, {r9 - r12, r14} - cmp r2, r3 - blo 1b - mov sp, r1 - add sp, sp, #128 @ relocate the stack - bl cache_clean_flush - ARM( add pc, r5, r0 ) @ call relocation code - THUMB( add r12, r5, r0 ) - THUMB( mov pc, r12 ) @ call relocation code - -/* - * We're not in danger of overwriting ourselves. Do this the simple way. - * - * r4 = kernel execution address - * r7 = architecture ID - */ -wont_overwrite: mov r0, r4 - mov r3, r7 - bl decompress_kernel - b call_kernel + bl cache_off + mov r0, #0 @ must be zero + mov r1, r7 @ restore architecture number + mov r2, r8 @ restore atags pointer + mov pc, r4 @ call kernel .align 2 .type LC0, #object @@ -323,11 +342,11 @@ LC0: .word LC0 @ r1 .word __bss_start @ r2 .word _end @ r3 .word _start @ r5 - .word _image_size @ r6 + .word _edata @ r6 + .word _image_size @ r9 .word _got_start @ r11 .word _got_end @ ip .word user_stack_end @ sp -LC1: .word reloc_end - reloc_start .size LC0, . - LC0 #ifdef CONFIG_ARCH_RPC @@ -353,7 +372,7 @@ params: ldr r0, =0x10000100 @ params_phys for RPC * On exit, * r0, r1, r2, r3, r9, r10, r12 corrupted * This routine must preserve: - * r4, r5, r6, r7, r8 + * r4, r7, r8 */ .align 5 cache_on: mov r3, #8 @ cache_on function @@ -551,43 +570,6 @@ __common_mmu_cache_on: #endif /* - * All code following this line is relocatable. It is relocated by - * the above code to the end of the decompressed kernel image and - * executed there. During this time, we have no stacks. - * - * r0 = decompressed kernel length - * r1-r3 = unused - * r4 = kernel execution address - * r5 = decompressed kernel start - * r7 = architecture ID - * r8 = atags pointer - * r9-r12,r14 = corrupted - */ - .align 5 -reloc_start: add r9, r5, r0 - sub r9, r9, #128 @ do not copy the stack - debug_reloc_start - mov r1, r4 -1: - .rept 4 - ldmia r5!, {r0, r2, r3, r10 - r12, r14} @ relocate kernel - stmia r1!, {r0, r2, r3, r10 - r12, r14} - .endr - - cmp r5, r9 - blo 1b - mov sp, r1 - add sp, sp, #128 @ relocate the stack - debug_reloc_end - -call_kernel: bl cache_clean_flush - bl cache_off - mov r0, #0 @ must be zero - mov r1, r7 @ restore architecture number - mov r2, r8 @ restore atags pointer - mov pc, r4 @ call kernel - -/* * Here follow the relocatable cache support functions for the * various processors. This is a generic hook for locating an * entry and jumping to an instruction at the specified offset @@ -791,7 +773,7 @@ proc_types: * On exit, * r0, r1, r2, r3, r9, r12 corrupted * This routine must preserve: - * r4, r6, r7 + * r4, r7, r8 */ .align 5 cache_off: mov r3, #12 @ cache_off function @@ -866,7 +848,7 @@ __armv3_mmu_cache_off: * On exit, * r1, r2, r3, r9, r10, r11, r12 corrupted * This routine must preserve: - * r0, r4, r5, r6, r7 + * r4, r6, r7, r8 */ .align 5 cache_clean_flush: @@ -1088,7 +1070,6 @@ memdump: mov r12, r0 #endif .ltorg -reloc_end: .align .section ".stack", "aw", %nobits diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c index e653a6d3c8d9..4657e877bf8f 100644 --- a/arch/arm/boot/compressed/misc.c +++ b/arch/arm/boot/compressed/misc.c @@ -36,7 +36,7 @@ extern void error(char *x); #ifdef CONFIG_DEBUG_ICEDCC -#ifdef CONFIG_CPU_V6 +#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) static void icedcc_putc(int ch) { diff --git a/arch/arm/boot/compressed/mmcif-sh7372.c b/arch/arm/boot/compressed/mmcif-sh7372.c new file mode 100644 index 000000000000..e6180af241f6 --- /dev/null +++ b/arch/arm/boot/compressed/mmcif-sh7372.c @@ -0,0 +1,87 @@ +/* + * sh7372 MMCIF loader + * + * Copyright (C) 2010 Magnus Damm + * Copyright (C) 2010 Simon Horman + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/mmc/sh_mmcif.h> +#include <mach/mmcif.h> + +#define MMCIF_BASE (void __iomem *)0xe6bd0000 + +#define PORT84CR (void __iomem *)0xe6050054 +#define PORT85CR (void __iomem *)0xe6050055 +#define PORT86CR (void __iomem *)0xe6050056 +#define PORT87CR (void __iomem *)0xe6050057 +#define PORT88CR (void __iomem *)0xe6050058 +#define PORT89CR (void __iomem *)0xe6050059 +#define PORT90CR (void __iomem *)0xe605005a +#define PORT91CR (void __iomem *)0xe605005b +#define PORT92CR (void __iomem *)0xe605005c +#define PORT99CR (void __iomem *)0xe6050063 + +#define SMSTPCR3 (void __iomem *)0xe615013c + +/* SH7372 specific MMCIF loader + * + * loads the zImage from an MMC card starting from block 1. + * + * The image must be start with a vrl4 header and + * the zImage must start at offset 512 of the image. That is, + * at block 2 (=byte 1024) on the media + * + * Use the following line to write the vrl4 formated zImage + * to an MMC card + * # dd if=vrl4.out of=/dev/sdx bs=512 seek=1 + */ +asmlinkage void mmcif_loader(unsigned char *buf, unsigned long len) +{ + mmcif_init_progress(); + mmcif_update_progress(MMCIF_PROGRESS_ENTER); + + /* Initialise MMC + * registers: PORT84CR-PORT92CR + * (MMCD0_0-MMCD0_7,MMCCMD0 Control) + * value: 0x04 - select function 4 + */ + __raw_writeb(0x04, PORT84CR); + __raw_writeb(0x04, PORT85CR); + __raw_writeb(0x04, PORT86CR); + __raw_writeb(0x04, PORT87CR); + __raw_writeb(0x04, PORT88CR); + __raw_writeb(0x04, PORT89CR); + __raw_writeb(0x04, PORT90CR); + __raw_writeb(0x04, PORT91CR); + __raw_writeb(0x04, PORT92CR); + + /* Initialise MMC + * registers: PORT99CR (MMCCLK0 Control) + * value: 0x10 | 0x04 - enable output | select function 4 + */ + __raw_writeb(0x14, PORT99CR); + + /* Enable clock to MMC hardware block */ + __raw_writel(__raw_readl(SMSTPCR3) & ~(1 << 12), SMSTPCR3); + + mmcif_update_progress(MMCIF_PROGRESS_INIT); + + /* setup MMCIF hardware */ + sh_mmcif_boot_init(MMCIF_BASE); + + mmcif_update_progress(MMCIF_PROGRESS_LOAD); + + /* load kernel via MMCIF interface */ + sh_mmcif_boot_do_read(MMCIF_BASE, 2, /* Kernel is at block 2 */ + (len + SH_MMCIF_BBS - 1) / SH_MMCIF_BBS, buf); + + + /* Disable clock to MMC hardware block */ + __raw_writel(__raw_readl(SMSTPCR3) & (1 << 12), SMSTPCR3); + + mmcif_update_progress(MMCIF_PROGRESS_DONE); +} diff --git a/arch/arm/boot/compressed/vmlinux.lds.in b/arch/arm/boot/compressed/vmlinux.lds.in index 366a924019ac..5309909d7282 100644 --- a/arch/arm/boot/compressed/vmlinux.lds.in +++ b/arch/arm/boot/compressed/vmlinux.lds.in @@ -43,9 +43,6 @@ SECTIONS _etext = .; - /* Assume size of decompressed image is 4x the compressed image */ - _image_size = (_etext - _text) * 4; - _got_start = .; .got : { *(.got) } _got_end = .; diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 224377211151..cb6b041c39d2 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -44,6 +44,19 @@ struct gic_chip_data { void __iomem *cpu_base; }; +/* + * Supported arch specific GIC irq extension. + * Default make them NULL. + */ +struct irq_chip gic_arch_extn = { + .irq_ack = NULL, + .irq_mask = NULL, + .irq_unmask = NULL, + .irq_retrigger = NULL, + .irq_set_type = NULL, + .irq_set_wake = NULL, +}; + #ifndef MAX_GIC_NR #define MAX_GIC_NR 1 #endif @@ -74,6 +87,8 @@ static inline unsigned int gic_irq(struct irq_data *d) static void gic_ack_irq(struct irq_data *d) { spin_lock(&irq_controller_lock); + if (gic_arch_extn.irq_ack) + gic_arch_extn.irq_ack(d); writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); spin_unlock(&irq_controller_lock); } @@ -84,6 +99,8 @@ static void gic_mask_irq(struct irq_data *d) spin_lock(&irq_controller_lock); writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); + if (gic_arch_extn.irq_mask) + gic_arch_extn.irq_mask(d); spin_unlock(&irq_controller_lock); } @@ -92,6 +109,8 @@ static void gic_unmask_irq(struct irq_data *d) u32 mask = 1 << (d->irq % 32); spin_lock(&irq_controller_lock); + if (gic_arch_extn.irq_unmask) + gic_arch_extn.irq_unmask(d); writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); spin_unlock(&irq_controller_lock); } @@ -116,6 +135,9 @@ static int gic_set_type(struct irq_data *d, unsigned int type) spin_lock(&irq_controller_lock); + if (gic_arch_extn.irq_set_type) + gic_arch_extn.irq_set_type(d, type); + val = readl(base + GIC_DIST_CONFIG + confoff); if (type == IRQ_TYPE_LEVEL_HIGH) val &= ~confmask; @@ -141,32 +163,54 @@ static int gic_set_type(struct irq_data *d, unsigned int type) return 0; } +static int gic_retrigger(struct irq_data *d) +{ + if (gic_arch_extn.irq_retrigger) + return gic_arch_extn.irq_retrigger(d); + + return -ENXIO; +} + #ifdef CONFIG_SMP -static int -gic_set_cpu(struct irq_data *d, const struct cpumask *mask_val, bool force) +static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, + bool force) { void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); unsigned int shift = (d->irq % 4) * 8; unsigned int cpu = cpumask_first(mask_val); - u32 val; - struct irq_desc *desc; + u32 val, mask, bit; - spin_lock(&irq_controller_lock); - desc = irq_to_desc(d->irq); - if (desc == NULL) { - spin_unlock(&irq_controller_lock); + if (cpu >= 8) return -EINVAL; - } + + mask = 0xff << shift; + bit = 1 << (cpu + shift); + + spin_lock(&irq_controller_lock); d->node = cpu; - val = readl(reg) & ~(0xff << shift); - val |= 1 << (cpu + shift); - writel(val, reg); + val = readl(reg) & ~mask; + writel(val | bit, reg); spin_unlock(&irq_controller_lock); return 0; } #endif +#ifdef CONFIG_PM +static int gic_set_wake(struct irq_data *d, unsigned int on) +{ + int ret = -ENXIO; + + if (gic_arch_extn.irq_set_wake) + ret = gic_arch_extn.irq_set_wake(d, on); + + return ret; +} + +#else +#define gic_set_wake NULL +#endif + static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) { struct gic_chip_data *chip_data = get_irq_data(irq); @@ -202,9 +246,11 @@ static struct irq_chip gic_chip = { .irq_mask = gic_mask_irq, .irq_unmask = gic_unmask_irq, .irq_set_type = gic_set_type, + .irq_retrigger = gic_retrigger, #ifdef CONFIG_SMP - .irq_set_affinity = gic_set_cpu, + .irq_set_affinity = gic_set_affinity, #endif + .irq_set_wake = gic_set_wake, }; void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) diff --git a/arch/arm/configs/lpd7a400_defconfig b/arch/arm/configs/lpd7a400_defconfig deleted file mode 100644 index 5a48f171204c..000000000000 --- a/arch/arm/configs/lpd7a400_defconfig +++ /dev/null @@ -1,68 +0,0 @@ -CONFIG_EXPERIMENTAL=y -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EXPERT=y -# CONFIG_HOTPLUG is not set -# CONFIG_EPOLL is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_ARCH_LH7A40X=y -CONFIG_MACH_LPD7A400=y -CONFIG_PREEMPT=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_FPE_NWFPE=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_IPV6 is not set -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_IDE=y -CONFIG_SCSI=y -# CONFIG_SCSI_PROC_FS is not set -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMC91X=y -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -# CONFIG_SERIO is not set -CONFIG_SERIAL_LH7A40X=y -CONFIG_SERIAL_LH7A40X_CONSOLE=y -CONFIG_FB=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_MIXER_OSS=y -CONFIG_SND_PCM_OSS=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_CRAMFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y diff --git a/arch/arm/configs/lpd7a404_defconfig b/arch/arm/configs/lpd7a404_defconfig deleted file mode 100644 index 22d0631de009..000000000000 --- a/arch/arm/configs/lpd7a404_defconfig +++ /dev/null @@ -1,81 +0,0 @@ -CONFIG_EXPERIMENTAL=y -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_LOG_BUF_SHIFT=16 -CONFIG_EXPERT=y -# CONFIG_HOTPLUG is not set -# CONFIG_EPOLL is not set -CONFIG_SLAB=y -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_ARCH_LH7A40X=y -CONFIG_MACH_LPD7A404=y -CONFIG_PREEMPT=y -CONFIG_DISCONTIGMEM_MANUAL=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_FPE_NWFPE=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_IPV6 is not set -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_IDE=y -CONFIG_SCSI=y -# CONFIG_SCSI_PROC_FS is not set -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMC91X=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -# CONFIG_SERIO is not set -CONFIG_SERIAL_LH7A40X=y -CONFIG_SERIAL_LH7A40X_CONSOLE=y -CONFIG_FB=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_MIXER_OSS=y -CONFIG_SND_PCM_OSS=y -CONFIG_USB=y -CONFIG_USB_DEVICEFS=y -CONFIG_USB_MON=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_USB_STORAGE_DEBUG=y -CONFIG_USB_STORAGE_DATAFAB=y -CONFIG_USB_GADGET=y -CONFIG_USB_ZERO=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -CONFIG_INOTIFY=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_CRAMFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig new file mode 100644 index 000000000000..7a9267e5da55 --- /dev/null +++ b/arch/arm/configs/tegra_defconfig @@ -0,0 +1,123 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_SCHED=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_ELF_CORE is not set +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_TEGRA=y +CONFIG_MACH_HARMONY=y +CONFIG_TEGRA_DEBUG_UARTD=y +CONFIG_ARM_ERRATA_742230=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_SMP=y +CONFIG_NR_CPUS=2 +CONFIG_PREEMPT=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_HIGHMEM=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_VFP=y +CONFIG_PM=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_INET_ESP=y +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_TUNNEL=y +CONFIG_IPV6_MULTIPLE_TABLES=y +# CONFIG_WIRELESS is not set +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_MISC_DEVICES=y +CONFIG_AD525X_DPOT=y +CONFIG_AD525X_DPOT_I2C=y +CONFIG_ICS932S401=y +CONFIG_APDS9802ALS=y +CONFIG_ISL29003=y +CONFIG_NETDEVICES=y +CONFIG_DUMMY=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +# CONFIG_HWMON is not set +# CONFIG_MFD_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_DNOTIFY is not set +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +CONFIG_DEBUG_SLAB=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_DEBUG_MUTEXES=y +CONFIG_DEBUG_SPINLOCK_SLEEP=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_VM=y +CONFIG_DEBUG_SG=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_TWOFISH=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y diff --git a/arch/arm/include/asm/a.out-core.h b/arch/arm/include/asm/a.out-core.h index 93d04acaa31f..92f10cb5c70c 100644 --- a/arch/arm/include/asm/a.out-core.h +++ b/arch/arm/include/asm/a.out-core.h @@ -32,11 +32,7 @@ static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump) dump->u_dsize = (tsk->mm->brk - tsk->mm->start_data + PAGE_SIZE - 1) >> PAGE_SHIFT; dump->u_ssize = 0; - dump->u_debugreg[0] = tsk->thread.debug.bp[0].address; - dump->u_debugreg[1] = tsk->thread.debug.bp[1].address; - dump->u_debugreg[2] = tsk->thread.debug.bp[0].insn.arm; - dump->u_debugreg[3] = tsk->thread.debug.bp[1].insn.arm; - dump->u_debugreg[4] = tsk->thread.debug.nsaved; + memset(dump->u_debugreg, 0, sizeof(dump->u_debugreg)); if (dump->start_stack < 0x04000000) dump->u_ssize = (0x04000000 - dump->start_stack) >> PAGE_SHIFT; diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index 7b1bb2bbaf88..af54ed102f5f 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -149,14 +149,18 @@ ____atomic_test_and_change_bit(unsigned int bit, volatile unsigned long *p) */ /* + * Native endian assembly bitops. nr = 0 -> word 0 bit 0. + */ +extern void _set_bit(int nr, volatile unsigned long * p); +extern void _clear_bit(int nr, volatile unsigned long * p); +extern void _change_bit(int nr, volatile unsigned long * p); +extern int _test_and_set_bit(int nr, volatile unsigned long * p); +extern int _test_and_clear_bit(int nr, volatile unsigned long * p); +extern int _test_and_change_bit(int nr, volatile unsigned long * p); + +/* * Little endian assembly bitops. nr = 0 -> byte 0 bit 0. */ -extern void _set_bit_le(int nr, volatile unsigned long * p); -extern void _clear_bit_le(int nr, volatile unsigned long * p); -extern void _change_bit_le(int nr, volatile unsigned long * p); -extern int _test_and_set_bit_le(int nr, volatile unsigned long * p); -extern int _test_and_clear_bit_le(int nr, volatile unsigned long * p); -extern int _test_and_change_bit_le(int nr, volatile unsigned long * p); extern int _find_first_zero_bit_le(const void * p, unsigned size); extern int _find_next_zero_bit_le(const void * p, int size, int offset); extern int _find_first_bit_le(const unsigned long *p, unsigned size); @@ -165,12 +169,6 @@ extern int _find_next_bit_le(const unsigned long *p, int size, int offset); /* * Big endian assembly bitops. nr = 0 -> byte 3 bit 0. */ -extern void _set_bit_be(int nr, volatile unsigned long * p); -extern void _clear_bit_be(int nr, volatile unsigned long * p); -extern void _change_bit_be(int nr, volatile unsigned long * p); -extern int _test_and_set_bit_be(int nr, volatile unsigned long * p); -extern int _test_and_clear_bit_be(int nr, volatile unsigned long * p); -extern int _test_and_change_bit_be(int nr, volatile unsigned long * p); extern int _find_first_zero_bit_be(const void * p, unsigned size); extern int _find_next_zero_bit_be(const void * p, int size, int offset); extern int _find_first_bit_be(const unsigned long *p, unsigned size); @@ -180,33 +178,26 @@ extern int _find_next_bit_be(const unsigned long *p, int size, int offset); /* * The __* form of bitops are non-atomic and may be reordered. */ -#define ATOMIC_BITOP_LE(name,nr,p) \ - (__builtin_constant_p(nr) ? \ - ____atomic_##name(nr, p) : \ - _##name##_le(nr,p)) - -#define ATOMIC_BITOP_BE(name,nr,p) \ - (__builtin_constant_p(nr) ? \ - ____atomic_##name(nr, p) : \ - _##name##_be(nr,p)) +#define ATOMIC_BITOP(name,nr,p) \ + (__builtin_constant_p(nr) ? ____atomic_##name(nr, p) : _##name(nr,p)) #else -#define ATOMIC_BITOP_LE(name,nr,p) _##name##_le(nr,p) -#define ATOMIC_BITOP_BE(name,nr,p) _##name##_be(nr,p) +#define ATOMIC_BITOP(name,nr,p) _##name(nr,p) #endif -#define NONATOMIC_BITOP(name,nr,p) \ - (____nonatomic_##name(nr, p)) +/* + * Native endian atomic definitions. + */ +#define set_bit(nr,p) ATOMIC_BITOP(set_bit,nr,p) +#define clear_bit(nr,p) ATOMIC_BITOP(clear_bit,nr,p) +#define change_bit(nr,p) ATOMIC_BITOP(change_bit,nr,p) +#define test_and_set_bit(nr,p) ATOMIC_BITOP(test_and_set_bit,nr,p) +#define test_and_clear_bit(nr,p) ATOMIC_BITOP(test_and_clear_bit,nr,p) +#define test_and_change_bit(nr,p) ATOMIC_BITOP(test_and_change_bit,nr,p) #ifndef __ARMEB__ /* * These are the little endian, atomic definitions. */ -#define set_bit(nr,p) ATOMIC_BITOP_LE(set_bit,nr,p) -#define clear_bit(nr,p) ATOMIC_BITOP_LE(clear_bit,nr,p) -#define change_bit(nr,p) ATOMIC_BITOP_LE(change_bit,nr,p) -#define test_and_set_bit(nr,p) ATOMIC_BITOP_LE(test_and_set_bit,nr,p) -#define test_and_clear_bit(nr,p) ATOMIC_BITOP_LE(test_and_clear_bit,nr,p) -#define test_and_change_bit(nr,p) ATOMIC_BITOP_LE(test_and_change_bit,nr,p) #define find_first_zero_bit(p,sz) _find_first_zero_bit_le(p,sz) #define find_next_zero_bit(p,sz,off) _find_next_zero_bit_le(p,sz,off) #define find_first_bit(p,sz) _find_first_bit_le(p,sz) @@ -215,16 +206,9 @@ extern int _find_next_bit_be(const unsigned long *p, int size, int offset); #define WORD_BITOFF_TO_LE(x) ((x)) #else - /* * These are the big endian, atomic definitions. */ -#define set_bit(nr,p) ATOMIC_BITOP_BE(set_bit,nr,p) -#define clear_bit(nr,p) ATOMIC_BITOP_BE(clear_bit,nr,p) -#define change_bit(nr,p) ATOMIC_BITOP_BE(change_bit,nr,p) -#define test_and_set_bit(nr,p) ATOMIC_BITOP_BE(test_and_set_bit,nr,p) -#define test_and_clear_bit(nr,p) ATOMIC_BITOP_BE(test_and_clear_bit,nr,p) -#define test_and_change_bit(nr,p) ATOMIC_BITOP_BE(test_and_change_bit,nr,p) #define find_first_zero_bit(p,sz) _find_first_zero_bit_be(p,sz) #define find_next_zero_bit(p,sz,off) _find_next_zero_bit_be(p,sz,off) #define find_first_bit(p,sz) _find_first_bit_be(p,sz) diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index 3acd8fa25e34..d5d8d5c72682 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -12,7 +12,7 @@ #include <linux/mm.h> -#include <asm/glue.h> +#include <asm/glue-cache.h> #include <asm/shmparam.h> #include <asm/cachetype.h> #include <asm/outercache.h> @@ -20,123 +20,6 @@ #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT) /* - * Cache Model - * =========== - */ -#undef _CACHE -#undef MULTI_CACHE - -#if defined(CONFIG_CPU_CACHE_V3) -# ifdef _CACHE -# define MULTI_CACHE 1 -# else -# define _CACHE v3 -# endif -#endif - -#if defined(CONFIG_CPU_CACHE_V4) -# ifdef _CACHE -# define MULTI_CACHE 1 -# else -# define _CACHE v4 -# endif -#endif - -#if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \ - defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) || \ - defined(CONFIG_CPU_ARM1026) -# define MULTI_CACHE 1 -#endif - -#if defined(CONFIG_CPU_FA526) -# ifdef _CACHE -# define MULTI_CACHE 1 -# else -# define _CACHE fa -# endif -#endif - -#if defined(CONFIG_CPU_ARM926T) -# ifdef _CACHE -# define MULTI_CACHE 1 -# else -# define _CACHE arm926 -# endif -#endif - -#if defined(CONFIG_CPU_ARM940T) -# ifdef _CACHE -# define MULTI_CACHE 1 -# else -# define _CACHE arm940 -# endif -#endif - -#if defined(CONFIG_CPU_ARM946E) -# ifdef _CACHE -# define MULTI_CACHE 1 -# else -# define _CACHE arm946 -# endif -#endif - -#if defined(CONFIG_CPU_CACHE_V4WB) -# ifdef _CACHE -# define MULTI_CACHE 1 -# else -# define _CACHE v4wb -# endif -#endif - -#if defined(CONFIG_CPU_XSCALE) -# ifdef _CACHE -# define MULTI_CACHE 1 -# else -# define _CACHE xscale -# endif -#endif - -#if defined(CONFIG_CPU_XSC3) -# ifdef _CACHE -# define MULTI_CACHE 1 -# else -# define _CACHE xsc3 -# endif -#endif - -#if defined(CONFIG_CPU_MOHAWK) -# ifdef _CACHE -# define MULTI_CACHE 1 -# else -# define _CACHE mohawk -# endif -#endif - -#if defined(CONFIG_CPU_FEROCEON) -# define MULTI_CACHE 1 -#endif - -#if defined(CONFIG_CPU_V6) -//# ifdef _CACHE -# define MULTI_CACHE 1 -//# else -//# define _CACHE v6 -//# endif -#endif - -#if defined(CONFIG_CPU_V7) -//# ifdef _CACHE -# define MULTI_CACHE 1 -//# else -//# define _CACHE v7 -//# endif -#endif - -#if !defined(_CACHE) && !defined(MULTI_CACHE) -#error Unknown cache maintainence model -#endif - -/* * This flag is used to indicate that the page pointed to by a pte is clean * and does not require cleaning before returning it to the user. */ @@ -249,19 +132,11 @@ extern struct cpu_cache_fns cpu_cache; * visible to the CPU. */ #define dmac_map_area cpu_cache.dma_map_area -#define dmac_unmap_area cpu_cache.dma_unmap_area +#define dmac_unmap_area cpu_cache.dma_unmap_area #define dmac_flush_range cpu_cache.dma_flush_range #else -#define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all) -#define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all) -#define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all) -#define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range) -#define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range) -#define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range) -#define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area) - extern void __cpuc_flush_icache_all(void); extern void __cpuc_flush_kern_all(void); extern void __cpuc_flush_user_all(void); @@ -276,10 +151,6 @@ extern void __cpuc_flush_dcache_area(void *, size_t); * is visible to DMA, or data written by DMA to system memory is * visible to the CPU. */ -#define dmac_map_area __glue(_CACHE,_dma_map_area) -#define dmac_unmap_area __glue(_CACHE,_dma_unmap_area) -#define dmac_flush_range __glue(_CACHE,_dma_flush_range) - extern void dmac_map_area(const void *, size_t, int); extern void dmac_unmap_area(const void *, size_t, int); extern void dmac_flush_range(const void *, const void *); @@ -316,7 +187,8 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *, * Optimized __flush_icache_all for the common cases. Note that UP ARMv7 * will fall through to use __flush_icache_all_generic. */ -#if (defined(CONFIG_CPU_V7) && defined(CONFIG_CPU_V6)) || \ +#if (defined(CONFIG_CPU_V7) && \ + (defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K))) || \ defined(CONFIG_SMP_ON_UP) #define __flush_icache_preferred __cpuc_flush_icache_all #elif __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP) diff --git a/arch/arm/include/asm/cpu-multi32.h b/arch/arm/include/asm/cpu-multi32.h deleted file mode 100644 index e2b5b0b2116a..000000000000 --- a/arch/arm/include/asm/cpu-multi32.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * arch/arm/include/asm/cpu-multi32.h - * - * Copyright (C) 2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <asm/page.h> - -struct mm_struct; - -/* - * Don't change this structure - ASM code - * relies on it. - */ -extern struct processor { - /* MISC - * get data abort address/flags - */ - void (*_data_abort)(unsigned long pc); - /* - * Retrieve prefetch fault address - */ - unsigned long (*_prefetch_abort)(unsigned long lr); - /* - * Set up any processor specifics - */ - void (*_proc_init)(void); - /* - * Disable any processor specifics - */ - void (*_proc_fin)(void); - /* - * Special stuff for a reset - */ - void (*reset)(unsigned long addr) __attribute__((noreturn)); - /* - * Idle the processor - */ - int (*_do_idle)(void); - /* - * Processor architecture specific - */ - /* - * clean a virtual address range from the - * D-cache without flushing the cache. - */ - void (*dcache_clean_area)(void *addr, int size); - - /* - * Set the page table - */ - void (*switch_mm)(unsigned long pgd_phys, struct mm_struct *mm); - /* - * Set a possibly extended PTE. Non-extended PTEs should - * ignore 'ext'. - */ - void (*set_pte_ext)(pte_t *ptep, pte_t pte, unsigned int ext); -} processor; - -#define cpu_proc_init() processor._proc_init() -#define cpu_proc_fin() processor._proc_fin() -#define cpu_reset(addr) processor.reset(addr) -#define cpu_do_idle() processor._do_idle() -#define cpu_dcache_clean_area(addr,sz) processor.dcache_clean_area(addr,sz) -#define cpu_set_pte_ext(ptep,pte,ext) processor.set_pte_ext(ptep,pte,ext) -#define cpu_do_switch_mm(pgd,mm) processor.switch_mm(pgd,mm) diff --git a/arch/arm/include/asm/cpu-single.h b/arch/arm/include/asm/cpu-single.h deleted file mode 100644 index f073a6d2a406..000000000000 --- a/arch/arm/include/asm/cpu-single.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * arch/arm/include/asm/cpu-single.h - * - * Copyright (C) 2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/* - * Single CPU - */ -#ifdef __STDC__ -#define __catify_fn(name,x) name##x -#else -#define __catify_fn(name,x) name/**/x -#endif -#define __cpu_fn(name,x) __catify_fn(name,x) - -/* - * If we are supporting multiple CPUs, then we must use a table of - * function pointers for this lot. Otherwise, we can optimise the - * table away. - */ -#define cpu_proc_init __cpu_fn(CPU_NAME,_proc_init) -#define cpu_proc_fin __cpu_fn(CPU_NAME,_proc_fin) -#define cpu_reset __cpu_fn(CPU_NAME,_reset) -#define cpu_do_idle __cpu_fn(CPU_NAME,_do_idle) -#define cpu_dcache_clean_area __cpu_fn(CPU_NAME,_dcache_clean_area) -#define cpu_do_switch_mm __cpu_fn(CPU_NAME,_switch_mm) -#define cpu_set_pte_ext __cpu_fn(CPU_NAME,_set_pte_ext) - -#include <asm/page.h> - -struct mm_struct; - -/* declare all the functions as extern */ -extern void cpu_proc_init(void); -extern void cpu_proc_fin(void); -extern int cpu_do_idle(void); -extern void cpu_dcache_clean_area(void *, int); -extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm); -extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext); -extern void cpu_reset(unsigned long addr) __attribute__((noreturn)); diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index 20ae96cc0020..ed5bc9e05a4e 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -23,6 +23,8 @@ #define CPUID_EXT_ISAR4 "c2, 4" #define CPUID_EXT_ISAR5 "c2, 5" +extern unsigned int processor_id; + #ifdef CONFIG_CPU_CP15 #define read_cpuid(reg) \ ({ \ @@ -43,7 +45,6 @@ __val; \ }) #else -extern unsigned int processor_id; #define read_cpuid(reg) (processor_id) #define read_cpuid_ext(reg) 0 #endif diff --git a/arch/arm/include/asm/fncpy.h b/arch/arm/include/asm/fncpy.h new file mode 100644 index 000000000000..de5354746924 --- /dev/null +++ b/arch/arm/include/asm/fncpy.h @@ -0,0 +1,94 @@ +/* + * arch/arm/include/asm/fncpy.h - helper macros for function body copying + * + * Copyright (C) 2011 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * These macros are intended for use when there is a need to copy a low-level + * function body into special memory. + * + * For example, when reconfiguring the SDRAM controller, the code doing the + * reconfiguration may need to run from SRAM. + * + * NOTE: that the copied function body must be entirely self-contained and + * position-independent in order for this to work properly. + * + * NOTE: in order for embedded literals and data to get referenced correctly, + * the alignment of functions must be preserved when copying. To ensure this, + * the source and destination addresses for fncpy() must be aligned to a + * multiple of 8 bytes: you will be get a BUG() if this condition is not met. + * You will typically need a ".align 3" directive in the assembler where the + * function to be copied is defined, and ensure that your allocator for the + * destination buffer returns 8-byte-aligned pointers. + * + * Typical usage example: + * + * extern int f(args); + * extern uint32_t size_of_f; + * int (*copied_f)(args); + * void *sram_buffer; + * + * copied_f = fncpy(sram_buffer, &f, size_of_f); + * + * ... later, call the function: ... + * + * copied_f(args); + * + * The size of the function to be copied can't be determined from C: + * this must be determined by other means, such as adding assmbler directives + * in the file where f is defined. + */ + +#ifndef __ASM_FNCPY_H +#define __ASM_FNCPY_H + +#include <linux/types.h> +#include <linux/string.h> + +#include <asm/bug.h> +#include <asm/cacheflush.h> + +/* + * Minimum alignment requirement for the source and destination addresses + * for function copying. + */ +#define FNCPY_ALIGN 8 + +#define fncpy(dest_buf, funcp, size) ({ \ + uintptr_t __funcp_address; \ + typeof(funcp) __result; \ + \ + asm("" : "=r" (__funcp_address) : "0" (funcp)); \ + \ + /* \ + * Ensure alignment of source and destination addresses, \ + * disregarding the function's Thumb bit: \ + */ \ + BUG_ON((uintptr_t)(dest_buf) & (FNCPY_ALIGN - 1) || \ + (__funcp_address & ~(uintptr_t)1 & (FNCPY_ALIGN - 1))); \ + \ + memcpy(dest_buf, (void const *)(__funcp_address & ~1), size); \ + flush_icache_range((unsigned long)(dest_buf), \ + (unsigned long)(dest_buf) + (size)); \ + \ + asm("" : "=r" (__result) \ + : "0" ((uintptr_t)(dest_buf) | (__funcp_address & 1))); \ + \ + __result; \ +}) + +#endif /* !__ASM_FNCPY_H */ diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h index b33fe7065b38..199a6b6de7f4 100644 --- a/arch/arm/include/asm/futex.h +++ b/arch/arm/include/asm/futex.h @@ -35,7 +35,7 @@ : "cc", "memory") static inline int -futex_atomic_op_inuser (int encoded_op, int __user *uaddr) +futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr) { int op = (encoded_op >> 28) & 7; int cmp = (encoded_op >> 24) & 15; @@ -46,7 +46,7 @@ futex_atomic_op_inuser (int encoded_op, int __user *uaddr) if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) oparg = 1 << oparg; - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; pagefault_disable(); /* implies preempt_disable() */ @@ -88,36 +88,35 @@ futex_atomic_op_inuser (int encoded_op, int __user *uaddr) } static inline int -futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) +futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) { - int val; + int ret = 0; + u32 val; - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; - pagefault_disable(); /* implies preempt_disable() */ - __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n" - "1: " T(ldr) " %0, [%3]\n" - " teq %0, %1\n" + "1: " T(ldr) " %1, [%4]\n" + " teq %1, %2\n" " it eq @ explicit IT needed for the 2b label\n" - "2: " T(streq) " %2, [%3]\n" + "2: " T(streq) " %3, [%4]\n" "3:\n" " .pushsection __ex_table,\"a\"\n" " .align 3\n" " .long 1b, 4f, 2b, 4f\n" " .popsection\n" " .pushsection .fixup,\"ax\"\n" - "4: mov %0, %4\n" + "4: mov %0, %5\n" " b 3b\n" " .popsection" - : "=&r" (val) + : "+r" (ret), "=&r" (val) : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT) : "cc", "memory"); - pagefault_enable(); /* subsumes preempt_enable() */ - - return val; + *uval = val; + return ret; } #endif /* !SMP */ diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h new file mode 100644 index 000000000000..c7afbc552c7f --- /dev/null +++ b/arch/arm/include/asm/glue-cache.h @@ -0,0 +1,146 @@ +/* + * arch/arm/include/asm/glue-cache.h + * + * Copyright (C) 1999-2002 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef ASM_GLUE_CACHE_H +#define ASM_GLUE_CACHE_H + +#include <asm/glue.h> + +/* + * Cache Model + * =========== + */ +#undef _CACHE +#undef MULTI_CACHE + +#if defined(CONFIG_CPU_CACHE_V3) +# ifdef _CACHE +# define MULTI_CACHE 1 +# else +# define _CACHE v3 +# endif +#endif + +#if defined(CONFIG_CPU_CACHE_V4) +# ifdef _CACHE +# define MULTI_CACHE 1 +# else +# define _CACHE v4 +# endif +#endif + +#if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \ + defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) || \ + defined(CONFIG_CPU_ARM1026) +# define MULTI_CACHE 1 +#endif + +#if defined(CONFIG_CPU_FA526) +# ifdef _CACHE +# define MULTI_CACHE 1 +# else +# define _CACHE fa +# endif +#endif + +#if defined(CONFIG_CPU_ARM926T) +# ifdef _CACHE +# define MULTI_CACHE 1 +# else +# define _CACHE arm926 +# endif +#endif + +#if defined(CONFIG_CPU_ARM940T) +# ifdef _CACHE +# define MULTI_CACHE 1 +# else +# define _CACHE arm940 +# endif +#endif + +#if defined(CONFIG_CPU_ARM946E) +# ifdef _CACHE +# define MULTI_CACHE 1 +# else +# define _CACHE arm946 +# endif +#endif + +#if defined(CONFIG_CPU_CACHE_V4WB) +# ifdef _CACHE +# define MULTI_CACHE 1 +# else +# define _CACHE v4wb +# endif +#endif + +#if defined(CONFIG_CPU_XSCALE) +# ifdef _CACHE +# define MULTI_CACHE 1 +# else +# define _CACHE xscale +# endif +#endif + +#if defined(CONFIG_CPU_XSC3) +# ifdef _CACHE +# define MULTI_CACHE 1 +# else +# define _CACHE xsc3 +# endif +#endif + +#if defined(CONFIG_CPU_MOHAWK) +# ifdef _CACHE +# define MULTI_CACHE 1 +# else +# define _CACHE mohawk +# endif +#endif + +#if defined(CONFIG_CPU_FEROCEON) +# define MULTI_CACHE 1 +#endif + +#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) +//# ifdef _CACHE +# define MULTI_CACHE 1 +//# else +//# define _CACHE v6 +//# endif +#endif + +#if defined(CONFIG_CPU_V7) +//# ifdef _CACHE +# define MULTI_CACHE 1 +//# else +//# define _CACHE v7 +//# endif +#endif + +#if !defined(_CACHE) && !defined(MULTI_CACHE) +#error Unknown cache maintainence model +#endif + +#ifndef MULTI_CACHE +#define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all) +#define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all) +#define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all) +#define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range) +#define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range) +#define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range) +#define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area) + +#define dmac_map_area __glue(_CACHE,_dma_map_area) +#define dmac_unmap_area __glue(_CACHE,_dma_unmap_area) +#define dmac_flush_range __glue(_CACHE,_dma_flush_range) +#endif + +#endif diff --git a/arch/arm/include/asm/glue-df.h b/arch/arm/include/asm/glue-df.h new file mode 100644 index 000000000000..354d571e8bcc --- /dev/null +++ b/arch/arm/include/asm/glue-df.h @@ -0,0 +1,110 @@ +/* + * arch/arm/include/asm/glue-df.h + * + * Copyright (C) 1997-1999 Russell King + * Copyright (C) 2000-2002 Deep Blue Solutions Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef ASM_GLUE_DF_H +#define ASM_GLUE_DF_H + +#include <asm/glue.h> + +/* + * Data Abort Model + * ================ + * + * We have the following to choose from: + * arm6 - ARM6 style + * arm7 - ARM7 style + * v4_early - ARMv4 without Thumb early abort handler + * v4t_late - ARMv4 with Thumb late abort handler + * v4t_early - ARMv4 with Thumb early abort handler + * v5tej_early - ARMv5 with Thumb and Java early abort handler + * xscale - ARMv5 with Thumb with Xscale extensions + * v6_early - ARMv6 generic early abort handler + * v7_early - ARMv7 generic early abort handler + */ +#undef CPU_DABORT_HANDLER +#undef MULTI_DABORT + +#if defined(CONFIG_CPU_ARM610) +# ifdef CPU_DABORT_HANDLER +# define MULTI_DABORT 1 +# else +# define CPU_DABORT_HANDLER cpu_arm6_data_abort +# endif +#endif + +#if defined(CONFIG_CPU_ARM710) +# ifdef CPU_DABORT_HANDLER +# define MULTI_DABORT 1 +# else +# define CPU_DABORT_HANDLER cpu_arm7_data_abort +# endif +#endif + +#ifdef CONFIG_CPU_ABRT_LV4T +# ifdef CPU_DABORT_HANDLER +# define MULTI_DABORT 1 +# else +# define CPU_DABORT_HANDLER v4t_late_abort +# endif +#endif + +#ifdef CONFIG_CPU_ABRT_EV4 +# ifdef CPU_DABORT_HANDLER +# define MULTI_DABORT 1 +# else +# define CPU_DABORT_HANDLER v4_early_abort +# endif +#endif + +#ifdef CONFIG_CPU_ABRT_EV4T +# ifdef CPU_DABORT_HANDLER +# define MULTI_DABORT 1 +# else +# define CPU_DABORT_HANDLER v4t_early_abort +# endif +#endif + +#ifdef CONFIG_CPU_ABRT_EV5TJ +# ifdef CPU_DABORT_HANDLER +# define MULTI_DABORT 1 +# else +# define CPU_DABORT_HANDLER v5tj_early_abort +# endif +#endif + +#ifdef CONFIG_CPU_ABRT_EV5T +# ifdef CPU_DABORT_HANDLER +# define MULTI_DABORT 1 +# else +# define CPU_DABORT_HANDLER v5t_early_abort +# endif +#endif + +#ifdef CONFIG_CPU_ABRT_EV6 +# ifdef CPU_DABORT_HANDLER +# define MULTI_DABORT 1 +# else +# define CPU_DABORT_HANDLER v6_early_abort +# endif +#endif + +#ifdef CONFIG_CPU_ABRT_EV7 +# ifdef CPU_DABORT_HANDLER +# define MULTI_DABORT 1 +# else +# define CPU_DABORT_HANDLER v7_early_abort +# endif +#endif + +#ifndef CPU_DABORT_HANDLER +#error Unknown data abort handler type +#endif + +#endif diff --git a/arch/arm/include/asm/glue-pf.h b/arch/arm/include/asm/glue-pf.h new file mode 100644 index 000000000000..d385f37c13f0 --- /dev/null +++ b/arch/arm/include/asm/glue-pf.h @@ -0,0 +1,57 @@ +/* + * arch/arm/include/asm/glue-pf.h + * + * Copyright (C) 1997-1999 Russell King + * Copyright (C) 2000-2002 Deep Blue Solutions Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef ASM_GLUE_PF_H +#define ASM_GLUE_PF_H + +#include <asm/glue.h> + +/* + * Prefetch Abort Model + * ================ + * + * We have the following to choose from: + * legacy - no IFSR, no IFAR + * v6 - ARMv6: IFSR, no IFAR + * v7 - ARMv7: IFSR and IFAR + */ + +#undef CPU_PABORT_HANDLER +#undef MULTI_PABORT + +#ifdef CONFIG_CPU_PABRT_LEGACY +# ifdef CPU_PABORT_HANDLER +# define MULTI_PABORT 1 +# else +# define CPU_PABORT_HANDLER legacy_pabort +# endif +#endif + +#ifdef CONFIG_CPU_PABRT_V6 +# ifdef CPU_PABORT_HANDLER +# define MULTI_PABORT 1 +# else +# define CPU_PABORT_HANDLER v6_pabort +# endif +#endif + +#ifdef CONFIG_CPU_PABRT_V7 +# ifdef CPU_PABORT_HANDLER +# define MULTI_PABORT 1 +# else +# define CPU_PABORT_HANDLER v7_pabort +# endif +#endif + +#ifndef CPU_PABORT_HANDLER +#error Unknown prefetch abort handler type +#endif + +#endif diff --git a/arch/arm/include/asm/glue-proc.h b/arch/arm/include/asm/glue-proc.h new file mode 100644 index 000000000000..e2be7f142668 --- /dev/null +++ b/arch/arm/include/asm/glue-proc.h @@ -0,0 +1,264 @@ +/* + * arch/arm/include/asm/glue-proc.h + * + * Copyright (C) 1997-1999 Russell King + * Copyright (C) 2000 Deep Blue Solutions Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef ASM_GLUE_PROC_H +#define ASM_GLUE_PROC_H + +#include <asm/glue.h> + +/* + * Work out if we need multiple CPU support + */ +#undef MULTI_CPU +#undef CPU_NAME + +/* + * CPU_NAME - the prefix for CPU related functions + */ + +#ifdef CONFIG_CPU_ARM610 +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_arm6 +# endif +#endif + +#ifdef CONFIG_CPU_ARM7TDMI +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_arm7tdmi +# endif +#endif + +#ifdef CONFIG_CPU_ARM710 +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_arm7 +# endif +#endif + +#ifdef CONFIG_CPU_ARM720T +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_arm720 +# endif +#endif + +#ifdef CONFIG_CPU_ARM740T +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_arm740 +# endif +#endif + +#ifdef CONFIG_CPU_ARM9TDMI +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_arm9tdmi +# endif +#endif + +#ifdef CONFIG_CPU_ARM920T +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_arm920 +# endif +#endif + +#ifdef CONFIG_CPU_ARM922T +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_arm922 +# endif +#endif + +#ifdef CONFIG_CPU_FA526 +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_fa526 +# endif +#endif + +#ifdef CONFIG_CPU_ARM925T +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_arm925 +# endif +#endif + +#ifdef CONFIG_CPU_ARM926T +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_arm926 +# endif +#endif + +#ifdef CONFIG_CPU_ARM940T +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_arm940 +# endif +#endif + +#ifdef CONFIG_CPU_ARM946E +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_arm946 +# endif +#endif + +#ifdef CONFIG_CPU_SA110 +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_sa110 +# endif +#endif + +#ifdef CONFIG_CPU_SA1100 +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_sa1100 +# endif +#endif + +#ifdef CONFIG_CPU_ARM1020 +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_arm1020 +# endif +#endif + +#ifdef CONFIG_CPU_ARM1020E +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_arm1020e +# endif +#endif + +#ifdef CONFIG_CPU_ARM1022 +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_arm1022 +# endif +#endif + +#ifdef CONFIG_CPU_ARM1026 +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_arm1026 +# endif +#endif + +#ifdef CONFIG_CPU_XSCALE +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_xscale +# endif +#endif + +#ifdef CONFIG_CPU_XSC3 +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_xsc3 +# endif +#endif + +#ifdef CONFIG_CPU_MOHAWK +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_mohawk +# endif +#endif + +#ifdef CONFIG_CPU_FEROCEON +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_feroceon +# endif +#endif + +#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_v6 +# endif +#endif + +#ifdef CONFIG_CPU_V7 +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_v7 +# endif +#endif + +#ifndef MULTI_CPU +#define cpu_proc_init __glue(CPU_NAME,_proc_init) +#define cpu_proc_fin __glue(CPU_NAME,_proc_fin) +#define cpu_reset __glue(CPU_NAME,_reset) +#define cpu_do_idle __glue(CPU_NAME,_do_idle) +#define cpu_dcache_clean_area __glue(CPU_NAME,_dcache_clean_area) +#define cpu_do_switch_mm __glue(CPU_NAME,_switch_mm) +#define cpu_set_pte_ext __glue(CPU_NAME,_set_pte_ext) +#define cpu_suspend_size __glue(CPU_NAME,_suspend_size) +#define cpu_do_suspend __glue(CPU_NAME,_do_suspend) +#define cpu_do_resume __glue(CPU_NAME,_do_resume) +#endif + +#endif diff --git a/arch/arm/include/asm/glue.h b/arch/arm/include/asm/glue.h index 234a3fc1c78e..0ec35d1698aa 100644 --- a/arch/arm/include/asm/glue.h +++ b/arch/arm/include/asm/glue.h @@ -15,7 +15,6 @@ */ #ifdef __KERNEL__ - #ifdef __STDC__ #define ____glue(name,fn) name##fn #else @@ -23,141 +22,4 @@ #endif #define __glue(name,fn) ____glue(name,fn) - - -/* - * Data Abort Model - * ================ - * - * We have the following to choose from: - * arm6 - ARM6 style - * arm7 - ARM7 style - * v4_early - ARMv4 without Thumb early abort handler - * v4t_late - ARMv4 with Thumb late abort handler - * v4t_early - ARMv4 with Thumb early abort handler - * v5tej_early - ARMv5 with Thumb and Java early abort handler - * xscale - ARMv5 with Thumb with Xscale extensions - * v6_early - ARMv6 generic early abort handler - * v7_early - ARMv7 generic early abort handler - */ -#undef CPU_DABORT_HANDLER -#undef MULTI_DABORT - -#if defined(CONFIG_CPU_ARM610) -# ifdef CPU_DABORT_HANDLER -# define MULTI_DABORT 1 -# else -# define CPU_DABORT_HANDLER cpu_arm6_data_abort -# endif -#endif - -#if defined(CONFIG_CPU_ARM710) -# ifdef CPU_DABORT_HANDLER -# define MULTI_DABORT 1 -# else -# define CPU_DABORT_HANDLER cpu_arm7_data_abort -# endif -#endif - -#ifdef CONFIG_CPU_ABRT_LV4T -# ifdef CPU_DABORT_HANDLER -# define MULTI_DABORT 1 -# else -# define CPU_DABORT_HANDLER v4t_late_abort -# endif -#endif - -#ifdef CONFIG_CPU_ABRT_EV4 -# ifdef CPU_DABORT_HANDLER -# define MULTI_DABORT 1 -# else -# define CPU_DABORT_HANDLER v4_early_abort -# endif -#endif - -#ifdef CONFIG_CPU_ABRT_EV4T -# ifdef CPU_DABORT_HANDLER -# define MULTI_DABORT 1 -# else -# define CPU_DABORT_HANDLER v4t_early_abort -# endif -#endif - -#ifdef CONFIG_CPU_ABRT_EV5TJ -# ifdef CPU_DABORT_HANDLER -# define MULTI_DABORT 1 -# else -# define CPU_DABORT_HANDLER v5tj_early_abort -# endif -#endif - -#ifdef CONFIG_CPU_ABRT_EV5T -# ifdef CPU_DABORT_HANDLER -# define MULTI_DABORT 1 -# else -# define CPU_DABORT_HANDLER v5t_early_abort -# endif -#endif - -#ifdef CONFIG_CPU_ABRT_EV6 -# ifdef CPU_DABORT_HANDLER -# define MULTI_DABORT 1 -# else -# define CPU_DABORT_HANDLER v6_early_abort -# endif -#endif - -#ifdef CONFIG_CPU_ABRT_EV7 -# ifdef CPU_DABORT_HANDLER -# define MULTI_DABORT 1 -# else -# define CPU_DABORT_HANDLER v7_early_abort -# endif -#endif - -#ifndef CPU_DABORT_HANDLER -#error Unknown data abort handler type -#endif - -/* - * Prefetch Abort Model - * ================ - * - * We have the following to choose from: - * legacy - no IFSR, no IFAR - * v6 - ARMv6: IFSR, no IFAR - * v7 - ARMv7: IFSR and IFAR - */ - -#undef CPU_PABORT_HANDLER -#undef MULTI_PABORT - -#ifdef CONFIG_CPU_PABRT_LEGACY -# ifdef CPU_PABORT_HANDLER -# define MULTI_PABORT 1 -# else -# define CPU_PABORT_HANDLER legacy_pabort -# endif -#endif - -#ifdef CONFIG_CPU_PABRT_V6 -# ifdef CPU_PABORT_HANDLER -# define MULTI_PABORT 1 -# else -# define CPU_PABORT_HANDLER v6_pabort -# endif -#endif - -#ifdef CONFIG_CPU_PABRT_V7 -# ifdef CPU_PABORT_HANDLER -# define MULTI_PABORT 1 -# else -# define CPU_PABORT_HANDLER v7_pabort -# endif -#endif - -#ifndef CPU_PABORT_HANDLER -#error Unknown prefetch abort handler type -#endif - #endif diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h index 84557d321001..0691f9dcc500 100644 --- a/arch/arm/include/asm/hardware/gic.h +++ b/arch/arm/include/asm/hardware/gic.h @@ -34,6 +34,7 @@ #ifndef __ASSEMBLY__ extern void __iomem *gic_cpu_base_addr; +extern struct irq_chip gic_arch_extn; void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *); void gic_secondary_init(unsigned int); diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h index 7080e2c8fa62..a4edd19dd3d6 100644 --- a/arch/arm/include/asm/highmem.h +++ b/arch/arm/include/asm/highmem.h @@ -19,11 +19,36 @@ extern pte_t *pkmap_page_table; +extern void *kmap_high(struct page *page); +extern void kunmap_high(struct page *page); + +/* + * The reason for kmap_high_get() is to ensure that the currently kmap'd + * page usage count does not decrease to zero while we're using its + * existing virtual mapping in an atomic context. With a VIVT cache this + * is essential to do, but with a VIPT cache this is only an optimization + * so not to pay the price of establishing a second mapping if an existing + * one can be used. However, on platforms without hardware TLB maintenance + * broadcast, we simply cannot use ARCH_NEEDS_KMAP_HIGH_GET at all since + * the locking involved must also disable IRQs which is incompatible with + * the IPI mechanism used by global TLB operations. + */ #define ARCH_NEEDS_KMAP_HIGH_GET +#if defined(CONFIG_SMP) && defined(CONFIG_CPU_TLB_V6) +#undef ARCH_NEEDS_KMAP_HIGH_GET +#if defined(CONFIG_HIGHMEM) && defined(CONFIG_CPU_CACHE_VIVT) +#error "The sum of features in your kernel config cannot be supported together" +#endif +#endif -extern void *kmap_high(struct page *page); +#ifdef ARCH_NEEDS_KMAP_HIGH_GET extern void *kmap_high_get(struct page *page); -extern void kunmap_high(struct page *page); +#else +static inline void *kmap_high_get(struct page *page) +{ + return NULL; +} +#endif /* * The following functions are already defined by <linux/highmem.h> diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h index 22ac140edd9e..febe495d0c6e 100644 --- a/arch/arm/include/asm/mach/irq.h +++ b/arch/arm/include/asm/mach/irq.h @@ -34,4 +34,35 @@ do { \ raw_spin_unlock(&desc->lock); \ } while(0) +#ifndef __ASSEMBLY__ +/* + * Entry/exit functions for chained handlers where the primary IRQ chip + * may implement either fasteoi or level-trigger flow control. + */ +static inline void chained_irq_enter(struct irq_chip *chip, + struct irq_desc *desc) +{ + /* FastEOI controllers require no action on entry. */ + if (chip->irq_eoi) + return; + + if (chip->irq_mask_ack) { + chip->irq_mask_ack(&desc->irq_data); + } else { + chip->irq_mask(&desc->irq_data); + if (chip->irq_ack) + chip->irq_ack(&desc->irq_data); + } +} + +static inline void chained_irq_exit(struct irq_chip *chip, + struct irq_desc *desc) +{ + if (chip->irq_eoi) + chip->irq_eoi(&desc->irq_data); + else + chip->irq_unmask(&desc->irq_data); +} +#endif + #endif diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index d0ee74b7cf86..431077c5a867 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -15,6 +15,7 @@ #include <linux/compiler.h> #include <linux/const.h> +#include <linux/types.h> #include <mach/memory.h> #include <asm/sizes.h> @@ -133,20 +134,10 @@ #endif /* - * Physical vs virtual RAM address space conversion. These are - * private definitions which should NOT be used outside memory.h - * files. Use virt_to_phys/phys_to_virt/__pa/__va instead. - */ -#ifndef __virt_to_phys -#define __virt_to_phys(x) ((x) - PAGE_OFFSET + PHYS_OFFSET) -#define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET) -#endif - -/* * Convert a physical address to a Page Frame Number and back */ -#define __phys_to_pfn(paddr) ((paddr) >> PAGE_SHIFT) -#define __pfn_to_phys(pfn) ((pfn) << PAGE_SHIFT) +#define __phys_to_pfn(paddr) ((unsigned long)((paddr) >> PAGE_SHIFT)) +#define __pfn_to_phys(pfn) ((phys_addr_t)(pfn) << PAGE_SHIFT) /* * Convert a page to/from a physical address @@ -157,6 +148,62 @@ #ifndef __ASSEMBLY__ /* + * Physical vs virtual RAM address space conversion. These are + * private definitions which should NOT be used outside memory.h + * files. Use virt_to_phys/phys_to_virt/__pa/__va instead. + */ +#ifndef __virt_to_phys +#ifdef CONFIG_ARM_PATCH_PHYS_VIRT + +/* + * Constants used to force the right instruction encodings and shifts + * so that all we need to do is modify the 8-bit constant field. + */ +#define __PV_BITS_31_24 0x81000000 +#define __PV_BITS_23_16 0x00810000 + +extern unsigned long __pv_phys_offset; +#define PHYS_OFFSET __pv_phys_offset + +#define __pv_stub(from,to,instr,type) \ + __asm__("@ __pv_stub\n" \ + "1: " instr " %0, %1, %2\n" \ + " .pushsection .pv_table,\"a\"\n" \ + " .long 1b\n" \ + " .popsection\n" \ + : "=r" (to) \ + : "r" (from), "I" (type)) + +static inline unsigned long __virt_to_phys(unsigned long x) +{ + unsigned long t; + __pv_stub(x, t, "add", __PV_BITS_31_24); +#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT + __pv_stub(t, t, "add", __PV_BITS_23_16); +#endif + return t; +} + +static inline unsigned long __phys_to_virt(unsigned long x) +{ + unsigned long t; + __pv_stub(x, t, "sub", __PV_BITS_31_24); +#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT + __pv_stub(t, t, "sub", __PV_BITS_23_16); +#endif + return t; +} +#else +#define __virt_to_phys(x) ((x) - PAGE_OFFSET + PHYS_OFFSET) +#define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET) +#endif +#endif + +#ifndef PHYS_OFFSET +#define PHYS_OFFSET PLAT_PHYS_OFFSET +#endif + +/* * The DMA mask corresponding to the maximum bus address allocatable * using GFP_DMA. The default here places no restriction on DMA * allocations. This must be the smallest DMA mask in the system, @@ -188,12 +235,12 @@ * translation for translating DMA addresses. Use the driver * DMA support - see dma-mapping.h. */ -static inline unsigned long virt_to_phys(const volatile void *x) +static inline phys_addr_t virt_to_phys(const volatile void *x) { return __virt_to_phys((unsigned long)(x)); } -static inline void *phys_to_virt(unsigned long x) +static inline void *phys_to_virt(phys_addr_t x) { return (void *)(__phys_to_virt((unsigned long)(x))); } diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h index 12c8e680cbff..543b44916d2c 100644 --- a/arch/arm/include/asm/module.h +++ b/arch/arm/include/asm/module.h @@ -25,8 +25,31 @@ struct mod_arch_specific { }; /* - * Include the ARM architecture version. + * Add the ARM architecture version to the version magic string */ -#define MODULE_ARCH_VERMAGIC "ARMv" __stringify(__LINUX_ARM_ARCH__) " " +#define MODULE_ARCH_VERMAGIC_ARMVSN "ARMv" __stringify(__LINUX_ARM_ARCH__) " " + +/* Add __virt_to_phys patching state as well */ +#ifdef CONFIG_ARM_PATCH_PHYS_VIRT +#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT +#define MODULE_ARCH_VERMAGIC_P2V "p2v16 " +#else +#define MODULE_ARCH_VERMAGIC_P2V "p2v8 " +#endif +#else +#define MODULE_ARCH_VERMAGIC_P2V "" +#endif + +/* Add instruction set architecture tag to distinguish ARM/Thumb kernels */ +#ifdef CONFIG_THUMB2_KERNEL +#define MODULE_ARCH_VERMAGIC_ARMTHUMB "thumb2 " +#else +#define MODULE_ARCH_VERMAGIC_ARMTHUMB "" +#endif + +#define MODULE_ARCH_VERMAGIC \ + MODULE_ARCH_VERMAGIC_ARMVSN \ + MODULE_ARCH_VERMAGIC_ARMTHUMB \ + MODULE_ARCH_VERMAGIC_P2V #endif /* _ASM_ARM_MODULE_H */ diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h index fc1900925275..348d513afa92 100644 --- a/arch/arm/include/asm/outercache.h +++ b/arch/arm/include/asm/outercache.h @@ -31,6 +31,7 @@ struct outer_cache_fns { #ifdef CONFIG_OUTER_CACHE_SYNC void (*sync)(void); #endif + void (*set_debug)(unsigned long); }; #ifdef CONFIG_OUTER_CACHE diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h index 8fdae9bc9abb..8ec535e11fd7 100644 --- a/arch/arm/include/asm/proc-fns.h +++ b/arch/arm/include/asm/proc-fns.h @@ -13,250 +13,86 @@ #ifdef __KERNEL__ +#include <asm/glue-proc.h> +#include <asm/page.h> -/* - * Work out if we need multiple CPU support - */ -#undef MULTI_CPU -#undef CPU_NAME +#ifndef __ASSEMBLY__ + +struct mm_struct; /* - * CPU_NAME - the prefix for CPU related functions + * Don't change this structure - ASM code relies on it. */ - -#ifdef CONFIG_CPU_ARM610 -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_arm6 -# endif -#endif - -#ifdef CONFIG_CPU_ARM7TDMI -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_arm7tdmi -# endif -#endif - -#ifdef CONFIG_CPU_ARM710 -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_arm7 -# endif -#endif - -#ifdef CONFIG_CPU_ARM720T -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_arm720 -# endif -#endif - -#ifdef CONFIG_CPU_ARM740T -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_arm740 -# endif -#endif - -#ifdef CONFIG_CPU_ARM9TDMI -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_arm9tdmi -# endif -#endif - -#ifdef CONFIG_CPU_ARM920T -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_arm920 -# endif -#endif - -#ifdef CONFIG_CPU_ARM922T -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_arm922 -# endif -#endif - -#ifdef CONFIG_CPU_FA526 -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_fa526 -# endif -#endif - -#ifdef CONFIG_CPU_ARM925T -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_arm925 -# endif -#endif - -#ifdef CONFIG_CPU_ARM926T -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_arm926 -# endif -#endif - -#ifdef CONFIG_CPU_ARM940T -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_arm940 -# endif -#endif - -#ifdef CONFIG_CPU_ARM946E -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_arm946 -# endif -#endif - -#ifdef CONFIG_CPU_SA110 -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_sa110 -# endif -#endif - -#ifdef CONFIG_CPU_SA1100 -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_sa1100 -# endif -#endif - -#ifdef CONFIG_CPU_ARM1020 -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_arm1020 -# endif -#endif - -#ifdef CONFIG_CPU_ARM1020E -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_arm1020e -# endif -#endif - -#ifdef CONFIG_CPU_ARM1022 -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_arm1022 -# endif -#endif - -#ifdef CONFIG_CPU_ARM1026 -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_arm1026 -# endif -#endif - -#ifdef CONFIG_CPU_XSCALE -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_xscale -# endif -#endif - -#ifdef CONFIG_CPU_XSC3 -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_xsc3 -# endif -#endif - -#ifdef CONFIG_CPU_MOHAWK -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_mohawk -# endif -#endif - -#ifdef CONFIG_CPU_FEROCEON -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_feroceon -# endif -#endif - -#ifdef CONFIG_CPU_V6 -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_v6 -# endif -#endif - -#ifdef CONFIG_CPU_V7 -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_v7 -# endif -#endif - -#ifndef __ASSEMBLY__ +extern struct processor { + /* MISC + * get data abort address/flags + */ + void (*_data_abort)(unsigned long pc); + /* + * Retrieve prefetch fault address + */ + unsigned long (*_prefetch_abort)(unsigned long lr); + /* + * Set up any processor specifics + */ + void (*_proc_init)(void); + /* + * Disable any processor specifics + */ + void (*_proc_fin)(void); + /* + * Special stuff for a reset + */ + void (*reset)(unsigned long addr) __attribute__((noreturn)); + /* + * Idle the processor + */ + int (*_do_idle)(void); + /* + * Processor architecture specific + */ + /* + * clean a virtual address range from the + * D-cache without flushing the cache. + */ + void (*dcache_clean_area)(void *addr, int size); + + /* + * Set the page table + */ + void (*switch_mm)(unsigned long pgd_phys, struct mm_struct *mm); + /* + * Set a possibly extended PTE. Non-extended PTEs should + * ignore 'ext'. + */ + void (*set_pte_ext)(pte_t *ptep, pte_t pte, unsigned int ext); + + /* Suspend/resume */ + unsigned int suspend_size; + void (*do_suspend)(void *); + void (*do_resume)(void *); +} processor; #ifndef MULTI_CPU -#include <asm/cpu-single.h> +extern void cpu_proc_init(void); +extern void cpu_proc_fin(void); +extern int cpu_do_idle(void); +extern void cpu_dcache_clean_area(void *, int); +extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm); +extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext); +extern void cpu_reset(unsigned long addr) __attribute__((noreturn)); #else -#include <asm/cpu-multi32.h> +#define cpu_proc_init() processor._proc_init() +#define cpu_proc_fin() processor._proc_fin() +#define cpu_reset(addr) processor.reset(addr) +#define cpu_do_idle() processor._do_idle() +#define cpu_dcache_clean_area(addr,sz) processor.dcache_clean_area(addr,sz) +#define cpu_set_pte_ext(ptep,pte,ext) processor.set_pte_ext(ptep,pte,ext) +#define cpu_do_switch_mm(pgd,mm) processor.switch_mm(pgd,mm) #endif +extern void cpu_resume(void); + #include <asm/memory.h> #ifdef CONFIG_MMU diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h index 67357baaeeeb..b2d9df5667af 100644 --- a/arch/arm/include/asm/processor.h +++ b/arch/arm/include/asm/processor.h @@ -29,19 +29,7 @@ #define STACK_TOP_MAX TASK_SIZE #endif -union debug_insn { - u32 arm; - u16 thumb; -}; - -struct debug_entry { - u32 address; - union debug_insn insn; -}; - struct debug_info { - int nsaved; - struct debug_entry bp[2]; #ifdef CONFIG_HAVE_HW_BREAKPOINT struct perf_event *hbp[ARM_MAX_HBP_SLOTS]; #endif @@ -95,7 +83,7 @@ extern void release_thread(struct task_struct *); unsigned long get_wchan(struct task_struct *p); -#if __LINUX_ARM_ARCH__ == 6 +#if __LINUX_ARM_ARCH__ == 6 || defined(CONFIG_ARM_ERRATA_754327) #define cpu_relax() smp_mb() #else #define cpu_relax() barrier() diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h index 783d50f32618..a8ff22b2a391 100644 --- a/arch/arm/include/asm/ptrace.h +++ b/arch/arm/include/asm/ptrace.h @@ -130,8 +130,6 @@ struct pt_regs { #ifdef __KERNEL__ -#define arch_has_single_step() (1) - #define user_mode(regs) \ (((regs)->ARM_cpsr & 0xf) == 0) diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h index f1e5a9bca249..da8b52ec49cf 100644 --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h @@ -192,11 +192,7 @@ static struct tagtable __tagtable_##fn __tag = { tag, fn } /* * Memory map description */ -#ifdef CONFIG_ARCH_LH7A40X -# define NR_BANKS 16 -#else -# define NR_BANKS 8 -#endif +#define NR_BANKS 8 struct membank { unsigned long start; diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h index 2376835015d6..4eb6d005ffaa 100644 --- a/arch/arm/include/asm/smp_scu.h +++ b/arch/arm/include/asm/smp_scu.h @@ -1,7 +1,14 @@ #ifndef __ASMARM_ARCH_SCU_H #define __ASMARM_ARCH_SCU_H +#define SCU_PM_NORMAL 0 +#define SCU_PM_DORMANT 2 +#define SCU_PM_POWEROFF 3 + +#ifndef __ASSEMBLER__ unsigned int scu_get_core_count(void __iomem *); void scu_enable(void __iomem *); +int scu_power_mode(void __iomem *, unsigned int); +#endif #endif diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h index 17eb355707dd..fdd3820edff8 100644 --- a/arch/arm/include/asm/spinlock.h +++ b/arch/arm/include/asm/spinlock.h @@ -5,17 +5,52 @@ #error SMP not supported on pre-ARMv6 CPUs #endif +/* + * sev and wfe are ARMv6K extensions. Uniprocessor ARMv6 may not have the K + * extensions, so when running on UP, we have to patch these instructions away. + */ +#define ALT_SMP(smp, up) \ + "9998: " smp "\n" \ + " .pushsection \".alt.smp.init\", \"a\"\n" \ + " .long 9998b\n" \ + " " up "\n" \ + " .popsection\n" + +#ifdef CONFIG_THUMB2_KERNEL +#define SEV ALT_SMP("sev.w", "nop.w") +/* + * For Thumb-2, special care is needed to ensure that the conditional WFE + * instruction really does assemble to exactly 4 bytes (as required by + * the SMP_ON_UP fixup code). By itself "wfene" might cause the + * assembler to insert a extra (16-bit) IT instruction, depending on the + * presence or absence of neighbouring conditional instructions. + * + * To avoid this unpredictableness, an approprite IT is inserted explicitly: + * the assembler won't change IT instructions which are explicitly present + * in the input. + */ +#define WFE(cond) ALT_SMP( \ + "it " cond "\n\t" \ + "wfe" cond ".n", \ + \ + "nop.w" \ +) +#else +#define SEV ALT_SMP("sev", "nop") +#define WFE(cond) ALT_SMP("wfe" cond, "nop") +#endif + static inline void dsb_sev(void) { #if __LINUX_ARM_ARCH__ >= 7 __asm__ __volatile__ ( "dsb\n" - "sev" + SEV ); -#elif defined(CONFIG_CPU_32v6K) +#else __asm__ __volatile__ ( "mcr p15, 0, %0, c7, c10, 4\n" - "sev" + SEV : : "r" (0) ); #endif @@ -46,9 +81,7 @@ static inline void arch_spin_lock(arch_spinlock_t *lock) __asm__ __volatile__( "1: ldrex %0, [%1]\n" " teq %0, #0\n" -#ifdef CONFIG_CPU_32v6K -" wfene\n" -#endif + WFE("ne") " strexeq %0, %2, [%1]\n" " teqeq %0, #0\n" " bne 1b" @@ -107,9 +140,7 @@ static inline void arch_write_lock(arch_rwlock_t *rw) __asm__ __volatile__( "1: ldrex %0, [%1]\n" " teq %0, #0\n" -#ifdef CONFIG_CPU_32v6K -" wfene\n" -#endif + WFE("ne") " strexeq %0, %2, [%1]\n" " teq %0, #0\n" " bne 1b" @@ -176,9 +207,7 @@ static inline void arch_read_lock(arch_rwlock_t *rw) "1: ldrex %0, [%2]\n" " adds %0, %0, #1\n" " strexpl %1, %0, [%2]\n" -#ifdef CONFIG_CPU_32v6K -" wfemi\n" -#endif + WFE("mi") " rsbpls %0, %1, #0\n" " bmi 1b" : "=&r" (tmp), "=&r" (tmp2) diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 97f6d60297d5..9a87823642d0 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -347,6 +347,7 @@ void cpu_idle_wait(void); #include <asm-generic/cmpxchg-local.h> #if __LINUX_ARM_ARCH__ < 6 +/* min ARCH < ARMv6 */ #ifdef CONFIG_SMP #error "SMP is not supported on this platform" @@ -365,7 +366,7 @@ void cpu_idle_wait(void); #include <asm-generic/cmpxchg.h> #endif -#else /* __LINUX_ARM_ARCH__ >= 6 */ +#else /* min ARCH >= ARMv6 */ extern void __bad_cmpxchg(volatile void *ptr, int size); @@ -379,7 +380,7 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, unsigned long oldval, res; switch (size) { -#ifdef CONFIG_CPU_32v6K +#ifndef CONFIG_CPU_V6 /* min ARCH >= ARMv6K */ case 1: do { asm volatile("@ __cmpxchg1\n" @@ -404,7 +405,7 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, : "memory", "cc"); } while (res); break; -#endif /* CONFIG_CPU_32v6K */ +#endif case 4: do { asm volatile("@ __cmpxchg4\n" @@ -450,12 +451,12 @@ static inline unsigned long __cmpxchg_local(volatile void *ptr, unsigned long ret; switch (size) { -#ifndef CONFIG_CPU_32v6K +#ifdef CONFIG_CPU_V6 /* min ARCH == ARMv6 */ case 1: case 2: ret = __cmpxchg_local_generic(ptr, old, new, size); break; -#endif /* !CONFIG_CPU_32v6K */ +#endif default: ret = __cmpxchg(ptr, old, new, size); } @@ -469,7 +470,7 @@ static inline unsigned long __cmpxchg_local(volatile void *ptr, (unsigned long)(n), \ sizeof(*(ptr)))) -#ifdef CONFIG_CPU_32v6K +#ifndef CONFIG_CPU_V6 /* min ARCH >= ARMv6K */ /* * Note : ARMv7-M (currently unsupported by Linux) does not support @@ -524,11 +525,11 @@ static inline unsigned long long __cmpxchg64_mb(volatile void *ptr, (unsigned long long)(o), \ (unsigned long long)(n))) -#else /* !CONFIG_CPU_32v6K */ +#else /* min ARCH = ARMv6 */ #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) -#endif /* CONFIG_CPU_32v6K */ +#endif #endif /* __LINUX_ARM_ARCH__ >= 6 */ diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h index e71d6ff8d104..60843eb0f61c 100644 --- a/arch/arm/include/asm/tls.h +++ b/arch/arm/include/asm/tls.h @@ -28,15 +28,14 @@ #define tls_emu 1 #define has_tls_reg 1 #define set_tls set_tls_none -#elif __LINUX_ARM_ARCH__ >= 7 || \ - (__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K)) -#define tls_emu 0 -#define has_tls_reg 1 -#define set_tls set_tls_v6k -#elif __LINUX_ARM_ARCH__ == 6 +#elif defined(CONFIG_CPU_V6) #define tls_emu 0 #define has_tls_reg (elf_hwcap & HWCAP_TLS) #define set_tls set_tls_v6 +#elif defined(CONFIG_CPU_32v6K) +#define tls_emu 0 +#define has_tls_reg 1 +#define set_tls set_tls_v6k #else #define tls_emu 0 #define has_tls_reg 0 diff --git a/arch/arm/include/asm/traps.h b/arch/arm/include/asm/traps.h index 1b960d5ef6a5..f90756dc16dc 100644 --- a/arch/arm/include/asm/traps.h +++ b/arch/arm/include/asm/traps.h @@ -45,6 +45,7 @@ static inline int in_exception_text(unsigned long ptr) extern void __init early_trap_init(void); extern void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame); +extern void ptrace_break(struct task_struct *tsk, struct pt_regs *regs); extern void *vectors_page; diff --git a/arch/arm/include/asm/user.h b/arch/arm/include/asm/user.h index 05ac4b06876a..35917b3a97f9 100644 --- a/arch/arm/include/asm/user.h +++ b/arch/arm/include/asm/user.h @@ -71,7 +71,7 @@ struct user{ /* the registers. */ unsigned long magic; /* To uniquely identify a core file */ char u_comm[32]; /* User command that was responsible */ - int u_debugreg[8]; + int u_debugreg[8]; /* No longer used */ struct user_fp u_fp; /* FP state */ struct user_fp_struct * u_fp0;/* Used by gdb to help find the values for */ /* the FP registers. */ diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 185ee822c935..74554f1742d7 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_MODULES) += armksyms.o module.o obj-$(CONFIG_ARTHUR) += arthur.o obj-$(CONFIG_ISA_DMA) += dma-isa.o obj-$(CONFIG_PCI) += bios32.o isa.o +obj-$(CONFIG_PM) += sleep.o obj-$(CONFIG_HAVE_SCHED_CLOCK) += sched_clock.o obj-$(CONFIG_SMP) += smp.o smp_tlb.o obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c index e5e1e5387678..acca35aebe28 100644 --- a/arch/arm/kernel/armksyms.c +++ b/arch/arm/kernel/armksyms.c @@ -140,24 +140,18 @@ EXPORT_SYMBOL(__aeabi_ulcmp); #endif /* bitops */ -EXPORT_SYMBOL(_set_bit_le); -EXPORT_SYMBOL(_test_and_set_bit_le); -EXPORT_SYMBOL(_clear_bit_le); -EXPORT_SYMBOL(_test_and_clear_bit_le); -EXPORT_SYMBOL(_change_bit_le); -EXPORT_SYMBOL(_test_and_change_bit_le); +EXPORT_SYMBOL(_set_bit); +EXPORT_SYMBOL(_test_and_set_bit); +EXPORT_SYMBOL(_clear_bit); +EXPORT_SYMBOL(_test_and_clear_bit); +EXPORT_SYMBOL(_change_bit); +EXPORT_SYMBOL(_test_and_change_bit); EXPORT_SYMBOL(_find_first_zero_bit_le); EXPORT_SYMBOL(_find_next_zero_bit_le); EXPORT_SYMBOL(_find_first_bit_le); EXPORT_SYMBOL(_find_next_bit_le); #ifdef __ARMEB__ -EXPORT_SYMBOL(_set_bit_be); -EXPORT_SYMBOL(_test_and_set_bit_be); -EXPORT_SYMBOL(_clear_bit_be); -EXPORT_SYMBOL(_test_and_clear_bit_be); -EXPORT_SYMBOL(_change_bit_be); -EXPORT_SYMBOL(_test_and_change_bit_be); EXPORT_SYMBOL(_find_first_zero_bit_be); EXPORT_SYMBOL(_find_next_zero_bit_be); EXPORT_SYMBOL(_find_first_bit_be); @@ -170,3 +164,7 @@ EXPORT_SYMBOL(mcount); #endif EXPORT_SYMBOL(__gnu_mcount_nc); #endif + +#ifdef CONFIG_ARM_PATCH_PHYS_VIRT +EXPORT_SYMBOL(__pv_phys_offset); +#endif diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c index 82da66172132..927522cfc12e 100644 --- a/arch/arm/kernel/asm-offsets.c +++ b/arch/arm/kernel/asm-offsets.c @@ -13,6 +13,9 @@ #include <linux/sched.h> #include <linux/mm.h> #include <linux/dma-mapping.h> +#include <asm/cacheflush.h> +#include <asm/glue-df.h> +#include <asm/glue-pf.h> #include <asm/mach/arch.h> #include <asm/thread_info.h> #include <asm/memory.h> @@ -114,6 +117,14 @@ int main(void) #ifdef MULTI_PABORT DEFINE(PROCESSOR_PABT_FUNC, offsetof(struct processor, _prefetch_abort)); #endif +#ifdef MULTI_CPU + DEFINE(CPU_SLEEP_SIZE, offsetof(struct processor, suspend_size)); + DEFINE(CPU_DO_SUSPEND, offsetof(struct processor, do_suspend)); + DEFINE(CPU_DO_RESUME, offsetof(struct processor, do_resume)); +#endif +#ifdef MULTI_CACHE + DEFINE(CACHE_FLUSH_KERN_ALL, offsetof(struct cpu_cache_fns, flush_kern_all)); +#endif BLANK(); DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL); DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE); diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index c6273a3bfc25..d86fcd44b220 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -583,6 +583,11 @@ void __init pci_common_init(struct hw_pci *hw) * Assign resources. */ pci_bus_assign_resources(bus); + + /* + * Enable bridges + */ + pci_enable_bridges(bus); } /* diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S index a0f07521ca8a..d2d983be096d 100644 --- a/arch/arm/kernel/debug.S +++ b/arch/arm/kernel/debug.S @@ -25,7 +25,7 @@ .macro addruart, rp, rv .endm -#if defined(CONFIG_CPU_V6) +#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) .macro senduart, rd, rx mcr p14, 0, \rd, c0, c5, 0 diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 2b46fea36c9f..e8d885676807 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -16,7 +16,8 @@ */ #include <asm/memory.h> -#include <asm/glue.h> +#include <asm/glue-df.h> +#include <asm/glue-pf.h> #include <asm/vfpmacros.h> #include <mach/entry-macro.S> #include <asm/thread_notify.h> diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S index ae9464900168..051166c2a932 100644 --- a/arch/arm/kernel/entry-header.S +++ b/arch/arm/kernel/entry-header.S @@ -76,13 +76,13 @@ #ifndef CONFIG_THUMB2_KERNEL .macro svc_exit, rpsr msr spsr_cxsf, \rpsr -#if defined(CONFIG_CPU_32v6K) - clrex @ clear the exclusive monitor - ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr -#elif defined (CONFIG_CPU_V6) +#if defined(CONFIG_CPU_V6) ldr r0, [sp] strex r1, r2, [sp] @ clear the exclusive monitor ldmib sp, {r1 - pc}^ @ load r1 - pc, cpsr +#elif defined(CONFIG_CPU_32v6K) + clrex @ clear the exclusive monitor + ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr #else ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr #endif @@ -92,10 +92,10 @@ ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr ldr lr, [sp, #\offset + S_PC]! @ get pc msr spsr_cxsf, r1 @ save in spsr_svc -#if defined(CONFIG_CPU_32v6K) - clrex @ clear the exclusive monitor -#elif defined (CONFIG_CPU_V6) +#if defined(CONFIG_CPU_V6) strex r1, r2, [sp] @ clear the exclusive monitor +#elif defined(CONFIG_CPU_32v6K) + clrex @ clear the exclusive monitor #endif .if \fast ldmdb sp, {r1 - lr}^ @ get calling r1 - lr diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S index 8f57515bbdb0..c84b57d27d07 100644 --- a/arch/arm/kernel/head-common.S +++ b/arch/arm/kernel/head-common.S @@ -25,83 +25,6 @@ * machine ID for example). */ __HEAD -__error_a: -#ifdef CONFIG_DEBUG_LL - mov r4, r1 @ preserve machine ID - adr r0, str_a1 - bl printascii - mov r0, r4 - bl printhex8 - adr r0, str_a2 - bl printascii - adr r3, __lookup_machine_type_data - ldmia r3, {r4, r5, r6} @ get machine desc list - sub r4, r3, r4 @ get offset between virt&phys - add r5, r5, r4 @ convert virt addresses to - add r6, r6, r4 @ physical address space -1: ldr r0, [r5, #MACHINFO_TYPE] @ get machine type - bl printhex8 - mov r0, #'\t' - bl printch - ldr r0, [r5, #MACHINFO_NAME] @ get machine name - add r0, r0, r4 - bl printascii - mov r0, #'\n' - bl printch - add r5, r5, #SIZEOF_MACHINE_DESC @ next machine_desc - cmp r5, r6 - blo 1b - adr r0, str_a3 - bl printascii - b __error -ENDPROC(__error_a) - -str_a1: .asciz "\nError: unrecognized/unsupported machine ID (r1 = 0x" -str_a2: .asciz ").\n\nAvailable machine support:\n\nID (hex)\tNAME\n" -str_a3: .asciz "\nPlease check your kernel config and/or bootloader.\n" - .align -#else - b __error -#endif - -/* - * Lookup machine architecture in the linker-build list of architectures. - * Note that we can't use the absolute addresses for the __arch_info - * lists since we aren't running with the MMU on (and therefore, we are - * not in the correct address space). We have to calculate the offset. - * - * r1 = machine architecture number - * Returns: - * r3, r4, r6 corrupted - * r5 = mach_info pointer in physical address space - */ -__lookup_machine_type: - adr r3, __lookup_machine_type_data - ldmia r3, {r4, r5, r6} - sub r3, r3, r4 @ get offset between virt&phys - add r5, r5, r3 @ convert virt addresses to - add r6, r6, r3 @ physical address space -1: ldr r3, [r5, #MACHINFO_TYPE] @ get machine type - teq r3, r1 @ matches loader number? - beq 2f @ found - add r5, r5, #SIZEOF_MACHINE_DESC @ next machine_desc - cmp r5, r6 - blo 1b - mov r5, #0 @ unknown machine -2: mov pc, lr -ENDPROC(__lookup_machine_type) - -/* - * Look in arch/arm/kernel/arch.[ch] for information about the - * __arch_info structures. - */ - .align 2 - .type __lookup_machine_type_data, %object -__lookup_machine_type_data: - .long . - .long __arch_info_begin - .long __arch_info_end - .size __lookup_machine_type_data, . - __lookup_machine_type_data /* Determine validity of the r2 atags pointer. The heuristic requires * that the pointer be aligned, in the first 16k of physical RAM and @@ -109,8 +32,6 @@ __lookup_machine_type_data: * of this function may be more lenient with the physical address and * may also be able to move the ATAGS block if necessary. * - * r8 = machinfo - * * Returns: * r2 either valid atags pointer, or zero * r5, r6 corrupted @@ -185,17 +106,6 @@ __mmap_switched_data: .size __mmap_switched_data, . - __mmap_switched_data /* - * This provides a C-API version of __lookup_machine_type - */ -ENTRY(lookup_machine_type) - stmfd sp!, {r4 - r6, lr} - mov r1, r0 - bl __lookup_machine_type - mov r0, r5 - ldmfd sp!, {r4 - r6, pc} -ENDPROC(lookup_machine_type) - -/* * This provides a C-API version of __lookup_processor_type */ ENTRY(lookup_processor_type) diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S index 814ce1a73270..6b1e0ad9ec3b 100644 --- a/arch/arm/kernel/head-nommu.S +++ b/arch/arm/kernel/head-nommu.S @@ -44,9 +44,6 @@ ENTRY(stext) bl __lookup_processor_type @ r5=procinfo r9=cpuid movs r10, r5 @ invalid processor (r5=0)? beq __error_p @ yes, error 'p' - bl __lookup_machine_type @ r5=machinfo - movs r8, r5 @ invalid machine (r5=0)? - beq __error_a @ yes, error 'a' adr lr, BSYM(__after_proc_init) @ return (PIC) address ARM( add pc, r10, #PROCINFO_INITFUNC ) diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index f06ff9feb0db..c9173cfbbc74 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -26,14 +26,6 @@ #include <mach/debug-macro.S> #endif -#if (PHYS_OFFSET & 0x001fffff) -#error "PHYS_OFFSET must be at an even 2MiB boundary!" -#endif - -#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) -#define KERNEL_RAM_PADDR (PHYS_OFFSET + TEXT_OFFSET) - - /* * swapper_pg_dir is the virtual address of the initial page table. * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must @@ -41,6 +33,7 @@ * the least significant 16 bits to be 0x8000, but we could probably * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000. */ +#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000 #error KERNEL_RAM_VADDR must start at 0xXXXX8000 #endif @@ -48,8 +41,8 @@ .globl swapper_pg_dir .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000 - .macro pgtbl, rd - ldr \rd, =(KERNEL_RAM_PADDR - 0x4000) + .macro pgtbl, rd, phys + add \rd, \phys, #TEXT_OFFSET - 0x4000 .endm #ifdef CONFIG_XIP_KERNEL @@ -87,25 +80,33 @@ ENTRY(stext) movs r10, r5 @ invalid processor (r5=0)? THUMB( it eq ) @ force fixup-able long branch encoding beq __error_p @ yes, error 'p' - bl __lookup_machine_type @ r5=machinfo - movs r8, r5 @ invalid machine (r5=0)? - THUMB( it eq ) @ force fixup-able long branch encoding - beq __error_a @ yes, error 'a' + +#ifndef CONFIG_XIP_KERNEL + adr r3, 2f + ldmia r3, {r4, r8} + sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET) + add r8, r8, r4 @ PHYS_OFFSET +#else + ldr r8, =PLAT_PHYS_OFFSET +#endif /* * r1 = machine no, r2 = atags, - * r8 = machinfo, r9 = cpuid, r10 = procinfo + * r8 = phys_offset, r9 = cpuid, r10 = procinfo */ bl __vet_atags #ifdef CONFIG_SMP_ON_UP bl __fixup_smp #endif +#ifdef CONFIG_ARM_PATCH_PHYS_VIRT + bl __fixup_pv_table +#endif bl __create_page_tables /* * The following calls CPU specific code in a position independent * manner. See arch/arm/mm/proc-*.S for details. r10 = base of - * xxx_proc_info structure selected by __lookup_machine_type + * xxx_proc_info structure selected by __lookup_processor_type * above. On return, the CPU will be ready for the MMU to be * turned on, and r0 will hold the CPU control register value. */ @@ -118,22 +119,24 @@ ENTRY(stext) 1: b __enable_mmu ENDPROC(stext) .ltorg +#ifndef CONFIG_XIP_KERNEL +2: .long . + .long PAGE_OFFSET +#endif /* * Setup the initial page tables. We only setup the barest * amount which are required to get the kernel running, which * generally means mapping in the kernel code. * - * r8 = machinfo - * r9 = cpuid - * r10 = procinfo + * r8 = phys_offset, r9 = cpuid, r10 = procinfo * * Returns: * r0, r3, r5-r7 corrupted * r4 = physical page table address */ __create_page_tables: - pgtbl r4 @ page table address + pgtbl r4, r8 @ page table address /* * Clear the 16K level 1 swapper page table @@ -189,10 +192,8 @@ __create_page_tables: /* * Map some ram to cover our .data and .bss areas. */ - orr r3, r7, #(KERNEL_RAM_PADDR & 0xff000000) - .if (KERNEL_RAM_PADDR & 0x00f00000) - orr r3, r3, #(KERNEL_RAM_PADDR & 0x00f00000) - .endif + add r3, r8, #TEXT_OFFSET + orr r3, r3, r7 add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> 18 str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]! ldr r6, =(_end - 1) @@ -205,14 +206,17 @@ __create_page_tables: #endif /* - * Then map first 1MB of ram in case it contains our boot params. + * Then map boot params address in r2 or + * the first 1MB of ram if boot params address is not specified. */ - add r0, r4, #PAGE_OFFSET >> 18 - orr r6, r7, #(PHYS_OFFSET & 0xff000000) - .if (PHYS_OFFSET & 0x00f00000) - orr r6, r6, #(PHYS_OFFSET & 0x00f00000) - .endif - str r6, [r0] + mov r0, r2, lsr #20 + movs r0, r0, lsl #20 + moveq r0, r8 + sub r3, r0, r8 + add r3, r3, #PAGE_OFFSET + add r3, r4, r3, lsr #18 + orr r6, r7, r0 + str r6, [r3] #ifdef CONFIG_DEBUG_LL #ifndef CONFIG_DEBUG_ICEDCC @@ -457,4 +461,129 @@ ENTRY(fixup_smp) ldmfd sp!, {r4 - r6, pc} ENDPROC(fixup_smp) +#ifdef CONFIG_ARM_PATCH_PHYS_VIRT + +/* __fixup_pv_table - patch the stub instructions with the delta between + * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and + * can be expressed by an immediate shifter operand. The stub instruction + * has a form of '(add|sub) rd, rn, #imm'. + */ + __HEAD +__fixup_pv_table: + adr r0, 1f + ldmia r0, {r3-r5, r7} + sub r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET + add r4, r4, r3 @ adjust table start address + add r5, r5, r3 @ adjust table end address + add r7, r7, r3 @ adjust __pv_phys_offset address + str r8, [r7] @ save computed PHYS_OFFSET to __pv_phys_offset +#ifndef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT + mov r6, r3, lsr #24 @ constant for add/sub instructions + teq r3, r6, lsl #24 @ must be 16MiB aligned +#else + mov r6, r3, lsr #16 @ constant for add/sub instructions + teq r3, r6, lsl #16 @ must be 64kiB aligned +#endif +THUMB( it ne @ cross section branch ) + bne __error + str r6, [r7, #4] @ save to __pv_offset + b __fixup_a_pv_table +ENDPROC(__fixup_pv_table) + + .align +1: .long . + .long __pv_table_begin + .long __pv_table_end +2: .long __pv_phys_offset + + .text +__fixup_a_pv_table: +#ifdef CONFIG_THUMB2_KERNEL +#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT + lsls r0, r6, #24 + lsr r6, #8 + beq 1f + clz r7, r0 + lsr r0, #24 + lsl r0, r7 + bic r0, 0x0080 + lsrs r7, #1 + orrcs r0, #0x0080 + orr r0, r0, r7, lsl #12 +#endif +1: lsls r6, #24 + beq 4f + clz r7, r6 + lsr r6, #24 + lsl r6, r7 + bic r6, #0x0080 + lsrs r7, #1 + orrcs r6, #0x0080 + orr r6, r6, r7, lsl #12 + orr r6, #0x4000 + b 4f +2: @ at this point the C flag is always clear + add r7, r3 +#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT + ldrh ip, [r7] + tst ip, 0x0400 @ the i bit tells us LS or MS byte + beq 3f + cmp r0, #0 @ set C flag, and ... + biceq ip, 0x0400 @ immediate zero value has a special encoding + streqh ip, [r7] @ that requires the i bit cleared +#endif +3: ldrh ip, [r7, #2] + and ip, 0x8f00 + orrcc ip, r6 @ mask in offset bits 31-24 + orrcs ip, r0 @ mask in offset bits 23-16 + strh ip, [r7, #2] +4: cmp r4, r5 + ldrcc r7, [r4], #4 @ use branch for delay slot + bcc 2b + bx lr +#else +#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT + and r0, r6, #255 @ offset bits 23-16 + mov r6, r6, lsr #8 @ offset bits 31-24 +#else + mov r0, #0 @ just in case... +#endif + b 3f +2: ldr ip, [r7, r3] + bic ip, ip, #0x000000ff + tst ip, #0x400 @ rotate shift tells us LS or MS byte + orrne ip, ip, r6 @ mask in offset bits 31-24 + orreq ip, ip, r0 @ mask in offset bits 23-16 + str ip, [r7, r3] +3: cmp r4, r5 + ldrcc r7, [r4], #4 @ use branch for delay slot + bcc 2b + mov pc, lr +#endif +ENDPROC(__fixup_a_pv_table) + +ENTRY(fixup_pv_table) + stmfd sp!, {r4 - r7, lr} + ldr r2, 2f @ get address of __pv_phys_offset + mov r3, #0 @ no offset + mov r4, r0 @ r0 = table start + add r5, r0, r1 @ r1 = table size + ldr r6, [r2, #4] @ get __pv_offset + bl __fixup_a_pv_table + ldmfd sp!, {r4 - r7, pc} +ENDPROC(fixup_pv_table) + + .align +2: .long __pv_phys_offset + + .data + .globl __pv_phys_offset + .type __pv_phys_offset, %object +__pv_phys_offset: + .long 0 + .size __pv_phys_offset, . - __pv_phys_offset +__pv_offset: + .long 0 +#endif + #include "head-common.S" diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 28536e352deb..3535d3793e65 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -179,14 +179,21 @@ int __init arch_probe_nr_irqs(void) #ifdef CONFIG_HOTPLUG_CPU -static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu) +static bool migrate_one_irq(struct irq_data *d) { - pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->irq_data.node, cpu); + unsigned int cpu = cpumask_any_and(d->affinity, cpu_online_mask); + bool ret = false; - raw_spin_lock_irq(&desc->lock); - desc->irq_data.chip->irq_set_affinity(&desc->irq_data, - cpumask_of(cpu), false); - raw_spin_unlock_irq(&desc->lock); + if (cpu >= nr_cpu_ids) { + cpu = cpumask_any(cpu_online_mask); + ret = true; + } + + pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", d->irq, d->node, cpu); + + d->chip->irq_set_affinity(d, cpumask_of(cpu), true); + + return ret; } /* @@ -198,25 +205,30 @@ void migrate_irqs(void) { unsigned int i, cpu = smp_processor_id(); struct irq_desc *desc; + unsigned long flags; + + local_irq_save(flags); for_each_irq_desc(i, desc) { struct irq_data *d = &desc->irq_data; + bool affinity_broken = false; - if (d->node == cpu) { - unsigned int newcpu = cpumask_any_and(d->affinity, - cpu_online_mask); - if (newcpu >= nr_cpu_ids) { - if (printk_ratelimit()) - printk(KERN_INFO "IRQ%u no longer affine to CPU%u\n", - i, cpu); + raw_spin_lock(&desc->lock); + do { + if (desc->action == NULL) + break; - cpumask_setall(d->affinity); - newcpu = cpumask_any_and(d->affinity, - cpu_online_mask); - } + if (d->node != cpu) + break; - route_irq(desc, i, newcpu); - } + affinity_broken = migrate_one_irq(d); + } while (0); + raw_spin_unlock(&desc->lock); + + if (affinity_broken && printk_ratelimit()) + pr_warning("IRQ%u no longer affine to CPU%u\n", i, cpu); } + + local_irq_restore(flags); } #endif /* CONFIG_HOTPLUG_CPU */ diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index 6d4105e6872f..fee7c36349eb 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c @@ -76,6 +76,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, for (i = 0; i < relsec->sh_size / sizeof(Elf32_Rel); i++, rel++) { unsigned long loc; Elf32_Sym *sym; + const char *symname; s32 offset; #ifdef CONFIG_THUMB2_KERNEL u32 upper, lower, sign, j1, j2; @@ -83,18 +84,18 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, offset = ELF32_R_SYM(rel->r_info); if (offset < 0 || offset > (symsec->sh_size / sizeof(Elf32_Sym))) { - printk(KERN_ERR "%s: bad relocation, section %d reloc %d\n", + pr_err("%s: section %u reloc %u: bad relocation sym offset\n", module->name, relindex, i); return -ENOEXEC; } sym = ((Elf32_Sym *)symsec->sh_addr) + offset; + symname = strtab + sym->st_name; if (rel->r_offset < 0 || rel->r_offset > dstsec->sh_size - sizeof(u32)) { - printk(KERN_ERR "%s: out of bounds relocation, " - "section %d reloc %d offset %d size %d\n", - module->name, relindex, i, rel->r_offset, - dstsec->sh_size); + pr_err("%s: section %u reloc %u sym '%s': out of bounds relocation, offset %d size %u\n", + module->name, relindex, i, symname, + rel->r_offset, dstsec->sh_size); return -ENOEXEC; } @@ -120,10 +121,10 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, if (offset & 3 || offset <= (s32)0xfe000000 || offset >= (s32)0x02000000) { - printk(KERN_ERR - "%s: relocation out of range, section " - "%d reloc %d sym '%s'\n", module->name, - relindex, i, strtab + sym->st_name); + pr_err("%s: section %u reloc %u sym '%s': relocation %u out of range (%#lx -> %#x)\n", + module->name, relindex, i, symname, + ELF32_R_TYPE(rel->r_info), loc, + sym->st_value); return -ENOEXEC; } @@ -196,10 +197,10 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, if (!(offset & 1) || offset <= (s32)0xff000000 || offset >= (s32)0x01000000) { - printk(KERN_ERR - "%s: relocation out of range, section " - "%d reloc %d sym '%s'\n", module->name, - relindex, i, strtab + sym->st_name); + pr_err("%s: section %u reloc %u sym '%s': relocation %u out of range (%#lx -> %#x)\n", + module->name, relindex, i, symname, + ELF32_R_TYPE(rel->r_info), loc, + sym->st_value); return -ENOEXEC; } @@ -282,12 +283,13 @@ static const Elf_Shdr *find_mod_section(const Elf32_Ehdr *hdr, return NULL; } +extern void fixup_pv_table(const void *, unsigned long); extern void fixup_smp(const void *, unsigned long); int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs, struct module *mod) { - const Elf_Shdr * __maybe_unused s = NULL; + const Elf_Shdr *s = NULL; #ifdef CONFIG_ARM_UNWIND const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset; const Elf_Shdr *sechdrs_end = sechdrs + hdr->e_shnum; @@ -332,6 +334,11 @@ int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs, maps[i].txt_sec->sh_addr, maps[i].txt_sec->sh_size); #endif +#ifdef CONFIG_ARM_PATCH_PHYS_VIRT + s = find_mod_section(hdr, sechdrs, ".pv_table"); + if (s) + fixup_pv_table((void *)s->sh_addr, s->sh_size); +#endif s = find_mod_section(hdr, sechdrs, ".alt.smp.init"); if (s && !is_smp()) fixup_smp((void *)s->sh_addr, s->sh_size); diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c index c058bfc8532b..6fc2d228db55 100644 --- a/arch/arm/kernel/perf_event_v6.c +++ b/arch/arm/kernel/perf_event_v6.c @@ -30,7 +30,7 @@ * enable the interrupt. */ -#ifdef CONFIG_CPU_V6 +#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) enum armv6_perf_types { ARMV6_PERFCTR_ICACHE_MISS = 0x0, ARMV6_PERFCTR_IBUF_STALL = 0x1, @@ -669,4 +669,4 @@ static const struct arm_pmu *__init armv6mpcore_pmu_init(void) { return NULL; } -#endif /* CONFIG_CPU_V6 */ +#endif /* CONFIG_CPU_V6 || CONFIG_CPU_V6K */ diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index b13e70f63d71..2bf27f364d09 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c @@ -26,8 +26,6 @@ #include <asm/system.h> #include <asm/traps.h> -#include "ptrace.h" - #define REG_PC 15 #define REG_PSR 16 /* @@ -184,389 +182,12 @@ put_user_reg(struct task_struct *task, int offset, long data) return ret; } -static inline int -read_u32(struct task_struct *task, unsigned long addr, u32 *res) -{ - int ret; - - ret = access_process_vm(task, addr, res, sizeof(*res), 0); - - return ret == sizeof(*res) ? 0 : -EIO; -} - -static inline int -read_instr(struct task_struct *task, unsigned long addr, u32 *res) -{ - int ret; - - if (addr & 1) { - u16 val; - ret = access_process_vm(task, addr & ~1, &val, sizeof(val), 0); - ret = ret == sizeof(val) ? 0 : -EIO; - *res = val; - } else { - u32 val; - ret = access_process_vm(task, addr & ~3, &val, sizeof(val), 0); - ret = ret == sizeof(val) ? 0 : -EIO; - *res = val; - } - return ret; -} - -/* - * Get value of register `rn' (in the instruction) - */ -static unsigned long -ptrace_getrn(struct task_struct *child, unsigned long insn) -{ - unsigned int reg = (insn >> 16) & 15; - unsigned long val; - - val = get_user_reg(child, reg); - if (reg == 15) - val += 8; - - return val; -} - -/* - * Get value of operand 2 (in an ALU instruction) - */ -static unsigned long -ptrace_getaluop2(struct task_struct *child, unsigned long insn) -{ - unsigned long val; - int shift; - int type; - - if (insn & 1 << 25) { - val = insn & 255; - shift = (insn >> 8) & 15; - type = 3; - } else { - val = get_user_reg (child, insn & 15); - - if (insn & (1 << 4)) - shift = (int)get_user_reg (child, (insn >> 8) & 15); - else - shift = (insn >> 7) & 31; - - type = (insn >> 5) & 3; - } - - switch (type) { - case 0: val <<= shift; break; - case 1: val >>= shift; break; - case 2: - val = (((signed long)val) >> shift); - break; - case 3: - val = (val >> shift) | (val << (32 - shift)); - break; - } - return val; -} - -/* - * Get value of operand 2 (in a LDR instruction) - */ -static unsigned long -ptrace_getldrop2(struct task_struct *child, unsigned long insn) -{ - unsigned long val; - int shift; - int type; - - val = get_user_reg(child, insn & 15); - shift = (insn >> 7) & 31; - type = (insn >> 5) & 3; - - switch (type) { - case 0: val <<= shift; break; - case 1: val >>= shift; break; - case 2: - val = (((signed long)val) >> shift); - break; - case 3: - val = (val >> shift) | (val << (32 - shift)); - break; - } - return val; -} - -#define OP_MASK 0x01e00000 -#define OP_AND 0x00000000 -#define OP_EOR 0x00200000 -#define OP_SUB 0x00400000 -#define OP_RSB 0x00600000 -#define OP_ADD 0x00800000 -#define OP_ADC 0x00a00000 -#define OP_SBC 0x00c00000 -#define OP_RSC 0x00e00000 -#define OP_ORR 0x01800000 -#define OP_MOV 0x01a00000 -#define OP_BIC 0x01c00000 -#define OP_MVN 0x01e00000 - -static unsigned long -get_branch_address(struct task_struct *child, unsigned long pc, unsigned long insn) -{ - u32 alt = 0; - - switch (insn & 0x0e000000) { - case 0x00000000: - case 0x02000000: { - /* - * data processing - */ - long aluop1, aluop2, ccbit; - - if ((insn & 0x0fffffd0) == 0x012fff10) { - /* - * bx or blx - */ - alt = get_user_reg(child, insn & 15); - break; - } - - - if ((insn & 0xf000) != 0xf000) - break; - - aluop1 = ptrace_getrn(child, insn); - aluop2 = ptrace_getaluop2(child, insn); - ccbit = get_user_reg(child, REG_PSR) & PSR_C_BIT ? 1 : 0; - - switch (insn & OP_MASK) { - case OP_AND: alt = aluop1 & aluop2; break; - case OP_EOR: alt = aluop1 ^ aluop2; break; - case OP_SUB: alt = aluop1 - aluop2; break; - case OP_RSB: alt = aluop2 - aluop1; break; - case OP_ADD: alt = aluop1 + aluop2; break; - case OP_ADC: alt = aluop1 + aluop2 + ccbit; break; - case OP_SBC: alt = aluop1 - aluop2 + ccbit; break; - case OP_RSC: alt = aluop2 - aluop1 + ccbit; break; - case OP_ORR: alt = aluop1 | aluop2; break; - case OP_MOV: alt = aluop2; break; - case OP_BIC: alt = aluop1 & ~aluop2; break; - case OP_MVN: alt = ~aluop2; break; - } - break; - } - - case 0x04000000: - case 0x06000000: - /* - * ldr - */ - if ((insn & 0x0010f000) == 0x0010f000) { - unsigned long base; - - base = ptrace_getrn(child, insn); - if (insn & 1 << 24) { - long aluop2; - - if (insn & 0x02000000) - aluop2 = ptrace_getldrop2(child, insn); - else - aluop2 = insn & 0xfff; - - if (insn & 1 << 23) - base += aluop2; - else - base -= aluop2; - } - read_u32(child, base, &alt); - } - break; - - case 0x08000000: - /* - * ldm - */ - if ((insn & 0x00108000) == 0x00108000) { - unsigned long base; - unsigned int nr_regs; - - if (insn & (1 << 23)) { - nr_regs = hweight16(insn & 65535) << 2; - - if (!(insn & (1 << 24))) - nr_regs -= 4; - } else { - if (insn & (1 << 24)) - nr_regs = -4; - else - nr_regs = 0; - } - - base = ptrace_getrn(child, insn); - - read_u32(child, base + nr_regs, &alt); - break; - } - break; - - case 0x0a000000: { - /* - * bl or b - */ - signed long displ; - /* It's a branch/branch link: instead of trying to - * figure out whether the branch will be taken or not, - * we'll put a breakpoint at both locations. This is - * simpler, more reliable, and probably not a whole lot - * slower than the alternative approach of emulating the - * branch. - */ - displ = (insn & 0x00ffffff) << 8; - displ = (displ >> 6) + 8; - if (displ != 0 && displ != 4) - alt = pc + displ; - } - break; - } - - return alt; -} - -static int -swap_insn(struct task_struct *task, unsigned long addr, - void *old_insn, void *new_insn, int size) -{ - int ret; - - ret = access_process_vm(task, addr, old_insn, size, 0); - if (ret == size) - ret = access_process_vm(task, addr, new_insn, size, 1); - return ret; -} - -static void -add_breakpoint(struct task_struct *task, struct debug_info *dbg, unsigned long addr) -{ - int nr = dbg->nsaved; - - if (nr < 2) { - u32 new_insn = BREAKINST_ARM; - int res; - - res = swap_insn(task, addr, &dbg->bp[nr].insn, &new_insn, 4); - - if (res == 4) { - dbg->bp[nr].address = addr; - dbg->nsaved += 1; - } - } else - printk(KERN_ERR "ptrace: too many breakpoints\n"); -} - -/* - * Clear one breakpoint in the user program. We copy what the hardware - * does and use bit 0 of the address to indicate whether this is a Thumb - * breakpoint or an ARM breakpoint. - */ -static void clear_breakpoint(struct task_struct *task, struct debug_entry *bp) -{ - unsigned long addr = bp->address; - union debug_insn old_insn; - int ret; - - if (addr & 1) { - ret = swap_insn(task, addr & ~1, &old_insn.thumb, - &bp->insn.thumb, 2); - - if (ret != 2 || old_insn.thumb != BREAKINST_THUMB) - printk(KERN_ERR "%s:%d: corrupted Thumb breakpoint at " - "0x%08lx (0x%04x)\n", task->comm, - task_pid_nr(task), addr, old_insn.thumb); - } else { - ret = swap_insn(task, addr & ~3, &old_insn.arm, - &bp->insn.arm, 4); - - if (ret != 4 || old_insn.arm != BREAKINST_ARM) - printk(KERN_ERR "%s:%d: corrupted ARM breakpoint at " - "0x%08lx (0x%08x)\n", task->comm, - task_pid_nr(task), addr, old_insn.arm); - } -} - -void ptrace_set_bpt(struct task_struct *child) -{ - struct pt_regs *regs; - unsigned long pc; - u32 insn; - int res; - - regs = task_pt_regs(child); - pc = instruction_pointer(regs); - - if (thumb_mode(regs)) { - printk(KERN_WARNING "ptrace: can't handle thumb mode\n"); - return; - } - - res = read_instr(child, pc, &insn); - if (!res) { - struct debug_info *dbg = &child->thread.debug; - unsigned long alt; - - dbg->nsaved = 0; - - alt = get_branch_address(child, pc, insn); - if (alt) - add_breakpoint(child, dbg, alt); - - /* - * Note that we ignore the result of setting the above - * breakpoint since it may fail. When it does, this is - * not so much an error, but a forewarning that we may - * be receiving a prefetch abort shortly. - * - * If we don't set this breakpoint here, then we can - * lose control of the thread during single stepping. - */ - if (!alt || predicate(insn) != PREDICATE_ALWAYS) - add_breakpoint(child, dbg, pc + 4); - } -} - -/* - * Ensure no single-step breakpoint is pending. Returns non-zero - * value if child was being single-stepped. - */ -void ptrace_cancel_bpt(struct task_struct *child) -{ - int i, nsaved = child->thread.debug.nsaved; - - child->thread.debug.nsaved = 0; - - if (nsaved > 2) { - printk("ptrace_cancel_bpt: bogus nsaved: %d!\n", nsaved); - nsaved = 2; - } - - for (i = 0; i < nsaved; i++) - clear_breakpoint(child, &child->thread.debug.bp[i]); -} - -void user_disable_single_step(struct task_struct *task) -{ - task->ptrace &= ~PT_SINGLESTEP; - ptrace_cancel_bpt(task); -} - -void user_enable_single_step(struct task_struct *task) -{ - task->ptrace |= PT_SINGLESTEP; -} - /* * Called by kernel/ptrace.c when detaching.. */ void ptrace_disable(struct task_struct *child) { - user_disable_single_step(child); + /* Nothing to do. */ } /* @@ -576,8 +197,6 @@ void ptrace_break(struct task_struct *tsk, struct pt_regs *regs) { siginfo_t info; - ptrace_cancel_bpt(tsk); - info.si_signo = SIGTRAP; info.si_errno = 0; info.si_code = TRAP_BRKPT; diff --git a/arch/arm/kernel/ptrace.h b/arch/arm/kernel/ptrace.h deleted file mode 100644 index 3926605b82ea..000000000000 --- a/arch/arm/kernel/ptrace.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * linux/arch/arm/kernel/ptrace.h - * - * Copyright (C) 2000-2003 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/ptrace.h> - -extern void ptrace_cancel_bpt(struct task_struct *); -extern void ptrace_set_bpt(struct task_struct *); -extern void ptrace_break(struct task_struct *, struct pt_regs *); - -/* - * Send SIGTRAP if we're single-stepping - */ -static inline void single_step_trap(struct task_struct *task) -{ - if (task->ptrace & PT_SINGLESTEP) { - ptrace_cancel_bpt(task); - send_sig(SIGTRAP, task, 1); - } -} - -static inline void single_step_clear(struct task_struct *task) -{ - if (task->ptrace & PT_SINGLESTEP) - ptrace_cancel_bpt(task); -} - -static inline void single_step_set(struct task_struct *task) -{ - if (task->ptrace & PT_SINGLESTEP) - ptrace_set_bpt(task); -} diff --git a/arch/arm/kernel/return_address.c b/arch/arm/kernel/return_address.c index df246da4ceca..0b13a72f855d 100644 --- a/arch/arm/kernel/return_address.c +++ b/arch/arm/kernel/return_address.c @@ -9,6 +9,7 @@ * the Free Software Foundation. */ #include <linux/module.h> +#include <linux/ftrace.h> #if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND) #include <linux/sched.h> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 5ea4fb718b97..d1da92174277 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -308,7 +308,22 @@ static void __init cacheid_init(void) * already provide the required functionality. */ extern struct proc_info_list *lookup_processor_type(unsigned int); -extern struct machine_desc *lookup_machine_type(unsigned int); + +static void __init early_print(const char *str, ...) +{ + extern void printascii(const char *); + char buf[256]; + va_list ap; + + va_start(ap, str); + vsnprintf(buf, sizeof(buf), str, ap); + va_end(ap); + +#ifdef CONFIG_DEBUG_LL + printascii(buf); +#endif + printk("%s", buf); +} static void __init feat_v6_fixup(void) { @@ -426,21 +441,29 @@ void cpu_init(void) static struct machine_desc * __init setup_machine(unsigned int nr) { - struct machine_desc *list; + extern struct machine_desc __arch_info_begin[], __arch_info_end[]; + struct machine_desc *p; /* * locate machine in the list of supported machines. */ - list = lookup_machine_type(nr); - if (!list) { - printk("Machine configuration botched (nr %d), unable " - "to continue.\n", nr); - while (1); - } + for (p = __arch_info_begin; p < __arch_info_end; p++) + if (nr == p->nr) { + printk("Machine: %s\n", p->name); + return p; + } - printk("Machine: %s\n", list->name); + early_print("\n" + "Error: unrecognized/unsupported machine ID (r1 = 0x%08x).\n\n" + "Available machine support:\n\nID (hex)\tNAME\n", nr); - return list; + for (p = __arch_info_begin; p < __arch_info_end; p++) + early_print("%08x\t%s\n", p->nr, p->name); + + early_print("\nPlease check your kernel config and/or bootloader.\n"); + + while (true) + /* can't use cpu_relax() here as it may require MMU setup */; } static int __init arm_add_memory(unsigned long start, unsigned long size) @@ -703,7 +726,7 @@ static struct init_tags { { tag_size(tag_core), ATAG_CORE }, { 1, PAGE_SIZE, 0xff }, { tag_size(tag_mem32), ATAG_MEM }, - { MEM_SIZE, PHYS_OFFSET }, + { MEM_SIZE }, { 0, ATAG_NONE } }; @@ -802,6 +825,8 @@ void __init setup_arch(char **cmdline_p) struct machine_desc *mdesc; char *from = default_command_line; + init_tags.mem.start = PHYS_OFFSET; + unwind_init(); setup_processor(); @@ -814,8 +839,25 @@ void __init setup_arch(char **cmdline_p) if (__atags_pointer) tags = phys_to_virt(__atags_pointer); - else if (mdesc->boot_params) - tags = phys_to_virt(mdesc->boot_params); + else if (mdesc->boot_params) { +#ifdef CONFIG_MMU + /* + * We still are executing with a minimal MMU mapping created + * with the presumption that the machine default for this + * is located in the first MB of RAM. Anything else will + * fault and silently hang the kernel at this point. + */ + if (mdesc->boot_params < PHYS_OFFSET || + mdesc->boot_params >= PHYS_OFFSET + SZ_1M) { + printk(KERN_WARNING + "Default boot params at physical 0x%08lx out of reach\n", + mdesc->boot_params); + } else +#endif + { + tags = phys_to_virt(mdesc->boot_params); + } + } #if defined(CONFIG_DEPRECATED_PARAM_STRUCT) /* diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index abaf8445ce25..cb8398317644 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -20,7 +20,6 @@ #include <asm/unistd.h> #include <asm/vfp.h> -#include "ptrace.h" #include "signal.h" #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) @@ -348,8 +347,6 @@ asmlinkage int sys_sigreturn(struct pt_regs *regs) if (restore_sigframe(regs, frame)) goto badframe; - single_step_trap(current); - return regs->ARM_r0; badframe: @@ -383,8 +380,6 @@ asmlinkage int sys_rt_sigreturn(struct pt_regs *regs) if (do_sigaltstack(&frame->sig.uc.uc_stack, NULL, regs->ARM_sp) == -EFAULT) goto badframe; - single_step_trap(current); - return regs->ARM_r0; badframe: @@ -706,8 +701,6 @@ static void do_signal(struct pt_regs *regs, int syscall) if (try_to_freeze()) goto no_signal; - single_step_clear(current); - signr = get_signal_to_deliver(&info, &ka, regs, NULL); if (signr > 0) { sigset_t *oldset; @@ -726,7 +719,6 @@ static void do_signal(struct pt_regs *regs, int syscall) if (test_thread_flag(TIF_RESTORE_SIGMASK)) clear_thread_flag(TIF_RESTORE_SIGMASK); } - single_step_set(current); return; } @@ -772,7 +764,6 @@ static void do_signal(struct pt_regs *regs, int syscall) sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL); } } - single_step_set(current); } asmlinkage void diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S new file mode 100644 index 000000000000..bfad698a02e7 --- /dev/null +++ b/arch/arm/kernel/sleep.S @@ -0,0 +1,134 @@ +#include <linux/linkage.h> +#include <linux/threads.h> +#include <asm/asm-offsets.h> +#include <asm/assembler.h> +#include <asm/glue-cache.h> +#include <asm/glue-proc.h> +#include <asm/system.h> + .text + +/* + * Save CPU state for a suspend + * r1 = v:p offset + * r3 = virtual return function + * Note: sp is decremented to allocate space for CPU state on stack + * r0-r3,r9,r10,lr corrupted + */ +ENTRY(cpu_suspend) + mov r9, lr +#ifdef MULTI_CPU + ldr r10, =processor + mov r2, sp @ current virtual SP + ldr r0, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state + ldr ip, [r10, #CPU_DO_RESUME] @ virtual resume function + sub sp, sp, r0 @ allocate CPU state on stack + mov r0, sp @ save pointer + add ip, ip, r1 @ convert resume fn to phys + stmfd sp!, {r1, r2, r3, ip} @ save v:p, virt SP, retfn, phys resume fn + ldr r3, =sleep_save_sp + add r2, sp, r1 @ convert SP to phys +#ifdef CONFIG_SMP + ALT_SMP(mrc p15, 0, lr, c0, c0, 5) + ALT_UP(mov lr, #0) + and lr, lr, #15 + str r2, [r3, lr, lsl #2] @ save phys SP +#else + str r2, [r3] @ save phys SP +#endif + mov lr, pc + ldr pc, [r10, #CPU_DO_SUSPEND] @ save CPU state +#else + mov r2, sp @ current virtual SP + ldr r0, =cpu_suspend_size + sub sp, sp, r0 @ allocate CPU state on stack + mov r0, sp @ save pointer + stmfd sp!, {r1, r2, r3} @ save v:p, virt SP, return fn + ldr r3, =sleep_save_sp + add r2, sp, r1 @ convert SP to phys +#ifdef CONFIG_SMP + ALT_SMP(mrc p15, 0, lr, c0, c0, 5) + ALT_UP(mov lr, #0) + and lr, lr, #15 + str r2, [r3, lr, lsl #2] @ save phys SP +#else + str r2, [r3] @ save phys SP +#endif + bl cpu_do_suspend +#endif + + @ flush data cache +#ifdef MULTI_CACHE + ldr r10, =cpu_cache + mov lr, r9 + ldr pc, [r10, #CACHE_FLUSH_KERN_ALL] +#else + mov lr, r9 + b __cpuc_flush_kern_all +#endif +ENDPROC(cpu_suspend) + .ltorg + +/* + * r0 = control register value + * r1 = v:p offset (preserved by cpu_do_resume) + * r2 = phys page table base + * r3 = L1 section flags + */ +ENTRY(cpu_resume_mmu) + adr r4, cpu_resume_turn_mmu_on + mov r4, r4, lsr #20 + orr r3, r3, r4, lsl #20 + ldr r5, [r2, r4, lsl #2] @ save old mapping + str r3, [r2, r4, lsl #2] @ setup 1:1 mapping for mmu code + sub r2, r2, r1 + ldr r3, =cpu_resume_after_mmu + bic r1, r0, #CR_C @ ensure D-cache is disabled + b cpu_resume_turn_mmu_on +ENDPROC(cpu_resume_mmu) + .ltorg + .align 5 +cpu_resume_turn_mmu_on: + mcr p15, 0, r1, c1, c0, 0 @ turn on MMU, I-cache, etc + mrc p15, 0, r1, c0, c0, 0 @ read id reg + mov r1, r1 + mov r1, r1 + mov pc, r3 @ jump to virtual address +ENDPROC(cpu_resume_turn_mmu_on) +cpu_resume_after_mmu: + str r5, [r2, r4, lsl #2] @ restore old mapping + mcr p15, 0, r0, c1, c0, 0 @ turn on D-cache + mov pc, lr +ENDPROC(cpu_resume_after_mmu) + +/* + * Note: Yes, part of the following code is located into the .data section. + * This is to allow sleep_save_sp to be accessed with a relative load + * while we can't rely on any MMU translation. We could have put + * sleep_save_sp in the .text section as well, but some setups might + * insist on it to be truly read-only. + */ + .data + .align +ENTRY(cpu_resume) +#ifdef CONFIG_SMP + adr r0, sleep_save_sp + ALT_SMP(mrc p15, 0, r1, c0, c0, 5) + ALT_UP(mov r1, #0) + and r1, r1, #15 + ldr r0, [r0, r1, lsl #2] @ stack phys addr +#else + ldr r0, sleep_save_sp @ stack phys addr +#endif + msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE @ set SVC, irqs off +#ifdef MULTI_CPU + ldmia r0!, {r1, sp, lr, pc} @ load v:p, stack, return fn, resume fn +#else + ldmia r0!, {r1, sp, lr} @ load v:p, stack, return fn + b cpu_do_resume +#endif +ENDPROC(cpu_resume) + +sleep_save_sp: + .rept CONFIG_NR_CPUS + .long 0 @ preserve stack phys ptr here + .endr diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c index 9ab4149bd983..a1e757c3439b 100644 --- a/arch/arm/kernel/smp_scu.c +++ b/arch/arm/kernel/smp_scu.c @@ -50,3 +50,26 @@ void __init scu_enable(void __iomem *scu_base) */ flush_cache_all(); } + +/* + * Set the executing CPUs power mode as defined. This will be in + * preparation for it executing a WFI instruction. + * + * This function must be called with preemption disabled, and as it + * has the side effect of disabling coherency, caches must have been + * flushed. Interrupts must also have been disabled. + */ +int scu_power_mode(void __iomem *scu_base, unsigned int mode) +{ + unsigned int val; + int cpu = smp_processor_id(); + + if (mode > 3 || mode == 1 || cpu > 3) + return -EINVAL; + + val = __raw_readb(scu_base + SCU_CPU_STATUS + cpu) & ~0x03; + val |= mode; + __raw_writeb(val, scu_base + SCU_CPU_STATUS + cpu); + + return 0; +} diff --git a/arch/arm/kernel/tcm.c b/arch/arm/kernel/tcm.c index 26685c2f7a49..f5cf660eefcc 100644 --- a/arch/arm/kernel/tcm.c +++ b/arch/arm/kernel/tcm.c @@ -15,7 +15,7 @@ #include <linux/string.h> /* memcpy */ #include <asm/cputype.h> #include <asm/mach/map.h> -#include <mach/memory.h> +#include <asm/memory.h> #include "tcm.h" static struct gen_pool *tcm_pool; diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index 3d76bf233734..1ff46cabc7ef 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c @@ -107,9 +107,7 @@ void timer_tick(void) { profile_tick(CPU_PROFILING); do_leds(); - write_seqlock(&xtime_lock); - do_timer(1); - write_sequnlock(&xtime_lock); + xtime_update(1); #ifndef CONFIG_SMP update_process_times(user_mode(get_irq_regs())); #endif diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index ee57640ba2bb..21ac43f1c2d0 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -23,6 +23,7 @@ #include <linux/kexec.h> #include <linux/delay.h> #include <linux/init.h> +#include <linux/sched.h> #include <asm/atomic.h> #include <asm/cacheflush.h> @@ -32,7 +33,6 @@ #include <asm/unwind.h> #include <asm/tls.h> -#include "ptrace.h" #include "signal.h" static const char *handler[]= { "prefetch abort", "data abort", "address exception", "interrupt" }; @@ -256,7 +256,7 @@ static int __die(const char *str, int err, struct thread_info *thread, struct pt return ret; } -DEFINE_SPINLOCK(die_lock); +static DEFINE_SPINLOCK(die_lock); /* * This function is protected against re-entrancy. diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index 61462790757f..b4348e62ef06 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S @@ -64,6 +64,10 @@ SECTIONS __smpalt_end = .; #endif + __pv_table_begin = .; + *(.pv_table) + __pv_table_end = .; + INIT_SETUP(16) INIT_CALLS @@ -78,7 +82,7 @@ SECTIONS #endif } - PERCPU(PAGE_SIZE) + PERCPU(32, PAGE_SIZE) #ifndef CONFIG_XIP_KERNEL . = ALIGN(PAGE_SIZE); diff --git a/arch/arm/lib/bitops.h b/arch/arm/lib/bitops.h index d42252918bfb..10d868a5a481 100644 --- a/arch/arm/lib/bitops.h +++ b/arch/arm/lib/bitops.h @@ -1,44 +1,52 @@ - -#if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_CPU_32v6K) +#if __LINUX_ARM_ARCH__ >= 6 .macro bitop, instr + ands ip, r1, #3 + strneb r1, [ip] @ assert word-aligned mov r2, #1 - and r3, r0, #7 @ Get bit offset - add r1, r1, r0, lsr #3 @ Get byte offset + and r3, r0, #31 @ Get bit offset + mov r0, r0, lsr #5 + add r1, r1, r0, lsl #2 @ Get word offset mov r3, r2, lsl r3 -1: ldrexb r2, [r1] +1: ldrex r2, [r1] \instr r2, r2, r3 - strexb r0, r2, [r1] + strex r0, r2, [r1] cmp r0, #0 bne 1b - mov pc, lr + bx lr .endm .macro testop, instr, store - and r3, r0, #7 @ Get bit offset + ands ip, r1, #3 + strneb r1, [ip] @ assert word-aligned mov r2, #1 - add r1, r1, r0, lsr #3 @ Get byte offset + and r3, r0, #31 @ Get bit offset + mov r0, r0, lsr #5 + add r1, r1, r0, lsl #2 @ Get word offset mov r3, r2, lsl r3 @ create mask smp_dmb -1: ldrexb r2, [r1] +1: ldrex r2, [r1] ands r0, r2, r3 @ save old value of bit - \instr r2, r2, r3 @ toggle bit - strexb ip, r2, [r1] + \instr r2, r2, r3 @ toggle bit + strex ip, r2, [r1] cmp ip, #0 bne 1b smp_dmb cmp r0, #0 movne r0, #1 -2: mov pc, lr +2: bx lr .endm #else .macro bitop, instr - and r2, r0, #7 + ands ip, r1, #3 + strneb r1, [ip] @ assert word-aligned + and r2, r0, #31 + mov r0, r0, lsr #5 mov r3, #1 mov r3, r3, lsl r2 save_and_disable_irqs ip - ldrb r2, [r1, r0, lsr #3] + ldr r2, [r1, r0, lsl #2] \instr r2, r2, r3 - strb r2, [r1, r0, lsr #3] + str r2, [r1, r0, lsl #2] restore_irqs ip mov pc, lr .endm @@ -52,11 +60,13 @@ * to avoid dirtying the data cache. */ .macro testop, instr, store - add r1, r1, r0, lsr #3 - and r3, r0, #7 - mov r0, #1 + ands ip, r1, #3 + strneb r1, [ip] @ assert word-aligned + and r3, r0, #31 + mov r0, r0, lsr #5 save_and_disable_irqs ip - ldrb r2, [r1] + ldr r2, [r1, r0, lsl #2]! + mov r0, #1 tst r2, r0, lsl r3 \instr r2, r2, r0, lsl r3 \store r2, [r1] diff --git a/arch/arm/lib/changebit.S b/arch/arm/lib/changebit.S index 80f3115cbee2..68ed5b62e839 100644 --- a/arch/arm/lib/changebit.S +++ b/arch/arm/lib/changebit.S @@ -12,12 +12,6 @@ #include "bitops.h" .text -/* Purpose : Function to change a bit - * Prototype: int change_bit(int bit, void *addr) - */ -ENTRY(_change_bit_be) - eor r0, r0, #0x18 @ big endian byte ordering -ENTRY(_change_bit_le) +ENTRY(_change_bit) bitop eor -ENDPROC(_change_bit_be) -ENDPROC(_change_bit_le) +ENDPROC(_change_bit) diff --git a/arch/arm/lib/clearbit.S b/arch/arm/lib/clearbit.S index 1a63e43a1df0..4c04c3b51eeb 100644 --- a/arch/arm/lib/clearbit.S +++ b/arch/arm/lib/clearbit.S @@ -12,13 +12,6 @@ #include "bitops.h" .text -/* - * Purpose : Function to clear a bit - * Prototype: int clear_bit(int bit, void *addr) - */ -ENTRY(_clear_bit_be) - eor r0, r0, #0x18 @ big endian byte ordering -ENTRY(_clear_bit_le) +ENTRY(_clear_bit) bitop bic -ENDPROC(_clear_bit_be) -ENDPROC(_clear_bit_le) +ENDPROC(_clear_bit) diff --git a/arch/arm/lib/setbit.S b/arch/arm/lib/setbit.S index 1dd7176c4b2b..bbee5c66a23e 100644 --- a/arch/arm/lib/setbit.S +++ b/arch/arm/lib/setbit.S @@ -12,13 +12,6 @@ #include "bitops.h" .text -/* - * Purpose : Function to set a bit - * Prototype: int set_bit(int bit, void *addr) - */ -ENTRY(_set_bit_be) - eor r0, r0, #0x18 @ big endian byte ordering -ENTRY(_set_bit_le) +ENTRY(_set_bit) bitop orr -ENDPROC(_set_bit_be) -ENDPROC(_set_bit_le) +ENDPROC(_set_bit) diff --git a/arch/arm/lib/testchangebit.S b/arch/arm/lib/testchangebit.S index 5c98dc567f0f..15a4d431f229 100644 --- a/arch/arm/lib/testchangebit.S +++ b/arch/arm/lib/testchangebit.S @@ -12,9 +12,6 @@ #include "bitops.h" .text -ENTRY(_test_and_change_bit_be) - eor r0, r0, #0x18 @ big endian byte ordering -ENTRY(_test_and_change_bit_le) - testop eor, strb -ENDPROC(_test_and_change_bit_be) -ENDPROC(_test_and_change_bit_le) +ENTRY(_test_and_change_bit) + testop eor, str +ENDPROC(_test_and_change_bit) diff --git a/arch/arm/lib/testclearbit.S b/arch/arm/lib/testclearbit.S index 543d7094d18e..521b66b5b95d 100644 --- a/arch/arm/lib/testclearbit.S +++ b/arch/arm/lib/testclearbit.S @@ -12,9 +12,6 @@ #include "bitops.h" .text -ENTRY(_test_and_clear_bit_be) - eor r0, r0, #0x18 @ big endian byte ordering -ENTRY(_test_and_clear_bit_le) - testop bicne, strneb -ENDPROC(_test_and_clear_bit_be) -ENDPROC(_test_and_clear_bit_le) +ENTRY(_test_and_clear_bit) + testop bicne, strne +ENDPROC(_test_and_clear_bit) diff --git a/arch/arm/lib/testsetbit.S b/arch/arm/lib/testsetbit.S index 0b3f390401ce..1c98cc2185bb 100644 --- a/arch/arm/lib/testsetbit.S +++ b/arch/arm/lib/testsetbit.S @@ -12,9 +12,6 @@ #include "bitops.h" .text -ENTRY(_test_and_set_bit_be) - eor r0, r0, #0x18 @ big endian byte ordering -ENTRY(_test_and_set_bit_le) - testop orreq, streqb -ENDPROC(_test_and_set_bit_be) -ENDPROC(_test_and_set_bit_le) +ENTRY(_test_and_set_bit) + testop orreq, streq +ENDPROC(_test_and_set_bit) diff --git a/arch/arm/mach-aaec2000/Kconfig b/arch/arm/mach-aaec2000/Kconfig deleted file mode 100644 index 5e4bef93754c..000000000000 --- a/arch/arm/mach-aaec2000/Kconfig +++ /dev/null @@ -1,11 +0,0 @@ -if ARCH_AAEC2000 - -menu "Agilent AAEC-2000 Implementations" - -config MACH_AAED2000 - bool "Agilent AAED-2000 Development Platform" - select CPU_ARM920T - -endmenu - -endif diff --git a/arch/arm/mach-aaec2000/Makefile b/arch/arm/mach-aaec2000/Makefile deleted file mode 100644 index 20ec83896c37..000000000000 --- a/arch/arm/mach-aaec2000/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Makefile for the linux kernel. -# - -# Common support (must be linked before board specific support) -obj-y += core.o - -# Specific board support -obj-$(CONFIG_MACH_AAED2000) += aaed2000.o diff --git a/arch/arm/mach-aaec2000/Makefile.boot b/arch/arm/mach-aaec2000/Makefile.boot deleted file mode 100644 index 8f5a8b7c53c7..000000000000 --- a/arch/arm/mach-aaec2000/Makefile.boot +++ /dev/null @@ -1 +0,0 @@ - zreladdr-y := 0xf0008000 diff --git a/arch/arm/mach-aaec2000/aaed2000.c b/arch/arm/mach-aaec2000/aaed2000.c deleted file mode 100644 index 0eb3e3e5b2d1..000000000000 --- a/arch/arm/mach-aaec2000/aaed2000.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * linux/arch/arm/mach-aaec2000/aaed2000.c - * - * Support for the Agilent AAED-2000 Development Platform. - * - * Copyright (c) 2005 Nicolas Bellido Y Ortega - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/device.h> -#include <linux/major.h> -#include <linux/interrupt.h> - -#include <asm/setup.h> -#include <asm/memory.h> -#include <asm/mach-types.h> -#include <mach/hardware.h> -#include <asm/irq.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <mach/aaed2000.h> - -#include "core.h" - -static void aaed2000_clcd_disable(struct clcd_fb *fb) -{ - AAED_EXT_GPIO &= ~AAED_EGPIO_LCD_PWR_EN; -} - -static void aaed2000_clcd_enable(struct clcd_fb *fb) -{ - AAED_EXT_GPIO |= AAED_EGPIO_LCD_PWR_EN; -} - -struct aaec2000_clcd_info clcd_info = { - .enable = aaed2000_clcd_enable, - .disable = aaed2000_clcd_disable, - .panel = { - .mode = { - .name = "Sharp", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 39721, - .left_margin = 20, - .right_margin = 44, - .upper_margin = 21, - .lower_margin = 34, - .hsync_len = 96, - .vsync_len = 2, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, - }, - .width = -1, - .height = -1, - .tim2 = TIM2_IVS | TIM2_IHS, - .cntl = CNTL_LCDTFT, - .bpp = 16, - }, -}; - -static void __init aaed2000_init_irq(void) -{ - aaec2000_init_irq(); -} - -static void __init aaed2000_init(void) -{ - aaec2000_set_clcd_plat_data(&clcd_info); -} - -static struct map_desc aaed2000_io_desc[] __initdata = { - { - .virtual = EXT_GPIO_VBASE, - .pfn = __phys_to_pfn(EXT_GPIO_PBASE), - .length = EXT_GPIO_LENGTH, - .type = MT_DEVICE - }, -}; - -static void __init aaed2000_map_io(void) -{ - aaec2000_map_io(); - iotable_init(aaed2000_io_desc, ARRAY_SIZE(aaed2000_io_desc)); -} - -MACHINE_START(AAED2000, "Agilent AAED-2000 Development Platform") - /* Maintainer: Nicolas Bellido Y Ortega */ - .map_io = aaed2000_map_io, - .init_irq = aaed2000_init_irq, - .timer = &aaec2000_timer, - .init_machine = aaed2000_init, -MACHINE_END diff --git a/arch/arm/mach-aaec2000/core.c b/arch/arm/mach-aaec2000/core.c deleted file mode 100644 index f8465bd17e67..000000000000 --- a/arch/arm/mach-aaec2000/core.c +++ /dev/null @@ -1,298 +0,0 @@ -/* - * linux/arch/arm/mach-aaec2000/core.c - * - * Code common to all AAEC-2000 machines - * - * Copyright (c) 2005 Nicolas Bellido Y Ortega - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/dma-mapping.h> -#include <linux/interrupt.h> -#include <linux/timex.h> -#include <linux/signal.h> -#include <linux/clk.h> -#include <linux/gfp.h> - -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/sizes.h> - -#include <asm/mach/flash.h> -#include <asm/mach/irq.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> - -#include "core.h" - -/* - * Common I/O mapping: - * - * Static virtual address mappings are as follow: - * - * 0xf8000000-0xf8001ffff: Devices connected to APB bus - * 0xf8002000-0xf8003ffff: Devices connected to AHB bus - * - * Below 0xe8000000 is reserved for vm allocation. - * - * The machine specific code must provide the extra mapping beside the - * default mapping provided here. - */ -static struct map_desc standard_io_desc[] __initdata = { - { - .virtual = VIO_APB_BASE, - .pfn = __phys_to_pfn(PIO_APB_BASE), - .length = IO_APB_LENGTH, - .type = MT_DEVICE - }, { - .virtual = VIO_AHB_BASE, - .pfn = __phys_to_pfn(PIO_AHB_BASE), - .length = IO_AHB_LENGTH, - .type = MT_DEVICE - } -}; - -void __init aaec2000_map_io(void) -{ - iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); -} - -/* - * Interrupt handling routines - */ -static void aaec2000_int_ack(struct irq_data *d) -{ - IRQ_INTSR = 1 << d->irq; -} - -static void aaec2000_int_mask(struct irq_data *d) -{ - IRQ_INTENC |= (1 << d->irq); -} - -static void aaec2000_int_unmask(struct irq_data *d) -{ - IRQ_INTENS |= (1 << d->irq); -} - -static struct irq_chip aaec2000_irq_chip = { - .irq_ack = aaec2000_int_ack, - .irq_mask = aaec2000_int_mask, - .irq_unmask = aaec2000_int_unmask, -}; - -void __init aaec2000_init_irq(void) -{ - unsigned int i; - - for (i = 0; i < NR_IRQS; i++) { - set_irq_handler(i, handle_level_irq); - set_irq_chip(i, &aaec2000_irq_chip); - set_irq_flags(i, IRQF_VALID); - } - - /* Disable all interrupts */ - IRQ_INTENC = 0xffffffff; - - /* Clear any pending interrupts */ - IRQ_INTSR = IRQ_INTSR; -} - -/* - * Time keeping - */ -/* IRQs are disabled before entering here from do_gettimeofday() */ -static unsigned long aaec2000_gettimeoffset(void) -{ - unsigned long ticks_to_match, elapsed, usec; - - /* Get ticks before next timer match */ - ticks_to_match = TIMER1_LOAD - TIMER1_VAL; - - /* We need elapsed ticks since last match */ - elapsed = LATCH - ticks_to_match; - - /* Now, convert them to usec */ - usec = (unsigned long)(elapsed * (tick_nsec / 1000))/LATCH; - - return usec; -} - -/* We enter here with IRQs enabled */ -static irqreturn_t -aaec2000_timer_interrupt(int irq, void *dev_id) -{ - /* TODO: Check timer accuracy */ - timer_tick(); - TIMER1_CLEAR = 1; - - return IRQ_HANDLED; -} - -static struct irqaction aaec2000_timer_irq = { - .name = "AAEC-2000 Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = aaec2000_timer_interrupt, -}; - -static void __init aaec2000_timer_init(void) -{ - /* Disable timer 1 */ - TIMER1_CTRL = 0; - - /* We have somehow to generate a 100Hz clock. - * We then use the 508KHz timer in periodic mode. - */ - TIMER1_LOAD = LATCH; - TIMER1_CLEAR = 1; /* Clear interrupt */ - - setup_irq(INT_TMR1_OFL, &aaec2000_timer_irq); - - TIMER1_CTRL = TIMER_CTRL_ENABLE | - TIMER_CTRL_PERIODIC | - TIMER_CTRL_CLKSEL_508K; -} - -struct sys_timer aaec2000_timer = { - .init = aaec2000_timer_init, - .offset = aaec2000_gettimeoffset, -}; - -static struct clcd_panel mach_clcd_panel; - -static int aaec2000_clcd_setup(struct clcd_fb *fb) -{ - dma_addr_t dma; - - fb->panel = &mach_clcd_panel; - - fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, SZ_1M, - &dma, GFP_KERNEL); - - if (!fb->fb.screen_base) { - printk(KERN_ERR "CLCD: unable to map framebuffer\n"); - return -ENOMEM; - } - - fb->fb.fix.smem_start = dma; - fb->fb.fix.smem_len = SZ_1M; - - return 0; -} - -static int aaec2000_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) -{ - return dma_mmap_writecombine(&fb->dev->dev, vma, - fb->fb.screen_base, - fb->fb.fix.smem_start, - fb->fb.fix.smem_len); -} - -static void aaec2000_clcd_remove(struct clcd_fb *fb) -{ - dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len, - fb->fb.screen_base, fb->fb.fix.smem_start); -} - -static struct clcd_board clcd_plat_data = { - .name = "AAEC-2000", - .check = clcdfb_check, - .decode = clcdfb_decode, - .setup = aaec2000_clcd_setup, - .mmap = aaec2000_clcd_mmap, - .remove = aaec2000_clcd_remove, -}; - -static struct amba_device clcd_device = { - .dev = { - .init_name = "mb:16", - .coherent_dma_mask = ~0, - .platform_data = &clcd_plat_data, - }, - .res = { - .start = AAEC_CLCD_PHYS, - .end = AAEC_CLCD_PHYS + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - .irq = { INT_LCD, NO_IRQ }, - .periphid = 0x41110, -}; - -static struct amba_device *amba_devs[] __initdata = { - &clcd_device, -}; - -void clk_disable(struct clk *clk) -{ -} - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - return 0; -} - -int clk_enable(struct clk *clk) -{ - return 0; -} - -struct clk *clk_get(struct device *dev, const char *id) -{ - return dev && strcmp(dev_name(dev), "mb:16") == 0 ? NULL : ERR_PTR(-ENOENT); -} - -void clk_put(struct clk *clk) -{ -} - -void __init aaec2000_set_clcd_plat_data(struct aaec2000_clcd_info *clcd) -{ - clcd_plat_data.enable = clcd->enable; - clcd_plat_data.disable = clcd->disable; - memcpy(&mach_clcd_panel, &clcd->panel, sizeof(struct clcd_panel)); -} - -static struct flash_platform_data aaec2000_flash_data = { - .map_name = "cfi_probe", - .width = 4, -}; - -static struct resource aaec2000_flash_resource = { - .start = AAEC_FLASH_BASE, - .end = AAEC_FLASH_BASE + AAEC_FLASH_SIZE, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device aaec2000_flash_device = { - .name = "armflash", - .id = 0, - .dev = { - .platform_data = &aaec2000_flash_data, - }, - .num_resources = 1, - .resource = &aaec2000_flash_resource, -}; - -static int __init aaec2000_init(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { - struct amba_device *d = amba_devs[i]; - amba_device_register(d, &iomem_resource); - } - - platform_device_register(&aaec2000_flash_device); - - return 0; -}; -arch_initcall(aaec2000_init); - diff --git a/arch/arm/mach-aaec2000/core.h b/arch/arm/mach-aaec2000/core.h deleted file mode 100644 index 59501b573167..000000000000 --- a/arch/arm/mach-aaec2000/core.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * linux/arch/arm/mach-aaec2000/core.h - * - * Copyright (c) 2005 Nicolas Bellido Y Ortega - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <linux/amba/bus.h> -#include <linux/amba/clcd.h> - -struct sys_timer; - -extern struct sys_timer aaec2000_timer; -extern void __init aaec2000_map_io(void); -extern void __init aaec2000_init_irq(void); - -struct aaec2000_clcd_info { - struct clcd_panel panel; - void (*disable)(struct clcd_fb *); - void (*enable)(struct clcd_fb *); -}; - -extern void __init aaec2000_set_clcd_plat_data(struct aaec2000_clcd_info *); - diff --git a/arch/arm/mach-aaec2000/include/mach/aaec2000.h b/arch/arm/mach-aaec2000/include/mach/aaec2000.h deleted file mode 100644 index bc729c42f843..000000000000 --- a/arch/arm/mach-aaec2000/include/mach/aaec2000.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * arch/arm/mach-aaec2000/include/mach/aaec2000.h - * - * AAEC-2000 registers definition - * - * Copyright (c) 2005 Nicolas Bellido Y Ortega - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_AAEC2000_H -#define __ASM_ARCH_AAEC2000_H - -#ifndef __ASM_ARCH_HARDWARE_H -#error You must include hardware.h not this file -#endif /* __ASM_ARCH_HARDWARE_H */ - -/* Chip selects */ -#define AAEC_CS0 0x00000000 -#define AAEC_CS1 0x10000000 -#define AAEC_CS2 0x20000000 -#define AAEC_CS3 0x30000000 - -/* Flash */ -#define AAEC_FLASH_BASE AAEC_CS0 -#define AAEC_FLASH_SIZE SZ_64M - -/* Interrupt controller */ -#define IRQ_BASE __REG(0x80000500) -#define IRQ_INTSR __REG(0x80000500) /* Int Status Register */ -#define IRQ_INTRSR __REG(0x80000504) /* Int Raw (unmasked) Status */ -#define IRQ_INTENS __REG(0x80000508) /* Int Enable Set */ -#define IRQ_INTENC __REG(0x8000050c) /* Int Enable Clear */ - -/* UART 1 */ -#define UART1_BASE __REG(0x80000600) -#define UART1_DR __REG(0x80000600) /* Data/FIFO Register */ -#define UART1_LCR __REG(0x80000604) /* Link Control Register */ -#define UART1_BRCR __REG(0x80000608) /* Baud Rate Control Register */ -#define UART1_CR __REG(0x8000060c) /* Control Register */ -#define UART1_SR __REG(0x80000610) /* Status Register */ -#define UART1_INT __REG(0x80000614) /* Interrupt Status Register */ -#define UART1_INTM __REG(0x80000618) /* Interrupt Mask Register */ -#define UART1_INTRES __REG(0x8000061c) /* Int Result (masked status) Register */ - -/* UART 2 */ -#define UART2_BASE __REG(0x80000700) -#define UART2_DR __REG(0x80000700) /* Data/FIFO Register */ -#define UART2_LCR __REG(0x80000704) /* Link Control Register */ -#define UART2_BRCR __REG(0x80000708) /* Baud Rate Control Register */ -#define UART2_CR __REG(0x8000070c) /* Control Register */ -#define UART2_SR __REG(0x80000710) /* Status Register */ -#define UART2_INT __REG(0x80000714) /* Interrupt Status Register */ -#define UART2_INTM __REG(0x80000718) /* Interrupt Mask Register */ -#define UART2_INTRES __REG(0x8000071c) /* Int Result (masked status) Register */ - -/* UART 3 */ -#define UART3_BASE __REG(0x80000800) -#define UART3_DR __REG(0x80000800) /* Data/FIFO Register */ -#define UART3_LCR __REG(0x80000804) /* Link Control Register */ -#define UART3_BRCR __REG(0x80000808) /* Baud Rate Control Register */ -#define UART3_CR __REG(0x8000080c) /* Control Register */ -#define UART3_SR __REG(0x80000810) /* Status Register */ -#define UART3_INT __REG(0x80000814) /* Interrupt Status Register */ -#define UART3_INTM __REG(0x80000818) /* Interrupt Mask Register */ -#define UART3_INTRES __REG(0x8000081c) /* Int Result (masked status) Register */ - -/* These are used in some places */ -#define _UART1_BASE __PREG(UART1_BASE) -#define _UART2_BASE __PREG(UART2_BASE) -#define _UART3_BASE __PREG(UART3_BASE) - -/* UART Registers Offsets */ -#define UART_DR 0x00 -#define UART_LCR 0x04 -#define UART_BRCR 0x08 -#define UART_CR 0x0c -#define UART_SR 0x10 -#define UART_INT 0x14 -#define UART_INTM 0x18 -#define UART_INTRES 0x1c - -/* UART_LCR Bitmask */ -#define UART_LCR_BRK (1 << 0) /* Send Break */ -#define UART_LCR_PEN (1 << 1) /* Parity Enable */ -#define UART_LCR_EP (1 << 2) /* Even/Odd Parity */ -#define UART_LCR_S2 (1 << 3) /* One/Two Stop bits */ -#define UART_LCR_FIFO (1 << 4) /* FIFO Enable */ -#define UART_LCR_WL5 (0 << 5) /* Word Length - 5 bits */ -#define UART_LCR_WL6 (1 << 5) /* Word Length - 6 bits */ -#define UART_LCR_WL7 (1 << 6) /* Word Length - 7 bits */ -#define UART_LCR_WL8 (1 << 7) /* Word Length - 8 bits */ - -/* UART_CR Bitmask */ -#define UART_CR_EN (1 << 0) /* UART Enable */ -#define UART_CR_SIR (1 << 1) /* IrDA SIR Enable */ -#define UART_CR_SIRLP (1 << 2) /* Low Power IrDA Enable */ -#define UART_CR_RXP (1 << 3) /* Receive Pin Polarity */ -#define UART_CR_TXP (1 << 4) /* Transmit Pin Polarity */ -#define UART_CR_MXP (1 << 5) /* Modem Pin Polarity */ -#define UART_CR_LOOP (1 << 6) /* Loopback Mode */ - -/* UART_SR Bitmask */ -#define UART_SR_CTS (1 << 0) /* Clear To Send Status */ -#define UART_SR_DSR (1 << 1) /* Data Set Ready Status */ -#define UART_SR_DCD (1 << 2) /* Data Carrier Detect Status */ -#define UART_SR_TxBSY (1 << 3) /* Transmitter Busy Status */ -#define UART_SR_RxFE (1 << 4) /* Receive FIFO Empty Status */ -#define UART_SR_TxFF (1 << 5) /* Transmit FIFO Full Status */ -#define UART_SR_RxFF (1 << 6) /* Receive FIFO Full Status */ -#define UART_SR_TxFE (1 << 7) /* Transmit FIFO Empty Status */ - -/* UART_INT Bitmask */ -#define UART_INT_RIS (1 << 0) /* Rx Interrupt */ -#define UART_INT_TIS (1 << 1) /* Tx Interrupt */ -#define UART_INT_MIS (1 << 2) /* Modem Interrupt */ -#define UART_INT_RTIS (1 << 3) /* Receive Timeout Interrupt */ - -/* Timer 1 */ -#define TIMER1_BASE __REG(0x80000c00) -#define TIMER1_LOAD __REG(0x80000c00) /* Timer 1 Load Register */ -#define TIMER1_VAL __REG(0x80000c04) /* Timer 1 Value Register */ -#define TIMER1_CTRL __REG(0x80000c08) /* Timer 1 Control Register */ -#define TIMER1_CLEAR __REG(0x80000c0c) /* Timer 1 Clear Register */ - -/* Timer 2 */ -#define TIMER2_BASE __REG(0x80000d00) -#define TIMER2_LOAD __REG(0x80000d00) /* Timer 2 Load Register */ -#define TIMER2_VAL __REG(0x80000d04) /* Timer 2 Value Register */ -#define TIMER2_CTRL __REG(0x80000d08) /* Timer 2 Control Register */ -#define TIMER2_CLEAR __REG(0x80000d0c) /* Timer 2 Clear Register */ - -/* Timer 3 */ -#define TIMER3_BASE __REG(0x80000e00) -#define TIMER3_LOAD __REG(0x80000e00) /* Timer 3 Load Register */ -#define TIMER3_VAL __REG(0x80000e04) /* Timer 3 Value Register */ -#define TIMER3_CTRL __REG(0x80000e08) /* Timer 3 Control Register */ -#define TIMER3_CLEAR __REG(0x80000e0c) /* Timer 3 Clear Register */ - -/* Timer Control register bits */ -#define TIMER_CTRL_ENABLE (1 << 7) /* Enable (Start Timer) */ -#define TIMER_CTRL_PERIODIC (1 << 6) /* Periodic Running Mode */ -#define TIMER_CTRL_FREE_RUNNING (0 << 6) /* Normal Running Mode */ -#define TIMER_CTRL_CLKSEL_508K (1 << 3) /* 508KHz Clock select (Timer 1, 2) */ -#define TIMER_CTRL_CLKSEL_2K (0 << 3) /* 2KHz Clock Select (Timer 1, 2) */ - -/* Power and State Control */ -#define POWER_BASE __REG(0x80000400) -#define POWER_PWRSR __REG(0x80000400) /* Power Status Register */ -#define POWER_PWRCNT __REG(0x80000404) /* Power/Clock control */ -#define POWER_HALT __REG(0x80000408) /* Power Idle Mode */ -#define POWER_STDBY __REG(0x8000040c) /* Power Standby Mode */ -#define POWER_BLEOI __REG(0x80000410) /* Battery Low End of Interrupt */ -#define POWER_MCEOI __REG(0x80000414) /* Media Changed EoI */ -#define POWER_TEOI __REG(0x80000418) /* Tick EoI */ -#define POWER_STFCLR __REG(0x8000041c) /* NbFlg, RSTFlg, PFFlg, CLDFlg Clear */ -#define POWER_CLKSET __REG(0x80000420) /* Clock Speed Control */ - -/* GPIO Registers */ -#define AAEC_GPIO_PHYS 0x80000e00 - -#define AAEC_GPIO_PADR __REG(AAEC_GPIO_PHYS + 0x00) -#define AAEC_GPIO_PBDR __REG(AAEC_GPIO_PHYS + 0x04) -#define AAEC_GPIO_PCDR __REG(AAEC_GPIO_PHYS + 0x08) -#define AAEC_GPIO_PDDR __REG(AAEC_GPIO_PHYS + 0x0c) -#define AAEC_GPIO_PADDR __REG(AAEC_GPIO_PHYS + 0x10) -#define AAEC_GPIO_PBDDR __REG(AAEC_GPIO_PHYS + 0x14) -#define AAEC_GPIO_PCDDR __REG(AAEC_GPIO_PHYS + 0x18) -#define AAEC_GPIO_PDDDR __REG(AAEC_GPIO_PHYS + 0x1c) -#define AAEC_GPIO_PEDR __REG(AAEC_GPIO_PHYS + 0x20) -#define AAEC_GPIO_PEDDR __REG(AAEC_GPIO_PHYS + 0x24) -#define AAEC_GPIO_KSCAN __REG(AAEC_GPIO_PHYS + 0x28) -#define AAEC_GPIO_PINMUX __REG(AAEC_GPIO_PHYS + 0x2c) -#define AAEC_GPIO_PFDR __REG(AAEC_GPIO_PHYS + 0x30) -#define AAEC_GPIO_PFDDR __REG(AAEC_GPIO_PHYS + 0x34) -#define AAEC_GPIO_PGDR __REG(AAEC_GPIO_PHYS + 0x38) -#define AAEC_GPIO_PGDDR __REG(AAEC_GPIO_PHYS + 0x3c) -#define AAEC_GPIO_PHDR __REG(AAEC_GPIO_PHYS + 0x40) -#define AAEC_GPIO_PHDDR __REG(AAEC_GPIO_PHYS + 0x44) -#define AAEC_GPIO_RAZ __REG(AAEC_GPIO_PHYS + 0x48) -#define AAEC_GPIO_INTTYPE1 __REG(AAEC_GPIO_PHYS + 0x4c) -#define AAEC_GPIO_INTTYPE2 __REG(AAEC_GPIO_PHYS + 0x50) -#define AAEC_GPIO_FEOI __REG(AAEC_GPIO_PHYS + 0x54) -#define AAEC_GPIO_INTEN __REG(AAEC_GPIO_PHYS + 0x58) -#define AAEC_GPIO_INTSTATUS __REG(AAEC_GPIO_PHYS + 0x5c) -#define AAEC_GPIO_RAWINTSTATUS __REG(AAEC_GPIO_PHYS + 0x60) -#define AAEC_GPIO_DB __REG(AAEC_GPIO_PHYS + 0x64) -#define AAEC_GPIO_PAPINDR __REG(AAEC_GPIO_PHYS + 0x68) -#define AAEC_GPIO_PBPINDR __REG(AAEC_GPIO_PHYS + 0x6c) -#define AAEC_GPIO_PCPINDR __REG(AAEC_GPIO_PHYS + 0x70) -#define AAEC_GPIO_PDPINDR __REG(AAEC_GPIO_PHYS + 0x74) -#define AAEC_GPIO_PEPINDR __REG(AAEC_GPIO_PHYS + 0x78) -#define AAEC_GPIO_PFPINDR __REG(AAEC_GPIO_PHYS + 0x7c) -#define AAEC_GPIO_PGPINDR __REG(AAEC_GPIO_PHYS + 0x80) -#define AAEC_GPIO_PHPINDR __REG(AAEC_GPIO_PHYS + 0x84) - -#define AAEC_GPIO_PINMUX_PE0CON (1 << 0) -#define AAEC_GPIO_PINMUX_PD0CON (1 << 1) -#define AAEC_GPIO_PINMUX_CODECON (1 << 2) -#define AAEC_GPIO_PINMUX_UART3CON (1 << 3) - -/* LCD Controller */ -#define AAEC_CLCD_PHYS 0x80003000 - -#endif /* __ARM_ARCH_AAEC2000_H */ diff --git a/arch/arm/mach-aaec2000/include/mach/aaed2000.h b/arch/arm/mach-aaec2000/include/mach/aaed2000.h deleted file mode 100644 index f821295ca71b..000000000000 --- a/arch/arm/mach-aaec2000/include/mach/aaed2000.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * arch/arm/mach-aaec2000/include/mach/aaed2000.h - * - * AAED-2000 specific bits definition - * - * Copyright (c) 2005 Nicolas Bellido Y Ortega - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_AAED2000_H -#define __ASM_ARCH_AAED2000_H - -/* External GPIOs. */ - -#define EXT_GPIO_PBASE AAEC_CS3 -#define EXT_GPIO_VBASE 0xf8100000 -#define EXT_GPIO_LENGTH 0x00001000 - -#define __ext_gpio_p2v(x) ((x) - EXT_GPIO_PBASE + EXT_GPIO_VBASE) -#define __ext_gpio_v2p(x) ((x) + EXT_GPIO_PBASE - EXT_GPIO_VBASE) - -#define __EXT_GPIO_REG(x) (*((volatile u32 *)__ext_gpio_p2v(x))) -#define __EXT_GPIO_PREG(x) (__ext_gpio_v2p((u32)&(x))) - -#define AAED_EXT_GPIO __EXT_GPIO_REG(EXT_GPIO_PBASE) - -#define AAED_EGPIO_KBD_SCAN 0x00003fff /* Keyboard scan data */ -#define AAED_EGPIO_PWR_INT 0x00008fff /* Smart battery charger interrupt */ -#define AAED_EGPIO_SWITCHED 0x000f0000 /* DIP Switches */ -#define AAED_EGPIO_USB_VBUS 0x00400000 /* USB Vbus sense */ -#define AAED_EGPIO_LCD_PWR_EN 0x02000000 /* LCD and backlight PWR enable */ -#define AAED_EGPIO_nLED0 0x20000000 /* LED 0 */ -#define AAED_EGPIO_nLED1 0x20000000 /* LED 1 */ -#define AAED_EGPIO_nLED2 0x20000000 /* LED 2 */ - - -#endif /* __ARM_ARCH_AAED2000_H */ diff --git a/arch/arm/mach-aaec2000/include/mach/debug-macro.S b/arch/arm/mach-aaec2000/include/mach/debug-macro.S deleted file mode 100644 index bc7ad5561c4c..000000000000 --- a/arch/arm/mach-aaec2000/include/mach/debug-macro.S +++ /dev/null @@ -1,35 +0,0 @@ -/* arch/arm/mach-aaec2000/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (c) 2005 Nicolas Bellido Y Ortega - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "hardware.h" - .macro addruart, rp, rv - mov \rp, 0x00000800 - orr \rv, \rp, #io_p2v(0x80000000) @ virtual - orr \rp, \rp, #0x80000000 @ physical - .endm - - .macro senduart,rd,rx - str \rd, [\rx, #0] - .endm - - .macro busyuart,rd,rx -1002: ldr \rd, [\rx, #0x10] - tst \rd, #(1 << 7) - beq 1002b - .endm - - .macro waituart,rd,rx -#if 0 -1001: ldr \rd, [\rx, #0x10] - tst \rd, #(1 << 5) - beq 1001b -#endif - .endm diff --git a/arch/arm/mach-aaec2000/include/mach/entry-macro.S b/arch/arm/mach-aaec2000/include/mach/entry-macro.S deleted file mode 100644 index c8fb34469007..000000000000 --- a/arch/arm/mach-aaec2000/include/mach/entry-macro.S +++ /dev/null @@ -1,40 +0,0 @@ -/* - * arch/arm/mach-aaec2000/include/mach/entry-macro.S - * - * Low-level IRQ helper for aaec-2000 based platforms - * - * Copyright (c) 2005 Nicolas Bellido Y Ortega - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#include <mach/irqs.h> - - .macro disable_fiq - .endm - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - mov r4, #0xf8000000 - add r4, r4, #0x00000500 - mov \base, r4 - ldr \irqstat, [\base, #0] - cmp \irqstat, #0 - bne 1001f - ldr \irqnr, =NR_IRQS+1 - b 1003f -1001: mov \irqnr, #0 -1002: ands \tmp, \irqstat, #1 - mov \irqstat, \irqstat, LSR #1 - add \irqnr, \irqnr, #1 - beq 1002b - sub \irqnr, \irqnr, #1 -1003: - .endm diff --git a/arch/arm/mach-aaec2000/include/mach/hardware.h b/arch/arm/mach-aaec2000/include/mach/hardware.h deleted file mode 100644 index 965a6f6672d6..000000000000 --- a/arch/arm/mach-aaec2000/include/mach/hardware.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * arch/arm/mach-aaec2000/include/mach/hardware.h - * - * Copyright (c) 2005 Nicolas Bellido Y Ortega - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <asm/sizes.h> -#include <mach/aaec2000.h> - -/* The kernel is loaded at physical address 0xf8000000. - * We map the IO space a bit after - */ -#define PIO_APB_BASE 0x80000000 -#define VIO_APB_BASE 0xf8000000 -#define IO_APB_LENGTH 0x2000 -#define PIO_AHB_BASE 0x80002000 -#define VIO_AHB_BASE 0xf8002000 -#define IO_AHB_LENGTH 0x2000 - -#define VIO_BASE VIO_APB_BASE -#define PIO_BASE PIO_APB_BASE - -#define io_p2v(x) ( (x) - PIO_BASE + VIO_BASE ) -#define io_v2p(x) ( (x) + PIO_BASE - VIO_BASE ) - -#ifndef __ASSEMBLY__ - -#include <asm/types.h> - -/* FIXME: Is it needed to optimize this a la pxa ?? */ -#define __REG(x) (*((volatile u32 *)io_p2v(x))) -#define __PREG(x) (io_v2p((u32)&(x))) - -#else /* __ASSEMBLY__ */ - -#define __REG(x) io_p2v(x) -#define __PREG(x) io_v2p(x) - -#endif - -#include "aaec2000.h" - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-aaec2000/include/mach/io.h b/arch/arm/mach-aaec2000/include/mach/io.h deleted file mode 100644 index ab4fe5d20eaf..000000000000 --- a/arch/arm/mach-aaec2000/include/mach/io.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * arch/arm/mach-aaec2000/include/mach/io.h - * - * Copied from asm/arch/sa1100/io.h - */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff - -/* - * We don't actually have real ISA nor PCI buses, but there is so many - * drivers out there that might just work if we fake them... - */ -#define __io(a) __typesafe_io(a) -#define __mem_pci(a) (a) - -#endif diff --git a/arch/arm/mach-aaec2000/include/mach/irqs.h b/arch/arm/mach-aaec2000/include/mach/irqs.h deleted file mode 100644 index bf45c6d2f294..000000000000 --- a/arch/arm/mach-aaec2000/include/mach/irqs.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * arch/arm/mach-aaec2000/include/mach/irqs.h - * - * Copyright (c) 2005 Nicolas Bellido Y Ortega - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - - -#define INT_GPIOF0_FIQ 0 /* External GPIO Port F O Fast Interrupt Input */ -#define INT_BL_FIQ 1 /* Battery Low Fast Interrupt */ -#define INT_WE_FIQ 2 /* Watchdog Expired Fast Interrupt */ -#define INT_MV_FIQ 3 /* Media Changed Interrupt */ -#define INT_SC 4 /* Sound Codec Interrupt */ -#define INT_GPIO1 5 /* GPIO Port F Configurable Int 1 */ -#define INT_GPIO2 6 /* GPIO Port F Configurable Int 2 */ -#define INT_GPIO3 7 /* GPIO Port F Configurable Int 3 */ -#define INT_TMR1_OFL 8 /* Timer 1 Overflow Interrupt */ -#define INT_TMR2_OFL 9 /* Timer 2 Overflow Interrupt */ -#define INT_RTC_CM 10 /* RTC Compare Match Interrupt */ -#define INT_TICK 11 /* 64Hz Tick Interrupt */ -#define INT_UART1 12 /* UART1 Interrupt */ -#define INT_UART2 13 /* UART2 & Modem State Changed Interrupt */ -#define INT_LCD 14 /* LCD Interrupt */ -#define INT_SSI 15 /* SSI End of Transfer Interrupt */ -#define INT_UART3 16 /* UART3 Interrupt */ -#define INT_SCI 17 /* SCI Interrupt */ -#define INT_AAC 18 /* Advanced Audio Codec Interrupt */ -#define INT_MMC 19 /* MMC Interrupt */ -#define INT_USB 20 /* USB Interrupt */ -#define INT_DMA 21 /* DMA Interrupt */ -#define INT_TMR3_UOFL 22 /* Timer 3 Underflow Interrupt */ -#define INT_GPIO4 23 /* GPIO Port F Configurable Int 4 */ -#define INT_GPIO5 24 /* GPIO Port F Configurable Int 4 */ -#define INT_GPIO6 25 /* GPIO Port F Configurable Int 4 */ -#define INT_GPIO7 26 /* GPIO Port F Configurable Int 4 */ -#define INT_BMI 27 /* BMI Interrupt */ - -#define NR_IRQS (INT_BMI + 1) - -#endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-aaec2000/include/mach/memory.h b/arch/arm/mach-aaec2000/include/mach/memory.h deleted file mode 100644 index 4f93c567a35a..000000000000 --- a/arch/arm/mach-aaec2000/include/mach/memory.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * arch/arm/mach-aaec2000/include/mach/memory.h - * - * Copyright (c) 2005 Nicolas Bellido Y Ortega - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - - -#define PHYS_OFFSET UL(0xf0000000) - -#endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/mach-aaec2000/include/mach/system.h b/arch/arm/mach-aaec2000/include/mach/system.h deleted file mode 100644 index fe08ca1add6f..000000000000 --- a/arch/arm/mach-aaec2000/include/mach/system.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * arch/arm/mach-aaed2000/include/mach/system.h - * - * Copyright (c) 2005 Nicolas Bellido Y Ortega - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_SYSTEM_H -#define __ASM_ARCH_SYSTEM_H - -static inline void arch_idle(void) -{ - cpu_do_idle(); -} - -static inline void arch_reset(char mode, const char *cmd) -{ - cpu_reset(0); -} - -#endif /* __ASM_ARCH_SYSTEM_H */ diff --git a/arch/arm/mach-aaec2000/include/mach/timex.h b/arch/arm/mach-aaec2000/include/mach/timex.h deleted file mode 100644 index 6c8edf4a8828..000000000000 --- a/arch/arm/mach-aaec2000/include/mach/timex.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * arch/arm/mach-aaec2000/include/mach/timex.h - * - * AAEC-2000 Architecture timex specification - * - * Copyright (c) 2005 Nicolas Bellido Y Ortega - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H - -#define CLOCK_TICK_RATE 508000 - -#endif /* __ASM_ARCH_TIMEX_H */ diff --git a/arch/arm/mach-aaec2000/include/mach/uncompress.h b/arch/arm/mach-aaec2000/include/mach/uncompress.h deleted file mode 100644 index 381ecad1a1bb..000000000000 --- a/arch/arm/mach-aaec2000/include/mach/uncompress.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * arch/arm/mach-aaec2000/include/mach/uncompress.h - * - * Copyright (c) 2005 Nicolas Bellido Y Ortega - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -#include "hardware.h" - -#define UART(x) (*(volatile unsigned long *)(serial_port + (x))) - -static void putc(int c) -{ - unsigned long serial_port; - do { - serial_port = _UART3_BASE; - if (UART(UART_CR) & UART_CR_EN) break; - serial_port = _UART1_BASE; - if (UART(UART_CR) & UART_CR_EN) break; - serial_port = _UART2_BASE; - if (UART(UART_CR) & UART_CR_EN) break; - return; - } while (0); - - /* wait for space in the UART's transmitter */ - while ((UART(UART_SR) & UART_SR_TxFF)) - barrier(); - - /* send the character out. */ - UART(UART_DR) = c; -} - -static inline void flush(void) -{ -} - -#define arch_decomp_setup() -#define arch_decomp_wdog() - -#endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-aaec2000/include/mach/vmalloc.h b/arch/arm/mach-aaec2000/include/mach/vmalloc.h deleted file mode 100644 index a6299e8321bd..000000000000 --- a/arch/arm/mach-aaec2000/include/mach/vmalloc.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * arch/arm/mach-aaec2000/include/mach/vmalloc.h - * - * Copyright (c) 2005 Nicolas Bellido Y Ortega - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_VMALLOC_H -#define __ASM_ARCH_VMALLOC_H - -#define VMALLOC_END 0xd0000000UL - -#endif /* __ASM_ARCH_VMALLOC_H */ diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c index 0a99b3cedd7a..17f7d9b32142 100644 --- a/arch/arm/mach-at91/board-snapper9260.c +++ b/arch/arm/mach-at91/board-snapper9260.c @@ -153,6 +153,7 @@ static struct i2c_board_info __initdata snapper9260_i2c_devices[] = { { /* RTC */ I2C_BOARD_INFO("isl1208", 0x6f), + .irq = gpio_to_irq(AT91_PIN_PA31), }, }; diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h index bfdd8ab26dc8..ddeb64536756 100644 --- a/arch/arm/mach-at91/include/mach/gpio.h +++ b/arch/arm/mach-at91/include/mach/gpio.h @@ -220,15 +220,8 @@ extern void at91_gpio_resume(void); #define gpio_set_value __gpio_set_value #define gpio_cansleep __gpio_cansleep -static inline int gpio_to_irq(unsigned gpio) -{ - return gpio; -} - -static inline int irq_to_gpio(unsigned irq) -{ - return irq; -} +#define gpio_to_irq(gpio) (gpio) +#define irq_to_gpio(irq) (irq) #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/mach-at91/include/mach/memory.h b/arch/arm/mach-at91/include/mach/memory.h index 14f4ef4b6a9e..c2cfe5040642 100644 --- a/arch/arm/mach-at91/include/mach/memory.h +++ b/arch/arm/mach-at91/include/mach/memory.h @@ -23,6 +23,6 @@ #include <mach/hardware.h> -#define PHYS_OFFSET (AT91_SDRAM_BASE) +#define PLAT_PHYS_OFFSET (AT91_SDRAM_BASE) #endif diff --git a/arch/arm/mach-bcmring/include/mach/hardware.h b/arch/arm/mach-bcmring/include/mach/hardware.h index 447eb340c611..8bf3564fba50 100644 --- a/arch/arm/mach-bcmring/include/mach/hardware.h +++ b/arch/arm/mach-bcmring/include/mach/hardware.h @@ -31,7 +31,7 @@ * *_SIZE is the size of the region * *_BASE is the virtual address */ -#define RAM_START PHYS_OFFSET +#define RAM_START PLAT_PHYS_OFFSET #define RAM_SIZE (CFG_GLOBAL_RAM_SIZE-CFG_GLOBAL_RAM_SIZE_RESERVED) #define RAM_BASE PAGE_OFFSET diff --git a/arch/arm/mach-bcmring/include/mach/memory.h b/arch/arm/mach-bcmring/include/mach/memory.h index 114f942bb4f3..15162e4c75f9 100644 --- a/arch/arm/mach-bcmring/include/mach/memory.h +++ b/arch/arm/mach-bcmring/include/mach/memory.h @@ -23,7 +23,7 @@ * files. Use virt_to_phys/phys_to_virt/__pa/__va instead. */ -#define PHYS_OFFSET CFG_GLOBAL_RAM_BASE +#define PLAT_PHYS_OFFSET CFG_GLOBAL_RAM_BASE /* * Maximum DMA memory allowed is 14M diff --git a/arch/arm/mach-clps711x/include/mach/memory.h b/arch/arm/mach-clps711x/include/mach/memory.h index f45c8e892cb5..3a032a67725c 100644 --- a/arch/arm/mach-clps711x/include/mach/memory.h +++ b/arch/arm/mach-clps711x/include/mach/memory.h @@ -23,7 +23,7 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0xc0000000) +#define PLAT_PHYS_OFFSET UL(0xc0000000) #if !defined(CONFIG_ARCH_CDB89712) && !defined (CONFIG_ARCH_AUTCPU12) diff --git a/arch/arm/mach-clps711x/include/mach/time.h b/arch/arm/mach-clps711x/include/mach/time.h index 8fe283ccd1f3..61fef9129c6a 100644 --- a/arch/arm/mach-clps711x/include/mach/time.h +++ b/arch/arm/mach-clps711x/include/mach/time.h @@ -30,7 +30,7 @@ p720t_timer_interrupt(int irq, void *dev_id) { struct pt_regs *regs = get_irq_regs(); do_leds(); - do_timer(1); + xtime_update(1); #ifndef CONFIG_SMP update_process_times(user_mode(regs)); #endif diff --git a/arch/arm/mach-cns3xxx/include/mach/memory.h b/arch/arm/mach-cns3xxx/include/mach/memory.h index 3b6b769b7a27..dc16c5c5d86b 100644 --- a/arch/arm/mach-cns3xxx/include/mach/memory.h +++ b/arch/arm/mach-cns3xxx/include/mach/memory.h @@ -13,7 +13,7 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #define __phys_to_bus(x) ((x) + PHYS_OFFSET) #define __bus_to_phys(x) ((x) - PHYS_OFFSET) diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h index 22eb97c1c30b..78822723f382 100644 --- a/arch/arm/mach-davinci/include/mach/memory.h +++ b/arch/arm/mach-davinci/include/mach/memory.h @@ -26,9 +26,9 @@ #if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx) #error Cannot enable DaVinci and DA8XX platforms concurrently #elif defined(CONFIG_ARCH_DAVINCI_DA8XX) -#define PHYS_OFFSET DA8XX_DDR_BASE +#define PLAT_PHYS_OFFSET DA8XX_DDR_BASE #else -#define PHYS_OFFSET DAVINCI_DDR_BASE +#define PLAT_PHYS_OFFSET DAVINCI_DDR_BASE #endif #define DDR2_SDRCR_OFFSET 0xc diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig index a4ed3900912a..dd937c526a45 100644 --- a/arch/arm/mach-dove/Kconfig +++ b/arch/arm/mach-dove/Kconfig @@ -9,7 +9,7 @@ config MACH_DOVE_DB Say 'Y' here if you want your kernel to support the Marvell DB-MV88AP510 Development Board. - config MACH_CM_A510 +config MACH_CM_A510 bool "CompuLab CM-A510 Board" help Say 'Y' here if you want your kernel to support the diff --git a/arch/arm/mach-dove/include/mach/memory.h b/arch/arm/mach-dove/include/mach/memory.h index d66872074946..bbc93fee6c75 100644 --- a/arch/arm/mach-dove/include/mach/memory.h +++ b/arch/arm/mach-dove/include/mach/memory.h @@ -5,6 +5,6 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif diff --git a/arch/arm/mach-ebsa110/include/mach/memory.h b/arch/arm/mach-ebsa110/include/mach/memory.h index 0ca66d080c69..8e49066ad850 100644 --- a/arch/arm/mach-ebsa110/include/mach/memory.h +++ b/arch/arm/mach-ebsa110/include/mach/memory.h @@ -19,7 +19,7 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) /* * Cache flushing area - SRAM diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c index 4b0431652131..9969bb115f60 100644 --- a/arch/arm/mach-ep93xx/edb93xx.c +++ b/arch/arm/mach-ep93xx/edb93xx.c @@ -30,8 +30,13 @@ #include <linux/gpio.h> #include <linux/i2c.h> #include <linux/i2c-gpio.h> +#include <linux/spi/spi.h> + +#include <sound/cs4271.h> #include <mach/hardware.h> +#include <mach/fb.h> +#include <mach/ep93xx_spi.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -93,6 +98,83 @@ static void __init edb93xx_register_i2c(void) /************************************************************************* + * EDB93xx SPI peripheral handling + *************************************************************************/ +static struct cs4271_platform_data edb93xx_cs4271_data = { + .gpio_nreset = -EINVAL, /* filled in later */ +}; + +static int edb93xx_cs4271_hw_setup(struct spi_device *spi) +{ + return gpio_request_one(EP93XX_GPIO_LINE_EGPIO6, + GPIOF_OUT_INIT_HIGH, spi->modalias); +} + +static void edb93xx_cs4271_hw_cleanup(struct spi_device *spi) +{ + gpio_free(EP93XX_GPIO_LINE_EGPIO6); +} + +static void edb93xx_cs4271_hw_cs_control(struct spi_device *spi, int value) +{ + gpio_set_value(EP93XX_GPIO_LINE_EGPIO6, value); +} + +static struct ep93xx_spi_chip_ops edb93xx_cs4271_hw = { + .setup = edb93xx_cs4271_hw_setup, + .cleanup = edb93xx_cs4271_hw_cleanup, + .cs_control = edb93xx_cs4271_hw_cs_control, +}; + +static struct spi_board_info edb93xx_spi_board_info[] __initdata = { + { + .modalias = "cs4271", + .platform_data = &edb93xx_cs4271_data, + .controller_data = &edb93xx_cs4271_hw, + .max_speed_hz = 6000000, + .bus_num = 0, + .chip_select = 0, + .mode = SPI_MODE_3, + }, +}; + +static struct ep93xx_spi_info edb93xx_spi_info __initdata = { + .num_chipselect = ARRAY_SIZE(edb93xx_spi_board_info), +}; + +static void __init edb93xx_register_spi(void) +{ + if (machine_is_edb9301() || machine_is_edb9302()) + edb93xx_cs4271_data.gpio_nreset = EP93XX_GPIO_LINE_EGPIO1; + else if (machine_is_edb9302a() || machine_is_edb9307a()) + edb93xx_cs4271_data.gpio_nreset = EP93XX_GPIO_LINE_H(2); + else if (machine_is_edb9315a()) + edb93xx_cs4271_data.gpio_nreset = EP93XX_GPIO_LINE_EGPIO14; + + ep93xx_register_spi(&edb93xx_spi_info, edb93xx_spi_board_info, + ARRAY_SIZE(edb93xx_spi_board_info)); +} + + +/************************************************************************* + * EDB93xx I2S + *************************************************************************/ +static int __init edb93xx_has_audio(void) +{ + return (machine_is_edb9301() || machine_is_edb9302() || + machine_is_edb9302a() || machine_is_edb9307a() || + machine_is_edb9315a()); +} + +static void __init edb93xx_register_i2s(void) +{ + if (edb93xx_has_audio()) { + ep93xx_register_i2s(); + } +} + + +/************************************************************************* * EDB93xx pwm *************************************************************************/ static void __init edb93xx_register_pwm(void) @@ -111,13 +193,47 @@ static void __init edb93xx_register_pwm(void) } +/************************************************************************* + * EDB93xx framebuffer + *************************************************************************/ +static struct ep93xxfb_mach_info __initdata edb93xxfb_info = { + .num_modes = EP93XXFB_USE_MODEDB, + .bpp = 16, + .flags = 0, +}; + +static int __init edb93xx_has_fb(void) +{ + /* These platforms have an ep93xx with video capability */ + return machine_is_edb9307() || machine_is_edb9307a() || + machine_is_edb9312() || machine_is_edb9315() || + machine_is_edb9315a(); +} + +static void __init edb93xx_register_fb(void) +{ + if (!edb93xx_has_fb()) + return; + + if (machine_is_edb9307a() || machine_is_edb9315a()) + edb93xxfb_info.flags |= EP93XXFB_USE_SDCSN0; + else + edb93xxfb_info.flags |= EP93XXFB_USE_SDCSN3; + + ep93xx_register_fb(&edb93xxfb_info); +} + + static void __init edb93xx_init_machine(void) { ep93xx_init_devices(); edb93xx_register_flash(); ep93xx_register_eth(&edb93xx_eth_data, 1); edb93xx_register_i2c(); + edb93xx_register_spi(); + edb93xx_register_i2s(); edb93xx_register_pwm(); + edb93xx_register_fb(); } diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c index bec34b834958..a889fa7c3ba1 100644 --- a/arch/arm/mach-ep93xx/gpio.c +++ b/arch/arm/mach-ep93xx/gpio.c @@ -61,7 +61,7 @@ static inline void ep93xx_gpio_int_mask(unsigned line) gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7)); } -void ep93xx_gpio_int_debounce(unsigned int irq, int enable) +static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable) { int line = irq_to_gpio(irq); int port = line >> 3; @@ -75,7 +75,6 @@ void ep93xx_gpio_int_debounce(unsigned int irq, int enable) __raw_writeb(gpio_int_debounce[port], EP93XX_GPIO_REG(int_debounce_register_offset[port])); } -EXPORT_SYMBOL(ep93xx_gpio_int_debounce); static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc) { @@ -335,6 +334,20 @@ static void ep93xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val) local_irq_restore(flags); } +static int ep93xx_gpio_set_debounce(struct gpio_chip *chip, + unsigned offset, unsigned debounce) +{ + int gpio = chip->base + offset; + int irq = gpio_to_irq(gpio); + + if (irq < 0) + return -EINVAL; + + ep93xx_gpio_int_debounce(irq, debounce ? true : false); + + return 0; +} + static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) { struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip); @@ -434,6 +447,18 @@ void __init ep93xx_gpio_init(void) EP93XX_SYSCON_DEVCFG_GONIDE | EP93XX_SYSCON_DEVCFG_HONIDE); - for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) - gpiochip_add(&ep93xx_gpio_banks[i].chip); + for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) { + struct gpio_chip *chip = &ep93xx_gpio_banks[i].chip; + + /* + * Ports A, B, and F support input debouncing when + * used as interrupts. + */ + if (!strcmp(chip->label, "A") || + !strcmp(chip->label, "B") || + !strcmp(chip->label, "F")) + chip->set_debounce = ep93xx_gpio_set_debounce; + + gpiochip_add(chip); + } } diff --git a/arch/arm/mach-ep93xx/include/mach/gpio.h b/arch/arm/mach-ep93xx/include/mach/gpio.h index c991b149bdf2..c57152c231f1 100644 --- a/arch/arm/mach-ep93xx/include/mach/gpio.h +++ b/arch/arm/mach-ep93xx/include/mach/gpio.h @@ -99,8 +99,6 @@ /* maximum value for irq capable line identifiers */ #define EP93XX_GPIO_LINE_MAX_IRQ EP93XX_GPIO_LINE_F(7) -extern void ep93xx_gpio_int_debounce(unsigned int irq, int enable); - /* new generic GPIO API - see Documentation/gpio.txt */ #include <asm-generic/gpio.h> diff --git a/arch/arm/mach-ep93xx/include/mach/memory.h b/arch/arm/mach-ep93xx/include/mach/memory.h index 554064e90307..c9400cf0051c 100644 --- a/arch/arm/mach-ep93xx/include/mach/memory.h +++ b/arch/arm/mach-ep93xx/include/mach/memory.h @@ -6,15 +6,15 @@ #define __ASM_ARCH_MEMORY_H #if defined(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET) -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #elif defined(CONFIG_EP93XX_SDCE0_PHYS_OFFSET) -#define PHYS_OFFSET UL(0xc0000000) +#define PLAT_PHYS_OFFSET UL(0xc0000000) #elif defined(CONFIG_EP93XX_SDCE1_PHYS_OFFSET) -#define PHYS_OFFSET UL(0xd0000000) +#define PLAT_PHYS_OFFSET UL(0xd0000000) #elif defined(CONFIG_EP93XX_SDCE2_PHYS_OFFSET) -#define PHYS_OFFSET UL(0xe0000000) +#define PLAT_PHYS_OFFSET UL(0xe0000000) #elif defined(CONFIG_EP93XX_SDCE3_ASYNC_PHYS_OFFSET) -#define PHYS_OFFSET UL(0xf0000000) +#define PLAT_PHYS_OFFSET UL(0xf0000000) #else #error "Kconfig bug: No EP93xx PHYS_OFFSET set" #endif diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c index bc5e83fb5819..a921fe92b858 100644 --- a/arch/arm/mach-footbridge/dc21285-timer.c +++ b/arch/arm/mach-footbridge/dc21285-timer.c @@ -4,10 +4,11 @@ * Copyright (C) 1998 Russell King. * Copyright (C) 1998 Phil Blundell */ +#include <linux/clockchips.h> +#include <linux/clocksource.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/irq.h> -#include <linux/spinlock.h> #include <asm/irq.h> @@ -16,32 +17,76 @@ #include "common.h" -/* - * Footbridge timer 1 support. - */ -static unsigned long timer1_latch; +static cycle_t cksrc_dc21285_read(struct clocksource *cs) +{ + return cs->mask - *CSR_TIMER2_VALUE; +} -static unsigned long timer1_gettimeoffset (void) +static int cksrc_dc21285_enable(struct clocksource *cs) { - unsigned long value = timer1_latch - *CSR_TIMER1_VALUE; + *CSR_TIMER2_LOAD = cs->mask; + *CSR_TIMER2_CLR = 0; + *CSR_TIMER2_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16; + return 0; +} - return ((tick_nsec / 1000) * value) / timer1_latch; +static int cksrc_dc21285_disable(struct clocksource *cs) +{ + *CSR_TIMER2_CNTL = 0; } -static irqreturn_t -timer1_interrupt(int irq, void *dev_id) +static struct clocksource cksrc_dc21285 = { + .name = "dc21285_timer2", + .rating = 200, + .read = cksrc_dc21285_read, + .enable = cksrc_dc21285_enable, + .disable = cksrc_dc21285_disable, + .mask = CLOCKSOURCE_MASK(24), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static void ckevt_dc21285_set_mode(enum clock_event_mode mode, + struct clock_event_device *c) { + switch (mode) { + case CLOCK_EVT_MODE_RESUME: + case CLOCK_EVT_MODE_PERIODIC: + *CSR_TIMER1_CLR = 0; + *CSR_TIMER1_LOAD = (mem_fclk_21285 + 8 * HZ) / (16 * HZ); + *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD | + TIMER_CNTL_DIV16; + break; + + default: + *CSR_TIMER1_CNTL = 0; + break; + } +} + +static struct clock_event_device ckevt_dc21285 = { + .name = "dc21285_timer1", + .features = CLOCK_EVT_FEAT_PERIODIC, + .rating = 200, + .irq = IRQ_TIMER1, + .set_mode = ckevt_dc21285_set_mode, +}; + +static irqreturn_t timer1_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *ce = dev_id; + *CSR_TIMER1_CLR = 0; - timer_tick(); + ce->event_handler(ce); return IRQ_HANDLED; } static struct irqaction footbridge_timer_irq = { - .name = "Timer1 timer tick", + .name = "dc21285_timer1", .handler = timer1_interrupt, .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .dev_id = &ckevt_dc21285, }; /* @@ -49,16 +94,19 @@ static struct irqaction footbridge_timer_irq = { */ static void __init footbridge_timer_init(void) { - timer1_latch = (mem_fclk_21285 + 8 * HZ) / (16 * HZ); + struct clock_event_device *ce = &ckevt_dc21285; + + clocksource_register_hz(&cksrc_dc21285, (mem_fclk_21285 + 8) / 16); + + setup_irq(ce->irq, &footbridge_timer_irq); - *CSR_TIMER1_CLR = 0; - *CSR_TIMER1_LOAD = timer1_latch; - *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD | TIMER_CNTL_DIV16; + clockevents_calc_mult_shift(ce, mem_fclk_21285, 5); + ce->max_delta_ns = clockevent_delta2ns(0xffffff, ce); + ce->min_delta_ns = clockevent_delta2ns(0x000004, ce); - setup_irq(IRQ_TIMER1, &footbridge_timer_irq); + clockevents_register_device(ce); } struct sys_timer footbridge_timer = { .init = footbridge_timer_init, - .offset = timer1_gettimeoffset, }; diff --git a/arch/arm/mach-footbridge/include/mach/hardware.h b/arch/arm/mach-footbridge/include/mach/hardware.h index 51dd902043ad..b6fdf23ecf6c 100644 --- a/arch/arm/mach-footbridge/include/mach/hardware.h +++ b/arch/arm/mach-footbridge/include/mach/hardware.h @@ -23,26 +23,33 @@ * 0xf9000000 0x50000000 1MB Cache flush * 0xf0000000 0x80000000 16MB ISA memory */ + +#ifdef CONFIG_MMU +#define MMU_IO(a, b) (a) +#else +#define MMU_IO(a, b) (b) +#endif + #define XBUS_SIZE 0x00100000 -#define XBUS_BASE 0xff800000 +#define XBUS_BASE MMU_IO(0xff800000, 0x40000000) #define ARMCSR_SIZE 0x00100000 -#define ARMCSR_BASE 0xfe000000 +#define ARMCSR_BASE MMU_IO(0xfe000000, 0x42000000) #define WFLUSH_SIZE 0x00100000 -#define WFLUSH_BASE 0xfd000000 +#define WFLUSH_BASE MMU_IO(0xfd000000, 0x78000000) #define PCIIACK_SIZE 0x00100000 -#define PCIIACK_BASE 0xfc000000 +#define PCIIACK_BASE MMU_IO(0xfc000000, 0x79000000) #define PCICFG1_SIZE 0x01000000 -#define PCICFG1_BASE 0xfb000000 +#define PCICFG1_BASE MMU_IO(0xfb000000, 0x7a000000) #define PCICFG0_SIZE 0x01000000 -#define PCICFG0_BASE 0xfa000000 +#define PCICFG0_BASE MMU_IO(0xfa000000, 0x7b000000) #define PCIMEM_SIZE 0x01000000 -#define PCIMEM_BASE 0xf0000000 +#define PCIMEM_BASE MMU_IO(0xf0000000, 0x80000000) #define XBUS_LEDS ((volatile unsigned char *)(XBUS_BASE + 0x12000)) #define XBUS_LED_AMBER (1 << 0) diff --git a/arch/arm/mach-footbridge/include/mach/io.h b/arch/arm/mach-footbridge/include/mach/io.h index 101a4fe90bde..32e4cc397c28 100644 --- a/arch/arm/mach-footbridge/include/mach/io.h +++ b/arch/arm/mach-footbridge/include/mach/io.h @@ -14,8 +14,14 @@ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H -#define PCIO_SIZE 0x00100000 -#define PCIO_BASE 0xff000000 +#ifdef CONFIG_MMU +#define MMU_IO(a, b) (a) +#else +#define MMU_IO(a, b) (b) +#endif + +#define PCIO_SIZE 0x00100000 +#define PCIO_BASE MMU_IO(0xff000000, 0x7c000000) #define IO_SPACE_LIMIT 0xffff diff --git a/arch/arm/mach-footbridge/include/mach/memory.h b/arch/arm/mach-footbridge/include/mach/memory.h index 8d64f4574087..5c6df377f969 100644 --- a/arch/arm/mach-footbridge/include/mach/memory.h +++ b/arch/arm/mach-footbridge/include/mach/memory.h @@ -62,7 +62,7 @@ extern unsigned long __bus_to_pfn(unsigned long); /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #define FLUSH_BASE_PHYS 0x50000000 diff --git a/arch/arm/mach-footbridge/isa-timer.c b/arch/arm/mach-footbridge/isa-timer.c index f488fa2082d7..441c6ce0d555 100644 --- a/arch/arm/mach-footbridge/isa-timer.c +++ b/arch/arm/mach-footbridge/isa-timer.c @@ -4,10 +4,13 @@ * Copyright (C) 1998 Russell King. * Copyright (C) 1998 Phil Blundell */ +#include <linux/clockchips.h> +#include <linux/clocksource.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/io.h> +#include <linux/timex.h> #include <asm/irq.h> @@ -15,77 +18,115 @@ #include "common.h" -/* - * ISA timer tick support - */ -#define mSEC_10_from_14 ((14318180 + 100) / 200) +#define PIT_MODE 0x43 +#define PIT_CH0 0x40 + +#define PIT_LATCH ((PIT_TICK_RATE + HZ / 2) / HZ) -static unsigned long isa_gettimeoffset(void) +static cycle_t pit_read(struct clocksource *cs) { + unsigned long flags; + static int old_count; + static u32 old_jifs; int count; + u32 jifs; - static int count_p = (mSEC_10_from_14/6); /* for the first call after boot */ - static unsigned long jiffies_p = 0; + raw_local_irq_save(flags); - /* - * cache volatile jiffies temporarily; we have IRQs turned off. - */ - unsigned long jiffies_t; + jifs = jiffies; + outb_p(0x00, PIT_MODE); /* latch the count */ + count = inb_p(PIT_CH0); /* read the latched count */ + count |= inb_p(PIT_CH0) << 8; - /* timer count may underflow right here */ - outb_p(0x00, 0x43); /* latch the count ASAP */ + if (count > old_count && jifs == old_jifs) + count = old_count; - count = inb_p(0x40); /* read the latched count */ + old_count = count; + old_jifs = jifs; - /* - * We do this guaranteed double memory access instead of a _p - * postfix in the previous port access. Wheee, hackady hack - */ - jiffies_t = jiffies; + raw_local_irq_restore(flags); - count |= inb_p(0x40) << 8; + count = (PIT_LATCH - 1) - count; - /* Detect timer underflows. If we haven't had a timer tick since - the last time we were called, and time is apparently going - backwards, the counter must have wrapped during this routine. */ - if ((jiffies_t == jiffies_p) && (count > count_p)) - count -= (mSEC_10_from_14/6); - else - jiffies_p = jiffies_t; + return (cycle_t)(jifs * PIT_LATCH) + count; +} - count_p = count; +static struct clocksource pit_cs = { + .name = "pit", + .rating = 110, + .read = pit_read, + .mask = CLOCKSOURCE_MASK(32), +}; - count = (((mSEC_10_from_14/6)-1) - count) * (tick_nsec / 1000); - count = (count + (mSEC_10_from_14/6)/2) / (mSEC_10_from_14/6); +static void pit_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + unsigned long flags; + + raw_local_irq_save(flags); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + outb_p(0x34, PIT_MODE); + outb_p(PIT_LATCH & 0xff, PIT_CH0); + outb_p(PIT_LATCH >> 8, PIT_CH0); + break; + + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + outb_p(0x30, PIT_MODE); + outb_p(0, PIT_CH0); + outb_p(0, PIT_CH0); + break; + + case CLOCK_EVT_MODE_ONESHOT: + case CLOCK_EVT_MODE_RESUME: + break; + } + local_irq_restore(flags); +} - return count; +static int pit_set_next_event(unsigned long delta, + struct clock_event_device *evt) +{ + return 0; } -static irqreturn_t -isa_timer_interrupt(int irq, void *dev_id) +static struct clock_event_device pit_ce = { + .name = "pit", + .features = CLOCK_EVT_FEAT_PERIODIC, + .set_mode = pit_set_mode, + .set_next_event = pit_set_next_event, + .shift = 32, +}; + +static irqreturn_t pit_timer_interrupt(int irq, void *dev_id) { - timer_tick(); + struct clock_event_device *ce = dev_id; + ce->event_handler(ce); return IRQ_HANDLED; } -static struct irqaction isa_timer_irq = { - .name = "ISA timer tick", - .handler = isa_timer_interrupt, +static struct irqaction pit_timer_irq = { + .name = "pit", + .handler = pit_timer_interrupt, .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .dev_id = &pit_ce, }; static void __init isa_timer_init(void) { - /* enable PIT timer */ - /* set for periodic (4) and LSB/MSB write (0x30) */ - outb(0x34, 0x43); - outb((mSEC_10_from_14/6) & 0xFF, 0x40); - outb((mSEC_10_from_14/6) >> 8, 0x40); + pit_ce.cpumask = cpumask_of(smp_processor_id()); + pit_ce.mult = div_sc(PIT_TICK_RATE, NSEC_PER_SEC, pit_ce.shift); + pit_ce.max_delta_ns = clockevent_delta2ns(0x7fff, &pit_ce); + pit_ce.min_delta_ns = clockevent_delta2ns(0x000f, &pit_ce); + + clocksource_register_hz(&pit_cs, PIT_TICK_RATE); - setup_irq(IRQ_ISA_TIMER, &isa_timer_irq); + setup_irq(pit_ce.irq, &pit_timer_irq); + clockevents_register_device(&pit_ce); } struct sys_timer isa_timer = { .init = isa_timer_init, - .offset = isa_gettimeoffset, }; diff --git a/arch/arm/mach-gemini/board-nas4220b.c b/arch/arm/mach-gemini/board-nas4220b.c index 2ba096de0034..0cf7a07c3f3f 100644 --- a/arch/arm/mach-gemini/board-nas4220b.c +++ b/arch/arm/mach-gemini/board-nas4220b.c @@ -98,6 +98,7 @@ static void __init ib4220b_init(void) platform_register_pflash(SZ_16M, NULL, 0); platform_device_register(&ib4220b_led_device); platform_device_register(&ib4220b_key_device); + platform_register_rtc(); } MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B") diff --git a/arch/arm/mach-gemini/board-rut1xx.c b/arch/arm/mach-gemini/board-rut1xx.c index a9a0d8b01942..4fa09af99495 100644 --- a/arch/arm/mach-gemini/board-rut1xx.c +++ b/arch/arm/mach-gemini/board-rut1xx.c @@ -82,6 +82,7 @@ static void __init rut1xx_init(void) platform_register_pflash(SZ_8M, NULL, 0); platform_device_register(&rut1xx_leds); platform_device_register(&rut1xx_keys_device); + platform_register_rtc(); } MACHINE_START(RUT100, "Teltonika RUT100") diff --git a/arch/arm/mach-gemini/board-wbd111.c b/arch/arm/mach-gemini/board-wbd111.c index 8b88d50d4337..af7b68a6b258 100644 --- a/arch/arm/mach-gemini/board-wbd111.c +++ b/arch/arm/mach-gemini/board-wbd111.c @@ -130,6 +130,7 @@ static void __init wbd111_init(void) wbd111_num_partitions); platform_device_register(&wbd111_leds_device); platform_device_register(&wbd111_keys_device); + platform_register_rtc(); } MACHINE_START(WBD111, "Wiliboard WBD-111") diff --git a/arch/arm/mach-gemini/board-wbd222.c b/arch/arm/mach-gemini/board-wbd222.c index 1eebcecd1c33..99e5bbecf923 100644 --- a/arch/arm/mach-gemini/board-wbd222.c +++ b/arch/arm/mach-gemini/board-wbd222.c @@ -130,6 +130,7 @@ static void __init wbd222_init(void) wbd222_num_partitions); platform_device_register(&wbd222_leds_device); platform_device_register(&wbd222_keys_device); + platform_register_rtc(); } MACHINE_START(WBD222, "Wiliboard WBD-222") diff --git a/arch/arm/mach-gemini/common.h b/arch/arm/mach-gemini/common.h index 9392834a214f..7670c39acb2f 100644 --- a/arch/arm/mach-gemini/common.h +++ b/arch/arm/mach-gemini/common.h @@ -18,6 +18,7 @@ extern void gemini_map_io(void); extern void gemini_init_irq(void); extern void gemini_timer_init(void); extern void gemini_gpio_init(void); +extern void platform_register_rtc(void); /* Common platform devices registration functions */ extern int platform_register_uart(void); diff --git a/arch/arm/mach-gemini/devices.c b/arch/arm/mach-gemini/devices.c index 6b525253d027..5cff29818b73 100644 --- a/arch/arm/mach-gemini/devices.c +++ b/arch/arm/mach-gemini/devices.c @@ -90,3 +90,29 @@ int platform_register_pflash(unsigned int size, struct mtd_partition *parts, return platform_device_register(&pflash_device); } + +static struct resource gemini_rtc_resources[] = { + [0] = { + .start = GEMINI_RTC_BASE, + .end = GEMINI_RTC_BASE + 0x24, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_RTC, + .end = IRQ_RTC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device gemini_rtc_device = { + .name = "rtc-gemini", + .id = 0, + .num_resources = ARRAY_SIZE(gemini_rtc_resources), + .resource = gemini_rtc_resources, +}; + +int __init platform_register_rtc(void) +{ + return platform_device_register(&gemini_rtc_device); +} + diff --git a/arch/arm/mach-gemini/include/mach/memory.h b/arch/arm/mach-gemini/include/mach/memory.h index 2d14d5bf1f9f..a50915f764d8 100644 --- a/arch/arm/mach-gemini/include/mach/memory.h +++ b/arch/arm/mach-gemini/include/mach/memory.h @@ -11,9 +11,9 @@ #define __MACH_MEMORY_H #ifdef CONFIG_GEMINI_MEM_SWAP -# define PHYS_OFFSET UL(0x00000000) +# define PLAT_PHYS_OFFSET UL(0x00000000) #else -# define PHYS_OFFSET UL(0x10000000) +# define PLAT_PHYS_OFFSET UL(0x10000000) #endif #endif /* __MACH_MEMORY_H */ diff --git a/arch/arm/mach-h720x/include/mach/memory.h b/arch/arm/mach-h720x/include/mach/memory.h index ef4c1e26f18e..9d3687651462 100644 --- a/arch/arm/mach-h720x/include/mach/memory.h +++ b/arch/arm/mach-h720x/include/mach/memory.h @@ -7,7 +7,7 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x40000000) +#define PLAT_PHYS_OFFSET UL(0x40000000) /* * This is the maximum DMA address that can be DMAd to. * There should not be more than (0xd0000000 - 0xc0000000) diff --git a/arch/arm/mach-integrator/include/mach/memory.h b/arch/arm/mach-integrator/include/mach/memory.h index 991f24d2c115..334d5e271889 100644 --- a/arch/arm/mach-integrator/include/mach/memory.h +++ b/arch/arm/mach-integrator/include/mach/memory.h @@ -23,7 +23,7 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #define BUS_OFFSET UL(0x80000000) #define __virt_to_bus(x) ((x) - PAGE_OFFSET + BUS_OFFSET) diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h index 3ad455318868..1afa99ef97fa 100644 --- a/arch/arm/mach-iop13xx/include/mach/memory.h +++ b/arch/arm/mach-iop13xx/include/mach/memory.h @@ -6,7 +6,7 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #ifndef __ASSEMBLY__ diff --git a/arch/arm/mach-iop32x/include/mach/memory.h b/arch/arm/mach-iop32x/include/mach/memory.h index c30f6450ad50..169cc239f76c 100644 --- a/arch/arm/mach-iop32x/include/mach/memory.h +++ b/arch/arm/mach-iop32x/include/mach/memory.h @@ -8,6 +8,6 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0xa0000000) +#define PLAT_PHYS_OFFSET UL(0xa0000000) #endif diff --git a/arch/arm/mach-iop33x/include/mach/memory.h b/arch/arm/mach-iop33x/include/mach/memory.h index a30a96aa6d2d..8e1daf7006b6 100644 --- a/arch/arm/mach-iop33x/include/mach/memory.h +++ b/arch/arm/mach-iop33x/include/mach/memory.h @@ -8,6 +8,6 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif diff --git a/arch/arm/mach-ixp2000/include/mach/memory.h b/arch/arm/mach-ixp2000/include/mach/memory.h index 98e3471be15b..5f0c4fd4076a 100644 --- a/arch/arm/mach-ixp2000/include/mach/memory.h +++ b/arch/arm/mach-ixp2000/include/mach/memory.h @@ -13,7 +13,7 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #include <mach/ixp2000-regs.h> diff --git a/arch/arm/mach-ixp23xx/include/mach/memory.h b/arch/arm/mach-ixp23xx/include/mach/memory.h index 6ef65d813f16..6cf0704e946a 100644 --- a/arch/arm/mach-ixp23xx/include/mach/memory.h +++ b/arch/arm/mach-ixp23xx/include/mach/memory.h @@ -17,7 +17,7 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET (0x00000000) +#define PLAT_PHYS_OFFSET (0x00000000) #define IXP23XX_PCI_SDRAM_OFFSET (*((volatile int *)IXP23XX_PCI_SDRAM_BAR) & 0xfffffff0) diff --git a/arch/arm/mach-ixp4xx/include/mach/memory.h b/arch/arm/mach-ixp4xx/include/mach/memory.h index 0136eaa29224..6d388c9d0e20 100644 --- a/arch/arm/mach-ixp4xx/include/mach/memory.h +++ b/arch/arm/mach-ixp4xx/include/mach/memory.h @@ -12,7 +12,7 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #if !defined(__ASSEMBLY__) && defined(CONFIG_PCI) diff --git a/arch/arm/mach-kirkwood/include/mach/memory.h b/arch/arm/mach-kirkwood/include/mach/memory.h index 45431e131465..4600b44e3ad3 100644 --- a/arch/arm/mach-kirkwood/include/mach/memory.h +++ b/arch/arm/mach-kirkwood/include/mach/memory.h @@ -5,6 +5,6 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif diff --git a/arch/arm/mach-ks8695/include/mach/memory.h b/arch/arm/mach-ks8695/include/mach/memory.h index bace9a681adc..f7e1b9bce345 100644 --- a/arch/arm/mach-ks8695/include/mach/memory.h +++ b/arch/arm/mach-ks8695/include/mach/memory.h @@ -18,7 +18,7 @@ /* * Physical SRAM offset. */ -#define PHYS_OFFSET KS8695_SDRAM_PA +#define PLAT_PHYS_OFFSET KS8695_SDRAM_PA #ifndef __ASSEMBLY__ diff --git a/arch/arm/mach-lh7a40x/Kconfig b/arch/arm/mach-lh7a40x/Kconfig deleted file mode 100644 index 9be7466e346c..000000000000 --- a/arch/arm/mach-lh7a40x/Kconfig +++ /dev/null @@ -1,74 +0,0 @@ -if ARCH_LH7A40X - -menu "LH7A40X Implementations" - -config MACH_KEV7A400 - bool "KEV7A400" - select ARCH_LH7A400 - help - Say Y here if you are using the Sharp KEV7A400 development - board. This hardware is discontinued, so I'd be very - surprised if you wanted this option. - -config MACH_LPD7A400 - bool "LPD7A400 Card Engine" - select ARCH_LH7A400 -# select IDE_POLL -# select HAS_TOUCHSCREEN_ADS7843_LH7 - help - Say Y here if you are using Logic Product Development's - LPD7A400 CardEngine. For the time being, the LPD7A400 and - LPD7A404 options are mutually exclusive. - -config MACH_LPD7A404 - bool "LPD7A404 Card Engine" - select ARCH_LH7A404 -# select IDE_POLL -# select HAS_TOUCHSCREEN_ADC_LH7 - help - Say Y here if you are using Logic Product Development's - LPD7A404 CardEngine. For the time being, the LPD7A400 and - LPD7A404 options are mutually exclusive. - -config ARCH_LH7A400 - bool - -config ARCH_LH7A404 - bool - -config LPD7A40X_CPLD_SSP - bool - -config LH7A40X_CONTIGMEM - bool "Disable NUMA/SparseMEM Support" - help - Say Y here if your bootloader sets the SROMLL bit(s) in - the SDRAM controller, organizing memory as a contiguous - array. This option will disable sparse memory support - and force the kernel to manage all memory in one node. - - Setting this option incorrectly may prevent the kernel - from booting. It is OK to leave it N. - - For more information, consult - <file:Documentation/arm/Sharp-LH/SDRAM>. - -config LH7A40X_ONE_BANK_PER_NODE - bool "Optimize NUMA Node Tables for Size" - depends on !LH7A40X_CONTIGMEM - help - Say Y here to produce compact memory node tables. By - default pairs of adjacent physical RAM banks are managed - together in a single node, incurring some wasted overhead - in the node tables, however also maintaining compatibility - with systems where physical memory is truly contiguous. - - Setting this option incorrectly may prevent the kernel from - booting. It is OK to leave it N. - - For more information, consult - <file:Documentation/arm/Sharp-LH/SDRAM>. - -endmenu - -endif diff --git a/arch/arm/mach-lh7a40x/Makefile b/arch/arm/mach-lh7a40x/Makefile deleted file mode 100644 index 94b8615fb3c3..000000000000 --- a/arch/arm/mach-lh7a40x/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# -# Makefile for the linux kernel. -# - -# Object file lists. - -obj-y := time.o clocks.o -obj-m := -obj-n := -obj- := - -obj-$(CONFIG_MACH_KEV7A400) += arch-kev7a400.o irq-lh7a400.o -obj-$(CONFIG_MACH_LPD7A400) += arch-lpd7a40x.o irq-lh7a400.o -obj-$(CONFIG_MACH_LPD7A404) += arch-lpd7a40x.o irq-lh7a404.o -obj-$(CONFIG_LPD7A40X_CPLD_SSP) += ssp-cpld.o -obj-$(CONFIG_FB_ARMCLCD) += clcd.o - diff --git a/arch/arm/mach-lh7a40x/Makefile.boot b/arch/arm/mach-lh7a40x/Makefile.boot deleted file mode 100644 index af941be076eb..000000000000 --- a/arch/arm/mach-lh7a40x/Makefile.boot +++ /dev/null @@ -1,4 +0,0 @@ - zreladdr-y := 0xc0008000 -params_phys-y := 0xc0000100 -initrd_phys-y := 0xc4000000 - diff --git a/arch/arm/mach-lh7a40x/arch-kev7a400.c b/arch/arm/mach-lh7a40x/arch-kev7a400.c deleted file mode 100644 index 71129c33c7d2..000000000000 --- a/arch/arm/mach-lh7a40x/arch-kev7a400.c +++ /dev/null @@ -1,118 +0,0 @@ -/* arch/arm/mach-lh7a40x/arch-kev7a400.c - * - * Copyright (C) 2004 Logic Product Development - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ - -#include <linux/tty.h> -#include <linux/init.h> -#include <linux/device.h> -#include <linux/interrupt.h> - -#include <mach/hardware.h> -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/irq.h> -#include <asm/mach/irq.h> -#include <asm/mach/map.h> - -#include "common.h" - - /* This function calls the board specific IRQ initialization function. */ - -static struct map_desc kev7a400_io_desc[] __initdata = { - { - .virtual = IO_VIRT, - .pfn = __phys_to_pfn(IO_PHYS), - .length = IO_SIZE, - .type = MT_DEVICE - }, { - .virtual = CPLD_VIRT, - .pfn = __phys_to_pfn(CPLD_PHYS), - .length = CPLD_SIZE, - .type = MT_DEVICE - } -}; - -void __init kev7a400_map_io(void) -{ - iotable_init (kev7a400_io_desc, ARRAY_SIZE (kev7a400_io_desc)); -} - -static u16 CPLD_IRQ_mask; /* Mask for CPLD IRQs, 1 == unmasked */ - -static void kev7a400_ack_cpld_irq(struct irq_data *d) -{ - CPLD_CL_INT = 1 << (d->irq - IRQ_KEV7A400_CPLD); -} - -static void kev7a400_mask_cpld_irq(struct irq_data *d) -{ - CPLD_IRQ_mask &= ~(1 << (d->irq - IRQ_KEV7A400_CPLD)); - CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask; -} - -static void kev7a400_unmask_cpld_irq(struct irq_data *d) -{ - CPLD_IRQ_mask |= 1 << (d->irq - IRQ_KEV7A400_CPLD); - CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask; -} - -static struct irq_chip kev7a400_cpld_chip = { - .name = "CPLD", - .irq_ack = kev7a400_ack_cpld_irq, - .irq_mask = kev7a400_mask_cpld_irq, - .irq_unmask = kev7a400_unmask_cpld_irq, -}; - - -static void kev7a400_cpld_handler (unsigned int irq, struct irq_desc *desc) -{ - u32 mask = CPLD_LATCHED_INTS; - irq = IRQ_KEV7A400_CPLD; - for (; mask; mask >>= 1, ++irq) - if (mask & 1) - generic_handle_irq(irq); -} - -void __init lh7a40x_init_board_irq (void) -{ - int irq; - - for (irq = IRQ_KEV7A400_CPLD; - irq < IRQ_KEV7A400_CPLD + NR_IRQ_BOARD; ++irq) { - set_irq_chip (irq, &kev7a400_cpld_chip); - set_irq_handler (irq, handle_edge_irq); - set_irq_flags (irq, IRQF_VALID); - } - set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler); - - /* Clear all CPLD interrupts */ - CPLD_CL_INT = 0xff; /* CPLD_INTR_MMC_CD | CPLD_INTR_ETH_INT; */ - - GPIO_GPIOINTEN = 0; /* Disable all GPIO interrupts */ - barrier(); - -#if 0 - GPIO_INTTYPE1 - = (GPIO_INTR_PCC1_CD | GPIO_INTR_PCC1_CD); /* Edge trig. */ - GPIO_INTTYPE2 = 0; /* Falling edge & low-level */ - GPIO_GPIOFEOI = 0xff; /* Clear all GPIO interrupts */ - GPIO_GPIOINTEN = 0xff; /* Enable all GPIO interrupts */ - - init_FIQ(); -#endif -} - -MACHINE_START (KEV7A400, "Sharp KEV7a400") - /* Maintainer: Marc Singer */ - .boot_params = 0xc0000100, - .map_io = kev7a400_map_io, - .init_irq = lh7a400_init_irq, - .timer = &lh7a40x_timer, -MACHINE_END diff --git a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c deleted file mode 100644 index e735546181ad..000000000000 --- a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c +++ /dev/null @@ -1,422 +0,0 @@ -/* arch/arm/mach-lh7a40x/arch-lpd7a40x.c - * - * Copyright (C) 2004 Logic Product Development - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ - -#include <linux/tty.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/interrupt.h> -#include <linux/irq.h> - -#include <mach/hardware.h> -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/irq.h> -#include <asm/mach/irq.h> -#include <asm/mach/map.h> - -#include "common.h" - -#define CPLD_INT_NETHERNET (1<<0) -#define CPLD_INTMASK_ETHERNET (1<<2) -#if defined (CONFIG_MACH_LPD7A400) -# define CPLD_INT_NTOUCH (1<<1) -# define CPLD_INTMASK_TOUCH (1<<3) -# define CPLD_INT_PEN (1<<4) -# define CPLD_INTMASK_PEN (1<<4) -# define CPLD_INT_PIRQ (1<<4) -#endif -#define CPLD_INTMASK_CPLD (1<<7) -#define CPLD_INT_CPLD (1<<6) - -#define CPLD_CONTROL_SWINT (1<<7) /* Disable all CPLD IRQs */ -#define CPLD_CONTROL_OCMSK (1<<6) /* Mask USB1 connect IRQ */ -#define CPLD_CONTROL_PDRV (1<<5) /* PCC_nDRV high */ -#define CPLD_CONTROL_USB1C (1<<4) /* USB1 connect IRQ active */ -#define CPLD_CONTROL_USB1P (1<<3) /* USB1 power disable */ -#define CPLD_CONTROL_AWKP (1<<2) /* Auto-wakeup disabled */ -#define CPLD_CONTROL_LCD_ENABLE (1<<1) /* LCD Vee enable */ -#define CPLD_CONTROL_WRLAN_NENABLE (1<<0) /* SMC91x power disable */ - - -static struct resource smc91x_resources[] = { - [0] = { - .start = CPLD00_PHYS, - .end = CPLD00_PHYS + CPLD00_SIZE - 1, /* Only needs 16B */ - .flags = IORESOURCE_MEM, - }, - - [1] = { - .start = IRQ_LPD7A40X_ETH_INT, - .end = IRQ_LPD7A40X_ETH_INT, - .flags = IORESOURCE_IRQ, - }, - -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, -}; - -static struct resource lh7a40x_usbclient_resources[] = { - [0] = { - .start = USB_PHYS, - .end = (USB_PHYS + PAGE_SIZE), - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_USB, - .end = IRQ_USB, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 lh7a40x_usbclient_dma_mask = 0xffffffffUL; - -static struct platform_device lh7a40x_usbclient_device = { -// .name = "lh7a40x_udc", - .name = "lh7-udc", - .id = 0, - .dev = { - .dma_mask = &lh7a40x_usbclient_dma_mask, - .coherent_dma_mask = 0xffffffffUL, - }, - .num_resources = ARRAY_SIZE (lh7a40x_usbclient_resources), - .resource = lh7a40x_usbclient_resources, -}; - -#if defined (CONFIG_ARCH_LH7A404) - -static struct resource lh7a404_usbhost_resources [] = { - [0] = { - .start = USBH_PHYS, - .end = (USBH_PHYS + 0xFF), - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_USHINTR, - .end = IRQ_USHINTR, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 lh7a404_usbhost_dma_mask = 0xffffffffUL; - -static struct platform_device lh7a404_usbhost_device = { - .name = "lh7a404-ohci", - .id = 0, - .dev = { - .dma_mask = &lh7a404_usbhost_dma_mask, - .coherent_dma_mask = 0xffffffffUL, - }, - .num_resources = ARRAY_SIZE (lh7a404_usbhost_resources), - .resource = lh7a404_usbhost_resources, -}; - -#endif - -static struct platform_device* lpd7a40x_devs[] __initdata = { - &smc91x_device, - &lh7a40x_usbclient_device, -#if defined (CONFIG_ARCH_LH7A404) - &lh7a404_usbhost_device, -#endif -}; - -extern void lpd7a400_map_io (void); - -static void __init lpd7a40x_init (void) -{ -#if defined (CONFIG_MACH_LPD7A400) - CPLD_CONTROL |= 0 - | CPLD_CONTROL_SWINT /* Disable software interrupt */ - | CPLD_CONTROL_OCMSK; /* Mask USB1 connection IRQ */ - CPLD_CONTROL &= ~(0 - | CPLD_CONTROL_LCD_ENABLE /* Disable LCD */ - | CPLD_CONTROL_WRLAN_NENABLE /* Enable SMC91x */ - ); -#endif - -#if defined (CONFIG_MACH_LPD7A404) - CPLD_CONTROL &= ~(0 - | CPLD_CONTROL_WRLAN_NENABLE /* Enable SMC91x */ - ); -#endif - - platform_add_devices (lpd7a40x_devs, ARRAY_SIZE (lpd7a40x_devs)); -#if defined (CONFIG_FB_ARMCLCD) - lh7a40x_clcd_init (); -#endif -} - -static void lh7a40x_ack_cpld_irq(struct irq_data *d) -{ - /* CPLD doesn't have ack capability, but some devices may */ - -#if defined (CPLD_INTMASK_TOUCH) - /* The touch control *must* mask the interrupt because the - * interrupt bit is read by the driver to determine if the pen - * is still down. */ - if (d->irq == IRQ_TOUCH) - CPLD_INTERRUPTS |= CPLD_INTMASK_TOUCH; -#endif -} - -static void lh7a40x_mask_cpld_irq(struct irq_data *d) -{ - switch (d->irq) { - case IRQ_LPD7A40X_ETH_INT: - CPLD_INTERRUPTS |= CPLD_INTMASK_ETHERNET; - break; -#if defined (IRQ_TOUCH) - case IRQ_TOUCH: - CPLD_INTERRUPTS |= CPLD_INTMASK_TOUCH; - break; -#endif - } -} - -static void lh7a40x_unmask_cpld_irq(struct irq_data *d) -{ - switch (d->irq) { - case IRQ_LPD7A40X_ETH_INT: - CPLD_INTERRUPTS &= ~CPLD_INTMASK_ETHERNET; - break; -#if defined (IRQ_TOUCH) - case IRQ_TOUCH: - CPLD_INTERRUPTS &= ~CPLD_INTMASK_TOUCH; - break; -#endif - } -} - -static struct irq_chip lpd7a40x_cpld_chip = { - .name = "CPLD", - .irq_ack = lh7a40x_ack_cpld_irq, - .irq_mask = lh7a40x_mask_cpld_irq, - .irq_unmask = lh7a40x_unmask_cpld_irq, -}; - -static void lpd7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc) -{ - unsigned int mask = CPLD_INTERRUPTS; - - desc->irq_data.chip->irq_ack(&desc->irq_data); - - if ((mask & (1<<0)) == 0) /* WLAN */ - generic_handle_irq(IRQ_LPD7A40X_ETH_INT); - -#if defined (IRQ_TOUCH) - if ((mask & (1<<1)) == 0) /* Touch */ - generic_handle_irq(IRQ_TOUCH); -#endif - - /* Level-triggered need this */ - desc->irq_data.chip->irq_unmask(&desc->irq_data); -} - - -void __init lh7a40x_init_board_irq (void) -{ - int irq; - - /* Rev A (v2.8): PF0, PF1, PF2, and PF3 are available IRQs. - PF7 supports the CPLD. - Rev B (v3.4): PF0, PF1, and PF2 are available IRQs. - PF3 supports the CPLD. - (Some) LPD7A404 prerelease boards report a version - number of 0x16, but we force an override since the - hardware is of the newer variety. - */ - - unsigned char cpld_version = CPLD_REVISION; - int pinCPLD = (cpld_version == 0x28) ? 7 : 3; - -#if defined CONFIG_MACH_LPD7A404 - cpld_version = 0x34; /* Coerce LPD7A404 to RevB */ -#endif - - /* First, configure user controlled GPIOF interrupts */ - - GPIO_PFDD &= ~0x0f; /* PF0-3 are inputs */ - GPIO_INTTYPE1 &= ~0x0f; /* PF0-3 are level triggered */ - GPIO_INTTYPE2 &= ~0x0f; /* PF0-3 are active low */ - barrier (); - GPIO_GPIOFINTEN |= 0x0f; /* Enable PF0, PF1, PF2, and PF3 IRQs */ - - /* Then, configure CPLD interrupt */ - - /* Disable all CPLD interrupts */ -#if defined (CONFIG_MACH_LPD7A400) - CPLD_INTERRUPTS = CPLD_INTMASK_TOUCH | CPLD_INTMASK_PEN - | CPLD_INTMASK_ETHERNET; - /* *** FIXME: don't know why we need 7 and 4. 7 is way wrong - and 4 is uncefined. */ - // (1<<7)|(1<<4)|(1<<3)|(1<<2); -#endif -#if defined (CONFIG_MACH_LPD7A404) - CPLD_INTERRUPTS = CPLD_INTMASK_ETHERNET; - /* *** FIXME: don't know why we need 6 and 5, neither is defined. */ - // (1<<6)|(1<<5)|(1<<3); -#endif - GPIO_PFDD &= ~(1 << pinCPLD); /* Make input */ - GPIO_INTTYPE1 &= ~(1 << pinCPLD); /* Level triggered */ - GPIO_INTTYPE2 &= ~(1 << pinCPLD); /* Active low */ - barrier (); - GPIO_GPIOFINTEN |= (1 << pinCPLD); /* Enable */ - - /* Cascade CPLD interrupts */ - - for (irq = IRQ_BOARD_START; - irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) { - set_irq_chip (irq, &lpd7a40x_cpld_chip); - set_irq_handler (irq, handle_level_irq); - set_irq_flags (irq, IRQF_VALID); - } - - set_irq_chained_handler ((cpld_version == 0x28) - ? IRQ_CPLD_V28 - : IRQ_CPLD_V34, - lpd7a40x_cpld_handler); -} - -static struct map_desc lpd7a40x_io_desc[] __initdata = { - { - .virtual = IO_VIRT, - .pfn = __phys_to_pfn(IO_PHYS), - .length = IO_SIZE, - .type = MT_DEVICE - }, - { /* Mapping added to work around chip select problems */ - .virtual = IOBARRIER_VIRT, - .pfn = __phys_to_pfn(IOBARRIER_PHYS), - .length = IOBARRIER_SIZE, - .type = MT_DEVICE - }, - { - .virtual = CF_VIRT, - .pfn = __phys_to_pfn(CF_PHYS), - .length = CF_SIZE, - .type = MT_DEVICE - }, - { - .virtual = CPLD02_VIRT, - .pfn = __phys_to_pfn(CPLD02_PHYS), - .length = CPLD02_SIZE, - .type = MT_DEVICE - }, - { - .virtual = CPLD06_VIRT, - .pfn = __phys_to_pfn(CPLD06_PHYS), - .length = CPLD06_SIZE, - .type = MT_DEVICE - }, - { - .virtual = CPLD08_VIRT, - .pfn = __phys_to_pfn(CPLD08_PHYS), - .length = CPLD08_SIZE, - .type = MT_DEVICE - }, - { - .virtual = CPLD08_VIRT, - .pfn = __phys_to_pfn(CPLD08_PHYS), - .length = CPLD08_SIZE, - .type = MT_DEVICE - }, - { - .virtual = CPLD0A_VIRT, - .pfn = __phys_to_pfn(CPLD0A_PHYS), - .length = CPLD0A_SIZE, - .type = MT_DEVICE - }, - { - .virtual = CPLD0C_VIRT, - .pfn = __phys_to_pfn(CPLD0C_PHYS), - .length = CPLD0C_SIZE, - .type = MT_DEVICE - }, - { - .virtual = CPLD0E_VIRT, - .pfn = __phys_to_pfn(CPLD0E_PHYS), - .length = CPLD0E_SIZE, - .type = MT_DEVICE - }, - { - .virtual = CPLD10_VIRT, - .pfn = __phys_to_pfn(CPLD10_PHYS), - .length = CPLD10_SIZE, - .type = MT_DEVICE - }, - { - .virtual = CPLD12_VIRT, - .pfn = __phys_to_pfn(CPLD12_PHYS), - .length = CPLD12_SIZE, - .type = MT_DEVICE - }, - { - .virtual = CPLD14_VIRT, - .pfn = __phys_to_pfn(CPLD14_PHYS), - .length = CPLD14_SIZE, - .type = MT_DEVICE - }, - { - .virtual = CPLD16_VIRT, - .pfn = __phys_to_pfn(CPLD16_PHYS), - .length = CPLD16_SIZE, - .type = MT_DEVICE - }, - { - .virtual = CPLD18_VIRT, - .pfn = __phys_to_pfn(CPLD18_PHYS), - .length = CPLD18_SIZE, - .type = MT_DEVICE - }, - { - .virtual = CPLD1A_VIRT, - .pfn = __phys_to_pfn(CPLD1A_PHYS), - .length = CPLD1A_SIZE, - .type = MT_DEVICE - }, -}; - -void __init -lpd7a40x_map_io(void) -{ - iotable_init (lpd7a40x_io_desc, ARRAY_SIZE (lpd7a40x_io_desc)); -} - -#ifdef CONFIG_MACH_LPD7A400 - -MACHINE_START (LPD7A400, "Logic Product Development LPD7A400-10") - /* Maintainer: Marc Singer */ - .boot_params = 0xc0000100, - .map_io = lpd7a40x_map_io, - .init_irq = lh7a400_init_irq, - .timer = &lh7a40x_timer, - .init_machine = lpd7a40x_init, -MACHINE_END - -#endif - -#ifdef CONFIG_MACH_LPD7A404 - -MACHINE_START (LPD7A404, "Logic Product Development LPD7A404-10") - /* Maintainer: Marc Singer */ - .boot_params = 0xc0000100, - .map_io = lpd7a40x_map_io, - .init_irq = lh7a404_init_irq, - .timer = &lh7a40x_timer, - .init_machine = lpd7a40x_init, -MACHINE_END - -#endif diff --git a/arch/arm/mach-lh7a40x/clcd.c b/arch/arm/mach-lh7a40x/clcd.c deleted file mode 100644 index 7fe4fd347c82..000000000000 --- a/arch/arm/mach-lh7a40x/clcd.c +++ /dev/null @@ -1,241 +0,0 @@ -/* - * arch/arm/mach-lh7a40x/clcd.c - * - * Copyright (C) 2004 Marc Singer - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ - -#include <linux/init.h> -#include <linux/gfp.h> -#include <linux/device.h> -#include <linux/dma-mapping.h> -#include <linux/sysdev.h> -#include <linux/interrupt.h> - -//#include <linux/module.h> -//#include <linux/time.h> - -//#include <asm/mach/time.h> -#include <asm/irq.h> -#include <asm/mach/irq.h> - -#include <asm/system.h> -#include <mach/hardware.h> -#include <linux/amba/bus.h> -#include <linux/amba/clcd.h> - -#define HRTFTC_HRSETUP __REG(HRTFTC_PHYS + 0x00) -#define HRTFTC_HRCON __REG(HRTFTC_PHYS + 0x04) -#define HRTFTC_HRTIMING1 __REG(HRTFTC_PHYS + 0x08) -#define HRTFTC_HRTIMING2 __REG(HRTFTC_PHYS + 0x0c) - -#define ALI_SETUP __REG(ALI_PHYS + 0x00) -#define ALI_CONTROL __REG(ALI_PHYS + 0x04) -#define ALI_TIMING1 __REG(ALI_PHYS + 0x08) -#define ALI_TIMING2 __REG(ALI_PHYS + 0x0c) - -#include "lcd-panel.h" - -static void lh7a40x_clcd_disable (struct clcd_fb *fb) -{ -#if defined (CONFIG_MACH_LPD7A400) - CPLD_CONTROL &= ~(1<<1); /* Disable LCD Vee */ -#endif - -#if defined (CONFIG_MACH_LPD7A404) - GPIO_PCD &= ~(1<<3); /* Disable LCD Vee */ -#endif - -#if defined (CONFIG_ARCH_LH7A400) - HRTFTC_HRSETUP &= ~(1<<13); /* Disable HRTFT controller */ -#endif - -#if defined (CONFIG_ARCH_LH7A404) - ALI_SETUP &= ~(1<<13); /* Disable ALI */ -#endif -} - -static void lh7a40x_clcd_enable (struct clcd_fb *fb) -{ - struct clcd_panel_extra* extra - = (struct clcd_panel_extra*) fb->board_data; - -#if defined (CONFIG_MACH_LPD7A400) - CPLD_CONTROL |= (1<<1); /* Enable LCD Vee */ -#endif - -#if defined (CONFIG_MACH_LPD7A404) - GPIO_PCDD &= ~(1<<3); /* Enable LCD Vee */ - GPIO_PCD |= (1<<3); -#endif - -#if defined (CONFIG_ARCH_LH7A400) - - if (extra) { - HRTFTC_HRSETUP - = (1 << 13) - | ((fb->fb.var.xres - 1) << 4) - | 0xc - | (extra->hrmode ? 1 : 0); - HRTFTC_HRCON - = ((extra->clsen ? 1 : 0) << 1) - | ((extra->spsen ? 1 : 0) << 0); - HRTFTC_HRTIMING1 - = (extra->pcdel << 8) - | (extra->revdel << 4) - | (extra->lpdel << 0); - HRTFTC_HRTIMING2 - = (extra->spldel << 9) - | (extra->pc2del << 0); - } - else - HRTFTC_HRSETUP - = (1 << 13) - | 0xc; -#endif - -#if defined (CONFIG_ARCH_LH7A404) - - if (extra) { - ALI_SETUP - = (1 << 13) - | ((fb->fb.var.xres - 1) << 4) - | 0xc - | (extra->hrmode ? 1 : 0); - ALI_CONTROL - = ((extra->clsen ? 1 : 0) << 1) - | ((extra->spsen ? 1 : 0) << 0); - ALI_TIMING1 - = (extra->pcdel << 8) - | (extra->revdel << 4) - | (extra->lpdel << 0); - ALI_TIMING2 - = (extra->spldel << 9) - | (extra->pc2del << 0); - } - else - ALI_SETUP - = (1 << 13) - | 0xc; -#endif - -} - -#define FRAMESIZE(s) (((s) + PAGE_SIZE - 1)&PAGE_MASK) - -static int lh7a40x_clcd_setup (struct clcd_fb *fb) -{ - dma_addr_t dma; - u32 len = FRAMESIZE (lcd_panel.mode.xres*lcd_panel.mode.yres - *(lcd_panel.bpp/8)); - - fb->panel = &lcd_panel; - - /* Enforce the sync polarity defaults */ - if (!(fb->panel->tim2 & TIM2_IHS)) - fb->fb.var.sync |= FB_SYNC_HOR_HIGH_ACT; - if (!(fb->panel->tim2 & TIM2_IVS)) - fb->fb.var.sync |= FB_SYNC_VERT_HIGH_ACT; - -#if defined (HAS_LCD_PANEL_EXTRA) - fb->board_data = &lcd_panel_extra; -#endif - - fb->fb.screen_base - = dma_alloc_writecombine (&fb->dev->dev, len, - &dma, GFP_KERNEL); - printk ("CLCD: LCD setup fb virt 0x%p phys 0x%p l %x io 0x%p \n", - fb->fb.screen_base, (void*) dma, len, - (void*) io_p2v (CLCDC_PHYS)); - printk ("CLCD: pixclock %d\n", lcd_panel.mode.pixclock); - - if (!fb->fb.screen_base) { - printk(KERN_ERR "CLCD: unable to map framebuffer\n"); - return -ENOMEM; - } - -#if defined (USE_RGB555) - fb->fb.var.green.length = 5; /* Panel uses RGB 5:5:5 */ -#endif - - fb->fb.fix.smem_start = dma; - fb->fb.fix.smem_len = len; - - /* Drive PE4 high to prevent CPLD crash */ - GPIO_PEDD |= (1<<4); - GPIO_PED |= (1<<4); - - GPIO_PINMUX |= (1<<1) | (1<<0); /* LCDVD[15:4] */ - -// fb->fb.fbops->fb_check_var (&fb->fb.var, &fb->fb); -// fb->fb.fbops->fb_set_par (&fb->fb); - - return 0; -} - -static int lh7a40x_clcd_mmap (struct clcd_fb *fb, struct vm_area_struct *vma) -{ - return dma_mmap_writecombine(&fb->dev->dev, vma, - fb->fb.screen_base, - fb->fb.fix.smem_start, - fb->fb.fix.smem_len); -} - -static void lh7a40x_clcd_remove (struct clcd_fb *fb) -{ - dma_free_writecombine (&fb->dev->dev, fb->fb.fix.smem_len, - fb->fb.screen_base, fb->fb.fix.smem_start); -} - -static struct clcd_board clcd_platform_data = { - .name = "lh7a40x FB", - .check = clcdfb_check, - .decode = clcdfb_decode, - .enable = lh7a40x_clcd_enable, - .setup = lh7a40x_clcd_setup, - .mmap = lh7a40x_clcd_mmap, - .remove = lh7a40x_clcd_remove, - .disable = lh7a40x_clcd_disable, -}; - -#define IRQ_CLCDC (IRQ_LCDINTR) - -#define AMBA_DEVICE(name,busid,base,plat,pid) \ -static struct amba_device name##_device = { \ - .dev = { \ - .coherent_dma_mask = ~0, \ - .init_name = busid, \ - .platform_data = plat, \ - }, \ - .res = { \ - .start = base##_PHYS, \ - .end = (base##_PHYS) + (4*1024) - 1, \ - .flags = IORESOURCE_MEM, \ - }, \ - .dma_mask = ~0, \ - .irq = { IRQ_##base, }, \ - /* .dma = base##_DMA,*/ \ - .periphid = pid, \ -} - -AMBA_DEVICE(clcd, "cldc-lh7a40x", CLCDC, &clcd_platform_data, 0x41110); - -static struct amba_device *amba_devs[] __initdata = { - &clcd_device, -}; - -void __init lh7a40x_clcd_init (void) -{ - int i; - int result; - printk ("CLCD: registering amba devices\n"); - for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { - struct amba_device *d = amba_devs[i]; - result = amba_device_register(d, &iomem_resource); - printk (" %d -> %d\n", i ,result); - } -} diff --git a/arch/arm/mach-lh7a40x/clocks.c b/arch/arm/mach-lh7a40x/clocks.c deleted file mode 100644 index 0651f96653f9..000000000000 --- a/arch/arm/mach-lh7a40x/clocks.c +++ /dev/null @@ -1,108 +0,0 @@ -/* arch/arm/mach-lh7a40x/clocks.c - * - * Copyright (C) 2004 Marc Singer - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ -#include <mach/hardware.h> -#include <mach/clocks.h> -#include <linux/err.h> -#include <linux/device.h> -#include <linux/string.h> - -struct module; - -struct clk { - struct list_head node; - unsigned long rate; - struct module *owner; - const char *name; -}; - -/* ----- */ - -#define MAINDIV1(c) (((c) >> 7) & 0x0f) -#define MAINDIV2(c) (((c) >> 11) & 0x1f) -#define PS(c) (((c) >> 18) & 0x03) -#define PREDIV(c) (((c) >> 2) & 0x1f) -#define HCLKDIV(c) (((c) >> 0) & 0x02) -#define PCLKDIV(c) (((c) >> 16) & 0x03) - -unsigned int fclkfreq_get (void) -{ - unsigned int clkset = CSC_CLKSET; - unsigned int gclk - = XTAL_IN - / (1 << PS(clkset)) - * (MAINDIV1(clkset) + 2) - / (PREDIV(clkset) + 2) - * (MAINDIV2(clkset) + 2) - ; - return gclk; -} - -unsigned int hclkfreq_get (void) -{ - unsigned int clkset = CSC_CLKSET; - unsigned int hclk = fclkfreq_get () / (HCLKDIV(clkset) + 1); - - return hclk; -} - -unsigned int pclkfreq_get (void) -{ - unsigned int clkset = CSC_CLKSET; - int pclkdiv = PCLKDIV(clkset); - unsigned int pclk; - if (pclkdiv == 0x3) - pclkdiv = 0x2; - pclk = hclkfreq_get () / (1 << pclkdiv); - - return pclk; -} - -/* ----- */ - -struct clk *clk_get (struct device *dev, const char *id) -{ - return dev && strcmp(dev_name(dev), "cldc-lh7a40x") == 0 - ? NULL : ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -void clk_put (struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); - -int clk_enable (struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable (struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate (struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_get_rate); - -long clk_round_rate (struct clk *clk, unsigned long rate) -{ - return rate; -} -EXPORT_SYMBOL(clk_round_rate); - -int clk_set_rate (struct clk *clk, unsigned long rate) -{ - return -EIO; -} -EXPORT_SYMBOL(clk_set_rate); diff --git a/arch/arm/mach-lh7a40x/common.h b/arch/arm/mach-lh7a40x/common.h deleted file mode 100644 index 6ed3f6b6db76..000000000000 --- a/arch/arm/mach-lh7a40x/common.h +++ /dev/null @@ -1,17 +0,0 @@ -/* arch/arm/mach-lh7a40x/common.h - * - * Copyright (C) 2004 Marc Singer - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ - -extern struct sys_timer lh7a40x_timer; - -extern void lh7a400_init_irq (void); -extern void lh7a404_init_irq (void); -extern void lh7a40x_clcd_init (void); -extern void lh7a40x_init_board_irq (void); - diff --git a/arch/arm/mach-lh7a40x/include/mach/clocks.h b/arch/arm/mach-lh7a40x/include/mach/clocks.h deleted file mode 100644 index fe2e0255c084..000000000000 --- a/arch/arm/mach-lh7a40x/include/mach/clocks.h +++ /dev/null @@ -1,18 +0,0 @@ -/* arch/arm/mach-lh7a40x/include/mach/clocks.h - * - * Copyright (C) 2004 Marc Singer - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ - -#ifndef __ASM_ARCH_CLOCKS_H -#define __ASM_ARCH_CLOCKS_H - -unsigned int fclkfreq_get (void); -unsigned int hclkfreq_get (void); -unsigned int pclkfreq_get (void); - -#endif /* _ASM_ARCH_CLOCKS_H */ diff --git a/arch/arm/mach-lh7a40x/include/mach/constants.h b/arch/arm/mach-lh7a40x/include/mach/constants.h deleted file mode 100644 index 55c6edbc2dfd..000000000000 --- a/arch/arm/mach-lh7a40x/include/mach/constants.h +++ /dev/null @@ -1,91 +0,0 @@ -/* arch/arm/mach-lh7a40x/include/mach/constants.h - * - * Copyright (C) 2004 Coastal Environmental Systems - * Copyright (C) 2004 Logic Product Development - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ - -#ifndef __ASM_ARCH_CONSTANTS_H -#define __ASM_ARCH_CONSTANTS_H - - -/* Addressing constants */ - - /* SoC CPU IO addressing */ -#define IO_PHYS (0x80000000) -#define IO_VIRT (0xf8000000) -#define IO_SIZE (0x0000B000) - -#ifdef CONFIG_MACH_KEV7A400 -# define CPLD_PHYS (0x20000000) -# define CPLD_VIRT (0xf2000000) -# define CPLD_SIZE PAGE_SIZE -#endif - -#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) - -# define IOBARRIER_PHYS 0x10000000 /* Second bank, fastest timing */ -# define IOBARRIER_VIRT 0xf0000000 -# define IOBARRIER_SIZE PAGE_SIZE - -# define CF_PHYS 0x60200000 -# define CF_VIRT 0xf6020000 -# define CF_SIZE (8*1024) - - /* The IO mappings for the LPD CPLD are, unfortunately, sparse. */ -# define CPLDX_PHYS(x) (0x70000000 | ((x) << 20)) -# define CPLDX_VIRT(x) (0xf7000000 | ((x) << 16)) -# define CPLD00_PHYS CPLDX_PHYS (0x00) /* Wired LAN */ -# define CPLD00_VIRT CPLDX_VIRT (0x00) -# define CPLD00_SIZE PAGE_SIZE -# define CPLD02_PHYS CPLDX_PHYS (0x02) -# define CPLD02_VIRT CPLDX_VIRT (0x02) -# define CPLD02_SIZE PAGE_SIZE -# define CPLD06_PHYS CPLDX_PHYS (0x06) -# define CPLD06_VIRT CPLDX_VIRT (0x06) -# define CPLD06_SIZE PAGE_SIZE -# define CPLD08_PHYS CPLDX_PHYS (0x08) -# define CPLD08_VIRT CPLDX_VIRT (0x08) -# define CPLD08_SIZE PAGE_SIZE -# define CPLD0A_PHYS CPLDX_PHYS (0x0a) -# define CPLD0A_VIRT CPLDX_VIRT (0x0a) -# define CPLD0A_SIZE PAGE_SIZE -# define CPLD0C_PHYS CPLDX_PHYS (0x0c) -# define CPLD0C_VIRT CPLDX_VIRT (0x0c) -# define CPLD0C_SIZE PAGE_SIZE -# define CPLD0E_PHYS CPLDX_PHYS (0x0e) -# define CPLD0E_VIRT CPLDX_VIRT (0x0e) -# define CPLD0E_SIZE PAGE_SIZE -# define CPLD10_PHYS CPLDX_PHYS (0x10) -# define CPLD10_VIRT CPLDX_VIRT (0x10) -# define CPLD10_SIZE PAGE_SIZE -# define CPLD12_PHYS CPLDX_PHYS (0x12) -# define CPLD12_VIRT CPLDX_VIRT (0x12) -# define CPLD12_SIZE PAGE_SIZE -# define CPLD14_PHYS CPLDX_PHYS (0x14) -# define CPLD14_VIRT CPLDX_VIRT (0x14) -# define CPLD14_SIZE PAGE_SIZE -# define CPLD16_PHYS CPLDX_PHYS (0x16) -# define CPLD16_VIRT CPLDX_VIRT (0x16) -# define CPLD16_SIZE PAGE_SIZE -# define CPLD18_PHYS CPLDX_PHYS (0x18) -# define CPLD18_VIRT CPLDX_VIRT (0x18) -# define CPLD18_SIZE PAGE_SIZE -# define CPLD1A_PHYS CPLDX_PHYS (0x1a) -# define CPLD1A_VIRT CPLDX_VIRT (0x1a) -# define CPLD1A_SIZE PAGE_SIZE -#endif - - /* Timing constants */ - -#define XTAL_IN 14745600 /* 14.7456 MHz crystal */ -#define PLL_CLOCK (XTAL_IN * 21) /* 309 MHz PLL clock */ -#define MAX_HCLK_KHZ 100000 /* HCLK max limit ~100MHz */ -#define HCLK (99993600) -//#define HCLK (119808000) - -#endif /* __ASM_ARCH_CONSTANTS_H */ diff --git a/arch/arm/mach-lh7a40x/include/mach/debug-macro.S b/arch/arm/mach-lh7a40x/include/mach/debug-macro.S deleted file mode 100644 index cff33625276f..000000000000 --- a/arch/arm/mach-lh7a40x/include/mach/debug-macro.S +++ /dev/null @@ -1,37 +0,0 @@ -/* arch/arm/mach-lh7a40x/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - - @ It is not known if this will be appropriate for every 40x - @ board. - - .macro addruart, rp, rv - mov \rp, #0x00000700 @ offset from base - orr \rv, \rp, #0xf8000000 @ virtual base - orr \rp, \rp, #0x80000000 @ physical base - .endm - - .macro senduart,rd,rx - strb \rd, [\rx] @ DATA - .endm - - .macro busyuart,rd,rx @ spin while busy -1001: ldr \rd, [\rx, #0x10] @ STATUS - tst \rd, #1 << 3 @ BUSY (TX FIFO not empty) - bne 1001b @ yes, spin - .endm - - .macro waituart,rd,rx @ wait for Tx FIFO room -1001: ldrb \rd, [\rx, #0x10] @ STATUS - tst \rd, #1 << 5 @ TXFF (TX FIFO full) - bne 1001b @ yes, spin - .endm diff --git a/arch/arm/mach-lh7a40x/include/mach/dma.h b/arch/arm/mach-lh7a40x/include/mach/dma.h deleted file mode 100644 index baa3f8dbd04b..000000000000 --- a/arch/arm/mach-lh7a40x/include/mach/dma.h +++ /dev/null @@ -1,86 +0,0 @@ -/* arch/arm/mach-lh7a40x/include/mach/dma.h - * - * Copyright (C) 2005 Marc Singer - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ - -typedef enum { - DMA_M2M0 = 0, - DMA_M2M1 = 1, - DMA_M2P0 = 2, /* Tx */ - DMA_M2P1 = 3, /* Rx */ - DMA_M2P2 = 4, /* Tx */ - DMA_M2P3 = 5, /* Rx */ - DMA_M2P4 = 6, /* Tx - AC97 */ - DMA_M2P5 = 7, /* Rx - AC97 */ - DMA_M2P6 = 8, /* Tx */ - DMA_M2P7 = 9, /* Rx */ -} dma_device_t; - -#define DMA_LENGTH_MAX ((64*1024) - 4) /* bytes */ - -#define DMAC_GCA __REG(DMAC_PHYS + 0x2b80) -#define DMAC_GIR __REG(DMAC_PHYS + 0x2bc0) - -#define DMAC_GIR_MMI1 (1<<11) -#define DMAC_GIR_MMI0 (1<<10) -#define DMAC_GIR_MPI8 (1<<9) -#define DMAC_GIR_MPI9 (1<<8) -#define DMAC_GIR_MPI6 (1<<7) -#define DMAC_GIR_MPI7 (1<<6) -#define DMAC_GIR_MPI4 (1<<5) -#define DMAC_GIR_MPI5 (1<<4) -#define DMAC_GIR_MPI2 (1<<3) -#define DMAC_GIR_MPI3 (1<<2) -#define DMAC_GIR_MPI0 (1<<1) -#define DMAC_GIR_MPI1 (1<<0) - -#define DMAC_M2P0 0x0000 -#define DMAC_M2P1 0x0040 -#define DMAC_M2P2 0x0080 -#define DMAC_M2P3 0x00c0 -#define DMAC_M2P4 0x0240 -#define DMAC_M2P5 0x0200 -#define DMAC_M2P6 0x02c0 -#define DMAC_M2P7 0x0280 -#define DMAC_M2P8 0x0340 -#define DMAC_M2P9 0x0300 -#define DMAC_M2M0 0x0100 -#define DMAC_M2M1 0x0140 - -#define DMAC_P_PCONTROL(c) __REG(DMAC_PHYS + (c) + 0x00) -#define DMAC_P_PINTERRUPT(c) __REG(DMAC_PHYS + (c) + 0x04) -#define DMAC_P_PPALLOC(c) __REG(DMAC_PHYS + (c) + 0x08) -#define DMAC_P_PSTATUS(c) __REG(DMAC_PHYS + (c) + 0x0c) -#define DMAC_P_REMAIN(c) __REG(DMAC_PHYS + (c) + 0x14) -#define DMAC_P_MAXCNT0(c) __REG(DMAC_PHYS + (c) + 0x20) -#define DMAC_P_BASE0(c) __REG(DMAC_PHYS + (c) + 0x24) -#define DMAC_P_CURRENT0(c) __REG(DMAC_PHYS + (c) + 0x28) -#define DMAC_P_MAXCNT1(c) __REG(DMAC_PHYS + (c) + 0x30) -#define DMAC_P_BASE1(c) __REG(DMAC_PHYS + (c) + 0x34) -#define DMAC_P_CURRENT1(c) __REG(DMAC_PHYS + (c) + 0x38) - -#define DMAC_PCONTROL_ENABLE (1<<4) - -#define DMAC_PORT_USB 0 -#define DMAC_PORT_SDMMC 1 -#define DMAC_PORT_AC97_1 2 -#define DMAC_PORT_AC97_2 3 -#define DMAC_PORT_AC97_3 4 -#define DMAC_PORT_UART1 6 -#define DMAC_PORT_UART2 7 -#define DMAC_PORT_UART3 8 - -#define DMAC_PSTATUS_CURRSTATE_SHIFT 4 -#define DMAC_PSTATUS_CURRSTATE_MASK 0x3 - -#define DMAC_PSTATUS_NEXTBUF (1<<6) -#define DMAC_PSTATUS_STALLRINT (1<<0) - -#define DMAC_INT_CHE (1<<3) -#define DMAC_INT_NFB (1<<1) -#define DMAC_INT_STALL (1<<0) diff --git a/arch/arm/mach-lh7a40x/include/mach/entry-macro.S b/arch/arm/mach-lh7a40x/include/mach/entry-macro.S deleted file mode 100644 index 069bb4cefff7..000000000000 --- a/arch/arm/mach-lh7a40x/include/mach/entry-macro.S +++ /dev/null @@ -1,149 +0,0 @@ -/* - * arch/arm/mach-lh7a40x/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for LH7A40x platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <mach/hardware.h> -#include <mach/irqs.h> - -/* In order to allow there to be support for both of the processor - classes at the same time, we make a hack here that isn't very - pretty. At startup, the link pointed to with the - branch_irq_lh7a400 symbol is replaced with a NOP when the CPU is - detected as a lh7a404. - - *** FIXME: we should clean this up so that there is only one - implementation for each CPU's design. - -*/ - -#if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404) - - .macro disable_fiq - .endm - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - -branch_irq_lh7a400: b 1000f - -@ Implementation of the LH7A404 get_irqnr_and_base. - - mov \irqnr, #0 @ VIC1 irq base - mov \base, #io_p2v(0x80000000) @ APB registers - add \base, \base, #0x8000 - ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR - tst \tmp, #VA_VECTORED @ Direct vectored - bne 1002f - tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1 - ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS - bne 1001f - add \base, \base, #(0xa000 - 0x8000) - ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR - tst \tmp, #VA_VECTORED @ Direct vectored - bne 1002f - ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS - mov \irqnr, #32 @ VIC2 irq base - -1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry - bcs 1008f @ Bit set; irq found - add \irqnr, \irqnr, #1 - bne 1001b @ Until no bits - b 1009f @ Nothing? Hmm. -1002: and \irqnr, \tmp, #0x3f @ Mask for valid bits -1008: movs \irqstat, #1 @ Force !Z - str \tmp, [\base, #0x0030] @ Clear vector - b 1009f - -@ Implementation of the LH7A400 get_irqnr_and_base. - -1000: mov \irqnr, #0 - mov \base, #io_p2v(0x80000000) @ APB registers - ldr \irqstat, [\base, #0x500] @ PIC INTSR - -1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry - bcs 1008f @ Bit set; irq found - add \irqnr, \irqnr, #1 - bne 1001b @ Until no bits - b 1009f @ Nothing? Hmm. -1008: movs \irqstat, #1 @ Force !Z - -1009: - .endm - - - -#elif defined (CONFIG_ARCH_LH7A400) - .macro disable_fiq - .endm - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - mov \irqnr, #0 - mov \base, #io_p2v(0x80000000) @ APB registers - ldr \irqstat, [\base, #0x500] @ PIC INTSR - -1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry - bcs 1008f @ Bit set; irq found - add \irqnr, \irqnr, #1 - bne 1001b @ Until no bits - b 1009f @ Nothing? Hmm. -1008: movs \irqstat, #1 @ Force !Z -1009: - .endm - -#elif defined(CONFIG_ARCH_LH7A404) - - .macro disable_fiq - .endm - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - mov \irqnr, #0 @ VIC1 irq base - mov \base, #io_p2v(0x80000000) @ APB registers - add \base, \base, #0x8000 - ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR - tst \tmp, #VA_VECTORED @ Direct vectored - bne 1002f - tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1 - ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS - bne 1001f - add \base, \base, #(0xa000 - 0x8000) - ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR - tst \tmp, #VA_VECTORED @ Direct vectored - bne 1002f - ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS - mov \irqnr, #32 @ VIC2 irq base - -1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry - bcs 1008f @ Bit set; irq found - add \irqnr, \irqnr, #1 - bne 1001b @ Until no bits - b 1009f @ Nothing? Hmm. -1002: and \irqnr, \tmp, #0x3f @ Mask for valid bits -1008: movs \irqstat, #1 @ Force !Z - str \tmp, [\base, #0x0030] @ Clear vector -1009: - .endm -#endif - - diff --git a/arch/arm/mach-lh7a40x/include/mach/hardware.h b/arch/arm/mach-lh7a40x/include/mach/hardware.h deleted file mode 100644 index 59d2ace35217..000000000000 --- a/arch/arm/mach-lh7a40x/include/mach/hardware.h +++ /dev/null @@ -1,62 +0,0 @@ -/* arch/arm/mach-lh7a40x/include/mach/hardware.h - * - * Copyright (C) 2004 Coastal Environmental Systems - * - * [ Substantially cribbed from arch/arm/mach-pxa/include/mach/hardware.h ] - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <asm/sizes.h> /* Added for the sake of amba-clcd driver */ - -#define io_p2v(x) (0xf0000000 | (((x) & 0xfff00000) >> 4) | ((x) & 0x0000ffff)) -#define io_v2p(x) ( (((x) & 0x0fff0000) << 4) | ((x) & 0x0000ffff)) - -#ifdef __ASSEMBLY__ - -# define __REG(x) io_p2v(x) -# define __PREG(x) io_v2p(x) - -#else - -# if 0 -# define __REG(x) (*((volatile u32 *)io_p2v(x))) -# else -/* - * This __REG() version gives the same results as the one above, except - * that we are fooling gcc somehow so it generates far better and smaller - * assembly code for access to contiguous registers. It's a shame that gcc - * doesn't guess this by itself. - */ -#include <asm/types.h> -typedef struct { volatile u32 offset[4096]; } __regbase; -# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2] -# define __REG(x) __REGP(io_p2v(x)) -typedef struct { volatile u16 offset[4096]; } __regbase16; -# define __REGP16(x) ((__regbase16 *)((x)&~4095))->offset[((x)&4095)>>1] -# define __REG16(x) __REGP16(io_p2v(x)) -typedef struct { volatile u8 offset[4096]; } __regbase8; -# define __REGP8(x) ((__regbase8 *)((x)&~4095))->offset[(x)&4095] -# define __REG8(x) __REGP8(io_p2v(x)) -#endif - -/* Let's kick gcc's ass again... */ -# define __REG2(x,y) \ - ( __builtin_constant_p(y) ? (__REG((x) + (y))) \ - : (*(volatile u32 *)((u32)&__REG(x) + (y))) ) - -# define __PREG(x) (io_v2p((u32)&(x))) - -#endif - -#define MASK_AND_SET(v,m,s) (v) = ((v)&~(m))|(s) - -#include "registers.h" - -#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-lh7a40x/include/mach/io.h b/arch/arm/mach-lh7a40x/include/mach/io.h deleted file mode 100644 index 6ece45911cbc..000000000000 --- a/arch/arm/mach-lh7a40x/include/mach/io.h +++ /dev/null @@ -1,20 +0,0 @@ -/* arch/arm/mach-lh7a40x/include/mach/io.h - * - * Copyright (C) 2004 Coastal Environmental Systems - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff - -/* No ISA or PCI bus on this machine. */ -#define __io(a) __typesafe_io(a) -#define __mem_pci(a) (a) - -#endif /* __ASM_ARCH_IO_H */ diff --git a/arch/arm/mach-lh7a40x/include/mach/irqs.h b/arch/arm/mach-lh7a40x/include/mach/irqs.h deleted file mode 100644 index 0f9b83675935..000000000000 --- a/arch/arm/mach-lh7a40x/include/mach/irqs.h +++ /dev/null @@ -1,200 +0,0 @@ -/* arch/arm/mach-lh7a40x/include/mach/irqs.h - * - * Copyright (C) 2004 Coastal Environmental Systems - * Copyright (C) 2004 Logic Product Development - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ - -/* It is to be seen whether or not we can build a kernel for more than - * one board. For the time being, these macros assume that we cannot. - * Thus, it is OK to ifdef machine/board specific IRQ assignments. - */ - - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - - -#define FIQ_START 80 - -#if defined (CONFIG_ARCH_LH7A400) - - /* FIQs */ - -# define IRQ_GPIO0FIQ 0 /* GPIO External FIQ Interrupt on F0 */ -# define IRQ_BLINT 1 /* Battery Low */ -# define IRQ_WEINT 2 /* Watchdog Timer, WDT overflow */ -# define IRQ_MCINT 3 /* Media Change, MEDCHG pin rising */ - - /* IRQs */ - -# define IRQ_CSINT 4 /* Audio Codec (ACI) */ -# define IRQ_GPIO1INTR 5 /* GPIO External IRQ Interrupt on F1 */ -# define IRQ_GPIO2INTR 6 /* GPIO External IRQ Interrupt on F2 */ -# define IRQ_GPIO3INTR 7 /* GPIO External IRQ Interrupt on F3 */ -# define IRQ_T1UI 8 /* Timer 1 underflow */ -# define IRQ_T2UI 9 /* Timer 2 underflow */ -# define IRQ_RTCMI 10 -# define IRQ_TINTR 11 /* Clock State Controller 64 Hz tick (CSC) */ -# define IRQ_UART1INTR 12 -# define IRQ_UART2INTR 13 -# define IRQ_LCDINTR 14 -# define IRQ_SSIEOT 15 /* Synchronous Serial Interface (SSI) */ -# define IRQ_UART3INTR 16 -# define IRQ_SCIINTR 17 /* Smart Card Interface (SCI) */ -# define IRQ_AACINTR 18 /* Advanced Audio Codec (AAC) */ -# define IRQ_MMCINTR 19 /* Multimedia Card (MMC) */ -# define IRQ_USBINTR 20 -# define IRQ_DMAINTR 21 -# define IRQ_T3UI 22 /* Timer 3 underflow */ -# define IRQ_GPIO4INTR 23 /* GPIO External IRQ Interrupt on F4 */ -# define IRQ_GPIO5INTR 24 /* GPIO External IRQ Interrupt on F5 */ -# define IRQ_GPIO6INTR 25 /* GPIO External IRQ Interrupt on F6 */ -# define IRQ_GPIO7INTR 26 /* GPIO External IRQ Interrupt on F7 */ -# define IRQ_BMIINTR 27 /* Battery Monitor Interface (BMI) */ - -# define NR_IRQ_CPU 28 /* IRQs directly recognized by CPU */ - - /* Given IRQ, return GPIO interrupt number 0-7 */ -# define IRQ_TO_GPIO(i) ((i) \ - - (((i) > IRQ_GPIO3INTR) ? IRQ_GPIO4INTR - IRQ_GPIO3INTR - 1 : 0)\ - - (((i) > IRQ_GPIO0INTR) ? IRQ_GPIO1INTR - IRQ_GPIO0INTR - 1 : 0)) - -#endif - -#if defined (CONFIG_ARCH_LH7A404) - -# define IRQ_BROWN 0 /* Brownout */ -# define IRQ_WDTINTR 1 /* Watchdog Timer */ -# define IRQ_COMMRX 2 /* ARM Comm Rx for Debug */ -# define IRQ_COMMTX 3 /* ARM Comm Tx for Debug */ -# define IRQ_T1UI 4 /* Timer 1 underflow */ -# define IRQ_T2UI 5 /* Timer 2 underflow */ -# define IRQ_CSINT 6 /* Codec Interrupt (shared by AAC on 404) */ -# define IRQ_DMAM2P0 7 /* -- DMA Memory to Peripheral */ -# define IRQ_DMAM2P1 8 -# define IRQ_DMAM2P2 9 -# define IRQ_DMAM2P3 10 -# define IRQ_DMAM2P4 11 -# define IRQ_DMAM2P5 12 -# define IRQ_DMAM2P6 13 -# define IRQ_DMAM2P7 14 -# define IRQ_DMAM2P8 15 -# define IRQ_DMAM2P9 16 -# define IRQ_DMAM2M0 17 /* -- DMA Memory to Memory */ -# define IRQ_DMAM2M1 18 -# define IRQ_GPIO0INTR 19 /* -- GPIOF Interrupt */ -# define IRQ_GPIO1INTR 20 -# define IRQ_GPIO2INTR 21 -# define IRQ_GPIO3INTR 22 -# define IRQ_SOFT_V1_23 23 /* -- Unassigned */ -# define IRQ_SOFT_V1_24 24 -# define IRQ_SOFT_V1_25 25 -# define IRQ_SOFT_V1_26 26 -# define IRQ_SOFT_V1_27 27 -# define IRQ_SOFT_V1_28 28 -# define IRQ_SOFT_V1_29 29 -# define IRQ_SOFT_V1_30 30 -# define IRQ_SOFT_V1_31 31 - -# define IRQ_BLINT 32 /* Battery Low */ -# define IRQ_BMIINTR 33 /* Battery Monitor */ -# define IRQ_MCINTR 34 /* Media Change */ -# define IRQ_TINTR 35 /* 64Hz Tick */ -# define IRQ_WEINT 36 /* Watchdog Expired */ -# define IRQ_RTCMI 37 /* Real-time Clock Match */ -# define IRQ_UART1INTR 38 /* UART1 Interrupt (including error) */ -# define IRQ_UART1ERR 39 /* UART1 Error */ -# define IRQ_UART2INTR 40 /* UART2 Interrupt (including error) */ -# define IRQ_UART2ERR 41 /* UART2 Error */ -# define IRQ_UART3INTR 42 /* UART3 Interrupt (including error) */ -# define IRQ_UART3ERR 43 /* UART3 Error */ -# define IRQ_SCIINTR 44 /* Smart Card */ -# define IRQ_TSCINTR 45 /* Touchscreen */ -# define IRQ_KMIINTR 46 /* Keyboard/Mouse (PS/2) */ -# define IRQ_GPIO4INTR 47 /* -- GPIOF Interrupt */ -# define IRQ_GPIO5INTR 48 -# define IRQ_GPIO6INTR 49 -# define IRQ_GPIO7INTR 50 -# define IRQ_T3UI 51 /* Timer 3 underflow */ -# define IRQ_LCDINTR 52 /* LCD Controller */ -# define IRQ_SSPINTR 53 /* Synchronous Serial Port */ -# define IRQ_SDINTR 54 /* Secure Digital Port (MMC) */ -# define IRQ_USBINTR 55 /* USB Device Port */ -# define IRQ_USHINTR 56 /* USB Host Port */ -# define IRQ_SOFT_V2_25 57 /* -- Unassigned */ -# define IRQ_SOFT_V2_26 58 -# define IRQ_SOFT_V2_27 59 -# define IRQ_SOFT_V2_28 60 -# define IRQ_SOFT_V2_29 61 -# define IRQ_SOFT_V2_30 62 -# define IRQ_SOFT_V2_31 63 - -# define NR_IRQ_CPU 64 /* IRQs directly recognized by CPU */ - - /* Given IRQ, return GPIO interrupt number 0-7 */ -# define IRQ_TO_GPIO(i) ((i) \ - - (((i) > IRQ_GPIO3INTR) ? IRQ_GPIO4INTR - IRQ_GPIO3INTR - 1 : 0)\ - - IRQ_GPIO0INTR) - - /* Vector Address constants */ -# define VA_VECTORED 0x100 /* Set for vectored interrupt */ -# define VA_VIC1DEFAULT 0x200 /* Set as default VECTADDR for VIC1 */ -# define VA_VIC2DEFAULT 0x400 /* Set as default VECTADDR for VIC2 */ - -#endif - - /* IRQ aliases */ - -#if !defined (IRQ_GPIO0INTR) -# define IRQ_GPIO0INTR IRQ_GPIO0FIQ -#endif -#define IRQ_TICK IRQ_TINTR -#define IRQ_PCC1_RDY IRQ_GPIO6INTR /* PCCard 1 ready */ -#define IRQ_PCC2_RDY IRQ_GPIO7INTR /* PCCard 2 ready */ -#define IRQ_USB IRQ_USBINTR /* USB device */ - -#ifdef CONFIG_MACH_KEV7A400 -# define IRQ_TS IRQ_GPIOFIQ /* Touchscreen */ -# define IRQ_CPLD IRQ_GPIO1INTR /* CPLD cascade */ -# define IRQ_PCC1_CD IRQ_GPIO_F2 /* PCCard 1 card detect */ -# define IRQ_PCC2_CD IRQ_GPIO_F3 /* PCCard 2 card detect */ -#endif - -#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) -# define IRQ_CPLD_V28 IRQ_GPIO7INTR /* CPLD cascade through GPIO_PF7 */ -# define IRQ_CPLD_V34 IRQ_GPIO3INTR /* CPLD cascade through GPIO_PF3 */ -#endif - - /* System specific IRQs */ - -#define IRQ_BOARD_START NR_IRQ_CPU - -#ifdef CONFIG_MACH_KEV7A400 -# define IRQ_KEV7A400_CPLD IRQ_BOARD_START -# define NR_IRQ_BOARD 5 -# define IRQ_KEV7A400_MMC_CD IRQ_KEV7A400_CPLD + 0 /* MMC Card Detect */ -# define IRQ_KEV7A400_RI2 IRQ_KEV7A400_CPLD + 1 /* Ring Indicator 2 */ -# define IRQ_KEV7A400_IDE_CF IRQ_KEV7A400_CPLD + 2 /* Compact Flash (?) */ -# define IRQ_KEV7A400_ETH_INT IRQ_KEV7A400_CPLD + 3 /* Ethernet chip */ -# define IRQ_KEV7A400_INT IRQ_KEV7A400_CPLD + 4 -#endif - -#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) -# define IRQ_LPD7A40X_CPLD IRQ_BOARD_START -# define NR_IRQ_BOARD 2 -# define IRQ_LPD7A40X_ETH_INT IRQ_LPD7A40X_CPLD + 0 /* Ethernet chip */ -# define IRQ_LPD7A400_TS IRQ_LPD7A40X_CPLD + 1 /* Touch screen */ -#endif - -#if defined (CONFIG_MACH_LPD7A400) -# define IRQ_TOUCH IRQ_LPD7A400_TS -#endif - -#define NR_IRQS (NR_IRQ_CPU + NR_IRQ_BOARD) - -#endif diff --git a/arch/arm/mach-lh7a40x/include/mach/memory.h b/arch/arm/mach-lh7a40x/include/mach/memory.h deleted file mode 100644 index edb8f5faf5d5..000000000000 --- a/arch/arm/mach-lh7a40x/include/mach/memory.h +++ /dev/null @@ -1,28 +0,0 @@ -/* arch/arm/mach-lh7a40x/include/mach/memory.h - * - * Copyright (C) 2004 Coastal Environmental Systems - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * - * Refer to <file:Documentation/arm/Sharp-LH/SDRAM> for more information. - * - */ - -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -/* - * Physical DRAM offset. - */ -#define PHYS_OFFSET UL(0xc0000000) - -/* - * Sparsemem version of the above - */ -#define MAX_PHYSMEM_BITS 32 -#define SECTION_SIZE_BITS 24 - -#endif diff --git a/arch/arm/mach-lh7a40x/include/mach/registers.h b/arch/arm/mach-lh7a40x/include/mach/registers.h deleted file mode 100644 index ea44396383a7..000000000000 --- a/arch/arm/mach-lh7a40x/include/mach/registers.h +++ /dev/null @@ -1,224 +0,0 @@ -/* arch/arm/mach-lh7a40x/include/mach/registers.h - * - * Copyright (C) 2004 Coastal Environmental Systems - * Copyright (C) 2004 Logic Product Development - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ - -#include <mach/constants.h> - -#ifndef __ASM_ARCH_REGISTERS_H -#define __ASM_ARCH_REGISTERS_H - - - /* Physical register base addresses */ - -#define AC97C_PHYS (0x80000000) /* AC97 Controller */ -#define MMC_PHYS (0x80000100) /* Multimedia Card Controller */ -#define USB_PHYS (0x80000200) /* USB Client */ -#define SCI_PHYS (0x80000300) /* Secure Card Interface */ -#define CSC_PHYS (0x80000400) /* Clock/State Controller */ -#define INTC_PHYS (0x80000500) /* Interrupt Controller */ -#define UART1_PHYS (0x80000600) /* UART1 Controller */ -#define SIR_PHYS (0x80000600) /* IR Controller, same are UART1 */ -#define UART2_PHYS (0x80000700) /* UART2 Controller */ -#define UART3_PHYS (0x80000800) /* UART3 Controller */ -#define DCDC_PHYS (0x80000900) /* DC to DC Controller */ -#define ACI_PHYS (0x80000a00) /* Audio Codec Interface */ -#define SSP_PHYS (0x80000b00) /* Synchronous ... */ -#define TIMER_PHYS (0x80000c00) /* Timer Controller */ -#define RTC_PHYS (0x80000d00) /* Real-time Clock */ -#define GPIO_PHYS (0x80000e00) /* General Purpose IO */ -#define BMI_PHYS (0x80000f00) /* Battery Monitor Interface */ -#define HRTFTC_PHYS (0x80001000) /* High-res TFT Controller (LH7A400) */ -#define ALI_PHYS (0x80001000) /* Advanced LCD Interface (LH7A404) */ -#define WDT_PHYS (0x80001400) /* Watchdog Timer */ -#define SMC_PHYS (0x80002000) /* Static Memory Controller */ -#define SDRC_PHYS (0x80002400) /* SDRAM Controller */ -#define DMAC_PHYS (0x80002800) /* DMA Controller */ -#define CLCDC_PHYS (0x80003000) /* Color LCD Controller */ - - /* Physical registers of the LH7A404 */ - -#define ADC_PHYS (0x80001300) /* A/D & Touchscreen Controller */ -#define VIC1_PHYS (0x80008000) /* Vectored Interrupt Controller 1 */ -#define USBH_PHYS (0x80009000) /* USB OHCI host controller */ -#define VIC2_PHYS (0x8000a000) /* Vectored Interrupt Controller 2 */ - -/*#define KBD_PHYS (0x80000e00) */ -/*#define LCDICP_PHYS (0x80001000) */ - - - /* Clock/State Controller register */ - -#define CSC_PWRSR __REG(CSC_PHYS + 0x00) /* Reset register & ID */ -#define CSC_PWRCNT __REG(CSC_PHYS + 0x04) /* Power control */ -#define CSC_CLKSET __REG(CSC_PHYS + 0x20) /* Clock speed control */ -#define CSC_USBDRESET __REG(CSC_PHYS + 0x4c) /* USB Device resets */ - -#define CSC_PWRCNT_USBH_EN (1<<28) /* USB Host power enable */ -#define CSC_PWRCNT_DMAC_M2M1_EN (1<<27) -#define CSC_PWRCNT_DMAC_M2M0_EN (1<<26) -#define CSC_PWRCNT_DMAC_M2P8_EN (1<<25) -#define CSC_PWRCNT_DMAC_M2P9_EN (1<<24) -#define CSC_PWRCNT_DMAC_M2P6_EN (1<<23) -#define CSC_PWRCNT_DMAC_M2P7_EN (1<<22) -#define CSC_PWRCNT_DMAC_M2P4_EN (1<<21) -#define CSC_PWRCNT_DMAC_M2P5_EN (1<<20) -#define CSC_PWRCNT_DMAC_M2P2_EN (1<<19) -#define CSC_PWRCNT_DMAC_M2P3_EN (1<<18) -#define CSC_PWRCNT_DMAC_M2P0_EN (1<<17) -#define CSC_PWRCNT_DMAC_M2P1_EN (1<<16) - -#define CSC_PWRSR_CHIPMAN_SHIFT (24) -#define CSC_PWRSR_CHIPMAN_MASK (0xff) -#define CSC_PWRSR_CHIPID_SHIFT (16) -#define CSC_PWRSR_CHIPID_MASK (0xff) - -#define CSC_USBDRESET_APBRESETREG (1<<1) -#define CSC_USBDRESET_IORESETREG (1<<0) - - /* Interrupt Controller registers */ - -#define INTC_INTSR __REG(INTC_PHYS + 0x00) /* Status */ -#define INTC_INTRSR __REG(INTC_PHYS + 0x04) /* Raw Status */ -#define INTC_INTENS __REG(INTC_PHYS + 0x08) /* Enable Set */ -#define INTC_INTENC __REG(INTC_PHYS + 0x0c) /* Enable Clear */ - - - /* Vectored Interrupted Controller registers */ - -#define VIC1_IRQSTATUS __REG(VIC1_PHYS + 0x00) -#define VIC1_FIQSTATUS __REG(VIC1_PHYS + 0x04) -#define VIC1_RAWINTR __REG(VIC1_PHYS + 0x08) -#define VIC1_INTSEL __REG(VIC1_PHYS + 0x0c) -#define VIC1_INTEN __REG(VIC1_PHYS + 0x10) -#define VIC1_INTENCLR __REG(VIC1_PHYS + 0x14) -#define VIC1_SOFTINT __REG(VIC1_PHYS + 0x18) -#define VIC1_SOFTINTCLR __REG(VIC1_PHYS + 0x1c) -#define VIC1_PROTECT __REG(VIC1_PHYS + 0x20) -#define VIC1_VECTADDR __REG(VIC1_PHYS + 0x30) -#define VIC1_NVADDR __REG(VIC1_PHYS + 0x34) -#define VIC1_VAD0 __REG(VIC1_PHYS + 0x100) -#define VIC1_VECTCNTL0 __REG(VIC1_PHYS + 0x200) -#define VIC2_IRQSTATUS __REG(VIC2_PHYS + 0x00) -#define VIC2_FIQSTATUS __REG(VIC2_PHYS + 0x04) -#define VIC2_RAWINTR __REG(VIC2_PHYS + 0x08) -#define VIC2_INTSEL __REG(VIC2_PHYS + 0x0c) -#define VIC2_INTEN __REG(VIC2_PHYS + 0x10) -#define VIC2_INTENCLR __REG(VIC2_PHYS + 0x14) -#define VIC2_SOFTINT __REG(VIC2_PHYS + 0x18) -#define VIC2_SOFTINTCLR __REG(VIC2_PHYS + 0x1c) -#define VIC2_PROTECT __REG(VIC2_PHYS + 0x20) -#define VIC2_VECTADDR __REG(VIC2_PHYS + 0x30) -#define VIC2_NVADDR __REG(VIC2_PHYS + 0x34) -#define VIC2_VAD0 __REG(VIC2_PHYS + 0x100) -#define VIC2_VECTCNTL0 __REG(VIC2_PHYS + 0x200) - -#define VIC_CNTL_ENABLE (0x20) - - /* USB Host registers (Open HCI compatible) */ - -#define USBH_CMDSTATUS __REG(USBH_PHYS + 0x08) - - - /* GPIO registers */ - -#define GPIO_INTTYPE1 __REG(GPIO_PHYS + 0x4c) /* Interrupt Type 1 (Edge) */ -#define GPIO_INTTYPE2 __REG(GPIO_PHYS + 0x50) /* Interrupt Type 2 */ -#define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */ -#define GPIO_GPIOINTEN __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */ -#define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */ -#define GPIO_PINMUX __REG(GPIO_PHYS + 0x2c) -#define GPIO_PADD __REG(GPIO_PHYS + 0x10) -#define GPIO_PAD __REG(GPIO_PHYS + 0x00) -#define GPIO_PCD __REG(GPIO_PHYS + 0x08) -#define GPIO_PCDD __REG(GPIO_PHYS + 0x18) -#define GPIO_PEDD __REG(GPIO_PHYS + 0x24) -#define GPIO_PED __REG(GPIO_PHYS + 0x20) - - - /* Static Memory Controller registers */ - -#define SMC_BCR0 __REG(SMC_PHYS + 0x00) /* Bank 0 Configuration */ -#define SMC_BCR1 __REG(SMC_PHYS + 0x04) /* Bank 1 Configuration */ -#define SMC_BCR2 __REG(SMC_PHYS + 0x08) /* Bank 2 Configuration */ -#define SMC_BCR3 __REG(SMC_PHYS + 0x0C) /* Bank 3 Configuration */ -#define SMC_BCR6 __REG(SMC_PHYS + 0x18) /* Bank 6 Configuration */ -#define SMC_BCR7 __REG(SMC_PHYS + 0x1c) /* Bank 7 Configuration */ - - -#ifdef CONFIG_MACH_KEV7A400 -# define CPLD_RD_OPT_DIP_SW __REG16(CPLD_PHYS + 0x00) /* Read Option SW */ -# define CPLD_WR_IO_BRD_CTL __REG16(CPLD_PHYS + 0x00) /* Write Control */ -# define CPLD_RD_PB_KEYS __REG16(CPLD_PHYS + 0x02) /* Read Btn Keys */ -# define CPLD_LATCHED_INTS __REG16(CPLD_PHYS + 0x04) /* Read INTR stat. */ -# define CPLD_CL_INT __REG16(CPLD_PHYS + 0x04) /* Clear INTR stat */ -# define CPLD_BOOT_MMC_STATUS __REG16(CPLD_PHYS + 0x06) /* R/O */ -# define CPLD_RD_KPD_ROW_SENSE __REG16(CPLD_PHYS + 0x08) -# define CPLD_WR_PB_INT_MASK __REG16(CPLD_PHYS + 0x08) -# define CPLD_RD_BRD_DISP_SW __REG16(CPLD_PHYS + 0x0a) -# define CPLD_WR_EXT_INT_MASK __REG16(CPLD_PHYS + 0x0a) -# define CPLD_LCD_PWR_CNTL __REG16(CPLD_PHYS + 0x0c) -# define CPLD_SEVEN_SEG __REG16(CPLD_PHYS + 0x0e) /* 7 seg. LED mask */ - -#endif - -#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) - -# define CPLD_CONTROL __REG16(CPLD02_PHYS) -# define CPLD_SPI_DATA __REG16(CPLD06_PHYS) -# define CPLD_SPI_CONTROL __REG16(CPLD08_PHYS) -# define CPLD_SPI_EEPROM __REG16(CPLD0A_PHYS) -# define CPLD_INTERRUPTS __REG16(CPLD0C_PHYS) /* IRQ mask/status */ -# define CPLD_BOOT_MODE __REG16(CPLD0E_PHYS) -# define CPLD_FLASH __REG16(CPLD10_PHYS) -# define CPLD_POWER_MGMT __REG16(CPLD12_PHYS) -# define CPLD_REVISION __REG16(CPLD14_PHYS) -# define CPLD_GPIO_EXT __REG16(CPLD16_PHYS) -# define CPLD_GPIO_DATA __REG16(CPLD18_PHYS) -# define CPLD_GPIO_DIR __REG16(CPLD1A_PHYS) - -#endif - - /* Timer registers */ - -#define TIMER_LOAD1 __REG(TIMER_PHYS + 0x00) /* Timer 1 initial value */ -#define TIMER_VALUE1 __REG(TIMER_PHYS + 0x04) /* Timer 1 current value */ -#define TIMER_CONTROL1 __REG(TIMER_PHYS + 0x08) /* Timer 1 control word */ -#define TIMER_EOI1 __REG(TIMER_PHYS + 0x0c) /* Timer 1 interrupt clear */ - -#define TIMER_LOAD2 __REG(TIMER_PHYS + 0x20) /* Timer 2 initial value */ -#define TIMER_VALUE2 __REG(TIMER_PHYS + 0x24) /* Timer 2 current value */ -#define TIMER_CONTROL2 __REG(TIMER_PHYS + 0x28) /* Timer 2 control word */ -#define TIMER_EOI2 __REG(TIMER_PHYS + 0x2c) /* Timer 2 interrupt clear */ - -#define TIMER_BUZZCON __REG(TIMER_PHYS + 0x40) /* Buzzer configuration */ - -#define TIMER_LOAD3 __REG(TIMER_PHYS + 0x80) /* Timer 3 initial value */ -#define TIMER_VALUE3 __REG(TIMER_PHYS + 0x84) /* Timer 3 current value */ -#define TIMER_CONTROL3 __REG(TIMER_PHYS + 0x88) /* Timer 3 control word */ -#define TIMER_EOI3 __REG(TIMER_PHYS + 0x8c) /* Timer 3 interrupt clear */ - -#define TIMER_C_ENABLE (1<<7) -#define TIMER_C_PERIODIC (1<<6) -#define TIMER_C_FREERUNNING (0) -#define TIMER_C_2KHZ (0x00) /* 1.986 kHz */ -#define TIMER_C_508KHZ (0x08) - - /* GPIO registers */ - -#define GPIO_PFDD __REG(GPIO_PHYS + 0x34) /* PF direction */ -#define GPIO_INTTYPE1 __REG(GPIO_PHYS + 0x4c) /* IRQ edge or lvl */ -#define GPIO_INTTYPE2 __REG(GPIO_PHYS + 0x50) /* IRQ activ hi/lo */ -#define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIOF end of IRQ */ -#define GPIO_GPIOFINTEN __REG(GPIO_PHYS + 0x58) /* GPIOF IRQ enable */ -#define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIOF IRQ latch */ -#define GPIO_RAWINTSTATUS __REG(GPIO_PHYS + 0x60) /* GPIOF IRQ raw */ - - -#endif /* _ASM_ARCH_REGISTERS_H */ diff --git a/arch/arm/mach-lh7a40x/include/mach/ssp.h b/arch/arm/mach-lh7a40x/include/mach/ssp.h deleted file mode 100644 index 509916182e34..000000000000 --- a/arch/arm/mach-lh7a40x/include/mach/ssp.h +++ /dev/null @@ -1,70 +0,0 @@ -/* ssp.h - - written by Marc Singer - 6 Dec 2004 - - Copyright (C) 2004 Marc Singer - - ----------- - DESCRIPTION - ----------- - - This SSP header is available throughout the kernel, for this - machine/architecture, because drivers that use it may be dispersed. - - This file was cloned from the 7952x implementation. It would be - better to share them, but we're taking an easier approach for the - time being. - -*/ - -#if !defined (__SSP_H__) -# define __SSP_H__ - -/* ----- Includes */ - -/* ----- Types */ - -struct ssp_driver { - int (*init) (void); - void (*exit) (void); - void (*acquire) (void); - void (*release) (void); - int (*configure) (int device, int mode, int speed, - int frame_size_write, int frame_size_read); - void (*chip_select) (int enable); - void (*set_callbacks) (void* handle, - irqreturn_t (*callback_tx)(void*), - irqreturn_t (*callback_rx)(void*)); - void (*enable) (void); - void (*disable) (void); -// int (*save_state) (void*); -// void (*restore_state) (void*); - int (*read) (void); - int (*write) (u16 data); - int (*write_read) (u16 data); - void (*flush) (void); - void (*write_async) (void* pv, size_t cb); - size_t (*write_pos) (void); -}; - - /* These modes are only available on the LH79524 */ -#define SSP_MODE_SPI (1) -#define SSP_MODE_SSI (2) -#define SSP_MODE_MICROWIRE (3) -#define SSP_MODE_I2S (4) - - /* CPLD SPI devices */ -#define DEVICE_EEPROM 0 /* Configuration eeprom */ -#define DEVICE_MAC 1 /* MAC eeprom (LPD79524) */ -#define DEVICE_CODEC 2 /* Audio codec */ -#define DEVICE_TOUCH 3 /* Touch screen (LPD79520) */ - -/* ----- Globals */ - -/* ----- Prototypes */ - -//extern struct ssp_driver lh79520_i2s_driver; -extern struct ssp_driver lh7a400_cpld_ssp_driver; - -#endif /* __SSP_H__ */ diff --git a/arch/arm/mach-lh7a40x/include/mach/system.h b/arch/arm/mach-lh7a40x/include/mach/system.h deleted file mode 100644 index 45a56d3b93d7..000000000000 --- a/arch/arm/mach-lh7a40x/include/mach/system.h +++ /dev/null @@ -1,19 +0,0 @@ -/* arch/arm/mach-lh7a40x/include/mach/system.h - * - * Copyright (C) 2004 Coastal Environmental Systems - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ - -static inline void arch_idle(void) -{ - cpu_do_idle (); -} - -static inline void arch_reset(char mode, const char *cmd) -{ - cpu_reset (0); -} diff --git a/arch/arm/mach-lh7a40x/include/mach/timex.h b/arch/arm/mach-lh7a40x/include/mach/timex.h deleted file mode 100644 index 08028cef1b3b..000000000000 --- a/arch/arm/mach-lh7a40x/include/mach/timex.h +++ /dev/null @@ -1,17 +0,0 @@ -/* arch/arm/mach-lh7a40x/include/mach/timex.h - * - * Copyright (C) 2004 Coastal Environmental Systems - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ - -#include <mach/constants.h> - -#define CLOCK_TICK_RATE (PLL_CLOCK/6/16) - -/* -#define CLOCK_TICK_RATE 3686400 -*/ diff --git a/arch/arm/mach-lh7a40x/include/mach/uncompress.h b/arch/arm/mach-lh7a40x/include/mach/uncompress.h deleted file mode 100644 index 55b80d479eb4..000000000000 --- a/arch/arm/mach-lh7a40x/include/mach/uncompress.h +++ /dev/null @@ -1,38 +0,0 @@ -/* arch/arm/mach-lh7a40x/include/mach/uncompress.h - * - * Copyright (C) 2004 Coastal Environmental Systems - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ - -#include <mach/registers.h> - -#ifndef UART_R_DATA -# define UART_R_DATA (0x00) -#endif -#ifndef UART_R_STATUS -# define UART_R_STATUS (0x10) -#endif -#define nTxRdy (0x20) /* Not TxReady (literally Tx FIFO full) */ - - /* Access UART with physical addresses before MMU is setup */ -#define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS)) -#define UART_DATA (*(volatile unsigned long*) (UART2_PHYS + UART_R_DATA)) - -static inline void putc(int ch) -{ - while (UART_STATUS & nTxRdy) - barrier(); - UART_DATA = ch; -} - -static inline void flush(void) -{ -} - - /* NULL functions; we don't presently need them */ -#define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-lh7a40x/include/mach/vmalloc.h b/arch/arm/mach-lh7a40x/include/mach/vmalloc.h deleted file mode 100644 index d62da7358b16..000000000000 --- a/arch/arm/mach-lh7a40x/include/mach/vmalloc.h +++ /dev/null @@ -1,10 +0,0 @@ -/* arch/arm/mach-lh7a40x/include/mach/vmalloc.h - * - * Copyright (C) 2004 Coastal Environmental Systems - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ -#define VMALLOC_END (0xe8000000UL) diff --git a/arch/arm/mach-lh7a40x/irq-kev7a400.c b/arch/arm/mach-lh7a40x/irq-kev7a400.c deleted file mode 100644 index c7433b3c5812..000000000000 --- a/arch/arm/mach-lh7a40x/irq-kev7a400.c +++ /dev/null @@ -1,93 +0,0 @@ -/* arch/arm/mach-lh7a40x/irq-kev7a400.c - * - * Copyright (C) 2004 Coastal Environmental Systems - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ - -#include <linux/interrupt.h> -#include <linux/init.h> - -#include <asm/irq.h> -#include <asm/mach/irq.h> -#include <asm/mach/hardware.h> -#include <asm/mach/irqs.h> - -#include "common.h" - - /* KEV7a400 CPLD IRQ handling */ - -static u16 CPLD_IRQ_mask; /* Mask for CPLD IRQs, 1 == unmasked */ - -static void -lh7a400_ack_cpld_irq (u32 irq) -{ - CPLD_CL_INT = 1 << (irq - IRQ_KEV7A400_CPLD); -} - -static void -lh7a400_mask_cpld_irq (u32 irq) -{ - CPLD_IRQ_mask &= ~(1 << (irq - IRQ_KEV7A400_CPLD)); - CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask; -} - -static void -lh7a400_unmask_cpld_irq (u32 irq) -{ - CPLD_IRQ_mask |= 1 << (irq - IRQ_KEV7A400_CPLD); - CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask; -} - -static struct -irq_chip lh7a400_cpld_chip = { - .name = "CPLD", - .ack = lh7a400_ack_cpld_irq, - .mask = lh7a400_mask_cpld_irq, - .unmask = lh7a400_unmask_cpld_irq, -}; - -static void -lh7a400_cpld_handler (unsigned int irq, struct irq_desc *desc) -{ - u32 mask = CPLD_LATCHED_INTS; - irq = IRQ_KEV_7A400_CPLD; - for (; mask; mask >>= 1, ++irq) { - if (mask & 1) - desc[irq].handle (irq, desc); - } -} - - /* IRQ initialization */ - -void __init -lh7a400_init_board_irq (void) -{ - int irq; - - for (irq = IRQ_KEV7A400_CPLD; - irq < IRQ_KEV7A400_CPLD + NR_IRQ_KEV7A400_CPLD; ++irq) { - set_irq_chip (irq, &lh7a400_cpld_chip); - set_irq_handler (irq, handle_edge_irq); - set_irq_flags (irq, IRQF_VALID); - } - set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler); - - /* Clear all CPLD interrupts */ - CPLD_CL_INT = 0xff; /* CPLD_INTR_MMC_CD | CPLD_INTR_ETH_INT; */ - - /* *** FIXME CF enabled in ide-probe.c */ - - GPIO_GPIOINTEN = 0; /* Disable all GPIO interrupts */ - barrier(); - GPIO_INTTYPE1 - = (GPIO_INTR_PCC1_CD | GPIO_INTR_PCC1_CD); /* Edge trig. */ - GPIO_INTTYPE2 = 0; /* Falling edge & low-level */ - GPIO_GPIOFEOI = 0xff; /* Clear all GPIO interrupts */ - GPIO_GPIOINTEN = 0xff; /* Enable all GPIO interrupts */ - - init_FIQ(); -} diff --git a/arch/arm/mach-lh7a40x/irq-lh7a400.c b/arch/arm/mach-lh7a40x/irq-lh7a400.c deleted file mode 100644 index f2e7e655ca35..000000000000 --- a/arch/arm/mach-lh7a40x/irq-lh7a400.c +++ /dev/null @@ -1,91 +0,0 @@ -/* arch/arm/mach-lh7a40x/irq-lh7a400.c - * - * Copyright (C) 2004 Coastal Environmental Systems - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/interrupt.h> - -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/mach/irq.h> -#include <mach/irqs.h> - -#include "common.h" - - /* CPU IRQ handling */ - -static void lh7a400_mask_irq(struct irq_data *d) -{ - INTC_INTENC = (1 << d->irq); -} - -static void lh7a400_unmask_irq(struct irq_data *d) -{ - INTC_INTENS = (1 << d->irq); -} - -static void lh7a400_ack_gpio_irq(struct irq_data *d) -{ - GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (d->irq)); - INTC_INTENC = (1 << d->irq); -} - -static struct irq_chip lh7a400_internal_chip = { - .name = "MPU", - .irq_ack = lh7a400_mask_irq, /* Level triggering -> mask is ack */ - .irq_mask = lh7a400_mask_irq, - .irq_unmask = lh7a400_unmask_irq, -}; - -static struct irq_chip lh7a400_gpio_chip = { - .name = "GPIO", - .irq_ack = lh7a400_ack_gpio_irq, - .irq_mask = lh7a400_mask_irq, - .irq_unmask = lh7a400_unmask_irq, -}; - - - /* IRQ initialization */ - -void __init lh7a400_init_irq (void) -{ - int irq; - - INTC_INTENC = 0xffffffff; /* Disable all interrupts */ - GPIO_GPIOFINTEN = 0x00; /* Disable all GPIOF interrupts */ - barrier (); - - for (irq = 0; irq < NR_IRQS; ++irq) { - switch (irq) { - case IRQ_GPIO0INTR: - case IRQ_GPIO1INTR: - case IRQ_GPIO2INTR: - case IRQ_GPIO3INTR: - case IRQ_GPIO4INTR: - case IRQ_GPIO5INTR: - case IRQ_GPIO6INTR: - case IRQ_GPIO7INTR: - set_irq_chip (irq, &lh7a400_gpio_chip); - set_irq_handler (irq, handle_level_irq); /* OK default */ - break; - default: - set_irq_chip (irq, &lh7a400_internal_chip); - set_irq_handler (irq, handle_level_irq); - } - set_irq_flags (irq, IRQF_VALID); - } - - lh7a40x_init_board_irq (); - -/* *** FIXME: the LH7a400 does use FIQ interrupts in some cases. For - the time being, these are not initialized. */ - -/* init_FIQ(); */ -} diff --git a/arch/arm/mach-lh7a40x/irq-lh7a404.c b/arch/arm/mach-lh7a40x/irq-lh7a404.c deleted file mode 100644 index 14b173389573..000000000000 --- a/arch/arm/mach-lh7a40x/irq-lh7a404.c +++ /dev/null @@ -1,175 +0,0 @@ -/* arch/arm/mach-lh7a40x/irq-lh7a404.c - * - * Copyright (C) 2004 Logic Product Development - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/interrupt.h> - -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/mach/irq.h> -#include <mach/irqs.h> - -#include "common.h" - -#define USE_PRIORITIES - -/* See Documentation/arm/Sharp-LH/VectoredInterruptController for more - * information on using the vectored interrupt controller's - * prioritizing feature. */ - -static unsigned char irq_pri_vic1[] = { -#if defined (USE_PRIORITIES) - IRQ_GPIO3INTR, /* CPLD */ - IRQ_DMAM2P4, IRQ_DMAM2P5, /* AC97 */ -#endif -}; -static unsigned char irq_pri_vic2[] = { -#if defined (USE_PRIORITIES) - IRQ_T3UI, /* Timer */ - IRQ_GPIO7INTR, /* CPLD */ - IRQ_UART1INTR, IRQ_UART2INTR, IRQ_UART3INTR, - IRQ_LCDINTR, /* LCD */ - IRQ_TSCINTR, /* ADC/Touchscreen */ -#endif -}; - - /* CPU IRQ handling */ - -static void lh7a404_vic1_mask_irq(struct irq_data *d) -{ - VIC1_INTENCLR = (1 << d->irq); -} - -static void lh7a404_vic1_unmask_irq(struct irq_data *d) -{ - VIC1_INTEN = (1 << d->irq); -} - -static void lh7a404_vic2_mask_irq(struct irq_data *d) -{ - VIC2_INTENCLR = (1 << (d->irq - 32)); -} - -static void lh7a404_vic2_unmask_irq(struct irq_data *d) -{ - VIC2_INTEN = (1 << (d->irq - 32)); -} - -static void lh7a404_vic1_ack_gpio_irq(struct irq_data *d) -{ - GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (d->irq)); - VIC1_INTENCLR = (1 << d->irq); -} - -static void lh7a404_vic2_ack_gpio_irq(struct irq_data *d) -{ - GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (d->irq)); - VIC2_INTENCLR = (1 << d->irq); -} - -static struct irq_chip lh7a404_vic1_chip = { - .name = "VIC1", - .irq_ack = lh7a404_vic1_mask_irq, /* Because level-triggered */ - .irq_mask = lh7a404_vic1_mask_irq, - .irq_unmask = lh7a404_vic1_unmask_irq, -}; - -static struct irq_chip lh7a404_vic2_chip = { - .name = "VIC2", - .irq_ack = lh7a404_vic2_mask_irq, /* Because level-triggered */ - .irq_mask = lh7a404_vic2_mask_irq, - .irq_unmask = lh7a404_vic2_unmask_irq, -}; - -static struct irq_chip lh7a404_gpio_vic1_chip = { - .name = "GPIO-VIC1", - .irq_ack = lh7a404_vic1_ack_gpio_irq, - .irq_mask = lh7a404_vic1_mask_irq, - .irq_unmask = lh7a404_vic1_unmask_irq, -}; - -static struct irq_chip lh7a404_gpio_vic2_chip = { - .name = "GPIO-VIC2", - .irq_ack = lh7a404_vic2_ack_gpio_irq, - .irq_mask = lh7a404_vic2_mask_irq, - .irq_unmask = lh7a404_vic2_unmask_irq, -}; - - /* IRQ initialization */ - -#if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404) -extern void* branch_irq_lh7a400; -#endif - -void __init lh7a404_init_irq (void) -{ - int irq; - -#if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404) -#define NOP 0xe1a00000 /* mov r0, r0 */ - branch_irq_lh7a400 = NOP; -#endif - - VIC1_INTENCLR = 0xffffffff; - VIC2_INTENCLR = 0xffffffff; - VIC1_INTSEL = 0; /* All IRQs */ - VIC2_INTSEL = 0; /* All IRQs */ - VIC1_NVADDR = VA_VIC1DEFAULT; - VIC2_NVADDR = VA_VIC2DEFAULT; - VIC1_VECTADDR = 0; - VIC2_VECTADDR = 0; - - GPIO_GPIOFINTEN = 0x00; /* Disable all GPIOF interrupts */ - barrier (); - - /* Install prioritized interrupts, if there are any. */ - /* The | 0x20*/ - for (irq = 0; irq < 16; ++irq) { - (&VIC1_VAD0)[irq] - = (irq < ARRAY_SIZE (irq_pri_vic1)) - ? (irq_pri_vic1[irq] | VA_VECTORED) : 0; - (&VIC1_VECTCNTL0)[irq] - = (irq < ARRAY_SIZE (irq_pri_vic1)) - ? (irq_pri_vic1[irq] | VIC_CNTL_ENABLE) : 0; - (&VIC2_VAD0)[irq] - = (irq < ARRAY_SIZE (irq_pri_vic2)) - ? (irq_pri_vic2[irq] | VA_VECTORED) : 0; - (&VIC2_VECTCNTL0)[irq] - = (irq < ARRAY_SIZE (irq_pri_vic2)) - ? (irq_pri_vic2[irq] | VIC_CNTL_ENABLE) : 0; - } - - for (irq = 0; irq < NR_IRQS; ++irq) { - switch (irq) { - case IRQ_GPIO0INTR: - case IRQ_GPIO1INTR: - case IRQ_GPIO2INTR: - case IRQ_GPIO3INTR: - case IRQ_GPIO4INTR: - case IRQ_GPIO5INTR: - case IRQ_GPIO6INTR: - case IRQ_GPIO7INTR: - set_irq_chip (irq, irq < 32 - ? &lh7a404_gpio_vic1_chip - : &lh7a404_gpio_vic2_chip); - set_irq_handler (irq, handle_level_irq); /* OK default */ - break; - default: - set_irq_chip (irq, irq < 32 - ? &lh7a404_vic1_chip - : &lh7a404_vic2_chip); - set_irq_handler (irq, handle_level_irq); - } - set_irq_flags (irq, IRQF_VALID); - } - - lh7a40x_init_board_irq (); -} diff --git a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c deleted file mode 100644 index 1bfdcddcb93e..000000000000 --- a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c +++ /dev/null @@ -1,128 +0,0 @@ -/* arch/arm/mach-lh7a40x/irq-lpd7a40x.c - * - * Copyright (C) 2004 Coastal Environmental Systems - * Copyright (C) 2004 Logic Product Development - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/interrupt.h> - -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/mach/irq.h> -#include <mach/irqs.h> - -#include "common.h" - -static void lh7a40x_ack_cpld_irq(struct irq_data *d) -{ - /* CPLD doesn't have ack capability */ -} - -static void lh7a40x_mask_cpld_irq(struct irq_data *d) -{ - switch (d->irq) { - case IRQ_LPD7A40X_ETH_INT: - CPLD_INTERRUPTS = CPLD_INTERRUPTS | 0x4; - break; - case IRQ_LPD7A400_TS: - CPLD_INTERRUPTS = CPLD_INTERRUPTS | 0x8; - break; - } -} - -static void lh7a40x_unmask_cpld_irq(struct irq_data *d) -{ - switch (d->irq) { - case IRQ_LPD7A40X_ETH_INT: - CPLD_INTERRUPTS = CPLD_INTERRUPTS & ~ 0x4; - break; - case IRQ_LPD7A400_TS: - CPLD_INTERRUPTS = CPLD_INTERRUPTS & ~ 0x8; - break; - } -} - -static struct irq_chip lh7a40x_cpld_chip = { - .name = "CPLD", - .irq_ack = lh7a40x_ack_cpld_irq, - .irq_mask = lh7a40x_mask_cpld_irq, - .irq_unmask = lh7a40x_unmask_cpld_irq, -}; - -static void lh7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc) -{ - unsigned int mask = CPLD_INTERRUPTS; - - desc->irq_data.chip->ack (irq); - - if ((mask & 0x1) == 0) /* WLAN */ - generic_handle_irq(IRQ_LPD7A40X_ETH_INT); - - if ((mask & 0x2) == 0) /* Touch */ - generic_handle_irq(IRQ_LPD7A400_TS); - - desc->irq_data.chip->unmask (irq); /* Level-triggered need this */ -} - - - /* IRQ initialization */ - -void __init lh7a40x_init_board_irq (void) -{ - int irq; - - /* Rev A (v2.8): PF0, PF1, PF2, and PF3 are available IRQs. - PF7 supports the CPLD. - Rev B (v3.4): PF0, PF1, and PF2 are available IRQs. - PF3 supports the CPLD. - (Some) LPD7A404 prerelease boards report a version - number of 0x16, but we force an override since the - hardware is of the newer variety. - */ - - unsigned char cpld_version = CPLD_REVISION; - int pinCPLD; - -#if defined CONFIG_MACH_LPD7A404 - cpld_version = 0x34; /* Override, for now */ -#endif - pinCPLD = (cpld_version == 0x28) ? 7 : 3; - - /* First, configure user controlled GPIOF interrupts */ - - GPIO_PFDD &= ~0x0f; /* PF0-3 are inputs */ - GPIO_INTTYPE1 &= ~0x0f; /* PF0-3 are level triggered */ - GPIO_INTTYPE2 &= ~0x0f; /* PF0-3 are active low */ - barrier (); - GPIO_GPIOFINTEN |= 0x0f; /* Enable PF0, PF1, PF2, and PF3 IRQs */ - - /* Then, configure CPLD interrupt */ - - CPLD_INTERRUPTS = 0x0c; /* Disable all CPLD interrupts */ - GPIO_PFDD &= ~(1 << pinCPLD); /* Make input */ - GPIO_INTTYPE1 |= (1 << pinCPLD); /* Edge triggered */ - GPIO_INTTYPE2 &= ~(1 << pinCPLD); /* Active low */ - barrier (); - GPIO_GPIOFINTEN |= (1 << pinCPLD); /* Enable */ - - /* Cascade CPLD interrupts */ - - for (irq = IRQ_BOARD_START; - irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) { - set_irq_chip (irq, &lh7a40x_cpld_chip); - set_irq_handler (irq, handle_edge_irq); - set_irq_flags (irq, IRQF_VALID); - } - - set_irq_chained_handler ((cpld_version == 0x28) - ? IRQ_CPLD_V28 - : IRQ_CPLD_V34, - lh7a40x_cpld_handler); -} diff --git a/arch/arm/mach-lh7a40x/lcd-panel.h b/arch/arm/mach-lh7a40x/lcd-panel.h deleted file mode 100644 index a7f5027b2f78..000000000000 --- a/arch/arm/mach-lh7a40x/lcd-panel.h +++ /dev/null @@ -1,345 +0,0 @@ -/* lcd-panel.h - - written by Marc Singer - 18 Jul 2005 - - Copyright (C) 2005 Marc Singer - - ----------- - DESCRIPTION - ----------- - - Only one panel may be defined at a time. - - The pixel clock is calculated to be no greater than the target. - - Each timing value is accompanied by a specification comment. - - UNITS/MIN/TYP/MAX - - Most of the units will be in clocks. - - USE_RGB555 - - Define this macro to configure the AMBA LCD controller to use an - RGB555 encoding for the pels instead of the normal RGB565. - - LPD9520, LPD79524, LPD7A400, LPD7A404-10, LPD7A404-11 - - These boards are best approximated by 555 for all panels. Some - can use an extra low-order bit of blue in bit 16 of the color - value, but we don't have a way to communicate this non-linear - mapping to the kernel. - -*/ - -#if !defined (__LCD_PANEL_H__) -# define __LCD_PANEL_H__ - -#if defined (MACH_LPD79520)\ - || defined (MACH_LPD79524)\ - || defined (MACH_LPD7A400)\ - || defined (MACH_LPD7A404) -# define USE_RGB555 -#endif - -struct clcd_panel_extra { - unsigned int hrmode; - unsigned int clsen; - unsigned int spsen; - unsigned int pcdel; - unsigned int revdel; - unsigned int lpdel; - unsigned int spldel; - unsigned int pc2del; -}; - -#define NS_TO_CLOCK(ns,c) ((((ns)*((c)/1000) + (1000000 - 1))/1000000)) -#define CLOCK_TO_DIV(e,c) (((c) + (e) - 1)/(e)) - -#if defined CONFIG_FB_ARMCLCD_SHARP_LQ035Q7DB02_HRTFT - - /* Logic Product Development LCD 3.5" QVGA HRTFT -10 */ - /* Sharp PN LQ035Q7DB02 w/HRTFT controller chip */ - -#define PIX_CLOCK_TARGET (6800000) -#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) -#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER) - -static struct clcd_panel lcd_panel = { - .mode = { - .name = "3.5in QVGA (LQ035Q7DB02)", - .xres = 240, - .yres = 320, - .pixclock = PIX_CLOCK, - .left_margin = 16, - .right_margin = 21, - .upper_margin = 8, // line/8/8/8 - .lower_margin = 5, - .hsync_len = 61, - .vsync_len = NS_TO_CLOCK (60, PIX_CLOCK), - .vmode = FB_VMODE_NONINTERLACED, - }, - .width = -1, - .height = -1, - .tim2 = TIM2_IPC | (PIX_CLOCK_DIVIDER - 2), - .cntl = CNTL_LCDTFT | CNTL_WATERMARK, - .bpp = 16, -}; - -#define HAS_LCD_PANEL_EXTRA - -static struct clcd_panel_extra lcd_panel_extra = { - .hrmode = 1, - .clsen = 1, - .spsen = 1, - .pcdel = 8, - .revdel = 7, - .lpdel = 13, - .spldel = 77, - .pc2del = 208, -}; - -#endif - -#if defined CONFIG_FB_ARMCLCD_SHARP_LQ057Q3DC02 - - /* Logic Product Development LCD 5.7" QVGA -10 */ - /* Sharp PN LQ057Q3DC02 */ - /* QVGA mode, V/Q=LOW */ - -/* From Sharp on 2006.1.3. I believe some of the values are incorrect - * based on the datasheet. - - Timing0 TIMING1 TIMING2 CONTROL - 0x140A0C4C 0x080504EF 0x013F380D 0x00000829 - HBP= 20 VBP= 8 BCD= 0 - HFP= 10 VFP= 5 CPL=319 - HSW= 12 VSW= 1 IOE= 0 - PPL= 19 LPP=239 IPC= 1 - IHS= 1 - IVS= 1 - ACB= 0 - CSEL= 0 - PCD= 13 - - */ - -/* The full horizontal cycle (Th) is clock/360/400/450. */ -/* The full vertical cycle (Tv) is line/251/262/280. */ - -#define PIX_CLOCK_TARGET (6300000) /* -/6.3/7 MHz */ -#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) -#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER) - -static struct clcd_panel lcd_panel = { - .mode = { - .name = "5.7in QVGA (LQ057Q3DC02)", - .xres = 320, - .yres = 240, - .pixclock = PIX_CLOCK, - .left_margin = 11, - .right_margin = 400-11-320-2, - .upper_margin = 7, // line/7/7/7 - .lower_margin = 262-7-240-2, - .hsync_len = 2, // clk/2/96/200 - .vsync_len = 2, // line/2/-/34 - .vmode = FB_VMODE_NONINTERLACED, - }, - .width = -1, - .height = -1, - .tim2 = TIM2_IHS | TIM2_IVS - | (PIX_CLOCK_DIVIDER - 2), - .cntl = CNTL_LCDTFT | CNTL_WATERMARK, - .bpp = 16, -}; - -#endif - -#if defined CONFIG_FB_ARMCLCD_SHARP_LQ64D343 - - /* Logic Product Development LCD 6.4" VGA -10 */ - /* Sharp PN LQ64D343 */ - -/* The full horizontal cycle (Th) is clock/750/800/900. */ -/* The full vertical cycle (Tv) is line/515/525/560. */ - -#define PIX_CLOCK_TARGET (28330000) -#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) -#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER) - -static struct clcd_panel lcd_panel = { - .mode = { - .name = "6.4in QVGA (LQ64D343)", - .xres = 640, - .yres = 480, - .pixclock = PIX_CLOCK, - .left_margin = 32, - .right_margin = 800-32-640-96, - .upper_margin = 32, // line/34/34/34 - .lower_margin = 540-32-480-2, - .hsync_len = 96, // clk/2/96/200 - .vsync_len = 2, // line/2/-/34 - .vmode = FB_VMODE_NONINTERLACED, - }, - .width = -1, - .height = -1, - .tim2 = TIM2_IHS | TIM2_IVS - | (PIX_CLOCK_DIVIDER - 2), - .cntl = CNTL_LCDTFT | CNTL_WATERMARK, - .bpp = 16, -}; - -#endif - -#if defined CONFIG_FB_ARMCLCD_SHARP_LQ10D368 - - /* Logic Product Development LCD 10.4" VGA -10 */ - /* Sharp PN LQ10D368 */ - -#define PIX_CLOCK_TARGET (28330000) -#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) -#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER) - -static struct clcd_panel lcd_panel = { - .mode = { - .name = "10.4in VGA (LQ10D368)", - .xres = 640, - .yres = 480, - .pixclock = PIX_CLOCK, - .left_margin = 21, - .right_margin = 15, - .upper_margin = 34, - .lower_margin = 5, - .hsync_len = 96, - .vsync_len = 16, - .vmode = FB_VMODE_NONINTERLACED, - }, - .width = -1, - .height = -1, - .tim2 = TIM2_IHS | TIM2_IVS - | (PIX_CLOCK_DIVIDER - 2), - .cntl = CNTL_LCDTFT | CNTL_WATERMARK, - .bpp = 16, -}; - -#endif - -#if defined CONFIG_FB_ARMCLCD_SHARP_LQ121S1DG41 - - /* Logic Product Development LCD 12.1" SVGA -10 */ - /* Sharp PN LQ121S1DG41, was LQ121S1DG31 */ - -/* Note that with a 99993900 Hz HCLK, it is not possible to hit the - * target clock frequency range of 35MHz to 42MHz. */ - -/* If the target pixel clock is substantially lower than the panel - * spec, this is done to prevent the LCD display from glitching when - * the CPU is under load. A pixel clock higher than 25MHz - * (empirically determined) will compete with the CPU for bus cycles - * for the Ethernet chip. However, even a pixel clock of 10MHz - * competes with Compact Flash interface during some operations - * (fdisk, e2fsck). And, at that speed the display may have a visible - * flicker. */ - -/* The full horizontal cycle (Th) is clock/832/1056/1395. */ - -#define PIX_CLOCK_TARGET (20000000) -#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) -#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER) - -static struct clcd_panel lcd_panel = { - .mode = { - .name = "12.1in SVGA (LQ121S1DG41)", - .xres = 800, - .yres = 600, - .pixclock = PIX_CLOCK, - .left_margin = 89, // ns/5/-/(1/PIX_CLOCK)-10 - .right_margin = 1056-800-89-128, - .upper_margin = 23, // line/23/23/23 - .lower_margin = 44, - .hsync_len = 128, // clk/2/128/200 - .vsync_len = 4, // line/2/4/6 - .vmode = FB_VMODE_NONINTERLACED, - }, - .width = -1, - .height = -1, - .tim2 = TIM2_IHS | TIM2_IVS - | (PIX_CLOCK_DIVIDER - 2), - .cntl = CNTL_LCDTFT | CNTL_WATERMARK, - .bpp = 16, -}; - -#endif - -#if defined CONFIG_FB_ARMCLCD_HITACHI - - /* Hitachi*/ - /* Submitted by Michele Da Rold <michele.darold@ecsproject.com> */ - -#define PIX_CLOCK_TARGET (49000000) -#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) -#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER) - -static struct clcd_panel lcd_panel = { - .mode = { - .name = "Hitachi 800x480", - .xres = 800, - .yres = 480, - .pixclock = PIX_CLOCK, - .left_margin = 88, - .right_margin = 40, - .upper_margin = 32, - .lower_margin = 11, - .hsync_len = 128, - .vsync_len = 2, - .vmode = FB_VMODE_NONINTERLACED, - }, - .width = -1, - .height = -1, - .tim2 = TIM2_IPC | TIM2_IHS | TIM2_IVS - | (PIX_CLOCK_DIVIDER - 2), - .cntl = CNTL_LCDTFT | CNTL_WATERMARK, - .bpp = 16, -}; - -#endif - - -#if defined CONFIG_FB_ARMCLCD_AUO_A070VW01_WIDE - - /* AU Optotronics A070VW01 7.0 Wide Screen color Display*/ - /* Submitted by Michele Da Rold <michele.darold@ecsproject.com> */ - -#define PIX_CLOCK_TARGET (10000000) -#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) -#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER) - -static struct clcd_panel lcd_panel = { - .mode = { - .name = "7.0in Wide (A070VW01)", - .xres = 480, - .yres = 234, - .pixclock = PIX_CLOCK, - .left_margin = 30, - .right_margin = 25, - .upper_margin = 14, - .lower_margin = 12, - .hsync_len = 100, - .vsync_len = 1, - .vmode = FB_VMODE_NONINTERLACED, - }, - .width = -1, - .height = -1, - .tim2 = TIM2_IPC | TIM2_IHS | TIM2_IVS - | (PIX_CLOCK_DIVIDER - 2), - .cntl = CNTL_LCDTFT | CNTL_WATERMARK, - .bpp = 16, -}; - -#endif - -#undef NS_TO_CLOCK -#undef CLOCK_TO_DIV - -#endif /* __LCD_PANEL_H__ */ diff --git a/arch/arm/mach-lh7a40x/ssp-cpld.c b/arch/arm/mach-lh7a40x/ssp-cpld.c deleted file mode 100644 index 2901d49d1484..000000000000 --- a/arch/arm/mach-lh7a40x/ssp-cpld.c +++ /dev/null @@ -1,343 +0,0 @@ -/* arch/arm/mach-lh7a40x/ssp-cpld.c - * - * Copyright (C) 2004,2005 Marc Singer - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * SSP/SPI driver for the CardEngine CPLD. - * - */ - -/* NOTES - ----- - - o *** This driver is cribbed from the 7952x implementation. - Some comments may not apply. - - o This driver contains sufficient logic to control either the - serial EEPROMs or the audio codec. It is included in the kernel - to support the codec. The EEPROMs are really the responsibility - of the boot loader and should probably be left alone. - - o The code must be augmented to cope with multiple, simultaneous - clients. - o The audio codec writes to the codec chip whenever playback - starts. - o The touchscreen driver writes to the ads chip every time it - samples. - o The audio codec must write 16 bits, but the touch chip writes - are 8 bits long. - o We need to be able to keep these configurations separate while - simultaneously active. - - */ - -#include <linux/module.h> -#include <linux/kernel.h> -//#include <linux/sched.h> -#include <linux/errno.h> -#include <linux/interrupt.h> -//#include <linux/ioport.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/spinlock.h> -#include <linux/io.h> - -#include <asm/irq.h> -#include <mach/hardware.h> - -#include <mach/ssp.h> - -//#define TALK - -#if defined (TALK) -#define PRINTK(f...) printk (f) -#else -#define PRINTK(f...) do {} while (0) -#endif - -#if defined (CONFIG_ARCH_LH7A400) -# define CPLD_SPID __REGP16(CPLD06_VIRT) /* SPI data */ -# define CPLD_SPIC __REGP16(CPLD08_VIRT) /* SPI control */ -# define CPLD_SPIC_CS_CODEC (1<<0) -# define CPLD_SPIC_CS_TOUCH (1<<1) -# define CPLD_SPIC_WRITE (0<<2) -# define CPLD_SPIC_READ (1<<2) -# define CPLD_SPIC_DONE (1<<3) /* r/o */ -# define CPLD_SPIC_LOAD (1<<4) -# define CPLD_SPIC_START (1<<4) -# define CPLD_SPIC_LOADED (1<<5) /* r/o */ -#endif - -#define CPLD_SPI __REGP16(CPLD0A_VIRT) /* SPI operation */ -#define CPLD_SPI_CS_EEPROM (1<<3) -#define CPLD_SPI_SCLK (1<<2) -#define CPLD_SPI_TX_SHIFT (1) -#define CPLD_SPI_TX (1<<CPLD_SPI_TX_SHIFT) -#define CPLD_SPI_RX_SHIFT (0) -#define CPLD_SPI_RX (1<<CPLD_SPI_RX_SHIFT) - -/* *** FIXME: these timing values are substantially larger than the - *** chip requires. We may implement an nsleep () function. */ -#define T_SKH 1 /* Clock time high (us) */ -#define T_SKL 1 /* Clock time low (us) */ -#define T_CS 1 /* Minimum chip select low time (us) */ -#define T_CSS 1 /* Minimum chip select setup time (us) */ -#define T_DIS 1 /* Data setup time (us) */ - - /* EEPROM SPI bits */ -#define P_START (1<<9) -#define P_WRITE (1<<7) -#define P_READ (2<<7) -#define P_ERASE (3<<7) -#define P_EWDS (0<<7) -#define P_WRAL (0<<7) -#define P_ERAL (0<<7) -#define P_EWEN (0<<7) -#define P_A_EWDS (0<<5) -#define P_A_WRAL (1<<5) -#define P_A_ERAL (2<<5) -#define P_A_EWEN (3<<5) - -struct ssp_configuration { - int device; - int mode; - int speed; - int frame_size_write; - int frame_size_read; -}; - -static struct ssp_configuration ssp_configuration; -static spinlock_t ssp_lock; - -static void enable_cs (void) -{ - switch (ssp_configuration.device) { - case DEVICE_EEPROM: - CPLD_SPI |= CPLD_SPI_CS_EEPROM; - break; - } - udelay (T_CSS); -} - -static void disable_cs (void) -{ - switch (ssp_configuration.device) { - case DEVICE_EEPROM: - CPLD_SPI &= ~CPLD_SPI_CS_EEPROM; - break; - } - udelay (T_CS); -} - -static void pulse_clock (void) -{ - CPLD_SPI |= CPLD_SPI_SCLK; - udelay (T_SKH); - CPLD_SPI &= ~CPLD_SPI_SCLK; - udelay (T_SKL); -} - - -/* execute_spi_command - - sends an spi command to a device. It first sends cwrite bits from - v. If cread is greater than zero it will read cread bits - (discarding the leading 0 bit) and return them. If cread is less - than zero it will check for completetion status and return 0 on - success or -1 on timeout. If cread is zero it does nothing other - than sending the command. - - On the LPD7A400, we can only read or write multiples of 8 bits on - the codec and the touch screen device. Here, we round up. - -*/ - -static int execute_spi_command (int v, int cwrite, int cread) -{ - unsigned long l = 0; - -#if defined (CONFIG_MACH_LPD7A400) - /* The codec and touch devices cannot be bit-banged. Instead, - * the CPLD provides an eight-bit shift register and a crude - * interface. */ - if ( ssp_configuration.device == DEVICE_CODEC - || ssp_configuration.device == DEVICE_TOUCH) { - int select = 0; - - PRINTK ("spi(%d %d.%d) 0x%04x", - ssp_configuration.device, cwrite, cread, - v); -#if defined (TALK) - if (ssp_configuration.device == DEVICE_CODEC) - PRINTK (" 0x%03x -> %2d", v & 0x1ff, (v >> 9) & 0x7f); -#endif - PRINTK ("\n"); - - if (ssp_configuration.device == DEVICE_CODEC) - select = CPLD_SPIC_CS_CODEC; - if (ssp_configuration.device == DEVICE_TOUCH) - select = CPLD_SPIC_CS_TOUCH; - if (cwrite) { - for (cwrite = (cwrite + 7)/8; cwrite-- > 0; ) { - CPLD_SPID = (v >> (8*cwrite)) & 0xff; - CPLD_SPIC = select | CPLD_SPIC_LOAD; - while (!(CPLD_SPIC & CPLD_SPIC_LOADED)) - ; - CPLD_SPIC = select; - while (!(CPLD_SPIC & CPLD_SPIC_DONE)) - ; - } - v = 0; - } - if (cread) { - mdelay (2); /* *** FIXME: required by ads7843? */ - v = 0; - for (cread = (cread + 7)/8; cread-- > 0;) { - CPLD_SPID = 0; - CPLD_SPIC = select | CPLD_SPIC_READ - | CPLD_SPIC_START; - while (!(CPLD_SPIC & CPLD_SPIC_LOADED)) - ; - CPLD_SPIC = select | CPLD_SPIC_READ; - while (!(CPLD_SPIC & CPLD_SPIC_DONE)) - ; - v = (v << 8) | CPLD_SPID; - } - } - return v; - } -#endif - - PRINTK ("spi(%d) 0x%04x -> 0x%x\r\n", ssp_configuration.device, - v & 0x1ff, (v >> 9) & 0x7f); - - enable_cs (); - - v <<= CPLD_SPI_TX_SHIFT; /* Correction for position of SPI_TX bit */ - while (cwrite--) { - CPLD_SPI - = (CPLD_SPI & ~CPLD_SPI_TX) - | ((v >> cwrite) & CPLD_SPI_TX); - udelay (T_DIS); - pulse_clock (); - } - - if (cread < 0) { - int delay = 10; - disable_cs (); - udelay (1); - enable_cs (); - - l = -1; - do { - if (CPLD_SPI & CPLD_SPI_RX) { - l = 0; - break; - } - } while (udelay (1), --delay); - } - else - /* We pulse the clock before the data to skip the leading zero. */ - while (cread-- > 0) { - pulse_clock (); - l = (l<<1) - | (((CPLD_SPI & CPLD_SPI_RX) - >> CPLD_SPI_RX_SHIFT) & 0x1); - } - - disable_cs (); - return l; -} - -static int ssp_init (void) -{ - spin_lock_init (&ssp_lock); - memset (&ssp_configuration, 0, sizeof (ssp_configuration)); - return 0; -} - - -/* ssp_chip_select - - drops the chip select line for the CPLD shift-register controlled - devices. It doesn't enable chip - -*/ - -static void ssp_chip_select (int enable) -{ -#if defined (CONFIG_MACH_LPD7A400) - int select; - - if (ssp_configuration.device == DEVICE_CODEC) - select = CPLD_SPIC_CS_CODEC; - else if (ssp_configuration.device == DEVICE_TOUCH) - select = CPLD_SPIC_CS_TOUCH; - else - return; - - if (enable) - CPLD_SPIC = select; - else - CPLD_SPIC = 0; -#endif -} - -static void ssp_acquire (void) -{ - spin_lock (&ssp_lock); -} - -static void ssp_release (void) -{ - ssp_chip_select (0); /* just in case */ - spin_unlock (&ssp_lock); -} - -static int ssp_configure (int device, int mode, int speed, - int frame_size_write, int frame_size_read) -{ - ssp_configuration.device = device; - ssp_configuration.mode = mode; - ssp_configuration.speed = speed; - ssp_configuration.frame_size_write = frame_size_write; - ssp_configuration.frame_size_read = frame_size_read; - - return 0; -} - -static int ssp_read (void) -{ - return execute_spi_command (0, 0, ssp_configuration.frame_size_read); -} - -static int ssp_write (u16 data) -{ - execute_spi_command (data, ssp_configuration.frame_size_write, 0); - return 0; -} - -static int ssp_write_read (u16 data) -{ - return execute_spi_command (data, ssp_configuration.frame_size_write, - ssp_configuration.frame_size_read); -} - -struct ssp_driver lh7a40x_cpld_ssp_driver = { - .init = ssp_init, - .acquire = ssp_acquire, - .release = ssp_release, - .configure = ssp_configure, - .chip_select = ssp_chip_select, - .read = ssp_read, - .write = ssp_write, - .write_read = ssp_write_read, -}; - - -MODULE_AUTHOR("Marc Singer"); -MODULE_DESCRIPTION("LPD7A40X CPLD SPI driver"); -MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-lh7a40x/time.c b/arch/arm/mach-lh7a40x/time.c deleted file mode 100644 index 4601e425bae3..000000000000 --- a/arch/arm/mach-lh7a40x/time.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * arch/arm/mach-lh7a40x/time.c - * - * Copyright (C) 2004 Logic Product Development - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/time.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/leds.h> - -#include <asm/mach/time.h> -#include "common.h" - -#if HZ < 100 -# define TIMER_CONTROL TIMER_CONTROL2 -# define TIMER_LOAD TIMER_LOAD2 -# define TIMER_CONSTANT (508469/HZ) -# define TIMER_MODE (TIMER_C_ENABLE | TIMER_C_PERIODIC | TIMER_C_508KHZ) -# define TIMER_EOI TIMER_EOI2 -# define TIMER_IRQ IRQ_T2UI -#else -# define TIMER_CONTROL TIMER_CONTROL3 -# define TIMER_LOAD TIMER_LOAD3 -# define TIMER_CONSTANT (3686400/HZ) -# define TIMER_MODE (TIMER_C_ENABLE | TIMER_C_PERIODIC) -# define TIMER_EOI TIMER_EOI3 -# define TIMER_IRQ IRQ_T3UI -#endif - -static irqreturn_t -lh7a40x_timer_interrupt(int irq, void *dev_id) -{ - TIMER_EOI = 0; - timer_tick(); - - return IRQ_HANDLED; -} - -static struct irqaction lh7a40x_timer_irq = { - .name = "LHA740x Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = lh7a40x_timer_interrupt, -}; - -static void __init lh7a40x_timer_init (void) -{ - /* Stop/disable all timers */ - TIMER_CONTROL1 = 0; - TIMER_CONTROL2 = 0; - TIMER_CONTROL3 = 0; - - setup_irq (TIMER_IRQ, &lh7a40x_timer_irq); - - TIMER_LOAD = TIMER_CONSTANT; - TIMER_CONTROL = TIMER_MODE; -} - -struct sys_timer lh7a40x_timer = { - .init = &lh7a40x_timer_init, -}; diff --git a/arch/arm/mach-loki/include/mach/memory.h b/arch/arm/mach-loki/include/mach/memory.h index 2ed7e6e732c2..66366657a875 100644 --- a/arch/arm/mach-loki/include/mach/memory.h +++ b/arch/arm/mach-loki/include/mach/memory.h @@ -5,6 +5,6 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif diff --git a/arch/arm/mach-lpc32xx/include/mach/memory.h b/arch/arm/mach-lpc32xx/include/mach/memory.h index 044e1acecbe6..a647dd624afa 100644 --- a/arch/arm/mach-lpc32xx/include/mach/memory.h +++ b/arch/arm/mach-lpc32xx/include/mach/memory.h @@ -22,6 +22,6 @@ /* * Physical DRAM offset of bank 0 */ -#define PHYS_OFFSET UL(0x80000000) +#define PLAT_PHYS_OFFSET UL(0x80000000) #endif diff --git a/arch/arm/mach-mmp/include/mach/memory.h b/arch/arm/mach-mmp/include/mach/memory.h index bdb21d70714c..d68b50a2d6a0 100644 --- a/arch/arm/mach-mmp/include/mach/memory.h +++ b/arch/arm/mach-mmp/include/mach/memory.h @@ -9,6 +9,6 @@ #ifndef __ASM_MACH_MEMORY_H #define __ASM_MACH_MEMORY_H -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif /* __ASM_MACH_MEMORY_H */ diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c index e7a76eff57d9..08fcd40a8cbd 100644 --- a/arch/arm/mach-msm/board-msm7x27.c +++ b/arch/arm/mach-msm/board-msm7x27.c @@ -132,7 +132,7 @@ static void __init msm7x2x_map_io(void) MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF") #ifdef CONFIG_MSM_DEBUG_UART #endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = msm7x2x_map_io, .init_irq = msm7x2x_init_irq, .init_machine = msm7x2x_init, @@ -142,7 +142,7 @@ MACHINE_END MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA") #ifdef CONFIG_MSM_DEBUG_UART #endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = msm7x2x_map_io, .init_irq = msm7x2x_init_irq, .init_machine = msm7x2x_init, @@ -152,7 +152,7 @@ MACHINE_END MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF") #ifdef CONFIG_MSM_DEBUG_UART #endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = msm7x2x_map_io, .init_irq = msm7x2x_init_irq, .init_machine = msm7x2x_init, @@ -162,7 +162,7 @@ MACHINE_END MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA") #ifdef CONFIG_MSM_DEBUG_UART #endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = msm7x2x_map_io, .init_irq = msm7x2x_init_irq, .init_machine = msm7x2x_init, diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c index 6f3b9735e970..25db8fd71a70 100644 --- a/arch/arm/mach-msm/board-msm7x30.c +++ b/arch/arm/mach-msm/board-msm7x30.c @@ -26,11 +26,11 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> +#include <asm/memory.h> #include <asm/setup.h> #include <mach/gpio.h> #include <mach/board.h> -#include <mach/memory.h> #include <mach/msm_iomap.h> #include <mach/dma.h> @@ -85,7 +85,7 @@ static void __init msm7x30_map_io(void) MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF") #ifdef CONFIG_MSM_DEBUG_UART #endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = msm7x30_map_io, .init_irq = msm7x30_init_irq, .init_machine = msm7x30_init, @@ -95,7 +95,7 @@ MACHINE_END MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA") #ifdef CONFIG_MSM_DEBUG_UART #endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = msm7x30_map_io, .init_irq = msm7x30_init_irq, .init_machine = msm7x30_init, @@ -105,7 +105,7 @@ MACHINE_END MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID") #ifdef CONFIG_MSM_DEBUG_UART #endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = msm7x30_map_io, .init_irq = msm7x30_init_irq, .init_machine = msm7x30_init, diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index 6dde8185205f..15c2bbd2ef81 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c @@ -118,7 +118,7 @@ static void __init qsd8x50_init(void) MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF") #ifdef CONFIG_MSM_DEBUG_UART #endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = qsd8x50_map_io, .init_irq = qsd8x50_init_irq, .init_machine = qsd8x50_init, @@ -128,7 +128,7 @@ MACHINE_END MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5") #ifdef CONFIG_MSM_DEBUG_UART #endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = qsd8x50_map_io, .init_irq = qsd8x50_init_irq, .init_machine = qsd8x50_init, diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c index 8919ffb17196..83604f526f0f 100644 --- a/arch/arm/mach-msm/board-sapphire.c +++ b/arch/arm/mach-msm/board-sapphire.c @@ -107,7 +107,7 @@ MACHINE_START(SAPPHIRE, "sapphire") /* Maintainer: Brian Swetland <swetland@google.com> */ #ifdef CONFIG_MSM_DEBUG_UART #endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .fixup = sapphire_fixup, .map_io = sapphire_map_io, .init_irq = sapphire_init_irq, diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h index 070e17d237f1..176875df241f 100644 --- a/arch/arm/mach-msm/include/mach/memory.h +++ b/arch/arm/mach-msm/include/mach/memory.h @@ -18,15 +18,15 @@ /* physical offset of RAM */ #if defined(CONFIG_ARCH_QSD8X50) && defined(CONFIG_MSM_SOC_REV_A) -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #elif defined(CONFIG_ARCH_QSD8X50) -#define PHYS_OFFSET UL(0x20000000) +#define PLAT_PHYS_OFFSET UL(0x20000000) #elif defined(CONFIG_ARCH_MSM7X30) -#define PHYS_OFFSET UL(0x00200000) +#define PLAT_PHYS_OFFSET UL(0x00200000) #elif defined(CONFIG_ARCH_MSM8X60) -#define PHYS_OFFSET UL(0x40200000) +#define PLAT_PHYS_OFFSET UL(0x40200000) #else -#define PHYS_OFFSET UL(0x10000000) +#define PLAT_PHYS_OFFSET UL(0x10000000) #endif #endif diff --git a/arch/arm/mach-mv78xx0/include/mach/memory.h b/arch/arm/mach-mv78xx0/include/mach/memory.h index e663042d307f..a648c51f2e42 100644 --- a/arch/arm/mach-mv78xx0/include/mach/memory.h +++ b/arch/arm/mach-mv78xx0/include/mach/memory.h @@ -5,6 +5,6 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c index a5f3eb24e4d5..df1a6ce8e3e1 100644 --- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c +++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c @@ -27,6 +27,7 @@ #include <asm/irq.h> #include <asm/mach-types.h> +#include <asm/memory.h> #include <asm/setup.h> #include <asm/mach/arch.h> #include <asm/mach/irq.h> @@ -36,7 +37,6 @@ #include <mach/clock.h> #include <mach/common.h> #include <mach/iomux-mx3.h> -#include <mach/memory.h> #include "devices-imx31.h" #include "devices.h" diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c index cb0c0e83a527..61991e4dde44 100644 --- a/arch/arm/mach-mxs/gpio.c +++ b/arch/arm/mach-mxs/gpio.c @@ -68,29 +68,29 @@ static void set_gpio_irqenable(struct mxs_gpio_port *port, u32 index, } } -static void mxs_gpio_ack_irq(u32 irq) +static void mxs_gpio_ack_irq(struct irq_data *d) { - u32 gpio = irq_to_gpio(irq); + u32 gpio = irq_to_gpio(d->irq); clear_gpio_irqstatus(&mxs_gpio_ports[gpio / 32], gpio & 0x1f); } -static void mxs_gpio_mask_irq(u32 irq) +static void mxs_gpio_mask_irq(struct irq_data *d) { - u32 gpio = irq_to_gpio(irq); + u32 gpio = irq_to_gpio(d->irq); set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 0); } -static void mxs_gpio_unmask_irq(u32 irq) +static void mxs_gpio_unmask_irq(struct irq_data *d) { - u32 gpio = irq_to_gpio(irq); + u32 gpio = irq_to_gpio(d->irq); set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 1); } static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset); -static int mxs_gpio_set_irq_type(u32 irq, u32 type) +static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type) { - u32 gpio = irq_to_gpio(irq); + u32 gpio = irq_to_gpio(d->irq); u32 pin_mask = 1 << (gpio & 31); struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32]; void __iomem *pin_addr; @@ -160,9 +160,9 @@ static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc) * @param enable enable as wake-up if equal to non-zero * @return This function returns 0 on success. */ -static int mxs_gpio_set_wake_irq(u32 irq, u32 enable) +static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable) { - u32 gpio = irq_to_gpio(irq); + u32 gpio = irq_to_gpio(d->irq); u32 gpio_idx = gpio & 0x1f; struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32]; @@ -182,11 +182,11 @@ static int mxs_gpio_set_wake_irq(u32 irq, u32 enable) } static struct irq_chip gpio_irq_chip = { - .ack = mxs_gpio_ack_irq, - .mask = mxs_gpio_mask_irq, - .unmask = mxs_gpio_unmask_irq, - .set_type = mxs_gpio_set_irq_type, - .set_wake = mxs_gpio_set_wake_irq, + .irq_ack = mxs_gpio_ack_irq, + .irq_mask = mxs_gpio_mask_irq, + .irq_unmask = mxs_gpio_unmask_irq, + .irq_set_type = mxs_gpio_set_irq_type, + .irq_set_wake = mxs_gpio_set_wake_irq, }; static void mxs_set_gpio_direction(struct gpio_chip *chip, unsigned offset, diff --git a/arch/arm/mach-mxs/icoll.c b/arch/arm/mach-mxs/icoll.c index 5dd43ba70058..0f4c120fc169 100644 --- a/arch/arm/mach-mxs/icoll.c +++ b/arch/arm/mach-mxs/icoll.c @@ -34,7 +34,7 @@ static void __iomem *icoll_base = MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR); -static void icoll_ack_irq(unsigned int irq) +static void icoll_ack_irq(struct irq_data *d) { /* * The Interrupt Collector is able to prioritize irqs. @@ -45,22 +45,22 @@ static void icoll_ack_irq(unsigned int irq) icoll_base + HW_ICOLL_LEVELACK); } -static void icoll_mask_irq(unsigned int irq) +static void icoll_mask_irq(struct irq_data *d) { __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, - icoll_base + HW_ICOLL_INTERRUPTn_CLR(irq)); + icoll_base + HW_ICOLL_INTERRUPTn_CLR(d->irq)); } -static void icoll_unmask_irq(unsigned int irq) +static void icoll_unmask_irq(struct irq_data *d) { __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, - icoll_base + HW_ICOLL_INTERRUPTn_SET(irq)); + icoll_base + HW_ICOLL_INTERRUPTn_SET(d->irq)); } static struct irq_chip mxs_icoll_chip = { - .ack = icoll_ack_irq, - .mask = icoll_mask_irq, - .unmask = icoll_unmask_irq, + .irq_ack = icoll_ack_irq, + .irq_mask = icoll_mask_irq, + .irq_unmask = icoll_unmask_irq, }; void __init icoll_init_irq(void) diff --git a/arch/arm/mach-netx/include/mach/memory.h b/arch/arm/mach-netx/include/mach/memory.h index 9a363f297f90..59561496c36e 100644 --- a/arch/arm/mach-netx/include/mach/memory.h +++ b/arch/arm/mach-netx/include/mach/memory.h @@ -20,7 +20,7 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x80000000) +#define PLAT_PHYS_OFFSET UL(0x80000000) #endif diff --git a/arch/arm/mach-nomadik/include/mach/memory.h b/arch/arm/mach-nomadik/include/mach/memory.h index 1e5689d98ecd..d3325211ba6a 100644 --- a/arch/arm/mach-nomadik/include/mach/memory.h +++ b/arch/arm/mach-nomadik/include/mach/memory.h @@ -23,6 +23,6 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif diff --git a/arch/arm/mach-ns9xxx/include/mach/memory.h b/arch/arm/mach-ns9xxx/include/mach/memory.h index 6107193adbfe..5c65aee6e7a9 100644 --- a/arch/arm/mach-ns9xxx/include/mach/memory.h +++ b/arch/arm/mach-ns9xxx/include/mach/memory.h @@ -19,6 +19,6 @@ #define NS9XXX_CS2STAT_LENGTH UL(0x1000) #define NS9XXX_CS3STAT_LENGTH UL(0x1000) -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif diff --git a/arch/arm/mach-nuc93x/include/mach/memory.h b/arch/arm/mach-nuc93x/include/mach/memory.h index 323ab0db3f7d..ef9864b002a6 100644 --- a/arch/arm/mach-nuc93x/include/mach/memory.h +++ b/arch/arm/mach-nuc93x/include/mach/memory.h @@ -16,6 +16,6 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif diff --git a/arch/arm/mach-omap1/include/mach/debug-macro.S b/arch/arm/mach-omap1/include/mach/debug-macro.S index 6a0fa0462365..62856044eb63 100644 --- a/arch/arm/mach-omap1/include/mach/debug-macro.S +++ b/arch/arm/mach-omap1/include/mach/debug-macro.S @@ -17,6 +17,9 @@ #include <plat/serial.h> +#define omap_uart_v2p(x) ((x) - PAGE_OFFSET + PLAT_PHYS_OFFSET) +#define omap_uart_p2v(x) ((x) - PLAT_PHYS_OFFSET + PAGE_OFFSET) + .pushsection .data omap_uart_phys: .word 0x0 omap_uart_virt: .word 0x0 @@ -33,7 +36,7 @@ omap_uart_virt: .word 0x0 /* Use omap_uart_phys/virt if already configured */ 9: mrc p15, 0, \rp, c1, c0 tst \rp, #1 @ MMU enabled? - ldreq \rp, =__virt_to_phys(omap_uart_phys) @ MMU not enabled + ldreq \rp, =omap_uart_v2p(omap_uart_phys) @ MMU disabled ldrne \rp, =omap_uart_phys @ MMU enabled add \rv, \rp, #4 @ omap_uart_virt ldr \rp, [\rp, #0] @@ -46,7 +49,7 @@ omap_uart_virt: .word 0x0 mrc p15, 0, \rp, c1, c0 tst \rp, #1 @ MMU enabled? ldreq \rp, =OMAP_UART_INFO @ MMU not enabled - ldrne \rp, =__phys_to_virt(OMAP_UART_INFO) @ MMU enabled + ldrne \rp, =omap_uart_p2v(OMAP_UART_INFO) @ MMU enabled ldr \rp, [\rp, #0] /* Select the UART to use based on the UART1 scratchpad value */ @@ -73,7 +76,7 @@ omap_uart_virt: .word 0x0 98: add \rp, \rp, #0xff000000 @ phys base mrc p15, 0, \rv, c1, c0 tst \rv, #1 @ MMU enabled? - ldreq \rv, =__virt_to_phys(omap_uart_phys) @ MMU not enabled + ldreq \rv, =omap_uart_v2p(omap_uart_phys) @ MMU disabled ldrne \rv, =omap_uart_phys @ MMU enabled str \rp, [\rv, #0] sub \rp, \rp, #0xff000000 @ phys base diff --git a/arch/arm/mach-omap1/pm.h b/arch/arm/mach-omap1/pm.h index 56a647986ae9..cd926dcb5e7f 100644 --- a/arch/arm/mach-omap1/pm.h +++ b/arch/arm/mach-omap1/pm.h @@ -123,9 +123,9 @@ extern void allow_idle_sleep(void); extern void omap1_pm_idle(void); extern void omap1_pm_suspend(void); -extern void omap7xx_cpu_suspend(unsigned short, unsigned short); -extern void omap1510_cpu_suspend(unsigned short, unsigned short); -extern void omap1610_cpu_suspend(unsigned short, unsigned short); +extern void omap7xx_cpu_suspend(unsigned long, unsigned long); +extern void omap1510_cpu_suspend(unsigned long, unsigned long); +extern void omap1610_cpu_suspend(unsigned long, unsigned long); extern void omap7xx_idle_loop_suspend(void); extern void omap1510_idle_loop_suspend(void); extern void omap1610_idle_loop_suspend(void); diff --git a/arch/arm/mach-omap1/sleep.S b/arch/arm/mach-omap1/sleep.S index ef771ce8b030..c875bdc902c5 100644 --- a/arch/arm/mach-omap1/sleep.S +++ b/arch/arm/mach-omap1/sleep.S @@ -58,6 +58,7 @@ */ #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) + .align 3 ENTRY(omap7xx_cpu_suspend) @ save registers on stack @@ -137,6 +138,7 @@ ENTRY(omap7xx_cpu_suspend_sz) #endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */ #ifdef CONFIG_ARCH_OMAP15XX + .align 3 ENTRY(omap1510_cpu_suspend) @ save registers on stack @@ -211,6 +213,7 @@ ENTRY(omap1510_cpu_suspend_sz) #endif /* CONFIG_ARCH_OMAP15XX */ #if defined(CONFIG_ARCH_OMAP16XX) + .align 3 ENTRY(omap1610_cpu_suspend) @ save registers on stack diff --git a/arch/arm/mach-omap1/sram.S b/arch/arm/mach-omap1/sram.S index 7724e520d07c..692587d07ea5 100644 --- a/arch/arm/mach-omap1/sram.S +++ b/arch/arm/mach-omap1/sram.S @@ -18,6 +18,7 @@ /* * Reprograms ULPD and CKCTL. */ + .align 3 ENTRY(omap1_sram_reprogram_clock) stmfd sp!, {r0 - r12, lr} @ save registers on stack diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 1a2cf6226a55..b69fa0a0299e 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -45,6 +45,7 @@ config ARCH_OMAP4 select CPU_V7 select ARM_GIC select PL310_ERRATA_588369 + select PL310_ERRATA_727915 select ARM_ERRATA_720789 select ARCH_HAS_OPP select PM_OPP if PM diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 1c0c2b02d870..64dc4176407b 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -229,7 +229,7 @@ usbfs-$(CONFIG_ARCH_OMAP_OTG) := usb-fs.o obj-y += $(usbfs-m) $(usbfs-y) obj-y += usb-musb.o obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o -obj-y += usb-ehci.o +obj-y += usb-host.o onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o obj-y += $(onenand-m) $(onenand-y) diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index d4e41ef86aa5..7542ba59f2b8 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -653,11 +653,11 @@ static void enable_board_wakeup_source(void) OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP); } -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = 57, @@ -816,7 +816,7 @@ static void __init omap_3430sdp_init(void) board_flash_init(sdp_flash_partitions, chip_sel_3430); sdp3430_display_init(); enable_board_wakeup_source(); - usb_ehci_init(&ehci_pdata); + usbhs_init(&usbhs_bdata); } MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index 62645640f5e4..deed2db32c53 100644 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c @@ -54,11 +54,11 @@ static void enable_board_wakeup_source(void) OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP); } -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = 126, @@ -211,7 +211,7 @@ static void __init omap_sdp_init(void) board_smc91x_init(); board_flash_init(sdp_flash_partitions, chip_sel_sdp); enable_board_wakeup_source(); - usb_ehci_init(&ehci_pdata); + usbhs_init(&usbhs_bdata); } MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board") diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 07d1b20b1148..f603f3b04cb8 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -44,7 +44,6 @@ #define ETH_KS8851_IRQ 34 #define ETH_KS8851_POWER_ON 48 #define ETH_KS8851_QUART 138 -#define OMAP4SDP_MDM_PWR_EN_GPIO 157 #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 #define OMAP4_SFH7741_ENABLE_GPIO 188 @@ -251,16 +250,6 @@ static void __init omap_4430sdp_init_irq(void) gic_init_irq(); } -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .phy_reset = false, - .reset_gpio_port[0] = -EINVAL, - .reset_gpio_port[1] = -EINVAL, - .reset_gpio_port[2] = -EINVAL, -}; - static struct omap_musb_board_data musb_board_data = { .interface_type = MUSB_INTERFACE_UTMI, .mode = MUSB_OTG, @@ -272,6 +261,7 @@ static struct twl4030_usb_data omap4_usbphy_data = { .phy_exit = omap4430_phy_exit, .phy_power = omap4430_phy_power, .phy_set_clock = omap4430_phy_set_clk, + .phy_suspend = omap4430_phy_suspend, }; static struct omap2_hsmmc_info mmc[] = { @@ -576,14 +566,6 @@ static void __init omap_4430sdp_init(void) omap_serial_init(); omap4_twl6030_hsmmc_init(mmc); - /* Power on the ULPI PHY */ - status = gpio_request(OMAP4SDP_MDM_PWR_EN_GPIO, "USBB1 PHY VMDM_3V3"); - if (status) - pr_err("%s: Could not get USBB1 PHY GPIO\n", __func__); - else - gpio_direction_output(OMAP4SDP_MDM_PWR_EN_GPIO, 1); - - usb_ehci_init(&ehci_pdata); usb_musb_init(&musb_board_data); status = omap_ethernet_init(); diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c index 71acb5ab281c..e3a194f6b13f 100644 --- a/arch/arm/mach-omap2/board-am3517crane.c +++ b/arch/arm/mach-omap2/board-am3517crane.c @@ -59,10 +59,10 @@ static void __init am3517_crane_init_irq(void) omap_init_irq(); } -static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, +static struct usbhs_omap_board_data usbhs_bdata __initdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = GPIO_USB_NRESET, @@ -103,7 +103,7 @@ static void __init am3517_crane_init(void) return; } - usb_ehci_init(&ehci_pdata); + usbhs_init(&usbhs_bdata); } MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD") diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 10d60b7743cf..913538ad17d8 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -430,15 +430,15 @@ static __init void am3517_evm_musb_init(void) usb_musb_init(&musb_board_data); } -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, #if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \ defined(CONFIG_PANEL_SHARP_LQ043T1DG01_MODULE) - .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, #else - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, #endif - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = 57, @@ -502,7 +502,7 @@ static void __init am3517_evm_init(void) /* Configure GPIO for EHCI port */ omap_mux_init_gpio(57, OMAP_PIN_OUTPUT); - usb_ehci_init(&ehci_pdata); + usbhs_init(&usbhs_bdata); am3517_evm_hecc_init(&am3517_evm_hecc_pdata); /* DSS */ am3517_evm_display_init(); diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index dac141610666..9be7289cbb56 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -605,10 +605,10 @@ static struct omap2_hsmmc_info mmc[] = { {} /* Terminator */ }; -static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, +static struct usbhs_omap_board_data usbhs_bdata __initdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = OMAP_MAX_GPIO_LINES + 6, @@ -810,7 +810,7 @@ static void __init cm_t35_init(void) cm_t35_init_display(); usb_musb_init(&musb_board_data); - usb_ehci_init(&ehci_pdata); + usbhs_init(&usbhs_bdata); } MACHINE_START(CM_T35, "Compulab CM-T35") diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c index 8f9a64d650ee..8e18dc76b11e 100644 --- a/arch/arm/mach-omap2/board-cm-t3517.c +++ b/arch/arm/mach-omap2/board-cm-t3517.c @@ -167,10 +167,10 @@ static inline void cm_t3517_init_rtc(void) {} #define HSUSB2_RESET_GPIO (147) #define USB_HUB_RESET_GPIO (152) -static struct ehci_hcd_omap_platform_data cm_t3517_ehci_pdata __initdata = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, +static struct usbhs_omap_board_data cm_t3517_ehci_pdata __initdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = HSUSB1_RESET_GPIO, @@ -192,7 +192,7 @@ static int cm_t3517_init_usbh(void) msleep(1); } - usb_ehci_init(&cm_t3517_ehci_pdata); + usbhs_init(&cm_t3517_ehci_pdata); return 0; } diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 9a2a31e011ce..bc0141b98694 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -620,11 +620,11 @@ static struct omap_musb_board_data musb_board_data = { .power = 100, }; -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = -EINVAL, @@ -803,7 +803,7 @@ static void __init devkit8000_init(void) devkit8000_ads7846_init(); usb_musb_init(&musb_board_data); - usb_ehci_init(&ehci_pdata); + usbhs_init(&usbhs_bdata); devkit8000_flash_init(); /* Ensure SDRC pins are mux'd for self-refresh */ diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 3be85a1f55f4..f9f534419311 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -627,10 +627,10 @@ static struct omap_musb_board_data musb_board_data = { .power = 100, }; -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = IGEP2_GPIO_USBH_NRESET, @@ -699,7 +699,7 @@ static void __init igep2_init(void) platform_add_devices(igep2_devices, ARRAY_SIZE(igep2_devices)); omap_serial_init(); usb_musb_init(&musb_board_data); - usb_ehci_init(&ehci_pdata); + usbhs_init(&usbhs_bdata); igep2_flash_init(); igep2_leds_init(); diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c index 4dc62a9b9cb2..579fc2d2525f 100644 --- a/arch/arm/mach-omap2/board-igep0030.c +++ b/arch/arm/mach-omap2/board-igep0030.c @@ -408,10 +408,10 @@ static void __init igep3_wifi_bt_init(void) void __init igep3_wifi_bt_init(void) {} #endif -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = -EINVAL, @@ -435,7 +435,7 @@ static void __init igep3_init(void) platform_add_devices(igep3_devices, ARRAY_SIZE(igep3_devices)); omap_serial_init(); usb_musb_init(&musb_board_data); - usb_ehci_init(&ehci_pdata); + usbhs_init(&usbhs_bdata); igep3_flash_init(); igep3_leds_init(); diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 46d814ab5656..f0963b6e4627 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -586,11 +586,11 @@ static void __init omap3beagle_flash_init(void) } } -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = -EINVAL, @@ -625,7 +625,7 @@ static void __init omap3_beagle_init(void) gpio_direction_output(170, true); usb_musb_init(&musb_board_data); - usb_ehci_init(&ehci_pdata); + usbhs_init(&usbhs_bdata); omap3beagle_flash_init(); /* Ensure SDRC pins are mux'd for self-refresh */ diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 323c3809ce39..38a2d91790c0 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -638,11 +638,11 @@ static struct platform_device *omap3_evm_devices[] __initdata = { &omap3_evm_dss_device, }; -static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { +static struct usbhs_omap_board_data usbhs_bdata __initdata = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, /* PHY reset GPIO will be runtime programmed based on EVM version */ @@ -700,7 +700,7 @@ static void __init omap3_evm_init(void) /* setup EHCI phy reset config */ omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP); - ehci_pdata.reset_gpio_port[1] = 21; + usbhs_bdata.reset_gpio_port[1] = 21; /* EVM REV >= E can supply 500mA with EXTVBUS programming */ musb_board_data.power = 500; @@ -708,10 +708,10 @@ static void __init omap3_evm_init(void) } else { /* setup EHCI phy reset on MDC */ omap_mux_init_gpio(135, OMAP_PIN_OUTPUT); - ehci_pdata.reset_gpio_port[1] = 135; + usbhs_bdata.reset_gpio_port[1] = 135; } usb_musb_init(&musb_board_data); - usb_ehci_init(&ehci_pdata); + usbhs_init(&usbhs_bdata); ads7846_dev_init(); omap3evm_init_smsc911x(); omap3_evm_display_init(); diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 0b34beded11f..aa05f2e46a61 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -681,11 +681,11 @@ static struct platform_device *omap3pandora_devices[] __initdata = { &pandora_vwlan_device, }; -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = 16, @@ -716,7 +716,7 @@ static void __init omap3pandora_init(void) spi_register_board_info(omap3pandora_spi_board_info, ARRAY_SIZE(omap3pandora_spi_board_info)); omap3pandora_ads7846_init(); - usb_ehci_init(&ehci_pdata); + usbhs_init(&usbhs_bdata); usb_musb_init(&musb_board_data); gpmc_nand_init(&pandora_nand_data); diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index 2a2dad447e86..f6c87787cd4f 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -608,10 +608,10 @@ static struct platform_device *omap3_stalker_devices[] __initdata = { &keys_gpio, }; -static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, +static struct usbhs_omap_board_data usbhs_bdata __initconst = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = -EINVAL, @@ -649,7 +649,7 @@ static void __init omap3_stalker_init(void) omap_serial_init(); usb_musb_init(&musb_board_data); - usb_ehci_init(&ehci_pdata); + usbhs_init(&usbhs_bdata); ads7846_dev_init(); omap_mux_init_gpio(21, OMAP_PIN_OUTPUT); diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index db1f74fe6c4f..84cfddb19a74 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -468,11 +468,11 @@ static void __init omap3touchbook_flash_init(void) } } -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = -EINVAL, @@ -527,7 +527,7 @@ static void __init omap3_touchbook_init(void) ARRAY_SIZE(omap3_ads7846_spi_board_info)); omap3_ads7846_init(); usb_musb_init(&musb_board_data); - usb_ehci_init(&ehci_pdata); + usbhs_init(&usbhs_bdata); omap3touchbook_flash_init(); /* Ensure SDRC pins are mux'd for self-refresh */ diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index e944025d5ef8..ed61c1f5d5e6 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -83,10 +83,10 @@ static void __init omap4_panda_init_irq(void) gic_init_irq(); } -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = false, .reset_gpio_port[0] = -EINVAL, .reset_gpio_port[1] = -EINVAL, @@ -128,7 +128,7 @@ static void __init omap4_ehci_init(void) gpio_set_value(GPIO_HUB_NRESET, 0); gpio_set_value(GPIO_HUB_NRESET, 1); - usb_ehci_init(&ehci_pdata); + usbhs_init(&usbhs_bdata); /* enable power to hub */ gpio_set_value(GPIO_HUB_POWER, 1); @@ -153,6 +153,7 @@ static struct twl4030_usb_data omap4_usbphy_data = { .phy_exit = omap4430_phy_exit, .phy_power = omap4430_phy_power, .phy_set_clock = omap4430_phy_set_clk, + .phy_suspend = omap4430_phy_suspend, }; static struct omap2_hsmmc_info mmc[] = { diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index cb26e5d8268d..08770ccec0f3 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -423,10 +423,10 @@ static struct platform_device *overo_devices[] __initdata = { &overo_lcd_device, }; -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = -EINVAL, @@ -454,7 +454,7 @@ static void __init overo_init(void) omap_serial_init(); overo_flash_init(); usb_musb_init(&musb_board_data); - usb_ehci_init(&ehci_pdata); + usbhs_init(&usbhs_bdata); overo_ads7846_init(); overo_init_smsc911x(); diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c index e26754c24ee8..1dd195afa396 100644 --- a/arch/arm/mach-omap2/board-zoom.c +++ b/arch/arm/mach-omap2/board-zoom.c @@ -106,10 +106,10 @@ static struct mtd_partition zoom_nand_partitions[] = { }, }; -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = -EINVAL, .reset_gpio_port[1] = ZOOM3_EHCI_RESET_GPIO, @@ -123,7 +123,7 @@ static void __init omap_zoom_init(void) } else if (machine_is_omap_zoom3()) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); omap_mux_init_gpio(ZOOM3_EHCI_RESET_GPIO, OMAP_PIN_OUTPUT); - usb_ehci_init(&ehci_pdata); + usbhs_init(&usbhs_bdata); } board_nand_init(zoom_nand_partitions, diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 403a4a1d3f9c..fbb1e30a73dc 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3286,7 +3286,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("ehci-omap.0", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("usbhs-omap.0", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX), CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX), CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), @@ -3322,7 +3322,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX), CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("ehci-omap.0", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("usbhs-omap.0", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX), CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX), @@ -3368,11 +3368,20 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX), CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX), CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("ehci-omap.0", "hs_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("usbhs-omap.0", "hs_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("ehci-omap.0", "fs_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("usbhs-omap.0", "fs_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("ehci-omap.0", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("usbhs-omap.0", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("usbhs-omap.0", "utmi_p1_gfclk", &dummy_ck, CK_3XXX), + CLK("usbhs-omap.0", "utmi_p2_gfclk", &dummy_ck, CK_3XXX), + CLK("usbhs-omap.0", "xclk60mhsp1_ck", &dummy_ck, CK_3XXX), + CLK("usbhs-omap.0", "xclk60mhsp2_ck", &dummy_ck, CK_3XXX), + CLK("usbhs-omap.0", "usb_host_hs_utmi_p1_clk", &dummy_ck, CK_3XXX), + CLK("usbhs-omap.0", "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX), + CLK("usbhs-omap.0", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX), + CLK("usbhs-omap.0", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX), + CLK("usbhs-omap.0", "init_60m_fclk", &dummy_ck, CK_3XXX), CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX), CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX), CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX), diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index de9ec8ddd2ae..46fd3f674cac 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -3197,7 +3197,7 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), - CLK("ehci-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X), + CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X), CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), @@ -3209,8 +3209,8 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), - CLK("ehci-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X), - CLK("ehci-omap.0", "usbhost_ick", &dummy_ck, CK_443X), + CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X), + CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X), CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), @@ -3219,8 +3219,8 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), - CLK("ehci-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X), - CLK("ehci-omap.0", "usbtll_fck", &dummy_ck, CK_443X), + CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X), + CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X), CLK(NULL, "usim_ck", &usim_ck, CK_443X), CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), CLK(NULL, "usim_fck", &usim_fck, CK_443X), diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S index 6a4d4136002e..6049f465ec84 100644 --- a/arch/arm/mach-omap2/include/mach/debug-macro.S +++ b/arch/arm/mach-omap2/include/mach/debug-macro.S @@ -19,6 +19,9 @@ #define UART_OFFSET(addr) ((addr) & 0x00ffffff) +#define omap_uart_v2p(x) ((x) - PAGE_OFFSET + PLAT_PHYS_OFFSET) +#define omap_uart_p2v(x) ((x) - PLAT_PHYS_OFFSET + PAGE_OFFSET) + .pushsection .data omap_uart_phys: .word 0 omap_uart_virt: .word 0 @@ -36,7 +39,7 @@ omap_uart_lsr: .word 0 /* Use omap_uart_phys/virt if already configured */ 10: mrc p15, 0, \rp, c1, c0 tst \rp, #1 @ MMU enabled? - ldreq \rp, =__virt_to_phys(omap_uart_phys) @ MMU not enabled + ldreq \rp, =omap_uart_v2p(omap_uart_phys) @ MMU disabled ldrne \rp, =omap_uart_phys @ MMU enabled add \rv, \rp, #4 @ omap_uart_virt ldr \rp, [\rp, #0] @@ -49,7 +52,7 @@ omap_uart_lsr: .word 0 mrc p15, 0, \rp, c1, c0 tst \rp, #1 @ MMU enabled? ldreq \rp, =OMAP_UART_INFO @ MMU not enabled - ldrne \rp, =__phys_to_virt(OMAP_UART_INFO) @ MMU enabled + ldrne \rp, =omap_uart_p2v(OMAP_UART_INFO) @ MMU enabled ldr \rp, [\rp, #0] /* Select the UART to use based on the UART1 scratchpad value */ @@ -94,7 +97,7 @@ omap_uart_lsr: .word 0 95: ldr \rp, =ZOOM_UART_BASE mrc p15, 0, \rv, c1, c0 tst \rv, #1 @ MMU enabled? - ldreq \rv, =__virt_to_phys(omap_uart_phys) @ MMU not enabled + ldreq \rv, =omap_uart_v2p(omap_uart_phys) @ MMU disabled ldrne \rv, =omap_uart_phys @ MMU enabled str \rp, [\rv, #0] ldr \rp, =ZOOM_UART_VIRT @@ -109,7 +112,7 @@ omap_uart_lsr: .word 0 98: add \rp, \rp, #0x48000000 @ phys base mrc p15, 0, \rv, c1, c0 tst \rv, #1 @ MMU enabled? - ldreq \rv, =__virt_to_phys(omap_uart_phys) @ MMU not enabled + ldreq \rv, =omap_uart_v2p(omap_uart_phys) @ MMU disabled ldrne \rv, =omap_uart_phys @ MMU enabled str \rp, [\rv, #0] sub \rp, \rp, #0x48000000 @ phys base @@ -131,7 +134,7 @@ omap_uart_lsr: .word 0 .macro busyuart,rd,rx 1001: mrc p15, 0, \rd, c1, c0 tst \rd, #1 @ MMU enabled? - ldreq \rd, =__virt_to_phys(omap_uart_lsr) @ MMU not enabled + ldreq \rd, =omap_uart_v2p(omap_uart_lsr) @ MMU disabled ldrne \rd, =omap_uart_lsr @ MMU enabled ldr \rd, [\rd, #0] ldrb \rd, [\rx, \rd] diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 19268647ce36..9ef8c29dd817 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -52,6 +52,12 @@ static void omap4_l2x0_disable(void) omap_smc1(0x102, 0x0); } +static void omap4_l2x0_set_debug(unsigned long val) +{ + /* Program PL310 L2 Cache controller debug register */ + omap_smc1(0x100, val); +} + static int __init omap_l2_cache_init(void) { u32 aux_ctrl = 0; @@ -99,6 +105,7 @@ static int __init omap_l2_cache_init(void) * specific one */ outer_cache.disable = omap4_l2x0_disable; + outer_cache.set_debug = omap4_l2x0_set_debug; return 0; } diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c index 745252c60e32..ebe33df708bd 100644 --- a/arch/arm/mach-omap2/omap_phy_internal.c +++ b/arch/arm/mach-omap2/omap_phy_internal.c @@ -43,6 +43,7 @@ static struct clk *phyclk, *clk48m, *clk32k; static void __iomem *ctrl_base; +static int usbotghs_control; int omap4430_phy_init(struct device *dev) { @@ -103,13 +104,6 @@ int omap4430_phy_set_clk(struct device *dev, int on) int omap4430_phy_power(struct device *dev, int ID, int on) { if (on) { - /* enabled the clocks */ - omap4430_phy_set_clk(dev, 1); - /* power on the phy */ - if (__raw_readl(ctrl_base + CONTROL_DEV_CONF) & PHY_PD) { - __raw_writel(~PHY_PD, ctrl_base + CONTROL_DEV_CONF); - mdelay(200); - } if (ID) /* enable VBUS valid, IDDIG groung */ __raw_writel(AVALID | VBUSVALID, ctrl_base + @@ -125,10 +119,31 @@ int omap4430_phy_power(struct device *dev, int ID, int on) /* Enable session END and IDIG to high impedence. */ __raw_writel(SESSEND | IDDIG, ctrl_base + USBOTGHS_CONTROL); + } + return 0; +} + +int omap4430_phy_suspend(struct device *dev, int suspend) +{ + if (suspend) { /* Disable the clocks */ omap4430_phy_set_clk(dev, 0); /* Power down the phy */ __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF); + + /* save the context */ + usbotghs_control = __raw_readl(ctrl_base + USBOTGHS_CONTROL); + } else { + /* Enable the internel phy clcoks */ + omap4430_phy_set_clk(dev, 1); + /* power on the phy */ + if (__raw_readl(ctrl_base + CONTROL_DEV_CONF) & PHY_PD) { + __raw_writel(~PHY_PD, ctrl_base + CONTROL_DEV_CONF); + mdelay(200); + } + + /* restore the context */ + __raw_writel(usbotghs_control, ctrl_base + USBOTGHS_CONTROL); } return 0; diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 1c1b0ab5b978..39580e6060e8 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -92,7 +92,7 @@ extern void omap24xx_idle_loop_suspend(void); extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl, void __iomem *sdrc_power); extern void omap34xx_cpu_suspend(u32 *addr, int save_state); -extern void save_secure_ram_context(u32 *addr); +extern int save_secure_ram_context(u32 *addr); extern void omap3_save_scratchpad_contents(void); extern unsigned int omap24xx_idle_loop_suspend_sz; diff --git a/arch/arm/mach-omap2/sleep24xx.S b/arch/arm/mach-omap2/sleep24xx.S index c7780cc8d919..b5071a47ec39 100644 --- a/arch/arm/mach-omap2/sleep24xx.S +++ b/arch/arm/mach-omap2/sleep24xx.S @@ -47,6 +47,7 @@ * Note: This code get's copied to internal SRAM at boot. When the OMAP * wakes up it continues execution at the point it went to sleep. */ + .align 3 ENTRY(omap24xx_idle_loop_suspend) stmfd sp!, {r0, lr} @ save registers on stack mov r0, #0 @ clear for mcr setup @@ -82,6 +83,7 @@ ENTRY(omap24xx_idle_loop_suspend_sz) * The DLL load value is not kept in RETENTION or OFF. It needs to be restored * at wake */ + .align 3 ENTRY(omap24xx_cpu_suspend) stmfd sp!, {r0 - r12, lr} @ save registers on stack mov r3, #0x0 @ clear for mcr call diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index 98d8232808b8..951a0be66cf7 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -118,6 +118,7 @@ ENTRY(enable_omap3630_toggle_l2_on_restore) .text /* Function to call rom code to save secure ram context */ + .align 3 ENTRY(save_secure_ram_context) stmfd sp!, {r1-r12, lr} @ save registers on stack adr r3, api_params @ r3 points to parameters @@ -169,6 +170,7 @@ ENTRY(save_secure_ram_context_sz) * depending on the low power mode (non-OFF vs OFF modes), * cf. 'Resume path for xxx mode' comments. */ + .align 3 ENTRY(omap34xx_cpu_suspend) stmfd sp!, {r0-r12, lr} @ save registers on stack diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S index 055310cc77de..ff9b9dbcb30e 100644 --- a/arch/arm/mach-omap2/sram242x.S +++ b/arch/arm/mach-omap2/sram242x.S @@ -39,6 +39,7 @@ .text + .align 3 ENTRY(omap242x_sram_ddr_init) stmfd sp!, {r0 - r12, lr} @ save registers on stack @@ -143,6 +144,7 @@ ENTRY(omap242x_sram_ddr_init_sz) * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR] * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0 */ + .align 3 ENTRY(omap242x_sram_reprogram_sdrc) stmfd sp!, {r0 - r10, lr} @ save registers on stack mov r3, #0x0 @ clear for mrc call @@ -238,6 +240,7 @@ ENTRY(omap242x_sram_reprogram_sdrc_sz) /* * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode. */ + .align 3 ENTRY(omap242x_sram_set_prcm) stmfd sp!, {r0-r12, lr} @ regs to stack adr r4, pbegin @ addr of preload start diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S index f9007580aea3..76730209fa0e 100644 --- a/arch/arm/mach-omap2/sram243x.S +++ b/arch/arm/mach-omap2/sram243x.S @@ -39,6 +39,7 @@ .text + .align 3 ENTRY(omap243x_sram_ddr_init) stmfd sp!, {r0 - r12, lr} @ save registers on stack @@ -143,6 +144,7 @@ ENTRY(omap243x_sram_ddr_init_sz) * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR] * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0 */ + .align 3 ENTRY(omap243x_sram_reprogram_sdrc) stmfd sp!, {r0 - r10, lr} @ save registers on stack mov r3, #0x0 @ clear for mrc call @@ -238,6 +240,7 @@ ENTRY(omap243x_sram_reprogram_sdrc_sz) /* * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode. */ + .align 3 ENTRY(omap243x_sram_set_prcm) stmfd sp!, {r0-r12, lr} @ regs to stack adr r4, pbegin @ addr of preload start diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 7f893a29d500..25011ca2145d 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -111,6 +111,7 @@ * since it will cause the ARM MMU to attempt to walk the page tables. * These crashes may be intermittent. */ + .align 3 ENTRY(omap3_sram_configure_core_dpll) stmfd sp!, {r1-r12, lr} @ store regs to stack diff --git a/arch/arm/mach-omap2/usb-ehci.c b/arch/arm/mach-omap2/usb-host.c index 25eeadabc39b..89ae29847c59 100644 --- a/arch/arm/mach-omap2/usb-ehci.c +++ b/arch/arm/mach-omap2/usb-host.c @@ -1,14 +1,15 @@ /* - * linux/arch/arm/mach-omap2/usb-ehci.c + * usb-host.c - OMAP USB Host * * This file will contain the board specific details for the - * Synopsys EHCI host controller on OMAP3430 + * Synopsys EHCI/OHCI host controller on OMAP3430 and onwards * - * Copyright (C) 2007 Texas Instruments + * Copyright (C) 2007-2011 Texas Instruments * Author: Vikram Pandita <vikram.pandita@ti.com> + * Author: Keshava Munegowda <keshava_mgowda@ti.com> * * Generalization by: - * Felipe Balbi <felipe.balbi@nokia.com> + * Felipe Balbi <balbi@ti.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -19,7 +20,7 @@ #include <linux/errno.h> #include <linux/delay.h> #include <linux/platform_device.h> -#include <linux/clk.h> +#include <linux/slab.h> #include <linux/dma-mapping.h> #include <asm/io.h> @@ -30,44 +31,56 @@ #include "mux.h" -#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE) +#ifdef CONFIG_MFD_OMAP_USB_HOST -static struct resource ehci_resources[] = { +#define OMAP_USBHS_DEVICE "usbhs-omap" + +static struct resource usbhs_resources[] = { + { + .name = "uhh", + .flags = IORESOURCE_MEM, + }, { + .name = "tll", .flags = IORESOURCE_MEM, }, { + .name = "ehci", .flags = IORESOURCE_MEM, }, { + .name = "ehci-irq", + .flags = IORESOURCE_IRQ, + }, + { + .name = "ohci", .flags = IORESOURCE_MEM, }, - { /* general IRQ */ - .flags = IORESOURCE_IRQ, + { + .name = "ohci-irq", + .flags = IORESOURCE_IRQ, } }; -static u64 ehci_dmamask = ~(u32)0; -static struct platform_device ehci_device = { - .name = "ehci-omap", - .id = 0, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = NULL, - }, - .num_resources = ARRAY_SIZE(ehci_resources), - .resource = ehci_resources, +static struct platform_device usbhs_device = { + .name = OMAP_USBHS_DEVICE, + .id = 0, + .num_resources = ARRAY_SIZE(usbhs_resources), + .resource = usbhs_resources, }; +static struct usbhs_omap_platform_data usbhs_data; +static struct ehci_hcd_omap_platform_data ehci_data; +static struct ohci_hcd_omap_platform_data ohci_data; + /* MUX settings for EHCI pins */ /* * setup_ehci_io_mux - initialize IO pad mux for USBHOST */ -static void setup_ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) +static void setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode) { switch (port_mode[0]) { - case EHCI_HCD_OMAP_MODE_PHY: + case OMAP_EHCI_PORT_MODE_PHY: omap_mux_init_signal("hsusb1_stp", OMAP_PIN_OUTPUT); omap_mux_init_signal("hsusb1_clk", OMAP_PIN_OUTPUT); omap_mux_init_signal("hsusb1_dir", OMAP_PIN_INPUT_PULLDOWN); @@ -81,7 +94,7 @@ static void setup_ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) omap_mux_init_signal("hsusb1_data6", OMAP_PIN_INPUT_PULLDOWN); omap_mux_init_signal("hsusb1_data7", OMAP_PIN_INPUT_PULLDOWN); break; - case EHCI_HCD_OMAP_MODE_TLL: + case OMAP_EHCI_PORT_MODE_TLL: omap_mux_init_signal("hsusb1_tll_stp", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("hsusb1_tll_clk", @@ -107,14 +120,14 @@ static void setup_ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) omap_mux_init_signal("hsusb1_tll_data7", OMAP_PIN_INPUT_PULLDOWN); break; - case EHCI_HCD_OMAP_MODE_UNKNOWN: + case OMAP_USBHS_PORT_MODE_UNUSED: /* FALLTHROUGH */ default: break; } switch (port_mode[1]) { - case EHCI_HCD_OMAP_MODE_PHY: + case OMAP_EHCI_PORT_MODE_PHY: omap_mux_init_signal("hsusb2_stp", OMAP_PIN_OUTPUT); omap_mux_init_signal("hsusb2_clk", OMAP_PIN_OUTPUT); omap_mux_init_signal("hsusb2_dir", OMAP_PIN_INPUT_PULLDOWN); @@ -136,7 +149,7 @@ static void setup_ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) omap_mux_init_signal("hsusb2_data7", OMAP_PIN_INPUT_PULLDOWN); break; - case EHCI_HCD_OMAP_MODE_TLL: + case OMAP_EHCI_PORT_MODE_TLL: omap_mux_init_signal("hsusb2_tll_stp", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("hsusb2_tll_clk", @@ -162,17 +175,17 @@ static void setup_ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) omap_mux_init_signal("hsusb2_tll_data7", OMAP_PIN_INPUT_PULLDOWN); break; - case EHCI_HCD_OMAP_MODE_UNKNOWN: + case OMAP_USBHS_PORT_MODE_UNUSED: /* FALLTHROUGH */ default: break; } switch (port_mode[2]) { - case EHCI_HCD_OMAP_MODE_PHY: + case OMAP_EHCI_PORT_MODE_PHY: printk(KERN_WARNING "Port3 can't be used in PHY mode\n"); break; - case EHCI_HCD_OMAP_MODE_TLL: + case OMAP_EHCI_PORT_MODE_TLL: omap_mux_init_signal("hsusb3_tll_stp", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("hsusb3_tll_clk", @@ -198,7 +211,7 @@ static void setup_ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) omap_mux_init_signal("hsusb3_tll_data7", OMAP_PIN_INPUT_PULLDOWN); break; - case EHCI_HCD_OMAP_MODE_UNKNOWN: + case OMAP_USBHS_PORT_MODE_UNUSED: /* FALLTHROUGH */ default: break; @@ -207,10 +220,10 @@ static void setup_ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) return; } -static void setup_4430ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) +static void setup_4430ehci_io_mux(const enum usbhs_omap_port_mode *port_mode) { switch (port_mode[0]) { - case EHCI_HCD_OMAP_MODE_PHY: + case OMAP_EHCI_PORT_MODE_PHY: omap_mux_init_signal("usbb1_ulpiphy_stp", OMAP_PIN_OUTPUT); omap_mux_init_signal("usbb1_ulpiphy_clk", @@ -236,7 +249,7 @@ static void setup_4430ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) omap_mux_init_signal("usbb1_ulpiphy_dat7", OMAP_PIN_INPUT_PULLDOWN); break; - case EHCI_HCD_OMAP_MODE_TLL: + case OMAP_EHCI_PORT_MODE_TLL: omap_mux_init_signal("usbb1_ulpitll_stp", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("usbb1_ulpitll_clk", @@ -262,12 +275,12 @@ static void setup_4430ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) omap_mux_init_signal("usbb1_ulpitll_dat7", OMAP_PIN_INPUT_PULLDOWN); break; - case EHCI_HCD_OMAP_MODE_UNKNOWN: + case OMAP_USBHS_PORT_MODE_UNUSED: default: break; } switch (port_mode[1]) { - case EHCI_HCD_OMAP_MODE_PHY: + case OMAP_EHCI_PORT_MODE_PHY: omap_mux_init_signal("usbb2_ulpiphy_stp", OMAP_PIN_OUTPUT); omap_mux_init_signal("usbb2_ulpiphy_clk", @@ -293,7 +306,7 @@ static void setup_4430ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) omap_mux_init_signal("usbb2_ulpiphy_dat7", OMAP_PIN_INPUT_PULLDOWN); break; - case EHCI_HCD_OMAP_MODE_TLL: + case OMAP_EHCI_PORT_MODE_TLL: omap_mux_init_signal("usbb2_ulpitll_stp", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("usbb2_ulpitll_clk", @@ -319,90 +332,13 @@ static void setup_4430ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) omap_mux_init_signal("usbb2_ulpitll_dat7", OMAP_PIN_INPUT_PULLDOWN); break; - case EHCI_HCD_OMAP_MODE_UNKNOWN: + case OMAP_USBHS_PORT_MODE_UNUSED: default: break; } } -void __init usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata) -{ - platform_device_add_data(&ehci_device, pdata, sizeof(*pdata)); - - /* Setup Pin IO MUX for EHCI */ - if (cpu_is_omap34xx()) { - ehci_resources[0].start = OMAP34XX_EHCI_BASE; - ehci_resources[0].end = OMAP34XX_EHCI_BASE + SZ_1K - 1; - ehci_resources[1].start = OMAP34XX_UHH_CONFIG_BASE; - ehci_resources[1].end = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1; - ehci_resources[2].start = OMAP34XX_USBTLL_BASE; - ehci_resources[2].end = OMAP34XX_USBTLL_BASE + SZ_4K - 1; - ehci_resources[3].start = INT_34XX_EHCI_IRQ; - setup_ehci_io_mux(pdata->port_mode); - } else if (cpu_is_omap44xx()) { - ehci_resources[0].start = OMAP44XX_HSUSB_EHCI_BASE; - ehci_resources[0].end = OMAP44XX_HSUSB_EHCI_BASE + SZ_1K - 1; - ehci_resources[1].start = OMAP44XX_UHH_CONFIG_BASE; - ehci_resources[1].end = OMAP44XX_UHH_CONFIG_BASE + SZ_2K - 1; - ehci_resources[2].start = OMAP44XX_USBTLL_BASE; - ehci_resources[2].end = OMAP44XX_USBTLL_BASE + SZ_4K - 1; - ehci_resources[3].start = OMAP44XX_IRQ_EHCI; - setup_4430ehci_io_mux(pdata->port_mode); - } - - if (platform_device_register(&ehci_device) < 0) { - printk(KERN_ERR "Unable to register HS-USB (EHCI) device\n"); - return; - } -} - -#else - -void __init usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata) - -{ -} - -#endif /* CONFIG_USB_EHCI_HCD */ - -#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) - -static struct resource ohci_resources[] = { - { - .start = OMAP34XX_OHCI_BASE, - .end = OMAP34XX_OHCI_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP34XX_UHH_CONFIG_BASE, - .end = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP34XX_USBTLL_BASE, - .end = OMAP34XX_USBTLL_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { /* general IRQ */ - .start = INT_34XX_OHCI_IRQ, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 ohci_dmamask = DMA_BIT_MASK(32); - -static struct platform_device ohci_device = { - .name = "ohci-omap3", - .id = 0, - .dev = { - .dma_mask = &ohci_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(ohci_resources), - .resource = ohci_resources, -}; - -static void setup_ohci_io_mux(const enum ohci_omap3_port_mode *port_mode) +static void setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode) { switch (port_mode[0]) { case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: @@ -430,7 +366,7 @@ static void setup_ohci_io_mux(const enum ohci_omap3_port_mode *port_mode) omap_mux_init_signal("mm1_txdat", OMAP_PIN_INPUT_PULLDOWN); break; - case OMAP_OHCI_PORT_MODE_UNUSED: + case OMAP_USBHS_PORT_MODE_UNUSED: /* FALLTHROUGH */ default: break; @@ -461,7 +397,7 @@ static void setup_ohci_io_mux(const enum ohci_omap3_port_mode *port_mode) omap_mux_init_signal("mm2_txdat", OMAP_PIN_INPUT_PULLDOWN); break; - case OMAP_OHCI_PORT_MODE_UNUSED: + case OMAP_USBHS_PORT_MODE_UNUSED: /* FALLTHROUGH */ default: break; @@ -492,31 +428,147 @@ static void setup_ohci_io_mux(const enum ohci_omap3_port_mode *port_mode) omap_mux_init_signal("mm3_txdat", OMAP_PIN_INPUT_PULLDOWN); break; - case OMAP_OHCI_PORT_MODE_UNUSED: + case OMAP_USBHS_PORT_MODE_UNUSED: /* FALLTHROUGH */ default: break; } } -void __init usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata) +static void setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode) { - platform_device_add_data(&ohci_device, pdata, sizeof(*pdata)); + switch (port_mode[0]) { + case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: + case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: + omap_mux_init_signal("usbb1_mm_rxdp", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb1_mm_rxdm", + OMAP_PIN_INPUT_PULLDOWN); - /* Setup Pin IO MUX for OHCI */ - if (cpu_is_omap34xx()) + case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: + case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: + omap_mux_init_signal("usbb1_mm_rxrcv", + OMAP_PIN_INPUT_PULLDOWN); + + case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: + omap_mux_init_signal("usbb1_mm_txen", + OMAP_PIN_INPUT_PULLDOWN); + + + case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: + omap_mux_init_signal("usbb1_mm_txdat", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb1_mm_txse0", + OMAP_PIN_INPUT_PULLDOWN); + break; + + case OMAP_USBHS_PORT_MODE_UNUSED: + default: + break; + } + + switch (port_mode[1]) { + case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: + case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: + omap_mux_init_signal("usbb2_mm_rxdp", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb2_mm_rxdm", + OMAP_PIN_INPUT_PULLDOWN); + + case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: + case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: + omap_mux_init_signal("usbb2_mm_rxrcv", + OMAP_PIN_INPUT_PULLDOWN); + + case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: + omap_mux_init_signal("usbb2_mm_txen", + OMAP_PIN_INPUT_PULLDOWN); + + + case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: + omap_mux_init_signal("usbb2_mm_txdat", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb2_mm_txse0", + OMAP_PIN_INPUT_PULLDOWN); + break; + + case OMAP_USBHS_PORT_MODE_UNUSED: + default: + break; + } +} + +void __init usbhs_init(const struct usbhs_omap_board_data *pdata) +{ + int i; + + for (i = 0; i < OMAP3_HS_USB_PORTS; i++) { + usbhs_data.port_mode[i] = pdata->port_mode[i]; + ohci_data.port_mode[i] = pdata->port_mode[i]; + ehci_data.port_mode[i] = pdata->port_mode[i]; + ehci_data.reset_gpio_port[i] = pdata->reset_gpio_port[i]; + ehci_data.regulator[i] = pdata->regulator[i]; + } + ehci_data.phy_reset = pdata->phy_reset; + ohci_data.es2_compatibility = pdata->es2_compatibility; + usbhs_data.ehci_data = &ehci_data; + usbhs_data.ohci_data = &ohci_data; + + if (cpu_is_omap34xx()) { + usbhs_resources[0].start = OMAP34XX_UHH_CONFIG_BASE; + usbhs_resources[0].end = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1; + usbhs_resources[1].start = OMAP34XX_USBTLL_BASE; + usbhs_resources[1].end = OMAP34XX_USBTLL_BASE + SZ_4K - 1; + usbhs_resources[2].start = OMAP34XX_EHCI_BASE; + usbhs_resources[2].end = OMAP34XX_EHCI_BASE + SZ_1K - 1; + usbhs_resources[3].start = INT_34XX_EHCI_IRQ; + usbhs_resources[4].start = OMAP34XX_OHCI_BASE; + usbhs_resources[4].end = OMAP34XX_OHCI_BASE + SZ_1K - 1; + usbhs_resources[5].start = INT_34XX_OHCI_IRQ; + setup_ehci_io_mux(pdata->port_mode); setup_ohci_io_mux(pdata->port_mode); + } else if (cpu_is_omap44xx()) { + usbhs_resources[0].start = OMAP44XX_UHH_CONFIG_BASE; + usbhs_resources[0].end = OMAP44XX_UHH_CONFIG_BASE + SZ_1K - 1; + usbhs_resources[1].start = OMAP44XX_USBTLL_BASE; + usbhs_resources[1].end = OMAP44XX_USBTLL_BASE + SZ_4K - 1; + usbhs_resources[2].start = OMAP44XX_HSUSB_EHCI_BASE; + usbhs_resources[2].end = OMAP44XX_HSUSB_EHCI_BASE + SZ_1K - 1; + usbhs_resources[3].start = OMAP44XX_IRQ_EHCI; + usbhs_resources[4].start = OMAP44XX_HSUSB_OHCI_BASE; + usbhs_resources[4].end = OMAP44XX_HSUSB_OHCI_BASE + SZ_1K - 1; + usbhs_resources[5].start = OMAP44XX_IRQ_OHCI; + setup_4430ehci_io_mux(pdata->port_mode); + setup_4430ohci_io_mux(pdata->port_mode); + } - if (platform_device_register(&ohci_device) < 0) { - pr_err("Unable to register FS-USB (OHCI) device\n"); - return; + if (platform_device_add_data(&usbhs_device, + &usbhs_data, sizeof(usbhs_data)) < 0) { + printk(KERN_ERR "USBHS platform_device_add_data failed\n"); + goto init_end; } + + if (platform_device_register(&usbhs_device) < 0) + printk(KERN_ERR "USBHS platform_device_register failed\n"); + +init_end: + return; } #else -void __init usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata) +void __init usbhs_init(const struct usbhs_omap_board_data *pdata) { } -#endif /* CONFIG_USB_OHCI_HCD */ +#endif + + diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 5298949d4b11..241fc94b4116 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -214,6 +214,10 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data) if (platform_device_register(&musb_device) < 0) printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n"); + + if (cpu_is_omap44xx()) + omap4430_phy_init(dev); + } #else diff --git a/arch/arm/mach-orion5x/include/mach/memory.h b/arch/arm/mach-orion5x/include/mach/memory.h index 52a2955d0f87..6769917882fe 100644 --- a/arch/arm/mach-orion5x/include/mach/memory.h +++ b/arch/arm/mach-orion5x/include/mach/memory.h @@ -7,6 +7,6 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif diff --git a/arch/arm/mach-pnx4008/include/mach/memory.h b/arch/arm/mach-pnx4008/include/mach/memory.h index 0e8770081058..1275db61cee5 100644 --- a/arch/arm/mach-pnx4008/include/mach/memory.h +++ b/arch/arm/mach-pnx4008/include/mach/memory.h @@ -16,6 +16,6 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x80000000) +#define PLAT_PHYS_OFFSET UL(0x80000000) #endif diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index a134a1413e01..e194d928cdaa 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c @@ -829,5 +829,5 @@ MACHINE_START(BALLOON3, "Balloon3") .init_irq = balloon3_init_irq, .timer = &pxa_timer, .init_machine = balloon3_init, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, MACHINE_END diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h index 92361a66b223..7f68724dcc27 100644 --- a/arch/arm/mach-pxa/include/mach/memory.h +++ b/arch/arm/mach-pxa/include/mach/memory.h @@ -15,7 +15,7 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0xa0000000) +#define PLAT_PHYS_OFFSET UL(0xa0000000) #if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) void cmx2xx_pci_adjust_zones(unsigned long *size, unsigned long *holes); diff --git a/arch/arm/mach-pxa/include/mach/pm.h b/arch/arm/mach-pxa/include/mach/pm.h index fd8360c6839d..f15afe012995 100644 --- a/arch/arm/mach-pxa/include/mach/pm.h +++ b/arch/arm/mach-pxa/include/mach/pm.h @@ -22,9 +22,8 @@ struct pxa_cpu_pm_fns { extern struct pxa_cpu_pm_fns *pxa_cpu_pm_fns; /* sleep.S */ -extern void pxa25x_cpu_suspend(unsigned int); -extern void pxa27x_cpu_suspend(unsigned int); -extern void pxa_cpu_resume(void); +extern void pxa25x_cpu_suspend(unsigned int, long); +extern void pxa27x_cpu_suspend(unsigned int, long); extern int pxa_pm_enter(suspend_state_t state); extern int pxa_pm_prepare(void); diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c index 7bf4017326e3..3010193b081e 100644 --- a/arch/arm/mach-pxa/palmz72.c +++ b/arch/arm/mach-pxa/palmz72.c @@ -212,7 +212,7 @@ static unsigned long store_ptr; static int palmz72_pm_suspend(struct sys_device *dev, pm_message_t msg) { /* setup the resume_info struct for the original bootloader */ - palmz72_resume_info.resume_addr = (u32) pxa_cpu_resume; + palmz72_resume_info.resume_addr = (u32) cpu_resume; /* Storing memory touched by ROM */ store_ptr = *PALMZ72_SAVE_DWORD; diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c index 1807c9abdde0..51e1583265b2 100644 --- a/arch/arm/mach-pxa/pm.c +++ b/arch/arm/mach-pxa/pm.c @@ -67,11 +67,6 @@ int pxa_pm_enter(suspend_state_t state) EXPORT_SYMBOL_GPL(pxa_pm_enter); -unsigned long sleep_phys_sp(void *sp) -{ - return virt_to_phys(sp); -} - static int pxa_pm_valid(suspend_state_t state) { if (pxa_cpu_pm_fns) diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index b166b1d845d7..6bde5956358d 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -244,7 +244,7 @@ static void pxa25x_cpu_pm_enter(suspend_state_t state) switch (state) { case PM_SUSPEND_MEM: - pxa25x_cpu_suspend(PWRMODE_SLEEP); + pxa25x_cpu_suspend(PWRMODE_SLEEP, PLAT_PHYS_OFFSET - PAGE_OFFSET); break; } } @@ -252,7 +252,7 @@ static void pxa25x_cpu_pm_enter(suspend_state_t state) static int pxa25x_cpu_pm_prepare(void) { /* set resume return address */ - PSPR = virt_to_phys(pxa_cpu_resume); + PSPR = virt_to_phys(cpu_resume); return 0; } diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 987301ff4c33..28b11be00b3f 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -300,7 +300,7 @@ void pxa27x_cpu_pm_enter(suspend_state_t state) pxa_cpu_standby(); break; case PM_SUSPEND_MEM: - pxa27x_cpu_suspend(pwrmode); + pxa27x_cpu_suspend(pwrmode, PLAT_PHYS_OFFSET - PAGE_OFFSET); break; } } @@ -313,7 +313,7 @@ static int pxa27x_cpu_pm_valid(suspend_state_t state) static int pxa27x_cpu_pm_prepare(void) { /* set resume return address */ - PSPR = virt_to_phys(pxa_cpu_resume); + PSPR = virt_to_phys(cpu_resume); return 0; } diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index a7a19e1cd640..1230343d9c70 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -142,8 +142,7 @@ static void pxa3xx_cpu_pm_suspend(void) volatile unsigned long *p = (volatile void *)0xc0000000; unsigned long saved_data = *p; - extern void pxa3xx_cpu_suspend(void); - extern void pxa3xx_cpu_resume(void); + extern void pxa3xx_cpu_suspend(long); /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); @@ -161,9 +160,9 @@ static void pxa3xx_cpu_pm_suspend(void) PSPR = 0x5c014000; /* overwrite with the resume address */ - *p = virt_to_phys(pxa3xx_cpu_resume); + *p = virt_to_phys(cpu_resume); - pxa3xx_cpu_suspend(); + pxa3xx_cpu_suspend(PLAT_PHYS_OFFSET - PAGE_OFFSET); *p = saved_data; diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S index c551da86baf6..6f5368899d84 100644 --- a/arch/arm/mach-pxa/sleep.S +++ b/arch/arm/mach-pxa/sleep.S @@ -22,133 +22,26 @@ .text -pxa_cpu_save_cp: - @ get coprocessor registers - mrc p14, 0, r3, c6, c0, 0 @ clock configuration, for turbo mode - mrc p15, 0, r4, c15, c1, 0 @ CP access reg - mrc p15, 0, r5, c13, c0, 0 @ PID - mrc p15, 0, r6, c3, c0, 0 @ domain ID - mrc p15, 0, r7, c2, c0, 0 @ translation table base addr - mrc p15, 0, r8, c1, c1, 0 @ auxiliary control reg - mrc p15, 0, r9, c1, c0, 0 @ control reg - - bic r3, r3, #2 @ clear frequency change bit - - @ store them plus current virtual stack ptr on stack - mov r10, sp - stmfd sp!, {r3 - r10} - - mov pc, lr - -pxa_cpu_save_sp: - @ preserve phys address of stack - mov r0, sp - str lr, [sp, #-4]! - bl sleep_phys_sp - ldr r1, =sleep_save_sp - str r0, [r1] - ldr pc, [sp], #4 - #ifdef CONFIG_PXA3xx /* * pxa3xx_cpu_suspend() - forces CPU into sleep state (S2D3C4) * - * NOTE: unfortunately, pxa_cpu_save_cp can not be reused here since - * the auxiliary control register address is different between pxa3xx - * and pxa{25x,27x} + * r0 = v:p offset */ - ENTRY(pxa3xx_cpu_suspend) #ifndef CONFIG_IWMMXT mra r2, r3, acc0 #endif stmfd sp!, {r2 - r12, lr} @ save registers on stack - - mrc p14, 0, r3, c6, c0, 0 @ clock configuration, for turbo mode - mrc p15, 0, r4, c15, c1, 0 @ CP access reg - mrc p15, 0, r5, c13, c0, 0 @ PID - mrc p15, 0, r6, c3, c0, 0 @ domain ID - mrc p15, 0, r7, c2, c0, 0 @ translation table base addr - mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg - mrc p15, 0, r9, c1, c0, 0 @ control reg - - bic r3, r3, #2 @ clear frequency change bit - - @ store them plus current virtual stack ptr on stack - mov r10, sp - stmfd sp!, {r3 - r10} - - @ store physical address of stack pointer - mov r0, sp - bl sleep_phys_sp - ldr r1, =sleep_save_sp - str r0, [r1] - - @ clean data cache - bl xsc3_flush_kern_cache_all + mov r1, r0 + ldr r3, =pxa_cpu_resume @ resume function + bl cpu_suspend mov r0, #0x06 @ S2D3C4 mode mcr p14, 0, r0, c7, c0, 0 @ enter sleep 20: b 20b @ waiting for sleep - - .data - .align 5 -/* - * pxa3xx_cpu_resume - */ - -ENTRY(pxa3xx_cpu_resume) - - mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE @ set SVC, irqs off - msr cpsr_c, r0 - - ldr r0, sleep_save_sp @ stack phys addr - ldmfd r0, {r3 - r9, sp} @ CP regs + virt stack ptr - - mov r1, #0 - mcr p15, 0, r1, c7, c7, 0 @ invalidate I & D caches, BTB - mcr p15, 0, r1, c7, c10, 4 @ drain write (&fill) buffer - mcr p15, 0, r1, c7, c5, 4 @ flush prefetch buffer - mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs - - mcr p14, 0, r3, c6, c0, 0 @ clock configuration, turbo mode. - mcr p15, 0, r4, c15, c1, 0 @ CP access reg - mcr p15, 0, r5, c13, c0, 0 @ PID - mcr p15, 0, r6, c3, c0, 0 @ domain ID - mcr p15, 0, r7, c2, c0, 0 @ translation table base addr - mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg - - @ temporarily map resume_turn_on_mmu into the page table, - @ otherwise prefetch abort occurs after MMU is turned on - mov r1, r7 - bic r1, r1, #0x00ff - bic r1, r1, #0x3f00 - ldr r2, =0x542e - - adr r3, resume_turn_on_mmu - mov r3, r3, lsr #20 - orr r4, r2, r3, lsl #20 - ldr r5, [r1, r3, lsl #2] - str r4, [r1, r3, lsl #2] - - @ Mapping page table address in the page table - mov r6, r1, lsr #20 - orr r7, r2, r6, lsl #20 - ldr r8, [r1, r6, lsl #2] - str r7, [r1, r6, lsl #2] - - ldr r2, =pxa3xx_resume_after_mmu @ absolute virtual address - b resume_turn_on_mmu @ cache align execution - - .text -pxa3xx_resume_after_mmu: - /* restore the temporary mapping */ - str r5, [r1, r3, lsl #2] - str r8, [r1, r6, lsl #2] - b resume_after_mmu - #endif /* CONFIG_PXA3xx */ #ifdef CONFIG_PXA27x @@ -158,28 +51,23 @@ pxa3xx_resume_after_mmu: * Forces CPU into sleep state. * * r0 = value for PWRMODE M field for desired sleep state + * r1 = v:p offset */ - ENTRY(pxa27x_cpu_suspend) #ifndef CONFIG_IWMMXT mra r2, r3, acc0 #endif stmfd sp!, {r2 - r12, lr} @ save registers on stack - - bl pxa_cpu_save_cp - - mov r5, r0 @ save sleep mode - bl pxa_cpu_save_sp - - @ clean data cache - bl xscale_flush_kern_cache_all + mov r4, r0 @ save sleep mode + ldr r3, =pxa_cpu_resume @ resume function + bl cpu_suspend @ Put the processor to sleep @ (also workaround for sighting 28071) @ prepare value for sleep mode - mov r1, r5 @ sleep mode + mov r1, r4 @ sleep mode @ prepare pointer to physical address 0 (virtual mapping in generic.c) mov r2, #UNCACHED_PHYS_0 @@ -216,21 +104,16 @@ ENTRY(pxa27x_cpu_suspend) * Forces CPU into sleep state. * * r0 = value for PWRMODE M field for desired sleep state + * r1 = v:p offset */ ENTRY(pxa25x_cpu_suspend) stmfd sp!, {r2 - r12, lr} @ save registers on stack - - bl pxa_cpu_save_cp - - mov r5, r0 @ save sleep mode - bl pxa_cpu_save_sp - - @ clean data cache - bl xscale_flush_kern_cache_all - + mov r4, r0 @ save sleep mode + ldr r3, =pxa_cpu_resume @ resume function + bl cpu_suspend @ prepare value for sleep mode - mov r1, r5 @ sleep mode + mov r1, r4 @ sleep mode @ prepare pointer to physical address 0 (virtual mapping in generic.c) mov r2, #UNCACHED_PHYS_0 @@ -317,53 +200,9 @@ pxa_cpu_do_suspend: * pxa_cpu_resume() * * entry point from bootloader into kernel during resume - * - * Note: Yes, part of the following code is located into the .data section. - * This is to allow sleep_save_sp to be accessed with a relative load - * while we can't rely on any MMU translation. We could have put - * sleep_save_sp in the .text section as well, but some setups might - * insist on it to be truly read-only. */ - - .data - .align 5 -ENTRY(pxa_cpu_resume) - mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE @ set SVC, irqs off - msr cpsr_c, r0 - - ldr r0, sleep_save_sp @ stack phys addr - ldr r2, =resume_after_mmu @ its absolute virtual address - ldmfd r0, {r3 - r9, sp} @ CP regs + virt stack ptr - - mov r1, #0 - mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs - mcr p15, 0, r1, c7, c7, 0 @ invalidate I & D caches, BTB - - mcr p14, 0, r3, c6, c0, 0 @ clock configuration, turbo mode. - mcr p15, 0, r4, c15, c1, 0 @ CP access reg - mcr p15, 0, r5, c13, c0, 0 @ PID - mcr p15, 0, r6, c3, c0, 0 @ domain ID - mcr p15, 0, r7, c2, c0, 0 @ translation table base addr - mcr p15, 0, r8, c1, c1, 0 @ auxiliary control reg - b resume_turn_on_mmu @ cache align execution - .align 5 -resume_turn_on_mmu: - mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, caches, etc. - - @ Let us ensure we jump to resume_after_mmu only when the mcr above - @ actually took effect. They call it the "cpwait" operation. - mrc p15, 0, r0, c2, c0, 0 @ queue a dependency on CP15 - sub pc, r2, r0, lsr #32 @ jump to virtual addr - nop - nop - nop - -sleep_save_sp: - .word 0 @ preserve stack phys ptr here - - .text -resume_after_mmu: +pxa_cpu_resume: ldmfd sp!, {r2, r3} #ifndef CONFIG_IWMMXT mar acc0, r2, r3 diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index f4b053b35815..b92aa3b8c4f7 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c @@ -676,7 +676,7 @@ static struct pxa2xx_udc_mach_info zeus_udc_info = { static void zeus_power_off(void) { local_irq_disable(); - pxa27x_cpu_suspend(PWRMODE_DEEPSLEEP); + pxa27x_cpu_suspend(PWRMODE_DEEPSLEEP, PLAT_PHYS_OFFSET - PAGE_OFFSET); } #else #define zeus_power_off NULL diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index 7ca138a943a9..b9a9805e4828 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig @@ -19,7 +19,7 @@ config REALVIEW_EB_A9MP config REALVIEW_EB_ARM11MP bool "Support ARM11MPCore Tile" depends on MACH_REALVIEW_EB - select CPU_V6 + select CPU_V6K select ARCH_HAS_BARRIERS if SMP help Enable support for the ARM11MPCore tile fitted to the Realview(R) @@ -36,7 +36,7 @@ config REALVIEW_EB_ARM11MP_REVB config MACH_REALVIEW_PB11MP bool "Support RealView(R) Platform Baseboard for ARM11MPCore" - select CPU_V6 + select CPU_V6K select ARM_GIC select HAVE_PATA_PLATFORM select ARCH_HAS_BARRIERS if SMP @@ -45,6 +45,7 @@ config MACH_REALVIEW_PB11MP the ARM11MPCore. This platform has an on-board ARM11MPCore and has support for PCI-E and Compact Flash. +# ARMv6 CPU without K extensions, but does have the new exclusive ops config MACH_REALVIEW_PB1176 bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S" select CPU_V6 diff --git a/arch/arm/mach-realview/include/mach/memory.h b/arch/arm/mach-realview/include/mach/memory.h index 5dafc157b276..e05fc2c4c080 100644 --- a/arch/arm/mach-realview/include/mach/memory.h +++ b/arch/arm/mach-realview/include/mach/memory.h @@ -24,9 +24,9 @@ * Physical DRAM offset. */ #ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET -#define PHYS_OFFSET UL(0x70000000) +#define PLAT_PHYS_OFFSET UL(0x70000000) #else -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif #if !defined(__ASSEMBLY__) && defined(CONFIG_ZONE_DMA) diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index 6ef5c5e528b2..8ede983b861c 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -484,7 +484,7 @@ static void __init realview_eb_init(void) MACHINE_START(REALVIEW_EB, "ARM-RealView EB") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ - .boot_params = PHYS_OFFSET + 0x00000100, + .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .fixup = realview_fixup, .map_io = realview_eb_map_io, .init_irq = gic_init_irq, diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c index cbdc97a5685f..9f26369555c7 100644 --- a/arch/arm/mach-realview/realview_pb1176.c +++ b/arch/arm/mach-realview/realview_pb1176.c @@ -379,7 +379,7 @@ static void __init realview_pb1176_init(void) MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ - .boot_params = PHYS_OFFSET + 0x00000100, + .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .fixup = realview_pb1176_fixup, .map_io = realview_pb1176_map_io, .init_irq = gic_init_irq, diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c index 8e8ab7d29a6a..dea06b2da3a2 100644 --- a/arch/arm/mach-realview/realview_pb11mp.c +++ b/arch/arm/mach-realview/realview_pb11mp.c @@ -381,7 +381,7 @@ static void __init realview_pb11mp_init(void) MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ - .boot_params = PHYS_OFFSET + 0x00000100, + .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .fixup = realview_fixup, .map_io = realview_pb11mp_map_io, .init_irq = gic_init_irq, diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c index 841118e3e118..7d0f1734a217 100644 --- a/arch/arm/mach-realview/realview_pba8.c +++ b/arch/arm/mach-realview/realview_pba8.c @@ -331,7 +331,7 @@ static void __init realview_pba8_init(void) MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ - .boot_params = PHYS_OFFSET + 0x00000100, + .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .fixup = realview_fixup, .map_io = realview_pba8_map_io, .init_irq = gic_init_irq, diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c index 02b755b009db..b89e28f8853e 100644 --- a/arch/arm/mach-realview/realview_pbx.c +++ b/arch/arm/mach-realview/realview_pbx.c @@ -414,7 +414,7 @@ static void __init realview_pbx_init(void) MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ - .boot_params = PHYS_OFFSET + 0x00000100, + .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .fixup = realview_pbx_fixup, .map_io = realview_pbx_map_io, .init_irq = gic_init_irq, diff --git a/arch/arm/mach-rpc/include/mach/memory.h b/arch/arm/mach-rpc/include/mach/memory.h index 78191bf25192..18a221093bf5 100644 --- a/arch/arm/mach-rpc/include/mach/memory.h +++ b/arch/arm/mach-rpc/include/mach/memory.h @@ -21,7 +21,7 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x10000000) +#define PLAT_PHYS_OFFSET UL(0x10000000) /* * Cache flushing area - ROM diff --git a/arch/arm/mach-s3c2400/include/mach/memory.h b/arch/arm/mach-s3c2400/include/mach/memory.h index cf5901ffd385..3f33670dd012 100644 --- a/arch/arm/mach-s3c2400/include/mach/memory.h +++ b/arch/arm/mach-s3c2400/include/mach/memory.h @@ -15,6 +15,6 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x0C000000) +#define PLAT_PHYS_OFFSET UL(0x0C000000) #endif diff --git a/arch/arm/mach-s3c2410/include/mach/memory.h b/arch/arm/mach-s3c2410/include/mach/memory.h index 6f1e5871ae4b..f92b97b89c0c 100644 --- a/arch/arm/mach-s3c2410/include/mach/memory.h +++ b/arch/arm/mach-s3c2410/include/mach/memory.h @@ -11,6 +11,6 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x30000000) +#define PLAT_PHYS_OFFSET UL(0x30000000) #endif diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 1a81fe12ccd7..1e93f176c1de 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -162,29 +162,10 @@ struct gpio_chip h1940_latch_gpiochip = { .get = h1940_gpiolib_latch_get, }; -static void h1940_udc_pullup(enum s3c2410_udc_cmd_e cmd) -{ - printk(KERN_DEBUG "udc: pullup(%d)\n",cmd); - - switch (cmd) - { - case S3C2410_UDC_P_ENABLE : - gpio_set_value(H1940_LATCH_USB_DP, 1); - break; - case S3C2410_UDC_P_DISABLE : - gpio_set_value(H1940_LATCH_USB_DP, 0); - break; - case S3C2410_UDC_P_RESET : - break; - default: - break; - } -} - static struct s3c2410_udc_mach_info h1940_udc_cfg __initdata = { - .udc_command = h1940_udc_pullup, .vbus_pin = S3C2410_GPG(5), .vbus_pin_inverted = 1, + .pullup_pin = H1940_LATCH_USB_DP, }; static struct s3c2410_ts_mach_info h1940_ts_cfg __initdata = { @@ -475,9 +456,6 @@ static void __init h1940_init(void) gpio_direction_output(H1940_LATCH_LCD_P4, 0); gpio_direction_output(H1940_LATCH_MAX1698_nSHUTDOWN, 0); - gpio_request(H1940_LATCH_USB_DP, "USB pullup"); - gpio_direction_output(H1940_LATCH_USB_DP, 0); - gpio_request(H1940_LATCH_SD_POWER, "SD power"); gpio_direction_output(H1940_LATCH_SD_POWER, 0); diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c index 271b9aa6d40a..66f44440d5d3 100644 --- a/arch/arm/mach-s3c2410/mach-n30.c +++ b/arch/arm/mach-s3c2410/mach-n30.c @@ -84,26 +84,10 @@ static struct s3c2410_uartcfg n30_uartcfgs[] = { }, }; -static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd) -{ - switch (cmd) { - case S3C2410_UDC_P_ENABLE : - gpio_set_value(S3C2410_GPB(3), 1); - break; - case S3C2410_UDC_P_DISABLE : - gpio_set_value(S3C2410_GPB(3), 0); - break; - case S3C2410_UDC_P_RESET : - break; - default: - break; - } -} - static struct s3c2410_udc_mach_info n30_udc_cfg __initdata = { - .udc_command = n30_udc_pullup, .vbus_pin = S3C2410_GPG(1), .vbus_pin_inverted = 0, + .pullup_pin = S3C2410_GPB(3), }; static struct gpio_keys_button n30_buttons[] = { @@ -596,9 +580,6 @@ static void __init n30_init(void) platform_add_devices(n35_devices, ARRAY_SIZE(n35_devices)); } - - WARN_ON(gpio_request(S3C2410_GPB(3), "udc pup")); - gpio_direction_output(S3C2410_GPB(3), 0); } MACHINE_START(N30, "Acer-N30") diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c index 8e5758bdd666..834cfb61bcfe 100644 --- a/arch/arm/mach-s3c2412/mach-smdk2413.c +++ b/arch/arm/mach-s3c2412/mach-smdk2413.c @@ -78,28 +78,9 @@ static struct s3c2410_uartcfg smdk2413_uartcfgs[] __initdata = { } }; -static void smdk2413_udc_pullup(enum s3c2410_udc_cmd_e cmd) -{ - printk(KERN_DEBUG "udc: pullup(%d)\n",cmd); - - switch (cmd) - { - case S3C2410_UDC_P_ENABLE : - gpio_set_value(S3C2410_GPF(2), 1); - break; - case S3C2410_UDC_P_DISABLE : - gpio_set_value(S3C2410_GPF(2), 0); - break; - case S3C2410_UDC_P_RESET : - break; - default: - break; - } -} - static struct s3c2410_udc_mach_info smdk2413_udc_cfg __initdata = { - .udc_command = smdk2413_udc_pullup, + .pullup_pin = S3C2410_GPF(2), }; @@ -133,9 +114,6 @@ static void __init smdk2413_machine_init(void) { /* Turn off suspend on both USB ports, and switch the * selectable USB port to USB device mode. */ - WARN_ON(gpio_request(S3C2410_GPF(2), "udc pull")); - gpio_direction_output(S3C2410_GPF(2), 0); - s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST | S3C2410_MISCCR_USBSUSPND0 | S3C2410_MISCCR_USBSUSPND1, 0x0); diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c index 9f2c14ec7181..37405d9abe32 100644 --- a/arch/arm/mach-s3c2440/mach-gta02.c +++ b/arch/arm/mach-s3c2440/mach-gta02.c @@ -455,28 +455,10 @@ static struct s3c2410_platform_nand __initdata gta02_nand_info = { }; -static void gta02_udc_command(enum s3c2410_udc_cmd_e cmd) -{ - switch (cmd) { - case S3C2410_UDC_P_ENABLE: - pr_debug("%s S3C2410_UDC_P_ENABLE\n", __func__); - gpio_direction_output(GTA02_GPIO_USB_PULLUP, 1); - break; - case S3C2410_UDC_P_DISABLE: - pr_debug("%s S3C2410_UDC_P_DISABLE\n", __func__); - gpio_direction_output(GTA02_GPIO_USB_PULLUP, 0); - break; - case S3C2410_UDC_P_RESET: - pr_debug("%s S3C2410_UDC_P_RESET\n", __func__); - /* FIXME: Do something here. */ - } -} - /* Get PMU to set USB current limit accordingly. */ -static struct s3c2410_udc_mach_info gta02_udc_cfg = { +static struct s3c2410_udc_mach_info gta02_udc_cfg __initdata = { .vbus_draw = gta02_udc_vbus_draw, - .udc_command = gta02_udc_command, - + .pullup_pin = GTA02_GPIO_USB_PULLUP, }; /* USB */ diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c index f62bb4c793bd..d80f129bca94 100644 --- a/arch/arm/mach-s3c2440/mach-mini2440.c +++ b/arch/arm/mach-s3c2440/mach-mini2440.c @@ -97,26 +97,8 @@ static struct s3c2410_uartcfg mini2440_uartcfgs[] __initdata = { /* USB device UDC support */ -static void mini2440_udc_pullup(enum s3c2410_udc_cmd_e cmd) -{ - pr_debug("udc: pullup(%d)\n", cmd); - - switch (cmd) { - case S3C2410_UDC_P_ENABLE : - gpio_set_value(S3C2410_GPC(5), 1); - break; - case S3C2410_UDC_P_DISABLE : - gpio_set_value(S3C2410_GPC(5), 0); - break; - case S3C2410_UDC_P_RESET : - break; - default: - break; - } -} - static struct s3c2410_udc_mach_info mini2440_udc_cfg __initdata = { - .udc_command = mini2440_udc_pullup, + .pullup_pin = S3C2410_GPC(5), }; @@ -644,10 +626,6 @@ static void __init mini2440_init(void) s3c2410_gpio_setpin(S3C2410_GPB(1), 0); s3c_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPIO_INPUT); - /* Make sure the D+ pullup pin is output */ - WARN_ON(gpio_request(S3C2410_GPC(5), "udc pup")); - gpio_direction_output(S3C2410_GPC(5), 0); - /* mark the key as input, without pullups (there is one on the board) */ for (i = 0; i < ARRAY_SIZE(mini2440_buttons); i++) { s3c_gpio_setpull(mini2440_buttons[i].gpio, S3C_GPIO_PULL_UP); diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c index eab6ae50683c..86bbc233b31c 100644 --- a/arch/arm/mach-s3c2440/mach-rx1950.c +++ b/arch/arm/mach-s3c2440/mach-rx1950.c @@ -566,26 +566,10 @@ static struct s3c2410_platform_nand rx1950_nand_info = { .sets = rx1950_nand_sets, }; -static void rx1950_udc_pullup(enum s3c2410_udc_cmd_e cmd) -{ - switch (cmd) { - case S3C2410_UDC_P_ENABLE: - gpio_direction_output(S3C2410_GPJ(5), 1); - break; - case S3C2410_UDC_P_DISABLE: - gpio_direction_output(S3C2410_GPJ(5), 0); - break; - case S3C2410_UDC_P_RESET: - break; - default: - break; - } -} - static struct s3c2410_udc_mach_info rx1950_udc_cfg __initdata = { - .udc_command = rx1950_udc_pullup, .vbus_pin = S3C2410_GPG(5), .vbus_pin_inverted = 1, + .pullup_pin = S3C2410_GPJ(5), }; static struct s3c2410_ts_mach_info rx1950_ts_cfg __initdata = { @@ -750,9 +734,6 @@ static void __init rx1950_init_machine(void) S3C2410_MISCCR_USBSUSPND0 | S3C2410_MISCCR_USBSUSPND1, 0x0); - WARN_ON(gpio_request(S3C2410_GPJ(5), "UDC pullup")); - gpio_direction_output(S3C2410_GPJ(5), 0); - /* mmc power is disabled by default */ WARN_ON(gpio_request(S3C2410_GPJ(1), "MMC power")); gpio_direction_output(S3C2410_GPJ(1), 0); diff --git a/arch/arm/mach-s3c24a0/include/mach/memory.h b/arch/arm/mach-s3c24a0/include/mach/memory.h index 7d74fd5c8d66..7d208a71b172 100644 --- a/arch/arm/mach-s3c24a0/include/mach/memory.h +++ b/arch/arm/mach-s3c24a0/include/mach/memory.h @@ -11,7 +11,7 @@ #ifndef __ASM_ARCH_24A0_MEMORY_H #define __ASM_ARCH_24A0_MEMORY_H __FILE__ -#define PHYS_OFFSET UL(0x10000000) +#define PLAT_PHYS_OFFSET UL(0x10000000) #define __virt_to_bus(x) __virt_to_phys(x) #define __bus_to_virt(x) __phys_to_virt(x) diff --git a/arch/arm/mach-s3c64xx/include/mach/memory.h b/arch/arm/mach-s3c64xx/include/mach/memory.h index 42cc54e2ee30..4760cdae1eb6 100644 --- a/arch/arm/mach-s3c64xx/include/mach/memory.h +++ b/arch/arm/mach-s3c64xx/include/mach/memory.h @@ -13,7 +13,7 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x50000000) +#define PLAT_PHYS_OFFSET UL(0x50000000) #define CONSISTENT_DMA_SIZE SZ_8M diff --git a/arch/arm/mach-s3c64xx/sleep.S b/arch/arm/mach-s3c64xx/sleep.S index b2ef44317368..afe5a762f46e 100644 --- a/arch/arm/mach-s3c64xx/sleep.S +++ b/arch/arm/mach-s3c64xx/sleep.S @@ -32,25 +32,13 @@ * code after resume. * * entry: - * r0 = pointer to the save block + * r1 = v:p offset */ ENTRY(s3c_cpu_save) stmfd sp!, { r4 - r12, lr } - - mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID - mrc p15, 0, r5, c3, c0, 0 @ Domain ID - mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 - mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 - mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control - mrc p15, 0, r9, c1, c0, 0 @ Control register - mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register - mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls - - stmia r0, { r4 - r13 } @ Save CP registers and SP - - @@ save our state to ram - bl s3c_pm_cb_flushcache + ldr r3, =resume_with_mmu + bl cpu_suspend @@ call final suspend code ldr r0, =pm_cpu_sleep @@ -61,18 +49,6 @@ ENTRY(s3c_cpu_save) resume_with_mmu: ldmfd sp!, { r4 - r12, pc } @ return, from sp from s3c_cpu_save - .data - - /* the next bit is code, but it requires easy access to the - * s3c_sleep_save_phys data before the MMU is switched on, so - * we store the code that needs this variable in the .data where - * the value can be written to (the .text segment is RO). - */ - - .global s3c_sleep_save_phys -s3c_sleep_save_phys: - .word 0 - /* Sleep magic, the word before the resume entry point so that the * bootloader can check for a resumeable image. */ @@ -110,35 +86,4 @@ ENTRY(s3c_cpu_resume) orr r0, r0, #1 << 15 @ GPN15 str r0, [ r3, #S3C64XX_GPNDAT ] #endif - - /* __v6_setup from arch/arm/mm/proc-v6.S, ensure that the caches - * are thoroughly cleaned just in case the bootloader didn't do it - * for us. */ - mov r0, #0 - mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache - mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache - mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache - mcr p15, 0, r0, c7, c10, 4 @ drain write buffer - @@mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs - @@mcr p15, 0, r0, c7, c7, 0 @ Invalidate I + D caches - - ldr r0, s3c_sleep_save_phys - ldmia r0, { r4 - r13 } - - mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID - mcr p15, 0, r5, c3, c0, 0 @ Domain ID - mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 - mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 - mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control - mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register - - mov r0, #0 @ restore copro access controls - mcr p15, 0, r11, c1, c0, 2 @ Co-processor access controls - mcr p15, 0, r0, c7, c5, 4 - - ldr r2, =resume_with_mmu - mcr p15, 0, r9, c1, c0, 0 /* turn mmu back on */ - nop - mov pc, r2 /* jump back */ - - .end + b cpu_resume diff --git a/arch/arm/mach-s5p6442/include/mach/memory.h b/arch/arm/mach-s5p6442/include/mach/memory.h index 9ddd877ba2ea..cfe259dded33 100644 --- a/arch/arm/mach-s5p6442/include/mach/memory.h +++ b/arch/arm/mach-s5p6442/include/mach/memory.h @@ -13,7 +13,7 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x20000000) +#define PLAT_PHYS_OFFSET UL(0x20000000) #define CONSISTENT_DMA_SIZE SZ_8M #endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/mach-s5p64x0/include/mach/memory.h b/arch/arm/mach-s5p64x0/include/mach/memory.h index 1b036b0a24ce..365a6eb4b88f 100644 --- a/arch/arm/mach-s5p64x0/include/mach/memory.h +++ b/arch/arm/mach-s5p64x0/include/mach/memory.h @@ -13,7 +13,7 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H __FILE__ -#define PHYS_OFFSET UL(0x20000000) +#define PLAT_PHYS_OFFSET UL(0x20000000) #define CONSISTENT_DMA_SIZE SZ_8M #endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/memory.h b/arch/arm/mach-s5pc100/include/mach/memory.h index 4b60d18179f7..bda4e79fd5fc 100644 --- a/arch/arm/mach-s5pc100/include/mach/memory.h +++ b/arch/arm/mach-s5pc100/include/mach/memory.h @@ -13,6 +13,6 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x20000000) +#define PLAT_PHYS_OFFSET UL(0x20000000) #endif diff --git a/arch/arm/mach-s5pv210/cpufreq.c b/arch/arm/mach-s5pv210/cpufreq.c index a6f22920a2c2..22046e2f53c2 100644 --- a/arch/arm/mach-s5pv210/cpufreq.c +++ b/arch/arm/mach-s5pv210/cpufreq.c @@ -390,8 +390,7 @@ static int s5pv210_target(struct cpufreq_policy *policy, } #ifdef CONFIG_PM -static int s5pv210_cpufreq_suspend(struct cpufreq_policy *policy, - pm_message_t pmsg) +static int s5pv210_cpufreq_suspend(struct cpufreq_policy *policy) { return 0; } diff --git a/arch/arm/mach-s5pv210/include/mach/memory.h b/arch/arm/mach-s5pv210/include/mach/memory.h index d503e0c4ce4f..7b5fcf0da0c4 100644 --- a/arch/arm/mach-s5pv210/include/mach/memory.h +++ b/arch/arm/mach-s5pv210/include/mach/memory.h @@ -13,7 +13,7 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x20000000) +#define PLAT_PHYS_OFFSET UL(0x20000000) #define CONSISTENT_DMA_SIZE (SZ_8M + SZ_4M + SZ_2M) /* diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S index d4d222b716b4..a3d649466fb1 100644 --- a/arch/arm/mach-s5pv210/sleep.S +++ b/arch/arm/mach-s5pv210/sleep.S @@ -35,50 +35,24 @@ /* s3c_cpu_save * * entry: - * r0 = save address (virtual addr of s3c_sleep_save_phys) + * r1 = v:p offset */ ENTRY(s3c_cpu_save) stmfd sp!, { r3 - r12, lr } - - mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID - mrc p15, 0, r5, c3, c0, 0 @ Domain ID - mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 - mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 - mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control - mrc p15, 0, r9, c1, c0, 0 @ Control register - mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register - mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls - mrc p15, 0, r12, c10, c2, 0 @ Read PRRR - mrc p15, 0, r3, c10, c2, 1 @ READ NMRR - - stmia r0, { r3 - r13 } - - bl s3c_pm_cb_flushcache + ldr r3, =resume_with_mmu + bl cpu_suspend ldr r0, =pm_cpu_sleep ldr r0, [ r0 ] mov pc, r0 resume_with_mmu: - /* - * After MMU is turned on, restore the previous MMU table. - */ - ldr r9 , =(PAGE_OFFSET - PHYS_OFFSET) - add r4, r4, r9 - str r12, [r4] - ldmfd sp!, { r3 - r12, pc } .ltorg - .data - - .global s3c_sleep_save_phys -s3c_sleep_save_phys: - .word 0 - /* sleep magic, to allow the bootloader to check for an valid * image to resume to. Must be the first word before the * s3c_cpu_resume entry. @@ -96,75 +70,4 @@ s3c_sleep_save_phys: */ ENTRY(s3c_cpu_resume) - mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE - msr cpsr_c, r0 - - mov r1, #0 - mcr p15, 0, r1, c8, c7, 0 @ invalidate TLBs - mcr p15, 0, r1, c7, c5, 0 @ invalidate I Cache - - ldr r0, s3c_sleep_save_phys @ address of restore block - ldmia r0, { r3 - r13 } - - mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID - mcr p15, 0, r5, c3, c0, 0 @ Domain ID - - mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control - mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 - mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 - - mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register - - mov r0, #0 - mcr p15, 0, r0, c8, c7, 0 @ Invalidate I & D TLB - - mov r0, #0 @ restore copro access - mcr p15, 0, r11, c1, c0, 2 @ Co-processor access - mcr p15, 0, r0, c7, c5, 4 - - mcr p15, 0, r12, c10, c2, 0 @ write PRRR - mcr p15, 0, r3, c10, c2, 1 @ write NMRR - - /* - * In Cortex-A8, when MMU is turned on, the pipeline is flushed. - * And there are no valid entries in the MMU table at this point. - * So before turning on the MMU, the MMU entry for the DRAM address - * range is added. After the MMU is turned on, the other entries - * in the MMU table will be restored. - */ - - /* r6 = Translation Table BASE0 */ - mov r4, r6 - mov r4, r4, LSR #14 - mov r4, r4, LSL #14 - - /* Load address for adding to MMU table list */ - ldr r11, =0xE010F000 @ INFORM0 reg. - ldr r10, [r11, #0] - mov r10, r10, LSR #18 - bic r10, r10, #0x3 - orr r4, r4, r10 - - /* Calculate MMU table entry */ - mov r10, r10, LSL #18 - ldr r5, =0x40E - orr r10, r10, r5 - - /* Back up originally data */ - ldr r12, [r4] - - /* Add calculated MMU table entry into MMU table list */ - str r10, [r4] - - ldr r2, =resume_with_mmu - mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, etc - - nop - nop - nop - nop - nop @ second-to-last before mmu - - mov pc, r2 @ go back to virtual address - - .ltorg + b cpu_resume diff --git a/arch/arm/mach-s5pv310/cpufreq.c b/arch/arm/mach-s5pv310/cpufreq.c index b04cbc731128..7c08ad7d8887 100644 --- a/arch/arm/mach-s5pv310/cpufreq.c +++ b/arch/arm/mach-s5pv310/cpufreq.c @@ -458,8 +458,7 @@ static int s5pv310_target(struct cpufreq_policy *policy, } #ifdef CONFIG_PM -static int s5pv310_cpufreq_suspend(struct cpufreq_policy *policy, - pm_message_t pmsg) +static int s5pv310_cpufreq_suspend(struct cpufreq_policy *policy) { return 0; } diff --git a/arch/arm/mach-s5pv310/include/mach/memory.h b/arch/arm/mach-s5pv310/include/mach/memory.h index 1dffb4823245..470b01bf8614 100644 --- a/arch/arm/mach-s5pv310/include/mach/memory.h +++ b/arch/arm/mach-s5pv310/include/mach/memory.h @@ -13,7 +13,7 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H __FILE__ -#define PHYS_OFFSET UL(0x40000000) +#define PLAT_PHYS_OFFSET UL(0x40000000) /* Maximum of 256MiB in one bank */ #define MAX_PHYSMEM_BITS 32 diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h index 128a1dfa96b9..a44da6a2916c 100644 --- a/arch/arm/mach-sa1100/include/mach/memory.h +++ b/arch/arm/mach-sa1100/include/mach/memory.h @@ -12,7 +12,7 @@ /* * Physical DRAM offset is 0xc0000000 on the SA1100 */ -#define PHYS_OFFSET UL(0xc0000000) +#define PLAT_PHYS_OFFSET UL(0xc0000000) #ifndef __ASSEMBLY__ diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c index ab9fc4470d36..c4661aab22fb 100644 --- a/arch/arm/mach-sa1100/pm.c +++ b/arch/arm/mach-sa1100/pm.c @@ -32,8 +32,7 @@ #include <asm/system.h> #include <asm/mach/time.h> -extern void sa1100_cpu_suspend(void); -extern void sa1100_cpu_resume(void); +extern void sa1100_cpu_suspend(long); #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] @@ -73,10 +72,10 @@ static int sa11x0_pm_enter(suspend_state_t state) RCSR = RCSR_HWR | RCSR_SWR | RCSR_WDR | RCSR_SMR; /* set resume return address */ - PSPR = virt_to_phys(sa1100_cpu_resume); + PSPR = virt_to_phys(cpu_resume); /* go zzz */ - sa1100_cpu_suspend(); + sa1100_cpu_suspend(PLAT_PHYS_OFFSET - PAGE_OFFSET); cpu_init(); @@ -115,11 +114,6 @@ static int sa11x0_pm_enter(suspend_state_t state) return 0; } -unsigned long sleep_phys_sp(void *sp) -{ - return virt_to_phys(sp); -} - static const struct platform_suspend_ops sa11x0_pm_ops = { .enter = sa11x0_pm_enter, .valid = suspend_valid_only_mem, diff --git a/arch/arm/mach-sa1100/sleep.S b/arch/arm/mach-sa1100/sleep.S index 80f31bad707c..04f2a618d4ef 100644 --- a/arch/arm/mach-sa1100/sleep.S +++ b/arch/arm/mach-sa1100/sleep.S @@ -20,12 +20,7 @@ #include <asm/assembler.h> #include <mach/hardware.h> - - .text - - - /* * sa1100_cpu_suspend() * @@ -34,27 +29,10 @@ */ ENTRY(sa1100_cpu_suspend) - stmfd sp!, {r4 - r12, lr} @ save registers on stack - - @ get coprocessor registers - mrc p15, 0, r4, c3, c0, 0 @ domain ID - mrc p15, 0, r5, c2, c0, 0 @ translation table base addr - mrc p15, 0, r6, c13, c0, 0 @ PID - mrc p15, 0, r7, c1, c0, 0 @ control reg - - @ store them plus current virtual stack ptr on stack - mov r8, sp - stmfd sp!, {r4 - r8} - - @ preserve phys address of stack - mov r0, sp - bl sleep_phys_sp - ldr r1, =sleep_save_sp - str r0, [r1] - - @ clean data cache and invalidate WB - bl v4wb_flush_kern_cache_all + mov r1, r0 + ldr r3, =sa1100_cpu_resume @ return function + bl cpu_suspend @ disable clock switching mcr p15, 0, r1, c15, c2, 2 @@ -166,50 +144,8 @@ sa1110_sdram_controller_fix: * cpu_sa1100_resume() * * entry point from bootloader into kernel during resume - * - * Note: Yes, part of the following code is located into the .data section. - * This is to allow sleep_save_sp to be accessed with a relative load - * while we can't rely on any MMU translation. We could have put - * sleep_save_sp in the .text section as well, but some setups might - * insist on it to be truly read-only. */ - - .data - .align 5 -ENTRY(sa1100_cpu_resume) - mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE - msr cpsr_c, r0 @ set SVC, irqs off - - ldr r0, sleep_save_sp @ stack phys addr - ldr r2, =resume_after_mmu @ its absolute virtual address - ldmfd r0, {r4 - r7, sp} @ CP regs + virt stack ptr - - mov r1, #0 - mcr p15, 0, r1, c8, c7, 0 @ flush I+D TLBs - mcr p15, 0, r1, c7, c7, 0 @ flush I&D cache - mcr p15, 0, r1, c9, c0, 0 @ invalidate RB - mcr p15, 0, r1, c9, c0, 5 @ allow user space to use RB - - mcr p15, 0, r4, c3, c0, 0 @ domain ID - mcr p15, 0, r5, c2, c0, 0 @ translation table base addr - mcr p15, 0, r6, c13, c0, 0 @ PID - b resume_turn_on_mmu @ cache align execution - .align 5 -resume_turn_on_mmu: - mcr p15, 0, r7, c1, c0, 0 @ turn on MMU, caches, etc. - nop - mov pc, r2 @ jump to virtual addr - nop - nop - nop - -sleep_save_sp: - .word 0 @ preserve stack phys ptr here - - .text -resume_after_mmu: +sa1100_cpu_resume: mcr p15, 0, r1, c15, c1, 2 @ enable clock switching ldmfd sp!, {r4 - r12, pc} @ return to caller - - diff --git a/arch/arm/mach-shark/include/mach/memory.h b/arch/arm/mach-shark/include/mach/memory.h index d9c4812f1c31..9afb17000008 100644 --- a/arch/arm/mach-shark/include/mach/memory.h +++ b/arch/arm/mach-shark/include/mach/memory.h @@ -15,7 +15,7 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x08000000) +#define PLAT_PHYS_OFFSET UL(0x08000000) #ifndef __ASSEMBLY__ diff --git a/arch/arm/mach-shmobile/include/mach/memory.h b/arch/arm/mach-shmobile/include/mach/memory.h index 377584e57e03..ad00c3c258f4 100644 --- a/arch/arm/mach-shmobile/include/mach/memory.h +++ b/arch/arm/mach-shmobile/include/mach/memory.h @@ -1,7 +1,7 @@ #ifndef __ASM_MACH_MEMORY_H #define __ASM_MACH_MEMORY_H -#define PHYS_OFFSET UL(CONFIG_MEMORY_START) +#define PLAT_PHYS_OFFSET UL(CONFIG_MEMORY_START) #define MEM_SIZE UL(CONFIG_MEMORY_SIZE) /* DMA memory at 0xf6000000 - 0xffdfffff */ diff --git a/arch/arm/mach-shmobile/include/mach/mmcif-ap4eb.h b/arch/arm/mach-shmobile/include/mach/mmcif-ap4eb.h new file mode 100644 index 000000000000..a8d02be8d2b6 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/mmcif-ap4eb.h @@ -0,0 +1,29 @@ +#ifndef MMCIF_AP4EB_H +#define MMCIF_AP4EB_H + +#define PORT185CR (void __iomem *)0xe60520b9 +#define PORT186CR (void __iomem *)0xe60520ba +#define PORT187CR (void __iomem *)0xe60520bb +#define PORT188CR (void __iomem *)0xe60520bc + +#define PORTR191_160DR (void __iomem *)0xe6056014 + +static inline void mmcif_init_progress(void) +{ + /* Initialise LEDS1-4 + * registers: PORT185CR-PORT188CR (LED1-LED4 Control) + * value: 0x10 - enable output + */ + __raw_writeb(0x10, PORT185CR); + __raw_writeb(0x10, PORT186CR); + __raw_writeb(0x10, PORT187CR); + __raw_writeb(0x10, PORT188CR); +} + +static inline void mmcif_update_progress(int n) +{ + __raw_writel((__raw_readl(PORTR191_160DR) & ~(0xf << 25)) | + (1 << (25 + n)), PORTR191_160DR); +} + +#endif /* MMCIF_AP4EB_H */ diff --git a/arch/arm/mach-shmobile/include/mach/mmcif-mackerel.h b/arch/arm/mach-shmobile/include/mach/mmcif-mackerel.h new file mode 100644 index 000000000000..4b4f6949a868 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/mmcif-mackerel.h @@ -0,0 +1,39 @@ +#ifndef MMCIF_MACKEREL_H +#define MMCIF_MACKEREL_H + +#define PORT0CR (void __iomem *)0xe6051000 +#define PORT1CR (void __iomem *)0xe6051001 +#define PORT2CR (void __iomem *)0xe6051002 +#define PORT159CR (void __iomem *)0xe605009f + +#define PORTR031_000DR (void __iomem *)0xe6055000 +#define PORTL159_128DR (void __iomem *)0xe6054010 + +static inline void mmcif_init_progress(void) +{ + /* Initialise LEDS0-3 + * registers: PORT0CR-PORT2CR,PORT159CR (LED0-LED3 Control) + * value: 0x10 - enable output + */ + __raw_writeb(0x10, PORT0CR); + __raw_writeb(0x10, PORT1CR); + __raw_writeb(0x10, PORT2CR); + __raw_writeb(0x10, PORT159CR); +} + +static inline void mmcif_update_progress(int n) +{ + unsigned a = 0, b = 0; + + if (n < 3) + a = 1 << n; + else + b = 1 << 31; + + __raw_writel((__raw_readl(PORTR031_000DR) & ~0x7) | a, + PORTR031_000DR); + __raw_writel((__raw_readl(PORTL159_128DR) & ~(1 << 31)) | b, + PORTL159_128DR); +} + +#endif /* MMCIF_MACKEREL_H */ diff --git a/arch/arm/mach-shmobile/include/mach/mmcif.h b/arch/arm/mach-shmobile/include/mach/mmcif.h new file mode 100644 index 000000000000..f4dc3279cf03 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/mmcif.h @@ -0,0 +1,18 @@ +#ifndef MMCIF_H +#define MMCIF_H + +/************************************************** + * + * board specific settings + * + **************************************************/ + +#ifdef CONFIG_MACH_AP4EVB +#include "mach/mmcif-ap4eb.h" +#elif CONFIG_MACH_MACKEREL +#include "mach/mmcif-mackerel.h" +#else +#error "unsupported board." +#endif + +#endif /* MMCIF_H */ diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c index 18febf92f20a..98bc7edc95a6 100644 --- a/arch/arm/mach-spear3xx/clock.c +++ b/arch/arm/mach-spear3xx/clock.c @@ -13,8 +13,8 @@ #include <linux/init.h> #include <linux/kernel.h> -#include <mach/misc_regs.h> #include <plat/clock.h> +#include <mach/misc_regs.h> /* root clks */ /* 32 KHz oscillator clock */ @@ -39,18 +39,43 @@ static struct clk rtc_clk = { }; /* clock derived from 24 MHz osc clk */ +/* pll masks structure */ +static struct pll_clk_masks pll1_masks = { + .mode_mask = PLL_MODE_MASK, + .mode_shift = PLL_MODE_SHIFT, + .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK, + .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT, + .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK, + .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT, + .div_p_mask = PLL_DIV_P_MASK, + .div_p_shift = PLL_DIV_P_SHIFT, + .div_n_mask = PLL_DIV_N_MASK, + .div_n_shift = PLL_DIV_N_SHIFT, +}; + /* pll1 configuration structure */ static struct pll_clk_config pll1_config = { .mode_reg = PLL1_CTR, .cfg_reg = PLL1_FRQ, + .masks = &pll1_masks, +}; + +/* pll rate configuration table, in ascending order of rates */ +struct pll_rate_tbl pll_rtbl[] = { + {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */ + {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */ }; /* PLL1 clock */ static struct clk pll1_clk = { + .flags = ENABLED_ON_INIT, .pclk = &osc_24m_clk, .en_reg = PLL1_CTR, .en_reg_bit = PLL_ENABLE, - .recalc = &pll1_clk_recalc, + .calc_rate = &pll_calc_rate, + .recalc = &pll_clk_recalc, + .set_rate = &pll_clk_set_rate, + .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1}, .private_data = &pll1_config, }; @@ -76,36 +101,83 @@ static struct clk cpu_clk = { .recalc = &follow_parent, }; +/* ahb masks structure */ +static struct bus_clk_masks ahb_masks = { + .mask = PLL_HCLK_RATIO_MASK, + .shift = PLL_HCLK_RATIO_SHIFT, +}; + /* ahb configuration structure */ static struct bus_clk_config ahb_config = { .reg = CORE_CLK_CFG, - .mask = PLL_HCLK_RATIO_MASK, - .shift = PLL_HCLK_RATIO_SHIFT, + .masks = &ahb_masks, +}; + +/* ahb rate configuration table, in ascending order of rates */ +struct bus_rate_tbl bus_rtbl[] = { + {.div = 3}, /* == parent divided by 4 */ + {.div = 2}, /* == parent divided by 3 */ + {.div = 1}, /* == parent divided by 2 */ + {.div = 0}, /* == parent divided by 1 */ }; /* ahb clock */ static struct clk ahb_clk = { .flags = ALWAYS_ENABLED, .pclk = &pll1_clk, + .calc_rate = &bus_calc_rate, .recalc = &bus_clk_recalc, + .set_rate = &bus_clk_set_rate, + .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2}, .private_data = &ahb_config, }; -/* uart configurations */ -static struct aux_clk_config uart_config = { +/* auxiliary synthesizers masks */ +static struct aux_clk_masks aux_masks = { + .eq_sel_mask = AUX_EQ_SEL_MASK, + .eq_sel_shift = AUX_EQ_SEL_SHIFT, + .eq1_mask = AUX_EQ1_SEL, + .eq2_mask = AUX_EQ2_SEL, + .xscale_sel_mask = AUX_XSCALE_MASK, + .xscale_sel_shift = AUX_XSCALE_SHIFT, + .yscale_sel_mask = AUX_YSCALE_MASK, + .yscale_sel_shift = AUX_YSCALE_SHIFT, +}; + +/* uart synth configurations */ +static struct aux_clk_config uart_synth_config = { .synth_reg = UART_CLK_SYNT, + .masks = &aux_masks, +}; + +/* aux rate configuration table, in ascending order of rates */ +struct aux_rate_tbl aux_rtbl[] = { + /* For PLL1 = 332 MHz */ + {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */ + {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */ + {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */ +}; + +/* uart synth clock */ +static struct clk uart_synth_clk = { + .en_reg = UART_CLK_SYNT, + .en_reg_bit = AUX_SYNT_ENB, + .pclk = &pll1_clk, + .calc_rate = &aux_calc_rate, + .recalc = &aux_clk_recalc, + .set_rate = &aux_clk_set_rate, + .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1}, + .private_data = &uart_synth_config, }; /* uart parents */ static struct pclk_info uart_pclk_info[] = { { - .pclk = &pll1_clk, - .pclk_mask = AUX_CLK_PLL1_MASK, - .scalable = 1, + .pclk = &uart_synth_clk, + .pclk_val = AUX_CLK_PLL1_VAL, }, { .pclk = &pll3_48m_clk, - .pclk_mask = AUX_CLK_PLL3_MASK, - .scalable = 0, + .pclk_val = AUX_CLK_PLL3_VAL, }, }; @@ -123,25 +195,35 @@ static struct clk uart_clk = { .en_reg_bit = UART_CLK_ENB, .pclk_sel = &uart_pclk_sel, .pclk_sel_shift = UART_CLK_SHIFT, - .recalc = &aux_clk_recalc, - .private_data = &uart_config, + .recalc = &follow_parent, }; /* firda configurations */ -static struct aux_clk_config firda_config = { +static struct aux_clk_config firda_synth_config = { .synth_reg = FIRDA_CLK_SYNT, + .masks = &aux_masks, +}; + +/* firda synth clock */ +static struct clk firda_synth_clk = { + .en_reg = FIRDA_CLK_SYNT, + .en_reg_bit = AUX_SYNT_ENB, + .pclk = &pll1_clk, + .calc_rate = &aux_calc_rate, + .recalc = &aux_clk_recalc, + .set_rate = &aux_clk_set_rate, + .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1}, + .private_data = &firda_synth_config, }; /* firda parents */ static struct pclk_info firda_pclk_info[] = { { - .pclk = &pll1_clk, - .pclk_mask = AUX_CLK_PLL1_MASK, - .scalable = 1, + .pclk = &firda_synth_clk, + .pclk_val = AUX_CLK_PLL1_VAL, }, { .pclk = &pll3_48m_clk, - .pclk_mask = AUX_CLK_PLL3_MASK, - .scalable = 0, + .pclk_val = AUX_CLK_PLL3_VAL, }, }; @@ -159,73 +241,155 @@ static struct clk firda_clk = { .en_reg_bit = FIRDA_CLK_ENB, .pclk_sel = &firda_pclk_sel, .pclk_sel_shift = FIRDA_CLK_SHIFT, - .recalc = &aux_clk_recalc, - .private_data = &firda_config, + .recalc = &follow_parent, +}; + +/* gpt synthesizer masks */ +static struct gpt_clk_masks gpt_masks = { + .mscale_sel_mask = GPT_MSCALE_MASK, + .mscale_sel_shift = GPT_MSCALE_SHIFT, + .nscale_sel_mask = GPT_NSCALE_MASK, + .nscale_sel_shift = GPT_NSCALE_SHIFT, +}; + +/* gpt rate configuration table, in ascending order of rates */ +struct gpt_rate_tbl gpt_rtbl[] = { + /* For pll1 = 332 MHz */ + {.mscale = 4, .nscale = 0}, /* 41.5 MHz */ + {.mscale = 2, .nscale = 0}, /* 55.3 MHz */ + {.mscale = 1, .nscale = 0}, /* 83 MHz */ +}; + +/* gpt0 synth clk config*/ +static struct gpt_clk_config gpt0_synth_config = { + .synth_reg = PRSC1_CLK_CFG, + .masks = &gpt_masks, +}; + +/* gpt synth clock */ +static struct clk gpt0_synth_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll1_clk, + .calc_rate = &gpt_calc_rate, + .recalc = &gpt_clk_recalc, + .set_rate = &gpt_clk_set_rate, + .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2}, + .private_data = &gpt0_synth_config, }; /* gpt parents */ -static struct pclk_info gpt_pclk_info[] = { +static struct pclk_info gpt0_pclk_info[] = { { - .pclk = &pll1_clk, - .pclk_mask = AUX_CLK_PLL1_MASK, - .scalable = 1, + .pclk = &gpt0_synth_clk, + .pclk_val = AUX_CLK_PLL1_VAL, }, { .pclk = &pll3_48m_clk, - .pclk_mask = AUX_CLK_PLL3_MASK, - .scalable = 0, + .pclk_val = AUX_CLK_PLL3_VAL, }, }; /* gpt parent select structure */ -static struct pclk_sel gpt_pclk_sel = { - .pclk_info = gpt_pclk_info, - .pclk_count = ARRAY_SIZE(gpt_pclk_info), +static struct pclk_sel gpt0_pclk_sel = { + .pclk_info = gpt0_pclk_info, + .pclk_count = ARRAY_SIZE(gpt0_pclk_info), .pclk_sel_reg = PERIP_CLK_CFG, .pclk_sel_mask = GPT_CLK_MASK, }; -/* gpt0 configurations */ -static struct aux_clk_config gpt0_config = { - .synth_reg = PRSC1_CLK_CFG, -}; - /* gpt0 timer clock */ static struct clk gpt0_clk = { .flags = ALWAYS_ENABLED, - .pclk_sel = &gpt_pclk_sel, + .pclk_sel = &gpt0_pclk_sel, .pclk_sel_shift = GPT0_CLK_SHIFT, - .recalc = &gpt_clk_recalc, - .private_data = &gpt0_config, + .recalc = &follow_parent, }; -/* gpt1 configurations */ -static struct aux_clk_config gpt1_config = { +/* gpt1 synth clk configurations */ +static struct gpt_clk_config gpt1_synth_config = { .synth_reg = PRSC2_CLK_CFG, + .masks = &gpt_masks, +}; + +/* gpt1 synth clock */ +static struct clk gpt1_synth_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll1_clk, + .calc_rate = &gpt_calc_rate, + .recalc = &gpt_clk_recalc, + .set_rate = &gpt_clk_set_rate, + .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2}, + .private_data = &gpt1_synth_config, +}; + +static struct pclk_info gpt1_pclk_info[] = { + { + .pclk = &gpt1_synth_clk, + .pclk_val = AUX_CLK_PLL1_VAL, + }, { + .pclk = &pll3_48m_clk, + .pclk_val = AUX_CLK_PLL3_VAL, + }, +}; + +/* gpt parent select structure */ +static struct pclk_sel gpt1_pclk_sel = { + .pclk_info = gpt1_pclk_info, + .pclk_count = ARRAY_SIZE(gpt1_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = GPT_CLK_MASK, }; /* gpt1 timer clock */ static struct clk gpt1_clk = { .en_reg = PERIP1_CLK_ENB, .en_reg_bit = GPT1_CLK_ENB, - .pclk_sel = &gpt_pclk_sel, + .pclk_sel = &gpt1_pclk_sel, .pclk_sel_shift = GPT1_CLK_SHIFT, - .recalc = &gpt_clk_recalc, - .private_data = &gpt1_config, + .recalc = &follow_parent, }; -/* gpt2 configurations */ -static struct aux_clk_config gpt2_config = { +/* gpt2 synth clk configurations */ +static struct gpt_clk_config gpt2_synth_config = { .synth_reg = PRSC3_CLK_CFG, + .masks = &gpt_masks, +}; + +/* gpt1 synth clock */ +static struct clk gpt2_synth_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll1_clk, + .calc_rate = &gpt_calc_rate, + .recalc = &gpt_clk_recalc, + .set_rate = &gpt_clk_set_rate, + .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2}, + .private_data = &gpt2_synth_config, +}; + +static struct pclk_info gpt2_pclk_info[] = { + { + .pclk = &gpt2_synth_clk, + .pclk_val = AUX_CLK_PLL1_VAL, + }, { + .pclk = &pll3_48m_clk, + .pclk_val = AUX_CLK_PLL3_VAL, + }, +}; + +/* gpt parent select structure */ +static struct pclk_sel gpt2_pclk_sel = { + .pclk_info = gpt2_pclk_info, + .pclk_count = ARRAY_SIZE(gpt2_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = GPT_CLK_MASK, }; /* gpt2 timer clock */ static struct clk gpt2_clk = { .en_reg = PERIP1_CLK_ENB, .en_reg_bit = GPT2_CLK_ENB, - .pclk_sel = &gpt_pclk_sel, + .pclk_sel = &gpt2_pclk_sel, .pclk_sel_shift = GPT2_CLK_SHIFT, - .recalc = &gpt_clk_recalc, - .private_data = &gpt2_config, + .recalc = &follow_parent, }; /* clock derived from pll3 clk */ @@ -245,26 +409,27 @@ static struct clk usbd_clk = { .recalc = &follow_parent, }; -/* clcd clock */ -static struct clk clcd_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &pll3_48m_clk, - .recalc = &follow_parent, +/* clock derived from ahb clk */ +/* apb masks structure */ +static struct bus_clk_masks apb_masks = { + .mask = HCLK_PCLK_RATIO_MASK, + .shift = HCLK_PCLK_RATIO_SHIFT, }; -/* clock derived from ahb clk */ /* apb configuration structure */ static struct bus_clk_config apb_config = { .reg = CORE_CLK_CFG, - .mask = HCLK_PCLK_RATIO_MASK, - .shift = HCLK_PCLK_RATIO_SHIFT, + .masks = &apb_masks, }; /* apb clock */ static struct clk apb_clk = { .flags = ALWAYS_ENABLED, .pclk = &ahb_clk, + .calc_rate = &bus_calc_rate, .recalc = &bus_clk_recalc, + .set_rate = &bus_clk_set_rate, + .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2}, .private_data = &apb_config, }; @@ -325,8 +490,17 @@ static struct clk adc_clk = { .recalc = &follow_parent, }; +#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) +/* emi clock */ +static struct clk emi_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &ahb_clk, + .recalc = &follow_parent, +}; +#endif + /* ssp clock */ -static struct clk ssp_clk = { +static struct clk ssp0_clk = { .pclk = &apb_clk, .en_reg = PERIP1_CLK_ENB, .en_reg_bit = SSP_CLK_ENB, @@ -343,14 +517,145 @@ static struct clk gpio_clk = { static struct clk dummy_apb_pclk; +#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \ + defined(CONFIG_MACH_SPEAR320) +/* fsmc clock */ +static struct clk fsmc_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &ahb_clk, + .recalc = &follow_parent, +}; +#endif + +/* common clocks to spear310 and spear320 */ +#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) +/* uart1 clock */ +static struct clk uart1_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; + +/* uart2 clock */ +static struct clk uart2_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; +#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */ + +/* common clocks to spear300 and spear320 */ +#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320) +/* clcd clock */ +static struct clk clcd_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll3_48m_clk, + .recalc = &follow_parent, +}; + +/* sdhci clock */ +static struct clk sdhci_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &ahb_clk, + .recalc = &follow_parent, +}; +#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */ + +/* spear300 machine specific clock structures */ +#ifdef CONFIG_MACH_SPEAR300 +/* gpio1 clock */ +static struct clk gpio1_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; + +/* keyboard clock */ +static struct clk kbd_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; + +#endif + +/* spear310 machine specific clock structures */ +#ifdef CONFIG_MACH_SPEAR310 +/* uart3 clock */ +static struct clk uart3_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; + +/* uart4 clock */ +static struct clk uart4_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; + +/* uart5 clock */ +static struct clk uart5_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; +#endif + +/* spear320 machine specific clock structures */ +#ifdef CONFIG_MACH_SPEAR320 +/* can0 clock */ +static struct clk can0_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; + +/* can1 clock */ +static struct clk can1_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; + +/* i2c1 clock */ +static struct clk i2c1_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &ahb_clk, + .recalc = &follow_parent, +}; + +/* ssp1 clock */ +static struct clk ssp1_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; + +/* ssp2 clock */ +static struct clk ssp2_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; + +/* pwm clock */ +static struct clk pwm_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; +#endif + /* array of all spear 3xx clock lookups */ static struct clk_lookup spear_clk_lookups[] = { - { .con_id = "apb_pclk", .clk = &dummy_apb_pclk}, + { .con_id = "apb_pclk", .clk = &dummy_apb_pclk}, /* root clks */ { .con_id = "osc_32k_clk", .clk = &osc_32k_clk}, { .con_id = "osc_24m_clk", .clk = &osc_24m_clk}, /* clock derived from 32 KHz osc clk */ - { .dev_id = "rtc", .clk = &rtc_clk}, + { .dev_id = "rtc-spear", .clk = &rtc_clk}, /* clock derived from 24 MHz osc clk */ { .con_id = "pll1_clk", .clk = &pll1_clk}, { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk}, @@ -358,18 +663,22 @@ static struct clk_lookup spear_clk_lookups[] = { /* clock derived from pll1 clk */ { .con_id = "cpu_clk", .clk = &cpu_clk}, { .con_id = "ahb_clk", .clk = &ahb_clk}, + { .con_id = "uart_synth_clk", .clk = &uart_synth_clk}, + { .con_id = "firda_synth_clk", .clk = &firda_synth_clk}, + { .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk}, + { .con_id = "gpt1_synth_clk", .clk = &gpt1_synth_clk}, + { .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk}, { .dev_id = "uart", .clk = &uart_clk}, { .dev_id = "firda", .clk = &firda_clk}, { .dev_id = "gpt0", .clk = &gpt0_clk}, { .dev_id = "gpt1", .clk = &gpt1_clk}, { .dev_id = "gpt2", .clk = &gpt2_clk}, /* clock derived from pll3 clk */ - { .dev_id = "usbh", .clk = &usbh_clk}, - { .dev_id = "usbd", .clk = &usbd_clk}, - { .dev_id = "clcd", .clk = &clcd_clk}, + { .dev_id = "designware_udc", .clk = &usbd_clk}, + { .con_id = "usbh_clk", .clk = &usbh_clk}, /* clock derived from ahb clk */ { .con_id = "apb_clk", .clk = &apb_clk}, - { .dev_id = "i2c", .clk = &i2c_clk}, + { .dev_id = "i2c_designware.0", .clk = &i2c_clk}, { .dev_id = "dma", .clk = &dma_clk}, { .dev_id = "jpeg", .clk = &jpeg_clk}, { .dev_id = "gmac", .clk = &gmac_clk}, @@ -377,8 +686,50 @@ static struct clk_lookup spear_clk_lookups[] = { { .dev_id = "c3", .clk = &c3_clk}, /* clock derived from apb clk */ { .dev_id = "adc", .clk = &adc_clk}, - { .dev_id = "ssp", .clk = &ssp_clk}, + { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk}, { .dev_id = "gpio", .clk = &gpio_clk}, +#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) + { .dev_id = "physmap-flash", .clk = &emi_clk}, +#endif +#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \ + defined(CONFIG_MACH_SPEAR320) + { .con_id = "fsmc", .clk = &fsmc_clk}, +#endif + +/* common clocks to spear310 and spear320 */ +#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) + { .dev_id = "uart1", .clk = &uart1_clk}, + { .dev_id = "uart2", .clk = &uart2_clk}, +#endif + + /* common clock to spear300 and spear320 */ +#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320) + { .dev_id = "clcd", .clk = &clcd_clk}, + { .dev_id = "sdhci", .clk = &sdhci_clk}, +#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */ + + /* spear300 machine specific clock structures */ +#ifdef CONFIG_MACH_SPEAR300 + { .dev_id = "gpio1", .clk = &gpio1_clk}, + { .dev_id = "keyboard", .clk = &kbd_clk}, +#endif + + /* spear310 machine specific clock structures */ +#ifdef CONFIG_MACH_SPEAR310 + { .dev_id = "uart3", .clk = &uart3_clk}, + { .dev_id = "uart4", .clk = &uart4_clk}, + { .dev_id = "uart5", .clk = &uart5_clk}, + +#endif + /* spear320 machine specific clock structures */ +#ifdef CONFIG_MACH_SPEAR320 + { .dev_id = "c_can_platform.0", .clk = &can0_clk}, + { .dev_id = "c_can_platform.1", .clk = &can1_clk}, + { .dev_id = "i2c_designware.1", .clk = &i2c1_clk}, + { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk}, + { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk}, + { .dev_id = "pwm", .clk = &pwm_clk}, +#endif }; void __init clk_init(void) diff --git a/arch/arm/mach-spear3xx/include/mach/entry-macro.S b/arch/arm/mach-spear3xx/include/mach/entry-macro.S index 947625d6b48d..53da4224ba3d 100644 --- a/arch/arm/mach-spear3xx/include/mach/entry-macro.S +++ b/arch/arm/mach-spear3xx/include/mach/entry-macro.S @@ -11,9 +11,8 @@ * warranty of any kind, whether express or implied. */ -#include <mach/hardware.h> -#include <mach/spear.h> #include <asm/hardware/vic.h> +#include <mach/hardware.h> .macro disable_fiq .endm diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h index af7e02c909a3..8e30636909ef 100644 --- a/arch/arm/mach-spear3xx/include/mach/generic.h +++ b/arch/arm/mach-spear3xx/include/mach/generic.h @@ -14,11 +14,11 @@ #ifndef __MACH_GENERIC_H #define __MACH_GENERIC_H -#include <asm/mach/time.h> -#include <asm/mach/map.h> #include <linux/init.h> #include <linux/platform_device.h> #include <linux/amba/bus.h> +#include <asm/mach/time.h> +#include <asm/mach/map.h> #include <plat/padmux.h> /* spear3xx declarations */ @@ -33,14 +33,14 @@ /* Add spear3xx family device structure declarations here */ extern struct amba_device gpio_device; extern struct amba_device uart_device; -extern struct sys_timer spear_sys_timer; +extern struct sys_timer spear3xx_timer; /* Add spear3xx family function declarations here */ void __init clk_init(void); +void __init spear_setup_timer(void); void __init spear3xx_map_io(void); void __init spear3xx_init_irq(void); void __init spear3xx_init(void); -void spear_pmx_init(struct pmx_driver *pmx_driver, uint base, uint size); /* pad mux declarations */ #define PMX_FIRDA_MASK (1 << 14) @@ -129,12 +129,10 @@ extern struct pmx_dev pmx_telecom_camera; extern struct pmx_dev pmx_telecom_dac; extern struct pmx_dev pmx_telecom_i2s; extern struct pmx_dev pmx_telecom_boot_pins; -extern struct pmx_dev pmx_telecom_sdio_4bit; -extern struct pmx_dev pmx_telecom_sdio_8bit; +extern struct pmx_dev pmx_telecom_sdhci_4bit; +extern struct pmx_dev pmx_telecom_sdhci_8bit; extern struct pmx_dev pmx_gpio1; -void spear300_pmx_init(void); - /* Add spear300 machine function declarations here */ void __init spear300_init(void); @@ -154,8 +152,6 @@ extern struct pmx_dev pmx_fsmc; extern struct pmx_dev pmx_rs485_0_1; extern struct pmx_dev pmx_tdm0; -void spear310_pmx_init(void); - /* Add spear310 machine function declarations here */ void __init spear310_init(void); @@ -176,14 +172,14 @@ extern struct pmx_dev pmx_clcd; extern struct pmx_dev pmx_emi; extern struct pmx_dev pmx_fsmc; extern struct pmx_dev pmx_spp; -extern struct pmx_dev pmx_sdio; +extern struct pmx_dev pmx_sdhci; extern struct pmx_dev pmx_i2s; extern struct pmx_dev pmx_uart1; extern struct pmx_dev pmx_uart1_modem; extern struct pmx_dev pmx_uart2; extern struct pmx_dev pmx_touchscreen; extern struct pmx_dev pmx_can; -extern struct pmx_dev pmx_sdio_led; +extern struct pmx_dev pmx_sdhci_led; extern struct pmx_dev pmx_pwm0; extern struct pmx_dev pmx_pwm1; extern struct pmx_dev pmx_pwm2; @@ -195,8 +191,6 @@ extern struct pmx_dev pmx_smii0; extern struct pmx_dev pmx_smii1; extern struct pmx_dev pmx_i2c1; -void spear320_pmx_init(void); - /* Add spear320 machine function declarations here */ void __init spear320_init(void); diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h index 4a86e6a3c444..4660c0d8ec0d 100644 --- a/arch/arm/mach-spear3xx/include/mach/hardware.h +++ b/arch/arm/mach-spear3xx/include/mach/hardware.h @@ -14,6 +14,9 @@ #ifndef __MACH_HARDWARE_H #define __MACH_HARDWARE_H +#include <plat/hardware.h> +#include <mach/spear.h> + /* Vitual to physical translation of statically mapped space */ #define IO_ADDRESS(x) (x | 0xF0000000) diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h index 7f940b818473..a1a7f481866d 100644 --- a/arch/arm/mach-spear3xx/include/mach/irqs.h +++ b/arch/arm/mach-spear3xx/include/mach/irqs.h @@ -69,7 +69,7 @@ #define IRQ_CLCD IRQ_GEN_RAS_3 /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ -#define IRQ_SDIO IRQ_INTRCOMM_RAS_ARM +#define IRQ_SDHCI IRQ_INTRCOMM_RAS_ARM /* GPIO pins virtual irqs */ #define SPEAR_GPIO_INT_BASE (VIRQ_START + 9) @@ -115,7 +115,7 @@ #define VIRQ_SPP (VIRQ_START + 2) /* IRQs sharing IRQ_GEN_RAS_2 */ -#define IRQ_SDIO IRQ_GEN_RAS_2 +#define IRQ_SDHCI IRQ_GEN_RAS_2 /* IRQs sharing IRQ_GEN_RAS_3 */ #define VIRQ_PLGPIO (VIRQ_START + 3) diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h index 38d767a1aba0..5bd8cd8d4852 100644 --- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h +++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h @@ -14,16 +14,16 @@ #ifndef __MACH_MISC_REGS_H #define __MACH_MISC_REGS_H -#include <mach/spear.h> +#include <mach/hardware.h> -#define MISC_BASE VA_SPEAR3XX_ICM3_MISC_REG_BASE +#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE) -#define SOC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x000)) -#define DIAG_CFG_CTR ((unsigned int *)(MISC_BASE + 0x004)) -#define PLL1_CTR ((unsigned int *)(MISC_BASE + 0x008)) -#define PLL1_FRQ ((unsigned int *)(MISC_BASE + 0x00C)) -#define PLL1_MOD ((unsigned int *)(MISC_BASE + 0x010)) -#define PLL2_CTR ((unsigned int *)(MISC_BASE + 0x014)) +#define SOC_CFG_CTR (MISC_BASE + 0x000) +#define DIAG_CFG_CTR (MISC_BASE + 0x004) +#define PLL1_CTR (MISC_BASE + 0x008) +#define PLL1_FRQ (MISC_BASE + 0x00C) +#define PLL1_MOD (MISC_BASE + 0x010) +#define PLL2_CTR (MISC_BASE + 0x014) /* PLL_CTR register masks */ #define PLL_ENABLE 2 #define PLL_MODE_SHIFT 4 @@ -33,7 +33,7 @@ #define PLL_MODE_DITH_DSB 2 #define PLL_MODE_DITH_SSB 3 -#define PLL2_FRQ ((unsigned int *)(MISC_BASE + 0x018)) +#define PLL2_FRQ (MISC_BASE + 0x018) /* PLL FRQ register masks */ #define PLL_DIV_N_SHIFT 0 #define PLL_DIV_N_MASK 0xFF @@ -44,16 +44,16 @@ #define PLL_DITH_FDBK_M_SHIFT 16 #define PLL_DITH_FDBK_M_MASK 0xFFFF -#define PLL2_MOD ((unsigned int *)(MISC_BASE + 0x01C)) -#define PLL_CLK_CFG ((unsigned int *)(MISC_BASE + 0x020)) -#define CORE_CLK_CFG ((unsigned int *)(MISC_BASE + 0x024)) +#define PLL2_MOD (MISC_BASE + 0x01C) +#define PLL_CLK_CFG (MISC_BASE + 0x020) +#define CORE_CLK_CFG (MISC_BASE + 0x024) /* CORE CLK CFG register masks */ #define PLL_HCLK_RATIO_SHIFT 10 #define PLL_HCLK_RATIO_MASK 0x3 #define HCLK_PCLK_RATIO_SHIFT 8 #define HCLK_PCLK_RATIO_MASK 0x3 -#define PERIP_CLK_CFG ((unsigned int *)(MISC_BASE + 0x028)) +#define PERIP_CLK_CFG (MISC_BASE + 0x028) /* PERIP_CLK_CFG register masks */ #define UART_CLK_SHIFT 4 #define UART_CLK_MASK 0x1 @@ -63,10 +63,10 @@ #define GPT1_CLK_SHIFT 11 #define GPT2_CLK_SHIFT 12 #define GPT_CLK_MASK 0x1 -#define AUX_CLK_PLL3_MASK 0 -#define AUX_CLK_PLL1_MASK 1 +#define AUX_CLK_PLL3_VAL 0 +#define AUX_CLK_PLL1_VAL 1 -#define PERIP1_CLK_ENB ((unsigned int *)(MISC_BASE + 0x02C)) +#define PERIP1_CLK_ENB (MISC_BASE + 0x02C) /* PERIP1_CLK_ENB register masks */ #define UART_CLK_ENB 3 #define SSP_CLK_ENB 5 @@ -85,34 +85,35 @@ #define USBH_CLK_ENB 25 #define C3_CLK_ENB 31 -#define SOC_CORE_ID ((unsigned int *)(MISC_BASE + 0x030)) -#define RAS_CLK_ENB ((unsigned int *)(MISC_BASE + 0x034)) -#define PERIP1_SOF_RST ((unsigned int *)(MISC_BASE + 0x038)) +#define SOC_CORE_ID (MISC_BASE + 0x030) +#define RAS_CLK_ENB (MISC_BASE + 0x034) +#define PERIP1_SOF_RST (MISC_BASE + 0x038) /* PERIP1_SOF_RST register masks */ #define JPEG_SOF_RST 8 -#define SOC_USER_ID ((unsigned int *)(MISC_BASE + 0x03C)) -#define RAS_SOF_RST ((unsigned int *)(MISC_BASE + 0x040)) -#define PRSC1_CLK_CFG ((unsigned int *)(MISC_BASE + 0x044)) -#define PRSC2_CLK_CFG ((unsigned int *)(MISC_BASE + 0x048)) -#define PRSC3_CLK_CFG ((unsigned int *)(MISC_BASE + 0x04C)) +#define SOC_USER_ID (MISC_BASE + 0x03C) +#define RAS_SOF_RST (MISC_BASE + 0x040) +#define PRSC1_CLK_CFG (MISC_BASE + 0x044) +#define PRSC2_CLK_CFG (MISC_BASE + 0x048) +#define PRSC3_CLK_CFG (MISC_BASE + 0x04C) /* gpt synthesizer register masks */ #define GPT_MSCALE_SHIFT 0 #define GPT_MSCALE_MASK 0xFFF #define GPT_NSCALE_SHIFT 12 #define GPT_NSCALE_MASK 0xF -#define AMEM_CLK_CFG ((unsigned int *)(MISC_BASE + 0x050)) -#define EXPI_CLK_CFG ((unsigned int *)(MISC_BASE + 0x054)) -#define CLCD_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x05C)) -#define FIRDA_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x060)) -#define UART_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x064)) -#define GMAC_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x068)) -#define RAS1_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x06C)) -#define RAS2_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x070)) -#define RAS3_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x074)) -#define RAS4_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x078)) +#define AMEM_CLK_CFG (MISC_BASE + 0x050) +#define EXPI_CLK_CFG (MISC_BASE + 0x054) +#define CLCD_CLK_SYNT (MISC_BASE + 0x05C) +#define FIRDA_CLK_SYNT (MISC_BASE + 0x060) +#define UART_CLK_SYNT (MISC_BASE + 0x064) +#define GMAC_CLK_SYNT (MISC_BASE + 0x068) +#define RAS1_CLK_SYNT (MISC_BASE + 0x06C) +#define RAS2_CLK_SYNT (MISC_BASE + 0x070) +#define RAS3_CLK_SYNT (MISC_BASE + 0x074) +#define RAS4_CLK_SYNT (MISC_BASE + 0x078) /* aux clk synthesiser register masks for irda to ras4 */ +#define AUX_SYNT_ENB 31 #define AUX_EQ_SEL_SHIFT 30 #define AUX_EQ_SEL_MASK 1 #define AUX_EQ1_SEL 0 @@ -122,42 +123,42 @@ #define AUX_YSCALE_SHIFT 0 #define AUX_YSCALE_MASK 0xFFF -#define ICM1_ARB_CFG ((unsigned int *)(MISC_BASE + 0x07C)) -#define ICM2_ARB_CFG ((unsigned int *)(MISC_BASE + 0x080)) -#define ICM3_ARB_CFG ((unsigned int *)(MISC_BASE + 0x084)) -#define ICM4_ARB_CFG ((unsigned int *)(MISC_BASE + 0x088)) -#define ICM5_ARB_CFG ((unsigned int *)(MISC_BASE + 0x08C)) -#define ICM6_ARB_CFG ((unsigned int *)(MISC_BASE + 0x090)) -#define ICM7_ARB_CFG ((unsigned int *)(MISC_BASE + 0x094)) -#define ICM8_ARB_CFG ((unsigned int *)(MISC_BASE + 0x098)) -#define ICM9_ARB_CFG ((unsigned int *)(MISC_BASE + 0x09C)) -#define DMA_CHN_CFG ((unsigned int *)(MISC_BASE + 0x0A0)) -#define USB2_PHY_CFG ((unsigned int *)(MISC_BASE + 0x0A4)) -#define GMAC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0A8)) -#define EXPI_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0AC)) -#define PRC1_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C0)) -#define PRC2_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C4)) -#define PRC3_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C8)) -#define PRC4_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0CC)) -#define PRC1_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D0)) -#define PRC2_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D4)) -#define PRC3_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D8)) -#define PRC4_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0DC)) -#define PWRDOWN_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0E0)) -#define COMPSSTL_1V8_CFG ((unsigned int *)(MISC_BASE + 0x0E4)) -#define COMPSSTL_2V5_CFG ((unsigned int *)(MISC_BASE + 0x0E8)) -#define COMPCOR_3V3_CFG ((unsigned int *)(MISC_BASE + 0x0EC)) -#define SSTLPAD_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F0)) -#define BIST1_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F4)) -#define BIST2_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F8)) -#define BIST3_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0FC)) -#define BIST4_CFG_CTR ((unsigned int *)(MISC_BASE + 0x100)) -#define BIST5_CFG_CTR ((unsigned int *)(MISC_BASE + 0x104)) -#define BIST1_STS_RES ((unsigned int *)(MISC_BASE + 0x108)) -#define BIST2_STS_RES ((unsigned int *)(MISC_BASE + 0x10C)) -#define BIST3_STS_RES ((unsigned int *)(MISC_BASE + 0x110)) -#define BIST4_STS_RES ((unsigned int *)(MISC_BASE + 0x114)) -#define BIST5_STS_RES ((unsigned int *)(MISC_BASE + 0x118)) -#define SYSERR_CFG_CTR ((unsigned int *)(MISC_BASE + 0x11C)) +#define ICM1_ARB_CFG (MISC_BASE + 0x07C) +#define ICM2_ARB_CFG (MISC_BASE + 0x080) +#define ICM3_ARB_CFG (MISC_BASE + 0x084) +#define ICM4_ARB_CFG (MISC_BASE + 0x088) +#define ICM5_ARB_CFG (MISC_BASE + 0x08C) +#define ICM6_ARB_CFG (MISC_BASE + 0x090) +#define ICM7_ARB_CFG (MISC_BASE + 0x094) +#define ICM8_ARB_CFG (MISC_BASE + 0x098) +#define ICM9_ARB_CFG (MISC_BASE + 0x09C) +#define DMA_CHN_CFG (MISC_BASE + 0x0A0) +#define USB2_PHY_CFG (MISC_BASE + 0x0A4) +#define GMAC_CFG_CTR (MISC_BASE + 0x0A8) +#define EXPI_CFG_CTR (MISC_BASE + 0x0AC) +#define PRC1_LOCK_CTR (MISC_BASE + 0x0C0) +#define PRC2_LOCK_CTR (MISC_BASE + 0x0C4) +#define PRC3_LOCK_CTR (MISC_BASE + 0x0C8) +#define PRC4_LOCK_CTR (MISC_BASE + 0x0CC) +#define PRC1_IRQ_CTR (MISC_BASE + 0x0D0) +#define PRC2_IRQ_CTR (MISC_BASE + 0x0D4) +#define PRC3_IRQ_CTR (MISC_BASE + 0x0D8) +#define PRC4_IRQ_CTR (MISC_BASE + 0x0DC) +#define PWRDOWN_CFG_CTR (MISC_BASE + 0x0E0) +#define COMPSSTL_1V8_CFG (MISC_BASE + 0x0E4) +#define COMPSSTL_2V5_CFG (MISC_BASE + 0x0E8) +#define COMPCOR_3V3_CFG (MISC_BASE + 0x0EC) +#define SSTLPAD_CFG_CTR (MISC_BASE + 0x0F0) +#define BIST1_CFG_CTR (MISC_BASE + 0x0F4) +#define BIST2_CFG_CTR (MISC_BASE + 0x0F8) +#define BIST3_CFG_CTR (MISC_BASE + 0x0FC) +#define BIST4_CFG_CTR (MISC_BASE + 0x100) +#define BIST5_CFG_CTR (MISC_BASE + 0x104) +#define BIST1_STS_RES (MISC_BASE + 0x108) +#define BIST2_STS_RES (MISC_BASE + 0x10C) +#define BIST3_STS_RES (MISC_BASE + 0x110) +#define BIST4_STS_RES (MISC_BASE + 0x114) +#define BIST5_STS_RES (MISC_BASE + 0x118) +#define SYSERR_CFG_CTR (MISC_BASE + 0x11C) #endif /* __MACH_MISC_REGS_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h index dcca8568a486..63fd98356919 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear.h +++ b/arch/arm/mach-spear3xx/include/mach/spear.h @@ -14,124 +14,61 @@ #ifndef __MACH_SPEAR3XX_H #define __MACH_SPEAR3XX_H -#include <mach/hardware.h> +#include <asm/memory.h> #include <mach/spear300.h> #include <mach/spear310.h> #include <mach/spear320.h> -#define SPEAR3XX_ML_SDRAM_BASE 0x00000000 -#define SPEAR3XX_ML_SDRAM_SIZE 0x40000000 +#define SPEAR3XX_ML_SDRAM_BASE UL(0x00000000) -#define SPEAR3XX_ICM9_BASE 0xC0000000 -#define SPEAR3XX_ICM9_SIZE 0x10000000 +#define SPEAR3XX_ICM9_BASE UL(0xC0000000) /* ICM1 - Low speed connection */ -#define SPEAR3XX_ICM1_2_BASE 0xD0000000 -#define SPEAR3XX_ICM1_2_SIZE 0x10000000 - -#define SPEAR3XX_ICM1_UART_BASE 0xD0000000 +#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000) +#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000) #define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE) -#define SPEAR3XX_ICM1_UART_SIZE 0x00080000 - -#define SPEAR3XX_ICM1_ADC_BASE 0xD0080000 -#define SPEAR3XX_ICM1_ADC_SIZE 0x00080000 - -#define SPEAR3XX_ICM1_SSP_BASE 0xD0100000 -#define SPEAR3XX_ICM1_SSP_SIZE 0x00080000 - -#define SPEAR3XX_ICM1_I2C_BASE 0xD0180000 -#define SPEAR3XX_ICM1_I2C_SIZE 0x00080000 - -#define SPEAR3XX_ICM1_JPEG_BASE 0xD0800000 -#define SPEAR3XX_ICM1_JPEG_SIZE 0x00800000 - -#define SPEAR3XX_ICM1_IRDA_BASE 0xD1000000 -#define SPEAR3XX_ICM1_IRDA_SIZE 0x00080000 - -#define SPEAR3XX_ICM1_SRAM_BASE 0xD2800000 -#define SPEAR3XX_ICM1_SRAM_SIZE 0x05800000 +#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000) +#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) +#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000) +#define SPEAR3XX_ICM1_JPEG_BASE UL(0xD0800000) +#define SPEAR3XX_ICM1_IRDA_BASE UL(0xD1000000) +#define SPEAR3XX_ICM1_SRAM_BASE UL(0xD2800000) /* ICM2 - Application Subsystem */ -#define SPEAR3XX_ICM2_HWACCEL0_BASE 0xD8800000 -#define SPEAR3XX_ICM2_HWACCEL0_SIZE 0x00800000 - -#define SPEAR3XX_ICM2_HWACCEL1_BASE 0xD9000000 -#define SPEAR3XX_ICM2_HWACCEL1_SIZE 0x00800000 +#define SPEAR3XX_ICM2_HWACCEL0_BASE UL(0xD8800000) +#define SPEAR3XX_ICM2_HWACCEL1_BASE UL(0xD9000000) /* ICM4 - High Speed Connection */ -#define SPEAR3XX_ICM4_BASE 0xE0000000 -#define SPEAR3XX_ICM4_SIZE 0x08000000 - -#define SPEAR3XX_ICM4_MII_BASE 0xE0800000 -#define SPEAR3XX_ICM4_MII_SIZE 0x00800000 - -#define SPEAR3XX_ICM4_USBD_FIFO_BASE 0xE1000000 -#define SPEAR3XX_ICM4_USBD_FIFO_SIZE 0x00100000 - -#define SPEAR3XX_ICM4_USBD_CSR_BASE 0xE1100000 -#define SPEAR3XX_ICM4_USBD_CSR_SIZE 0x00100000 - -#define SPEAR3XX_ICM4_USBD_PLDT_BASE 0xE1200000 -#define SPEAR3XX_ICM4_USBD_PLDT_SIZE 0x00100000 - -#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE 0xE1800000 -#define SPEAR3XX_ICM4_USB_EHCI0_1_SIZE 0x00100000 - -#define SPEAR3XX_ICM4_USB_OHCI0_BASE 0xE1900000 -#define SPEAR3XX_ICM4_USB_OHCI0_SIZE 0x00100000 - -#define SPEAR3XX_ICM4_USB_OHCI1_BASE 0xE2100000 -#define SPEAR3XX_ICM4_USB_OHCI1_SIZE 0x00100000 - -#define SPEAR3XX_ICM4_USB_ARB_BASE 0xE2800000 -#define SPEAR3XX_ICM4_USB_ARB_SIZE 0x00010000 +#define SPEAR3XX_ICM4_BASE UL(0xE0000000) +#define SPEAR3XX_ICM4_MII_BASE UL(0xE0800000) +#define SPEAR3XX_ICM4_USBD_FIFO_BASE UL(0xE1000000) +#define SPEAR3XX_ICM4_USBD_CSR_BASE UL(0xE1100000) +#define SPEAR3XX_ICM4_USBD_PLDT_BASE UL(0xE1200000) +#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE UL(0xE1800000) +#define SPEAR3XX_ICM4_USB_OHCI0_BASE UL(0xE1900000) +#define SPEAR3XX_ICM4_USB_OHCI1_BASE UL(0xE2100000) +#define SPEAR3XX_ICM4_USB_ARB_BASE UL(0xE2800000) /* ML1 - Multi Layer CPU Subsystem */ -#define SPEAR3XX_ICM3_ML1_2_BASE 0xF0000000 -#define SPEAR3XX_ICM3_ML1_2_SIZE 0x0F000000 - -#define SPEAR3XX_ML1_TMR_BASE 0xF0000000 -#define SPEAR3XX_ML1_TMR_SIZE 0x00100000 - -#define SPEAR3XX_ML1_VIC_BASE 0xF1100000 +#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000) +#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000) +#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000) #define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE) -#define SPEAR3XX_ML1_VIC_SIZE 0x00100000 /* ICM3 - Basic Subsystem */ -#define SPEAR3XX_ICM3_SMEM_BASE 0xF8000000 -#define SPEAR3XX_ICM3_SMEM_SIZE 0x04000000 - -#define SPEAR3XX_ICM3_SMI_CTRL_BASE 0xFC000000 -#define SPEAR3XX_ICM3_SMI_CTRL_SIZE 0x00200000 - -#define SPEAR3XX_ICM3_DMA_BASE 0xFC400000 -#define SPEAR3XX_ICM3_DMA_SIZE 0x00200000 - -#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE 0xFC600000 -#define SPEAR3XX_ICM3_SDRAM_CTRL_SIZE 0x00200000 - -#define SPEAR3XX_ICM3_TMR0_BASE 0xFC800000 -#define SPEAR3XX_ICM3_TMR0_SIZE 0x00080000 - -#define SPEAR3XX_ICM3_WDT_BASE 0xFC880000 -#define SPEAR3XX_ICM3_WDT_SIZE 0x00080000 - -#define SPEAR3XX_ICM3_RTC_BASE 0xFC900000 -#define SPEAR3XX_ICM3_RTC_SIZE 0x00080000 - -#define SPEAR3XX_ICM3_GPIO_BASE 0xFC980000 -#define SPEAR3XX_ICM3_GPIO_SIZE 0x00080000 - -#define SPEAR3XX_ICM3_SYS_CTRL_BASE 0xFCA00000 +#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000) +#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) +#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000) +#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000) +#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000) +#define SPEAR3XX_ICM3_WDT_BASE UL(0xFC880000) +#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000) +#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000) +#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) #define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE) -#define SPEAR3XX_ICM3_SYS_CTRL_SIZE 0x00080000 - -#define SPEAR3XX_ICM3_MISC_REG_BASE 0xFCA80000 +#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000) #define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE) -#define SPEAR3XX_ICM3_MISC_REG_SIZE 0x00080000 - -#define SPEAR3XX_ICM3_TMR1_BASE 0xFCB00000 -#define SPEAR3XX_ICM3_TMR1_SIZE 0x00080000 +#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000) /* Debug uart for linux, will be used for debug and uncompress messages */ #define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h index ccaa76522ee2..c723515f8853 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear300.h +++ b/arch/arm/mach-spear3xx/include/mach/spear300.h @@ -17,11 +17,9 @@ #define __MACH_SPEAR300_H /* Base address of various IPs */ -#define SPEAR300_TELECOM_BASE 0x50000000 -#define SPEAR300_TELECOM_SIZE 0x10000000 +#define SPEAR300_TELECOM_BASE UL(0x50000000) /* Interrupt registers offsets and masks */ -#define SPEAR300_TELECOM_REG_SIZE 0x00010000 #define INT_ENB_MASK_REG 0x54 #define INT_STS_MASK_REG 0x58 #define IT_PERS_S_IRQ_MASK (1 << 0) @@ -36,47 +34,20 @@ #define SHIRQ_RAS1_MASK 0x1FF -#define SPEAR300_CLCD_BASE 0x60000000 -#define SPEAR300_CLCD_SIZE 0x10000000 - -#define SPEAR300_SDIO_BASE 0x70000000 -#define SPEAR300_SDIO_SIZE 0x10000000 - -#define SPEAR300_NAND_0_BASE 0x80000000 -#define SPEAR300_NAND_0_SIZE 0x04000000 - -#define SPEAR300_NAND_1_BASE 0x84000000 -#define SPEAR300_NAND_1_SIZE 0x04000000 - -#define SPEAR300_NAND_2_BASE 0x88000000 -#define SPEAR300_NAND_2_SIZE 0x04000000 - -#define SPEAR300_NAND_3_BASE 0x8c000000 -#define SPEAR300_NAND_3_SIZE 0x04000000 - -#define SPEAR300_NOR_0_BASE 0x90000000 -#define SPEAR300_NOR_0_SIZE 0x01000000 - -#define SPEAR300_NOR_1_BASE 0x91000000 -#define SPEAR300_NOR_1_SIZE 0x01000000 - -#define SPEAR300_NOR_2_BASE 0x92000000 -#define SPEAR300_NOR_2_SIZE 0x01000000 - -#define SPEAR300_NOR_3_BASE 0x93000000 -#define SPEAR300_NOR_3_SIZE 0x01000000 - -#define SPEAR300_FSMC_BASE 0x94000000 -#define SPEAR300_FSMC_SIZE 0x05000000 - -#define SPEAR300_SOC_CONFIG_BASE 0x99000000 -#define SPEAR300_SOC_CONFIG_SIZE 0x00000008 - -#define SPEAR300_KEYBOARD_BASE 0xA0000000 -#define SPEAR300_KEYBOARD_SIZE 0x09000000 - -#define SPEAR300_GPIO_BASE 0xA9000000 -#define SPEAR300_GPIO_SIZE 0x07000000 +#define SPEAR300_CLCD_BASE UL(0x60000000) +#define SPEAR300_SDHCI_BASE UL(0x70000000) +#define SPEAR300_NAND_0_BASE UL(0x80000000) +#define SPEAR300_NAND_1_BASE UL(0x84000000) +#define SPEAR300_NAND_2_BASE UL(0x88000000) +#define SPEAR300_NAND_3_BASE UL(0x8c000000) +#define SPEAR300_NOR_0_BASE UL(0x90000000) +#define SPEAR300_NOR_1_BASE UL(0x91000000) +#define SPEAR300_NOR_2_BASE UL(0x92000000) +#define SPEAR300_NOR_3_BASE UL(0x93000000) +#define SPEAR300_FSMC_BASE UL(0x94000000) +#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000) +#define SPEAR300_KEYBOARD_BASE UL(0xA0000000) +#define SPEAR300_GPIO_BASE UL(0xA9000000) #endif /* __MACH_SPEAR300_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h index b27bb8af3309..1e853479b8cd 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear310.h +++ b/arch/arm/mach-spear3xx/include/mach/spear310.h @@ -16,30 +16,18 @@ #ifndef __MACH_SPEAR310_H #define __MACH_SPEAR310_H -#define SPEAR310_NAND_BASE 0x40000000 -#define SPEAR310_NAND_SIZE 0x04000000 +#define SPEAR310_NAND_BASE UL(0x40000000) +#define SPEAR310_FSMC_BASE UL(0x44000000) +#define SPEAR310_UART1_BASE UL(0xB2000000) +#define SPEAR310_UART2_BASE UL(0xB2080000) +#define SPEAR310_UART3_BASE UL(0xB2100000) +#define SPEAR310_UART4_BASE UL(0xB2180000) +#define SPEAR310_UART5_BASE UL(0xB2200000) +#define SPEAR310_HDLC_BASE UL(0xB2800000) +#define SPEAR310_RS485_0_BASE UL(0xB3000000) +#define SPEAR310_RS485_1_BASE UL(0xB3800000) +#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000) -#define SPEAR310_FSMC_BASE 0x44000000 -#define SPEAR310_FSMC_SIZE 0x01000000 - -#define SPEAR310_UART1_BASE 0xB2000000 -#define SPEAR310_UART2_BASE 0xB2080000 -#define SPEAR310_UART3_BASE 0xB2100000 -#define SPEAR310_UART4_BASE 0xB2180000 -#define SPEAR310_UART5_BASE 0xB2200000 -#define SPEAR310_UART_SIZE 0x00080000 - -#define SPEAR310_HDLC_BASE 0xB2800000 -#define SPEAR310_HDLC_SIZE 0x00800000 - -#define SPEAR310_RS485_0_BASE 0xB3000000 -#define SPEAR310_RS485_0_SIZE 0x00800000 - -#define SPEAR310_RS485_1_BASE 0xB3800000 -#define SPEAR310_RS485_1_SIZE 0x00800000 - -#define SPEAR310_SOC_CONFIG_BASE 0xB4000000 -#define SPEAR310_SOC_CONFIG_SIZE 0x00000070 /* Interrupt registers offsets and masks */ #define INT_STS_MASK_REG 0x04 #define SMII0_IRQ_MASK (1 << 0) diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h index 53677e464d4b..940f0d85d959 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear320.h +++ b/arch/arm/mach-spear3xx/include/mach/spear320.h @@ -16,54 +16,25 @@ #ifndef __MACH_SPEAR320_H #define __MACH_SPEAR320_H -#define SPEAR320_EMI_CTRL_BASE 0x40000000 -#define SPEAR320_EMI_CTRL_SIZE 0x08000000 +#define SPEAR320_EMI_CTRL_BASE UL(0x40000000) +#define SPEAR320_FSMC_BASE UL(0x4C000000) +#define SPEAR320_NAND_BASE UL(0x50000000) +#define SPEAR320_I2S_BASE UL(0x60000000) +#define SPEAR320_SDHCI_BASE UL(0x70000000) +#define SPEAR320_CLCD_BASE UL(0x90000000) +#define SPEAR320_PAR_PORT_BASE UL(0xA0000000) +#define SPEAR320_CAN0_BASE UL(0xA1000000) +#define SPEAR320_CAN1_BASE UL(0xA2000000) +#define SPEAR320_UART1_BASE UL(0xA3000000) +#define SPEAR320_UART2_BASE UL(0xA4000000) +#define SPEAR320_SSP0_BASE UL(0xA5000000) +#define SPEAR320_SSP1_BASE UL(0xA6000000) +#define SPEAR320_I2C_BASE UL(0xA7000000) +#define SPEAR320_PWM_BASE UL(0xA8000000) +#define SPEAR320_SMII0_BASE UL(0xAA000000) +#define SPEAR320_SMII1_BASE UL(0xAB000000) +#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) -#define SPEAR320_FSMC_BASE 0x4C000000 -#define SPEAR320_FSMC_SIZE 0x01000000 - -#define SPEAR320_I2S_BASE 0x60000000 -#define SPEAR320_I2S_SIZE 0x10000000 - -#define SPEAR320_SDIO_BASE 0x70000000 -#define SPEAR320_SDIO_SIZE 0x10000000 - -#define SPEAR320_CLCD_BASE 0x90000000 -#define SPEAR320_CLCD_SIZE 0x10000000 - -#define SPEAR320_PAR_PORT_BASE 0xA0000000 -#define SPEAR320_PAR_PORT_SIZE 0x01000000 - -#define SPEAR320_CAN0_BASE 0xA1000000 -#define SPEAR320_CAN0_SIZE 0x01000000 - -#define SPEAR320_CAN1_BASE 0xA2000000 -#define SPEAR320_CAN1_SIZE 0x01000000 - -#define SPEAR320_UART1_BASE 0xA3000000 -#define SPEAR320_UART2_BASE 0xA4000000 -#define SPEAR320_UART_SIZE 0x01000000 - -#define SPEAR320_SSP0_BASE 0xA5000000 -#define SPEAR320_SSP0_SIZE 0x01000000 - -#define SPEAR320_SSP1_BASE 0xA6000000 -#define SPEAR320_SSP1_SIZE 0x01000000 - -#define SPEAR320_I2C_BASE 0xA7000000 -#define SPEAR320_I2C_SIZE 0x01000000 - -#define SPEAR320_PWM_BASE 0xA8000000 -#define SPEAR320_PWM_SIZE 0x01000000 - -#define SPEAR320_SMII0_BASE 0xAA000000 -#define SPEAR320_SMII0_SIZE 0x01000000 - -#define SPEAR320_SMII1_BASE 0xAB000000 -#define SPEAR320_SMII1_SIZE 0x01000000 - -#define SPEAR320_SOC_CONFIG_BASE 0xB3000000 -#define SPEAR320_SOC_CONFIG_SIZE 0x00000070 /* Interrupt registers offsets and masks */ #define INT_STS_MASK_REG 0x04 #define INT_CLR_MASK_REG 0x04 @@ -74,7 +45,7 @@ #define EMI_IRQ_MASK (1 << 7) #define CLCD_IRQ_MASK (1 << 8) #define SPP_IRQ_MASK (1 << 9) -#define SDIO_IRQ_MASK (1 << 10) +#define SDHCI_IRQ_MASK (1 << 10) #define CAN_U_IRQ_MASK (1 << 11) #define CAN_L_IRQ_MASK (1 << 12) #define UART1_IRQ_MASK (1 << 13) diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c index 5aa2d54ebfaa..2697e65adf86 100644 --- a/arch/arm/mach-spear3xx/spear300.c +++ b/arch/arm/mach-spear3xx/spear300.c @@ -15,9 +15,9 @@ #include <linux/amba/pl061.h> #include <linux/ptrace.h> #include <asm/irq.h> -#include <mach/generic.h> -#include <mach/spear.h> #include <plat/shirq.h> +#include <mach/generic.h> +#include <mach/hardware.h> /* pad multiplexing support */ /* muxing registers */ @@ -310,7 +310,7 @@ struct pmx_dev pmx_telecom_boot_pins = { .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_telecom_sdio_4bit_modes[] = { +struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = { { .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | @@ -323,14 +323,14 @@ struct pmx_dev_mode pmx_telecom_sdio_4bit_modes[] = { }, }; -struct pmx_dev pmx_telecom_sdio_4bit = { - .name = "telecom_sdio_4bit", - .modes = pmx_telecom_sdio_4bit_modes, - .mode_count = ARRAY_SIZE(pmx_telecom_sdio_4bit_modes), +struct pmx_dev pmx_telecom_sdhci_4bit = { + .name = "telecom_sdhci_4bit", + .modes = pmx_telecom_sdhci_4bit_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_telecom_sdio_8bit_modes[] = { +struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = { { .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | @@ -342,10 +342,10 @@ struct pmx_dev_mode pmx_telecom_sdio_8bit_modes[] = { }, }; -struct pmx_dev pmx_telecom_sdio_8bit = { - .name = "telecom_sdio_8bit", - .modes = pmx_telecom_sdio_8bit_modes, - .mode_count = ARRAY_SIZE(pmx_telecom_sdio_8bit_modes), +struct pmx_dev pmx_telecom_sdhci_8bit = { + .name = "telecom_sdhci_8bit", + .modes = pmx_telecom_sdhci_8bit_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes), .enb_on_reset = 1, }; @@ -370,26 +370,6 @@ struct pmx_driver pmx_driver = { .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, }; -/* Add spear300 specific devices here */ -/* arm gpio1 device registration */ -static struct pl061_platform_data gpio1_plat_data = { - .gpio_base = 8, - .irq_base = SPEAR_GPIO1_INT_BASE, -}; - -struct amba_device gpio1_device = { - .dev = { - .init_name = "gpio1", - .platform_data = &gpio1_plat_data, - }, - .res = { - .start = SPEAR300_GPIO_BASE, - .end = SPEAR300_GPIO_BASE + SPEAR300_GPIO_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - .irq = {VIRQ_GPIO1, NO_IRQ}, -}; - /* spear3xx shared irq */ struct shirq_dev_config shirq_ras1_config[] = { { @@ -443,6 +423,26 @@ struct spear_shirq shirq_ras1 = { }, }; +/* Add spear300 specific devices here */ +/* arm gpio1 device registration */ +static struct pl061_platform_data gpio1_plat_data = { + .gpio_base = 8, + .irq_base = SPEAR_GPIO1_INT_BASE, +}; + +struct amba_device gpio1_device = { + .dev = { + .init_name = "gpio1", + .platform_data = &gpio1_plat_data, + }, + .res = { + .start = SPEAR300_GPIO_BASE, + .end = SPEAR300_GPIO_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {VIRQ_GPIO1, NO_IRQ}, +}; + /* spear300 routines */ void __init spear300_init(void) { @@ -452,17 +452,21 @@ void __init spear300_init(void) spear3xx_init(); /* shared irq registration */ - shirq_ras1.regs.base = - ioremap(SPEAR300_TELECOM_BASE, SPEAR300_TELECOM_REG_SIZE); + shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K); if (shirq_ras1.regs.base) { ret = spear_shirq_register(&shirq_ras1); if (ret) printk(KERN_ERR "Error registering Shared IRQ\n"); } -} -void spear300_pmx_init(void) -{ - spear_pmx_init(&pmx_driver, SPEAR300_SOC_CONFIG_BASE, - SPEAR300_SOC_CONFIG_SIZE); + /* pmx initialization */ + pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K); + if (pmx_driver.base) { + ret = pmx_register(&pmx_driver); + if (ret) + printk(KERN_ERR "padmux: registeration failed. err no" + ": %d\n", ret); + /* Free Mapping, device selection already done */ + iounmap(pmx_driver.base); + } } diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c index bb21db152a23..42d2253ef540 100644 --- a/arch/arm/mach-spear3xx/spear300_evb.c +++ b/arch/arm/mach-spear3xx/spear300_evb.c @@ -14,7 +14,7 @@ #include <asm/mach/arch.h> #include <asm/mach-types.h> #include <mach/generic.h> -#include <mach/spear.h> +#include <mach/hardware.h> /* padmux devices to enable */ static struct pmx_dev *pmx_devs[] = { @@ -28,7 +28,7 @@ static struct pmx_dev *pmx_devs[] = { /* spear300 specific devices */ &pmx_fsmc_2_chips, &pmx_clcd, - &pmx_telecom_sdio_4bit, + &pmx_telecom_sdhci_4bit, &pmx_gpio1, }; @@ -51,14 +51,13 @@ static void __init spear300_evb_init(void) { unsigned int i; - /* call spear300 machine init function */ - spear300_init(); - - /* padmux initialization */ + /* padmux initialization, must be done before spear300_init */ pmx_driver.mode = &photo_frame_mode; pmx_driver.devs = pmx_devs; pmx_driver.devs_count = ARRAY_SIZE(pmx_devs); - spear300_pmx_init(); + + /* call spear300 machine init function */ + spear300_init(); /* Add Platform Devices */ platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); @@ -72,6 +71,6 @@ MACHINE_START(SPEAR300, "ST-SPEAR300-EVB") .boot_params = 0x00000100, .map_io = spear3xx_map_io, .init_irq = spear3xx_init_irq, - .timer = &spear_sys_timer, + .timer = &spear3xx_timer, .init_machine = spear300_evb_init, MACHINE_END diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c index 53b41b52d7ee..5c0a67b60c2a 100644 --- a/arch/arm/mach-spear3xx/spear310.c +++ b/arch/arm/mach-spear3xx/spear310.c @@ -13,9 +13,9 @@ #include <linux/ptrace.h> #include <asm/irq.h> -#include <mach/generic.h> -#include <mach/spear.h> #include <plat/shirq.h> +#include <mach/generic.h> +#include <mach/hardware.h> /* pad multiplexing support */ /* muxing registers */ @@ -139,8 +139,6 @@ struct pmx_driver pmx_driver = { .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, }; -/* Add spear310 specific devices here */ - /* spear3xx shared irq */ struct shirq_dev_config shirq_ras1_config[] = { { @@ -257,6 +255,8 @@ struct spear_shirq shirq_intrcomm_ras = { }, }; +/* Add spear310 specific devices here */ + /* spear310 routines */ void __init spear310_init(void) { @@ -267,7 +267,7 @@ void __init spear310_init(void) spear3xx_init(); /* shared irq registration */ - base = ioremap(SPEAR310_SOC_CONFIG_BASE, SPEAR310_SOC_CONFIG_SIZE); + base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K); if (base) { /* shirq 1 */ shirq_ras1.regs.base = base; @@ -293,10 +293,11 @@ void __init spear310_init(void) if (ret) printk(KERN_ERR "Error registering Shared IRQ 4\n"); } -} -void spear310_pmx_init(void) -{ - spear_pmx_init(&pmx_driver, SPEAR310_SOC_CONFIG_BASE, - SPEAR310_SOC_CONFIG_SIZE); + /* pmx initialization */ + pmx_driver.base = base; + ret = pmx_register(&pmx_driver); + if (ret) + printk(KERN_ERR "padmux: registeration failed. err no: %d\n", + ret); } diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c index 7facf6643199..2d7f333bd67b 100644 --- a/arch/arm/mach-spear3xx/spear310_evb.c +++ b/arch/arm/mach-spear3xx/spear310_evb.c @@ -14,7 +14,7 @@ #include <asm/mach/arch.h> #include <asm/mach-types.h> #include <mach/generic.h> -#include <mach/spear.h> +#include <mach/hardware.h> /* padmux devices to enable */ static struct pmx_dev *pmx_devs[] = { @@ -58,14 +58,13 @@ static void __init spear310_evb_init(void) { unsigned int i; - /* call spear310 machine init function */ - spear310_init(); - - /* padmux initialization */ + /* padmux initialization, must be done before spear310_init */ pmx_driver.mode = NULL; pmx_driver.devs = pmx_devs; pmx_driver.devs_count = ARRAY_SIZE(pmx_devs); - spear310_pmx_init(); + + /* call spear310 machine init function */ + spear310_init(); /* Add Platform Devices */ platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); @@ -79,6 +78,6 @@ MACHINE_START(SPEAR310, "ST-SPEAR310-EVB") .boot_params = 0x00000100, .map_io = spear3xx_map_io, .init_irq = spear3xx_init_irq, - .timer = &spear_sys_timer, + .timer = &spear3xx_timer, .init_machine = spear310_evb_init, MACHINE_END diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c index 88b465284c36..741c1f414cbd 100644 --- a/arch/arm/mach-spear3xx/spear320.c +++ b/arch/arm/mach-spear3xx/spear320.c @@ -13,9 +13,9 @@ #include <linux/ptrace.h> #include <asm/irq.h> -#include <mach/generic.h> -#include <mach/spear.h> #include <plat/shirq.h> +#include <mach/generic.h> +#include <mach/hardware.h> /* pad multiplexing support */ /* muxing registers */ @@ -110,7 +110,7 @@ struct pmx_dev pmx_spp = { .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_sdio_modes[] = { +struct pmx_dev_mode pmx_sdhci_modes[] = { { .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | SMALL_PRINTERS_MODE, @@ -118,10 +118,10 @@ struct pmx_dev_mode pmx_sdio_modes[] = { }, }; -struct pmx_dev pmx_sdio = { - .name = "sdio", - .modes = pmx_sdio_modes, - .mode_count = ARRAY_SIZE(pmx_sdio_modes), +struct pmx_dev pmx_sdhci = { + .name = "sdhci", + .modes = pmx_sdhci_modes, + .mode_count = ARRAY_SIZE(pmx_sdhci_modes), .enb_on_reset = 1, }; @@ -215,17 +215,17 @@ struct pmx_dev pmx_can = { .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_sdio_led_modes[] = { +struct pmx_dev_mode pmx_sdhci_led_modes[] = { { .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, .mask = PMX_SSP_CS_MASK, }, }; -struct pmx_dev pmx_sdio_led = { - .name = "sdio_led", - .modes = pmx_sdio_led_modes, - .mode_count = ARRAY_SIZE(pmx_sdio_led_modes), +struct pmx_dev pmx_sdhci_led = { + .name = "sdhci_led", + .modes = pmx_sdhci_led_modes, + .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes), .enb_on_reset = 1, }; @@ -384,8 +384,6 @@ struct pmx_driver pmx_driver = { .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, }; -/* Add spear320 specific devices here */ - /* spear3xx shared irq */ struct shirq_dev_config shirq_ras1_config[] = { { @@ -510,6 +508,8 @@ struct spear_shirq shirq_intrcomm_ras = { }, }; +/* Add spear320 specific devices here */ + /* spear320 routines */ void __init spear320_init(void) { @@ -520,7 +520,7 @@ void __init spear320_init(void) spear3xx_init(); /* shared irq registration */ - base = ioremap(SPEAR320_SOC_CONFIG_BASE, SPEAR320_SOC_CONFIG_SIZE); + base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K); if (base) { /* shirq 1 */ shirq_ras1.regs.base = base; @@ -540,10 +540,11 @@ void __init spear320_init(void) if (ret) printk(KERN_ERR "Error registering Shared IRQ 4\n"); } -} -void spear320_pmx_init(void) -{ - spear_pmx_init(&pmx_driver, SPEAR320_SOC_CONFIG_BASE, - SPEAR320_SOC_CONFIG_SIZE); + /* pmx initialization */ + pmx_driver.base = base; + ret = pmx_register(&pmx_driver); + if (ret) + printk(KERN_ERR "padmux: registeration failed. err no: %d\n", + ret); } diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c index 62ac685a4135..8213e4b66c14 100644 --- a/arch/arm/mach-spear3xx/spear320_evb.c +++ b/arch/arm/mach-spear3xx/spear320_evb.c @@ -14,7 +14,7 @@ #include <asm/mach/arch.h> #include <asm/mach-types.h> #include <mach/generic.h> -#include <mach/spear.h> +#include <mach/hardware.h> /* padmux devices to enable */ static struct pmx_dev *pmx_devs[] = { @@ -26,7 +26,7 @@ static struct pmx_dev *pmx_devs[] = { /* spear320 specific devices */ &pmx_fsmc, - &pmx_sdio, + &pmx_sdhci, &pmx_i2s, &pmx_uart1, &pmx_uart2, @@ -55,14 +55,13 @@ static void __init spear320_evb_init(void) { unsigned int i; - /* call spear320 machine init function */ - spear320_init(); - - /* padmux initialization */ + /* padmux initialization, must be done before spear320_init */ pmx_driver.mode = &auto_net_mii_mode; pmx_driver.devs = pmx_devs; pmx_driver.devs_count = ARRAY_SIZE(pmx_devs); - spear320_pmx_init(); + + /* call spear320 machine init function */ + spear320_init(); /* Add Platform Devices */ platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); @@ -76,6 +75,6 @@ MACHINE_START(SPEAR320, "ST-SPEAR320-EVB") .boot_params = 0x00000100, .map_io = spear3xx_map_io, .init_irq = spear3xx_init_irq, - .timer = &spear_sys_timer, + .timer = &spear3xx_timer, .init_machine = spear320_evb_init, MACHINE_END diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c index 52f553c8c46d..d3ba8ca1bc59 100644 --- a/arch/arm/mach-spear3xx/spear3xx.c +++ b/arch/arm/mach-spear3xx/spear3xx.c @@ -19,7 +19,7 @@ #include <asm/irq.h> #include <asm/mach/arch.h> #include <mach/generic.h> -#include <mach/spear.h> +#include <mach/hardware.h> /* Add spear3xx machines common devices here */ /* gpio device registration */ @@ -35,7 +35,7 @@ struct amba_device gpio_device = { }, .res = { .start = SPEAR3XX_ICM3_GPIO_BASE, - .end = SPEAR3XX_ICM3_GPIO_BASE + SPEAR3XX_ICM3_GPIO_SIZE - 1, + .end = SPEAR3XX_ICM3_GPIO_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, .irq = {IRQ_BASIC_GPIO, NO_IRQ}, @@ -48,7 +48,7 @@ struct amba_device uart_device = { }, .res = { .start = SPEAR3XX_ICM1_UART_BASE, - .end = SPEAR3XX_ICM1_UART_BASE + SPEAR3XX_ICM1_UART_SIZE - 1, + .end = SPEAR3XX_ICM1_UART_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, .irq = {IRQ_UART, NO_IRQ}, @@ -71,22 +71,22 @@ struct map_desc spear3xx_io_desc[] __initdata = { { .virtual = VA_SPEAR3XX_ICM1_UART_BASE, .pfn = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE), - .length = SPEAR3XX_ICM1_UART_SIZE, + .length = SZ_4K, .type = MT_DEVICE }, { .virtual = VA_SPEAR3XX_ML1_VIC_BASE, .pfn = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE), - .length = SPEAR3XX_ML1_VIC_SIZE, + .length = SZ_4K, .type = MT_DEVICE }, { .virtual = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE, .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE), - .length = SPEAR3XX_ICM3_SYS_CTRL_SIZE, + .length = SZ_4K, .type = MT_DEVICE }, { .virtual = VA_SPEAR3XX_ICM3_MISC_REG_BASE, .pfn = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE), - .length = SPEAR3XX_ICM3_MISC_REG_SIZE, + .length = SZ_4K, .type = MT_DEVICE }, }; @@ -523,26 +523,35 @@ struct pmx_dev pmx_plgpio_45_46_49_50 = { .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes), .enb_on_reset = 1, }; +#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */ -#endif - -/* spear padmux initialization function */ -void spear_pmx_init(struct pmx_driver *pmx_driver, uint base, uint size) +static void __init spear3xx_timer_init(void) { - int ret = 0; + char pclk_name[] = "pll3_48m_clk"; + struct clk *gpt_clk, *pclk; + + /* get the system timer clock */ + gpt_clk = clk_get_sys("gpt0", NULL); + if (IS_ERR(gpt_clk)) { + pr_err("%s:couldn't get clk for gpt\n", __func__); + BUG(); + } - /* pad mux initialization */ - pmx_driver->base = ioremap(base, size); - if (!pmx_driver->base) { - ret = -ENOMEM; - goto pmx_fail; + /* get the suitable parent clock for timer*/ + pclk = clk_get(NULL, pclk_name); + if (IS_ERR(pclk)) { + pr_err("%s:couldn't get %s as parent for gpt\n", + __func__, pclk_name); + BUG(); } - ret = pmx_register(pmx_driver); - iounmap(pmx_driver->base); + clk_set_parent(gpt_clk, pclk); + clk_put(gpt_clk); + clk_put(pclk); -pmx_fail: - if (ret) - printk(KERN_ERR "padmux: registration failed. err no: %d\n", - ret); + spear_setup_timer(); } + +struct sys_timer spear3xx_timer = { + .init = spear3xx_timer_init, +}; diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c index 36ff056b7321..88b748b5be80 100644 --- a/arch/arm/mach-spear6xx/clock.c +++ b/arch/arm/mach-spear6xx/clock.c @@ -13,8 +13,8 @@ #include <linux/init.h> #include <linux/kernel.h> -#include <mach/misc_regs.h> #include <plat/clock.h> +#include <mach/misc_regs.h> /* root clks */ /* 32 KHz oscillator clock */ @@ -39,18 +39,43 @@ static struct clk rtc_clk = { }; /* clock derived from 30 MHz osc clk */ +/* pll masks structure */ +static struct pll_clk_masks pll1_masks = { + .mode_mask = PLL_MODE_MASK, + .mode_shift = PLL_MODE_SHIFT, + .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK, + .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT, + .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK, + .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT, + .div_p_mask = PLL_DIV_P_MASK, + .div_p_shift = PLL_DIV_P_SHIFT, + .div_n_mask = PLL_DIV_N_MASK, + .div_n_shift = PLL_DIV_N_SHIFT, +}; + /* pll1 configuration structure */ static struct pll_clk_config pll1_config = { .mode_reg = PLL1_CTR, .cfg_reg = PLL1_FRQ, + .masks = &pll1_masks, +}; + +/* pll rate configuration table, in ascending order of rates */ +struct pll_rate_tbl pll_rtbl[] = { + {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */ + {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */ }; /* PLL1 clock */ static struct clk pll1_clk = { + .flags = ENABLED_ON_INIT, .pclk = &osc_30m_clk, .en_reg = PLL1_CTR, .en_reg_bit = PLL_ENABLE, - .recalc = &pll1_clk_recalc, + .calc_rate = &pll_calc_rate, + .recalc = &pll_clk_recalc, + .set_rate = &pll_clk_set_rate, + .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1}, .private_data = &pll1_config, }; @@ -76,31 +101,83 @@ static struct clk cpu_clk = { .recalc = &follow_parent, }; +/* ahb masks structure */ +static struct bus_clk_masks ahb_masks = { + .mask = PLL_HCLK_RATIO_MASK, + .shift = PLL_HCLK_RATIO_SHIFT, +}; + /* ahb configuration structure */ static struct bus_clk_config ahb_config = { .reg = CORE_CLK_CFG, - .mask = PLL_HCLK_RATIO_MASK, - .shift = PLL_HCLK_RATIO_SHIFT, + .masks = &ahb_masks, +}; + +/* ahb rate configuration table, in ascending order of rates */ +struct bus_rate_tbl bus_rtbl[] = { + {.div = 3}, /* == parent divided by 4 */ + {.div = 2}, /* == parent divided by 3 */ + {.div = 1}, /* == parent divided by 2 */ + {.div = 0}, /* == parent divided by 1 */ }; /* ahb clock */ static struct clk ahb_clk = { .flags = ALWAYS_ENABLED, .pclk = &pll1_clk, + .calc_rate = &bus_calc_rate, .recalc = &bus_clk_recalc, + .set_rate = &bus_clk_set_rate, + .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2}, .private_data = &ahb_config, }; +/* auxiliary synthesizers masks */ +static struct aux_clk_masks aux_masks = { + .eq_sel_mask = AUX_EQ_SEL_MASK, + .eq_sel_shift = AUX_EQ_SEL_SHIFT, + .eq1_mask = AUX_EQ1_SEL, + .eq2_mask = AUX_EQ2_SEL, + .xscale_sel_mask = AUX_XSCALE_MASK, + .xscale_sel_shift = AUX_XSCALE_SHIFT, + .yscale_sel_mask = AUX_YSCALE_MASK, + .yscale_sel_shift = AUX_YSCALE_SHIFT, +}; + +/* uart configurations */ +static struct aux_clk_config uart_synth_config = { + .synth_reg = UART_CLK_SYNT, + .masks = &aux_masks, +}; + +/* aux rate configuration table, in ascending order of rates */ +struct aux_rate_tbl aux_rtbl[] = { + /* For PLL1 = 332 MHz */ + {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */ + {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */ + {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */ +}; + +/* uart synth clock */ +static struct clk uart_synth_clk = { + .en_reg = UART_CLK_SYNT, + .en_reg_bit = AUX_SYNT_ENB, + .pclk = &pll1_clk, + .calc_rate = &aux_calc_rate, + .recalc = &aux_clk_recalc, + .set_rate = &aux_clk_set_rate, + .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2}, + .private_data = &uart_synth_config, +}; + /* uart parents */ static struct pclk_info uart_pclk_info[] = { { - .pclk = &pll1_clk, - .pclk_mask = AUX_CLK_PLL1_MASK, - .scalable = 1, + .pclk = &uart_synth_clk, + .pclk_val = AUX_CLK_PLL1_VAL, }, { .pclk = &pll3_48m_clk, - .pclk_mask = AUX_CLK_PLL3_MASK, - .scalable = 0, + .pclk_val = AUX_CLK_PLL3_VAL, }, }; @@ -112,19 +189,13 @@ static struct pclk_sel uart_pclk_sel = { .pclk_sel_mask = UART_CLK_MASK, }; -/* uart configurations */ -static struct aux_clk_config uart_config = { - .synth_reg = UART_CLK_SYNT, -}; - /* uart0 clock */ static struct clk uart0_clk = { .en_reg = PERIP1_CLK_ENB, .en_reg_bit = UART0_CLK_ENB, .pclk_sel = &uart_pclk_sel, .pclk_sel_shift = UART_CLK_SHIFT, - .recalc = &aux_clk_recalc, - .private_data = &uart_config, + .recalc = &follow_parent, }; /* uart1 clock */ @@ -133,25 +204,35 @@ static struct clk uart1_clk = { .en_reg_bit = UART1_CLK_ENB, .pclk_sel = &uart_pclk_sel, .pclk_sel_shift = UART_CLK_SHIFT, - .recalc = &aux_clk_recalc, - .private_data = &uart_config, + .recalc = &follow_parent, }; /* firda configurations */ -static struct aux_clk_config firda_config = { +static struct aux_clk_config firda_synth_config = { .synth_reg = FIRDA_CLK_SYNT, + .masks = &aux_masks, +}; + +/* firda synth clock */ +static struct clk firda_synth_clk = { + .en_reg = FIRDA_CLK_SYNT, + .en_reg_bit = AUX_SYNT_ENB, + .pclk = &pll1_clk, + .calc_rate = &aux_calc_rate, + .recalc = &aux_clk_recalc, + .set_rate = &aux_clk_set_rate, + .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2}, + .private_data = &firda_synth_config, }; /* firda parents */ static struct pclk_info firda_pclk_info[] = { { - .pclk = &pll1_clk, - .pclk_mask = AUX_CLK_PLL1_MASK, - .scalable = 1, + .pclk = &firda_synth_clk, + .pclk_val = AUX_CLK_PLL1_VAL, }, { .pclk = &pll3_48m_clk, - .pclk_mask = AUX_CLK_PLL3_MASK, - .scalable = 0, + .pclk_val = AUX_CLK_PLL3_VAL, }, }; @@ -169,25 +250,35 @@ static struct clk firda_clk = { .en_reg_bit = FIRDA_CLK_ENB, .pclk_sel = &firda_pclk_sel, .pclk_sel_shift = FIRDA_CLK_SHIFT, - .recalc = &aux_clk_recalc, - .private_data = &firda_config, + .recalc = &follow_parent, }; /* clcd configurations */ -static struct aux_clk_config clcd_config = { +static struct aux_clk_config clcd_synth_config = { .synth_reg = CLCD_CLK_SYNT, + .masks = &aux_masks, +}; + +/* firda synth clock */ +static struct clk clcd_synth_clk = { + .en_reg = CLCD_CLK_SYNT, + .en_reg_bit = AUX_SYNT_ENB, + .pclk = &pll1_clk, + .calc_rate = &aux_calc_rate, + .recalc = &aux_clk_recalc, + .set_rate = &aux_clk_set_rate, + .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2}, + .private_data = &clcd_synth_config, }; /* clcd parents */ static struct pclk_info clcd_pclk_info[] = { { - .pclk = &pll1_clk, - .pclk_mask = AUX_CLK_PLL1_MASK, - .scalable = 1, + .pclk = &clcd_synth_clk, + .pclk_val = AUX_CLK_PLL1_VAL, }, { .pclk = &pll3_48m_clk, - .pclk_mask = AUX_CLK_PLL3_MASK, - .scalable = 0, + .pclk_val = AUX_CLK_PLL3_VAL, }, }; @@ -205,82 +296,173 @@ static struct clk clcd_clk = { .en_reg_bit = CLCD_CLK_ENB, .pclk_sel = &clcd_pclk_sel, .pclk_sel_shift = CLCD_CLK_SHIFT, - .recalc = &aux_clk_recalc, - .private_data = &clcd_config, + .recalc = &follow_parent, +}; + +/* gpt synthesizer masks */ +static struct gpt_clk_masks gpt_masks = { + .mscale_sel_mask = GPT_MSCALE_MASK, + .mscale_sel_shift = GPT_MSCALE_SHIFT, + .nscale_sel_mask = GPT_NSCALE_MASK, + .nscale_sel_shift = GPT_NSCALE_SHIFT, +}; + +/* gpt rate configuration table, in ascending order of rates */ +struct gpt_rate_tbl gpt_rtbl[] = { + /* For pll1 = 332 MHz */ + {.mscale = 4, .nscale = 0}, /* 41.5 MHz */ + {.mscale = 2, .nscale = 0}, /* 55.3 MHz */ + {.mscale = 1, .nscale = 0}, /* 83 MHz */ +}; + +/* gpt0 synth clk config*/ +static struct gpt_clk_config gpt0_synth_config = { + .synth_reg = PRSC1_CLK_CFG, + .masks = &gpt_masks, +}; + +/* gpt synth clock */ +static struct clk gpt0_synth_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll1_clk, + .calc_rate = &gpt_calc_rate, + .recalc = &gpt_clk_recalc, + .set_rate = &gpt_clk_set_rate, + .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2}, + .private_data = &gpt0_synth_config, }; /* gpt parents */ -static struct pclk_info gpt_pclk_info[] = { +static struct pclk_info gpt0_pclk_info[] = { { - .pclk = &pll1_clk, - .pclk_mask = AUX_CLK_PLL1_MASK, - .scalable = 1, + .pclk = &gpt0_synth_clk, + .pclk_val = AUX_CLK_PLL1_VAL, }, { .pclk = &pll3_48m_clk, - .pclk_mask = AUX_CLK_PLL3_MASK, - .scalable = 0, + .pclk_val = AUX_CLK_PLL3_VAL, }, }; /* gpt parent select structure */ -static struct pclk_sel gpt_pclk_sel = { - .pclk_info = gpt_pclk_info, - .pclk_count = ARRAY_SIZE(gpt_pclk_info), +static struct pclk_sel gpt0_pclk_sel = { + .pclk_info = gpt0_pclk_info, + .pclk_count = ARRAY_SIZE(gpt0_pclk_info), .pclk_sel_reg = PERIP_CLK_CFG, .pclk_sel_mask = GPT_CLK_MASK, }; -/* gpt0_1 configurations */ -static struct aux_clk_config gpt0_1_config = { - .synth_reg = PRSC1_CLK_CFG, -}; - /* gpt0 ARM1 subsystem timer clock */ static struct clk gpt0_clk = { .flags = ALWAYS_ENABLED, - .pclk_sel = &gpt_pclk_sel, + .pclk_sel = &gpt0_pclk_sel, .pclk_sel_shift = GPT0_CLK_SHIFT, - .recalc = &gpt_clk_recalc, - .private_data = &gpt0_1_config, + .recalc = &follow_parent, +}; + + +/* Note: gpt0 and gpt1 share same parent clocks */ +/* gpt parent select structure */ +static struct pclk_sel gpt1_pclk_sel = { + .pclk_info = gpt0_pclk_info, + .pclk_count = ARRAY_SIZE(gpt0_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = GPT_CLK_MASK, }; /* gpt1 timer clock */ static struct clk gpt1_clk = { .flags = ALWAYS_ENABLED, - .pclk_sel = &gpt_pclk_sel, + .pclk_sel = &gpt1_pclk_sel, .pclk_sel_shift = GPT1_CLK_SHIFT, - .recalc = &gpt_clk_recalc, - .private_data = &gpt0_1_config, + .recalc = &follow_parent, }; -/* gpt2 configurations */ -static struct aux_clk_config gpt2_config = { +/* gpt2 synth clk config*/ +static struct gpt_clk_config gpt2_synth_config = { .synth_reg = PRSC2_CLK_CFG, + .masks = &gpt_masks, +}; + +/* gpt synth clock */ +static struct clk gpt2_synth_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll1_clk, + .calc_rate = &gpt_calc_rate, + .recalc = &gpt_clk_recalc, + .set_rate = &gpt_clk_set_rate, + .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2}, + .private_data = &gpt2_synth_config, +}; + +/* gpt parents */ +static struct pclk_info gpt2_pclk_info[] = { + { + .pclk = &gpt2_synth_clk, + .pclk_val = AUX_CLK_PLL1_VAL, + }, { + .pclk = &pll3_48m_clk, + .pclk_val = AUX_CLK_PLL3_VAL, + }, +}; + +/* gpt parent select structure */ +static struct pclk_sel gpt2_pclk_sel = { + .pclk_info = gpt2_pclk_info, + .pclk_count = ARRAY_SIZE(gpt2_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = GPT_CLK_MASK, }; /* gpt2 timer clock */ static struct clk gpt2_clk = { - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = GPT2_CLK_ENB, - .pclk_sel = &gpt_pclk_sel, + .flags = ALWAYS_ENABLED, + .pclk_sel = &gpt2_pclk_sel, .pclk_sel_shift = GPT2_CLK_SHIFT, - .recalc = &gpt_clk_recalc, - .private_data = &gpt2_config, + .recalc = &follow_parent, }; -/* gpt3 configurations */ -static struct aux_clk_config gpt3_config = { +/* gpt3 synth clk config*/ +static struct gpt_clk_config gpt3_synth_config = { .synth_reg = PRSC3_CLK_CFG, + .masks = &gpt_masks, +}; + +/* gpt synth clock */ +static struct clk gpt3_synth_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll1_clk, + .calc_rate = &gpt_calc_rate, + .recalc = &gpt_clk_recalc, + .set_rate = &gpt_clk_set_rate, + .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2}, + .private_data = &gpt3_synth_config, +}; + +/* gpt parents */ +static struct pclk_info gpt3_pclk_info[] = { + { + .pclk = &gpt3_synth_clk, + .pclk_val = AUX_CLK_PLL1_VAL, + }, { + .pclk = &pll3_48m_clk, + .pclk_val = AUX_CLK_PLL3_VAL, + }, +}; + +/* gpt parent select structure */ +static struct pclk_sel gpt3_pclk_sel = { + .pclk_info = gpt3_pclk_info, + .pclk_count = ARRAY_SIZE(gpt3_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = GPT_CLK_MASK, }; /* gpt3 timer clock */ static struct clk gpt3_clk = { - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = GPT3_CLK_ENB, - .pclk_sel = &gpt_pclk_sel, + .flags = ALWAYS_ENABLED, + .pclk_sel = &gpt3_pclk_sel, .pclk_sel_shift = GPT3_CLK_SHIFT, - .recalc = &gpt_clk_recalc, - .private_data = &gpt3_config, + .recalc = &follow_parent, }; /* clock derived from pll3 clk */ @@ -309,18 +491,26 @@ static struct clk usbd_clk = { }; /* clock derived from ahb clk */ +/* apb masks structure */ +static struct bus_clk_masks apb_masks = { + .mask = HCLK_PCLK_RATIO_MASK, + .shift = HCLK_PCLK_RATIO_SHIFT, +}; + /* apb configuration structure */ static struct bus_clk_config apb_config = { .reg = CORE_CLK_CFG, - .mask = HCLK_PCLK_RATIO_MASK, - .shift = HCLK_PCLK_RATIO_SHIFT, + .masks = &apb_masks, }; /* apb clock */ static struct clk apb_clk = { .flags = ALWAYS_ENABLED, .pclk = &ahb_clk, + .calc_rate = &bus_calc_rate, .recalc = &bus_clk_recalc, + .set_rate = &bus_clk_set_rate, + .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2}, .private_data = &apb_config, }; @@ -432,12 +622,12 @@ static struct clk dummy_apb_pclk; /* array of all spear 6xx clock lookups */ static struct clk_lookup spear_clk_lookups[] = { - { .con_id = "apb_pclk", .clk = &dummy_apb_pclk}, + { .con_id = "apb_pclk", .clk = &dummy_apb_pclk}, /* root clks */ { .con_id = "osc_32k_clk", .clk = &osc_32k_clk}, { .con_id = "osc_30m_clk", .clk = &osc_30m_clk}, /* clock derived from 32 KHz os clk */ - { .dev_id = "rtc", .clk = &rtc_clk}, + { .dev_id = "rtc-spear", .clk = &rtc_clk}, /* clock derived from 30 MHz os clk */ { .con_id = "pll1_clk", .clk = &pll1_clk}, { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk}, @@ -445,6 +635,12 @@ static struct clk_lookup spear_clk_lookups[] = { /* clock derived from pll1 clk */ { .con_id = "cpu_clk", .clk = &cpu_clk}, { .con_id = "ahb_clk", .clk = &ahb_clk}, + { .con_id = "uart_synth_clk", .clk = &uart_synth_clk}, + { .con_id = "firda_synth_clk", .clk = &firda_synth_clk}, + { .con_id = "clcd_synth_clk", .clk = &clcd_synth_clk}, + { .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk}, + { .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk}, + { .con_id = "gpt3_synth_clk", .clk = &gpt3_synth_clk}, { .dev_id = "uart0", .clk = &uart0_clk}, { .dev_id = "uart1", .clk = &uart1_clk}, { .dev_id = "firda", .clk = &firda_clk}, @@ -454,22 +650,22 @@ static struct clk_lookup spear_clk_lookups[] = { { .dev_id = "gpt2", .clk = &gpt2_clk}, { .dev_id = "gpt3", .clk = &gpt3_clk}, /* clock derived from pll3 clk */ - { .dev_id = "usbh0", .clk = &usbh0_clk}, - { .dev_id = "usbh1", .clk = &usbh1_clk}, - { .dev_id = "usbd", .clk = &usbd_clk}, + { .dev_id = "designware_udc", .clk = &usbd_clk}, + { .con_id = "usbh.0_clk", .clk = &usbh0_clk}, + { .con_id = "usbh.1_clk", .clk = &usbh1_clk}, /* clock derived from ahb clk */ { .con_id = "apb_clk", .clk = &apb_clk}, - { .dev_id = "i2c", .clk = &i2c_clk}, + { .dev_id = "i2c_designware.0", .clk = &i2c_clk}, { .dev_id = "dma", .clk = &dma_clk}, { .dev_id = "jpeg", .clk = &jpeg_clk}, { .dev_id = "gmac", .clk = &gmac_clk}, { .dev_id = "smi", .clk = &smi_clk}, - { .dev_id = "fsmc", .clk = &fsmc_clk}, + { .con_id = "fsmc", .clk = &fsmc_clk}, /* clock derived from apb clk */ { .dev_id = "adc", .clk = &adc_clk}, - { .dev_id = "ssp0", .clk = &ssp0_clk}, - { .dev_id = "ssp1", .clk = &ssp1_clk}, - { .dev_id = "ssp2", .clk = &ssp2_clk}, + { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk}, + { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk}, + { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk}, { .dev_id = "gpio0", .clk = &gpio0_clk}, { .dev_id = "gpio1", .clk = &gpio1_clk}, { .dev_id = "gpio2", .clk = &gpio2_clk}, diff --git a/arch/arm/mach-spear6xx/include/mach/entry-macro.S b/arch/arm/mach-spear6xx/include/mach/entry-macro.S index 9eaecaeafcf0..8a0b0ed7b203 100644 --- a/arch/arm/mach-spear6xx/include/mach/entry-macro.S +++ b/arch/arm/mach-spear6xx/include/mach/entry-macro.S @@ -11,9 +11,8 @@ * warranty of any kind, whether express or implied. */ -#include <mach/hardware.h> -#include <mach/spear.h> #include <asm/hardware/vic.h> +#include <mach/hardware.h> .macro disable_fiq .endm diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h index 16205a538756..94cf4a648b57 100644 --- a/arch/arm/mach-spear6xx/include/mach/generic.h +++ b/arch/arm/mach-spear6xx/include/mach/generic.h @@ -14,11 +14,11 @@ #ifndef __MACH_GENERIC_H #define __MACH_GENERIC_H -#include <asm/mach/time.h> -#include <asm/mach/map.h> #include <linux/init.h> #include <linux/platform_device.h> #include <linux/amba/bus.h> +#include <asm/mach/time.h> +#include <asm/mach/map.h> /* * Each GPT has 2 timer channels @@ -31,9 +31,10 @@ /* Add spear6xx family device structure declarations here */ extern struct amba_device gpio_device[]; extern struct amba_device uart_device[]; -extern struct sys_timer spear_sys_timer; +extern struct sys_timer spear6xx_timer; /* Add spear6xx family function declarations here */ +void __init spear_setup_timer(void); void __init spear6xx_map_io(void); void __init spear6xx_init_irq(void); void __init spear6xx_init(void); diff --git a/arch/arm/mach-spear6xx/include/mach/hardware.h b/arch/arm/mach-spear6xx/include/mach/hardware.h index 7545116deca9..0b3f96ae2848 100644 --- a/arch/arm/mach-spear6xx/include/mach/hardware.h +++ b/arch/arm/mach-spear6xx/include/mach/hardware.h @@ -14,8 +14,10 @@ #ifndef __MACH_HARDWARE_H #define __MACH_HARDWARE_H +#include <plat/hardware.h> +#include <mach/spear.h> + /* Vitual to physical translation of statically mapped space */ #define IO_ADDRESS(x) (x | 0xF0000000) #endif /* __MACH_HARDWARE_H */ - diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h index 03908036b0d0..68c20a007b0d 100644 --- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h +++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h @@ -14,16 +14,16 @@ #ifndef __MACH_MISC_REGS_H #define __MACH_MISC_REGS_H -#include <mach/spear.h> +#include <mach/hardware.h> -#define MISC_BASE VA_SPEAR6XX_ICM3_MISC_REG_BASE +#define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE) -#define SOC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x000)) -#define DIAG_CFG_CTR ((unsigned int *)(MISC_BASE + 0x004)) -#define PLL1_CTR ((unsigned int *)(MISC_BASE + 0x008)) -#define PLL1_FRQ ((unsigned int *)(MISC_BASE + 0x00C)) -#define PLL1_MOD ((unsigned int *)(MISC_BASE + 0x010)) -#define PLL2_CTR ((unsigned int *)(MISC_BASE + 0x014)) +#define SOC_CFG_CTR (MISC_BASE + 0x000) +#define DIAG_CFG_CTR (MISC_BASE + 0x004) +#define PLL1_CTR (MISC_BASE + 0x008) +#define PLL1_FRQ (MISC_BASE + 0x00C) +#define PLL1_MOD (MISC_BASE + 0x010) +#define PLL2_CTR (MISC_BASE + 0x014) /* PLL_CTR register masks */ #define PLL_ENABLE 2 #define PLL_MODE_SHIFT 4 @@ -33,7 +33,7 @@ #define PLL_MODE_DITH_DSB 2 #define PLL_MODE_DITH_SSB 3 -#define PLL2_FRQ ((unsigned int *)(MISC_BASE + 0x018)) +#define PLL2_FRQ (MISC_BASE + 0x018) /* PLL FRQ register masks */ #define PLL_DIV_N_SHIFT 0 #define PLL_DIV_N_MASK 0xFF @@ -44,16 +44,16 @@ #define PLL_DITH_FDBK_M_SHIFT 16 #define PLL_DITH_FDBK_M_MASK 0xFFFF -#define PLL2_MOD ((unsigned int *)(MISC_BASE + 0x01C)) -#define PLL_CLK_CFG ((unsigned int *)(MISC_BASE + 0x020)) -#define CORE_CLK_CFG ((unsigned int *)(MISC_BASE + 0x024)) +#define PLL2_MOD (MISC_BASE + 0x01C) +#define PLL_CLK_CFG (MISC_BASE + 0x020) +#define CORE_CLK_CFG (MISC_BASE + 0x024) /* CORE CLK CFG register masks */ #define PLL_HCLK_RATIO_SHIFT 10 #define PLL_HCLK_RATIO_MASK 0x3 #define HCLK_PCLK_RATIO_SHIFT 8 #define HCLK_PCLK_RATIO_MASK 0x3 -#define PERIP_CLK_CFG ((unsigned int *)(MISC_BASE + 0x028)) +#define PERIP_CLK_CFG (MISC_BASE + 0x028) /* PERIP_CLK_CFG register masks */ #define CLCD_CLK_SHIFT 2 #define CLCD_CLK_MASK 0x3 @@ -66,10 +66,10 @@ #define GPT2_CLK_SHIFT 11 #define GPT3_CLK_SHIFT 12 #define GPT_CLK_MASK 0x1 -#define AUX_CLK_PLL3_MASK 0 -#define AUX_CLK_PLL1_MASK 1 +#define AUX_CLK_PLL3_VAL 0 +#define AUX_CLK_PLL1_VAL 1 -#define PERIP1_CLK_ENB ((unsigned int *)(MISC_BASE + 0x02C)) +#define PERIP1_CLK_ENB (MISC_BASE + 0x02C) /* PERIP1_CLK_ENB register masks */ #define UART0_CLK_ENB 3 #define UART1_CLK_ENB 4 @@ -95,34 +95,35 @@ #define USBH0_CLK_ENB 25 #define USBH1_CLK_ENB 26 -#define SOC_CORE_ID ((unsigned int *)(MISC_BASE + 0x030)) -#define RAS_CLK_ENB ((unsigned int *)(MISC_BASE + 0x034)) -#define PERIP1_SOF_RST ((unsigned int *)(MISC_BASE + 0x038)) +#define SOC_CORE_ID (MISC_BASE + 0x030) +#define RAS_CLK_ENB (MISC_BASE + 0x034) +#define PERIP1_SOF_RST (MISC_BASE + 0x038) /* PERIP1_SOF_RST register masks */ #define JPEG_SOF_RST 8 -#define SOC_USER_ID ((unsigned int *)(MISC_BASE + 0x03C)) -#define RAS_SOF_RST ((unsigned int *)(MISC_BASE + 0x040)) -#define PRSC1_CLK_CFG ((unsigned int *)(MISC_BASE + 0x044)) -#define PRSC2_CLK_CFG ((unsigned int *)(MISC_BASE + 0x048)) -#define PRSC3_CLK_CFG ((unsigned int *)(MISC_BASE + 0x04C)) +#define SOC_USER_ID (MISC_BASE + 0x03C) +#define RAS_SOF_RST (MISC_BASE + 0x040) +#define PRSC1_CLK_CFG (MISC_BASE + 0x044) +#define PRSC2_CLK_CFG (MISC_BASE + 0x048) +#define PRSC3_CLK_CFG (MISC_BASE + 0x04C) /* gpt synthesizer register masks */ #define GPT_MSCALE_SHIFT 0 #define GPT_MSCALE_MASK 0xFFF #define GPT_NSCALE_SHIFT 12 #define GPT_NSCALE_MASK 0xF -#define AMEM_CLK_CFG ((unsigned int *)(MISC_BASE + 0x050)) -#define EXPI_CLK_CFG ((unsigned int *)(MISC_BASE + 0x054)) -#define CLCD_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x05C)) -#define FIRDA_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x060)) -#define UART_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x064)) -#define GMAC_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x068)) -#define RAS1_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x06C)) -#define RAS2_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x070)) -#define RAS3_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x074)) -#define RAS4_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x078)) +#define AMEM_CLK_CFG (MISC_BASE + 0x050) +#define EXPI_CLK_CFG (MISC_BASE + 0x054) +#define CLCD_CLK_SYNT (MISC_BASE + 0x05C) +#define FIRDA_CLK_SYNT (MISC_BASE + 0x060) +#define UART_CLK_SYNT (MISC_BASE + 0x064) +#define GMAC_CLK_SYNT (MISC_BASE + 0x068) +#define RAS1_CLK_SYNT (MISC_BASE + 0x06C) +#define RAS2_CLK_SYNT (MISC_BASE + 0x070) +#define RAS3_CLK_SYNT (MISC_BASE + 0x074) +#define RAS4_CLK_SYNT (MISC_BASE + 0x078) /* aux clk synthesiser register masks for irda to ras4 */ +#define AUX_SYNT_ENB 31 #define AUX_EQ_SEL_SHIFT 30 #define AUX_EQ_SEL_MASK 1 #define AUX_EQ1_SEL 0 @@ -132,42 +133,42 @@ #define AUX_YSCALE_SHIFT 0 #define AUX_YSCALE_MASK 0xFFF -#define ICM1_ARB_CFG ((unsigned int *)(MISC_BASE + 0x07C)) -#define ICM2_ARB_CFG ((unsigned int *)(MISC_BASE + 0x080)) -#define ICM3_ARB_CFG ((unsigned int *)(MISC_BASE + 0x084)) -#define ICM4_ARB_CFG ((unsigned int *)(MISC_BASE + 0x088)) -#define ICM5_ARB_CFG ((unsigned int *)(MISC_BASE + 0x08C)) -#define ICM6_ARB_CFG ((unsigned int *)(MISC_BASE + 0x090)) -#define ICM7_ARB_CFG ((unsigned int *)(MISC_BASE + 0x094)) -#define ICM8_ARB_CFG ((unsigned int *)(MISC_BASE + 0x098)) -#define ICM9_ARB_CFG ((unsigned int *)(MISC_BASE + 0x09C)) -#define DMA_CHN_CFG ((unsigned int *)(MISC_BASE + 0x0A0)) -#define USB2_PHY_CFG ((unsigned int *)(MISC_BASE + 0x0A4)) -#define GMAC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0A8)) -#define EXPI_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0AC)) -#define PRC1_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C0)) -#define PRC2_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C4)) -#define PRC3_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C8)) -#define PRC4_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0CC)) -#define PRC1_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D0)) -#define PRC2_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D4)) -#define PRC3_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D8)) -#define PRC4_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0DC)) -#define PWRDOWN_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0E0)) -#define COMPSSTL_1V8_CFG ((unsigned int *)(MISC_BASE + 0x0E4)) -#define COMPSSTL_2V5_CFG ((unsigned int *)(MISC_BASE + 0x0E8)) -#define COMPCOR_3V3_CFG ((unsigned int *)(MISC_BASE + 0x0EC)) -#define SSTLPAD_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F0)) -#define BIST1_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F4)) -#define BIST2_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F8)) -#define BIST3_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0FC)) -#define BIST4_CFG_CTR ((unsigned int *)(MISC_BASE + 0x100)) -#define BIST5_CFG_CTR ((unsigned int *)(MISC_BASE + 0x104)) -#define BIST1_STS_RES ((unsigned int *)(MISC_BASE + 0x108)) -#define BIST2_STS_RES ((unsigned int *)(MISC_BASE + 0x10C)) -#define BIST3_STS_RES ((unsigned int *)(MISC_BASE + 0x110)) -#define BIST4_STS_RES ((unsigned int *)(MISC_BASE + 0x114)) -#define BIST5_STS_RES ((unsigned int *)(MISC_BASE + 0x118)) -#define SYSERR_CFG_CTR ((unsigned int *)(MISC_BASE + 0x11C)) +#define ICM1_ARB_CFG (MISC_BASE + 0x07C) +#define ICM2_ARB_CFG (MISC_BASE + 0x080) +#define ICM3_ARB_CFG (MISC_BASE + 0x084) +#define ICM4_ARB_CFG (MISC_BASE + 0x088) +#define ICM5_ARB_CFG (MISC_BASE + 0x08C) +#define ICM6_ARB_CFG (MISC_BASE + 0x090) +#define ICM7_ARB_CFG (MISC_BASE + 0x094) +#define ICM8_ARB_CFG (MISC_BASE + 0x098) +#define ICM9_ARB_CFG (MISC_BASE + 0x09C) +#define DMA_CHN_CFG (MISC_BASE + 0x0A0) +#define USB2_PHY_CFG (MISC_BASE + 0x0A4) +#define GMAC_CFG_CTR (MISC_BASE + 0x0A8) +#define EXPI_CFG_CTR (MISC_BASE + 0x0AC) +#define PRC1_LOCK_CTR (MISC_BASE + 0x0C0) +#define PRC2_LOCK_CTR (MISC_BASE + 0x0C4) +#define PRC3_LOCK_CTR (MISC_BASE + 0x0C8) +#define PRC4_LOCK_CTR (MISC_BASE + 0x0CC) +#define PRC1_IRQ_CTR (MISC_BASE + 0x0D0) +#define PRC2_IRQ_CTR (MISC_BASE + 0x0D4) +#define PRC3_IRQ_CTR (MISC_BASE + 0x0D8) +#define PRC4_IRQ_CTR (MISC_BASE + 0x0DC) +#define PWRDOWN_CFG_CTR (MISC_BASE + 0x0E0) +#define COMPSSTL_1V8_CFG (MISC_BASE + 0x0E4) +#define COMPSSTL_2V5_CFG (MISC_BASE + 0x0E8) +#define COMPCOR_3V3_CFG (MISC_BASE + 0x0EC) +#define SSTLPAD_CFG_CTR (MISC_BASE + 0x0F0) +#define BIST1_CFG_CTR (MISC_BASE + 0x0F4) +#define BIST2_CFG_CTR (MISC_BASE + 0x0F8) +#define BIST3_CFG_CTR (MISC_BASE + 0x0FC) +#define BIST4_CFG_CTR (MISC_BASE + 0x100) +#define BIST5_CFG_CTR (MISC_BASE + 0x104) +#define BIST1_STS_RES (MISC_BASE + 0x108) +#define BIST2_STS_RES (MISC_BASE + 0x10C) +#define BIST3_STS_RES (MISC_BASE + 0x110) +#define BIST4_STS_RES (MISC_BASE + 0x114) +#define BIST5_STS_RES (MISC_BASE + 0x118) +#define SYSERR_CFG_CTR (MISC_BASE + 0x11C) #endif /* __MACH_MISC_REGS_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h index a835f5b6b182..7fd621532def 100644 --- a/arch/arm/mach-spear6xx/include/mach/spear.h +++ b/arch/arm/mach-spear6xx/include/mach/spear.h @@ -14,153 +14,70 @@ #ifndef __MACH_SPEAR6XX_H #define __MACH_SPEAR6XX_H -#include <mach/hardware.h> +#include <asm/memory.h> #include <mach/spear600.h> -#define SPEAR6XX_ML_SDRAM_BASE 0x00000000 -#define SPEAR6XX_ML_SDRAM_SIZE 0x40000000 - +#define SPEAR6XX_ML_SDRAM_BASE UL(0x00000000) /* ICM1 - Low speed connection */ -#define SPEAR6XX_ICM1_BASE 0xD0000000 -#define SPEAR6XX_ICM1_SIZE 0x08000000 +#define SPEAR6XX_ICM1_BASE UL(0xD0000000) -#define SPEAR6XX_ICM1_UART0_BASE 0xD0000000 +#define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000) #define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE) -#define SPEAR6XX_ICM1_UART0_SIZE 0x00080000 - -#define SPEAR6XX_ICM1_UART1_BASE 0xD0080000 -#define SPEAR6XX_ICM1_UART1_SIZE 0x00080000 - -#define SPEAR6XX_ICM1_SSP0_BASE 0xD0100000 -#define SPEAR6XX_ICM1_SSP0_SIZE 0x00080000 - -#define SPEAR6XX_ICM1_SSP1_BASE 0xD0180000 -#define SPEAR6XX_ICM1_SSP1_SIZE 0x00080000 - -#define SPEAR6XX_ICM1_I2C_BASE 0xD0200000 -#define SPEAR6XX_ICM1_I2C_SIZE 0x00080000 -#define SPEAR6XX_ICM1_JPEG_BASE 0xD0800000 -#define SPEAR6XX_ICM1_JPEG_SIZE 0x00800000 - -#define SPEAR6XX_ICM1_IRDA_BASE 0xD1000000 -#define SPEAR6XX_ICM1_IRDA_SIZE 0x00800000 - -#define SPEAR6XX_ICM1_FSMC_BASE 0xD1800000 -#define SPEAR6XX_ICM1_FSMC_SIZE 0x00800000 - -#define SPEAR6XX_ICM1_NAND_BASE 0xD2000000 -#define SPEAR6XX_ICM1_NAND_SIZE 0x00800000 - -#define SPEAR6XX_ICM1_SRAM_BASE 0xD2800000 -#define SPEAR6XX_ICM1_SRAM_SIZE 0x00800000 +#define SPEAR6XX_ICM1_UART1_BASE UL(0xD0080000) +#define SPEAR6XX_ICM1_SSP0_BASE UL(0xD0100000) +#define SPEAR6XX_ICM1_SSP1_BASE UL(0xD0180000) +#define SPEAR6XX_ICM1_I2C_BASE UL(0xD0200000) +#define SPEAR6XX_ICM1_JPEG_BASE UL(0xD0800000) +#define SPEAR6XX_ICM1_IRDA_BASE UL(0xD1000000) +#define SPEAR6XX_ICM1_FSMC_BASE UL(0xD1800000) +#define SPEAR6XX_ICM1_NAND_BASE UL(0xD2000000) +#define SPEAR6XX_ICM1_SRAM_BASE UL(0xD2800000) /* ICM2 - Application Subsystem */ -#define SPEAR6XX_ICM2_BASE 0xD8000000 -#define SPEAR6XX_ICM2_SIZE 0x08000000 - -#define SPEAR6XX_ICM2_TMR0_BASE 0xD8000000 -#define SPEAR6XX_ICM2_TMR0_SIZE 0x00080000 - -#define SPEAR6XX_ICM2_TMR1_BASE 0xD8080000 -#define SPEAR6XX_ICM2_TMR1_SIZE 0x00080000 - -#define SPEAR6XX_ICM2_GPIO_BASE 0xD8100000 -#define SPEAR6XX_ICM2_GPIO_SIZE 0x00080000 - -#define SPEAR6XX_ICM2_SPI2_BASE 0xD8180000 -#define SPEAR6XX_ICM2_SPI2_SIZE 0x00080000 - -#define SPEAR6XX_ICM2_ADC_BASE 0xD8200000 -#define SPEAR6XX_ICM2_ADC_SIZE 0x00080000 +#define SPEAR6XX_ICM2_BASE UL(0xD8000000) +#define SPEAR6XX_ICM2_TMR0_BASE UL(0xD8000000) +#define SPEAR6XX_ICM2_TMR1_BASE UL(0xD8080000) +#define SPEAR6XX_ICM2_GPIO_BASE UL(0xD8100000) +#define SPEAR6XX_ICM2_SSP2_BASE UL(0xD8180000) +#define SPEAR6XX_ICM2_ADC_BASE UL(0xD8200000) /* ML-1, 2 - Multi Layer CPU Subsystem */ -#define SPEAR6XX_ML_CPU_BASE 0xF0000000 -#define SPEAR6XX_ML_CPU_SIZE 0x08000000 - -#define SPEAR6XX_CPU_TMR_BASE 0xF0000000 -#define SPEAR6XX_CPU_TMR_SIZE 0x00100000 - -#define SPEAR6XX_CPU_GPIO_BASE 0xF0100000 -#define SPEAR6XX_CPU_GPIO_SIZE 0x00100000 - -#define SPEAR6XX_CPU_VIC_SEC_BASE 0xF1000000 +#define SPEAR6XX_ML_CPU_BASE UL(0xF0000000) +#define SPEAR6XX_CPU_TMR_BASE UL(0xF0000000) +#define SPEAR6XX_CPU_GPIO_BASE UL(0xF0100000) +#define SPEAR6XX_CPU_VIC_SEC_BASE UL(0xF1000000) #define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE) -#define SPEAR6XX_CPU_VIC_SEC_SIZE 0x00100000 - -#define SPEAR6XX_CPU_VIC_PRI_BASE 0xF1100000 +#define SPEAR6XX_CPU_VIC_PRI_BASE UL(0xF1100000) #define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE) -#define SPEAR6XX_CPU_VIC_PRI_SIZE 0x00100000 /* ICM3 - Basic Subsystem */ -#define SPEAR6XX_ICM3_BASE 0xF8000000 -#define SPEAR6XX_ICM3_SIZE 0x08000000 - -#define SPEAR6XX_ICM3_SMEM_BASE 0xF8000000 -#define SPEAR6XX_ICM3_SMEM_SIZE 0x04000000 - -#define SPEAR6XX_ICM3_SMI_CTRL_BASE 0xFC000000 -#define SPEAR6XX_ICM3_SMI_CTRL_SIZE 0x00200000 - -#define SPEAR6XX_ICM3_CLCD_BASE 0xFC200000 -#define SPEAR6XX_ICM3_CLCD_SIZE 0x00200000 - -#define SPEAR6XX_ICM3_DMA_BASE 0xFC400000 -#define SPEAR6XX_ICM3_DMA_SIZE 0x00200000 - -#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE 0xFC600000 -#define SPEAR6XX_ICM3_SDRAM_CTRL_SIZE 0x00200000 - -#define SPEAR6XX_ICM3_TMR_BASE 0xFC800000 -#define SPEAR6XX_ICM3_TMR_SIZE 0x00080000 - -#define SPEAR6XX_ICM3_WDT_BASE 0xFC880000 -#define SPEAR6XX_ICM3_WDT_SIZE 0x00080000 - -#define SPEAR6XX_ICM3_RTC_BASE 0xFC900000 -#define SPEAR6XX_ICM3_RTC_SIZE 0x00080000 - -#define SPEAR6XX_ICM3_GPIO_BASE 0xFC980000 -#define SPEAR6XX_ICM3_GPIO_SIZE 0x00080000 - -#define SPEAR6XX_ICM3_SYS_CTRL_BASE 0xFCA00000 +#define SPEAR6XX_ICM3_BASE UL(0xF8000000) +#define SPEAR6XX_ICM3_SMEM_BASE UL(0xF8000000) +#define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) +#define SPEAR6XX_ICM3_CLCD_BASE UL(0xFC200000) +#define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000) +#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000) +#define SPEAR6XX_ICM3_TMR_BASE UL(0xFC800000) +#define SPEAR6XX_ICM3_WDT_BASE UL(0xFC880000) +#define SPEAR6XX_ICM3_RTC_BASE UL(0xFC900000) +#define SPEAR6XX_ICM3_GPIO_BASE UL(0xFC980000) +#define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) #define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE) -#define SPEAR6XX_ICM3_SYS_CTRL_SIZE 0x00080000 - -#define SPEAR6XX_ICM3_MISC_REG_BASE 0xFCA80000 +#define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000) #define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE) -#define SPEAR6XX_ICM3_MISC_REG_SIZE 0x00080000 /* ICM4 - High Speed Connection */ -#define SPEAR6XX_ICM4_BASE 0xE0000000 -#define SPEAR6XX_ICM4_SIZE 0x08000000 - -#define SPEAR6XX_ICM4_GMAC_BASE 0xE0800000 -#define SPEAR6XX_ICM4_GMAC_SIZE 0x00800000 - -#define SPEAR6XX_ICM4_USBD_FIFO_BASE 0xE1000000 -#define SPEAR6XX_ICM4_USBD_FIFO_SIZE 0x00100000 - -#define SPEAR6XX_ICM4_USBD_CSR_BASE 0xE1100000 -#define SPEAR6XX_ICM4_USBD_CSR_SIZE 0x00100000 - -#define SPEAR6XX_ICM4_USBD_PLDT_BASE 0xE1200000 -#define SPEAR6XX_ICM4_USBD_PLDT_SIZE 0x00100000 - -#define SPEAR6XX_ICM4_USB_EHCI0_BASE 0xE1800000 -#define SPEAR6XX_ICM4_USB_EHCI0_SIZE 0x00100000 - -#define SPEAR6XX_ICM4_USB_OHCI0_BASE 0xE1900000 -#define SPEAR6XX_ICM4_USB_OHCI0_SIZE 0x00100000 - -#define SPEAR6XX_ICM4_USB_EHCI1_BASE 0xE2000000 -#define SPEAR6XX_ICM4_USB_EHCI1_SIZE 0x00100000 - -#define SPEAR6XX_ICM4_USB_OHCI1_BASE 0xE2100000 -#define SPEAR6XX_ICM4_USB_OHCI1_SIZE 0x00100000 - -#define SPEAR6XX_ICM4_USB_ARB_BASE 0xE2800000 -#define SPEAR6XX_ICM4_USB_ARB_SIZE 0x00010000 +#define SPEAR6XX_ICM4_BASE UL(0xE0000000) +#define SPEAR6XX_ICM4_GMAC_BASE UL(0xE0800000) +#define SPEAR6XX_ICM4_USBD_FIFO_BASE UL(0xE1000000) +#define SPEAR6XX_ICM4_USBD_CSR_BASE UL(0xE1100000) +#define SPEAR6XX_ICM4_USBD_PLDT_BASE UL(0xE1200000) +#define SPEAR6XX_ICM4_USB_EHCI0_BASE UL(0xE1800000) +#define SPEAR6XX_ICM4_USB_OHCI0_BASE UL(0xE1900000) +#define SPEAR6XX_ICM4_USB_EHCI1_BASE UL(0xE2000000) +#define SPEAR6XX_ICM4_USB_OHCI1_BASE UL(0xE2100000) +#define SPEAR6XX_ICM4_USB_ARB_BASE UL(0xE2800000) /* Debug uart for linux, will be used for debug and uncompress messages */ #define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE diff --git a/arch/arm/mach-spear6xx/spear600.c b/arch/arm/mach-spear6xx/spear600.c index 5c484c433dc1..d0e6eeae9b04 100644 --- a/arch/arm/mach-spear6xx/spear600.c +++ b/arch/arm/mach-spear6xx/spear600.c @@ -14,7 +14,7 @@ #include <linux/ptrace.h> #include <asm/irq.h> #include <mach/generic.h> -#include <mach/spear.h> +#include <mach/hardware.h> /* Add spear600 specific devices here */ diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c index daff8d04f7b6..f19cefe91a2b 100644 --- a/arch/arm/mach-spear6xx/spear600_evb.c +++ b/arch/arm/mach-spear6xx/spear600_evb.c @@ -14,7 +14,7 @@ #include <asm/mach/arch.h> #include <asm/mach-types.h> #include <mach/generic.h> -#include <mach/spear.h> +#include <mach/hardware.h> static struct amba_device *amba_devs[] __initdata = { &gpio_device[0], @@ -46,6 +46,6 @@ MACHINE_START(SPEAR600, "ST-SPEAR600-EVB") .boot_params = 0x00000100, .map_io = spear6xx_map_io, .init_irq = spear6xx_init_irq, - .timer = &spear_sys_timer, + .timer = &spear6xx_timer, .init_machine = spear600_evb_init, MACHINE_END diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c index f2fe14e8471d..981812961ac7 100644 --- a/arch/arm/mach-spear6xx/spear6xx.c +++ b/arch/arm/mach-spear6xx/spear6xx.c @@ -18,9 +18,9 @@ #include <asm/hardware/vic.h> #include <asm/irq.h> #include <asm/mach/arch.h> -#include <mach/irqs.h> #include <mach/generic.h> -#include <mach/spear.h> +#include <mach/hardware.h> +#include <mach/irqs.h> /* Add spear6xx machines common devices here */ /* uart device registration */ @@ -31,8 +31,7 @@ struct amba_device uart_device[] = { }, .res = { .start = SPEAR6XX_ICM1_UART0_BASE, - .end = SPEAR6XX_ICM1_UART0_BASE + - SPEAR6XX_ICM1_UART0_SIZE - 1, + .end = SPEAR6XX_ICM1_UART0_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, .irq = {IRQ_UART_0, NO_IRQ}, @@ -42,8 +41,7 @@ struct amba_device uart_device[] = { }, .res = { .start = SPEAR6XX_ICM1_UART1_BASE, - .end = SPEAR6XX_ICM1_UART1_BASE + - SPEAR6XX_ICM1_UART1_SIZE - 1, + .end = SPEAR6XX_ICM1_UART1_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, .irq = {IRQ_UART_1, NO_IRQ}, @@ -72,8 +70,7 @@ struct amba_device gpio_device[] = { }, .res = { .start = SPEAR6XX_CPU_GPIO_BASE, - .end = SPEAR6XX_CPU_GPIO_BASE + - SPEAR6XX_CPU_GPIO_SIZE - 1, + .end = SPEAR6XX_CPU_GPIO_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, .irq = {IRQ_LOCAL_GPIO, NO_IRQ}, @@ -84,8 +81,7 @@ struct amba_device gpio_device[] = { }, .res = { .start = SPEAR6XX_ICM3_GPIO_BASE, - .end = SPEAR6XX_ICM3_GPIO_BASE + - SPEAR6XX_ICM3_GPIO_SIZE - 1, + .end = SPEAR6XX_ICM3_GPIO_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, .irq = {IRQ_BASIC_GPIO, NO_IRQ}, @@ -96,8 +92,7 @@ struct amba_device gpio_device[] = { }, .res = { .start = SPEAR6XX_ICM2_GPIO_BASE, - .end = SPEAR6XX_ICM2_GPIO_BASE + - SPEAR6XX_ICM2_GPIO_SIZE - 1, + .end = SPEAR6XX_ICM2_GPIO_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, .irq = {IRQ_APPL_GPIO, NO_IRQ}, @@ -122,27 +117,27 @@ static struct map_desc spear6xx_io_desc[] __initdata = { { .virtual = VA_SPEAR6XX_ICM1_UART0_BASE, .pfn = __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE), - .length = SPEAR6XX_ICM1_UART0_SIZE, + .length = SZ_4K, .type = MT_DEVICE }, { .virtual = VA_SPEAR6XX_CPU_VIC_PRI_BASE, .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE), - .length = SPEAR6XX_CPU_VIC_PRI_SIZE, + .length = SZ_4K, .type = MT_DEVICE }, { .virtual = VA_SPEAR6XX_CPU_VIC_SEC_BASE, .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE), - .length = SPEAR6XX_CPU_VIC_SEC_SIZE, + .length = SZ_4K, .type = MT_DEVICE }, { .virtual = VA_SPEAR6XX_ICM3_SYS_CTRL_BASE, .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE), - .length = SPEAR6XX_ICM3_MISC_REG_BASE, + .length = SZ_4K, .type = MT_DEVICE }, { .virtual = VA_SPEAR6XX_ICM3_MISC_REG_BASE, .pfn = __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE), - .length = SPEAR6XX_ICM3_MISC_REG_SIZE, + .length = SZ_4K, .type = MT_DEVICE }, }; @@ -155,3 +150,34 @@ void __init spear6xx_map_io(void) /* This will initialize clock framework */ clk_init(); } + +static void __init spear6xx_timer_init(void) +{ + char pclk_name[] = "pll3_48m_clk"; + struct clk *gpt_clk, *pclk; + + /* get the system timer clock */ + gpt_clk = clk_get_sys("gpt0", NULL); + if (IS_ERR(gpt_clk)) { + pr_err("%s:couldn't get clk for gpt\n", __func__); + BUG(); + } + + /* get the suitable parent clock for timer*/ + pclk = clk_get(NULL, pclk_name); + if (IS_ERR(pclk)) { + pr_err("%s:couldn't get %s as parent for gpt\n", + __func__, pclk_name); + BUG(); + } + + clk_set_parent(gpt_clk, pclk); + clk_put(gpt_clk); + clk_put(pclk); + + spear_setup_timer(); +} + +struct sys_timer spear6xx_timer = { + .init = spear6xx_timer_init, +}; diff --git a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c index 7991415e666b..fb6426ddeb77 100644 --- a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c +++ b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c @@ -54,7 +54,7 @@ static void __init tcc8k_map_io(void) } MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board") - .boot_params = PHYS_OFFSET + 0x00000100, + .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .map_io = tcc8k_map_io, .init_irq = tcc8k_init_irq, .init_machine = tcc8k_init, diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index acd9552f8ada..622a9ec1ff08 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -10,6 +10,9 @@ config ARCH_TEGRA_2x_SOC select CPU_V7 select ARM_GIC select ARCH_REQUIRE_GPIOLIB + select USB_ARCH_HAS_EHCI if USB_SUPPORT + select USB_ULPI if USB_SUPPORT + select USB_ULPI_VIEWPORT if USB_SUPPORT help Support for NVIDIA Tegra AP20 and T20 processors, based on the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller @@ -27,6 +30,31 @@ config MACH_HARMONY help Support for nVidia Harmony development platform +config MACH_KAEN + bool "Kaen board" + select MACH_SEABOARD + help + Support for the Kaen version of Seaboard + +config MACH_SEABOARD + bool "Seaboard board" + help + Support for nVidia Seaboard development platform. It will + also be included for some of the derivative boards that + have large similarities with the seaboard design. + +config MACH_TRIMSLICE + bool "TrimSlice board" + select TEGRA_PCI + help + Support for CompuLab TrimSlice platform + +config MACH_WARIO + bool "Wario board" + select MACH_SEABOARD + help + Support for the Wario version of Seaboard + choice prompt "Low-level debug console UART" default TEGRA_DEBUG_UART_NONE @@ -58,4 +86,7 @@ config TEGRA_SYSTEM_DMA Adds system DMA functionality for NVIDIA Tegra SoCs, used by several Tegra device drivers +config TEGRA_EMC_SCALING_ENABLE + bool "Enable scaling the memory frequency" + endif diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index cdbc68e4c0ca..9f7a7e1e0c38 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -1,21 +1,30 @@ obj-y += common.o +obj-y += devices.o obj-y += io.o obj-y += irq.o legacy_irq.o obj-y += clock.o obj-y += timer.o obj-y += gpio.o obj-y += pinmux.o +obj-y += powergate.o obj-y += fuse.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clock.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o -obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_dvfs.o +obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-t2-tables.o obj-$(CONFIG_SMP) += platsmp.o localtimer.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o obj-$(CONFIG_TEGRA_PCI) += pcie.o +obj-$(CONFIG_USB_SUPPORT) += usb_phy.o obj-${CONFIG_MACH_HARMONY} += board-harmony.o obj-${CONFIG_MACH_HARMONY} += board-harmony-pinmux.o obj-${CONFIG_MACH_HARMONY} += board-harmony-pcie.o + +obj-${CONFIG_MACH_SEABOARD} += board-seaboard.o +obj-${CONFIG_MACH_SEABOARD} += board-seaboard-pinmux.o + +obj-${CONFIG_MACH_TRIMSLICE} += board-trimslice.o +obj-${CONFIG_MACH_TRIMSLICE} += board-trimslice-pinmux.o diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c index 50b15d500cac..98368d947be3 100644 --- a/arch/arm/mach-tegra/board-harmony-pinmux.c +++ b/arch/arm/mach-tegra/board-harmony-pinmux.c @@ -15,8 +15,10 @@ */ #include <linux/kernel.h> +#include <linux/gpio.h> #include <mach/pinmux.h> +#include "gpio-names.h" #include "board-harmony.h" static struct tegra_pingroup_config harmony_pinmux[] = { @@ -34,10 +36,10 @@ static struct tegra_pingroup_config harmony_pinmux[] = { {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, - {TEGRA_PINGROUP_DTA, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, - {TEGRA_PINGROUP_DTB, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTA, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTB, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_DTC, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, - {TEGRA_PINGROUP_DTD, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTD, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_DTE, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, @@ -138,7 +140,18 @@ static struct tegra_pingroup_config harmony_pinmux[] = { {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, }; +static struct tegra_gpio_table gpio_table[] = { + { .gpio = TEGRA_GPIO_PI5, .enable = true }, /* mmc2 cd */ + { .gpio = TEGRA_GPIO_PH1, .enable = true }, /* mmc2 wp */ + { .gpio = TEGRA_GPIO_PT3, .enable = true }, /* mmc2 pwr */ + { .gpio = TEGRA_GPIO_PH2, .enable = true }, /* mmc4 cd */ + { .gpio = TEGRA_GPIO_PH3, .enable = true }, /* mmc4 wp */ + { .gpio = TEGRA_GPIO_PI6, .enable = true }, /* mmc4 pwr */ +}; + void harmony_pinmux_init(void) { tegra_pinmux_config_table(harmony_pinmux, ARRAY_SIZE(harmony_pinmux)); + + tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table)); } diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c index b9dbdb1289d0..49224e936eb4 100644 --- a/arch/arm/mach-tegra/board-harmony.c +++ b/arch/arm/mach-tegra/board-harmony.c @@ -30,35 +30,13 @@ #include <mach/iomap.h> #include <mach/irqs.h> +#include <mach/sdhci.h> #include "board.h" #include "board-harmony.h" #include "clock.h" - -/* NVidia bootloader tags */ -#define ATAG_NVIDIA 0x41000801 - -#define ATAG_NVIDIA_RM 0x1 -#define ATAG_NVIDIA_DISPLAY 0x2 -#define ATAG_NVIDIA_FRAMEBUFFER 0x3 -#define ATAG_NVIDIA_CHIPSHMOO 0x4 -#define ATAG_NVIDIA_CHIPSHMOOPHYS 0x5 -#define ATAG_NVIDIA_PRESERVED_MEM_0 0x10000 -#define ATAG_NVIDIA_PRESERVED_MEM_N 2 -#define ATAG_NVIDIA_FORCE_32 0x7fffffff - -struct tag_tegra { - __u32 bootarg_key; - __u32 bootarg_len; - char bootarg[1]; -}; - -static int __init parse_tag_nvidia(const struct tag *tag) -{ - - return 0; -} -__tagtable(ATAG_NVIDIA, parse_tag_nvidia); +#include "devices.h" +#include "gpio-names.h" static struct plat_serial8250_port debug_uart_platform_data[] = { { @@ -84,6 +62,9 @@ static struct platform_device debug_uart = { static struct platform_device *harmony_devices[] __initdata = { &debug_uart, + &tegra_sdhci_device1, + &tegra_sdhci_device2, + &tegra_sdhci_device4, }; static void __init tegra_harmony_fixup(struct machine_desc *desc, @@ -102,22 +83,45 @@ static __initdata struct tegra_clk_init_table harmony_clk_init_table[] = { { NULL, NULL, 0, 0}, }; + +static struct tegra_sdhci_platform_data sdhci_pdata1 = { + .cd_gpio = -1, + .wp_gpio = -1, + .power_gpio = -1, +}; + +static struct tegra_sdhci_platform_data sdhci_pdata2 = { + .cd_gpio = TEGRA_GPIO_PI5, + .wp_gpio = TEGRA_GPIO_PH1, + .power_gpio = TEGRA_GPIO_PT3, +}; + +static struct tegra_sdhci_platform_data sdhci_pdata4 = { + .cd_gpio = TEGRA_GPIO_PH2, + .wp_gpio = TEGRA_GPIO_PH3, + .power_gpio = TEGRA_GPIO_PI6, + .is_8bit = 1, +}; + static void __init tegra_harmony_init(void) { - tegra_common_init(); - tegra_clk_init_from_table(harmony_clk_init_table); harmony_pinmux_init(); + tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1; + tegra_sdhci_device2.dev.platform_data = &sdhci_pdata2; + tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4; + platform_add_devices(harmony_devices, ARRAY_SIZE(harmony_devices)); } MACHINE_START(HARMONY, "harmony") .boot_params = 0x00000100, .fixup = tegra_harmony_fixup, - .init_irq = tegra_init_irq, - .init_machine = tegra_harmony_init, .map_io = tegra_map_common_io, + .init_early = tegra_init_early, + .init_irq = tegra_init_irq, .timer = &tegra_timer, + .init_machine = tegra_harmony_init, MACHINE_END diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c new file mode 100644 index 000000000000..2d6ad83ed4b2 --- /dev/null +++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c @@ -0,0 +1,179 @@ +/* + * Copyright (C) 2010 NVIDIA Corporation + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/gpio.h> + +#include <mach/pinmux.h> +#include <mach/pinmux-t2.h> + +#include "gpio-names.h" +#include "board-seaboard.h" + +#define DEFAULT_DRIVE(_name) \ + { \ + .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \ + .hsm = TEGRA_HSM_DISABLE, \ + .schmitt = TEGRA_SCHMITT_ENABLE, \ + .drive = TEGRA_DRIVE_DIV_1, \ + .pull_down = TEGRA_PULL_31, \ + .pull_up = TEGRA_PULL_31, \ + .slew_rising = TEGRA_SLEW_SLOWEST, \ + .slew_falling = TEGRA_SLEW_SLOWEST, \ + } + +static __initdata struct tegra_drive_pingroup_config seaboard_drive_pinmux[] = { + DEFAULT_DRIVE(SDIO1), +}; + +static __initdata struct tegra_pingroup_config seaboard_pinmux[] = { + {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTE, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPU, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LCSN, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LDC, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LM0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LM1, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LPW0, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LPW1, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LPW2, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSC1, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSCK, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSDA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSDI, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LVP0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDB, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDD, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, +}; + + + + +static struct tegra_gpio_table gpio_table[] = { + { .gpio = TEGRA_GPIO_PI5, .enable = true }, /* mmc2 cd */ + { .gpio = TEGRA_GPIO_PH1, .enable = true }, /* mmc2 wp */ + { .gpio = TEGRA_GPIO_PI6, .enable = true }, /* mmc2 pwr */ + { .gpio = TEGRA_GPIO_LIDSWITCH, .enable = true }, /* lid switch */ + { .gpio = TEGRA_GPIO_POWERKEY, .enable = true }, /* power key */ +}; + +void __init seaboard_pinmux_init(void) +{ + tegra_pinmux_config_table(seaboard_pinmux, ARRAY_SIZE(seaboard_pinmux)); + + tegra_drive_pinmux_config_table(seaboard_drive_pinmux, + ARRAY_SIZE(seaboard_drive_pinmux)); + + tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c new file mode 100644 index 000000000000..6ca9e61f6cd0 --- /dev/null +++ b/arch/arm/mach-tegra/board-seaboard.c @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2010, 2011 NVIDIA Corporation. + * Copyright (C) 2010, 2011 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/serial_8250.h> +#include <linux/delay.h> +#include <linux/input.h> +#include <linux/io.h> +#include <linux/gpio_keys.h> + +#include <mach/iomap.h> +#include <mach/irqs.h> +#include <mach/sdhci.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include "board.h" +#include "board-seaboard.h" +#include "clock.h" +#include "devices.h" +#include "gpio-names.h" + +static struct plat_serial8250_port debug_uart_platform_data[] = { + { + /* Memory and IRQ filled in before registration */ + .flags = UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = 216000000, + }, { + .flags = 0, + } +}; + +static struct platform_device debug_uart = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = debug_uart_platform_data, + }, +}; + +static __initdata struct tegra_clk_init_table seaboard_clk_init_table[] = { + /* name parent rate enabled */ + { "uartb", "pll_p", 216000000, true}, + { "uartd", "pll_p", 216000000, true}, + { NULL, NULL, 0, 0}, +}; + +static struct gpio_keys_button seaboard_gpio_keys_buttons[] = { + { + .code = SW_LID, + .gpio = TEGRA_GPIO_LIDSWITCH, + .active_low = 0, + .desc = "Lid", + .type = EV_SW, + .wakeup = 1, + .debounce_interval = 1, + }, + { + .code = KEY_POWER, + .gpio = TEGRA_GPIO_POWERKEY, + .active_low = 1, + .desc = "Power", + .type = EV_KEY, + .wakeup = 1, + }, +}; + +static struct gpio_keys_platform_data seaboard_gpio_keys = { + .buttons = seaboard_gpio_keys_buttons, + .nbuttons = ARRAY_SIZE(seaboard_gpio_keys_buttons), +}; + +static struct platform_device seaboard_gpio_keys_device = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &seaboard_gpio_keys, + } +}; + +static struct tegra_sdhci_platform_data sdhci_pdata1 = { + .cd_gpio = -1, + .wp_gpio = -1, + .power_gpio = -1, +}; + +static struct tegra_sdhci_platform_data sdhci_pdata3 = { + .cd_gpio = TEGRA_GPIO_PI5, + .wp_gpio = TEGRA_GPIO_PH1, + .power_gpio = TEGRA_GPIO_PI6, +}; + +static struct tegra_sdhci_platform_data sdhci_pdata4 = { + .cd_gpio = -1, + .wp_gpio = -1, + .power_gpio = -1, + .is_8bit = 1, +}; + +static struct platform_device *seaboard_devices[] __initdata = { + &debug_uart, + &tegra_pmu_device, + &tegra_sdhci_device1, + &tegra_sdhci_device3, + &tegra_sdhci_device4, + &seaboard_gpio_keys_device, +}; + +static void __init __tegra_seaboard_init(void) +{ + seaboard_pinmux_init(); + + tegra_clk_init_from_table(seaboard_clk_init_table); + + tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1; + tegra_sdhci_device3.dev.platform_data = &sdhci_pdata3; + tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4; + + platform_add_devices(seaboard_devices, ARRAY_SIZE(seaboard_devices)); +} + +static void __init tegra_seaboard_init(void) +{ + /* Seaboard uses UARTD for the debug port. */ + debug_uart_platform_data[0].membase = IO_ADDRESS(TEGRA_UARTD_BASE); + debug_uart_platform_data[0].mapbase = TEGRA_UARTD_BASE; + debug_uart_platform_data[0].irq = INT_UARTD; + + __tegra_seaboard_init(); +} + +static void __init tegra_kaen_init(void) +{ + /* Kaen uses UARTB for the debug port. */ + debug_uart_platform_data[0].membase = IO_ADDRESS(TEGRA_UARTB_BASE); + debug_uart_platform_data[0].mapbase = TEGRA_UARTB_BASE; + debug_uart_platform_data[0].irq = INT_UARTB; + + __tegra_seaboard_init(); +} + +static void __init tegra_wario_init(void) +{ + /* Wario uses UARTB for the debug port. */ + debug_uart_platform_data[0].membase = IO_ADDRESS(TEGRA_UARTB_BASE); + debug_uart_platform_data[0].mapbase = TEGRA_UARTB_BASE; + debug_uart_platform_data[0].irq = INT_UARTB; + + __tegra_seaboard_init(); +} + + +MACHINE_START(SEABOARD, "seaboard") + .boot_params = 0x00000100, + .map_io = tegra_map_common_io, + .init_early = tegra_init_early, + .init_irq = tegra_init_irq, + .timer = &tegra_timer, + .init_machine = tegra_seaboard_init, +MACHINE_END + +MACHINE_START(KAEN, "kaen") + .boot_params = 0x00000100, + .map_io = tegra_map_common_io, + .init_early = tegra_init_early, + .init_irq = tegra_init_irq, + .timer = &tegra_timer, + .init_machine = tegra_kaen_init, +MACHINE_END + +MACHINE_START(WARIO, "wario") + .boot_params = 0x00000100, + .map_io = tegra_map_common_io, + .init_early = tegra_init_early, + .init_irq = tegra_init_irq, + .timer = &tegra_timer, + .init_machine = tegra_wario_init, +MACHINE_END diff --git a/arch/arm/mach-tegra/board-seaboard.h b/arch/arm/mach-tegra/board-seaboard.h new file mode 100644 index 000000000000..a098e3599731 --- /dev/null +++ b/arch/arm/mach-tegra/board-seaboard.h @@ -0,0 +1,38 @@ +/* + * arch/arm/mach-tegra/board-seaboard.h + * + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _MACH_TEGRA_BOARD_SEABOARD_H +#define _MACH_TEGRA_BOARD_SEABOARD_H + +#define TEGRA_GPIO_LIDSWITCH TEGRA_GPIO_PC7 +#define TEGRA_GPIO_USB1 TEGRA_GPIO_PD0 +#define TEGRA_GPIO_POWERKEY TEGRA_GPIO_PV2 +#define TEGRA_GPIO_BACKLIGHT TEGRA_GPIO_PD4 +#define TEGRA_GPIO_LVDS_SHUTDOWN TEGRA_GPIO_PB2 +#define TEGRA_GPIO_BACKLIGHT_PWM TEGRA_GPIO_PU5 +#define TEGRA_GPIO_BACKLIGHT_VDD TEGRA_GPIO_PW0 +#define TEGRA_GPIO_EN_VDD_PNL TEGRA_GPIO_PC6 +#define TEGRA_GPIO_MAGNETOMETER TEGRA_GPIO_PN5 +#define TEGRA_GPIO_ISL29018_IRQ TEGRA_GPIO_PZ2 +#define TEGRA_GPIO_AC_ONLINE TEGRA_GPIO_PV3 + +#define TPS_GPIO_BASE TEGRA_NR_GPIOS + +#define TPS_GPIO_WWAN_PWR (TPS_GPIO_BASE + 2) + +void seaboard_pinmux_init(void); + +#endif diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c new file mode 100644 index 000000000000..6d4fc9f7f1fb --- /dev/null +++ b/arch/arm/mach-tegra/board-trimslice-pinmux.c @@ -0,0 +1,145 @@ +/* + * arch/arm/mach-tegra/board-trimslice-pinmux.c + * + * Copyright (C) 2011 CompuLab, Ltd. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <mach/pinmux.h> + +#include "board-trimslice.h" + +static __initdata struct tegra_pingroup_config trimslice_pinmux[] = { + {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_OSC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTE, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMB, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_GMC, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GME, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_GPU, TEGRA_MUX_UARTA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_PTA, TEGRA_MUX_RSVD3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPDI, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPDO, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIA, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIB, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIC, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, +}; + +void __init trimslice_pinmux_init(void) +{ + tegra_pinmux_config_table(trimslice_pinmux, ARRAY_SIZE(trimslice_pinmux)); +} diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c new file mode 100644 index 000000000000..7be7d4acd02f --- /dev/null +++ b/arch/arm/mach-tegra/board-trimslice.c @@ -0,0 +1,106 @@ +/* + * arch/arm/mach-tegra/board-trimslice.c + * + * Copyright (C) 2011 CompuLab, Ltd. + * Author: Mike Rapoport <mike@compulab.co.il> + * + * Based on board-harmony.c + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/serial_8250.h> +#include <linux/io.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/setup.h> + +#include <mach/iomap.h> + +#include "board.h" +#include "clock.h" + +#include "board-trimslice.h" + +static struct plat_serial8250_port debug_uart_platform_data[] = { + { + .membase = IO_ADDRESS(TEGRA_UARTA_BASE), + .mapbase = TEGRA_UARTA_BASE, + .irq = INT_UARTA, + .flags = UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = 216000000, + }, { + .flags = 0 + } +}; + +static struct platform_device debug_uart = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = debug_uart_platform_data, + }, +}; + +static struct platform_device *trimslice_devices[] __initdata = { + &debug_uart, +}; + +static void __init tegra_trimslice_fixup(struct machine_desc *desc, + struct tag *tags, char **cmdline, struct meminfo *mi) +{ + mi->nr_banks = 2; + mi->bank[0].start = PHYS_OFFSET; + mi->bank[0].size = 448 * SZ_1M; + mi->bank[1].start = SZ_512M; + mi->bank[1].size = SZ_512M; +} + +static __initdata struct tegra_clk_init_table trimslice_clk_init_table[] = { + /* name parent rate enabled */ + { "uarta", "pll_p", 216000000, true }, + { NULL, NULL, 0, 0}, +}; + +static int __init tegra_trimslice_pci_init(void) +{ + if (!machine_is_trimslice()) + return 0; + + return tegra_pcie_init(true, true); +} +subsys_initcall(tegra_trimslice_pci_init); + +static void __init tegra_trimslice_init(void) +{ + tegra_clk_init_from_table(trimslice_clk_init_table); + + trimslice_pinmux_init(); + + platform_add_devices(trimslice_devices, ARRAY_SIZE(trimslice_devices)); +} + +MACHINE_START(TRIMSLICE, "trimslice") + .boot_params = 0x00000100, + .fixup = tegra_trimslice_fixup, + .map_io = tegra_map_common_io, + .init_early = tegra_init_early, + .init_irq = tegra_init_irq, + .timer = &tegra_timer, + .init_machine = tegra_trimslice_init, +MACHINE_END diff --git a/arch/arm/mach-tegra/board-trimslice.h b/arch/arm/mach-tegra/board-trimslice.h new file mode 100644 index 000000000000..16ec0f0d3bb1 --- /dev/null +++ b/arch/arm/mach-tegra/board-trimslice.h @@ -0,0 +1,22 @@ +/* + * arch/arm/mach-tegra/board-trimslice.h + * + * Copyright (C) 2011 CompuLab, Ltd. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _MACH_TEGRA_BOARD_TRIMSLICE_H +#define _MACH_TEGRA_BOARD_TRIMSLICE_H + +void trimslice_pinmux_init(void); + +#endif diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h index 0de565ca37c5..1d14df7eb7de 100644 --- a/arch/arm/mach-tegra/board.h +++ b/arch/arm/mach-tegra/board.h @@ -23,7 +23,9 @@ #include <linux/types.h> -void __init tegra_common_init(void); +void tegra_assert_system_reset(char mode, const char *cmd); + +void __init tegra_init_early(void); void __init tegra_map_common_io(void); void __init tegra_init_irq(void); void __init tegra_init_clock(void); diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 77948e0f4909..e028320ab423 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -18,238 +18,177 @@ #include <linux/kernel.h> #include <linux/clk.h> -#include <linux/list.h> +#include <linux/clkdev.h> +#include <linux/debugfs.h> +#include <linux/delay.h> #include <linux/init.h> +#include <linux/list.h> #include <linux/module.h> -#include <linux/debugfs.h> -#include <linux/slab.h> +#include <linux/sched.h> #include <linux/seq_file.h> -#include <linux/regulator/consumer.h> -#include <linux/clkdev.h> +#include <linux/slab.h> + +#include <mach/clk.h> -#include "clock.h" #include "board.h" -#include "fuse.h" +#include "clock.h" +/* + * Locking: + * + * Each struct clk has a spinlock. + * + * To avoid AB-BA locking problems, locks must always be traversed from child + * clock to parent clock. For example, when enabling a clock, the clock's lock + * is taken, and then clk_enable is called on the parent, which take's the + * parent clock's lock. There is one exceptions to this ordering: When dumping + * the clock tree through debugfs. In this case, clk_lock_all is called, + * which attemps to iterate through the entire list of clocks and take every + * clock lock. If any call to spin_trylock fails, all locked clocks are + * unlocked, and the process is retried. When all the locks are held, + * the only clock operation that can be called is clk_get_rate_all_locked. + * + * Within a single clock, no clock operation can call another clock operation + * on itself, except for clk_get_rate_locked and clk_set_rate_locked. Any + * clock operation can call any other clock operation on any of it's possible + * parents. + * + * An additional mutex, clock_list_lock, is used to protect the list of all + * clocks. + * + * The clock operations must lock internally to protect against + * read-modify-write on registers that are shared by multiple clocks + */ +static DEFINE_MUTEX(clock_list_lock); static LIST_HEAD(clocks); -static DEFINE_SPINLOCK(clock_lock); -static DEFINE_MUTEX(dvfs_lock); - -static int clk_is_dvfs(struct clk *c) -{ - return (c->dvfs != NULL); -}; - -static int dvfs_set_rate(struct dvfs *d, unsigned long rate) -{ - struct dvfs_table *t; - - if (d->table == NULL) - return -ENODEV; - - for (t = d->table; t->rate != 0; t++) { - if (rate <= t->rate) { - if (!d->reg) - return 0; - - return regulator_set_voltage(d->reg, - t->millivolts * 1000, - d->max_millivolts * 1000); - } - } - - return -EINVAL; -} - -static void dvfs_init(struct clk *c) -{ - int process_id; - int i; - struct dvfs_table *table; - - process_id = c->dvfs->cpu ? tegra_core_process_id() : - tegra_cpu_process_id(); - - for (i = 0; i < c->dvfs->process_id_table_length; i++) - if (process_id == c->dvfs->process_id_table[i].process_id) - c->dvfs->table = c->dvfs->process_id_table[i].table; - - if (c->dvfs->table == NULL) { - pr_err("Failed to find dvfs table for clock %s process %d\n", - c->name, process_id); - return; - } - - c->dvfs->max_millivolts = 0; - for (table = c->dvfs->table; table->rate != 0; table++) - if (c->dvfs->max_millivolts < table->millivolts) - c->dvfs->max_millivolts = table->millivolts; - - c->dvfs->reg = regulator_get(NULL, c->dvfs->reg_id); - - if (IS_ERR(c->dvfs->reg)) { - pr_err("Failed to get regulator %s for clock %s\n", - c->dvfs->reg_id, c->name); - c->dvfs->reg = NULL; - return; - } - - if (c->refcnt > 0) - dvfs_set_rate(c->dvfs, c->rate); -} - struct clk *tegra_get_clock_by_name(const char *name) { struct clk *c; struct clk *ret = NULL; - unsigned long flags; - spin_lock_irqsave(&clock_lock, flags); + mutex_lock(&clock_list_lock); list_for_each_entry(c, &clocks, node) { if (strcmp(c->name, name) == 0) { ret = c; break; } } - spin_unlock_irqrestore(&clock_lock, flags); + mutex_unlock(&clock_list_lock); return ret; } -static void clk_recalculate_rate(struct clk *c) +/* Must be called with c->spinlock held */ +static unsigned long clk_predict_rate_from_parent(struct clk *c, struct clk *p) { u64 rate; - if (!c->parent) - return; - - rate = c->parent->rate; + rate = clk_get_rate(p); if (c->mul != 0 && c->div != 0) { - rate = rate * c->mul; + rate *= c->mul; + rate += c->div - 1; /* round up */ do_div(rate, c->div); } - if (rate > c->max_rate) - pr_warn("clocks: Set clock %s to rate %llu, max is %lu\n", - c->name, rate, c->max_rate); - - c->rate = rate; + return rate; } -int clk_reparent(struct clk *c, struct clk *parent) +/* Must be called with c->spinlock held */ +unsigned long clk_get_rate_locked(struct clk *c) { - pr_debug("%s: %s\n", __func__, c->name); - c->parent = parent; - list_del(&c->sibling); - list_add_tail(&c->sibling, &parent->children); - return 0; -} + unsigned long rate; -static void propagate_rate(struct clk *c) -{ - struct clk *clkp; - pr_debug("%s: %s\n", __func__, c->name); - list_for_each_entry(clkp, &c->children, sibling) { - pr_debug(" %s\n", clkp->name); - clk_recalculate_rate(clkp); - propagate_rate(clkp); - } + if (c->parent) + rate = clk_predict_rate_from_parent(c, c->parent); + else + rate = c->rate; + + return rate; } -void clk_init(struct clk *c) +unsigned long clk_get_rate(struct clk *c) { unsigned long flags; + unsigned long rate; + + spin_lock_irqsave(&c->spinlock, flags); - pr_debug("%s: %s\n", __func__, c->name); + rate = clk_get_rate_locked(c); - spin_lock_irqsave(&clock_lock, flags); + spin_unlock_irqrestore(&c->spinlock, flags); - INIT_LIST_HEAD(&c->children); - INIT_LIST_HEAD(&c->sibling); + return rate; +} +EXPORT_SYMBOL(clk_get_rate); + +int clk_reparent(struct clk *c, struct clk *parent) +{ + c->parent = parent; + return 0; +} + +void clk_init(struct clk *c) +{ + spin_lock_init(&c->spinlock); if (c->ops && c->ops->init) c->ops->init(c); - clk_recalculate_rate(c); + if (!c->ops || !c->ops->enable) { + c->refcnt++; + c->set = true; + if (c->parent) + c->state = c->parent->state; + else + c->state = ON; + } + mutex_lock(&clock_list_lock); list_add(&c->node, &clocks); - - if (c->parent) - list_add_tail(&c->sibling, &c->parent->children); - - spin_unlock_irqrestore(&clock_lock, flags); + mutex_unlock(&clock_list_lock); } -int clk_enable_locked(struct clk *c) +int clk_enable(struct clk *c) { - int ret; - pr_debug("%s: %s\n", __func__, c->name); + int ret = 0; + unsigned long flags; + + spin_lock_irqsave(&c->spinlock, flags); + if (c->refcnt == 0) { if (c->parent) { - ret = clk_enable_locked(c->parent); + ret = clk_enable(c->parent); if (ret) - return ret; + goto out; } if (c->ops && c->ops->enable) { ret = c->ops->enable(c); if (ret) { if (c->parent) - clk_disable_locked(c->parent); - return ret; + clk_disable(c->parent); + goto out; } c->state = ON; -#ifdef CONFIG_DEBUG_FS - c->set = 1; -#endif + c->set = true; } } c->refcnt++; - - return 0; -} - -int clk_enable_cansleep(struct clk *c) -{ - int ret; - unsigned long flags; - - mutex_lock(&dvfs_lock); - - if (clk_is_dvfs(c) && c->refcnt > 0) - dvfs_set_rate(c->dvfs, c->rate); - - spin_lock_irqsave(&clock_lock, flags); - ret = clk_enable_locked(c); - spin_unlock_irqrestore(&clock_lock, flags); - - mutex_unlock(&dvfs_lock); - +out: + spin_unlock_irqrestore(&c->spinlock, flags); return ret; } -EXPORT_SYMBOL(clk_enable_cansleep); +EXPORT_SYMBOL(clk_enable); -int clk_enable(struct clk *c) +void clk_disable(struct clk *c) { - int ret; unsigned long flags; - if (clk_is_dvfs(c)) - BUG(); - - spin_lock_irqsave(&clock_lock, flags); - ret = clk_enable_locked(c); - spin_unlock_irqrestore(&clock_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_enable); + spin_lock_irqsave(&c->spinlock, flags); -void clk_disable_locked(struct clk *c) -{ - pr_debug("%s: %s\n", __func__, c->name); if (c->refcnt == 0) { WARN(1, "Attempting to disable clock %s with refcnt 0", c->name); + spin_unlock_irqrestore(&c->spinlock, flags); return; } if (c->refcnt == 1) { @@ -257,71 +196,39 @@ void clk_disable_locked(struct clk *c) c->ops->disable(c); if (c->parent) - clk_disable_locked(c->parent); + clk_disable(c->parent); c->state = OFF; } c->refcnt--; -} - -void clk_disable_cansleep(struct clk *c) -{ - unsigned long flags; - - mutex_lock(&dvfs_lock); - - spin_lock_irqsave(&clock_lock, flags); - clk_disable_locked(c); - spin_unlock_irqrestore(&clock_lock, flags); - if (clk_is_dvfs(c) && c->refcnt == 0) - dvfs_set_rate(c->dvfs, c->rate); - - mutex_unlock(&dvfs_lock); -} -EXPORT_SYMBOL(clk_disable_cansleep); - -void clk_disable(struct clk *c) -{ - unsigned long flags; - - if (clk_is_dvfs(c)) - BUG(); - - spin_lock_irqsave(&clock_lock, flags); - clk_disable_locked(c); - spin_unlock_irqrestore(&clock_lock, flags); + spin_unlock_irqrestore(&c->spinlock, flags); } EXPORT_SYMBOL(clk_disable); -int clk_set_parent_locked(struct clk *c, struct clk *parent) +int clk_set_parent(struct clk *c, struct clk *parent) { int ret; + unsigned long flags; + unsigned long new_rate; + unsigned long old_rate; - pr_debug("%s: %s\n", __func__, c->name); + spin_lock_irqsave(&c->spinlock, flags); - if (!c->ops || !c->ops->set_parent) - return -ENOSYS; + if (!c->ops || !c->ops->set_parent) { + ret = -ENOSYS; + goto out; + } - ret = c->ops->set_parent(c, parent); + new_rate = clk_predict_rate_from_parent(c, parent); + old_rate = clk_get_rate_locked(c); + ret = c->ops->set_parent(c, parent); if (ret) - return ret; - - clk_recalculate_rate(c); - - propagate_rate(c); - - return 0; -} + goto out; -int clk_set_parent(struct clk *c, struct clk *parent) -{ - int ret; - unsigned long flags; - spin_lock_irqsave(&clock_lock, flags); - ret = clk_set_parent_locked(c, parent); - spin_unlock_irqrestore(&clock_lock, flags); +out: + spin_unlock_irqrestore(&c->spinlock, flags); return ret; } EXPORT_SYMBOL(clk_set_parent); @@ -334,100 +241,86 @@ EXPORT_SYMBOL(clk_get_parent); int clk_set_rate_locked(struct clk *c, unsigned long rate) { - int ret; - - if (rate > c->max_rate) - rate = c->max_rate; + long new_rate; if (!c->ops || !c->ops->set_rate) return -ENOSYS; - ret = c->ops->set_rate(c, rate); - - if (ret) - return ret; - - clk_recalculate_rate(c); - - propagate_rate(c); - - return 0; -} - -int clk_set_rate_cansleep(struct clk *c, unsigned long rate) -{ - int ret = 0; - unsigned long flags; - - pr_debug("%s: %s\n", __func__, c->name); - - mutex_lock(&dvfs_lock); - - if (rate > c->rate) - ret = dvfs_set_rate(c->dvfs, rate); - if (ret) - goto out; + if (rate > c->max_rate) + rate = c->max_rate; - spin_lock_irqsave(&clock_lock, flags); - ret = clk_set_rate_locked(c, rate); - spin_unlock_irqrestore(&clock_lock, flags); + if (c->ops && c->ops->round_rate) { + new_rate = c->ops->round_rate(c, rate); - if (ret) - goto out; + if (new_rate < 0) + return new_rate; - ret = dvfs_set_rate(c->dvfs, rate); + rate = new_rate; + } -out: - mutex_unlock(&dvfs_lock); - return ret; + return c->ops->set_rate(c, rate); } -EXPORT_SYMBOL(clk_set_rate_cansleep); int clk_set_rate(struct clk *c, unsigned long rate) { - int ret = 0; + int ret; unsigned long flags; - pr_debug("%s: %s\n", __func__, c->name); - - if (clk_is_dvfs(c)) - BUG(); + spin_lock_irqsave(&c->spinlock, flags); - spin_lock_irqsave(&clock_lock, flags); ret = clk_set_rate_locked(c, rate); - spin_unlock_irqrestore(&clock_lock, flags); + + spin_unlock_irqrestore(&c->spinlock, flags); return ret; } EXPORT_SYMBOL(clk_set_rate); -unsigned long clk_get_rate(struct clk *c) -{ - unsigned long flags; - unsigned long ret; - - spin_lock_irqsave(&clock_lock, flags); - pr_debug("%s: %s\n", __func__, c->name); +/* Must be called with clocks lock and all indvidual clock locks held */ +unsigned long clk_get_rate_all_locked(struct clk *c) +{ + u64 rate; + int mul = 1; + int div = 1; + struct clk *p = c; + + while (p) { + c = p; + if (c->mul != 0 && c->div != 0) { + mul *= c->mul; + div *= c->div; + } + p = c->parent; + } - ret = c->rate; + rate = c->rate; + rate *= mul; + do_div(rate, div); - spin_unlock_irqrestore(&clock_lock, flags); - return ret; + return rate; } -EXPORT_SYMBOL(clk_get_rate); long clk_round_rate(struct clk *c, unsigned long rate) { - pr_debug("%s: %s\n", __func__, c->name); + unsigned long flags; + long ret; - if (!c->ops || !c->ops->round_rate) - return -ENOSYS; + spin_lock_irqsave(&c->spinlock, flags); + + if (!c->ops || !c->ops->round_rate) { + ret = -ENOSYS; + goto out; + } if (rate > c->max_rate) rate = c->max_rate; - return c->ops->round_rate(c, rate); + ret = c->ops->round_rate(c, rate); + +out: + spin_unlock_irqrestore(&c->spinlock, flags); + return ret; } EXPORT_SYMBOL(clk_round_rate); @@ -509,31 +402,90 @@ void __init tegra_init_clock(void) tegra2_init_clocks(); } -int __init tegra_init_dvfs(void) +/* + * The SDMMC controllers have extra bits in the clock source register that + * adjust the delay between the clock and data to compenstate for delays + * on the PCB. + */ +void tegra_sdmmc_tap_delay(struct clk *c, int delay) { - struct clk *c, *safe; + unsigned long flags; + + spin_lock_irqsave(&c->spinlock, flags); + tegra2_sdmmc_tap_delay(c, delay); + spin_unlock_irqrestore(&c->spinlock, flags); +} - mutex_lock(&dvfs_lock); +#ifdef CONFIG_DEBUG_FS - list_for_each_entry_safe(c, safe, &clocks, node) - if (c->dvfs) - dvfs_init(c); +static int __clk_lock_all_spinlocks(void) +{ + struct clk *c; - mutex_unlock(&dvfs_lock); + list_for_each_entry(c, &clocks, node) + if (!spin_trylock(&c->spinlock)) + goto unlock_spinlocks; return 0; + +unlock_spinlocks: + list_for_each_entry_continue_reverse(c, &clocks, node) + spin_unlock(&c->spinlock); + + return -EAGAIN; } -late_initcall(tegra_init_dvfs); +static void __clk_unlock_all_spinlocks(void) +{ + struct clk *c; + + list_for_each_entry_reverse(c, &clocks, node) + spin_unlock(&c->spinlock); +} + +/* + * This function retries until it can take all locks, and may take + * an arbitrarily long time to complete. + * Must be called with irqs enabled, returns with irqs disabled + * Must be called with clock_list_lock held + */ +static void clk_lock_all(void) +{ + int ret; +retry: + local_irq_disable(); + + ret = __clk_lock_all_spinlocks(); + if (ret) + goto failed_spinlocks; + + /* All locks taken successfully, return */ + return; + +failed_spinlocks: + local_irq_enable(); + yield(); + goto retry; +} + +/* + * Unlocks all clocks after a clk_lock_all + * Must be called with irqs disabled, returns with irqs enabled + * Must be called with clock_list_lock held + */ +static void clk_unlock_all(void) +{ + __clk_unlock_all_spinlocks(); + + local_irq_enable(); +} -#ifdef CONFIG_DEBUG_FS static struct dentry *clk_debugfs_root; static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level) { struct clk *child; - struct clk *safe; const char *state = "uninit"; char div[8] = {0}; @@ -564,8 +516,12 @@ static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level) c->rate > c->max_rate ? '!' : ' ', !c->set ? '*' : ' ', 30 - level * 3, c->name, - state, c->refcnt, div, c->rate); - list_for_each_entry_safe(child, safe, &c->children, sibling) { + state, c->refcnt, div, clk_get_rate_all_locked(c)); + + list_for_each_entry(child, &clocks, node) { + if (child->parent != c) + continue; + clock_tree_show_one(s, child, level + 1); } } @@ -573,14 +529,20 @@ static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level) static int clock_tree_show(struct seq_file *s, void *data) { struct clk *c; - unsigned long flags; seq_printf(s, " clock state ref div rate\n"); seq_printf(s, "--------------------------------------------------------------\n"); - spin_lock_irqsave(&clock_lock, flags); + + mutex_lock(&clock_list_lock); + + clk_lock_all(); + list_for_each_entry(c, &clocks, node) if (c->parent == NULL) clock_tree_show_one(s, c, 0); - spin_unlock_irqrestore(&clock_lock, flags); + + clk_unlock_all(); + + mutex_unlock(&clock_list_lock); return 0; } diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h index 083a4cfc6cf0..688316abc64e 100644 --- a/arch/arm/mach-tegra/clock.h +++ b/arch/arm/mach-tegra/clock.h @@ -20,8 +20,9 @@ #ifndef __MACH_TEGRA_CLOCK_H #define __MACH_TEGRA_CLOCK_H -#include <linux/list.h> #include <linux/clkdev.h> +#include <linux/list.h> +#include <linux/spinlock.h> #define DIV_BUS (1 << 0) #define DIV_U71 (1 << 1) @@ -41,36 +42,13 @@ #define ENABLE_ON_INIT (1 << 28) struct clk; -struct regulator; - -struct dvfs_table { - unsigned long rate; - int millivolts; -}; - -struct dvfs_process_id_table { - int process_id; - struct dvfs_table *table; -}; - - -struct dvfs { - struct regulator *reg; - struct dvfs_table *table; - int max_millivolts; - - int process_id_table_length; - const char *reg_id; - bool cpu; - struct dvfs_process_id_table process_id_table[]; -}; struct clk_mux_sel { struct clk *input; u32 value; }; -struct clk_pll_table { +struct clk_pll_freq_table { unsigned long input_rate; unsigned long output_rate; u16 n; @@ -86,6 +64,7 @@ struct clk_ops { int (*set_parent)(struct clk *, struct clk *); int (*set_rate)(struct clk *, unsigned long); long (*round_rate)(struct clk *, unsigned long); + void (*reset)(struct clk *, bool); }; enum clk_state { @@ -96,55 +75,64 @@ enum clk_state { struct clk { /* node for master clocks list */ - struct list_head node; - struct list_head children; /* list of children */ - struct list_head sibling; /* node for children */ -#ifdef CONFIG_DEBUG_FS - struct dentry *dent; - struct dentry *parent_dent; -#endif - struct clk_ops *ops; - struct clk *parent; - struct clk_lookup lookup; - unsigned long rate; - unsigned long max_rate; - u32 flags; - u32 refcnt; - const char *name; - u32 reg; - u32 reg_shift; - unsigned int clk_num; - enum clk_state state; + struct list_head node; /* node for list of all clocks */ + struct clk_lookup lookup; + #ifdef CONFIG_DEBUG_FS - bool set; + struct dentry *dent; #endif + bool set; + struct clk_ops *ops; + unsigned long rate; + unsigned long max_rate; + unsigned long min_rate; + u32 flags; + const char *name; + + u32 refcnt; + enum clk_state state; + struct clk *parent; + u32 div; + u32 mul; - /* PLL */ - unsigned long input_min; - unsigned long input_max; - unsigned long cf_min; - unsigned long cf_max; - unsigned long vco_min; - unsigned long vco_max; - const struct clk_pll_table *pll_table; - - /* DIV */ - u32 div; - u32 mul; - - /* MUX */ const struct clk_mux_sel *inputs; - u32 sel; - u32 reg_mask; - - /* Virtual cpu clock */ - struct clk *main; - struct clk *backup; + u32 reg; + u32 reg_shift; - struct dvfs *dvfs; + struct list_head shared_bus_list; + + union { + struct { + unsigned int clk_num; + } periph; + struct { + unsigned long input_min; + unsigned long input_max; + unsigned long cf_min; + unsigned long cf_max; + unsigned long vco_min; + unsigned long vco_max; + const struct clk_pll_freq_table *freq_table; + int lock_delay; + } pll; + struct { + u32 sel; + u32 reg_mask; + } mux; + struct { + struct clk *main; + struct clk *backup; + } cpu; + struct { + struct list_head node; + bool enabled; + unsigned long rate; + } shared_bus_user; + } u; + + spinlock_t spinlock; }; - struct clk_duplicate { const char *name; struct clk_lookup lookup; @@ -163,11 +151,10 @@ void tegra2_periph_reset_assert(struct clk *c); void clk_init(struct clk *clk); struct clk *tegra_get_clock_by_name(const char *name); unsigned long clk_measure_input_freq(void); -void clk_disable_locked(struct clk *c); -int clk_enable_locked(struct clk *c); -int clk_set_parent_locked(struct clk *c, struct clk *parent); -int clk_set_rate_locked(struct clk *c, unsigned long rate); int clk_reparent(struct clk *c, struct clk *parent); void tegra_clk_init_from_table(struct tegra_clk_init_table *table); +unsigned long clk_get_rate_locked(struct clk *c); +int clk_set_rate_locked(struct clk *c, unsigned long rate); +void tegra2_sdmmc_tap_delay(struct clk *c, int delay); #endif diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 7c91e2b9d643..d5e3f89b05af 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -25,12 +25,25 @@ #include <asm/hardware/cache-l2x0.h> #include <mach/iomap.h> -#include <mach/dma.h> +#include <mach/system.h> #include "board.h" #include "clock.h" #include "fuse.h" +void (*arch_reset)(char mode, const char *cmd) = tegra_assert_system_reset; + +void tegra_assert_system_reset(char mode, const char *cmd) +{ + void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04); + u32 reg; + + /* use *_related to avoid spinlock since caches are off */ + reg = readl_relaxed(reset); + reg |= 0x04; + writel_relaxed(reg, reset); +} + static __initdata struct tegra_clk_init_table common_clk_init_table[] = { /* name parent rate enabled */ { "clk_m", NULL, 0, true }, @@ -42,6 +55,9 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { { "sclk", "pll_p_out4", 108000000, true }, { "hclk", "sclk", 108000000, true }, { "pclk", "hclk", 54000000, true }, + { "csite", NULL, 0, true }, + { "emc", NULL, 0, true }, + { "cpu", NULL, 0, true }, { NULL, NULL, 0, 0}, }; @@ -50,21 +66,18 @@ void __init tegra_init_cache(void) #ifdef CONFIG_CACHE_L2X0 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; - writel(0x331, p + L2X0_TAG_LATENCY_CTRL); - writel(0x441, p + L2X0_DATA_LATENCY_CTRL); + writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL); + writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL); l2x0_init(p, 0x6C080001, 0x8200c3fe); #endif } -void __init tegra_common_init(void) +void __init tegra_init_early(void) { tegra_init_fuse(); tegra_init_clock(); tegra_clk_init_from_table(common_clk_init_table); tegra_init_cache(); -#ifdef CONFIG_TEGRA_SYSTEM_DMA - tegra_dma_init(); -#endif } diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c index fea5719c7072..0e1016a827ac 100644 --- a/arch/arm/mach-tegra/cpu-tegra.c +++ b/arch/arm/mach-tegra/cpu-tegra.c @@ -28,6 +28,7 @@ #include <linux/err.h> #include <linux/clk.h> #include <linux/io.h> +#include <linux/suspend.h> #include <asm/system.h> @@ -36,21 +37,25 @@ /* Frequency table index must be sequential starting at 0 */ static struct cpufreq_frequency_table freq_table[] = { - { 0, 312000 }, - { 1, 456000 }, - { 2, 608000 }, - { 3, 760000 }, - { 4, 816000 }, - { 5, 912000 }, - { 6, 1000000 }, - { 7, CPUFREQ_TABLE_END }, + { 0, 216000 }, + { 1, 312000 }, + { 2, 456000 }, + { 3, 608000 }, + { 4, 760000 }, + { 5, 816000 }, + { 6, 912000 }, + { 7, 1000000 }, + { 8, CPUFREQ_TABLE_END }, }; #define NUM_CPUS 2 static struct clk *cpu_clk; +static struct clk *emc_clk; static unsigned long target_cpu_speed[NUM_CPUS]; +static DEFINE_MUTEX(tegra_cpu_lock); +static bool is_suspended; int tegra_verify_speed(struct cpufreq_policy *policy) { @@ -68,22 +73,28 @@ unsigned int tegra_getspeed(unsigned int cpu) return rate; } -static int tegra_update_cpu_speed(void) +static int tegra_update_cpu_speed(unsigned long rate) { - int i; - unsigned long rate = 0; int ret = 0; struct cpufreq_freqs freqs; - for_each_online_cpu(i) - rate = max(rate, target_cpu_speed[i]); - freqs.old = tegra_getspeed(0); freqs.new = rate; if (freqs.old == freqs.new) return ret; + /* + * Vote on memory bus frequency based on cpu frequency + * This sets the minimum frequency, display or avp may request higher + */ + if (rate >= 816000) + clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */ + else if (rate >= 456000) + clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */ + else + clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */ + for_each_online_cpu(freqs.cpu) cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); @@ -92,7 +103,7 @@ static int tegra_update_cpu_speed(void) freqs.old, freqs.new); #endif - ret = clk_set_rate_cansleep(cpu_clk, freqs.new * 1000); + ret = clk_set_rate(cpu_clk, freqs.new * 1000); if (ret) { pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n", freqs.new); @@ -105,12 +116,30 @@ static int tegra_update_cpu_speed(void) return 0; } +static unsigned long tegra_cpu_highest_speed(void) +{ + unsigned long rate = 0; + int i; + + for_each_online_cpu(i) + rate = max(rate, target_cpu_speed[i]); + return rate; +} + static int tegra_target(struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation) { int idx; unsigned int freq; + int ret = 0; + + mutex_lock(&tegra_cpu_lock); + + if (is_suspended) { + ret = -EBUSY; + goto out; + } cpufreq_frequency_table_target(policy, freq_table, target_freq, relation, &idx); @@ -119,9 +148,34 @@ static int tegra_target(struct cpufreq_policy *policy, target_cpu_speed[policy->cpu] = freq; - return tegra_update_cpu_speed(); + ret = tegra_update_cpu_speed(tegra_cpu_highest_speed()); + +out: + mutex_unlock(&tegra_cpu_lock); + return ret; } +static int tegra_pm_notify(struct notifier_block *nb, unsigned long event, + void *dummy) +{ + mutex_lock(&tegra_cpu_lock); + if (event == PM_SUSPEND_PREPARE) { + is_suspended = true; + pr_info("Tegra cpufreq suspend: setting frequency to %d kHz\n", + freq_table[0].frequency); + tegra_update_cpu_speed(freq_table[0].frequency); + } else if (event == PM_POST_SUSPEND) { + is_suspended = false; + } + mutex_unlock(&tegra_cpu_lock); + + return NOTIFY_OK; +} + +static struct notifier_block tegra_cpu_pm_notifier = { + .notifier_call = tegra_pm_notify, +}; + static int tegra_cpu_init(struct cpufreq_policy *policy) { if (policy->cpu >= NUM_CPUS) @@ -131,6 +185,15 @@ static int tegra_cpu_init(struct cpufreq_policy *policy) if (IS_ERR(cpu_clk)) return PTR_ERR(cpu_clk); + emc_clk = clk_get_sys("cpu", "emc"); + if (IS_ERR(emc_clk)) { + clk_put(cpu_clk); + return PTR_ERR(emc_clk); + } + + clk_enable(emc_clk); + clk_enable(cpu_clk); + cpufreq_frequency_table_cpuinfo(policy, freq_table); cpufreq_frequency_table_get_attr(freq_table, policy->cpu); policy->cur = tegra_getspeed(policy->cpu); @@ -142,12 +205,17 @@ static int tegra_cpu_init(struct cpufreq_policy *policy) policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; cpumask_copy(policy->related_cpus, cpu_possible_mask); + if (policy->cpu == 0) + register_pm_notifier(&tegra_cpu_pm_notifier); + return 0; } static int tegra_cpu_exit(struct cpufreq_policy *policy) { cpufreq_frequency_table_cpuinfo(policy, freq_table); + clk_disable(emc_clk); + clk_put(emc_clk); clk_put(cpu_clk); return 0; } diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c new file mode 100644 index 000000000000..682e6d33108c --- /dev/null +++ b/arch/arm/mach-tegra/devices.c @@ -0,0 +1,505 @@ +/* + * Copyright (C) 2010,2011 Google, Inc. + * + * Author: + * Colin Cross <ccross@android.com> + * Erik Gilling <ccross@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + + +#include <linux/resource.h> +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> +#include <linux/fsl_devices.h> +#include <linux/serial_8250.h> +#include <asm/pmu.h> +#include <mach/irqs.h> +#include <mach/iomap.h> +#include <mach/dma.h> + +static struct resource i2c_resource1[] = { + [0] = { + .start = INT_I2C, + .end = INT_I2C, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = TEGRA_I2C_BASE, + .end = TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource i2c_resource2[] = { + [0] = { + .start = INT_I2C2, + .end = INT_I2C2, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = TEGRA_I2C2_BASE, + .end = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource i2c_resource3[] = { + [0] = { + .start = INT_I2C3, + .end = INT_I2C3, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = TEGRA_I2C3_BASE, + .end = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource i2c_resource4[] = { + [0] = { + .start = INT_DVC, + .end = INT_DVC, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = TEGRA_DVC_BASE, + .end = TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device tegra_i2c_device1 = { + .name = "tegra-i2c", + .id = 0, + .resource = i2c_resource1, + .num_resources = ARRAY_SIZE(i2c_resource1), + .dev = { + .platform_data = 0, + }, +}; + +struct platform_device tegra_i2c_device2 = { + .name = "tegra-i2c", + .id = 1, + .resource = i2c_resource2, + .num_resources = ARRAY_SIZE(i2c_resource2), + .dev = { + .platform_data = 0, + }, +}; + +struct platform_device tegra_i2c_device3 = { + .name = "tegra-i2c", + .id = 2, + .resource = i2c_resource3, + .num_resources = ARRAY_SIZE(i2c_resource3), + .dev = { + .platform_data = 0, + }, +}; + +struct platform_device tegra_i2c_device4 = { + .name = "tegra-i2c", + .id = 3, + .resource = i2c_resource4, + .num_resources = ARRAY_SIZE(i2c_resource4), + .dev = { + .platform_data = 0, + }, +}; + +static struct resource spi_resource1[] = { + [0] = { + .start = INT_S_LINK1, + .end = INT_S_LINK1, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = TEGRA_SPI1_BASE, + .end = TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource spi_resource2[] = { + [0] = { + .start = INT_SPI_2, + .end = INT_SPI_2, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = TEGRA_SPI2_BASE, + .end = TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource spi_resource3[] = { + [0] = { + .start = INT_SPI_3, + .end = INT_SPI_3, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = TEGRA_SPI3_BASE, + .end = TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource spi_resource4[] = { + [0] = { + .start = INT_SPI_4, + .end = INT_SPI_4, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = TEGRA_SPI4_BASE, + .end = TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device tegra_spi_device1 = { + .name = "spi_tegra", + .id = 0, + .resource = spi_resource1, + .num_resources = ARRAY_SIZE(spi_resource1), + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +struct platform_device tegra_spi_device2 = { + .name = "spi_tegra", + .id = 1, + .resource = spi_resource2, + .num_resources = ARRAY_SIZE(spi_resource2), + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +struct platform_device tegra_spi_device3 = { + .name = "spi_tegra", + .id = 2, + .resource = spi_resource3, + .num_resources = ARRAY_SIZE(spi_resource3), + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +struct platform_device tegra_spi_device4 = { + .name = "spi_tegra", + .id = 3, + .resource = spi_resource4, + .num_resources = ARRAY_SIZE(spi_resource4), + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + + +static struct resource sdhci_resource1[] = { + [0] = { + .start = INT_SDMMC1, + .end = INT_SDMMC1, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = TEGRA_SDMMC1_BASE, + .end = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource sdhci_resource2[] = { + [0] = { + .start = INT_SDMMC2, + .end = INT_SDMMC2, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = TEGRA_SDMMC2_BASE, + .end = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource sdhci_resource3[] = { + [0] = { + .start = INT_SDMMC3, + .end = INT_SDMMC3, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = TEGRA_SDMMC3_BASE, + .end = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource sdhci_resource4[] = { + [0] = { + .start = INT_SDMMC4, + .end = INT_SDMMC4, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = TEGRA_SDMMC4_BASE, + .end = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1, + .flags = IORESOURCE_MEM, + }, +}; + +/* board files should fill in platform_data register the devices themselvs. + * See board-harmony.c for an example + */ +struct platform_device tegra_sdhci_device1 = { + .name = "sdhci-tegra", + .id = 0, + .resource = sdhci_resource1, + .num_resources = ARRAY_SIZE(sdhci_resource1), +}; + +struct platform_device tegra_sdhci_device2 = { + .name = "sdhci-tegra", + .id = 1, + .resource = sdhci_resource2, + .num_resources = ARRAY_SIZE(sdhci_resource2), +}; + +struct platform_device tegra_sdhci_device3 = { + .name = "sdhci-tegra", + .id = 2, + .resource = sdhci_resource3, + .num_resources = ARRAY_SIZE(sdhci_resource3), +}; + +struct platform_device tegra_sdhci_device4 = { + .name = "sdhci-tegra", + .id = 3, + .resource = sdhci_resource4, + .num_resources = ARRAY_SIZE(sdhci_resource4), +}; + +static struct resource tegra_usb1_resources[] = { + [0] = { + .start = TEGRA_USB_BASE, + .end = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_USB, + .end = INT_USB, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource tegra_usb2_resources[] = { + [0] = { + .start = TEGRA_USB2_BASE, + .end = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_USB2, + .end = INT_USB2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource tegra_usb3_resources[] = { + [0] = { + .start = TEGRA_USB3_BASE, + .end = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_USB3, + .end = INT_USB3, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32); + +struct platform_device tegra_ehci1_device = { + .name = "tegra-ehci", + .id = 0, + .dev = { + .dma_mask = &tegra_ehci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = tegra_usb1_resources, + .num_resources = ARRAY_SIZE(tegra_usb1_resources), +}; + +struct platform_device tegra_ehci2_device = { + .name = "tegra-ehci", + .id = 1, + .dev = { + .dma_mask = &tegra_ehci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = tegra_usb2_resources, + .num_resources = ARRAY_SIZE(tegra_usb2_resources), +}; + +struct platform_device tegra_ehci3_device = { + .name = "tegra-ehci", + .id = 2, + .dev = { + .dma_mask = &tegra_ehci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = tegra_usb3_resources, + .num_resources = ARRAY_SIZE(tegra_usb3_resources), +}; + +static struct resource tegra_pmu_resources[] = { + [0] = { + .start = INT_CPU0_PMU_INTR, + .end = INT_CPU0_PMU_INTR, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = INT_CPU1_PMU_INTR, + .end = INT_CPU1_PMU_INTR, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device tegra_pmu_device = { + .name = "arm-pmu", + .id = ARM_PMU_DEVICE_CPU, + .num_resources = ARRAY_SIZE(tegra_pmu_resources), + .resource = tegra_pmu_resources, +}; + +static struct resource tegra_uarta_resources[] = { + [0] = { + .start = TEGRA_UARTA_BASE, + .end = TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_UARTA, + .end = INT_UARTA, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource tegra_uartb_resources[] = { + [0] = { + .start = TEGRA_UARTB_BASE, + .end = TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_UARTB, + .end = INT_UARTB, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource tegra_uartc_resources[] = { + [0] = { + .start = TEGRA_UARTC_BASE, + .end = TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_UARTC, + .end = INT_UARTC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource tegra_uartd_resources[] = { + [0] = { + .start = TEGRA_UARTD_BASE, + .end = TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_UARTD, + .end = INT_UARTD, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource tegra_uarte_resources[] = { + [0] = { + .start = TEGRA_UARTE_BASE, + .end = TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_UARTE, + .end = INT_UARTE, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device tegra_uarta_device = { + .name = "tegra_uart", + .id = 0, + .num_resources = ARRAY_SIZE(tegra_uarta_resources), + .resource = tegra_uarta_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +struct platform_device tegra_uartb_device = { + .name = "tegra_uart", + .id = 1, + .num_resources = ARRAY_SIZE(tegra_uartb_resources), + .resource = tegra_uartb_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +struct platform_device tegra_uartc_device = { + .name = "tegra_uart", + .id = 2, + .num_resources = ARRAY_SIZE(tegra_uartc_resources), + .resource = tegra_uartc_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +struct platform_device tegra_uartd_device = { + .name = "tegra_uart", + .id = 3, + .num_resources = ARRAY_SIZE(tegra_uartd_resources), + .resource = tegra_uartd_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +struct platform_device tegra_uarte_device = { + .name = "tegra_uart", + .id = 4, + .num_resources = ARRAY_SIZE(tegra_uarte_resources), + .resource = tegra_uarte_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; diff --git a/arch/arm/mach-tegra/devices.h b/arch/arm/mach-tegra/devices.h new file mode 100644 index 000000000000..888810c37ee9 --- /dev/null +++ b/arch/arm/mach-tegra/devices.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2010,2011 Google, Inc. + * + * Author: + * Colin Cross <ccross@android.com> + * Erik Gilling <ccross@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_DEVICES_H +#define __MACH_TEGRA_DEVICES_H + +#include <linux/platform_device.h> + +extern struct platform_device tegra_sdhci_device1; +extern struct platform_device tegra_sdhci_device2; +extern struct platform_device tegra_sdhci_device3; +extern struct platform_device tegra_sdhci_device4; +extern struct platform_device tegra_i2c_device1; +extern struct platform_device tegra_i2c_device2; +extern struct platform_device tegra_i2c_device3; +extern struct platform_device tegra_i2c_device4; +extern struct platform_device tegra_spi_device1; +extern struct platform_device tegra_spi_device2; +extern struct platform_device tegra_spi_device3; +extern struct platform_device tegra_spi_device4; +extern struct platform_device tegra_ehci1_device; +extern struct platform_device tegra_ehci2_device; +extern struct platform_device tegra_ehci3_device; +extern struct platform_device tegra_uarta_device; +extern struct platform_device tegra_uartb_device; +extern struct platform_device tegra_uartc_device; +extern struct platform_device tegra_uartd_device; +extern struct platform_device tegra_uarte_device; +extern struct platform_device tegra_pmu_device; + +#endif diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c index edda6ec5e925..e945ae28ee77 100644 --- a/arch/arm/mach-tegra/dma.c +++ b/arch/arm/mach-tegra/dma.c @@ -27,9 +27,11 @@ #include <linux/err.h> #include <linux/irq.h> #include <linux/delay.h> +#include <linux/clk.h> #include <mach/dma.h> #include <mach/irqs.h> #include <mach/iomap.h> +#include <mach/suspend.h> #define APB_DMA_GEN 0x000 #define GEN_ENABLE (1<<31) @@ -120,17 +122,14 @@ struct tegra_dma_channel { void __iomem *addr; int mode; int irq; - - /* Register shadow */ - u32 csr; - u32 ahb_seq; - u32 ahb_ptr; - u32 apb_seq; - u32 apb_ptr; + int req_transfer_count; }; #define NV_DMA_MAX_CHANNELS 32 +static bool tegra_dma_initialized; +static DEFINE_MUTEX(tegra_dma_lock); + static DECLARE_BITMAP(channel_usage, NV_DMA_MAX_CHANNELS); static struct tegra_dma_channel dma_channels[NV_DMA_MAX_CHANNELS]; @@ -138,7 +137,6 @@ static void tegra_dma_update_hw(struct tegra_dma_channel *ch, struct tegra_dma_req *req); static void tegra_dma_update_hw_partial(struct tegra_dma_channel *ch, struct tegra_dma_req *req); -static void tegra_dma_init_hw(struct tegra_dma_channel *ch); static void tegra_dma_stop(struct tegra_dma_channel *ch); void tegra_dma_flush(struct tegra_dma_channel *ch) @@ -150,6 +148,9 @@ void tegra_dma_dequeue(struct tegra_dma_channel *ch) { struct tegra_dma_req *req; + if (tegra_dma_is_empty(ch)) + return; + req = list_entry(ch->list.next, typeof(*req), node); tegra_dma_dequeue_req(ch, req); @@ -158,10 +159,10 @@ void tegra_dma_dequeue(struct tegra_dma_channel *ch) void tegra_dma_stop(struct tegra_dma_channel *ch) { - unsigned int csr; - unsigned int status; + u32 csr; + u32 status; - csr = ch->csr; + csr = readl(ch->addr + APB_DMA_CHAN_CSR); csr &= ~CSR_IE_EOC; writel(csr, ch->addr + APB_DMA_CHAN_CSR); @@ -175,19 +176,16 @@ void tegra_dma_stop(struct tegra_dma_channel *ch) int tegra_dma_cancel(struct tegra_dma_channel *ch) { - unsigned int csr; + u32 csr; unsigned long irq_flags; spin_lock_irqsave(&ch->lock, irq_flags); while (!list_empty(&ch->list)) list_del(ch->list.next); - csr = ch->csr; + csr = readl(ch->addr + APB_DMA_CHAN_CSR); csr &= ~CSR_REQ_SEL_MASK; csr |= CSR_REQ_SEL_INVALID; - - /* Set the enable as that is not shadowed */ - csr |= CSR_ENB; writel(csr, ch->addr + APB_DMA_CHAN_CSR); tegra_dma_stop(ch); @@ -229,18 +227,15 @@ int tegra_dma_dequeue_req(struct tegra_dma_channel *ch, * - Finally stop or program the DMA to the next buffer in the * list. */ - csr = ch->csr; + csr = readl(ch->addr + APB_DMA_CHAN_CSR); csr &= ~CSR_REQ_SEL_MASK; csr |= CSR_REQ_SEL_INVALID; - - /* Set the enable as that is not shadowed */ - csr |= CSR_ENB; writel(csr, ch->addr + APB_DMA_CHAN_CSR); /* Get the transfer count */ status = readl(ch->addr + APB_DMA_CHAN_STA); to_transfer = (status & STA_COUNT_MASK) >> STA_COUNT_SHIFT; - req_transfer_count = (ch->csr & CSR_WCOUNT_MASK) >> CSR_WCOUNT_SHIFT; + req_transfer_count = ch->req_transfer_count; req_transfer_count += 1; to_transfer += 1; @@ -318,6 +313,7 @@ int tegra_dma_enqueue_req(struct tegra_dma_channel *ch, struct tegra_dma_req *req) { unsigned long irq_flags; + struct tegra_dma_req *_req; int start_dma = 0; if (req->size > NV_DMA_MAX_TRASFER_SIZE || @@ -328,6 +324,13 @@ int tegra_dma_enqueue_req(struct tegra_dma_channel *ch, spin_lock_irqsave(&ch->lock, irq_flags); + list_for_each_entry(_req, &ch->list, node) { + if (req == _req) { + spin_unlock_irqrestore(&ch->lock, irq_flags); + return -EEXIST; + } + } + req->bytes_transferred = 0; req->status = 0; req->buffer_status = 0; @@ -348,7 +351,12 @@ EXPORT_SYMBOL(tegra_dma_enqueue_req); struct tegra_dma_channel *tegra_dma_allocate_channel(int mode) { int channel; - struct tegra_dma_channel *ch; + struct tegra_dma_channel *ch = NULL; + + if (WARN_ON(!tegra_dma_initialized)) + return NULL; + + mutex_lock(&tegra_dma_lock); /* first channel is the shared channel */ if (mode & TEGRA_DMA_SHARED) { @@ -357,11 +365,14 @@ struct tegra_dma_channel *tegra_dma_allocate_channel(int mode) channel = find_first_zero_bit(channel_usage, ARRAY_SIZE(dma_channels)); if (channel >= ARRAY_SIZE(dma_channels)) - return NULL; + goto out; } __set_bit(channel, channel_usage); ch = &dma_channels[channel]; ch->mode = mode; + +out: + mutex_unlock(&tegra_dma_lock); return ch; } EXPORT_SYMBOL(tegra_dma_allocate_channel); @@ -371,22 +382,27 @@ void tegra_dma_free_channel(struct tegra_dma_channel *ch) if (ch->mode & TEGRA_DMA_SHARED) return; tegra_dma_cancel(ch); + mutex_lock(&tegra_dma_lock); __clear_bit(ch->id, channel_usage); + mutex_unlock(&tegra_dma_lock); } EXPORT_SYMBOL(tegra_dma_free_channel); static void tegra_dma_update_hw_partial(struct tegra_dma_channel *ch, struct tegra_dma_req *req) { + u32 apb_ptr; + u32 ahb_ptr; + if (req->to_memory) { - ch->apb_ptr = req->source_addr; - ch->ahb_ptr = req->dest_addr; + apb_ptr = req->source_addr; + ahb_ptr = req->dest_addr; } else { - ch->apb_ptr = req->dest_addr; - ch->ahb_ptr = req->source_addr; + apb_ptr = req->dest_addr; + ahb_ptr = req->source_addr; } - writel(ch->apb_ptr, ch->addr + APB_DMA_CHAN_APB_PTR); - writel(ch->ahb_ptr, ch->addr + APB_DMA_CHAN_AHB_PTR); + writel(apb_ptr, ch->addr + APB_DMA_CHAN_APB_PTR); + writel(ahb_ptr, ch->addr + APB_DMA_CHAN_AHB_PTR); req->status = TEGRA_DMA_REQ_INFLIGHT; return; @@ -400,38 +416,39 @@ static void tegra_dma_update_hw(struct tegra_dma_channel *ch, int ahb_bus_width; int apb_bus_width; int index; - unsigned long csr; + u32 ahb_seq; + u32 apb_seq; + u32 ahb_ptr; + u32 apb_ptr; + u32 csr; + + csr = CSR_IE_EOC | CSR_FLOW; + ahb_seq = AHB_SEQ_INTR_ENB | AHB_SEQ_BURST_1; + apb_seq = 0; - ch->csr |= CSR_FLOW; - ch->csr &= ~CSR_REQ_SEL_MASK; - ch->csr |= req->req_sel << CSR_REQ_SEL_SHIFT; - ch->ahb_seq &= ~AHB_SEQ_BURST_MASK; - ch->ahb_seq |= AHB_SEQ_BURST_1; + csr |= req->req_sel << CSR_REQ_SEL_SHIFT; /* One shot mode is always single buffered, * continuous mode is always double buffered * */ if (ch->mode & TEGRA_DMA_MODE_ONESHOT) { - ch->csr |= CSR_ONCE; - ch->ahb_seq &= ~AHB_SEQ_DBL_BUF; - ch->csr &= ~CSR_WCOUNT_MASK; - ch->csr |= ((req->size>>2) - 1) << CSR_WCOUNT_SHIFT; + csr |= CSR_ONCE; + ch->req_transfer_count = (req->size >> 2) - 1; } else { - ch->csr &= ~CSR_ONCE; - ch->ahb_seq |= AHB_SEQ_DBL_BUF; + ahb_seq |= AHB_SEQ_DBL_BUF; /* In double buffered mode, we set the size to half the * requested size and interrupt when half the buffer * is full */ - ch->csr &= ~CSR_WCOUNT_MASK; - ch->csr |= ((req->size>>3) - 1) << CSR_WCOUNT_SHIFT; + ch->req_transfer_count = (req->size >> 3) - 1; } + csr |= ch->req_transfer_count << CSR_WCOUNT_SHIFT; + if (req->to_memory) { - ch->csr &= ~CSR_DIR; - ch->apb_ptr = req->source_addr; - ch->ahb_ptr = req->dest_addr; + apb_ptr = req->source_addr; + ahb_ptr = req->dest_addr; apb_addr_wrap = req->source_wrap; ahb_addr_wrap = req->dest_wrap; @@ -439,9 +456,9 @@ static void tegra_dma_update_hw(struct tegra_dma_channel *ch, ahb_bus_width = req->dest_bus_width; } else { - ch->csr |= CSR_DIR; - ch->apb_ptr = req->dest_addr; - ch->ahb_ptr = req->source_addr; + csr |= CSR_DIR; + apb_ptr = req->dest_addr; + ahb_ptr = req->source_addr; apb_addr_wrap = req->dest_wrap; ahb_addr_wrap = req->source_wrap; @@ -460,8 +477,7 @@ static void tegra_dma_update_hw(struct tegra_dma_channel *ch, index++; } while (index < ARRAY_SIZE(apb_addr_wrap_table)); BUG_ON(index == ARRAY_SIZE(apb_addr_wrap_table)); - ch->apb_seq &= ~APB_SEQ_WRAP_MASK; - ch->apb_seq |= index << APB_SEQ_WRAP_SHIFT; + apb_seq |= index << APB_SEQ_WRAP_SHIFT; /* set address wrap for AHB size */ index = 0; @@ -471,55 +487,42 @@ static void tegra_dma_update_hw(struct tegra_dma_channel *ch, index++; } while (index < ARRAY_SIZE(ahb_addr_wrap_table)); BUG_ON(index == ARRAY_SIZE(ahb_addr_wrap_table)); - ch->ahb_seq &= ~AHB_SEQ_WRAP_MASK; - ch->ahb_seq |= index << AHB_SEQ_WRAP_SHIFT; + ahb_seq |= index << AHB_SEQ_WRAP_SHIFT; for (index = 0; index < ARRAY_SIZE(bus_width_table); index++) { if (bus_width_table[index] == ahb_bus_width) break; } BUG_ON(index == ARRAY_SIZE(bus_width_table)); - ch->ahb_seq &= ~AHB_SEQ_BUS_WIDTH_MASK; - ch->ahb_seq |= index << AHB_SEQ_BUS_WIDTH_SHIFT; + ahb_seq |= index << AHB_SEQ_BUS_WIDTH_SHIFT; for (index = 0; index < ARRAY_SIZE(bus_width_table); index++) { if (bus_width_table[index] == apb_bus_width) break; } BUG_ON(index == ARRAY_SIZE(bus_width_table)); - ch->apb_seq &= ~APB_SEQ_BUS_WIDTH_MASK; - ch->apb_seq |= index << APB_SEQ_BUS_WIDTH_SHIFT; - - ch->csr |= CSR_IE_EOC; + apb_seq |= index << APB_SEQ_BUS_WIDTH_SHIFT; - /* update hw registers with the shadow */ - writel(ch->csr, ch->addr + APB_DMA_CHAN_CSR); - writel(ch->apb_seq, ch->addr + APB_DMA_CHAN_APB_SEQ); - writel(ch->apb_ptr, ch->addr + APB_DMA_CHAN_APB_PTR); - writel(ch->ahb_seq, ch->addr + APB_DMA_CHAN_AHB_SEQ); - writel(ch->ahb_ptr, ch->addr + APB_DMA_CHAN_AHB_PTR); + writel(csr, ch->addr + APB_DMA_CHAN_CSR); + writel(apb_seq, ch->addr + APB_DMA_CHAN_APB_SEQ); + writel(apb_ptr, ch->addr + APB_DMA_CHAN_APB_PTR); + writel(ahb_seq, ch->addr + APB_DMA_CHAN_AHB_SEQ); + writel(ahb_ptr, ch->addr + APB_DMA_CHAN_AHB_PTR); - csr = ch->csr | CSR_ENB; + csr |= CSR_ENB; writel(csr, ch->addr + APB_DMA_CHAN_CSR); req->status = TEGRA_DMA_REQ_INFLIGHT; } -static void tegra_dma_init_hw(struct tegra_dma_channel *ch) -{ - /* One shot with an interrupt to CPU after transfer */ - ch->csr = CSR_ONCE | CSR_IE_EOC; - ch->ahb_seq = AHB_SEQ_BUS_WIDTH_32 | AHB_SEQ_INTR_ENB; - ch->apb_seq = APB_SEQ_BUS_WIDTH_32 | 1 << APB_SEQ_WRAP_SHIFT; -} - static void handle_oneshot_dma(struct tegra_dma_channel *ch) { struct tegra_dma_req *req; + unsigned long irq_flags; - spin_lock(&ch->lock); + spin_lock_irqsave(&ch->lock, irq_flags); if (list_empty(&ch->list)) { - spin_unlock(&ch->lock); + spin_unlock_irqrestore(&ch->lock, irq_flags); return; } @@ -527,8 +530,7 @@ static void handle_oneshot_dma(struct tegra_dma_channel *ch) if (req) { int bytes_transferred; - bytes_transferred = - (ch->csr & CSR_WCOUNT_MASK) >> CSR_WCOUNT_SHIFT; + bytes_transferred = ch->req_transfer_count; bytes_transferred += 1; bytes_transferred <<= 2; @@ -536,12 +538,12 @@ static void handle_oneshot_dma(struct tegra_dma_channel *ch) req->bytes_transferred = bytes_transferred; req->status = TEGRA_DMA_REQ_SUCCESS; - spin_unlock(&ch->lock); + spin_unlock_irqrestore(&ch->lock, irq_flags); /* Callback should be called without any lock */ pr_debug("%s: transferred %d bytes\n", __func__, req->bytes_transferred); req->complete(req); - spin_lock(&ch->lock); + spin_lock_irqsave(&ch->lock, irq_flags); } if (!list_empty(&ch->list)) { @@ -551,22 +553,55 @@ static void handle_oneshot_dma(struct tegra_dma_channel *ch) if (req->status != TEGRA_DMA_REQ_INFLIGHT) tegra_dma_update_hw(ch, req); } - spin_unlock(&ch->lock); + spin_unlock_irqrestore(&ch->lock, irq_flags); } static void handle_continuous_dma(struct tegra_dma_channel *ch) { struct tegra_dma_req *req; + unsigned long irq_flags; - spin_lock(&ch->lock); + spin_lock_irqsave(&ch->lock, irq_flags); if (list_empty(&ch->list)) { - spin_unlock(&ch->lock); + spin_unlock_irqrestore(&ch->lock, irq_flags); return; } req = list_entry(ch->list.next, typeof(*req), node); if (req) { if (req->buffer_status == TEGRA_DMA_REQ_BUF_STATUS_EMPTY) { + bool is_dma_ping_complete; + is_dma_ping_complete = (readl(ch->addr + APB_DMA_CHAN_STA) + & STA_PING_PONG) ? true : false; + if (req->to_memory) + is_dma_ping_complete = !is_dma_ping_complete; + /* Out of sync - Release current buffer */ + if (!is_dma_ping_complete) { + int bytes_transferred; + + bytes_transferred = ch->req_transfer_count; + bytes_transferred += 1; + bytes_transferred <<= 3; + req->buffer_status = TEGRA_DMA_REQ_BUF_STATUS_FULL; + req->bytes_transferred = bytes_transferred; + req->status = TEGRA_DMA_REQ_SUCCESS; + tegra_dma_stop(ch); + + if (!list_is_last(&req->node, &ch->list)) { + struct tegra_dma_req *next_req; + + next_req = list_entry(req->node.next, + typeof(*next_req), node); + tegra_dma_update_hw(ch, next_req); + } + + list_del(&req->node); + + /* DMA lock is NOT held when callbak is called */ + spin_unlock_irqrestore(&ch->lock, irq_flags); + req->complete(req); + return; + } /* Load the next request into the hardware, if available * */ if (!list_is_last(&req->node, &ch->list)) { @@ -579,7 +614,7 @@ static void handle_continuous_dma(struct tegra_dma_channel *ch) req->buffer_status = TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL; req->status = TEGRA_DMA_REQ_SUCCESS; /* DMA lock is NOT held when callback is called */ - spin_unlock(&ch->lock); + spin_unlock_irqrestore(&ch->lock, irq_flags); if (likely(req->threshold)) req->threshold(req); return; @@ -590,8 +625,7 @@ static void handle_continuous_dma(struct tegra_dma_channel *ch) * the second interrupt */ int bytes_transferred; - bytes_transferred = - (ch->csr & CSR_WCOUNT_MASK) >> CSR_WCOUNT_SHIFT; + bytes_transferred = ch->req_transfer_count; bytes_transferred += 1; bytes_transferred <<= 3; @@ -601,7 +635,7 @@ static void handle_continuous_dma(struct tegra_dma_channel *ch) list_del(&req->node); /* DMA lock is NOT held when callbak is called */ - spin_unlock(&ch->lock); + spin_unlock_irqrestore(&ch->lock, irq_flags); req->complete(req); return; @@ -609,7 +643,7 @@ static void handle_continuous_dma(struct tegra_dma_channel *ch) BUG(); } } - spin_unlock(&ch->lock); + spin_unlock_irqrestore(&ch->lock, irq_flags); } static irqreturn_t dma_isr(int irq, void *data) @@ -646,6 +680,21 @@ int __init tegra_dma_init(void) int i; unsigned int irq; void __iomem *addr; + struct clk *c; + + bitmap_fill(channel_usage, NV_DMA_MAX_CHANNELS); + + c = clk_get_sys("tegra-dma", NULL); + if (IS_ERR(c)) { + pr_err("Unable to get clock for APB DMA\n"); + ret = PTR_ERR(c); + goto fail; + } + ret = clk_enable(c); + if (ret != 0) { + pr_err("Unable to enable clock for APB DMA\n"); + goto fail; + } addr = IO_ADDRESS(TEGRA_APB_DMA_BASE); writel(GEN_ENABLE, addr + APB_DMA_GEN); @@ -653,18 +702,9 @@ int __init tegra_dma_init(void) writel(0xFFFFFFFFul >> (31 - TEGRA_SYSTEM_DMA_CH_MAX), addr + APB_DMA_IRQ_MASK_SET); - memset(channel_usage, 0, sizeof(channel_usage)); - memset(dma_channels, 0, sizeof(dma_channels)); - - /* Reserve all the channels we are not supposed to touch */ - for (i = 0; i < TEGRA_SYSTEM_DMA_CH_MIN; i++) - __set_bit(i, channel_usage); - for (i = TEGRA_SYSTEM_DMA_CH_MIN; i <= TEGRA_SYSTEM_DMA_CH_MAX; i++) { struct tegra_dma_channel *ch = &dma_channels[i]; - __clear_bit(i, channel_usage); - ch->id = i; snprintf(ch->name, TEGRA_DMA_NAME_SIZE, "dma_channel_%d", i); @@ -673,7 +713,6 @@ int __init tegra_dma_init(void) spin_lock_init(&ch->lock); INIT_LIST_HEAD(&ch->list); - tegra_dma_init_hw(ch); irq = INT_APB_DMA_CH0 + i; ret = request_threaded_irq(irq, dma_isr, dma_thread_fn, 0, @@ -684,14 +723,15 @@ int __init tegra_dma_init(void) goto fail; } ch->irq = irq; + + __clear_bit(i, channel_usage); } /* mark the shared channel allocated */ __set_bit(TEGRA_SYSTEM_DMA_CH_MIN, channel_usage); - for (i = TEGRA_SYSTEM_DMA_CH_MAX+1; i < NV_DMA_MAX_CHANNELS; i++) - __set_bit(i, channel_usage); + tegra_dma_initialized = true; - return ret; + return 0; fail: writel(0, addr + APB_DMA_GEN); for (i = TEGRA_SYSTEM_DMA_CH_MIN; i <= TEGRA_SYSTEM_DMA_CH_MAX; i++) { @@ -701,6 +741,7 @@ fail: } return ret; } +postcore_initcall(tegra_dma_init); #ifdef CONFIG_PM static u32 apb_dma[5*TEGRA_SYSTEM_DMA_CH_NR + 3]; diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c index ad8048801513..12090a2cf3e0 100644 --- a/arch/arm/mach-tegra/gpio.c +++ b/arch/arm/mach-tegra/gpio.c @@ -25,6 +25,7 @@ #include <linux/gpio.h> #include <mach/iomap.h> +#include <mach/suspend.h> #define GPIO_BANK(x) ((x) >> 5) #define GPIO_PORT(x) (((x) >> 3) & 0x3) @@ -380,6 +381,20 @@ static int __init tegra_gpio_init(void) postcore_initcall(tegra_gpio_init); +void __init tegra_gpio_config(struct tegra_gpio_table *table, int num) +{ + int i; + + for (i = 0; i < num; i++) { + int gpio = table[i].gpio; + + if (table[i].enable) + tegra_gpio_enable(gpio); + else + tegra_gpio_disable(gpio); + } +} + #ifdef CONFIG_DEBUG_FS #include <linux/debugfs.h> diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h index a217f68ba57c..c8baf8f80d23 100644 --- a/arch/arm/mach-tegra/include/mach/clk.h +++ b/arch/arm/mach-tegra/include/mach/clk.h @@ -25,9 +25,7 @@ struct clk; void tegra_periph_reset_deassert(struct clk *c); void tegra_periph_reset_assert(struct clk *c); -int clk_enable_cansleep(struct clk *clk); -void clk_disable_cansleep(struct clk *clk); -int clk_set_rate_cansleep(struct clk *clk, unsigned long rate); -int clk_set_parent_cansleep(struct clk *clk, struct clk *parent); +unsigned long clk_get_rate_all_locked(struct clk *c); +void tegra_sdmmc_tap_delay(struct clk *c, int delay); #endif diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S index a0e7c12868bd..e0ebe65c1657 100644 --- a/arch/arm/mach-tegra/include/mach/debug-macro.S +++ b/arch/arm/mach-tegra/include/mach/debug-macro.S @@ -19,30 +19,15 @@ */ #include <mach/io.h> +#include <mach/iomap.h> .macro addruart, rp, rv ldr \rp, =IO_APB_PHYS @ physical ldr \rv, =IO_APB_VIRT @ virtual -#if defined(CONFIG_TEGRA_DEBUG_UART_NONE) -#error "A debug UART must be selected in the kernel config to use DEBUG_LL" -#elif defined(CONFIG_TEGRA_DEBUG_UARTA) - orr \rp, \rp, #0x6000 - orr \rv, \rv, #0x6000 -#elif defined(CONFIG_TEGRA_DEBUG_UARTB) - orr \rp, \rp, #0x6000 - orr \rp, \rp, #0x40 - orr \rv, \rv, #0x6000 - orr \rv, \rv, #0x40 -#elif defined(CONFIG_TEGRA_DEBUG_UARTC) - orr \rp, \rp, #0x6200 - orr \rv, \rv, #0x6200 -#elif defined(CONFIG_TEGRA_DEBUG_UARTD) - orr \rp, \rp, #0x6300 - orr \rv, \rv, #0x6300 -#elif defined(CONFIG_TEGRA_DEBUG_UARTE) - orr \rp, \rp, #0x6400 - orr \rv, \rv, #0x6400 -#endif + orr \rp, \rp, #(TEGRA_DEBUG_UART_BASE & 0xFF) + orr \rp, \rp, #(TEGRA_DEBUG_UART_BASE & 0xFF00) + orr \rv, \rv, #(TEGRA_DEBUG_UART_BASE & 0xFF) + orr \rv, \rv, #(TEGRA_DEBUG_UART_BASE & 0xFF00) .endm #define UART_SHIFT 2 diff --git a/arch/arm/mach-tegra/include/mach/gpio.h b/arch/arm/mach-tegra/include/mach/gpio.h index e31f486d69a2..196f114dc241 100644 --- a/arch/arm/mach-tegra/include/mach/gpio.h +++ b/arch/arm/mach-tegra/include/mach/gpio.h @@ -20,6 +20,7 @@ #ifndef __MACH_TEGRA_GPIO_H #define __MACH_TEGRA_GPIO_H +#include <linux/init.h> #include <mach/irqs.h> #define TEGRA_NR_GPIOS INT_GPIO_NR @@ -31,7 +32,7 @@ #define gpio_cansleep __gpio_cansleep #define TEGRA_GPIO_TO_IRQ(gpio) (INT_GPIO_BASE + (gpio)) -#define TEGRA_IRQ_TO_GPIO(irq) ((gpio) - INT_GPIO_BASE) +#define TEGRA_IRQ_TO_GPIO(irq) ((irq) - INT_GPIO_BASE) static inline int gpio_to_irq(unsigned int gpio) { @@ -47,6 +48,12 @@ static inline int irq_to_gpio(unsigned int irq) return -EINVAL; } +struct tegra_gpio_table { + int gpio; /* GPIO number */ + bool enable; /* Enable for GPIO at init? */ +}; + +void tegra_gpio_config(struct tegra_gpio_table *table, int num); void tegra_gpio_enable(int gpio); void tegra_gpio_disable(int gpio); diff --git a/arch/arm/mach-tegra/include/mach/harmony_audio.h b/arch/arm/mach-tegra/include/mach/harmony_audio.h new file mode 100644 index 000000000000..af086500ab7d --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/harmony_audio.h @@ -0,0 +1,22 @@ +/* + * arch/arm/mach-tegra/include/mach/harmony_audio.h + * + * Copyright 2011 NVIDIA, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +struct harmony_audio_platform_data { + int gpio_spkr_en; + int gpio_hp_det; + int gpio_int_mic_en; + int gpio_ext_mic_en; +}; diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h index 44a4f4bcf91f..691cdabd69cf 100644 --- a/arch/arm/mach-tegra/include/mach/iomap.h +++ b/arch/arm/mach-tegra/include/mach/iomap.h @@ -26,6 +26,9 @@ #define TEGRA_IRAM_BASE 0x40000000 #define TEGRA_IRAM_SIZE SZ_256K +#define TEGRA_HOST1X_BASE 0x50000000 +#define TEGRA_HOST1X_SIZE 0x24000 + #define TEGRA_ARM_PERIF_BASE 0x50040000 #define TEGRA_ARM_PERIF_SIZE SZ_8K @@ -35,12 +38,30 @@ #define TEGRA_ARM_INT_DIST_BASE 0x50041000 #define TEGRA_ARM_INT_DIST_SIZE SZ_4K +#define TEGRA_MPE_BASE 0x54040000 +#define TEGRA_MPE_SIZE SZ_256K + +#define TEGRA_VI_BASE 0x54080000 +#define TEGRA_VI_SIZE SZ_256K + +#define TEGRA_ISP_BASE 0x54100000 +#define TEGRA_ISP_SIZE SZ_256K + #define TEGRA_DISPLAY_BASE 0x54200000 #define TEGRA_DISPLAY_SIZE SZ_256K #define TEGRA_DISPLAY2_BASE 0x54240000 #define TEGRA_DISPLAY2_SIZE SZ_256K +#define TEGRA_HDMI_BASE 0x54280000 +#define TEGRA_HDMI_SIZE SZ_256K + +#define TEGRA_GART_BASE 0x58000000 +#define TEGRA_GART_SIZE SZ_32M + +#define TEGRA_RES_SEMA_BASE 0x60001000 +#define TEGRA_RES_SEMA_SIZE SZ_4K + #define TEGRA_PRIMARY_ICTLR_BASE 0x60004000 #define TEGRA_PRIMARY_ICTLR_SIZE SZ_64 @@ -140,6 +161,18 @@ #define TEGRA_PWFM_BASE 0x7000A000 #define TEGRA_PWFM_SIZE SZ_256 +#define TEGRA_PWFM0_BASE 0x7000A000 +#define TEGRA_PWFM0_SIZE 4 + +#define TEGRA_PWFM1_BASE 0x7000A010 +#define TEGRA_PWFM1_SIZE 4 + +#define TEGRA_PWFM2_BASE 0x7000A020 +#define TEGRA_PWFM2_SIZE 4 + +#define TEGRA_PWFM3_BASE 0x7000A030 +#define TEGRA_PWFM3_SIZE 4 + #define TEGRA_MIPI_BASE 0x7000B000 #define TEGRA_MIPI_SIZE SZ_256 @@ -221,4 +254,18 @@ #define TEGRA_SDMMC4_BASE 0xC8000600 #define TEGRA_SDMMC4_SIZE SZ_512 +#if defined(CONFIG_TEGRA_DEBUG_UART_NONE) +# define TEGRA_DEBUG_UART_BASE 0 +#elif defined(CONFIG_TEGRA_DEBUG_UARTA) +# define TEGRA_DEBUG_UART_BASE TEGRA_UARTA_BASE +#elif defined(CONFIG_TEGRA_DEBUG_UARTB) +# define TEGRA_DEBUG_UART_BASE TEGRA_UARTB_BASE +#elif defined(CONFIG_TEGRA_DEBUG_UARTC) +# define TEGRA_DEBUG_UART_BASE TEGRA_UARTC_BASE +#elif defined(CONFIG_TEGRA_DEBUG_UARTD) +# define TEGRA_DEBUG_UART_BASE TEGRA_UARTD_BASE +#elif defined(CONFIG_TEGRA_DEBUG_UARTE) +# define TEGRA_DEBUG_UART_BASE TEGRA_UARTE_BASE +#endif + #endif diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h index 71bbf3422953..73265af4dda3 100644 --- a/arch/arm/mach-tegra/include/mach/irqs.h +++ b/arch/arm/mach-tegra/include/mach/irqs.h @@ -88,7 +88,7 @@ #define INT_SYS_STATS_MON (INT_SEC_BASE + 22) #define INT_GPIO5 (INT_SEC_BASE + 23) #define INT_CPU0_PMU_INTR (INT_SEC_BASE + 24) -#define INT_CPU2_PMU_INTR (INT_SEC_BASE + 25) +#define INT_CPU1_PMU_INTR (INT_SEC_BASE + 25) #define INT_SEC_RES_26 (INT_SEC_BASE + 26) #define INT_S_LINK1 (INT_SEC_BASE + 27) #define INT_APB_DMA_COP (INT_SEC_BASE + 28) @@ -166,10 +166,18 @@ #define INT_QUAD_RES_30 (INT_QUAD_BASE + 30) #define INT_QUAD_RES_31 (INT_QUAD_BASE + 31) -#define INT_GPIO_BASE (INT_QUAD_BASE + 32) +#define INT_MAIN_NR (INT_QUAD_BASE + 32 - INT_PRI_BASE) + +#define INT_GPIO_BASE (INT_PRI_BASE + INT_MAIN_NR) + #define INT_GPIO_NR (28 * 8) -#define NR_IRQS (INT_GPIO_BASE + INT_GPIO_NR) +#define TEGRA_NR_IRQS (INT_GPIO_BASE + INT_GPIO_NR) + +#define INT_BOARD_BASE TEGRA_NR_IRQS +#define NR_BOARD_IRQS 32 + +#define NR_IRQS (INT_BOARD_BASE + NR_BOARD_IRQS) #endif #endif diff --git a/arch/arm/mach-tegra/include/mach/legacy_irq.h b/arch/arm/mach-tegra/include/mach/legacy_irq.h index db1eb3dd04c8..d898c0e3d905 100644 --- a/arch/arm/mach-tegra/include/mach/legacy_irq.h +++ b/arch/arm/mach-tegra/include/mach/legacy_irq.h @@ -27,5 +27,9 @@ int tegra_legacy_force_irq_status(unsigned int irq); void tegra_legacy_select_fiq(unsigned int irq, bool fiq); unsigned long tegra_legacy_vfiq(int nr); unsigned long tegra_legacy_class(int nr); +int tegra_legacy_irq_set_wake(int irq, int enable); +void tegra_legacy_irq_set_lp1_wake_mask(void); +void tegra_legacy_irq_restore_mask(void); +void tegra_init_legacy_irq(void); #endif diff --git a/arch/arm/mach-tegra/include/mach/memory.h b/arch/arm/mach-tegra/include/mach/memory.h index 6151bab62af2..537db3aa81a7 100644 --- a/arch/arm/mach-tegra/include/mach/memory.h +++ b/arch/arm/mach-tegra/include/mach/memory.h @@ -22,7 +22,7 @@ #define __MACH_TEGRA_MEMORY_H /* physical offset of RAM */ -#define PHYS_OFFSET UL(0) +#define PLAT_PHYS_OFFSET UL(0) #endif diff --git a/arch/arm/mach-tegra/include/mach/pinmux-t2.h b/arch/arm/mach-tegra/include/mach/pinmux-t2.h index e5b9d740f973..4c2626347263 100644 --- a/arch/arm/mach-tegra/include/mach/pinmux-t2.h +++ b/arch/arm/mach-tegra/include/mach/pinmux-t2.h @@ -167,6 +167,16 @@ enum tegra_drive_pingroup { TEGRA_DRIVE_PINGROUP_XM2D, TEGRA_DRIVE_PINGROUP_XM2CLK, TEGRA_DRIVE_PINGROUP_MEMCOMP, + TEGRA_DRIVE_PINGROUP_SDIO1, + TEGRA_DRIVE_PINGROUP_CRT, + TEGRA_DRIVE_PINGROUP_DDC, + TEGRA_DRIVE_PINGROUP_GMA, + TEGRA_DRIVE_PINGROUP_GMB, + TEGRA_DRIVE_PINGROUP_GMC, + TEGRA_DRIVE_PINGROUP_GMD, + TEGRA_DRIVE_PINGROUP_GME, + TEGRA_DRIVE_PINGROUP_OWR, + TEGRA_DRIVE_PINGROUP_UAD, TEGRA_MAX_DRIVE_PINGROUP, }; diff --git a/arch/arm/mach-tegra/include/mach/powergate.h b/arch/arm/mach-tegra/include/mach/powergate.h new file mode 100644 index 000000000000..401d1b725291 --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/powergate.h @@ -0,0 +1,40 @@ +/* + * drivers/regulator/tegra-regulator.c + * + * Copyright (c) 2010 Google, Inc + * + * Author: + * Colin Cross <ccross@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _MACH_TEGRA_POWERGATE_H_ +#define _MACH_TEGRA_POWERGATE_H_ + +#define TEGRA_POWERGATE_CPU 0 +#define TEGRA_POWERGATE_3D 1 +#define TEGRA_POWERGATE_VENC 2 +#define TEGRA_POWERGATE_PCIE 3 +#define TEGRA_POWERGATE_VDEC 4 +#define TEGRA_POWERGATE_L2 5 +#define TEGRA_POWERGATE_MPE 6 +#define TEGRA_NUM_POWERGATE 7 + +int tegra_powergate_power_on(int id); +int tegra_powergate_power_off(int id); +bool tegra_powergate_is_powered(int id); +int tegra_powergate_remove_clamping(int id); + +/* Must be called with clk disabled, and returns with clk enabled */ +int tegra_powergate_sequence_power_up(int id, struct clk *clk); + +#endif /* _MACH_TEGRA_POWERGATE_H_ */ diff --git a/arch/arm/mach-tegra/include/mach/suspend.h b/arch/arm/mach-tegra/include/mach/suspend.h new file mode 100644 index 000000000000..5af8715d2e1e --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/suspend.h @@ -0,0 +1,38 @@ +/* + * arch/arm/mach-tegra/include/mach/suspend.h + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + + +#ifndef _MACH_TEGRA_SUSPEND_H_ +#define _MACH_TEGRA_SUSPEND_H_ + +void tegra_pinmux_suspend(void); +void tegra_irq_suspend(void); +void tegra_gpio_suspend(void); +void tegra_clk_suspend(void); +void tegra_dma_suspend(void); +void tegra_timer_suspend(void); + +void tegra_pinmux_resume(void); +void tegra_irq_resume(void); +void tegra_gpio_resume(void); +void tegra_clk_resume(void); +void tegra_dma_resume(void); +void tegra_timer_resume(void); + +#endif /* _MACH_TEGRA_SUSPEND_H_ */ diff --git a/arch/arm/mach-tegra/include/mach/system.h b/arch/arm/mach-tegra/include/mach/system.h index 84d5d46113f7..d0183d876c3b 100644 --- a/arch/arm/mach-tegra/include/mach/system.h +++ b/arch/arm/mach-tegra/include/mach/system.h @@ -24,16 +24,10 @@ #include <mach/hardware.h> #include <mach/iomap.h> -static inline void arch_idle(void) -{ -} +extern void (*arch_reset)(char mode, const char *cmd); -static inline void arch_reset(char mode, const char *cmd) +static inline void arch_idle(void) { - void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04); - u32 reg = readl(reset); - reg |= 0x04; - writel(reg, reset); } #endif diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h index 6c4dd815abd7..4e8323770c79 100644 --- a/arch/arm/mach-tegra/include/mach/uncompress.h +++ b/arch/arm/mach-tegra/include/mach/uncompress.h @@ -26,23 +26,9 @@ #include <mach/iomap.h> -#if defined(CONFIG_TEGRA_DEBUG_UARTA) -#define DEBUG_UART_BASE TEGRA_UARTA_BASE -#elif defined(CONFIG_TEGRA_DEBUG_UARTB) -#define DEBUG_UART_BASE TEGRA_UARTB_BASE -#elif defined(CONFIG_TEGRA_DEBUG_UARTC) -#define DEBUG_UART_BASE TEGRA_UARTC_BASE -#elif defined(CONFIG_TEGRA_DEBUG_UARTD) -#define DEBUG_UART_BASE TEGRA_UARTD_BASE -#elif defined(CONFIG_TEGRA_DEBUG_UARTE) -#define DEBUG_UART_BASE TEGRA_UARTE_BASE -#else -#define DEBUG_UART_BASE NULL -#endif - static void putc(int c) { - volatile u8 *uart = (volatile u8 *)DEBUG_UART_BASE; + volatile u8 *uart = (volatile u8 *)TEGRA_DEBUG_UART_BASE; int shift = 2; if (uart == NULL) @@ -59,7 +45,7 @@ static inline void flush(void) static inline void arch_decomp_setup(void) { - volatile u8 *uart = (volatile u8 *)DEBUG_UART_BASE; + volatile u8 *uart = (volatile u8 *)TEGRA_DEBUG_UART_BASE; int shift = 2; if (uart == NULL) diff --git a/arch/arm/mach-tegra/include/mach/usb_phy.h b/arch/arm/mach-tegra/include/mach/usb_phy.h new file mode 100644 index 000000000000..d4b8f9e298a8 --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/usb_phy.h @@ -0,0 +1,86 @@ +/* + * arch/arm/mach-tegra/include/mach/usb_phy.h + * + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_USB_PHY_H +#define __MACH_USB_PHY_H + +#include <linux/clk.h> +#include <linux/usb/otg.h> + +struct tegra_utmip_config { + u8 hssync_start_delay; + u8 elastic_limit; + u8 idle_wait_delay; + u8 term_range_adj; + u8 xcvr_setup; + u8 xcvr_lsfslew; + u8 xcvr_lsrslew; +}; + +struct tegra_ulpi_config { + int reset_gpio; + const char *clk; +}; + +enum tegra_usb_phy_port_speed { + TEGRA_USB_PHY_PORT_SPEED_FULL = 0, + TEGRA_USB_PHY_PORT_SPEED_LOW, + TEGRA_USB_PHY_PORT_SPEED_HIGH, +}; + +enum tegra_usb_phy_mode { + TEGRA_USB_PHY_MODE_DEVICE, + TEGRA_USB_PHY_MODE_HOST, +}; + +struct tegra_xtal_freq; + +struct tegra_usb_phy { + int instance; + const struct tegra_xtal_freq *freq; + void __iomem *regs; + void __iomem *pad_regs; + struct clk *clk; + struct clk *pll_u; + struct clk *pad_clk; + enum tegra_usb_phy_mode mode; + void *config; + struct otg_transceiver *ulpi; +}; + +struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs, + void *config, enum tegra_usb_phy_mode phy_mode); + +int tegra_usb_phy_power_on(struct tegra_usb_phy *phy); + +void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy); + +void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy); + +void tegra_usb_phy_power_off(struct tegra_usb_phy *phy); + +void tegra_usb_phy_preresume(struct tegra_usb_phy *phy); + +void tegra_usb_phy_postresume(struct tegra_usb_phy *phy); + +void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy, + enum tegra_usb_phy_port_speed port_speed); + +void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy); + +void tegra_usb_phy_close(struct tegra_usb_phy *phy); + +#endif /* __MACH_USB_PHY_H */ diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index 17c74d21077c..dfbc219ea492 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -18,6 +18,7 @@ */ #include <linux/kernel.h> +#include <linux/delay.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/irq.h> @@ -26,73 +27,119 @@ #include <asm/hardware/gic.h> #include <mach/iomap.h> +#include <mach/legacy_irq.h> +#include <mach/suspend.h> #include "board.h" -#define INT_SYS_NR (INT_GPIO_BASE - INT_PRI_BASE) -#define INT_SYS_SZ (INT_SEC_BASE - INT_PRI_BASE) -#define PPI_NR ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ) +#define PMC_CTRL 0x0 +#define PMC_CTRL_LATCH_WAKEUPS (1 << 5) +#define PMC_WAKE_MASK 0xc +#define PMC_WAKE_LEVEL 0x10 +#define PMC_WAKE_STATUS 0x14 +#define PMC_SW_WAKE_STATUS 0x18 +#define PMC_DPD_SAMPLE 0x20 -#define APBDMA_IRQ_STA_CPU 0x14 -#define APBDMA_IRQ_MASK_SET 0x20 -#define APBDMA_IRQ_MASK_CLR 0x24 +static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); -#define ICTLR_CPU_IER 0x20 -#define ICTLR_CPU_IER_SET 0x24 -#define ICTLR_CPU_IER_CLR 0x28 -#define ICTLR_CPU_IEP_CLASS 0x2c -#define ICTLR_COP_IER 0x30 -#define ICTLR_COP_IER_SET 0x34 -#define ICTLR_COP_IER_CLR 0x38 -#define ICTLR_COP_IEP_CLASS 0x3c +static u32 tegra_lp0_wake_enb; +static u32 tegra_lp0_wake_level; +static u32 tegra_lp0_wake_level_any; static void (*tegra_gic_mask_irq)(struct irq_data *d); static void (*tegra_gic_unmask_irq)(struct irq_data *d); +static void (*tegra_gic_ack_irq)(struct irq_data *d); -#define irq_to_ictlr(irq) (((irq) - 32) >> 5) -static void __iomem *tegra_ictlr_base = IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE); -#define ictlr_to_virt(ictlr) (tegra_ictlr_base + (ictlr) * 0x100) +/* ensures that sufficient time is passed for a register write to + * serialize into the 32KHz domain */ +static void pmc_32kwritel(u32 val, unsigned long offs) +{ + writel(val, pmc + offs); + udelay(130); +} + +int tegra_set_lp1_wake(int irq, int enable) +{ + return tegra_legacy_irq_set_wake(irq, enable); +} + +void tegra_set_lp0_wake_pads(u32 wake_enb, u32 wake_level, u32 wake_any) +{ + u32 temp; + u32 status; + u32 lvl; + + wake_level &= wake_enb; + wake_any &= wake_enb; + + wake_level |= (tegra_lp0_wake_level & tegra_lp0_wake_enb); + wake_any |= (tegra_lp0_wake_level_any & tegra_lp0_wake_enb); + + wake_enb |= tegra_lp0_wake_enb; + + pmc_32kwritel(0, PMC_SW_WAKE_STATUS); + temp = readl(pmc + PMC_CTRL); + temp |= PMC_CTRL_LATCH_WAKEUPS; + pmc_32kwritel(temp, PMC_CTRL); + temp &= ~PMC_CTRL_LATCH_WAKEUPS; + pmc_32kwritel(temp, PMC_CTRL); + status = readl(pmc + PMC_SW_WAKE_STATUS); + lvl = readl(pmc + PMC_WAKE_LEVEL); + + /* flip the wakeup trigger for any-edge triggered pads + * which are currently asserting as wakeups */ + lvl ^= status; + lvl &= wake_any; + + wake_level |= lvl; + + writel(wake_level, pmc + PMC_WAKE_LEVEL); + /* Enable DPD sample to trigger sampling pads data and direction + * in which pad will be driven during lp0 mode*/ + writel(0x1, pmc + PMC_DPD_SAMPLE); + + writel(wake_enb, pmc + PMC_WAKE_MASK); +} static void tegra_mask(struct irq_data *d) { - void __iomem *addr = ictlr_to_virt(irq_to_ictlr(d->irq)); tegra_gic_mask_irq(d); - writel(1 << (d->irq & 31), addr+ICTLR_CPU_IER_CLR); + tegra_legacy_mask_irq(d->irq); } static void tegra_unmask(struct irq_data *d) { - void __iomem *addr = ictlr_to_virt(irq_to_ictlr(d->irq)); tegra_gic_unmask_irq(d); - writel(1<<(d->irq&31), addr+ICTLR_CPU_IER_SET); + tegra_legacy_unmask_irq(d->irq); } -#ifdef CONFIG_PM +static void tegra_ack(struct irq_data *d) +{ + tegra_legacy_force_irq_clr(d->irq); + tegra_gic_ack_irq(d); +} -static int tegra_set_wake(struct irq_data *d, unsigned int on) +static int tegra_retrigger(struct irq_data *d) { - return 0; + tegra_legacy_force_irq_set(d->irq); + return 1; } -#endif static struct irq_chip tegra_irq = { - .name = "PPI", - .irq_mask = tegra_mask, - .irq_unmask = tegra_unmask, -#ifdef CONFIG_PM - .irq_set_wake = tegra_set_wake, -#endif + .name = "PPI", + .irq_ack = tegra_ack, + .irq_mask = tegra_mask, + .irq_unmask = tegra_unmask, + .irq_retrigger = tegra_retrigger, }; void __init tegra_init_irq(void) { struct irq_chip *gic; unsigned int i; + int irq; - for (i = 0; i < PPI_NR; i++) { - writel(~0, ictlr_to_virt(i) + ICTLR_CPU_IER_CLR); - writel(0, ictlr_to_virt(i) + ICTLR_CPU_IEP_CLASS); - } + tegra_init_legacy_irq(); gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); @@ -100,72 +147,15 @@ void __init tegra_init_irq(void) gic = get_irq_chip(29); tegra_gic_unmask_irq = gic->irq_unmask; tegra_gic_mask_irq = gic->irq_mask; - tegra_irq.irq_ack = gic->irq_ack; + tegra_gic_ack_irq = gic->irq_ack; #ifdef CONFIG_SMP tegra_irq.irq_set_affinity = gic->irq_set_affinity; #endif - for (i = INT_PRI_BASE; i < INT_GPIO_BASE; i++) { - set_irq_chip(i, &tegra_irq); - set_irq_handler(i, handle_level_irq); - set_irq_flags(i, IRQF_VALID); + for (i = 0; i < INT_MAIN_NR; i++) { + irq = INT_PRI_BASE + i; + set_irq_chip(irq, &tegra_irq); + set_irq_handler(irq, handle_level_irq); + set_irq_flags(irq, IRQF_VALID); } } - -#ifdef CONFIG_PM -static u32 cop_ier[PPI_NR]; -static u32 cpu_ier[PPI_NR]; -static u32 cpu_iep[PPI_NR]; - -void tegra_irq_suspend(void) -{ - unsigned long flags; - int i; - - for (i = INT_PRI_BASE; i < INT_GPIO_BASE; i++) { - struct irq_desc *desc = irq_to_desc(i); - if (!desc) - continue; - if (desc->status & IRQ_WAKEUP) { - pr_debug("irq %d is wakeup\n", i); - continue; - } - disable_irq(i); - } - - local_irq_save(flags); - for (i = 0; i < PPI_NR; i++) { - void __iomem *ictlr = ictlr_to_virt(i); - cpu_ier[i] = readl(ictlr + ICTLR_CPU_IER); - cpu_iep[i] = readl(ictlr + ICTLR_CPU_IEP_CLASS); - cop_ier[i] = readl(ictlr + ICTLR_COP_IER); - writel(~0, ictlr + ICTLR_COP_IER_CLR); - } - local_irq_restore(flags); -} - -void tegra_irq_resume(void) -{ - unsigned long flags; - int i; - - local_irq_save(flags); - for (i = 0; i < PPI_NR; i++) { - void __iomem *ictlr = ictlr_to_virt(i); - writel(cpu_iep[i], ictlr + ICTLR_CPU_IEP_CLASS); - writel(~0ul, ictlr + ICTLR_CPU_IER_CLR); - writel(cpu_ier[i], ictlr + ICTLR_CPU_IER_SET); - writel(0, ictlr + ICTLR_COP_IEP_CLASS); - writel(~0ul, ictlr + ICTLR_COP_IER_CLR); - writel(cop_ier[i], ictlr + ICTLR_COP_IER_SET); - } - local_irq_restore(flags); - - for (i = INT_PRI_BASE; i < INT_GPIO_BASE; i++) { - struct irq_desc *desc = irq_to_desc(i); - if (!desc || (desc->status & IRQ_WAKEUP)) - continue; - enable_irq(i); - } -} -#endif diff --git a/arch/arm/mach-tegra/legacy_irq.c b/arch/arm/mach-tegra/legacy_irq.c index 7cc8601c19ff..38eb719a4f53 100644 --- a/arch/arm/mach-tegra/legacy_irq.c +++ b/arch/arm/mach-tegra/legacy_irq.c @@ -18,17 +18,30 @@ #include <linux/io.h> #include <linux/kernel.h> #include <mach/iomap.h> +#include <mach/irqs.h> #include <mach/legacy_irq.h> -#define ICTLR_CPU_IER 0x20 -#define ICTLR_CPU_IER_SET 0x24 -#define ICTLR_CPU_IER_CLR 0x28 -#define ICTLR_CPU_IEP_CLASS 0x2C +#define INT_SYS_NR (INT_GPIO_BASE - INT_PRI_BASE) +#define INT_SYS_SZ (INT_SEC_BASE - INT_PRI_BASE) +#define PPI_NR ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ) + #define ICTLR_CPU_IEP_VFIQ 0x08 #define ICTLR_CPU_IEP_FIR 0x14 #define ICTLR_CPU_IEP_FIR_SET 0x18 #define ICTLR_CPU_IEP_FIR_CLR 0x1c +#define ICTLR_CPU_IER 0x20 +#define ICTLR_CPU_IER_SET 0x24 +#define ICTLR_CPU_IER_CLR 0x28 +#define ICTLR_CPU_IEP_CLASS 0x2C + +#define ICTLR_COP_IER 0x30 +#define ICTLR_COP_IER_SET 0x34 +#define ICTLR_COP_IER_CLR 0x38 +#define ICTLR_COP_IEP_CLASS 0x3c + +#define NUM_ICTLRS 4 + static void __iomem *ictlr_reg_base[] = { IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE), IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE), @@ -36,6 +49,9 @@ static void __iomem *ictlr_reg_base[] = { IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE), }; +static u32 tegra_legacy_wake_mask[4]; +static u32 tegra_legacy_saved_mask[4]; + /* When going into deep sleep, the CPU is powered down, taking the GIC with it In order to wake, the wake interrupts need to be enabled in the legacy interrupt controller. */ @@ -112,3 +128,88 @@ unsigned long tegra_legacy_class(int nr) base = ictlr_reg_base[nr]; return readl(base + ICTLR_CPU_IEP_CLASS); } + +int tegra_legacy_irq_set_wake(int irq, int enable) +{ + irq -= 32; + if (enable) + tegra_legacy_wake_mask[irq >> 5] |= 1 << (irq & 31); + else + tegra_legacy_wake_mask[irq >> 5] &= ~(1 << (irq & 31)); + + return 0; +} + +void tegra_legacy_irq_set_lp1_wake_mask(void) +{ + void __iomem *base; + int i; + + for (i = 0; i < NUM_ICTLRS; i++) { + base = ictlr_reg_base[i]; + tegra_legacy_saved_mask[i] = readl(base + ICTLR_CPU_IER); + writel(tegra_legacy_wake_mask[i], base + ICTLR_CPU_IER); + } +} + +void tegra_legacy_irq_restore_mask(void) +{ + void __iomem *base; + int i; + + for (i = 0; i < NUM_ICTLRS; i++) { + base = ictlr_reg_base[i]; + writel(tegra_legacy_saved_mask[i], base + ICTLR_CPU_IER); + } +} + +void tegra_init_legacy_irq(void) +{ + int i; + + for (i = 0; i < NUM_ICTLRS; i++) { + void __iomem *ictlr = ictlr_reg_base[i]; + writel(~0, ictlr + ICTLR_CPU_IER_CLR); + writel(0, ictlr + ICTLR_CPU_IEP_CLASS); + } +} + +#ifdef CONFIG_PM +static u32 cop_ier[NUM_ICTLRS]; +static u32 cpu_ier[NUM_ICTLRS]; +static u32 cpu_iep[NUM_ICTLRS]; + +void tegra_irq_suspend(void) +{ + unsigned long flags; + int i; + + local_irq_save(flags); + for (i = 0; i < NUM_ICTLRS; i++) { + void __iomem *ictlr = ictlr_reg_base[i]; + cpu_ier[i] = readl(ictlr + ICTLR_CPU_IER); + cpu_iep[i] = readl(ictlr + ICTLR_CPU_IEP_CLASS); + cop_ier[i] = readl(ictlr + ICTLR_COP_IER); + writel(~0, ictlr + ICTLR_COP_IER_CLR); + } + local_irq_restore(flags); +} + +void tegra_irq_resume(void) +{ + unsigned long flags; + int i; + + local_irq_save(flags); + for (i = 0; i < NUM_ICTLRS; i++) { + void __iomem *ictlr = ictlr_reg_base[i]; + writel(cpu_iep[i], ictlr + ICTLR_CPU_IEP_CLASS); + writel(~0ul, ictlr + ICTLR_CPU_IER_CLR); + writel(cpu_ier[i], ictlr + ICTLR_CPU_IER_SET); + writel(0, ictlr + ICTLR_COP_IEP_CLASS); + writel(~0ul, ictlr + ICTLR_COP_IER_CLR); + writel(cop_ier[i], ictlr + ICTLR_COP_IER_SET); + } + local_irq_restore(flags); +} +#endif diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c index 53f5fa37014a..2941212b853c 100644 --- a/arch/arm/mach-tegra/pcie.c +++ b/arch/arm/mach-tegra/pcie.c @@ -39,6 +39,7 @@ #include <mach/pinmux.h> #include <mach/iomap.h> #include <mach/clk.h> +#include <mach/powergate.h> /* register definitions */ #define AFI_OFFSET 0x3800 @@ -682,24 +683,41 @@ static void tegra_pcie_xclk_clamp(bool clamp) pmc_writel(reg, PMC_SCRATCH42); } -static int tegra_pcie_power_on(void) +static void tegra_pcie_power_off(void) { - tegra_pcie_xclk_clamp(true); tegra_periph_reset_assert(tegra_pcie.pcie_xclk); - tegra_pcie_xclk_clamp(false); + tegra_periph_reset_assert(tegra_pcie.afi_clk); + tegra_periph_reset_assert(tegra_pcie.pex_clk); - clk_enable(tegra_pcie.afi_clk); - clk_enable(tegra_pcie.pex_clk); - return clk_enable(tegra_pcie.pll_e); + tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); + tegra_pcie_xclk_clamp(true); } -static void tegra_pcie_power_off(void) +static int tegra_pcie_power_regate(void) { + int err; + + tegra_pcie_power_off(); + + tegra_pcie_xclk_clamp(true); + tegra_periph_reset_assert(tegra_pcie.pcie_xclk); tegra_periph_reset_assert(tegra_pcie.afi_clk); - tegra_periph_reset_assert(tegra_pcie.pex_clk); - tegra_pcie_xclk_clamp(true); + err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE, + tegra_pcie.pex_clk); + if (err) { + pr_err("PCIE: powerup sequence failed: %d\n", err); + return err; + } + + tegra_periph_reset_deassert(tegra_pcie.afi_clk); + + tegra_pcie_xclk_clamp(false); + + clk_enable(tegra_pcie.afi_clk); + clk_enable(tegra_pcie.pex_clk); + return clk_enable(tegra_pcie.pll_e); } static int tegra_pcie_clocks_get(void) @@ -759,7 +777,7 @@ static int __init tegra_pcie_get_resources(void) return err; } - err = tegra_pcie_power_on(); + err = tegra_pcie_power_regate(); if (err) { pr_err("PCIE: failed to power up: %d\n", err); goto err_pwr_on; diff --git a/arch/arm/mach-tegra/pinmux-t2-tables.c b/arch/arm/mach-tegra/pinmux-t2-tables.c index a6ea34e782dc..a475367befa3 100644 --- a/arch/arm/mach-tegra/pinmux-t2-tables.c +++ b/arch/arm/mach-tegra/pinmux-t2-tables.c @@ -29,6 +29,7 @@ #include <mach/iomap.h> #include <mach/pinmux.h> +#include <mach/suspend.h> #define DRIVE_PINGROUP(pg_name, r) \ [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \ @@ -65,6 +66,16 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE DRIVE_PINGROUP(XM2D, 0x8cc), DRIVE_PINGROUP(XM2CLK, 0x8d0), DRIVE_PINGROUP(MEMCOMP, 0x8d4), + DRIVE_PINGROUP(SDIO1, 0x8e0), + DRIVE_PINGROUP(CRT, 0x8ec), + DRIVE_PINGROUP(DDC, 0x8f0), + DRIVE_PINGROUP(GMA, 0x8f4), + DRIVE_PINGROUP(GMB, 0x8f8), + DRIVE_PINGROUP(GMC, 0x8fc), + DRIVE_PINGROUP(GMD, 0x900), + DRIVE_PINGROUP(GME, 0x904), + DRIVE_PINGROUP(OWR, 0x908), + DRIVE_PINGROUP(UAD, 0x90c), }; #define PINGROUP(pg_name, vdd, f0, f1, f2, f3, f_safe, \ @@ -216,7 +227,8 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = { #define PULLUPDOWN_REG_NUM 5 static u32 pinmux_reg[TRISTATE_REG_NUM + PIN_MUX_CTL_REG_NUM + - PULLUPDOWN_REG_NUM]; + PULLUPDOWN_REG_NUM + + ARRAY_SIZE(tegra_soc_drive_pingroups)]; static inline unsigned long pg_readl(unsigned long offset) { @@ -233,14 +245,17 @@ void tegra_pinmux_suspend(void) unsigned int i; u32 *ctx = pinmux_reg; - for (i = 0; i < TRISTATE_REG_NUM; i++) - *ctx++ = pg_readl(TRISTATE_REG_A + i*4); - for (i = 0; i < PIN_MUX_CTL_REG_NUM; i++) *ctx++ = pg_readl(PIN_MUX_CTL_REG_A + i*4); for (i = 0; i < PULLUPDOWN_REG_NUM; i++) *ctx++ = pg_readl(PULLUPDOWN_REG_A + i*4); + + for (i = 0; i < TRISTATE_REG_NUM; i++) + *ctx++ = pg_readl(TRISTATE_REG_A + i*4); + + for (i = 0; i < ARRAY_SIZE(tegra_soc_drive_pingroups); i++) + *ctx++ = pg_readl(tegra_soc_drive_pingroups[i].reg); } void tegra_pinmux_resume(void) @@ -256,5 +271,8 @@ void tegra_pinmux_resume(void) for (i = 0; i < TRISTATE_REG_NUM; i++) pg_writel(*ctx++, TRISTATE_REG_A + i*4); + + for (i = 0; i < ARRAY_SIZE(tegra_soc_drive_pingroups); i++) + pg_writel(*ctx++, tegra_soc_drive_pingroups[i].reg); } #endif diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c new file mode 100644 index 000000000000..3cee9aa1f2c8 --- /dev/null +++ b/arch/arm/mach-tegra/powergate.c @@ -0,0 +1,212 @@ +/* + * drivers/powergate/tegra-powergate.c + * + * Copyright (c) 2010 Google, Inc + * + * Author: + * Colin Cross <ccross@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/clk.h> +#include <linux/debugfs.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/seq_file.h> +#include <linux/spinlock.h> + +#include <mach/clk.h> +#include <mach/iomap.h> +#include <mach/powergate.h> + +#define PWRGATE_TOGGLE 0x30 +#define PWRGATE_TOGGLE_START (1 << 8) + +#define REMOVE_CLAMPING 0x34 + +#define PWRGATE_STATUS 0x38 + +static DEFINE_SPINLOCK(tegra_powergate_lock); + +static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); + +static u32 pmc_read(unsigned long reg) +{ + return readl(pmc + reg); +} + +static void pmc_write(u32 val, unsigned long reg) +{ + writel(val, pmc + reg); +} + +static int tegra_powergate_set(int id, bool new_state) +{ + bool status; + unsigned long flags; + + spin_lock_irqsave(&tegra_powergate_lock, flags); + + status = pmc_read(PWRGATE_STATUS) & (1 << id); + + if (status == new_state) { + spin_unlock_irqrestore(&tegra_powergate_lock, flags); + return -EINVAL; + } + + pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); + + spin_unlock_irqrestore(&tegra_powergate_lock, flags); + + return 0; +} + +int tegra_powergate_power_on(int id) +{ + if (id < 0 || id >= TEGRA_NUM_POWERGATE) + return -EINVAL; + + return tegra_powergate_set(id, true); +} + +int tegra_powergate_power_off(int id) +{ + if (id < 0 || id >= TEGRA_NUM_POWERGATE) + return -EINVAL; + + return tegra_powergate_set(id, false); +} + +bool tegra_powergate_is_powered(int id) +{ + u32 status; + + if (id < 0 || id >= TEGRA_NUM_POWERGATE) + return -EINVAL; + + status = pmc_read(PWRGATE_STATUS) & (1 << id); + return !!status; +} + +int tegra_powergate_remove_clamping(int id) +{ + u32 mask; + + if (id < 0 || id >= TEGRA_NUM_POWERGATE) + return -EINVAL; + + /* + * Tegra 2 has a bug where PCIE and VDE clamping masks are + * swapped relatively to the partition ids + */ + if (id == TEGRA_POWERGATE_VDEC) + mask = (1 << TEGRA_POWERGATE_PCIE); + else if (id == TEGRA_POWERGATE_PCIE) + mask = (1 << TEGRA_POWERGATE_VDEC); + else + mask = (1 << id); + + pmc_write(mask, REMOVE_CLAMPING); + + return 0; +} + +/* Must be called with clk disabled, and returns with clk enabled */ +int tegra_powergate_sequence_power_up(int id, struct clk *clk) +{ + int ret; + + tegra_periph_reset_assert(clk); + + ret = tegra_powergate_power_on(id); + if (ret) + goto err_power; + + ret = clk_enable(clk); + if (ret) + goto err_clk; + + udelay(10); + + ret = tegra_powergate_remove_clamping(id); + if (ret) + goto err_clamp; + + udelay(10); + tegra_periph_reset_deassert(clk); + + return 0; + +err_clamp: + clk_disable(clk); +err_clk: + tegra_powergate_power_off(id); +err_power: + return ret; +} + +#ifdef CONFIG_DEBUG_FS + +static const char * const powergate_name[] = { + [TEGRA_POWERGATE_CPU] = "cpu", + [TEGRA_POWERGATE_3D] = "3d", + [TEGRA_POWERGATE_VENC] = "venc", + [TEGRA_POWERGATE_VDEC] = "vdec", + [TEGRA_POWERGATE_PCIE] = "pcie", + [TEGRA_POWERGATE_L2] = "l2", + [TEGRA_POWERGATE_MPE] = "mpe", +}; + +static int powergate_show(struct seq_file *s, void *data) +{ + int i; + + seq_printf(s, " powergate powered\n"); + seq_printf(s, "------------------\n"); + + for (i = 0; i < TEGRA_NUM_POWERGATE; i++) + seq_printf(s, " %9s %7s\n", powergate_name[i], + tegra_powergate_is_powered(i) ? "yes" : "no"); + return 0; +} + +static int powergate_open(struct inode *inode, struct file *file) +{ + return single_open(file, powergate_show, inode->i_private); +} + +static const struct file_operations powergate_fops = { + .open = powergate_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int __init powergate_debugfs_init(void) +{ + struct dentry *d; + int err = -ENOMEM; + + d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, + &powergate_fops); + if (!d) + return -ENOMEM; + + return err; +} + +late_initcall(powergate_debugfs_init); + +#endif diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index f0dae6d8ba52..6d7c4eea4dcb 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -23,14 +23,15 @@ #include <linux/spinlock.h> #include <linux/delay.h> #include <linux/io.h> -#include <linux/hrtimer.h> #include <linux/clkdev.h> +#include <linux/clk.h> #include <mach/iomap.h> +#include <mach/suspend.h> #include "clock.h" #include "fuse.h" -#include "tegra2_dvfs.h" +#include "tegra2_emc.h" #define RST_DEVICES 0x004 #define RST_DEVICES_SET 0x300 @@ -51,7 +52,7 @@ #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30) #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30) #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30) -#define OSC_CTRL_MASK 0x3f2 +#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) #define OSC_FREQ_DET 0x58 #define OSC_FREQ_DET_TRIG (1<<31) @@ -73,12 +74,15 @@ #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF #define PERIPH_CLK_SOURCE_DIV_SHIFT 0 +#define SDMMC_CLK_INT_FB_SEL (1 << 23) +#define SDMMC_CLK_INT_FB_DLY_SHIFT 16 +#define SDMMC_CLK_INT_FB_DLY_MASK (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT) + #define PLL_BASE 0x0 #define PLL_BASE_BYPASS (1<<31) #define PLL_BASE_ENABLE (1<<30) #define PLL_BASE_REF_ENABLE (1<<29) #define PLL_BASE_OVERRIDE (1<<28) -#define PLL_BASE_LOCK (1<<27) #define PLL_BASE_DIVP_MASK (0x7<<20) #define PLL_BASE_DIVP_SHIFT 20 #define PLL_BASE_DIVN_MASK (0x3FF<<8) @@ -93,7 +97,6 @@ #define PLL_OUT_RESET_DISABLE (1<<0) #define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc) -#define PLL_MISC_LOCK_ENABLE(c) (((c)->flags & PLLU) ? (1<<22) : (1<<18)) #define PLL_MISC_DCCON_SHIFT 20 #define PLL_MISC_CPCON_SHIFT 8 @@ -111,9 +114,9 @@ #define PLLE_MISC_READY (1 << 15) -#define PERIPH_CLK_TO_ENB_REG(c) ((c->clk_num / 32) * 4) -#define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->clk_num / 32) * 8) -#define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->clk_num % 32)) +#define PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4) +#define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8) +#define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32)) #define SUPER_CLK_MUX 0x00 #define SUPER_STATE_SHIFT 28 @@ -134,12 +137,42 @@ #define BUS_CLK_DISABLE (1<<3) #define BUS_CLK_DIV_MASK 0x3 +#define PMC_CTRL 0x0 + #define PMC_CTRL_BLINK_ENB (1 << 7) + +#define PMC_DPD_PADS_ORIDE 0x1c + #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20) + +#define PMC_BLINK_TIMER_DATA_ON_SHIFT 0 +#define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff +#define PMC_BLINK_TIMER_ENB (1 << 15) +#define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16 +#define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff + static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE); +static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); + +/* + * Some clocks share a register with other clocks. Any clock op that + * non-atomically modifies a register used by another clock must lock + * clock_register_lock first. + */ +static DEFINE_SPINLOCK(clock_register_lock); + +/* + * Some peripheral clocks share an enable bit, so refcount the enable bits + * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U + */ +static int tegra_periph_clk_enable_refcount[3 * 32]; #define clk_writel(value, reg) \ __raw_writel(value, (u32)reg_clk_base + (reg)) #define clk_readl(reg) \ __raw_readl((u32)reg_clk_base + (reg)) +#define pmc_writel(value, reg) \ + __raw_writel(value, (u32)reg_pmc_base + (reg)) +#define pmc_readl(reg) \ + __raw_readl((u32)reg_pmc_base + (reg)) unsigned long clk_measure_input_freq(void) { @@ -245,6 +278,18 @@ static struct clk_ops tegra_clk_m_ops = { .disable = tegra2_clk_m_disable, }; +void tegra2_periph_reset_assert(struct clk *c) +{ + BUG_ON(!c->ops->reset); + c->ops->reset(c, true); +} + +void tegra2_periph_reset_deassert(struct clk *c) +{ + BUG_ON(!c->ops->reset); + c->ops->reset(c, false); +} + /* super clock functions */ /* "super clocks" on tegra have two-stage muxes and a clock skipping * super divider. We will ignore the clock skipping divider, since we @@ -303,12 +348,12 @@ static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p) val |= sel->value << shift; if (c->refcnt) - clk_enable_locked(p); + clk_enable(p); clk_writel(val, c->reg); if (c->refcnt && c->parent) - clk_disable_locked(c->parent); + clk_disable(c->parent); clk_reparent(c, p); return 0; @@ -317,11 +362,24 @@ static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p) return -EINVAL; } +/* + * Super clocks have "clock skippers" instead of dividers. Dividing using + * a clock skipper does not allow the voltage to be scaled down, so instead + * adjust the rate of the parent clock. This requires that the parent of a + * super clock have no other children, otherwise the rate will change + * underneath the other children. + */ +static int tegra2_super_clk_set_rate(struct clk *c, unsigned long rate) +{ + return clk_set_rate(c->parent, rate); +} + static struct clk_ops tegra_super_ops = { .init = tegra2_super_clk_init, .enable = tegra2_super_clk_enable, .disable = tegra2_super_clk_disable, .set_parent = tegra2_super_clk_set_parent, + .set_rate = tegra2_super_clk_set_rate, }; /* virtual cpu clock functions */ @@ -351,25 +409,36 @@ static void tegra2_cpu_clk_disable(struct clk *c) static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate) { int ret; - ret = clk_set_parent_locked(c->parent, c->backup); + /* + * Take an extra reference to the main pll so it doesn't turn + * off when we move the cpu off of it + */ + clk_enable(c->u.cpu.main); + + ret = clk_set_parent(c->parent, c->u.cpu.backup); if (ret) { - pr_err("Failed to switch cpu to clock %s\n", c->backup->name); - return ret; + pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.backup->name); + goto out; } - ret = clk_set_rate_locked(c->main, rate); + if (rate == clk_get_rate(c->u.cpu.backup)) + goto out; + + ret = clk_set_rate(c->u.cpu.main, rate); if (ret) { pr_err("Failed to change cpu pll to %lu\n", rate); - return ret; + goto out; } - ret = clk_set_parent_locked(c->parent, c->main); + ret = clk_set_parent(c->parent, c->u.cpu.main); if (ret) { - pr_err("Failed to switch cpu to clock %s\n", c->main->name); - return ret; + pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.main->name); + goto out; } - return 0; +out: + clk_disable(c->u.cpu.main); + return ret; } static struct clk_ops tegra_cpu_ops = { @@ -379,6 +448,20 @@ static struct clk_ops tegra_cpu_ops = { .set_rate = tegra2_cpu_clk_set_rate, }; +/* virtual cop clock functions. Used to acquire the fake 'cop' clock to + * reset the COP block (i.e. AVP) */ +static void tegra2_cop_clk_reset(struct clk *c, bool assert) +{ + unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR; + + pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert"); + clk_writel(1 << 1, reg); +} + +static struct clk_ops tegra_cop_ops = { + .reset = tegra2_cop_clk_reset, +}; + /* bus clock functions */ static void tegra2_bus_clk_init(struct clk *c) { @@ -390,24 +473,45 @@ static void tegra2_bus_clk_init(struct clk *c) static int tegra2_bus_clk_enable(struct clk *c) { - u32 val = clk_readl(c->reg); + u32 val; + unsigned long flags; + + spin_lock_irqsave(&clock_register_lock, flags); + + val = clk_readl(c->reg); val &= ~(BUS_CLK_DISABLE << c->reg_shift); clk_writel(val, c->reg); + + spin_unlock_irqrestore(&clock_register_lock, flags); + return 0; } static void tegra2_bus_clk_disable(struct clk *c) { - u32 val = clk_readl(c->reg); + u32 val; + unsigned long flags; + + spin_lock_irqsave(&clock_register_lock, flags); + + val = clk_readl(c->reg); val |= BUS_CLK_DISABLE << c->reg_shift; clk_writel(val, c->reg); + + spin_unlock_irqrestore(&clock_register_lock, flags); } static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate) { - u32 val = clk_readl(c->reg); - unsigned long parent_rate = c->parent->rate; + u32 val; + unsigned long parent_rate = clk_get_rate(c->parent); + unsigned long flags; + int ret = -EINVAL; int i; + + spin_lock_irqsave(&clock_register_lock, flags); + + val = clk_readl(c->reg); for (i = 1; i <= 4; i++) { if (rate == parent_rate / i) { val &= ~(BUS_CLK_DIV_MASK << c->reg_shift); @@ -415,10 +519,14 @@ static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate) clk_writel(val, c->reg); c->div = i; c->mul = 1; - return 0; + ret = 0; + break; } } - return -EINVAL; + + spin_unlock_irqrestore(&clock_register_lock, flags); + + return ret; } static struct clk_ops tegra_bus_ops = { @@ -428,24 +536,96 @@ static struct clk_ops tegra_bus_ops = { .set_rate = tegra2_bus_clk_set_rate, }; -/* PLL Functions */ -static int tegra2_pll_clk_wait_for_lock(struct clk *c) +/* Blink output functions */ + +static void tegra2_blink_clk_init(struct clk *c) { - ktime_t before; + u32 val; - before = ktime_get(); + val = pmc_readl(PMC_CTRL); + c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF; + c->mul = 1; + val = pmc_readl(c->reg); + + if (val & PMC_BLINK_TIMER_ENB) { + unsigned int on_off; + + on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) & + PMC_BLINK_TIMER_DATA_ON_MASK; + val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT; + val &= PMC_BLINK_TIMER_DATA_OFF_MASK; + on_off += val; + /* each tick in the blink timer is 4 32KHz clocks */ + c->div = on_off * 4; + } else { + c->div = 1; + } +} - while (!(clk_readl(c->reg + PLL_BASE) & PLL_BASE_LOCK)) { - if (ktime_us_delta(ktime_get(), before) > 5000) { - pr_err("Timed out waiting for lock bit on pll %s", - c->name); - return -1; - } +static int tegra2_blink_clk_enable(struct clk *c) +{ + u32 val; + + val = pmc_readl(PMC_DPD_PADS_ORIDE); + pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); + + val = pmc_readl(PMC_CTRL); + pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL); + + return 0; +} + +static void tegra2_blink_clk_disable(struct clk *c) +{ + u32 val; + + val = pmc_readl(PMC_CTRL); + pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL); + + val = pmc_readl(PMC_DPD_PADS_ORIDE); + pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); +} + +static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate) +{ + unsigned long parent_rate = clk_get_rate(c->parent); + if (rate >= parent_rate) { + c->div = 1; + pmc_writel(0, c->reg); + } else { + unsigned int on_off; + u32 val; + + on_off = DIV_ROUND_UP(parent_rate / 8, rate); + c->div = on_off * 8; + + val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) << + PMC_BLINK_TIMER_DATA_ON_SHIFT; + on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK; + on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT; + val |= on_off; + val |= PMC_BLINK_TIMER_ENB; + pmc_writel(val, c->reg); } return 0; } +static struct clk_ops tegra_blink_clk_ops = { + .init = &tegra2_blink_clk_init, + .enable = &tegra2_blink_clk_enable, + .disable = &tegra2_blink_clk_disable, + .set_rate = &tegra2_blink_clk_set_rate, +}; + +/* PLL Functions */ +static int tegra2_pll_clk_wait_for_lock(struct clk *c) +{ + udelay(c->u.pll.lock_delay); + + return 0; +} + static void tegra2_pll_clk_init(struct clk *c) { u32 val = clk_readl(c->reg + PLL_BASE); @@ -479,10 +659,6 @@ static int tegra2_pll_clk_enable(struct clk *c) val |= PLL_BASE_ENABLE; clk_writel(val, c->reg + PLL_BASE); - val = clk_readl(c->reg + PLL_MISC(c)); - val |= PLL_MISC_LOCK_ENABLE(c); - clk_writel(val, c->reg + PLL_MISC(c)); - tegra2_pll_clk_wait_for_lock(c); return 0; @@ -502,13 +678,12 @@ static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate) { u32 val; unsigned long input_rate; - const struct clk_pll_table *sel; + const struct clk_pll_freq_table *sel; pr_debug("%s: %s %lu\n", __func__, c->name, rate); - BUG_ON(c->refcnt != 0); - input_rate = c->parent->rate; - for (sel = c->pll_table; sel->input_rate != 0; sel++) { + input_rate = clk_get_rate(c->parent); + for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { if (sel->input_rate == input_rate && sel->output_rate == rate) { c->mul = sel->n; c->div = sel->m * sel->p; @@ -620,9 +795,11 @@ static int tegra2_pll_div_clk_enable(struct clk *c) { u32 val; u32 new_val; + unsigned long flags; pr_debug("%s: %s\n", __func__, c->name); if (c->flags & DIV_U71) { + spin_lock_irqsave(&clock_register_lock, flags); val = clk_readl(c->reg); new_val = val >> c->reg_shift; new_val &= 0xFFFF; @@ -632,12 +809,15 @@ static int tegra2_pll_div_clk_enable(struct clk *c) val &= ~(0xFFFF << c->reg_shift); val |= new_val << c->reg_shift; clk_writel(val, c->reg); + spin_unlock_irqrestore(&clock_register_lock, flags); return 0; } else if (c->flags & DIV_2) { BUG_ON(!(c->flags & PLLD)); + spin_lock_irqsave(&clock_register_lock, flags); val = clk_readl(c->reg); val &= ~PLLD_MISC_DIV_RST; clk_writel(val, c->reg); + spin_unlock_irqrestore(&clock_register_lock, flags); return 0; } return -EINVAL; @@ -647,9 +827,11 @@ static void tegra2_pll_div_clk_disable(struct clk *c) { u32 val; u32 new_val; + unsigned long flags; pr_debug("%s: %s\n", __func__, c->name); if (c->flags & DIV_U71) { + spin_lock_irqsave(&clock_register_lock, flags); val = clk_readl(c->reg); new_val = val >> c->reg_shift; new_val &= 0xFFFF; @@ -659,11 +841,14 @@ static void tegra2_pll_div_clk_disable(struct clk *c) val &= ~(0xFFFF << c->reg_shift); val |= new_val << c->reg_shift; clk_writel(val, c->reg); + spin_unlock_irqrestore(&clock_register_lock, flags); } else if (c->flags & DIV_2) { BUG_ON(!(c->flags & PLLD)); + spin_lock_irqsave(&clock_register_lock, flags); val = clk_readl(c->reg); val |= PLLD_MISC_DIV_RST; clk_writel(val, c->reg); + spin_unlock_irqrestore(&clock_register_lock, flags); } } @@ -672,10 +857,14 @@ static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate) u32 val; u32 new_val; int divider_u71; + unsigned long parent_rate = clk_get_rate(c->parent); + unsigned long flags; + pr_debug("%s: %s %lu\n", __func__, c->name, rate); if (c->flags & DIV_U71) { - divider_u71 = clk_div71_get_divider(c->parent->rate, rate); + divider_u71 = clk_div71_get_divider(parent_rate, rate); if (divider_u71 >= 0) { + spin_lock_irqsave(&clock_register_lock, flags); val = clk_readl(c->reg); new_val = val >> c->reg_shift; new_val &= 0xFFFF; @@ -689,10 +878,11 @@ static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate) clk_writel(val, c->reg); c->div = divider_u71 + 2; c->mul = 2; + spin_unlock_irqrestore(&clock_register_lock, flags); return 0; } } else if (c->flags & DIV_2) { - if (c->parent->rate == rate * 2) + if (parent_rate == rate * 2) return 0; } return -EINVAL; @@ -701,15 +891,16 @@ static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate) static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate) { int divider; + unsigned long parent_rate = clk_get_rate(c->parent); pr_debug("%s: %s %lu\n", __func__, c->name, rate); if (c->flags & DIV_U71) { - divider = clk_div71_get_divider(c->parent->rate, rate); + divider = clk_div71_get_divider(parent_rate, rate); if (divider < 0) return divider; - return c->parent->rate * 2 / (divider + 2); + return DIV_ROUND_UP(parent_rate * 2, divider + 2); } else if (c->flags & DIV_2) { - return c->parent->rate / 2; + return DIV_ROUND_UP(parent_rate, 2); } return -EINVAL; } @@ -755,9 +946,14 @@ static void tegra2_periph_clk_init(struct clk *c) } c->state = ON; + + if (!c->u.periph.clk_num) + return; + if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_ENB_BIT(c))) c->state = OFF; + if (!(c->flags & PERIPH_NO_RESET)) if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_ENB_BIT(c)) @@ -767,8 +963,20 @@ static void tegra2_periph_clk_init(struct clk *c) static int tegra2_periph_clk_enable(struct clk *c) { u32 val; + unsigned long flags; + int refcount; pr_debug("%s on clock %s\n", __func__, c->name); + if (!c->u.periph.clk_num) + return 0; + + spin_lock_irqsave(&clock_register_lock, flags); + + refcount = tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++; + + if (refcount > 1) + goto out; + clk_writel(PERIPH_CLK_TO_ENB_BIT(c), CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c)); if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET)) @@ -781,34 +989,48 @@ static int tegra2_periph_clk_enable(struct clk *c) val |= 0x3 << 24; clk_writel(val, c->reg); } + +out: + spin_unlock_irqrestore(&clock_register_lock, flags); + return 0; } static void tegra2_periph_clk_disable(struct clk *c) { + unsigned long flags; + pr_debug("%s on clock %s\n", __func__, c->name); - clk_writel(PERIPH_CLK_TO_ENB_BIT(c), - CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c)); -} + if (!c->u.periph.clk_num) + return; -void tegra2_periph_reset_deassert(struct clk *c) -{ - pr_debug("%s on clock %s\n", __func__, c->name); - if (!(c->flags & PERIPH_NO_RESET)) + spin_lock_irqsave(&clock_register_lock, flags); + + if (c->refcnt) + tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--; + + if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) clk_writel(PERIPH_CLK_TO_ENB_BIT(c), - RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c)); + CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c)); + + spin_unlock_irqrestore(&clock_register_lock, flags); } -void tegra2_periph_reset_assert(struct clk *c) +static void tegra2_periph_clk_reset(struct clk *c, bool assert) { - pr_debug("%s on clock %s\n", __func__, c->name); + unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR; + + pr_debug("%s %s on clock %s\n", __func__, + assert ? "assert" : "deassert", c->name); + + BUG_ON(!c->u.periph.clk_num); + if (!(c->flags & PERIPH_NO_RESET)) clk_writel(PERIPH_CLK_TO_ENB_BIT(c), - RST_DEVICES_SET + PERIPH_CLK_TO_ENB_SET_REG(c)); + base + PERIPH_CLK_TO_ENB_SET_REG(c)); } - static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p) { u32 val; @@ -821,12 +1043,12 @@ static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p) val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT; if (c->refcnt) - clk_enable_locked(p); + clk_enable(p); clk_writel(val, c->reg); if (c->refcnt && c->parent) - clk_disable_locked(c->parent); + clk_disable(c->parent); clk_reparent(c, p); return 0; @@ -840,9 +1062,10 @@ static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate) { u32 val; int divider; - pr_debug("%s: %lu\n", __func__, rate); + unsigned long parent_rate = clk_get_rate(c->parent); + if (c->flags & DIV_U71) { - divider = clk_div71_get_divider(c->parent->rate, rate); + divider = clk_div71_get_divider(parent_rate, rate); if (divider >= 0) { val = clk_readl(c->reg); val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK; @@ -853,7 +1076,7 @@ static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate) return 0; } } else if (c->flags & DIV_U16) { - divider = clk_div16_get_divider(c->parent->rate, rate); + divider = clk_div16_get_divider(parent_rate, rate); if (divider >= 0) { val = clk_readl(c->reg); val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK; @@ -863,7 +1086,7 @@ static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate) c->mul = 1; return 0; } - } else if (c->parent->rate <= rate) { + } else if (parent_rate <= rate) { c->div = 1; c->mul = 1; return 0; @@ -875,19 +1098,20 @@ static long tegra2_periph_clk_round_rate(struct clk *c, unsigned long rate) { int divider; + unsigned long parent_rate = clk_get_rate(c->parent); pr_debug("%s: %s %lu\n", __func__, c->name, rate); if (c->flags & DIV_U71) { - divider = clk_div71_get_divider(c->parent->rate, rate); + divider = clk_div71_get_divider(parent_rate, rate); if (divider < 0) return divider; - return c->parent->rate * 2 / (divider + 2); + return DIV_ROUND_UP(parent_rate * 2, divider + 2); } else if (c->flags & DIV_U16) { - divider = clk_div16_get_divider(c->parent->rate, rate); + divider = clk_div16_get_divider(parent_rate, rate); if (divider < 0) return divider; - return c->parent->rate / (divider + 1); + return DIV_ROUND_UP(parent_rate, divider + 1); } return -EINVAL; } @@ -899,6 +1123,71 @@ static struct clk_ops tegra_periph_clk_ops = { .set_parent = &tegra2_periph_clk_set_parent, .set_rate = &tegra2_periph_clk_set_rate, .round_rate = &tegra2_periph_clk_round_rate, + .reset = &tegra2_periph_clk_reset, +}; + +/* The SDMMC controllers have extra bits in the clock source register that + * adjust the delay between the clock and data to compenstate for delays + * on the PCB. */ +void tegra2_sdmmc_tap_delay(struct clk *c, int delay) +{ + u32 reg; + + delay = clamp(delay, 0, 15); + reg = clk_readl(c->reg); + reg &= ~SDMMC_CLK_INT_FB_DLY_MASK; + reg |= SDMMC_CLK_INT_FB_SEL; + reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT; + clk_writel(reg, c->reg); +} + +/* External memory controller clock ops */ +static void tegra2_emc_clk_init(struct clk *c) +{ + tegra2_periph_clk_init(c); + c->max_rate = clk_get_rate_locked(c); +} + +static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate) +{ + long new_rate = rate; + + new_rate = tegra_emc_round_rate(new_rate); + if (new_rate < 0) + return c->max_rate; + + BUG_ON(new_rate != tegra2_periph_clk_round_rate(c, new_rate)); + + return new_rate; +} + +static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate) +{ + int ret; + /* + * The Tegra2 memory controller has an interlock with the clock + * block that allows memory shadowed registers to be updated, + * and then transfer them to the main registers at the same + * time as the clock update without glitches. + */ + ret = tegra_emc_set_rate(rate); + if (ret < 0) + return ret; + + ret = tegra2_periph_clk_set_rate(c, rate); + udelay(1); + + return ret; +} + +static struct clk_ops tegra_emc_clk_ops = { + .init = &tegra2_emc_clk_init, + .enable = &tegra2_periph_clk_enable, + .disable = &tegra2_periph_clk_disable, + .set_parent = &tegra2_periph_clk_set_parent, + .set_rate = &tegra2_emc_clk_set_rate, + .round_rate = &tegra2_emc_clk_round_rate, + .reset = &tegra2_periph_clk_reset, }; /* Clock doubler ops */ @@ -907,6 +1196,10 @@ static void tegra2_clk_double_init(struct clk *c) c->mul = 2; c->div = 1; c->state = ON; + + if (!c->u.periph.clk_num) + return; + if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_ENB_BIT(c))) c->state = OFF; @@ -914,7 +1207,7 @@ static void tegra2_clk_double_init(struct clk *c) static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate) { - if (rate != 2 * c->parent->rate) + if (rate != 2 * clk_get_rate(c->parent)) return -EINVAL; c->mul = 2; c->div = 1; @@ -928,6 +1221,7 @@ static struct clk_ops tegra_clk_double_ops = { .set_rate = &tegra2_clk_double_set_rate, }; +/* Audio sync clock ops */ static void tegra2_audio_sync_clk_init(struct clk *c) { int source; @@ -964,12 +1258,12 @@ static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p) val |= sel->value; if (c->refcnt) - clk_enable_locked(p); + clk_enable(p); clk_writel(val, c->reg); if (c->refcnt && c->parent) - clk_disable_locked(c->parent); + clk_disable(c->parent); clk_reparent(c, p); return 0; @@ -979,33 +1273,153 @@ static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p) return -EINVAL; } -static int tegra2_audio_sync_clk_set_rate(struct clk *c, unsigned long rate) -{ - unsigned long parent_rate; - if (!c->parent) { - pr_err("%s: clock has no parent\n", __func__); - return -EINVAL; - } - parent_rate = c->parent->rate; - if (rate != parent_rate) { - pr_err("%s: %s/%ld differs from parent %s/%ld\n", - __func__, - c->name, rate, - c->parent->name, parent_rate); - return -EINVAL; - } - c->rate = parent_rate; - return 0; -} - static struct clk_ops tegra_audio_sync_clk_ops = { .init = tegra2_audio_sync_clk_init, .enable = tegra2_audio_sync_clk_enable, .disable = tegra2_audio_sync_clk_disable, - .set_rate = tegra2_audio_sync_clk_set_rate, .set_parent = tegra2_audio_sync_clk_set_parent, }; +/* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */ + +static void tegra2_cdev_clk_init(struct clk *c) +{ + /* We could un-tristate the cdev1 or cdev2 pingroup here; this is + * currently done in the pinmux code. */ + c->state = ON; + + BUG_ON(!c->u.periph.clk_num); + + if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) & + PERIPH_CLK_TO_ENB_BIT(c))) + c->state = OFF; +} + +static int tegra2_cdev_clk_enable(struct clk *c) +{ + BUG_ON(!c->u.periph.clk_num); + + clk_writel(PERIPH_CLK_TO_ENB_BIT(c), + CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c)); + return 0; +} + +static void tegra2_cdev_clk_disable(struct clk *c) +{ + BUG_ON(!c->u.periph.clk_num); + + clk_writel(PERIPH_CLK_TO_ENB_BIT(c), + CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c)); +} + +static struct clk_ops tegra_cdev_clk_ops = { + .init = &tegra2_cdev_clk_init, + .enable = &tegra2_cdev_clk_enable, + .disable = &tegra2_cdev_clk_disable, +}; + +/* shared bus ops */ +/* + * Some clocks may have multiple downstream users that need to request a + * higher clock rate. Shared bus clocks provide a unique shared_bus_user + * clock to each user. The frequency of the bus is set to the highest + * enabled shared_bus_user clock, with a minimum value set by the + * shared bus. + */ +static int tegra_clk_shared_bus_update(struct clk *bus) +{ + struct clk *c; + unsigned long rate = bus->min_rate; + + list_for_each_entry(c, &bus->shared_bus_list, u.shared_bus_user.node) + if (c->u.shared_bus_user.enabled) + rate = max(c->u.shared_bus_user.rate, rate); + + if (rate == clk_get_rate_locked(bus)) + return 0; + + return clk_set_rate_locked(bus, rate); +}; + +static void tegra_clk_shared_bus_init(struct clk *c) +{ + unsigned long flags; + + c->max_rate = c->parent->max_rate; + c->u.shared_bus_user.rate = c->parent->max_rate; + c->state = OFF; + c->set = true; + + spin_lock_irqsave(&c->parent->spinlock, flags); + + list_add_tail(&c->u.shared_bus_user.node, + &c->parent->shared_bus_list); + + spin_unlock_irqrestore(&c->parent->spinlock, flags); +} + +static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate) +{ + unsigned long flags; + int ret; + + rate = clk_round_rate(c->parent, rate); + if (rate < 0) + return rate; + + spin_lock_irqsave(&c->parent->spinlock, flags); + + c->u.shared_bus_user.rate = rate; + ret = tegra_clk_shared_bus_update(c->parent); + + spin_unlock_irqrestore(&c->parent->spinlock, flags); + + return ret; +} + +static long tegra_clk_shared_bus_round_rate(struct clk *c, unsigned long rate) +{ + return clk_round_rate(c->parent, rate); +} + +static int tegra_clk_shared_bus_enable(struct clk *c) +{ + unsigned long flags; + int ret; + + spin_lock_irqsave(&c->parent->spinlock, flags); + + c->u.shared_bus_user.enabled = true; + ret = tegra_clk_shared_bus_update(c->parent); + + spin_unlock_irqrestore(&c->parent->spinlock, flags); + + return ret; +} + +static void tegra_clk_shared_bus_disable(struct clk *c) +{ + unsigned long flags; + int ret; + + spin_lock_irqsave(&c->parent->spinlock, flags); + + c->u.shared_bus_user.enabled = false; + ret = tegra_clk_shared_bus_update(c->parent); + WARN_ON_ONCE(ret); + + spin_unlock_irqrestore(&c->parent->spinlock, flags); +} + +static struct clk_ops tegra_clk_shared_bus_ops = { + .init = tegra_clk_shared_bus_init, + .enable = tegra_clk_shared_bus_enable, + .disable = tegra_clk_shared_bus_disable, + .set_rate = tegra_clk_shared_bus_set_rate, + .round_rate = tegra_clk_shared_bus_round_rate, +}; + + /* Clock definitions */ static struct clk tegra_clk_32k = { .name = "clk_32k", @@ -1014,7 +1428,7 @@ static struct clk tegra_clk_32k = { .max_rate = 32768, }; -static struct clk_pll_table tegra_pll_s_table[] = { +static struct clk_pll_freq_table tegra_pll_s_freq_table[] = { {32768, 12000000, 366, 1, 1, 0}, {32768, 13000000, 397, 1, 1, 0}, {32768, 19200000, 586, 1, 1, 0}, @@ -1026,16 +1440,19 @@ static struct clk tegra_pll_s = { .name = "pll_s", .flags = PLL_ALT_MISC_REG, .ops = &tegra_pll_ops, - .reg = 0xf0, - .input_min = 32768, - .input_max = 32768, .parent = &tegra_clk_32k, - .cf_min = 0, /* FIXME */ - .cf_max = 0, /* FIXME */ - .vco_min = 12000000, - .vco_max = 26000000, - .pll_table = tegra_pll_s_table, .max_rate = 26000000, + .reg = 0xf0, + .u.pll = { + .input_min = 32768, + .input_max = 32768, + .cf_min = 0, /* FIXME */ + .cf_max = 0, /* FIXME */ + .vco_min = 12000000, + .vco_max = 26000000, + .freq_table = tegra_pll_s_freq_table, + .lock_delay = 300, + }, }; static struct clk_mux_sel tegra_clk_m_sel[] = { @@ -1043,18 +1460,18 @@ static struct clk_mux_sel tegra_clk_m_sel[] = { { .input = &tegra_pll_s, .value = 1}, { 0, 0}, }; + static struct clk tegra_clk_m = { .name = "clk_m", .flags = ENABLE_ON_INIT, .ops = &tegra_clk_m_ops, .inputs = tegra_clk_m_sel, .reg = 0x1fc, - .reg_mask = (1<<28), .reg_shift = 28, .max_rate = 26000000, }; -static struct clk_pll_table tegra_pll_c_table[] = { +static struct clk_pll_freq_table tegra_pll_c_freq_table[] = { { 0, 0, 0, 0, 0, 0 }, }; @@ -1063,15 +1480,18 @@ static struct clk tegra_pll_c = { .flags = PLL_HAS_CPCON, .ops = &tegra_pll_ops, .reg = 0x80, - .input_min = 2000000, - .input_max = 31000000, .parent = &tegra_clk_m, - .cf_min = 1000000, - .cf_max = 6000000, - .vco_min = 20000000, - .vco_max = 1400000000, - .pll_table = tegra_pll_c_table, .max_rate = 600000000, + .u.pll = { + .input_min = 2000000, + .input_max = 31000000, + .cf_min = 1000000, + .cf_max = 6000000, + .vco_min = 20000000, + .vco_max = 1400000000, + .freq_table = tegra_pll_c_freq_table, + .lock_delay = 300, + }, }; static struct clk tegra_pll_c_out1 = { @@ -1084,7 +1504,7 @@ static struct clk tegra_pll_c_out1 = { .max_rate = 600000000, }; -static struct clk_pll_table tegra_pll_m_table[] = { +static struct clk_pll_freq_table tegra_pll_m_freq_table[] = { { 12000000, 666000000, 666, 12, 1, 8}, { 13000000, 666000000, 666, 13, 1, 8}, { 19200000, 666000000, 555, 16, 1, 8}, @@ -1101,15 +1521,18 @@ static struct clk tegra_pll_m = { .flags = PLL_HAS_CPCON, .ops = &tegra_pll_ops, .reg = 0x90, - .input_min = 2000000, - .input_max = 31000000, .parent = &tegra_clk_m, - .cf_min = 1000000, - .cf_max = 6000000, - .vco_min = 20000000, - .vco_max = 1200000000, - .pll_table = tegra_pll_m_table, .max_rate = 800000000, + .u.pll = { + .input_min = 2000000, + .input_max = 31000000, + .cf_min = 1000000, + .cf_max = 6000000, + .vco_min = 20000000, + .vco_max = 1200000000, + .freq_table = tegra_pll_m_freq_table, + .lock_delay = 300, + }, }; static struct clk tegra_pll_m_out1 = { @@ -1122,7 +1545,7 @@ static struct clk tegra_pll_m_out1 = { .max_rate = 600000000, }; -static struct clk_pll_table tegra_pll_p_table[] = { +static struct clk_pll_freq_table tegra_pll_p_freq_table[] = { { 12000000, 216000000, 432, 12, 2, 8}, { 13000000, 216000000, 432, 13, 2, 8}, { 19200000, 216000000, 90, 4, 2, 1}, @@ -1139,15 +1562,18 @@ static struct clk tegra_pll_p = { .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, .ops = &tegra_pll_ops, .reg = 0xa0, - .input_min = 2000000, - .input_max = 31000000, .parent = &tegra_clk_m, - .cf_min = 1000000, - .cf_max = 6000000, - .vco_min = 20000000, - .vco_max = 1400000000, - .pll_table = tegra_pll_p_table, .max_rate = 432000000, + .u.pll = { + .input_min = 2000000, + .input_max = 31000000, + .cf_min = 1000000, + .cf_max = 6000000, + .vco_min = 20000000, + .vco_max = 1400000000, + .freq_table = tegra_pll_p_freq_table, + .lock_delay = 300, + }, }; static struct clk tegra_pll_p_out1 = { @@ -1190,11 +1616,9 @@ static struct clk tegra_pll_p_out4 = { .max_rate = 432000000, }; -static struct clk_pll_table tegra_pll_a_table[] = { +static struct clk_pll_freq_table tegra_pll_a_freq_table[] = { { 28800000, 56448000, 49, 25, 1, 1}, { 28800000, 73728000, 64, 25, 1, 1}, - { 28800000, 11289600, 49, 25, 1, 1}, - { 28800000, 12288000, 64, 25, 1, 1}, { 28800000, 24000000, 5, 6, 1, 1}, { 0, 0, 0, 0, 0, 0 }, }; @@ -1204,15 +1628,18 @@ static struct clk tegra_pll_a = { .flags = PLL_HAS_CPCON, .ops = &tegra_pll_ops, .reg = 0xb0, - .input_min = 2000000, - .input_max = 31000000, .parent = &tegra_pll_p_out1, - .cf_min = 1000000, - .cf_max = 6000000, - .vco_min = 20000000, - .vco_max = 1400000000, - .pll_table = tegra_pll_a_table, - .max_rate = 56448000, + .max_rate = 73728000, + .u.pll = { + .input_min = 2000000, + .input_max = 31000000, + .cf_min = 1000000, + .cf_max = 6000000, + .vco_min = 20000000, + .vco_max = 1400000000, + .freq_table = tegra_pll_a_freq_table, + .lock_delay = 300, + }, }; static struct clk tegra_pll_a_out0 = { @@ -1222,14 +1649,25 @@ static struct clk tegra_pll_a_out0 = { .parent = &tegra_pll_a, .reg = 0xb4, .reg_shift = 0, - .max_rate = 56448000, + .max_rate = 73728000, }; -static struct clk_pll_table tegra_pll_d_table[] = { +static struct clk_pll_freq_table tegra_pll_d_freq_table[] = { + { 12000000, 216000000, 216, 12, 1, 4}, + { 13000000, 216000000, 216, 13, 1, 4}, + { 19200000, 216000000, 135, 12, 1, 3}, + { 26000000, 216000000, 216, 26, 1, 4}, + + { 12000000, 594000000, 594, 12, 1, 8}, + { 13000000, 594000000, 594, 13, 1, 8}, + { 19200000, 594000000, 495, 16, 1, 8}, + { 26000000, 594000000, 594, 26, 1, 8}, + { 12000000, 1000000000, 1000, 12, 1, 12}, { 13000000, 1000000000, 1000, 13, 1, 12}, { 19200000, 1000000000, 625, 12, 1, 8}, { 26000000, 1000000000, 1000, 26, 1, 12}, + { 0, 0, 0, 0, 0, 0 }, }; @@ -1238,15 +1676,18 @@ static struct clk tegra_pll_d = { .flags = PLL_HAS_CPCON | PLLD, .ops = &tegra_pll_ops, .reg = 0xd0, - .input_min = 2000000, - .input_max = 40000000, .parent = &tegra_clk_m, - .cf_min = 1000000, - .cf_max = 6000000, - .vco_min = 40000000, - .vco_max = 1000000000, - .pll_table = tegra_pll_d_table, .max_rate = 1000000000, + .u.pll = { + .input_min = 2000000, + .input_max = 40000000, + .cf_min = 1000000, + .cf_max = 6000000, + .vco_min = 40000000, + .vco_max = 1000000000, + .freq_table = tegra_pll_d_freq_table, + .lock_delay = 1000, + }, }; static struct clk tegra_pll_d_out0 = { @@ -1257,7 +1698,7 @@ static struct clk tegra_pll_d_out0 = { .max_rate = 500000000, }; -static struct clk_pll_table tegra_pll_u_table[] = { +static struct clk_pll_freq_table tegra_pll_u_freq_table[] = { { 12000000, 480000000, 960, 12, 2, 0}, { 13000000, 480000000, 960, 13, 2, 0}, { 19200000, 480000000, 200, 4, 2, 0}, @@ -1270,18 +1711,21 @@ static struct clk tegra_pll_u = { .flags = PLLU, .ops = &tegra_pll_ops, .reg = 0xc0, - .input_min = 2000000, - .input_max = 40000000, .parent = &tegra_clk_m, - .cf_min = 1000000, - .cf_max = 6000000, - .vco_min = 480000000, - .vco_max = 960000000, - .pll_table = tegra_pll_u_table, .max_rate = 480000000, -}; - -static struct clk_pll_table tegra_pll_x_table[] = { + .u.pll = { + .input_min = 2000000, + .input_max = 40000000, + .cf_min = 1000000, + .cf_max = 6000000, + .vco_min = 480000000, + .vco_max = 960000000, + .freq_table = tegra_pll_u_freq_table, + .lock_delay = 1000, + }, +}; + +static struct clk_pll_freq_table tegra_pll_x_freq_table[] = { /* 1 GHz */ { 12000000, 1000000000, 1000, 12, 1, 12}, { 13000000, 1000000000, 1000, 13, 1, 12}, @@ -1307,10 +1751,10 @@ static struct clk_pll_table tegra_pll_x_table[] = { { 26000000, 760000000, 760, 26, 1, 12}, /* 608 MHz */ - { 12000000, 608000000, 760, 12, 1, 12}, - { 13000000, 608000000, 760, 13, 1, 12}, + { 12000000, 608000000, 608, 12, 1, 12}, + { 13000000, 608000000, 608, 13, 1, 12}, { 19200000, 608000000, 380, 12, 1, 8}, - { 26000000, 608000000, 760, 26, 1, 12}, + { 26000000, 608000000, 608, 26, 1, 12}, /* 456 MHz */ { 12000000, 456000000, 456, 12, 1, 12}, @@ -1332,18 +1776,21 @@ static struct clk tegra_pll_x = { .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG, .ops = &tegra_pllx_ops, .reg = 0xe0, - .input_min = 2000000, - .input_max = 31000000, .parent = &tegra_clk_m, - .cf_min = 1000000, - .cf_max = 6000000, - .vco_min = 20000000, - .vco_max = 1200000000, - .pll_table = tegra_pll_x_table, .max_rate = 1000000000, -}; - -static struct clk_pll_table tegra_pll_e_table[] = { + .u.pll = { + .input_min = 2000000, + .input_max = 31000000, + .cf_min = 1000000, + .cf_max = 6000000, + .vco_min = 20000000, + .vco_max = 1200000000, + .freq_table = tegra_pll_x_freq_table, + .lock_delay = 300, + }, +}; + +static struct clk_pll_freq_table tegra_pll_e_freq_table[] = { { 12000000, 100000000, 200, 24, 1, 0 }, { 0, 0, 0, 0, 0, 0 }, }; @@ -1352,23 +1799,49 @@ static struct clk tegra_pll_e = { .name = "pll_e", .flags = PLL_ALT_MISC_REG, .ops = &tegra_plle_ops, - .input_min = 12000000, - .input_max = 12000000, - .max_rate = 100000000, .parent = &tegra_clk_m, .reg = 0xe8, - .pll_table = tegra_pll_e_table, + .max_rate = 100000000, + .u.pll = { + .input_min = 12000000, + .input_max = 12000000, + .freq_table = tegra_pll_e_freq_table, + }, }; static struct clk tegra_clk_d = { .name = "clk_d", .flags = PERIPH_NO_RESET, .ops = &tegra_clk_double_ops, - .clk_num = 90, .reg = 0x34, .reg_shift = 12, .parent = &tegra_clk_m, .max_rate = 52000000, + .u.periph = { + .clk_num = 90, + }, +}; + +/* dap_mclk1, belongs to the cdev1 pingroup. */ +static struct clk tegra_clk_cdev1 = { + .name = "cdev1", + .ops = &tegra_cdev_clk_ops, + .rate = 26000000, + .max_rate = 26000000, + .u.periph = { + .clk_num = 94, + }, +}; + +/* dap_mclk2, belongs to the cdev2 pingroup. */ +static struct clk tegra_clk_cdev2 = { + .name = "cdev2", + .ops = &tegra_cdev_clk_ops, + .rate = 26000000, + .max_rate = 26000000, + .u.periph = { + .clk_num = 93, + }, }; /* initialized before peripheral clocks */ @@ -1394,7 +1867,7 @@ static struct clk tegra_clk_audio = { .name = "audio", .inputs = mux_audio_sync_clk, .reg = 0x38, - .max_rate = 24000000, + .max_rate = 73728000, .ops = &tegra_audio_sync_clk_ops }; @@ -1403,10 +1876,12 @@ static struct clk tegra_clk_audio_2x = { .flags = PERIPH_NO_RESET, .max_rate = 48000000, .ops = &tegra_clk_double_ops, - .clk_num = 89, .reg = 0x34, .reg_shift = 8, .parent = &tegra_clk_audio, + .u.periph = { + .clk_num = 89, + }, }; struct clk_lookup tegra_audio_clk_lookups[] = { @@ -1478,17 +1953,26 @@ static struct clk tegra_clk_sclk = { .inputs = mux_sclk, .reg = 0x28, .ops = &tegra_super_ops, - .max_rate = 600000000, + .max_rate = 240000000, + .min_rate = 120000000, }; static struct clk tegra_clk_virtual_cpu = { .name = "cpu", .parent = &tegra_clk_cclk, - .main = &tegra_pll_x, - .backup = &tegra_clk_m, .ops = &tegra_cpu_ops, .max_rate = 1000000000, - .dvfs = &tegra_dvfs_virtual_cpu_dvfs, + .u.cpu = { + .main = &tegra_pll_x, + .backup = &tegra_pll_p, + }, +}; + +static struct clk tegra_clk_cop = { + .name = "cop", + .parent = &tegra_clk_sclk, + .ops = &tegra_cop_ops, + .max_rate = 240000000, }; static struct clk tegra_clk_hclk = { @@ -1508,7 +1992,15 @@ static struct clk tegra_clk_pclk = { .reg = 0x30, .reg_shift = 0, .ops = &tegra_bus_ops, - .max_rate = 108000000, + .max_rate = 120000000, +}; + +static struct clk tegra_clk_blink = { + .name = "blink", + .parent = &tegra_clk_32k, + .reg = 0x40, + .ops = &tegra_blink_clk_ops, + .max_rate = 32768, }; static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = { @@ -1587,6 +2079,23 @@ static struct clk_mux_sel mux_clk_32k[] = { { 0, 0}, }; +static struct clk_mux_sel mux_pclk[] = { + { .input = &tegra_clk_pclk, .value = 0}, + { 0, 0}, +}; + +static struct clk tegra_clk_emc = { + .name = "emc", + .ops = &tegra_emc_clk_ops, + .reg = 0x19c, + .max_rate = 800000000, + .inputs = mux_pllm_pllc_pllp_clkm, + .flags = MUX | DIV_U71 | PERIPH_EMC_ENB, + .u.periph = { + .clk_num = 57, + }, +}; + #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \ { \ .name = _name, \ @@ -1595,19 +2104,32 @@ static struct clk_mux_sel mux_clk_32k[] = { .con_id = _con, \ }, \ .ops = &tegra_periph_clk_ops, \ - .clk_num = _clk_num, \ .reg = _reg, \ .inputs = _inputs, \ .flags = _flags, \ .max_rate = _max, \ + .u.periph = { \ + .clk_num = _clk_num, \ + }, \ + } + +#define SHARED_CLK(_name, _dev, _con, _parent) \ + { \ + .name = _name, \ + .lookup = { \ + .dev_id = _dev, \ + .con_id = _con, \ + }, \ + .ops = &tegra_clk_shared_bus_ops, \ + .parent = _parent, \ } -struct clk tegra_periph_clks[] = { +struct clk tegra_list_clks[] = { + PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 108000000, mux_pclk, 0), PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET), PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0), - PERIPH_CLK("i2s1", "i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71), - PERIPH_CLK("i2s2", "i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71), - /* FIXME: spdif has 2 clocks but 1 enable */ + PERIPH_CLK("i2s1", "tegra-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71), + PERIPH_CLK("i2s2", "tegra-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71), PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71), PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71), PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71), @@ -1620,13 +2142,15 @@ struct clk tegra_periph_clks[] = { PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), PERIPH_CLK("ide", "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ - /* FIXME: vfir shares an enable with uartb */ PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ - PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x160, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ - PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */ + PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ + PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0), + PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0), + PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0), + PERIPH_CLK("vde", "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */ PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */ /* FIXME: what is la? */ PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), @@ -1641,37 +2165,46 @@ struct clk tegra_periph_clks[] = { PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0), PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0), PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0), - PERIPH_CLK("uarta", "uart.0", NULL, 6, 0x178, 216000000, mux_pllp_pllc_pllm_clkm, MUX), - PERIPH_CLK("uartb", "uart.1", NULL, 7, 0x17c, 216000000, mux_pllp_pllc_pllm_clkm, MUX), - PERIPH_CLK("uartc", "uart.2", NULL, 55, 0x1a0, 216000000, mux_pllp_pllc_pllm_clkm, MUX), - PERIPH_CLK("uartd", "uart.3", NULL, 65, 0x1c0, 216000000, mux_pllp_pllc_pllm_clkm, MUX), - PERIPH_CLK("uarte", "uart.4", NULL, 66, 0x1c4, 216000000, mux_pllp_pllc_pllm_clkm, MUX), + PERIPH_CLK("uarta", "uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX), + PERIPH_CLK("uartb", "uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX), + PERIPH_CLK("uartc", "uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX), + PERIPH_CLK("uartd", "uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX), + PERIPH_CLK("uarte", "uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX), PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */ PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ - /* FIXME: vi and vi_sensor share an enable */ - PERIPH_CLK("vi", "vi", NULL, 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ - PERIPH_CLK("vi_sensor", "vi_sensor", NULL, 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */ + PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ + PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */ PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ - /* FIXME: cve and tvo share an enable */ PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ - PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ + PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ - PERIPH_CLK("disp1", "tegrafb.0", NULL, 27, 0x138, 190000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */ - PERIPH_CLK("disp2", "tegrafb.1", NULL, 26, 0x13c, 190000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */ + PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */ + PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */ PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */ PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */ PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */ - PERIPH_CLK("emc", "emc", NULL, 57, 0x19c, 800000000, mux_pllm_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_EMC_ENB), PERIPH_CLK("dsi", "dsi", NULL, 48, 0, 500000000, mux_plld, 0), /* scales with voltage */ - PERIPH_CLK("csi", "csi", NULL, 52, 0, 72000000, mux_pllp_out3, 0), - PERIPH_CLK("isp", "isp", NULL, 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */ - PERIPH_CLK("csus", "csus", NULL, 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET), + PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0), + PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */ + PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET), PERIPH_CLK("pex", NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET), PERIPH_CLK("afi", NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET), PERIPH_CLK("pcie_xclk", NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET), + + SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sclk), + SHARED_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc), + SHARED_CLK("cpu.emc", "cpu", "emc", &tegra_clk_emc), + SHARED_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc), + SHARED_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc), + SHARED_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc), + SHARED_CLK("host.emc", "tegra_grhost", "emc", &tegra_clk_emc), + SHARED_CLK("usbd.emc", "fsl-tegra-udc", "emc", &tegra_clk_emc), + SHARED_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc), + SHARED_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc), + SHARED_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc), }; #define CLK_DUPLICATE(_name, _dev, _con) \ @@ -1693,9 +2226,22 @@ struct clk_duplicate tegra_clk_duplicates[] = { CLK_DUPLICATE("uartc", "tegra_uart.2", NULL), CLK_DUPLICATE("uartd", "tegra_uart.3", NULL), CLK_DUPLICATE("uarte", "tegra_uart.4", NULL), - CLK_DUPLICATE("host1x", "tegrafb.0", "host1x"), - CLK_DUPLICATE("host1x", "tegrafb.1", "host1x"), + CLK_DUPLICATE("usbd", "utmip-pad", NULL), CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL), + CLK_DUPLICATE("usbd", "tegra-otg", NULL), + CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"), + CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"), + CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL), + CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL), + CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL), + CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL), + CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"), + CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"), + CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"), + CLK_DUPLICATE("epp", "tegra_grhost", "epp"), + CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"), + CLK_DUPLICATE("cop", "tegra-avp", "cop"), + CLK_DUPLICATE("vde", "tegra-aes", "vde"), }; #define CLK(dev, con, ck) \ @@ -1705,68 +2251,70 @@ struct clk_duplicate tegra_clk_duplicates[] = { .clk = ck, \ } -struct clk_lookup tegra_clk_lookups[] = { - /* external root sources */ - CLK(NULL, "32k_clk", &tegra_clk_32k), - CLK(NULL, "pll_s", &tegra_pll_s), - CLK(NULL, "clk_m", &tegra_clk_m), - CLK(NULL, "pll_m", &tegra_pll_m), - CLK(NULL, "pll_m_out1", &tegra_pll_m_out1), - CLK(NULL, "pll_c", &tegra_pll_c), - CLK(NULL, "pll_c_out1", &tegra_pll_c_out1), - CLK(NULL, "pll_p", &tegra_pll_p), - CLK(NULL, "pll_p_out1", &tegra_pll_p_out1), - CLK(NULL, "pll_p_out2", &tegra_pll_p_out2), - CLK(NULL, "pll_p_out3", &tegra_pll_p_out3), - CLK(NULL, "pll_p_out4", &tegra_pll_p_out4), - CLK(NULL, "pll_a", &tegra_pll_a), - CLK(NULL, "pll_a_out0", &tegra_pll_a_out0), - CLK(NULL, "pll_d", &tegra_pll_d), - CLK(NULL, "pll_d_out0", &tegra_pll_d_out0), - CLK(NULL, "pll_u", &tegra_pll_u), - CLK(NULL, "pll_x", &tegra_pll_x), - CLK(NULL, "pll_e", &tegra_pll_e), - CLK(NULL, "cclk", &tegra_clk_cclk), - CLK(NULL, "sclk", &tegra_clk_sclk), - CLK(NULL, "hclk", &tegra_clk_hclk), - CLK(NULL, "pclk", &tegra_clk_pclk), - CLK(NULL, "clk_d", &tegra_clk_d), - CLK(NULL, "cpu", &tegra_clk_virtual_cpu), -}; +struct clk *tegra_ptr_clks[] = { + &tegra_clk_32k, + &tegra_pll_s, + &tegra_clk_m, + &tegra_pll_m, + &tegra_pll_m_out1, + &tegra_pll_c, + &tegra_pll_c_out1, + &tegra_pll_p, + &tegra_pll_p_out1, + &tegra_pll_p_out2, + &tegra_pll_p_out3, + &tegra_pll_p_out4, + &tegra_pll_a, + &tegra_pll_a_out0, + &tegra_pll_d, + &tegra_pll_d_out0, + &tegra_pll_u, + &tegra_pll_x, + &tegra_pll_e, + &tegra_clk_cclk, + &tegra_clk_sclk, + &tegra_clk_hclk, + &tegra_clk_pclk, + &tegra_clk_d, + &tegra_clk_cdev1, + &tegra_clk_cdev2, + &tegra_clk_virtual_cpu, + &tegra_clk_blink, + &tegra_clk_cop, + &tegra_clk_emc, +}; + +static void tegra2_init_one_clock(struct clk *c) +{ + clk_init(c); + INIT_LIST_HEAD(&c->shared_bus_list); + if (!c->lookup.dev_id && !c->lookup.con_id) + c->lookup.con_id = c->name; + c->lookup.clk = c; + clkdev_add(&c->lookup); +} void __init tegra2_init_clocks(void) { int i; - struct clk_lookup *cl; struct clk *c; - struct clk_duplicate *cd; - - for (i = 0; i < ARRAY_SIZE(tegra_clk_lookups); i++) { - cl = &tegra_clk_lookups[i]; - clk_init(cl->clk); - clkdev_add(cl); - } - for (i = 0; i < ARRAY_SIZE(tegra_periph_clks); i++) { - c = &tegra_periph_clks[i]; - cl = &c->lookup; - cl->clk = c; + for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++) + tegra2_init_one_clock(tegra_ptr_clks[i]); - clk_init(cl->clk); - clkdev_add(cl); - } + for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++) + tegra2_init_one_clock(&tegra_list_clks[i]); for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) { - cd = &tegra_clk_duplicates[i]; - c = tegra_get_clock_by_name(cd->name); - if (c) { - cl = &cd->lookup; - cl->clk = c; - clkdev_add(cl); - } else { + c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name); + if (!c) { pr_err("%s: Unknown duplicate clock %s\n", __func__, - cd->name); + tegra_clk_duplicates[i].name); + continue; } + + tegra_clk_duplicates[i].lookup.clk = c; + clkdev_add(&tegra_clk_duplicates[i].lookup); } init_audio_sync_clock_mux(); @@ -1774,7 +2322,7 @@ void __init tegra2_init_clocks(void) #ifdef CONFIG_PM static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM + - PERIPH_CLK_SOURCE_NUM + 3]; + PERIPH_CLK_SOURCE_NUM + 22]; void tegra_clk_suspend(void) { @@ -1782,6 +2330,29 @@ void tegra_clk_suspend(void) u32 *ctx = clk_rst_suspend; *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK; + *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE); + *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c)); + *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE); + *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a)); + *ctx++ = clk_readl(tegra_pll_s.reg + PLL_BASE); + *ctx++ = clk_readl(tegra_pll_s.reg + PLL_MISC(&tegra_pll_s)); + *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE); + *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d)); + *ctx++ = clk_readl(tegra_pll_u.reg + PLL_BASE); + *ctx++ = clk_readl(tegra_pll_u.reg + PLL_MISC(&tegra_pll_u)); + + *ctx++ = clk_readl(tegra_pll_m_out1.reg); + *ctx++ = clk_readl(tegra_pll_a_out0.reg); + *ctx++ = clk_readl(tegra_pll_c_out1.reg); + + *ctx++ = clk_readl(tegra_clk_cclk.reg); + *ctx++ = clk_readl(tegra_clk_cclk.reg + SUPER_CLK_DIVIDER); + + *ctx++ = clk_readl(tegra_clk_sclk.reg); + *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER); + *ctx++ = clk_readl(tegra_clk_pclk.reg); + + *ctx++ = clk_readl(tegra_clk_audio.reg); for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC; off += 4) { @@ -1800,6 +2371,8 @@ void tegra_clk_suspend(void) *ctx++ = clk_readl(MISC_CLK_ENB); *ctx++ = clk_readl(CLK_MASK_ARM); + + BUG_ON(ctx - clk_rst_suspend != ARRAY_SIZE(clk_rst_suspend)); } void tegra_clk_resume(void) @@ -1812,6 +2385,31 @@ void tegra_clk_resume(void) val |= *ctx++; clk_writel(val, OSC_CTRL); + clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE); + clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c)); + clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE); + clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a)); + clk_writel(*ctx++, tegra_pll_s.reg + PLL_BASE); + clk_writel(*ctx++, tegra_pll_s.reg + PLL_MISC(&tegra_pll_s)); + clk_writel(*ctx++, tegra_pll_d.reg + PLL_BASE); + clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d)); + clk_writel(*ctx++, tegra_pll_u.reg + PLL_BASE); + clk_writel(*ctx++, tegra_pll_u.reg + PLL_MISC(&tegra_pll_u)); + udelay(1000); + + clk_writel(*ctx++, tegra_pll_m_out1.reg); + clk_writel(*ctx++, tegra_pll_a_out0.reg); + clk_writel(*ctx++, tegra_pll_c_out1.reg); + + clk_writel(*ctx++, tegra_clk_cclk.reg); + clk_writel(*ctx++, tegra_clk_cclk.reg + SUPER_CLK_DIVIDER); + + clk_writel(*ctx++, tegra_clk_sclk.reg); + clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER); + clk_writel(*ctx++, tegra_clk_pclk.reg); + + clk_writel(*ctx++, tegra_clk_audio.reg); + /* enable all clocks before configuring clock sources */ clk_writel(0xbffffff9ul, CLK_OUT_ENB); clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4); diff --git a/arch/arm/mach-tegra/tegra2_dvfs.c b/arch/arm/mach-tegra/tegra2_dvfs.c deleted file mode 100644 index 5529c238dd77..000000000000 --- a/arch/arm/mach-tegra/tegra2_dvfs.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * arch/arm/mach-tegra/tegra2_dvfs.c - * - * Copyright (C) 2010 Google, Inc. - * - * Author: - * Colin Cross <ccross@google.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/kernel.h> - -#include "clock.h" -#include "tegra2_dvfs.h" - -static struct dvfs_table virtual_cpu_process_0[] = { - {314000000, 750}, - {456000000, 825}, - {608000000, 900}, - {760000000, 975}, - {817000000, 1000}, - {912000000, 1050}, - {1000000000, 1100}, - {0, 0}, -}; - -static struct dvfs_table virtual_cpu_process_1[] = { - {314000000, 750}, - {456000000, 825}, - {618000000, 900}, - {770000000, 975}, - {827000000, 1000}, - {922000000, 1050}, - {1000000000, 1100}, - {0, 0}, -}; - -static struct dvfs_table virtual_cpu_process_2[] = { - {494000000, 750}, - {675000000, 825}, - {817000000, 875}, - {922000000, 925}, - {1000000000, 975}, - {0, 0}, -}; - -static struct dvfs_table virtual_cpu_process_3[] = { - {730000000, 750}, - {760000000, 775}, - {845000000, 800}, - {1000000000, 875}, - {0, 0}, -}; - -struct dvfs tegra_dvfs_virtual_cpu_dvfs = { - .reg_id = "vdd_cpu", - .process_id_table = { - { - .process_id = 0, - .table = virtual_cpu_process_0, - }, - { - .process_id = 1, - .table = virtual_cpu_process_1, - }, - { - .process_id = 2, - .table = virtual_cpu_process_2, - }, - { - .process_id = 3, - .table = virtual_cpu_process_3, - }, - }, - .process_id_table_length = 4, - .cpu = 1, -}; diff --git a/arch/arm/mach-tegra/tegra2_emc.c b/arch/arm/mach-tegra/tegra2_emc.c new file mode 100644 index 000000000000..0f7ae6e90b55 --- /dev/null +++ b/arch/arm/mach-tegra/tegra2_emc.c @@ -0,0 +1,178 @@ +/* + * Copyright (C) 2011 Google, Inc. + * + * Author: + * Colin Cross <ccross@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> + +#include <mach/iomap.h> + +#include "tegra2_emc.h" + +#ifdef CONFIG_TEGRA_EMC_SCALING_ENABLE +static bool emc_enable = true; +#else +static bool emc_enable; +#endif +module_param(emc_enable, bool, 0644); + +static void __iomem *emc = IO_ADDRESS(TEGRA_EMC_BASE); +static const struct tegra_emc_table *tegra_emc_table; +static int tegra_emc_table_size; + +static inline void emc_writel(u32 val, unsigned long addr) +{ + writel(val, emc + addr); +} + +static inline u32 emc_readl(unsigned long addr) +{ + return readl(emc + addr); +} + +static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = { + 0x2c, /* RC */ + 0x30, /* RFC */ + 0x34, /* RAS */ + 0x38, /* RP */ + 0x3c, /* R2W */ + 0x40, /* W2R */ + 0x44, /* R2P */ + 0x48, /* W2P */ + 0x4c, /* RD_RCD */ + 0x50, /* WR_RCD */ + 0x54, /* RRD */ + 0x58, /* REXT */ + 0x5c, /* WDV */ + 0x60, /* QUSE */ + 0x64, /* QRST */ + 0x68, /* QSAFE */ + 0x6c, /* RDV */ + 0x70, /* REFRESH */ + 0x74, /* BURST_REFRESH_NUM */ + 0x78, /* PDEX2WR */ + 0x7c, /* PDEX2RD */ + 0x80, /* PCHG2PDEN */ + 0x84, /* ACT2PDEN */ + 0x88, /* AR2PDEN */ + 0x8c, /* RW2PDEN */ + 0x90, /* TXSR */ + 0x94, /* TCKE */ + 0x98, /* TFAW */ + 0x9c, /* TRPAB */ + 0xa0, /* TCLKSTABLE */ + 0xa4, /* TCLKSTOP */ + 0xa8, /* TREFBW */ + 0xac, /* QUSE_EXTRA */ + 0x114, /* FBIO_CFG6 */ + 0xb0, /* ODT_WRITE */ + 0xb4, /* ODT_READ */ + 0x104, /* FBIO_CFG5 */ + 0x2bc, /* CFG_DIG_DLL */ + 0x2c0, /* DLL_XFORM_DQS */ + 0x2c4, /* DLL_XFORM_QUSE */ + 0x2e0, /* ZCAL_REF_CNT */ + 0x2e4, /* ZCAL_WAIT_CNT */ + 0x2a8, /* AUTO_CAL_INTERVAL */ + 0x2d0, /* CFG_CLKTRIM_0 */ + 0x2d4, /* CFG_CLKTRIM_1 */ + 0x2d8, /* CFG_CLKTRIM_2 */ +}; + +/* Select the closest EMC rate that is higher than the requested rate */ +long tegra_emc_round_rate(unsigned long rate) +{ + int i; + int best = -1; + unsigned long distance = ULONG_MAX; + + if (!tegra_emc_table) + return -EINVAL; + + if (!emc_enable) + return -EINVAL; + + pr_debug("%s: %lu\n", __func__, rate); + + /* + * The EMC clock rate is twice the bus rate, and the bus rate is + * measured in kHz + */ + rate = rate / 2 / 1000; + + for (i = 0; i < tegra_emc_table_size; i++) { + if (tegra_emc_table[i].rate >= rate && + (tegra_emc_table[i].rate - rate) < distance) { + distance = tegra_emc_table[i].rate - rate; + best = i; + } + } + + if (best < 0) + return -EINVAL; + + pr_debug("%s: using %lu\n", __func__, tegra_emc_table[best].rate); + + return tegra_emc_table[best].rate * 2 * 1000; +} + +/* + * The EMC registers have shadow registers. When the EMC clock is updated + * in the clock controller, the shadow registers are copied to the active + * registers, allowing glitchless memory bus frequency changes. + * This function updates the shadow registers for a new clock frequency, + * and relies on the clock lock on the emc clock to avoid races between + * multiple frequency changes + */ +int tegra_emc_set_rate(unsigned long rate) +{ + int i; + int j; + + if (!tegra_emc_table) + return -EINVAL; + + /* + * The EMC clock rate is twice the bus rate, and the bus rate is + * measured in kHz + */ + rate = rate / 2 / 1000; + + for (i = 0; i < tegra_emc_table_size; i++) + if (tegra_emc_table[i].rate == rate) + break; + + if (i >= tegra_emc_table_size) + return -EINVAL; + + pr_debug("%s: setting to %lu\n", __func__, rate); + + for (j = 0; j < TEGRA_EMC_NUM_REGS; j++) + emc_writel(tegra_emc_table[i].regs[j], emc_reg_addr[j]); + + emc_readl(tegra_emc_table[i].regs[TEGRA_EMC_NUM_REGS - 1]); + + return 0; +} + +void tegra_init_emc(const struct tegra_emc_table *table, int table_size) +{ + tegra_emc_table = table; + tegra_emc_table_size = table_size; +} diff --git a/arch/arm/mach-tegra/tegra2_emc.h b/arch/arm/mach-tegra/tegra2_emc.h new file mode 100644 index 000000000000..19f08cb31603 --- /dev/null +++ b/arch/arm/mach-tegra/tegra2_emc.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2011 Google, Inc. + * + * Author: + * Colin Cross <ccross@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#define TEGRA_EMC_NUM_REGS 46 + +struct tegra_emc_table { + unsigned long rate; + u32 regs[TEGRA_EMC_NUM_REGS]; +}; + +int tegra_emc_set_rate(unsigned long rate); +long tegra_emc_round_rate(unsigned long rate); +void tegra_init_emc(const struct tegra_emc_table *table, int table_size); diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c index 7b8ad1f98f44..0fcb1eb4214d 100644 --- a/arch/arm/mach-tegra/timer.c +++ b/arch/arm/mach-tegra/timer.c @@ -18,6 +18,7 @@ */ #include <linux/init.h> +#include <linux/err.h> #include <linux/sched.h> #include <linux/time.h> #include <linux/interrupt.h> @@ -33,10 +34,15 @@ #include <mach/iomap.h> #include <mach/irqs.h> +#include <mach/suspend.h> #include "board.h" #include "clock.h" +#define RTC_SECONDS 0x08 +#define RTC_SHADOW_SECONDS 0x0c +#define RTC_MILLISECONDS 0x10 + #define TIMERUS_CNTR_1US 0x10 #define TIMERUS_USEC_CFG 0x14 #define TIMERUS_CNTR_FREEZE 0x4c @@ -49,9 +55,11 @@ #define TIMER_PTV 0x0 #define TIMER_PCR 0x4 -struct tegra_timer; - static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE); +static void __iomem *rtc_base = IO_ADDRESS(TEGRA_RTC_BASE); + +static struct timespec persistent_ts; +static u64 persistent_ms, last_persistent_ms; #define timer_writel(value, reg) \ __raw_writel(value, (u32)timer_reg_base + (reg)) @@ -132,6 +140,42 @@ static void notrace tegra_update_sched_clock(void) update_sched_clock(&cd, cyc, (u32)~0); } +/* + * tegra_rtc_read - Reads the Tegra RTC registers + * Care must be taken that this funciton is not called while the + * tegra_rtc driver could be executing to avoid race conditions + * on the RTC shadow register + */ +u64 tegra_rtc_read_ms(void) +{ + u32 ms = readl(rtc_base + RTC_MILLISECONDS); + u32 s = readl(rtc_base + RTC_SHADOW_SECONDS); + return (u64)s * MSEC_PER_SEC + ms; +} + +/* + * read_persistent_clock - Return time from a persistent clock. + * + * Reads the time from a source which isn't disabled during PM, the + * 32k sync timer. Convert the cycles elapsed since last read into + * nsecs and adds to a monotonically increasing timespec. + * Care must be taken that this funciton is not called while the + * tegra_rtc driver could be executing to avoid race conditions + * on the RTC shadow register + */ +void read_persistent_clock(struct timespec *ts) +{ + u64 delta; + struct timespec *tsp = &persistent_ts; + + last_persistent_ms = persistent_ms; + persistent_ms = tegra_rtc_read_ms(); + delta = persistent_ms - last_persistent_ms; + + timespec_add_ns(tsp, delta * NSEC_PER_MSEC); + *ts = *tsp; +} + static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *evt = (struct clock_event_device *)dev_id; @@ -150,9 +194,22 @@ static struct irqaction tegra_timer_irq = { static void __init tegra_init_timer(void) { + struct clk *clk; unsigned long rate = clk_measure_input_freq(); int ret; + clk = clk_get_sys("timer", NULL); + BUG_ON(IS_ERR(clk)); + clk_enable(clk); + + /* + * rtc registers are used by read_persistent_clock, keep the rtc clock + * enabled + */ + clk = clk_get_sys("rtc-tegra", NULL); + BUG_ON(IS_ERR(clk)); + clk_enable(clk); + #ifdef CONFIG_HAVE_ARM_TWD twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600); #endif @@ -196,10 +253,22 @@ static void __init tegra_init_timer(void) tegra_clockevent.cpumask = cpu_all_mask; tegra_clockevent.irq = tegra_timer_irq.irq; clockevents_register_device(&tegra_clockevent); - - return; } struct sys_timer tegra_timer = { .init = tegra_init_timer, }; + +#ifdef CONFIG_PM +static u32 usec_config; + +void tegra_timer_suspend(void) +{ + usec_config = timer_readl(TIMERUS_USEC_CFG); +} + +void tegra_timer_resume(void) +{ + timer_writel(usec_config, TIMERUS_USEC_CFG); +} +#endif diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c new file mode 100644 index 000000000000..88081bb3ec52 --- /dev/null +++ b/arch/arm/mach-tegra/usb_phy.c @@ -0,0 +1,795 @@ +/* + * arch/arm/mach-tegra/usb_phy.c + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Erik Gilling <konkers@google.com> + * Benoit Goby <benoit@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/resource.h> +#include <linux/delay.h> +#include <linux/slab.h> +#include <linux/err.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/gpio.h> +#include <linux/usb/otg.h> +#include <linux/usb/ulpi.h> +#include <asm/mach-types.h> +#include <mach/usb_phy.h> +#include <mach/iomap.h> + +#define ULPI_VIEWPORT 0x170 + +#define USB_PORTSC1 0x184 +#define USB_PORTSC1_PTS(x) (((x) & 0x3) << 30) +#define USB_PORTSC1_PSPD(x) (((x) & 0x3) << 26) +#define USB_PORTSC1_PHCD (1 << 23) +#define USB_PORTSC1_WKOC (1 << 22) +#define USB_PORTSC1_WKDS (1 << 21) +#define USB_PORTSC1_WKCN (1 << 20) +#define USB_PORTSC1_PTC(x) (((x) & 0xf) << 16) +#define USB_PORTSC1_PP (1 << 12) +#define USB_PORTSC1_SUSP (1 << 7) +#define USB_PORTSC1_PE (1 << 2) +#define USB_PORTSC1_CCS (1 << 0) + +#define USB_SUSP_CTRL 0x400 +#define USB_WAKE_ON_CNNT_EN_DEV (1 << 3) +#define USB_WAKE_ON_DISCON_EN_DEV (1 << 4) +#define USB_SUSP_CLR (1 << 5) +#define USB_PHY_CLK_VALID (1 << 7) +#define UTMIP_RESET (1 << 11) +#define UHSIC_RESET (1 << 11) +#define UTMIP_PHY_ENABLE (1 << 12) +#define ULPI_PHY_ENABLE (1 << 13) +#define USB_SUSP_SET (1 << 14) +#define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16) + +#define USB1_LEGACY_CTRL 0x410 +#define USB1_NO_LEGACY_MODE (1 << 0) +#define USB1_VBUS_SENSE_CTL_MASK (3 << 1) +#define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1) +#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \ + (1 << 1) +#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1) +#define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1) + +#define ULPI_TIMING_CTRL_0 0x424 +#define ULPI_OUTPUT_PINMUX_BYP (1 << 10) +#define ULPI_CLKOUT_PINMUX_BYP (1 << 11) + +#define ULPI_TIMING_CTRL_1 0x428 +#define ULPI_DATA_TRIMMER_LOAD (1 << 0) +#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) +#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) +#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) +#define ULPI_DIR_TRIMMER_LOAD (1 << 24) +#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) + +#define UTMIP_PLL_CFG1 0x804 +#define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) +#define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) + +#define UTMIP_XCVR_CFG0 0x808 +#define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0) +#define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8) +#define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10) +#define UTMIP_FORCE_PD_POWERDOWN (1 << 14) +#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) +#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) +#define UTMIP_XCVR_HSSLEW_MSB(x) (((x) & 0x7f) << 25) + +#define UTMIP_BIAS_CFG0 0x80c +#define UTMIP_OTGPD (1 << 11) +#define UTMIP_BIASPD (1 << 10) + +#define UTMIP_HSRX_CFG0 0x810 +#define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10) +#define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15) + +#define UTMIP_HSRX_CFG1 0x814 +#define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1) + +#define UTMIP_TX_CFG0 0x820 +#define UTMIP_FS_PREABMLE_J (1 << 19) +#define UTMIP_HS_DISCON_DISABLE (1 << 8) + +#define UTMIP_MISC_CFG0 0x824 +#define UTMIP_DPDM_OBSERVE (1 << 26) +#define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27) +#define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf) +#define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe) +#define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd) +#define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc) +#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22) + +#define UTMIP_MISC_CFG1 0x828 +#define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18) +#define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6) + +#define UTMIP_DEBOUNCE_CFG0 0x82c +#define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0) + +#define UTMIP_BAT_CHRG_CFG0 0x830 +#define UTMIP_PD_CHRG (1 << 0) + +#define UTMIP_SPARE_CFG0 0x834 +#define FUSE_SETUP_SEL (1 << 3) + +#define UTMIP_XCVR_CFG1 0x838 +#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) +#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) +#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) +#define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18) + +#define UTMIP_BIAS_CFG1 0x83c +#define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3) + +static DEFINE_SPINLOCK(utmip_pad_lock); +static int utmip_pad_count; + +struct tegra_xtal_freq { + int freq; + u8 enable_delay; + u8 stable_count; + u8 active_delay; + u8 xtal_freq_count; + u16 debounce; +}; + +static const struct tegra_xtal_freq tegra_freq_table[] = { + { + .freq = 12000000, + .enable_delay = 0x02, + .stable_count = 0x2F, + .active_delay = 0x04, + .xtal_freq_count = 0x76, + .debounce = 0x7530, + }, + { + .freq = 13000000, + .enable_delay = 0x02, + .stable_count = 0x33, + .active_delay = 0x05, + .xtal_freq_count = 0x7F, + .debounce = 0x7EF4, + }, + { + .freq = 19200000, + .enable_delay = 0x03, + .stable_count = 0x4B, + .active_delay = 0x06, + .xtal_freq_count = 0xBB, + .debounce = 0xBB80, + }, + { + .freq = 26000000, + .enable_delay = 0x04, + .stable_count = 0x66, + .active_delay = 0x09, + .xtal_freq_count = 0xFE, + .debounce = 0xFDE8, + }, +}; + +static struct tegra_utmip_config utmip_default[] = { + [0] = { + .hssync_start_delay = 9, + .idle_wait_delay = 17, + .elastic_limit = 16, + .term_range_adj = 6, + .xcvr_setup = 9, + .xcvr_lsfslew = 1, + .xcvr_lsrslew = 1, + }, + [2] = { + .hssync_start_delay = 9, + .idle_wait_delay = 17, + .elastic_limit = 16, + .term_range_adj = 6, + .xcvr_setup = 9, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + }, +}; + +static inline bool phy_is_ulpi(struct tegra_usb_phy *phy) +{ + return (phy->instance == 1); +} + +static int utmip_pad_open(struct tegra_usb_phy *phy) +{ + phy->pad_clk = clk_get_sys("utmip-pad", NULL); + if (IS_ERR(phy->pad_clk)) { + pr_err("%s: can't get utmip pad clock\n", __func__); + return PTR_ERR(phy->pad_clk); + } + + if (phy->instance == 0) { + phy->pad_regs = phy->regs; + } else { + phy->pad_regs = ioremap(TEGRA_USB_BASE, TEGRA_USB_SIZE); + if (!phy->pad_regs) { + pr_err("%s: can't remap usb registers\n", __func__); + clk_put(phy->pad_clk); + return -ENOMEM; + } + } + return 0; +} + +static void utmip_pad_close(struct tegra_usb_phy *phy) +{ + if (phy->instance != 0) + iounmap(phy->pad_regs); + clk_put(phy->pad_clk); +} + +static void utmip_pad_power_on(struct tegra_usb_phy *phy) +{ + unsigned long val, flags; + void __iomem *base = phy->pad_regs; + + clk_enable(phy->pad_clk); + + spin_lock_irqsave(&utmip_pad_lock, flags); + + if (utmip_pad_count++ == 0) { + val = readl(base + UTMIP_BIAS_CFG0); + val &= ~(UTMIP_OTGPD | UTMIP_BIASPD); + writel(val, base + UTMIP_BIAS_CFG0); + } + + spin_unlock_irqrestore(&utmip_pad_lock, flags); + + clk_disable(phy->pad_clk); +} + +static int utmip_pad_power_off(struct tegra_usb_phy *phy) +{ + unsigned long val, flags; + void __iomem *base = phy->pad_regs; + + if (!utmip_pad_count) { + pr_err("%s: utmip pad already powered off\n", __func__); + return -EINVAL; + } + + clk_enable(phy->pad_clk); + + spin_lock_irqsave(&utmip_pad_lock, flags); + + if (--utmip_pad_count == 0) { + val = readl(base + UTMIP_BIAS_CFG0); + val |= UTMIP_OTGPD | UTMIP_BIASPD; + writel(val, base + UTMIP_BIAS_CFG0); + } + + spin_unlock_irqrestore(&utmip_pad_lock, flags); + + clk_disable(phy->pad_clk); + + return 0; +} + +static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result) +{ + unsigned long timeout = 2000; + do { + if ((readl(reg) & mask) == result) + return 0; + udelay(1); + timeout--; + } while (timeout); + return -1; +} + +static void utmi_phy_clk_disable(struct tegra_usb_phy *phy) +{ + unsigned long val; + void __iomem *base = phy->regs; + + if (phy->instance == 0) { + val = readl(base + USB_SUSP_CTRL); + val |= USB_SUSP_SET; + writel(val, base + USB_SUSP_CTRL); + + udelay(10); + + val = readl(base + USB_SUSP_CTRL); + val &= ~USB_SUSP_SET; + writel(val, base + USB_SUSP_CTRL); + } + + if (phy->instance == 2) { + val = readl(base + USB_PORTSC1); + val |= USB_PORTSC1_PHCD; + writel(val, base + USB_PORTSC1); + } + + if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0) + pr_err("%s: timeout waiting for phy to stabilize\n", __func__); +} + +static void utmi_phy_clk_enable(struct tegra_usb_phy *phy) +{ + unsigned long val; + void __iomem *base = phy->regs; + + if (phy->instance == 0) { + val = readl(base + USB_SUSP_CTRL); + val |= USB_SUSP_CLR; + writel(val, base + USB_SUSP_CTRL); + + udelay(10); + + val = readl(base + USB_SUSP_CTRL); + val &= ~USB_SUSP_CLR; + writel(val, base + USB_SUSP_CTRL); + } + + if (phy->instance == 2) { + val = readl(base + USB_PORTSC1); + val &= ~USB_PORTSC1_PHCD; + writel(val, base + USB_PORTSC1); + } + + if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, + USB_PHY_CLK_VALID)) + pr_err("%s: timeout waiting for phy to stabilize\n", __func__); +} + +static int utmi_phy_power_on(struct tegra_usb_phy *phy) +{ + unsigned long val; + void __iomem *base = phy->regs; + struct tegra_utmip_config *config = phy->config; + + val = readl(base + USB_SUSP_CTRL); + val |= UTMIP_RESET; + writel(val, base + USB_SUSP_CTRL); + + if (phy->instance == 0) { + val = readl(base + USB1_LEGACY_CTRL); + val |= USB1_NO_LEGACY_MODE; + writel(val, base + USB1_LEGACY_CTRL); + } + + val = readl(base + UTMIP_TX_CFG0); + val &= ~UTMIP_FS_PREABMLE_J; + writel(val, base + UTMIP_TX_CFG0); + + val = readl(base + UTMIP_HSRX_CFG0); + val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0)); + val |= UTMIP_IDLE_WAIT(config->idle_wait_delay); + val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit); + writel(val, base + UTMIP_HSRX_CFG0); + + val = readl(base + UTMIP_HSRX_CFG1); + val &= ~UTMIP_HS_SYNC_START_DLY(~0); + val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay); + writel(val, base + UTMIP_HSRX_CFG1); + + val = readl(base + UTMIP_DEBOUNCE_CFG0); + val &= ~UTMIP_BIAS_DEBOUNCE_A(~0); + val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce); + writel(val, base + UTMIP_DEBOUNCE_CFG0); + + val = readl(base + UTMIP_MISC_CFG0); + val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE; + writel(val, base + UTMIP_MISC_CFG0); + + val = readl(base + UTMIP_MISC_CFG1); + val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0)); + val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) | + UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count); + writel(val, base + UTMIP_MISC_CFG1); + + val = readl(base + UTMIP_PLL_CFG1); + val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0)); + val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) | + UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay); + writel(val, base + UTMIP_PLL_CFG1); + + if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) { + val = readl(base + USB_SUSP_CTRL); + val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV); + writel(val, base + USB_SUSP_CTRL); + } + + utmip_pad_power_on(phy); + + val = readl(base + UTMIP_XCVR_CFG0); + val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | + UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_SETUP(~0) | + UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0) | + UTMIP_XCVR_HSSLEW_MSB(~0)); + val |= UTMIP_XCVR_SETUP(config->xcvr_setup); + val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew); + val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew); + writel(val, base + UTMIP_XCVR_CFG0); + + val = readl(base + UTMIP_XCVR_CFG1); + val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | + UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0)); + val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj); + writel(val, base + UTMIP_XCVR_CFG1); + + val = readl(base + UTMIP_BAT_CHRG_CFG0); + val &= ~UTMIP_PD_CHRG; + writel(val, base + UTMIP_BAT_CHRG_CFG0); + + val = readl(base + UTMIP_BIAS_CFG1); + val &= ~UTMIP_BIAS_PDTRK_COUNT(~0); + val |= UTMIP_BIAS_PDTRK_COUNT(0x5); + writel(val, base + UTMIP_BIAS_CFG1); + + if (phy->instance == 0) { + val = readl(base + UTMIP_SPARE_CFG0); + if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) + val &= ~FUSE_SETUP_SEL; + else + val |= FUSE_SETUP_SEL; + writel(val, base + UTMIP_SPARE_CFG0); + } + + if (phy->instance == 2) { + val = readl(base + USB_SUSP_CTRL); + val |= UTMIP_PHY_ENABLE; + writel(val, base + USB_SUSP_CTRL); + } + + val = readl(base + USB_SUSP_CTRL); + val &= ~UTMIP_RESET; + writel(val, base + USB_SUSP_CTRL); + + if (phy->instance == 0) { + val = readl(base + USB1_LEGACY_CTRL); + val &= ~USB1_VBUS_SENSE_CTL_MASK; + val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD; + writel(val, base + USB1_LEGACY_CTRL); + + val = readl(base + USB_SUSP_CTRL); + val &= ~USB_SUSP_SET; + writel(val, base + USB_SUSP_CTRL); + } + + utmi_phy_clk_enable(phy); + + if (phy->instance == 2) { + val = readl(base + USB_PORTSC1); + val &= ~USB_PORTSC1_PTS(~0); + writel(val, base + USB_PORTSC1); + } + + return 0; +} + +static void utmi_phy_power_off(struct tegra_usb_phy *phy) +{ + unsigned long val; + void __iomem *base = phy->regs; + + utmi_phy_clk_disable(phy); + + if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) { + val = readl(base + USB_SUSP_CTRL); + val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0); + val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5); + writel(val, base + USB_SUSP_CTRL); + } + + val = readl(base + USB_SUSP_CTRL); + val |= UTMIP_RESET; + writel(val, base + USB_SUSP_CTRL); + + val = readl(base + UTMIP_BAT_CHRG_CFG0); + val |= UTMIP_PD_CHRG; + writel(val, base + UTMIP_BAT_CHRG_CFG0); + + val = readl(base + UTMIP_XCVR_CFG0); + val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | + UTMIP_FORCE_PDZI_POWERDOWN; + writel(val, base + UTMIP_XCVR_CFG0); + + val = readl(base + UTMIP_XCVR_CFG1); + val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | + UTMIP_FORCE_PDDR_POWERDOWN; + writel(val, base + UTMIP_XCVR_CFG1); + + utmip_pad_power_off(phy); +} + +static void utmi_phy_preresume(struct tegra_usb_phy *phy) +{ + unsigned long val; + void __iomem *base = phy->regs; + + val = readl(base + UTMIP_TX_CFG0); + val |= UTMIP_HS_DISCON_DISABLE; + writel(val, base + UTMIP_TX_CFG0); +} + +static void utmi_phy_postresume(struct tegra_usb_phy *phy) +{ + unsigned long val; + void __iomem *base = phy->regs; + + val = readl(base + UTMIP_TX_CFG0); + val &= ~UTMIP_HS_DISCON_DISABLE; + writel(val, base + UTMIP_TX_CFG0); +} + +static void utmi_phy_restore_start(struct tegra_usb_phy *phy, + enum tegra_usb_phy_port_speed port_speed) +{ + unsigned long val; + void __iomem *base = phy->regs; + + val = readl(base + UTMIP_MISC_CFG0); + val &= ~UTMIP_DPDM_OBSERVE_SEL(~0); + if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW) + val |= UTMIP_DPDM_OBSERVE_SEL_FS_K; + else + val |= UTMIP_DPDM_OBSERVE_SEL_FS_J; + writel(val, base + UTMIP_MISC_CFG0); + udelay(1); + + val = readl(base + UTMIP_MISC_CFG0); + val |= UTMIP_DPDM_OBSERVE; + writel(val, base + UTMIP_MISC_CFG0); + udelay(10); +} + +static void utmi_phy_restore_end(struct tegra_usb_phy *phy) +{ + unsigned long val; + void __iomem *base = phy->regs; + + val = readl(base + UTMIP_MISC_CFG0); + val &= ~UTMIP_DPDM_OBSERVE; + writel(val, base + UTMIP_MISC_CFG0); + udelay(10); +} + +static int ulpi_phy_power_on(struct tegra_usb_phy *phy) +{ + int ret; + unsigned long val; + void __iomem *base = phy->regs; + struct tegra_ulpi_config *config = phy->config; + + gpio_direction_output(config->reset_gpio, 0); + msleep(5); + gpio_direction_output(config->reset_gpio, 1); + + clk_enable(phy->clk); + msleep(1); + + val = readl(base + USB_SUSP_CTRL); + val |= UHSIC_RESET; + writel(val, base + USB_SUSP_CTRL); + + val = readl(base + ULPI_TIMING_CTRL_0); + val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP; + writel(val, base + ULPI_TIMING_CTRL_0); + + val = readl(base + USB_SUSP_CTRL); + val |= ULPI_PHY_ENABLE; + writel(val, base + USB_SUSP_CTRL); + + val = 0; + writel(val, base + ULPI_TIMING_CTRL_1); + + val |= ULPI_DATA_TRIMMER_SEL(4); + val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); + val |= ULPI_DIR_TRIMMER_SEL(4); + writel(val, base + ULPI_TIMING_CTRL_1); + udelay(10); + + val |= ULPI_DATA_TRIMMER_LOAD; + val |= ULPI_STPDIRNXT_TRIMMER_LOAD; + val |= ULPI_DIR_TRIMMER_LOAD; + writel(val, base + ULPI_TIMING_CTRL_1); + + /* Fix VbusInvalid due to floating VBUS */ + ret = otg_io_write(phy->ulpi, 0x40, 0x08); + if (ret) { + pr_err("%s: ulpi write failed\n", __func__); + return ret; + } + + ret = otg_io_write(phy->ulpi, 0x80, 0x0B); + if (ret) { + pr_err("%s: ulpi write failed\n", __func__); + return ret; + } + + val = readl(base + USB_PORTSC1); + val |= USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN; + writel(val, base + USB_PORTSC1); + + val = readl(base + USB_SUSP_CTRL); + val |= USB_SUSP_CLR; + writel(val, base + USB_SUSP_CTRL); + udelay(100); + + val = readl(base + USB_SUSP_CTRL); + val &= ~USB_SUSP_CLR; + writel(val, base + USB_SUSP_CTRL); + + return 0; +} + +static void ulpi_phy_power_off(struct tegra_usb_phy *phy) +{ + unsigned long val; + void __iomem *base = phy->regs; + struct tegra_ulpi_config *config = phy->config; + + /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB + * Controller to immediately bring the ULPI PHY out of low power + */ + val = readl(base + USB_PORTSC1); + val &= ~(USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN); + writel(val, base + USB_PORTSC1); + + gpio_direction_output(config->reset_gpio, 0); + clk_disable(phy->clk); +} + +struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs, + void *config, enum tegra_usb_phy_mode phy_mode) +{ + struct tegra_usb_phy *phy; + struct tegra_ulpi_config *ulpi_config; + unsigned long parent_rate; + int i; + int err; + + phy = kmalloc(sizeof(struct tegra_usb_phy), GFP_KERNEL); + if (!phy) + return ERR_PTR(-ENOMEM); + + phy->instance = instance; + phy->regs = regs; + phy->config = config; + phy->mode = phy_mode; + + if (!phy->config) { + if (phy_is_ulpi(phy)) { + pr_err("%s: ulpi phy configuration missing", __func__); + err = -EINVAL; + goto err0; + } else { + phy->config = &utmip_default[instance]; + } + } + + phy->pll_u = clk_get_sys(NULL, "pll_u"); + if (IS_ERR(phy->pll_u)) { + pr_err("Can't get pll_u clock\n"); + err = PTR_ERR(phy->pll_u); + goto err0; + } + clk_enable(phy->pll_u); + + parent_rate = clk_get_rate(clk_get_parent(phy->pll_u)); + for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) { + if (tegra_freq_table[i].freq == parent_rate) { + phy->freq = &tegra_freq_table[i]; + break; + } + } + if (!phy->freq) { + pr_err("invalid pll_u parent rate %ld\n", parent_rate); + err = -EINVAL; + goto err1; + } + + if (phy_is_ulpi(phy)) { + ulpi_config = config; + phy->clk = clk_get_sys(NULL, ulpi_config->clk); + if (IS_ERR(phy->clk)) { + pr_err("%s: can't get ulpi clock\n", __func__); + err = -ENXIO; + goto err1; + } + tegra_gpio_enable(ulpi_config->reset_gpio); + gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b"); + gpio_direction_output(ulpi_config->reset_gpio, 0); + phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0); + phy->ulpi->io_priv = regs + ULPI_VIEWPORT; + } else { + err = utmip_pad_open(phy); + if (err < 0) + goto err1; + } + + return phy; + +err1: + clk_disable(phy->pll_u); + clk_put(phy->pll_u); +err0: + kfree(phy); + return ERR_PTR(err); +} + +int tegra_usb_phy_power_on(struct tegra_usb_phy *phy) +{ + if (phy_is_ulpi(phy)) + return ulpi_phy_power_on(phy); + else + return utmi_phy_power_on(phy); +} + +void tegra_usb_phy_power_off(struct tegra_usb_phy *phy) +{ + if (phy_is_ulpi(phy)) + ulpi_phy_power_off(phy); + else + utmi_phy_power_off(phy); +} + +void tegra_usb_phy_preresume(struct tegra_usb_phy *phy) +{ + if (!phy_is_ulpi(phy)) + utmi_phy_preresume(phy); +} + +void tegra_usb_phy_postresume(struct tegra_usb_phy *phy) +{ + if (!phy_is_ulpi(phy)) + utmi_phy_postresume(phy); +} + +void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy, + enum tegra_usb_phy_port_speed port_speed) +{ + if (!phy_is_ulpi(phy)) + utmi_phy_restore_start(phy, port_speed); +} + +void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy) +{ + if (!phy_is_ulpi(phy)) + utmi_phy_restore_end(phy); +} + +void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy) +{ + if (!phy_is_ulpi(phy)) + utmi_phy_clk_disable(phy); +} + +void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy) +{ + if (!phy_is_ulpi(phy)) + utmi_phy_clk_enable(phy); +} + +void tegra_usb_phy_close(struct tegra_usb_phy *phy) +{ + if (phy_is_ulpi(phy)) + clk_put(phy->clk); + else + utmip_pad_close(phy); + clk_disable(phy->pll_u); + clk_put(phy->pll_u); + kfree(phy); +} diff --git a/arch/arm/mach-u300/include/mach/memory.h b/arch/arm/mach-u300/include/mach/memory.h index bf134bcc129d..888e2e351ee1 100644 --- a/arch/arm/mach-u300/include/mach/memory.h +++ b/arch/arm/mach-u300/include/mach/memory.h @@ -15,17 +15,17 @@ #ifdef CONFIG_MACH_U300_DUAL_RAM -#define PHYS_OFFSET UL(0x48000000) +#define PLAT_PHYS_OFFSET UL(0x48000000) #define BOOT_PARAMS_OFFSET (PHYS_OFFSET + 0x100) #else #ifdef CONFIG_MACH_U300_2MB_ALIGNMENT_FIX -#define PHYS_OFFSET (0x28000000 + \ +#define PLAT_PHYS_OFFSET (0x28000000 + \ (CONFIG_MACH_U300_ACCESS_MEM_SIZE - \ (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024) #else -#define PHYS_OFFSET (0x28000000 + \ +#define PLAT_PHYS_OFFSET (0x28000000 + \ (CONFIG_MACH_U300_ACCESS_MEM_SIZE + \ (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024) #endif diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c index 07c35a846424..48b3b7f39966 100644 --- a/arch/arm/mach-u300/u300.c +++ b/arch/arm/mach-u300/u300.c @@ -19,9 +19,9 @@ #include <linux/io.h> #include <mach/hardware.h> #include <mach/platform.h> -#include <mach/memory.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> +#include <asm/memory.h> static void __init u300_reserve(void) { diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 247caa3400d0..203b986280f5 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -6,6 +6,7 @@ config UX500_SOC_COMMON select ARM_GIC select HAS_MTU select NOMADIK_GPIO + select ARM_ERRATA_753970 menu "Ux500 SoC" diff --git a/arch/arm/mach-ux500/include/mach/memory.h b/arch/arm/mach-ux500/include/mach/memory.h index 510571a59e25..2ef697a67006 100644 --- a/arch/arm/mach-ux500/include/mach/memory.h +++ b/arch/arm/mach-ux500/include/mach/memory.h @@ -12,7 +12,7 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #define BUS_OFFSET UL(0x00000000) #endif diff --git a/arch/arm/mach-versatile/include/mach/memory.h b/arch/arm/mach-versatile/include/mach/memory.h index 79aeab86b903..dacc9d8e4e6a 100644 --- a/arch/arm/mach-versatile/include/mach/memory.h +++ b/arch/arm/mach-versatile/include/mach/memory.h @@ -23,6 +23,6 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c index e628402b754c..e9bccc5230c9 100644 --- a/arch/arm/mach-vexpress/ct-ca9x4.c +++ b/arch/arm/mach-vexpress/ct-ca9x4.c @@ -243,7 +243,7 @@ static void __init ct_ca9x4_init(void) } MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4") - .boot_params = PHYS_OFFSET + 0x00000100, + .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .map_io = ct_ca9x4_map_io, .init_irq = ct_ca9x4_init_irq, #if 0 diff --git a/arch/arm/mach-vexpress/include/mach/memory.h b/arch/arm/mach-vexpress/include/mach/memory.h index be28232ae639..5b7fcd439d87 100644 --- a/arch/arm/mach-vexpress/include/mach/memory.h +++ b/arch/arm/mach-vexpress/include/mach/memory.h @@ -20,6 +20,6 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x60000000) +#define PLAT_PHYS_OFFSET UL(0x60000000) #endif diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig new file mode 100644 index 000000000000..2c20a341c11a --- /dev/null +++ b/arch/arm/mach-vt8500/Kconfig @@ -0,0 +1,73 @@ +if ARCH_VT8500 + +config VTWM_VERSION_VT8500 + bool + +config VTWM_VERSION_WM8505 + bool + +config MACH_BV07 + bool "Benign BV07-8500 Mini Netbook" + depends on ARCH_VT8500 + select VTWM_VERSION_VT8500 + help + Add support for the inexpensive 7-inch netbooks sold by many + Chinese distributors under various names. Note that there are + many hardware implementations in identical exterior, make sure + that yours is indeed based on a VIA VT8500 chip. + +config MACH_WM8505_7IN_NETBOOK + bool "WM8505 7-inch generic netbook" + depends on ARCH_VT8500 + select VTWM_VERSION_WM8505 + help + Add support for the inexpensive 7-inch netbooks sold by many + Chinese distributors under various names. Note that there are + many hardware implementations in identical exterior, make sure + that yours is indeed based on a WonderMedia WM8505 chip. + +comment "LCD panel size" + +config WMT_PANEL_800X480 + bool "7-inch with 800x480 resolution" + depends on (FB_VT8500 || FB_WM8505) + default y + help + These are found in most of the netbooks in generic cases, as + well as in Eken M001 tablets and possibly elsewhere. + + To select this panel at runtime, say y here and append + 'panel=800x480' to your kernel command line. Otherwise, the + largest one available will be used. + +config WMT_PANEL_800X600 + bool "8-inch with 800x600 resolution" + depends on (FB_VT8500 || FB_WM8505) + help + These are found in Eken M003 tablets and possibly elsewhere. + + To select this panel at runtime, say y here and append + 'panel=800x600' to your kernel command line. Otherwise, the + largest one available will be used. + +config WMT_PANEL_1024X576 + bool "10-inch with 1024x576 resolution" + depends on (FB_VT8500 || FB_WM8505) + help + These are found in CherryPal netbooks and possibly elsewhere. + + To select this panel at runtime, say y here and append + 'panel=1024x576' to your kernel command line. Otherwise, the + largest one available will be used. + +config WMT_PANEL_1024X600 + bool "10-inch with 1024x600 resolution" + depends on (FB_VT8500 || FB_WM8505) + help + These are found in Eken M006 tablets and possibly elsewhere. + + To select this panel at runtime, say y here and append + 'panel=1024x600' to your kernel command line. Otherwise, the + largest one available will be used. + +endif diff --git a/arch/arm/mach-vt8500/Makefile b/arch/arm/mach-vt8500/Makefile new file mode 100644 index 000000000000..81aedb7c893c --- /dev/null +++ b/arch/arm/mach-vt8500/Makefile @@ -0,0 +1,9 @@ +obj-y += devices.o gpio.o irq.o timer.o + +obj-$(CONFIG_VTWM_VERSION_VT8500) += devices-vt8500.o +obj-$(CONFIG_VTWM_VERSION_WM8505) += devices-wm8505.o + +obj-$(CONFIG_MACH_BV07) += bv07.o +obj-$(CONFIG_MACH_WM8505_7IN_NETBOOK) += wm8505_7in.o + +obj-$(CONFIG_HAVE_PWM) += pwm.o diff --git a/arch/arm/mach-vt8500/Makefile.boot b/arch/arm/mach-vt8500/Makefile.boot new file mode 100644 index 000000000000..a8acc4e24902 --- /dev/null +++ b/arch/arm/mach-vt8500/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x01000000 diff --git a/arch/arm/mach-vt8500/bv07.c b/arch/arm/mach-vt8500/bv07.c new file mode 100644 index 000000000000..94a261d86bf0 --- /dev/null +++ b/arch/arm/mach-vt8500/bv07.c @@ -0,0 +1,77 @@ +/* + * arch/arm/mach-vt8500/bv07.c + * + * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/io.h> +#include <linux/pm.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include "devices.h" + +static void __iomem *pmc_hiber; + +static struct platform_device *devices[] __initdata = { + &vt8500_device_uart0, + &vt8500_device_lcdc, + &vt8500_device_ehci, + &vt8500_device_ge_rops, + &vt8500_device_pwm, + &vt8500_device_pwmbl, + &vt8500_device_rtc, +}; + +static void vt8500_power_off(void) +{ + local_irq_disable(); + writew(5, pmc_hiber); + asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0)); +} + +void __init bv07_init(void) +{ +#ifdef CONFIG_FB_VT8500 + void __iomem *gpio_mux_reg = ioremap(wmt_gpio_base + 0x200, 4); + if (gpio_mux_reg) { + writel(readl(gpio_mux_reg) | 1, gpio_mux_reg); + iounmap(gpio_mux_reg); + } else { + printk(KERN_ERR "Could not remap the GPIO mux register, display may not work properly!\n"); + } +#endif + pmc_hiber = ioremap(wmt_pmc_base + 0x12, 2); + if (pmc_hiber) + pm_power_off = &vt8500_power_off; + else + printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n"); + + vt8500_set_resources(); + platform_add_devices(devices, ARRAY_SIZE(devices)); + vt8500_gpio_init(); +} + +MACHINE_START(BV07, "Benign BV07 Mini Netbook") + .boot_params = 0x00000100, + .reserve = vt8500_reserve_mem, + .map_io = vt8500_map_io, + .init_irq = vt8500_init_irq, + .timer = &vt8500_timer, + .init_machine = bv07_init, +MACHINE_END diff --git a/arch/arm/mach-vt8500/devices-vt8500.c b/arch/arm/mach-vt8500/devices-vt8500.c new file mode 100644 index 000000000000..19519aeecf37 --- /dev/null +++ b/arch/arm/mach-vt8500/devices-vt8500.c @@ -0,0 +1,91 @@ +/* linux/arch/arm/mach-vt8500/devices-vt8500.c + * + * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/platform_device.h> + +#include <mach/vt8500_regs.h> +#include <mach/vt8500_irqs.h> +#include <mach/i8042.h> +#include "devices.h" + +void __init vt8500_set_resources(void) +{ + struct resource tmp[3]; + + tmp[0] = wmt_mmio_res(VT8500_LCDC_BASE, SZ_1K); + tmp[1] = wmt_irq_res(IRQ_LCDC); + wmt_res_add(&vt8500_device_lcdc, tmp, 2); + + tmp[0] = wmt_mmio_res(VT8500_UART0_BASE, 0x1040); + tmp[1] = wmt_irq_res(IRQ_UART0); + wmt_res_add(&vt8500_device_uart0, tmp, 2); + + tmp[0] = wmt_mmio_res(VT8500_UART1_BASE, 0x1040); + tmp[1] = wmt_irq_res(IRQ_UART1); + wmt_res_add(&vt8500_device_uart1, tmp, 2); + + tmp[0] = wmt_mmio_res(VT8500_UART2_BASE, 0x1040); + tmp[1] = wmt_irq_res(IRQ_UART2); + wmt_res_add(&vt8500_device_uart2, tmp, 2); + + tmp[0] = wmt_mmio_res(VT8500_UART3_BASE, 0x1040); + tmp[1] = wmt_irq_res(IRQ_UART3); + wmt_res_add(&vt8500_device_uart3, tmp, 2); + + tmp[0] = wmt_mmio_res(VT8500_EHCI_BASE, SZ_512); + tmp[1] = wmt_irq_res(IRQ_EHCI); + wmt_res_add(&vt8500_device_ehci, tmp, 2); + + tmp[0] = wmt_mmio_res(VT8500_GEGEA_BASE, SZ_256); + wmt_res_add(&vt8500_device_ge_rops, tmp, 1); + + tmp[0] = wmt_mmio_res(VT8500_PWM_BASE, 0x44); + wmt_res_add(&vt8500_device_pwm, tmp, 1); + + tmp[0] = wmt_mmio_res(VT8500_RTC_BASE, 0x2c); + tmp[1] = wmt_irq_res(IRQ_RTC); + tmp[2] = wmt_irq_res(IRQ_RTCSM); + wmt_res_add(&vt8500_device_rtc, tmp, 3); +} + +static void __init vt8500_set_externs(void) +{ + /* Non-resource-aware stuff */ + wmt_ic_base = VT8500_IC_BASE; + wmt_gpio_base = VT8500_GPIO_BASE; + wmt_pmc_base = VT8500_PMC_BASE; + wmt_i8042_base = VT8500_PS2_BASE; + + wmt_nr_irqs = VT8500_NR_IRQS; + wmt_timer_irq = IRQ_PMCOS0; + wmt_gpio_ext_irq[0] = IRQ_EXT0; + wmt_gpio_ext_irq[1] = IRQ_EXT1; + wmt_gpio_ext_irq[2] = IRQ_EXT2; + wmt_gpio_ext_irq[3] = IRQ_EXT3; + wmt_gpio_ext_irq[4] = IRQ_EXT4; + wmt_gpio_ext_irq[5] = IRQ_EXT5; + wmt_gpio_ext_irq[6] = IRQ_EXT6; + wmt_gpio_ext_irq[7] = IRQ_EXT7; + wmt_i8042_kbd_irq = IRQ_PS2KBD; + wmt_i8042_aux_irq = IRQ_PS2MOUSE; +} + +void __init vt8500_map_io(void) +{ + iotable_init(wmt_io_desc, ARRAY_SIZE(wmt_io_desc)); + + /* Should be done before interrupts and timers are initialized */ + vt8500_set_externs(); +} diff --git a/arch/arm/mach-vt8500/devices-wm8505.c b/arch/arm/mach-vt8500/devices-wm8505.c new file mode 100644 index 000000000000..db4594e029f4 --- /dev/null +++ b/arch/arm/mach-vt8500/devices-wm8505.c @@ -0,0 +1,99 @@ +/* linux/arch/arm/mach-vt8500/devices-wm8505.c + * + * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/platform_device.h> + +#include <mach/wm8505_regs.h> +#include <mach/wm8505_irqs.h> +#include <mach/i8042.h> +#include "devices.h" + +void __init wm8505_set_resources(void) +{ + struct resource tmp[3]; + + tmp[0] = wmt_mmio_res(WM8505_GOVR_BASE, SZ_512); + wmt_res_add(&vt8500_device_wm8505_fb, tmp, 1); + + tmp[0] = wmt_mmio_res(WM8505_UART0_BASE, 0x1040); + tmp[1] = wmt_irq_res(IRQ_UART0); + wmt_res_add(&vt8500_device_uart0, tmp, 2); + + tmp[0] = wmt_mmio_res(WM8505_UART1_BASE, 0x1040); + tmp[1] = wmt_irq_res(IRQ_UART1); + wmt_res_add(&vt8500_device_uart1, tmp, 2); + + tmp[0] = wmt_mmio_res(WM8505_UART2_BASE, 0x1040); + tmp[1] = wmt_irq_res(IRQ_UART2); + wmt_res_add(&vt8500_device_uart2, tmp, 2); + + tmp[0] = wmt_mmio_res(WM8505_UART3_BASE, 0x1040); + tmp[1] = wmt_irq_res(IRQ_UART3); + wmt_res_add(&vt8500_device_uart3, tmp, 2); + + tmp[0] = wmt_mmio_res(WM8505_UART4_BASE, 0x1040); + tmp[1] = wmt_irq_res(IRQ_UART4); + wmt_res_add(&vt8500_device_uart4, tmp, 2); + + tmp[0] = wmt_mmio_res(WM8505_UART5_BASE, 0x1040); + tmp[1] = wmt_irq_res(IRQ_UART5); + wmt_res_add(&vt8500_device_uart5, tmp, 2); + + tmp[0] = wmt_mmio_res(WM8505_EHCI_BASE, SZ_512); + tmp[1] = wmt_irq_res(IRQ_EHCI); + wmt_res_add(&vt8500_device_ehci, tmp, 2); + + tmp[0] = wmt_mmio_res(WM8505_GEGEA_BASE, SZ_256); + wmt_res_add(&vt8500_device_ge_rops, tmp, 1); + + tmp[0] = wmt_mmio_res(WM8505_PWM_BASE, 0x44); + wmt_res_add(&vt8500_device_pwm, tmp, 1); + + tmp[0] = wmt_mmio_res(WM8505_RTC_BASE, 0x2c); + tmp[1] = wmt_irq_res(IRQ_RTC); + tmp[2] = wmt_irq_res(IRQ_RTCSM); + wmt_res_add(&vt8500_device_rtc, tmp, 3); +} + +static void __init wm8505_set_externs(void) +{ + /* Non-resource-aware stuff */ + wmt_ic_base = WM8505_IC_BASE; + wmt_sic_base = WM8505_SIC_BASE; + wmt_gpio_base = WM8505_GPIO_BASE; + wmt_pmc_base = WM8505_PMC_BASE; + wmt_i8042_base = WM8505_PS2_BASE; + + wmt_nr_irqs = WM8505_NR_IRQS; + wmt_timer_irq = IRQ_PMCOS0; + wmt_gpio_ext_irq[0] = IRQ_EXT0; + wmt_gpio_ext_irq[1] = IRQ_EXT1; + wmt_gpio_ext_irq[2] = IRQ_EXT2; + wmt_gpio_ext_irq[3] = IRQ_EXT3; + wmt_gpio_ext_irq[4] = IRQ_EXT4; + wmt_gpio_ext_irq[5] = IRQ_EXT5; + wmt_gpio_ext_irq[6] = IRQ_EXT6; + wmt_gpio_ext_irq[7] = IRQ_EXT7; + wmt_i8042_kbd_irq = IRQ_PS2KBD; + wmt_i8042_aux_irq = IRQ_PS2MOUSE; +} + +void __init wm8505_map_io(void) +{ + iotable_init(wmt_io_desc, ARRAY_SIZE(wmt_io_desc)); + + /* Should be done before interrupts and timers are initialized */ + wm8505_set_externs(); +} diff --git a/arch/arm/mach-vt8500/devices.c b/arch/arm/mach-vt8500/devices.c new file mode 100644 index 000000000000..1fcdc36b358d --- /dev/null +++ b/arch/arm/mach-vt8500/devices.c @@ -0,0 +1,270 @@ +/* linux/arch/arm/mach-vt8500/devices.c + * + * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/device.h> +#include <linux/dma-mapping.h> +#include <linux/platform_device.h> +#include <linux/pwm_backlight.h> +#include <linux/memblock.h> + +#include <asm/mach/arch.h> + +#include <mach/vt8500fb.h> +#include <mach/i8042.h> +#include "devices.h" + +/* These can't use resources currently */ +unsigned long wmt_ic_base __initdata; +unsigned long wmt_sic_base __initdata; +unsigned long wmt_gpio_base __initdata; +unsigned long wmt_pmc_base __initdata; +unsigned long wmt_i8042_base __initdata; + +int wmt_nr_irqs __initdata; +int wmt_timer_irq __initdata; +int wmt_gpio_ext_irq[8] __initdata; + +/* Should remain accessible after init. + * i8042 driver desperately calls for attention... + */ +int wmt_i8042_kbd_irq; +int wmt_i8042_aux_irq; + +static u64 fb_dma_mask = DMA_BIT_MASK(32); + +struct platform_device vt8500_device_lcdc = { + .name = "vt8500-lcd", + .id = 0, + .dev = { + .dma_mask = &fb_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +struct platform_device vt8500_device_wm8505_fb = { + .name = "wm8505-fb", + .id = 0, +}; + +/* Smallest to largest */ +static struct vt8500fb_platform_data panels[] = { +#ifdef CONFIG_WMT_PANEL_800X480 +{ + .xres_virtual = 800, + .yres_virtual = 480 * 2, + .mode = { + .name = "800x480", + .xres = 800, + .yres = 480, + .left_margin = 88, + .right_margin = 40, + .upper_margin = 32, + .lower_margin = 11, + .hsync_len = 0, + .vsync_len = 1, + .vmode = FB_VMODE_NONINTERLACED, + }, +}, +#endif +#ifdef CONFIG_WMT_PANEL_800X600 +{ + .xres_virtual = 800, + .yres_virtual = 600 * 2, + .mode = { + .name = "800x600", + .xres = 800, + .yres = 600, + .left_margin = 88, + .right_margin = 40, + .upper_margin = 32, + .lower_margin = 11, + .hsync_len = 0, + .vsync_len = 1, + .vmode = FB_VMODE_NONINTERLACED, + }, +}, +#endif +#ifdef CONFIG_WMT_PANEL_1024X576 +{ + .xres_virtual = 1024, + .yres_virtual = 576 * 2, + .mode = { + .name = "1024x576", + .xres = 1024, + .yres = 576, + .left_margin = 40, + .right_margin = 24, + .upper_margin = 32, + .lower_margin = 11, + .hsync_len = 96, + .vsync_len = 2, + .vmode = FB_VMODE_NONINTERLACED, + }, +}, +#endif +#ifdef CONFIG_WMT_PANEL_1024X600 +{ + .xres_virtual = 1024, + .yres_virtual = 600 * 2, + .mode = { + .name = "1024x600", + .xres = 1024, + .yres = 600, + .left_margin = 66, + .right_margin = 2, + .upper_margin = 19, + .lower_margin = 1, + .hsync_len = 23, + .vsync_len = 8, + .vmode = FB_VMODE_NONINTERLACED, + }, +}, +#endif +}; + +static int current_panel_idx __initdata = ARRAY_SIZE(panels) - 1; + +static int __init panel_setup(char *str) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(panels); i++) { + if (strcmp(panels[i].mode.name, str) == 0) { + current_panel_idx = i; + break; + } + } + return 0; +} + +early_param("panel", panel_setup); + +static inline void preallocate_fb(struct vt8500fb_platform_data *p, + unsigned long align) { + p->video_mem_len = (p->xres_virtual * p->yres_virtual * 4) >> + (p->bpp > 16 ? 0 : (p->bpp > 8 ? 1 : + (8 / p->bpp) + 1)); + p->video_mem_phys = (unsigned long)memblock_alloc(p->video_mem_len, + align); + p->video_mem_virt = phys_to_virt(p->video_mem_phys); +} + +struct platform_device vt8500_device_uart0 = { + .name = "vt8500_serial", + .id = 0, +}; + +struct platform_device vt8500_device_uart1 = { + .name = "vt8500_serial", + .id = 1, +}; + +struct platform_device vt8500_device_uart2 = { + .name = "vt8500_serial", + .id = 2, +}; + +struct platform_device vt8500_device_uart3 = { + .name = "vt8500_serial", + .id = 3, +}; + +struct platform_device vt8500_device_uart4 = { + .name = "vt8500_serial", + .id = 4, +}; + +struct platform_device vt8500_device_uart5 = { + .name = "vt8500_serial", + .id = 5, +}; + +static u64 ehci_dma_mask = DMA_BIT_MASK(32); + +struct platform_device vt8500_device_ehci = { + .name = "vt8500-ehci", + .id = 0, + .dev = { + .dma_mask = &ehci_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +struct platform_device vt8500_device_ge_rops = { + .name = "wmt_ge_rops", + .id = -1, +}; + +struct platform_device vt8500_device_pwm = { + .name = "vt8500-pwm", + .id = 0, +}; + +static struct platform_pwm_backlight_data vt8500_pwmbl_data = { + .pwm_id = 0, + .max_brightness = 128, + .dft_brightness = 70, + .pwm_period_ns = 250000, /* revisit when clocks are implemented */ +}; + +struct platform_device vt8500_device_pwmbl = { + .name = "pwm-backlight", + .id = 0, + .dev = { + .platform_data = &vt8500_pwmbl_data, + }, +}; + +struct platform_device vt8500_device_rtc = { + .name = "vt8500-rtc", + .id = 0, +}; + +struct map_desc wmt_io_desc[] __initdata = { + /* SoC MMIO registers */ + [0] = { + .virtual = 0xf8000000, + .pfn = __phys_to_pfn(0xd8000000), + .length = 0x00390000, /* max of all chip variants */ + .type = MT_DEVICE + }, + /* PCI I/O space, numbers tied to those in <mach/io.h> */ + [1] = { + .virtual = 0xf0000000, + .pfn = __phys_to_pfn(0xc0000000), + .length = SZ_64K, + .type = MT_DEVICE + }, +}; + +void __init vt8500_reserve_mem(void) +{ +#ifdef CONFIG_FB_VT8500 + panels[current_panel_idx].bpp = 16; /* Always use RGB565 */ + preallocate_fb(&panels[current_panel_idx], SZ_4M); + vt8500_device_lcdc.dev.platform_data = &panels[current_panel_idx]; +#endif +} + +void __init wm8505_reserve_mem(void) +{ +#if defined CONFIG_FB_WM8505 + panels[current_panel_idx].bpp = 32; /* Always use RGB888 */ + preallocate_fb(&panels[current_panel_idx], 32); + vt8500_device_wm8505_fb.dev.platform_data = &panels[current_panel_idx]; +#endif +} diff --git a/arch/arm/mach-vt8500/devices.h b/arch/arm/mach-vt8500/devices.h new file mode 100644 index 000000000000..188d4e17f35c --- /dev/null +++ b/arch/arm/mach-vt8500/devices.h @@ -0,0 +1,88 @@ +/* linux/arch/arm/mach-vt8500/devices.h + * + * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ARCH_ARM_MACH_VT8500_DEVICES_H +#define __ARCH_ARM_MACH_VT8500_DEVICES_H + +#include <linux/platform_device.h> +#include <asm/mach/map.h> + +void __init vt8500_init_irq(void); +void __init wm8505_init_irq(void); +void __init vt8500_map_io(void); +void __init wm8505_map_io(void); +void __init vt8500_reserve_mem(void); +void __init wm8505_reserve_mem(void); +void __init vt8500_gpio_init(void); +void __init vt8500_set_resources(void); +void __init wm8505_set_resources(void); + +extern unsigned long wmt_ic_base __initdata; +extern unsigned long wmt_sic_base __initdata; +extern unsigned long wmt_gpio_base __initdata; +extern unsigned long wmt_pmc_base __initdata; + +extern int wmt_nr_irqs __initdata; +extern int wmt_timer_irq __initdata; +extern int wmt_gpio_ext_irq[8] __initdata; + +extern struct map_desc wmt_io_desc[2] __initdata; + +static inline struct resource wmt_mmio_res(u32 start, u32 size) +{ + struct resource tmp = { + .flags = IORESOURCE_MEM, + .start = start, + .end = start + size - 1, + }; + + return tmp; +} + +static inline struct resource wmt_irq_res(int irq) +{ + struct resource tmp = { + .flags = IORESOURCE_IRQ, + .start = irq, + .end = irq, + }; + + return tmp; +} + +static inline void wmt_res_add(struct platform_device *pdev, + const struct resource *res, unsigned int num) +{ + if (unlikely(platform_device_add_resources(pdev, res, num))) + pr_err("Failed to assign resources\n"); +} + +extern struct sys_timer vt8500_timer; + +extern struct platform_device vt8500_device_uart0; +extern struct platform_device vt8500_device_uart1; +extern struct platform_device vt8500_device_uart2; +extern struct platform_device vt8500_device_uart3; +extern struct platform_device vt8500_device_uart4; +extern struct platform_device vt8500_device_uart5; + +extern struct platform_device vt8500_device_lcdc; +extern struct platform_device vt8500_device_wm8505_fb; +extern struct platform_device vt8500_device_ehci; +extern struct platform_device vt8500_device_ge_rops; +extern struct platform_device vt8500_device_pwm; +extern struct platform_device vt8500_device_pwmbl; +extern struct platform_device vt8500_device_rtc; +#endif diff --git a/arch/arm/mach-vt8500/gpio.c b/arch/arm/mach-vt8500/gpio.c new file mode 100644 index 000000000000..2bcc0ec783df --- /dev/null +++ b/arch/arm/mach-vt8500/gpio.c @@ -0,0 +1,240 @@ +/* linux/arch/arm/mach-vt8500/gpio.c + * + * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include "devices.h" + +#define to_vt8500(__chip) container_of(__chip, struct vt8500_gpio_chip, chip) + +#define ENABLE_REGS 0x0 +#define DIRECTION_REGS 0x20 +#define OUTVALUE_REGS 0x40 +#define INVALUE_REGS 0x60 + +#define EXT_REGOFF 0x1c + +static void __iomem *regbase; + +struct vt8500_gpio_chip { + struct gpio_chip chip; + unsigned int shift; + unsigned int regoff; +}; + +static int gpio_to_irq_map[8]; + +static int vt8500_muxed_gpio_request(struct gpio_chip *chip, + unsigned offset) +{ + struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip); + unsigned val = readl(regbase + ENABLE_REGS + vt8500_chip->regoff); + + val |= (1 << vt8500_chip->shift << offset); + writel(val, regbase + ENABLE_REGS + vt8500_chip->regoff); + + return 0; +} + +static void vt8500_muxed_gpio_free(struct gpio_chip *chip, + unsigned offset) +{ + struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip); + unsigned val = readl(regbase + ENABLE_REGS + vt8500_chip->regoff); + + val &= ~(1 << vt8500_chip->shift << offset); + writel(val, regbase + ENABLE_REGS + vt8500_chip->regoff); +} + +static int vt8500_muxed_gpio_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip); + unsigned val = readl(regbase + DIRECTION_REGS + vt8500_chip->regoff); + + val &= ~(1 << vt8500_chip->shift << offset); + writel(val, regbase + DIRECTION_REGS + vt8500_chip->regoff); + + return 0; +} + +static int vt8500_muxed_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip); + unsigned val = readl(regbase + DIRECTION_REGS + vt8500_chip->regoff); + + val |= (1 << vt8500_chip->shift << offset); + writel(val, regbase + DIRECTION_REGS + vt8500_chip->regoff); + + if (value) { + val = readl(regbase + OUTVALUE_REGS + vt8500_chip->regoff); + val |= (1 << vt8500_chip->shift << offset); + writel(val, regbase + OUTVALUE_REGS + vt8500_chip->regoff); + } + return 0; +} + +static int vt8500_muxed_gpio_get_value(struct gpio_chip *chip, + unsigned offset) +{ + struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip); + + return (readl(regbase + INVALUE_REGS + vt8500_chip->regoff) + >> vt8500_chip->shift >> offset) & 1; +} + +static void vt8500_muxed_gpio_set_value(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip); + unsigned val = readl(regbase + INVALUE_REGS + vt8500_chip->regoff); + + if (value) + val |= (1 << vt8500_chip->shift << offset); + else + val &= ~(1 << vt8500_chip->shift << offset); + + writel(val, regbase + INVALUE_REGS + vt8500_chip->regoff); +} + +#define VT8500_GPIO_BANK(__name, __shift, __off, __base, __num) \ +{ \ + .chip = { \ + .label = __name, \ + .request = vt8500_muxed_gpio_request, \ + .free = vt8500_muxed_gpio_free, \ + .direction_input = vt8500_muxed_gpio_direction_input, \ + .direction_output = vt8500_muxed_gpio_direction_output, \ + .get = vt8500_muxed_gpio_get_value, \ + .set = vt8500_muxed_gpio_set_value, \ + .can_sleep = 0, \ + .base = __base, \ + .ngpio = __num, \ + }, \ + .shift = __shift, \ + .regoff = __off, \ +} + +static struct vt8500_gpio_chip vt8500_muxed_gpios[] = { + VT8500_GPIO_BANK("uart0", 0, 0x0, 8, 4), + VT8500_GPIO_BANK("uart1", 4, 0x0, 12, 4), + VT8500_GPIO_BANK("spi0", 8, 0x0, 16, 4), + VT8500_GPIO_BANK("spi1", 12, 0x0, 20, 4), + VT8500_GPIO_BANK("spi2", 16, 0x0, 24, 4), + VT8500_GPIO_BANK("pwmout", 24, 0x0, 28, 2), + + VT8500_GPIO_BANK("sdmmc", 0, 0x4, 30, 11), + VT8500_GPIO_BANK("ms", 16, 0x4, 41, 7), + VT8500_GPIO_BANK("i2c0", 24, 0x4, 48, 2), + VT8500_GPIO_BANK("i2c1", 26, 0x4, 50, 2), + + VT8500_GPIO_BANK("mii", 0, 0x8, 52, 20), + VT8500_GPIO_BANK("see", 20, 0x8, 72, 4), + VT8500_GPIO_BANK("ide", 24, 0x8, 76, 7), + + VT8500_GPIO_BANK("ccir", 0, 0xc, 83, 19), + + VT8500_GPIO_BANK("ts", 8, 0x10, 102, 11), + + VT8500_GPIO_BANK("lcd", 0, 0x14, 113, 23), +}; + +static int vt8500_gpio_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + unsigned val = readl(regbase + DIRECTION_REGS + EXT_REGOFF); + + val &= ~(1 << offset); + writel(val, regbase + DIRECTION_REGS + EXT_REGOFF); + return 0; +} + +static int vt8500_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + unsigned val = readl(regbase + DIRECTION_REGS + EXT_REGOFF); + + val |= (1 << offset); + writel(val, regbase + DIRECTION_REGS + EXT_REGOFF); + + if (value) { + val = readl(regbase + OUTVALUE_REGS + EXT_REGOFF); + val |= (1 << offset); + writel(val, regbase + OUTVALUE_REGS + EXT_REGOFF); + } + return 0; +} + +static int vt8500_gpio_get_value(struct gpio_chip *chip, + unsigned offset) +{ + return (readl(regbase + INVALUE_REGS + EXT_REGOFF) >> offset) & 1; +} + +static void vt8500_gpio_set_value(struct gpio_chip *chip, + unsigned offset, int value) +{ + unsigned val = readl(regbase + OUTVALUE_REGS + EXT_REGOFF); + + if (value) + val |= (1 << offset); + else + val &= ~(1 << offset); + + writel(val, regbase + OUTVALUE_REGS + EXT_REGOFF); +} + +static int vt8500_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + if (offset > 7) + return -EINVAL; + + return gpio_to_irq_map[offset]; +} + +static struct gpio_chip vt8500_external_gpios = { + .label = "extgpio", + .direction_input = vt8500_gpio_direction_input, + .direction_output = vt8500_gpio_direction_output, + .get = vt8500_gpio_get_value, + .set = vt8500_gpio_set_value, + .to_irq = vt8500_gpio_to_irq, + .can_sleep = 0, + .base = 0, + .ngpio = 8, +}; + +void __init vt8500_gpio_init(void) +{ + int i; + + for (i = 0; i < 8; i++) + gpio_to_irq_map[i] = wmt_gpio_ext_irq[i]; + + regbase = ioremap(wmt_gpio_base, SZ_64K); + if (!regbase) { + printk(KERN_ERR "Failed to map MMIO registers for GPIO\n"); + return; + } + + gpiochip_add(&vt8500_external_gpios); + + for (i = 0; i < ARRAY_SIZE(vt8500_muxed_gpios); i++) + gpiochip_add(&vt8500_muxed_gpios[i].chip); +} diff --git a/arch/arm/mach-vt8500/include/mach/debug-macro.S b/arch/arm/mach-vt8500/include/mach/debug-macro.S new file mode 100644 index 000000000000..f1191626ad51 --- /dev/null +++ b/arch/arm/mach-vt8500/include/mach/debug-macro.S @@ -0,0 +1,31 @@ +/* + * arch/arm/mach-vt8500/include/mach/debug-macro.S + * + * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> + * + * Debugging macro include header + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + + .macro addruart, rp, rv + mov \rp, #0x00200000 + orr \rv, \rp, #0xf8000000 + orr \rp, \rp, #0xd8000000 + .endm + + .macro senduart,rd,rx + strb \rd, [\rx, #0] + .endm + + .macro busyuart,rd,rx +1001: ldr \rd, [\rx, #0x1c] + ands \rd, \rd, #0x2 + bne 1001b + .endm + + .macro waituart,rd,rx + .endm diff --git a/arch/arm/mach-vt8500/include/mach/entry-macro.S b/arch/arm/mach-vt8500/include/mach/entry-macro.S new file mode 100644 index 000000000000..92684c7eaed3 --- /dev/null +++ b/arch/arm/mach-vt8500/include/mach/entry-macro.S @@ -0,0 +1,32 @@ +/* + * arch/arm/mach-vt8500/include/mach/entry-macro.S + * + * Low-level IRQ helper macros for VIA VT8500 + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + @ physical 0xd8140000 is virtual 0xf8140000 + mov \base, #0xf8000000 + orr \base, \base, #0x00140000 + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \irqnr, [\base] + cmp \irqnr, #63 @ may be false positive, check interrupt status + bne 1001f + ldr \irqstat, [\base, #0x84] + ands \irqstat, #0x80000000 + moveq \irqnr, #0 +1001: + .endm + diff --git a/arch/arm/mach-vt8500/include/mach/gpio.h b/arch/arm/mach-vt8500/include/mach/gpio.h new file mode 100644 index 000000000000..94ff27678a46 --- /dev/null +++ b/arch/arm/mach-vt8500/include/mach/gpio.h @@ -0,0 +1,6 @@ +#include <asm-generic/gpio.h> + +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#define gpio_to_irq __gpio_to_irq diff --git a/arch/arm/mach-tegra/tegra2_dvfs.h b/arch/arm/mach-vt8500/include/mach/hardware.h index f8c1adba96a6..db4163f72c39 100644 --- a/arch/arm/mach-tegra/tegra2_dvfs.h +++ b/arch/arm/mach-vt8500/include/mach/hardware.h @@ -1,10 +1,4 @@ -/* - * arch/arm/mach-tegra/tegra2_dvfs.h - * - * Copyright (C) 2010 Google, Inc. - * - * Author: - * Colin Cross <ccross@google.com> +/* arch/arm/mach-vt8500/include/mach/hardware.h * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -16,5 +10,3 @@ * GNU General Public License for more details. * */ - -extern struct dvfs tegra_dvfs_virtual_cpu_dvfs; diff --git a/arch/arm/mach-vt8500/include/mach/i8042.h b/arch/arm/mach-vt8500/include/mach/i8042.h new file mode 100644 index 000000000000..cd7143cad6f3 --- /dev/null +++ b/arch/arm/mach-vt8500/include/mach/i8042.h @@ -0,0 +1,18 @@ +/* arch/arm/mach-vt8500/include/mach/i8042.h + * + * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +extern unsigned long wmt_i8042_base __initdata; +extern int wmt_i8042_kbd_irq; +extern int wmt_i8042_aux_irq; diff --git a/arch/arm/mach-vt8500/include/mach/io.h b/arch/arm/mach-vt8500/include/mach/io.h new file mode 100644 index 000000000000..9077239f78c9 --- /dev/null +++ b/arch/arm/mach-vt8500/include/mach/io.h @@ -0,0 +1,28 @@ +/* + * arch/arm/mach-vt8500/include/mach/io.h + * + * Copyright (C) 2010 Alexey Charkov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffff + +#define __io(a) __typesafe_io((a) + 0xf0000000) +#define __mem_pci(a) (a) + +#endif diff --git a/arch/arm/mach-vt8500/include/mach/irqs.h b/arch/arm/mach-vt8500/include/mach/irqs.h new file mode 100644 index 000000000000..a129fd1222fb --- /dev/null +++ b/arch/arm/mach-vt8500/include/mach/irqs.h @@ -0,0 +1,22 @@ +/* + * arch/arm/mach-vt8500/include/mach/irqs.h + * + * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* This value is just to make the core happy, never used otherwise */ +#define NR_IRQS 128 diff --git a/arch/arm/mach-vt8500/include/mach/memory.h b/arch/arm/mach-vt8500/include/mach/memory.h new file mode 100644 index 000000000000..175f914eff93 --- /dev/null +++ b/arch/arm/mach-vt8500/include/mach/memory.h @@ -0,0 +1,28 @@ +/* + * arch/arm/mach-vt8500/include/mach/memory.h + * + * Copyright (C) 2003 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +/* + * Physical DRAM offset. + */ +#define PHYS_OFFSET UL(0x00000000) + +#endif diff --git a/arch/arm/mach-vt8500/include/mach/system.h b/arch/arm/mach-vt8500/include/mach/system.h new file mode 100644 index 000000000000..d6c757eaf26b --- /dev/null +++ b/arch/arm/mach-vt8500/include/mach/system.h @@ -0,0 +1,18 @@ +/* + * arch/arm/mach-vt8500/include/mach/system.h + * + */ +#include <asm/io.h> + +/* PM Software Reset request register */ +#define VT8500_PMSR_VIRT 0xf8130060 + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode, const char *cmd) +{ + writel(1, VT8500_PMSR_VIRT); +} diff --git a/arch/arm/mach-vt8500/include/mach/timex.h b/arch/arm/mach-vt8500/include/mach/timex.h new file mode 100644 index 000000000000..8487e4c690b7 --- /dev/null +++ b/arch/arm/mach-vt8500/include/mach/timex.h @@ -0,0 +1,26 @@ +/* + * arch/arm/mach-vt8500/include/mach/timex.h + * + * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef MACH_TIMEX_H +#define MACH_TIMEX_H + +#define CLOCK_TICK_RATE (3000000) + +#endif /* MACH_TIMEX_H */ diff --git a/arch/arm/mach-vt8500/include/mach/uncompress.h b/arch/arm/mach-vt8500/include/mach/uncompress.h new file mode 100644 index 000000000000..bb9e2d23fee3 --- /dev/null +++ b/arch/arm/mach-vt8500/include/mach/uncompress.h @@ -0,0 +1,37 @@ +/* arch/arm/mach-vt8500/include/mach/uncompress.h + * + * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> + * + * Based on arch/arm/mach-dove/include/mach/uncompress.h + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#define UART0_PHYS 0xd8200000 +#include <asm/io.h> + +static void putc(const char c) +{ + while (readb(UART0_PHYS + 0x1c) & 0x2) + /* Tx busy, wait and poll */; + + writeb(c, UART0_PHYS); +} + +static void flush(void) +{ +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/arch/arm/mach-vt8500/include/mach/vmalloc.h b/arch/arm/mach-vt8500/include/mach/vmalloc.h new file mode 100644 index 000000000000..4642290ce416 --- /dev/null +++ b/arch/arm/mach-vt8500/include/mach/vmalloc.h @@ -0,0 +1,20 @@ +/* + * arch/arm/mach-vt8500/include/mach/vmalloc.h + * + * Copyright (C) 2000 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#define VMALLOC_END 0xd0000000UL diff --git a/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h b/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h new file mode 100644 index 000000000000..ecfee9124711 --- /dev/null +++ b/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h @@ -0,0 +1,88 @@ +/* + * arch/arm/mach-vt8500/include/mach/vt8500_irqs.h + * + * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* VT8500 Interrupt Sources */ + +#define IRQ_JPEGENC 0 /* JPEG Encoder */ +#define IRQ_JPEGDEC 1 /* JPEG Decoder */ + /* Reserved */ +#define IRQ_PATA 3 /* PATA Controller */ + /* Reserved */ +#define IRQ_DMA 5 /* DMA Controller */ +#define IRQ_EXT0 6 /* External Interrupt 0 */ +#define IRQ_EXT1 7 /* External Interrupt 1 */ +#define IRQ_GE 8 /* Graphic Engine */ +#define IRQ_GOV 9 /* Graphic Overlay Engine */ +#define IRQ_ETHER 10 /* Ethernet MAC */ +#define IRQ_MPEGTS 11 /* Transport Stream Interface */ +#define IRQ_LCDC 12 /* LCD Controller */ +#define IRQ_EXT2 13 /* External Interrupt 2 */ +#define IRQ_EXT3 14 /* External Interrupt 3 */ +#define IRQ_EXT4 15 /* External Interrupt 4 */ +#define IRQ_CIPHER 16 /* Cipher */ +#define IRQ_VPP 17 /* Video Post-Processor */ +#define IRQ_I2C1 18 /* I2C 1 */ +#define IRQ_I2C0 19 /* I2C 0 */ +#define IRQ_SDMMC 20 /* SD/MMC Controller */ +#define IRQ_SDMMC_DMA 21 /* SD/MMC Controller DMA */ +#define IRQ_PMC_WU 22 /* Power Management Controller Wakeup */ + /* Reserved */ +#define IRQ_SPI0 24 /* SPI 0 */ +#define IRQ_SPI1 25 /* SPI 1 */ +#define IRQ_SPI2 26 /* SPI 2 */ +#define IRQ_LCDDF 27 /* LCD Data Formatter */ +#define IRQ_NAND 28 /* NAND Flash Controller */ +#define IRQ_NAND_DMA 29 /* NAND Flash Controller DMA */ +#define IRQ_MS 30 /* MemoryStick Controller */ +#define IRQ_MS_DMA 31 /* MemoryStick Controller DMA */ +#define IRQ_UART0 32 /* UART 0 */ +#define IRQ_UART1 33 /* UART 1 */ +#define IRQ_I2S 34 /* I2S */ +#define IRQ_PCM 35 /* PCM */ +#define IRQ_PMCOS0 36 /* PMC OS Timer 0 */ +#define IRQ_PMCOS1 37 /* PMC OS Timer 1 */ +#define IRQ_PMCOS2 38 /* PMC OS Timer 2 */ +#define IRQ_PMCOS3 39 /* PMC OS Timer 3 */ +#define IRQ_VPU 40 /* Video Processing Unit */ +#define IRQ_VID 41 /* Video Digital Input Interface */ +#define IRQ_AC97 42 /* AC97 Interface */ +#define IRQ_EHCI 43 /* USB */ +#define IRQ_NOR 44 /* NOR Flash Controller */ +#define IRQ_PS2MOUSE 45 /* PS/2 Mouse */ +#define IRQ_PS2KBD 46 /* PS/2 Keyboard */ +#define IRQ_UART2 47 /* UART 2 */ +#define IRQ_RTC 48 /* RTC Interrupt */ +#define IRQ_RTCSM 49 /* RTC Second/Minute Update Interrupt */ +#define IRQ_UART3 50 /* UART 3 */ +#define IRQ_ADC 51 /* ADC */ +#define IRQ_EXT5 52 /* External Interrupt 5 */ +#define IRQ_EXT6 53 /* External Interrupt 6 */ +#define IRQ_EXT7 54 /* External Interrupt 7 */ +#define IRQ_CIR 55 /* CIR */ +#define IRQ_DMA0 56 /* DMA Channel 0 */ +#define IRQ_DMA1 57 /* DMA Channel 1 */ +#define IRQ_DMA2 58 /* DMA Channel 2 */ +#define IRQ_DMA3 59 /* DMA Channel 3 */ +#define IRQ_DMA4 60 /* DMA Channel 4 */ +#define IRQ_DMA5 61 /* DMA Channel 5 */ +#define IRQ_DMA6 62 /* DMA Channel 6 */ +#define IRQ_DMA7 63 /* DMA Channel 7 */ + +#define VT8500_NR_IRQS 64 diff --git a/arch/arm/mach-vt8500/include/mach/vt8500_regs.h b/arch/arm/mach-vt8500/include/mach/vt8500_regs.h new file mode 100644 index 000000000000..29c63ecb2383 --- /dev/null +++ b/arch/arm/mach-vt8500/include/mach/vt8500_regs.h @@ -0,0 +1,79 @@ +/* + * arch/arm/mach-vt8500/include/mach/vt8500_regs.h + * + * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARM_ARCH_VT8500_REGS_H +#define __ASM_ARM_ARCH_VT8500_REGS_H + +/* VT8500 Registers Map */ + +#define VT8500_REGS_START_PHYS 0xd8000000 /* Start of MMIO registers */ +#define VT8500_REGS_START_VIRT 0xf8000000 /* Virtual mapping start */ + +#define VT8500_DDR_BASE 0xd8000000 /* 1k DDR/DDR2 Memory + Controller */ +#define VT8500_DMA_BASE 0xd8001000 /* 1k DMA Controller */ +#define VT8500_SFLASH_BASE 0xd8002000 /* 1k Serial Flash Memory + Controller */ +#define VT8500_ETHER_BASE 0xd8004000 /* 1k Ethernet MAC 0 */ +#define VT8500_CIPHER_BASE 0xd8006000 /* 4k Cipher */ +#define VT8500_USB_BASE 0xd8007800 /* 2k USB OTG */ +# define VT8500_EHCI_BASE 0xd8007900 /* EHCI */ +# define VT8500_UHCI_BASE 0xd8007b01 /* UHCI */ +#define VT8500_PATA_BASE 0xd8008000 /* 512 PATA */ +#define VT8500_PS2_BASE 0xd8008800 /* 1k PS/2 */ +#define VT8500_NAND_BASE 0xd8009000 /* 1k NAND Controller */ +#define VT8500_NOR_BASE 0xd8009400 /* 1k NOR Controller */ +#define VT8500_SDMMC_BASE 0xd800a000 /* 1k SD/MMC Controller */ +#define VT8500_MS_BASE 0xd800b000 /* 1k MS/MSPRO Controller */ +#define VT8500_LCDC_BASE 0xd800e400 /* 1k LCD Controller */ +#define VT8500_VPU_BASE 0xd8050000 /* 256 VPU */ +#define VT8500_GOV_BASE 0xd8050300 /* 256 GOV */ +#define VT8500_GEGEA_BASE 0xd8050400 /* 768 GE/GE Alpha Mixing */ +#define VT8500_LCDF_BASE 0xd8050900 /* 256 LCD Formatter */ +#define VT8500_VID_BASE 0xd8050a00 /* 256 VID */ +#define VT8500_VPP_BASE 0xd8050b00 /* 256 VPP */ +#define VT8500_TSBK_BASE 0xd80f4000 /* 4k TSBK */ +#define VT8500_JPEGDEC_BASE 0xd80fe000 /* 4k JPEG Decoder */ +#define VT8500_JPEGENC_BASE 0xd80ff000 /* 4k JPEG Encoder */ +#define VT8500_RTC_BASE 0xd8100000 /* 64k RTC */ +#define VT8500_GPIO_BASE 0xd8110000 /* 64k GPIO Configuration */ +#define VT8500_SCC_BASE 0xd8120000 /* 64k System Configuration*/ +#define VT8500_PMC_BASE 0xd8130000 /* 64k PMC Configuration */ +#define VT8500_IC_BASE 0xd8140000 /* 64k Interrupt Controller*/ +#define VT8500_UART0_BASE 0xd8200000 /* 64k UART 0 */ +#define VT8500_UART2_BASE 0xd8210000 /* 64k UART 2 */ +#define VT8500_PWM_BASE 0xd8220000 /* 64k PWM Configuration */ +#define VT8500_SPI0_BASE 0xd8240000 /* 64k SPI 0 */ +#define VT8500_SPI1_BASE 0xd8250000 /* 64k SPI 1 */ +#define VT8500_CIR_BASE 0xd8270000 /* 64k CIR */ +#define VT8500_I2C0_BASE 0xd8280000 /* 64k I2C 0 */ +#define VT8500_AC97_BASE 0xd8290000 /* 64k AC97 */ +#define VT8500_SPI2_BASE 0xd82a0000 /* 64k SPI 2 */ +#define VT8500_UART1_BASE 0xd82b0000 /* 64k UART 1 */ +#define VT8500_UART3_BASE 0xd82c0000 /* 64k UART 3 */ +#define VT8500_PCM_BASE 0xd82d0000 /* 64k PCM */ +#define VT8500_I2C1_BASE 0xd8320000 /* 64k I2C 1 */ +#define VT8500_I2S_BASE 0xd8330000 /* 64k I2S */ +#define VT8500_ADC_BASE 0xd8340000 /* 64k ADC */ + +#define VT8500_REGS_END_PHYS 0xd834ffff /* End of MMIO registers */ +#define VT8500_REGS_LENGTH (VT8500_REGS_END_PHYS \ + - VT8500_REGS_START_PHYS + 1) + +#endif diff --git a/arch/arm/mach-vt8500/include/mach/vt8500fb.h b/arch/arm/mach-vt8500/include/mach/vt8500fb.h new file mode 100644 index 000000000000..7f399c370fe0 --- /dev/null +++ b/arch/arm/mach-vt8500/include/mach/vt8500fb.h @@ -0,0 +1,31 @@ +/* + * VT8500/WM8505 Frame Buffer platform data definitions + * + * Copyright (C) 2010 Ed Spiridonov <edo.rus@gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _VT8500FB_H +#define _VT8500FB_H + +#include <linux/fb.h> + +struct vt8500fb_platform_data { + struct fb_videomode mode; + u32 xres_virtual; + u32 yres_virtual; + u32 bpp; + unsigned long video_mem_phys; + void *video_mem_virt; + unsigned long video_mem_len; +}; + +#endif /* _VT8500FB_H */ diff --git a/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h b/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h new file mode 100644 index 000000000000..6128627ac753 --- /dev/null +++ b/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h @@ -0,0 +1,115 @@ +/* + * arch/arm/mach-vt8500/include/mach/wm8505_irqs.h + * + * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* WM8505 Interrupt Sources */ + +#define IRQ_UHCI 0 /* UHC FS (UHCI?) */ +#define IRQ_EHCI 1 /* UHC HS */ +#define IRQ_UDCDMA 2 /* UDC DMA */ + /* Reserved */ +#define IRQ_PS2MOUSE 4 /* PS/2 Mouse */ +#define IRQ_UDC 5 /* UDC */ +#define IRQ_EXT0 6 /* External Interrupt 0 */ +#define IRQ_EXT1 7 /* External Interrupt 1 */ +#define IRQ_KEYPAD 8 /* Keypad */ +#define IRQ_DMA 9 /* DMA Controller */ +#define IRQ_ETHER 10 /* Ethernet MAC */ + /* Reserved */ + /* Reserved */ +#define IRQ_EXT2 13 /* External Interrupt 2 */ +#define IRQ_EXT3 14 /* External Interrupt 3 */ +#define IRQ_EXT4 15 /* External Interrupt 4 */ +#define IRQ_APB 16 /* APB Bridge */ +#define IRQ_DMA0 17 /* DMA Channel 0 */ +#define IRQ_I2C1 18 /* I2C 1 */ +#define IRQ_I2C0 19 /* I2C 0 */ +#define IRQ_SDMMC 20 /* SD/MMC Controller */ +#define IRQ_SDMMC_DMA 21 /* SD/MMC Controller DMA */ +#define IRQ_PMC_WU 22 /* Power Management Controller Wakeup */ +#define IRQ_PS2KBD 23 /* PS/2 Keyboard */ +#define IRQ_SPI0 24 /* SPI 0 */ +#define IRQ_SPI1 25 /* SPI 1 */ +#define IRQ_SPI2 26 /* SPI 2 */ +#define IRQ_DMA1 27 /* DMA Channel 1 */ +#define IRQ_NAND 28 /* NAND Flash Controller */ +#define IRQ_NAND_DMA 29 /* NAND Flash Controller DMA */ +#define IRQ_UART5 30 /* UART 5 */ +#define IRQ_UART4 31 /* UART 4 */ +#define IRQ_UART0 32 /* UART 0 */ +#define IRQ_UART1 33 /* UART 1 */ +#define IRQ_DMA2 34 /* DMA Channel 2 */ +#define IRQ_I2S 35 /* I2S */ +#define IRQ_PMCOS0 36 /* PMC OS Timer 0 */ +#define IRQ_PMCOS1 37 /* PMC OS Timer 1 */ +#define IRQ_PMCOS2 38 /* PMC OS Timer 2 */ +#define IRQ_PMCOS3 39 /* PMC OS Timer 3 */ +#define IRQ_DMA3 40 /* DMA Channel 3 */ +#define IRQ_DMA4 41 /* DMA Channel 4 */ +#define IRQ_AC97 42 /* AC97 Interface */ + /* Reserved */ +#define IRQ_NOR 44 /* NOR Flash Controller */ +#define IRQ_DMA5 45 /* DMA Channel 5 */ +#define IRQ_DMA6 46 /* DMA Channel 6 */ +#define IRQ_UART2 47 /* UART 2 */ +#define IRQ_RTC 48 /* RTC Interrupt */ +#define IRQ_RTCSM 49 /* RTC Second/Minute Update Interrupt */ +#define IRQ_UART3 50 /* UART 3 */ +#define IRQ_DMA7 51 /* DMA Channel 7 */ +#define IRQ_EXT5 52 /* External Interrupt 5 */ +#define IRQ_EXT6 53 /* External Interrupt 6 */ +#define IRQ_EXT7 54 /* External Interrupt 7 */ +#define IRQ_CIR 55 /* CIR */ +#define IRQ_SIC0 56 /* SIC IRQ0 */ +#define IRQ_SIC1 57 /* SIC IRQ1 */ +#define IRQ_SIC2 58 /* SIC IRQ2 */ +#define IRQ_SIC3 59 /* SIC IRQ3 */ +#define IRQ_SIC4 60 /* SIC IRQ4 */ +#define IRQ_SIC5 61 /* SIC IRQ5 */ +#define IRQ_SIC6 62 /* SIC IRQ6 */ +#define IRQ_SIC7 63 /* SIC IRQ7 */ + /* Reserved */ +#define IRQ_JPEGDEC 65 /* JPEG Decoder */ +#define IRQ_SAE 66 /* SAE (?) */ + /* Reserved */ +#define IRQ_VPU 79 /* Video Processing Unit */ +#define IRQ_VPP 80 /* Video Post-Processor */ +#define IRQ_VID 81 /* Video Digital Input Interface */ +#define IRQ_SPU 82 /* SPU (?) */ +#define IRQ_PIP 83 /* PIP Error */ +#define IRQ_GE 84 /* Graphic Engine */ +#define IRQ_GOV 85 /* Graphic Overlay Engine */ +#define IRQ_DVO 86 /* Digital Video Output */ + /* Reserved */ +#define IRQ_DMA8 92 /* DMA Channel 8 */ +#define IRQ_DMA9 93 /* DMA Channel 9 */ +#define IRQ_DMA10 94 /* DMA Channel 10 */ +#define IRQ_DMA11 95 /* DMA Channel 11 */ +#define IRQ_DMA12 96 /* DMA Channel 12 */ +#define IRQ_DMA13 97 /* DMA Channel 13 */ +#define IRQ_DMA14 98 /* DMA Channel 14 */ +#define IRQ_DMA15 99 /* DMA Channel 15 */ + /* Reserved */ +#define IRQ_GOVW 111 /* GOVW (?) */ +#define IRQ_GOVRSDSCD 112 /* GOVR SDSCD (?) */ +#define IRQ_GOVRSDMIF 113 /* GOVR SDMIF (?) */ +#define IRQ_GOVRHDSCD 114 /* GOVR HDSCD (?) */ +#define IRQ_GOVRHDMIF 115 /* GOVR HDMIF (?) */ + +#define WM8505_NR_IRQS 116 diff --git a/arch/arm/mach-vt8500/include/mach/wm8505_regs.h b/arch/arm/mach-vt8500/include/mach/wm8505_regs.h new file mode 100644 index 000000000000..df1550941efb --- /dev/null +++ b/arch/arm/mach-vt8500/include/mach/wm8505_regs.h @@ -0,0 +1,78 @@ +/* + * arch/arm/mach-vt8500/include/mach/wm8505_regs.h + * + * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARM_ARCH_WM8505_REGS_H +#define __ASM_ARM_ARCH_WM8505_REGS_H + +/* WM8505 Registers Map */ + +#define WM8505_REGS_START_PHYS 0xd8000000 /* Start of MMIO registers */ +#define WM8505_REGS_START_VIRT 0xf8000000 /* Virtual mapping start */ + +#define WM8505_DDR_BASE 0xd8000400 /* 1k DDR/DDR2 Memory + Controller */ +#define WM8505_DMA_BASE 0xd8001800 /* 1k DMA Controller */ +#define WM8505_VDMA_BASE 0xd8001c00 /* 1k VDMA */ +#define WM8505_SFLASH_BASE 0xd8002000 /* 1k Serial Flash Memory + Controller */ +#define WM8505_ETHER_BASE 0xd8004000 /* 1k Ethernet MAC 0 */ +#define WM8505_CIPHER_BASE 0xd8006000 /* 4k Cipher */ +#define WM8505_USB_BASE 0xd8007000 /* 2k USB 2.0 Host */ +# define WM8505_EHCI_BASE 0xd8007100 /* EHCI */ +# define WM8505_UHCI_BASE 0xd8007301 /* UHCI */ +#define WM8505_PS2_BASE 0xd8008800 /* 1k PS/2 */ +#define WM8505_NAND_BASE 0xd8009000 /* 1k NAND Controller */ +#define WM8505_NOR_BASE 0xd8009400 /* 1k NOR Controller */ +#define WM8505_SDMMC_BASE 0xd800a000 /* 1k SD/MMC Controller */ +#define WM8505_VPU_BASE 0xd8050000 /* 256 VPU */ +#define WM8505_GOV_BASE 0xd8050300 /* 256 GOV */ +#define WM8505_GEGEA_BASE 0xd8050400 /* 768 GE/GE Alpha Mixing */ +#define WM8505_GOVR_BASE 0xd8050800 /* 512 GOVR (frambuffer) */ +#define WM8505_VID_BASE 0xd8050a00 /* 256 VID */ +#define WM8505_SCL_BASE 0xd8050d00 /* 256 SCL */ +#define WM8505_VPP_BASE 0xd8050f00 /* 256 VPP */ +#define WM8505_JPEGDEC_BASE 0xd80fe000 /* 4k JPEG Decoder */ +#define WM8505_RTC_BASE 0xd8100000 /* 64k RTC */ +#define WM8505_GPIO_BASE 0xd8110000 /* 64k GPIO Configuration */ +#define WM8505_SCC_BASE 0xd8120000 /* 64k System Configuration*/ +#define WM8505_PMC_BASE 0xd8130000 /* 64k PMC Configuration */ +#define WM8505_IC_BASE 0xd8140000 /* 64k Interrupt Controller*/ +#define WM8505_SIC_BASE 0xd8150000 /* 64k Secondary IC */ +#define WM8505_UART0_BASE 0xd8200000 /* 64k UART 0 */ +#define WM8505_UART2_BASE 0xd8210000 /* 64k UART 2 */ +#define WM8505_PWM_BASE 0xd8220000 /* 64k PWM Configuration */ +#define WM8505_SPI0_BASE 0xd8240000 /* 64k SPI 0 */ +#define WM8505_SPI1_BASE 0xd8250000 /* 64k SPI 1 */ +#define WM8505_KEYPAD_BASE 0xd8260000 /* 64k Keypad control */ +#define WM8505_CIR_BASE 0xd8270000 /* 64k CIR */ +#define WM8505_I2C0_BASE 0xd8280000 /* 64k I2C 0 */ +#define WM8505_AC97_BASE 0xd8290000 /* 64k AC97 */ +#define WM8505_SPI2_BASE 0xd82a0000 /* 64k SPI 2 */ +#define WM8505_UART1_BASE 0xd82b0000 /* 64k UART 1 */ +#define WM8505_UART3_BASE 0xd82c0000 /* 64k UART 3 */ +#define WM8505_I2C1_BASE 0xd8320000 /* 64k I2C 1 */ +#define WM8505_I2S_BASE 0xd8330000 /* 64k I2S */ +#define WM8505_UART4_BASE 0xd8370000 /* 64k UART 4 */ +#define WM8505_UART5_BASE 0xd8380000 /* 64k UART 5 */ + +#define WM8505_REGS_END_PHYS 0xd838ffff /* End of MMIO registers */ +#define WM8505_REGS_LENGTH (WM8505_REGS_END_PHYS \ + - WM8505_REGS_START_PHYS + 1) + +#endif diff --git a/arch/arm/mach-vt8500/irq.c b/arch/arm/mach-vt8500/irq.c new file mode 100644 index 000000000000..5f4ddde4f02a --- /dev/null +++ b/arch/arm/mach-vt8500/irq.c @@ -0,0 +1,177 @@ +/* + * arch/arm/mach-vt8500/irq.c + * + * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/interrupt.h> + +#include <asm/irq.h> + +#include "devices.h" + +#define VT8500_IC_DCTR 0x40 /* Destination control + register, 64*u8 */ +#define VT8500_INT_ENABLE (1 << 3) +#define VT8500_TRIGGER_HIGH (0 << 4) +#define VT8500_TRIGGER_RISING (1 << 4) +#define VT8500_TRIGGER_FALLING (2 << 4) +#define VT8500_EDGE ( VT8500_TRIGGER_RISING \ + | VT8500_TRIGGER_FALLING) +#define VT8500_IC_STATUS 0x80 /* Interrupt status, 2*u32 */ + +static void __iomem *ic_regbase; +static void __iomem *sic_regbase; + +static void vt8500_irq_mask(unsigned int irq) +{ + void __iomem *base = ic_regbase; + u8 edge; + + if (irq >= 64) { + base = sic_regbase; + irq -= 64; + } + edge = readb(base + VT8500_IC_DCTR + irq) & VT8500_EDGE; + if (edge) { + void __iomem *stat_reg = base + VT8500_IC_STATUS + + (irq < 32 ? 0 : 4); + unsigned status = readl(stat_reg); + + status |= (1 << (irq & 0x1f)); + writel(status, stat_reg); + } else { + u8 dctr = readb(base + VT8500_IC_DCTR + irq); + + dctr &= ~VT8500_INT_ENABLE; + writeb(dctr, base + VT8500_IC_DCTR + irq); + } +} + +static void vt8500_irq_unmask(unsigned int irq) +{ + void __iomem *base = ic_regbase; + u8 dctr; + + if (irq >= 64) { + base = sic_regbase; + irq -= 64; + } + dctr = readb(base + VT8500_IC_DCTR + irq); + dctr |= VT8500_INT_ENABLE; + writeb(dctr, base + VT8500_IC_DCTR + irq); +} + +static int vt8500_irq_set_type(unsigned int irq, unsigned int flow_type) +{ + void __iomem *base = ic_regbase; + unsigned int orig_irq = irq; + u8 dctr; + + if (irq >= 64) { + base = sic_regbase; + irq -= 64; + } + + dctr = readb(base + VT8500_IC_DCTR + irq); + dctr &= ~VT8500_EDGE; + + switch (flow_type) { + case IRQF_TRIGGER_LOW: + return -EINVAL; + case IRQF_TRIGGER_HIGH: + dctr |= VT8500_TRIGGER_HIGH; + irq_desc[orig_irq].handle_irq = handle_level_irq; + break; + case IRQF_TRIGGER_FALLING: + dctr |= VT8500_TRIGGER_FALLING; + irq_desc[orig_irq].handle_irq = handle_edge_irq; + break; + case IRQF_TRIGGER_RISING: + dctr |= VT8500_TRIGGER_RISING; + irq_desc[orig_irq].handle_irq = handle_edge_irq; + break; + } + writeb(dctr, base + VT8500_IC_DCTR + irq); + + return 0; +} + +static struct irq_chip vt8500_irq_chip = { + .name = "vt8500", + .ack = vt8500_irq_mask, + .mask = vt8500_irq_mask, + .unmask = vt8500_irq_unmask, + .set_type = vt8500_irq_set_type, +}; + +void __init vt8500_init_irq(void) +{ + unsigned int i; + + ic_regbase = ioremap(wmt_ic_base, SZ_64K); + + if (ic_regbase) { + /* Enable rotating priority for IRQ */ + writel((1 << 6), ic_regbase + 0x20); + writel(0, ic_regbase + 0x24); + + for (i = 0; i < wmt_nr_irqs; i++) { + /* Disable all interrupts and route them to IRQ */ + writeb(0x00, ic_regbase + VT8500_IC_DCTR + i); + + set_irq_chip(i, &vt8500_irq_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + } else { + printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n"); + } +} + +void __init wm8505_init_irq(void) +{ + unsigned int i; + + ic_regbase = ioremap(wmt_ic_base, SZ_64K); + sic_regbase = ioremap(wmt_sic_base, SZ_64K); + + if (ic_regbase && sic_regbase) { + /* Enable rotating priority for IRQ */ + writel((1 << 6), ic_regbase + 0x20); + writel(0, ic_regbase + 0x24); + writel((1 << 6), sic_regbase + 0x20); + writel(0, sic_regbase + 0x24); + + for (i = 0; i < wmt_nr_irqs; i++) { + /* Disable all interrupts and route them to IRQ */ + if (i < 64) + writeb(0x00, ic_regbase + VT8500_IC_DCTR + i); + else + writeb(0x00, sic_regbase + VT8500_IC_DCTR + + i - 64); + + set_irq_chip(i, &vt8500_irq_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + } else { + printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n"); + } +} diff --git a/arch/arm/mach-vt8500/pwm.c b/arch/arm/mach-vt8500/pwm.c new file mode 100644 index 000000000000..8ad825e93592 --- /dev/null +++ b/arch/arm/mach-vt8500/pwm.c @@ -0,0 +1,265 @@ +/* + * arch/arm/mach-vt8500/pwm.c + * + * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/pwm.h> +#include <linux/delay.h> + +#include <asm/div64.h> + +#define VT8500_NR_PWMS 4 + +static DEFINE_MUTEX(pwm_lock); +static LIST_HEAD(pwm_list); + +struct pwm_device { + struct list_head node; + struct platform_device *pdev; + + const char *label; + + void __iomem *regbase; + + unsigned int use_count; + unsigned int pwm_id; +}; + +#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) +static inline void pwm_busy_wait(void __iomem *reg, u8 bitmask) +{ + int loops = msecs_to_loops(10); + while ((readb(reg) & bitmask) && --loops) + cpu_relax(); + + if (unlikely(!loops)) + pr_warning("Waiting for status bits 0x%x to clear timed out\n", + bitmask); +} + +int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) +{ + unsigned long long c; + unsigned long period_cycles, prescale, pv, dc; + + if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) + return -EINVAL; + + c = 25000000/2; /* wild guess --- need to implement clocks */ + c = c * period_ns; + do_div(c, 1000000000); + period_cycles = c; + + if (period_cycles < 1) + period_cycles = 1; + prescale = (period_cycles - 1) / 4096; + pv = period_cycles / (prescale + 1) - 1; + if (pv > 4095) + pv = 4095; + + if (prescale > 1023) + return -EINVAL; + + c = (unsigned long long)pv * duty_ns; + do_div(c, period_ns); + dc = c; + + pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 1)); + writel(prescale, pwm->regbase + 0x4 + (pwm->pwm_id << 4)); + + pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 2)); + writel(pv, pwm->regbase + 0x8 + (pwm->pwm_id << 4)); + + pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 3)); + writel(dc, pwm->regbase + 0xc + (pwm->pwm_id << 4)); + + return 0; +} +EXPORT_SYMBOL(pwm_config); + +int pwm_enable(struct pwm_device *pwm) +{ + pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 0)); + writel(5, pwm->regbase + (pwm->pwm_id << 4)); + return 0; +} +EXPORT_SYMBOL(pwm_enable); + +void pwm_disable(struct pwm_device *pwm) +{ + pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 0)); + writel(0, pwm->regbase + (pwm->pwm_id << 4)); +} +EXPORT_SYMBOL(pwm_disable); + +struct pwm_device *pwm_request(int pwm_id, const char *label) +{ + struct pwm_device *pwm; + int found = 0; + + mutex_lock(&pwm_lock); + + list_for_each_entry(pwm, &pwm_list, node) { + if (pwm->pwm_id == pwm_id) { + found = 1; + break; + } + } + + if (found) { + if (pwm->use_count == 0) { + pwm->use_count++; + pwm->label = label; + } else { + pwm = ERR_PTR(-EBUSY); + } + } else { + pwm = ERR_PTR(-ENOENT); + } + + mutex_unlock(&pwm_lock); + return pwm; +} +EXPORT_SYMBOL(pwm_request); + +void pwm_free(struct pwm_device *pwm) +{ + mutex_lock(&pwm_lock); + + if (pwm->use_count) { + pwm->use_count--; + pwm->label = NULL; + } else { + pr_warning("PWM device already freed\n"); + } + + mutex_unlock(&pwm_lock); +} +EXPORT_SYMBOL(pwm_free); + +static inline void __add_pwm(struct pwm_device *pwm) +{ + mutex_lock(&pwm_lock); + list_add_tail(&pwm->node, &pwm_list); + mutex_unlock(&pwm_lock); +} + +static int __devinit pwm_probe(struct platform_device *pdev) +{ + struct pwm_device *pwms; + struct resource *r; + int ret = 0; + int i; + + pwms = kzalloc(sizeof(struct pwm_device) * VT8500_NR_PWMS, GFP_KERNEL); + if (pwms == NULL) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + return -ENOMEM; + } + + for (i = 0; i < VT8500_NR_PWMS; i++) { + pwms[i].use_count = 0; + pwms[i].pwm_id = i; + pwms[i].pdev = pdev; + } + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (r == NULL) { + dev_err(&pdev->dev, "no memory resource defined\n"); + ret = -ENODEV; + goto err_free; + } + + r = request_mem_region(r->start, resource_size(r), pdev->name); + if (r == NULL) { + dev_err(&pdev->dev, "failed to request memory resource\n"); + ret = -EBUSY; + goto err_free; + } + + pwms[0].regbase = ioremap(r->start, resource_size(r)); + if (pwms[0].regbase == NULL) { + dev_err(&pdev->dev, "failed to ioremap() registers\n"); + ret = -ENODEV; + goto err_free_mem; + } + + for (i = 1; i < VT8500_NR_PWMS; i++) + pwms[i].regbase = pwms[0].regbase; + + for (i = 0; i < VT8500_NR_PWMS; i++) + __add_pwm(&pwms[i]); + + platform_set_drvdata(pdev, pwms); + return 0; + +err_free_mem: + release_mem_region(r->start, resource_size(r)); +err_free: + kfree(pwms); + return ret; +} + +static int __devexit pwm_remove(struct platform_device *pdev) +{ + struct pwm_device *pwms; + struct resource *r; + int i; + + pwms = platform_get_drvdata(pdev); + if (pwms == NULL) + return -ENODEV; + + mutex_lock(&pwm_lock); + + for (i = 0; i < VT8500_NR_PWMS; i++) + list_del(&pwms[i].node); + mutex_unlock(&pwm_lock); + + iounmap(pwms[0].regbase); + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(r->start, resource_size(r)); + + kfree(pwms); + return 0; +} + +static struct platform_driver pwm_driver = { + .driver = { + .name = "vt8500-pwm", + .owner = THIS_MODULE, + }, + .probe = pwm_probe, + .remove = __devexit_p(pwm_remove), +}; + +static int __init pwm_init(void) +{ + return platform_driver_register(&pwm_driver); +} +arch_initcall(pwm_init); + +static void __exit pwm_exit(void) +{ + platform_driver_unregister(&pwm_driver); +} +module_exit(pwm_exit); + +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-vt8500/timer.c b/arch/arm/mach-vt8500/timer.c new file mode 100644 index 000000000000..d5376c592ab6 --- /dev/null +++ b/arch/arm/mach-vt8500/timer.c @@ -0,0 +1,155 @@ +/* + * arch/arm/mach-vt8500/timer.c + * + * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/clocksource.h> +#include <linux/clockchips.h> +#include <linux/delay.h> + +#include <asm/mach/time.h> + +#include "devices.h" + +#define VT8500_TIMER_OFFSET 0x0100 +#define TIMER_MATCH_VAL 0x0000 +#define TIMER_COUNT_VAL 0x0010 +#define TIMER_STATUS_VAL 0x0014 +#define TIMER_IER_VAL 0x001c /* interrupt enable */ +#define TIMER_CTRL_VAL 0x0020 +#define TIMER_AS_VAL 0x0024 /* access status */ +#define TIMER_COUNT_R_ACTIVE (1 << 5) /* not ready for read */ +#define TIMER_COUNT_W_ACTIVE (1 << 4) /* not ready for write */ +#define TIMER_MATCH_W_ACTIVE (1 << 0) /* not ready for write */ +#define VT8500_TIMER_HZ 3000000 + +#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) + +static void __iomem *regbase; + +static cycle_t vt8500_timer_read(struct clocksource *cs) +{ + int loops = msecs_to_loops(10); + writel(3, regbase + TIMER_CTRL_VAL); + while ((readl((regbase + TIMER_AS_VAL)) & TIMER_COUNT_R_ACTIVE) + && --loops) + cpu_relax(); + return readl(regbase + TIMER_COUNT_VAL); +} + +struct clocksource clocksource = { + .name = "vt8500_timer", + .rating = 200, + .read = vt8500_timer_read, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static int vt8500_timer_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + int loops = msecs_to_loops(10); + cycle_t alarm = clocksource.read(&clocksource) + cycles; + while ((readl(regbase + TIMER_AS_VAL) & TIMER_MATCH_W_ACTIVE) + && --loops) + cpu_relax(); + writel((unsigned long)alarm, regbase + TIMER_MATCH_VAL); + + if ((signed)(alarm - clocksource.read(&clocksource)) <= 16) + return -ETIME; + + writel(1, regbase + TIMER_IER_VAL); + + return 0; +} + +static void vt8500_timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + switch (mode) { + case CLOCK_EVT_MODE_RESUME: + case CLOCK_EVT_MODE_PERIODIC: + break; + case CLOCK_EVT_MODE_ONESHOT: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + writel(readl(regbase + TIMER_CTRL_VAL) | 1, + regbase + TIMER_CTRL_VAL); + writel(0, regbase + TIMER_IER_VAL); + break; + } +} + +struct clock_event_device clockevent = { + .name = "vt8500_timer", + .features = CLOCK_EVT_FEAT_ONESHOT, + .rating = 200, + .set_next_event = vt8500_timer_set_next_event, + .set_mode = vt8500_timer_set_mode, +}; + +static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = dev_id; + writel(0xf, regbase + TIMER_STATUS_VAL); + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +struct irqaction irq = { + .name = "vt8500_timer", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = vt8500_timer_interrupt, + .dev_id = &clockevent, +}; + +static void __init vt8500_timer_init(void) +{ + regbase = ioremap(wmt_pmc_base + VT8500_TIMER_OFFSET, 0x28); + if (!regbase) + printk(KERN_ERR "vt8500_timer_init: failed to map MMIO registers\n"); + + writel(1, regbase + TIMER_CTRL_VAL); + writel(0xf, regbase + TIMER_STATUS_VAL); + writel(~0, regbase + TIMER_MATCH_VAL); + + if (clocksource_register_hz(&clocksource, VT8500_TIMER_HZ)) + printk(KERN_ERR "vt8500_timer_init: clocksource_register failed for %s\n", + clocksource.name); + + clockevents_calc_mult_shift(&clockevent, VT8500_TIMER_HZ, 4); + + /* copy-pasted from mach-msm; no idea */ + clockevent.max_delta_ns = + clockevent_delta2ns(0xf0000000, &clockevent); + clockevent.min_delta_ns = clockevent_delta2ns(4, &clockevent); + clockevent.cpumask = cpumask_of(0); + + if (setup_irq(wmt_timer_irq, &irq)) + printk(KERN_ERR "vt8500_timer_init: setup_irq failed for %s\n", + clockevent.name); + clockevents_register_device(&clockevent); +} + +struct sys_timer vt8500_timer = { + .init = vt8500_timer_init +}; diff --git a/arch/arm/mach-vt8500/wm8505_7in.c b/arch/arm/mach-vt8500/wm8505_7in.c new file mode 100644 index 000000000000..e73aadbcafd6 --- /dev/null +++ b/arch/arm/mach-vt8500/wm8505_7in.c @@ -0,0 +1,77 @@ +/* + * arch/arm/mach-vt8500/wm8505_7in.c + * + * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/io.h> +#include <linux/pm.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include "devices.h" + +static void __iomem *pmc_hiber; + +static struct platform_device *devices[] __initdata = { + &vt8500_device_uart0, + &vt8500_device_ehci, + &vt8500_device_wm8505_fb, + &vt8500_device_ge_rops, + &vt8500_device_pwm, + &vt8500_device_pwmbl, + &vt8500_device_rtc, +}; + +static void vt8500_power_off(void) +{ + local_irq_disable(); + writew(5, pmc_hiber); + asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0)); +} + +void __init wm8505_7in_init(void) +{ +#ifdef CONFIG_FB_WM8505 + void __iomem *gpio_mux_reg = ioremap(wmt_gpio_base + 0x200, 4); + if (gpio_mux_reg) { + writel(readl(gpio_mux_reg) | 0x80000000, gpio_mux_reg); + iounmap(gpio_mux_reg); + } else { + printk(KERN_ERR "Could not remap the GPIO mux register, display may not work properly!\n"); + } +#endif + pmc_hiber = ioremap(wmt_pmc_base + 0x12, 2); + if (pmc_hiber) + pm_power_off = &vt8500_power_off; + else + printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n"); + + wm8505_set_resources(); + platform_add_devices(devices, ARRAY_SIZE(devices)); + vt8500_gpio_init(); +} + +MACHINE_START(WM8505_7IN_NETBOOK, "WM8505 7-inch generic netbook") + .boot_params = 0x00000100, + .reserve = wm8505_reserve_mem, + .map_io = wm8505_map_io, + .init_irq = wm8505_init_irq, + .timer = &vt8500_timer, + .init_machine = wm8505_7in_init, +MACHINE_END diff --git a/arch/arm/mach-w90x900/include/mach/memory.h b/arch/arm/mach-w90x900/include/mach/memory.h index 971b80702c27..f02905ba7746 100644 --- a/arch/arm/mach-w90x900/include/mach/memory.h +++ b/arch/arm/mach-w90x900/include/mach/memory.h @@ -18,6 +18,6 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index e4509bae8fc4..89266382b536 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -390,7 +390,7 @@ config CPU_PJ4 # ARMv6 config CPU_V6 - bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_DOVE + bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX select CPU_32v6 select CPU_ABRT_EV6 select CPU_PABRT_V6 @@ -402,16 +402,18 @@ config CPU_V6 select CPU_TLB_V6 if MMU # ARMv6k -config CPU_32v6K - bool "Support ARM V6K processor extensions" if !SMP - depends on CPU_V6 || CPU_V7 - default y if SMP - help - Say Y here if your ARMv6 processor supports the 'K' extension. - This enables the kernel to use some instructions not present - on previous processors, and as such a kernel build with this - enabled will not boot on processors with do not support these - instructions. +config CPU_V6K + bool "Support ARM V6K processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX + select CPU_32v6 + select CPU_32v6K + select CPU_ABRT_EV6 + select CPU_PABRT_V6 + select CPU_CACHE_V6 + select CPU_CACHE_VIPT + select CPU_CP15_MMU + select CPU_HAS_ASID if MMU + select CPU_COPY_V6 if MMU + select CPU_TLB_V6 if MMU # ARMv7 config CPU_V7 @@ -433,25 +435,33 @@ config CPU_32v3 bool select TLS_REG_EMUL if SMP || !MMU select NEEDS_SYSCALL_FOR_CMPXCHG if SMP + select CPU_USE_DOMAINS if MMU config CPU_32v4 bool select TLS_REG_EMUL if SMP || !MMU select NEEDS_SYSCALL_FOR_CMPXCHG if SMP + select CPU_USE_DOMAINS if MMU config CPU_32v4T bool select TLS_REG_EMUL if SMP || !MMU select NEEDS_SYSCALL_FOR_CMPXCHG if SMP + select CPU_USE_DOMAINS if MMU config CPU_32v5 bool select TLS_REG_EMUL if SMP || !MMU select NEEDS_SYSCALL_FOR_CMPXCHG if SMP + select CPU_USE_DOMAINS if MMU config CPU_32v6 bool select TLS_REG_EMUL if !CPU_32v6K && !MMU + select CPU_USE_DOMAINS if CPU_V6 && MMU + +config CPU_32v6K + bool config CPU_32v7 bool @@ -607,8 +617,6 @@ config CPU_CP15_MPU config CPU_USE_DOMAINS bool - depends on MMU - default y if !CPU_32v6K help This option enables or disables the use of domain switching via the set_fs() function. @@ -623,7 +631,7 @@ comment "Processor Features" config ARM_THUMB bool "Support Thumb user binaries" - depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V7 || CPU_FEROCEON + depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON default y help Say Y if you want to include kernel support for running user space @@ -644,7 +652,7 @@ config ARM_THUMBEE config SWP_EMULATE bool "Emulate SWP/SWPB instructions" - depends on !CPU_USE_DOMAINS && CPU_V7 && !CPU_V6 + depends on !CPU_USE_DOMAINS && CPU_V7 select HAVE_PROC_CPU if PROC_FS default y if SMP help @@ -681,7 +689,7 @@ config CPU_BIG_ENDIAN config CPU_ENDIAN_BE8 bool depends on CPU_BIG_ENDIAN - default CPU_V6 || CPU_V7 + default CPU_V6 || CPU_V6K || CPU_V7 help Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors. @@ -747,7 +755,7 @@ config CPU_CACHE_ROUND_ROBIN config CPU_BPREDICT_DISABLE bool "Disable branch prediction" - depends on CPU_ARM1020 || CPU_V6 || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 + depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 help Say Y here to disable branch prediction. If unsure, say N. @@ -767,7 +775,7 @@ config NEEDS_SYSCALL_FOR_CMPXCHG config DMA_CACHE_RWFO bool "Enable read/write for ownership DMA cache maintenance" - depends on CPU_V6 && SMP + depends on CPU_V6K && SMP default y help The Snoop Control Unit on ARM11MPCore does not detect the @@ -823,7 +831,7 @@ config CACHE_L2X0 config CACHE_PL310 bool depends on CACHE_L2X0 - default y if CPU_V7 && !CPU_V6 + default y if CPU_V7 && !(CPU_V6 || CPU_V6K) help This option enables optimisations for the PL310 cache controller. @@ -845,16 +853,21 @@ config CACHE_XSC3L2 help This option enables the L2 cache on XScale3. +config ARM_L1_CACHE_SHIFT_6 + bool + help + Setting ARM L1 cache line size to 64 Bytes. + config ARM_L1_CACHE_SHIFT int default 6 if ARM_L1_CACHE_SHIFT_6 default 5 config ARM_DMA_MEM_BUFFERABLE - bool "Use non-cacheable memory for DMA" if CPU_V6 && !CPU_V7 + bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7 depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \ MACH_REALVIEW_PB11MP) - default y if CPU_V6 || CPU_V7 + default y if CPU_V6 || CPU_V6K || CPU_V7 help Historically, the kernel has used strongly ordered mappings to provide DMA coherent memory. With the advent of ARMv7, mapping diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 00d74a04af3a..bca7e61928c7 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -90,6 +90,7 @@ obj-$(CONFIG_CPU_XSC3) += proc-xsc3.o obj-$(CONFIG_CPU_MOHAWK) += proc-mohawk.o obj-$(CONFIG_CPU_FEROCEON) += proc-feroceon.o obj-$(CONFIG_CPU_V6) += proc-v6.o +obj-$(CONFIG_CPU_V6K) += proc-v6.o obj-$(CONFIG_CPU_V7) += proc-v7.o AFLAGS_proc-v6.o :=-Wa,-march=armv6 diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S index f332df7f0d37..1478aa522144 100644 --- a/arch/arm/mm/abort-ev6.S +++ b/arch/arm/mm/abort-ev6.S @@ -20,11 +20,11 @@ */ .align 5 ENTRY(v6_early_abort) -#ifdef CONFIG_CPU_32v6K - clrex -#else +#ifdef CONFIG_CPU_V6 sub r1, sp, #4 @ Get unused stack location strex r0, r1, [r1] @ Clear the exclusive monitor +#elif defined(CONFIG_CPU_32v6K) + clrex #endif mrc p15, 0, r1, c5, c0, 0 @ get FSR mrc p15, 0, r0, c6, c0, 0 @ get FAR diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index f2ce38e085d2..ef59099a5463 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -73,18 +73,24 @@ static inline void l2x0_inv_line(unsigned long addr) writel_relaxed(addr, base + L2X0_INV_LINE_PA); } -#ifdef CONFIG_PL310_ERRATA_588369 -static void debug_writel(unsigned long val) -{ - extern void omap_smc1(u32 fn, u32 arg); +#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) - /* - * Texas Instrument secure monitor api to modify the - * PL310 Debug Control Register. - */ - omap_smc1(0x100, val); +#define debug_writel(val) outer_cache.set_debug(val) + +static void l2x0_set_debug(unsigned long val) +{ + writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL); } +#else +/* Optimised out for non-errata case */ +static inline void debug_writel(unsigned long val) +{ +} + +#define l2x0_set_debug NULL +#endif +#ifdef CONFIG_PL310_ERRATA_588369 static inline void l2x0_flush_line(unsigned long addr) { void __iomem *base = l2x0_base; @@ -97,11 +103,6 @@ static inline void l2x0_flush_line(unsigned long addr) } #else -/* Optimised out for non-errata case */ -static inline void debug_writel(unsigned long val) -{ -} - static inline void l2x0_flush_line(unsigned long addr) { void __iomem *base = l2x0_base; @@ -125,9 +126,11 @@ static void l2x0_flush_all(void) /* clean all ways */ spin_lock_irqsave(&l2x0_lock, flags); + debug_writel(0x03); writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY); cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask); cache_sync(); + debug_writel(0x00); spin_unlock_irqrestore(&l2x0_lock, flags); } @@ -335,6 +338,7 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) outer_cache.flush_all = l2x0_flush_all; outer_cache.inv_all = l2x0_inv_all; outer_cache.disable = l2x0_disable; + outer_cache.set_debug = l2x0_set_debug; printk(KERN_INFO "%s cache controller enabled\n", type); printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c index b0a98305055c..afe209e1e1f8 100644 --- a/arch/arm/mm/mmap.c +++ b/arch/arm/mm/mmap.c @@ -31,7 +31,7 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr, struct mm_struct *mm = current->mm; struct vm_area_struct *vma; unsigned long start_addr; -#ifdef CONFIG_CPU_V6 +#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) unsigned int cache_type; int do_align = 0, aliasing = 0; diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 3c67e92f7d59..ff7b43b5885a 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -827,16 +827,6 @@ static void __init sanity_check_meminfo(void) * rather difficult. */ reason = "with VIPT aliasing cache"; - } else if (is_smp() && tlb_ops_need_broadcast()) { - /* - * kmap_high needs to occasionally flush TLB entries, - * however, if the TLB entries need to be broadcast - * we may deadlock: - * kmap_high(irqs off)->flush_all_zero_pkmaps-> - * flush_tlb_kernel_range->smp_call_function_many - * (must not be called with irqs off) - */ - reason = "without hardware TLB ops broadcasting"; } if (reason) { printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n", diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S index bcf748d9f4e2..226e3d8351c2 100644 --- a/arch/arm/mm/proc-arm1020.S +++ b/arch/arm/mm/proc-arm1020.S @@ -493,6 +493,9 @@ arm1020_processor_functions: .word cpu_arm1020_dcache_clean_area .word cpu_arm1020_switch_mm .word cpu_arm1020_set_pte_ext + .word 0 + .word 0 + .word 0 .size arm1020_processor_functions, . - arm1020_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S index ab7ec26657ea..86d9c2cf0bce 100644 --- a/arch/arm/mm/proc-arm1020e.S +++ b/arch/arm/mm/proc-arm1020e.S @@ -474,6 +474,9 @@ arm1020e_processor_functions: .word cpu_arm1020e_dcache_clean_area .word cpu_arm1020e_switch_mm .word cpu_arm1020e_set_pte_ext + .word 0 + .word 0 + .word 0 .size arm1020e_processor_functions, . - arm1020e_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S index 831c5e54e22f..83d3dd34f846 100644 --- a/arch/arm/mm/proc-arm1022.S +++ b/arch/arm/mm/proc-arm1022.S @@ -457,6 +457,9 @@ arm1022_processor_functions: .word cpu_arm1022_dcache_clean_area .word cpu_arm1022_switch_mm .word cpu_arm1022_set_pte_ext + .word 0 + .word 0 + .word 0 .size arm1022_processor_functions, . - arm1022_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S index e3f7e9a166bf..686043ee7281 100644 --- a/arch/arm/mm/proc-arm1026.S +++ b/arch/arm/mm/proc-arm1026.S @@ -452,6 +452,9 @@ arm1026_processor_functions: .word cpu_arm1026_dcache_clean_area .word cpu_arm1026_switch_mm .word cpu_arm1026_set_pte_ext + .word 0 + .word 0 + .word 0 .size arm1026_processor_functions, . - arm1026_processor_functions .section .rodata diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S index 6a7be1863edd..5f79dc4ce3fb 100644 --- a/arch/arm/mm/proc-arm6_7.S +++ b/arch/arm/mm/proc-arm6_7.S @@ -284,6 +284,9 @@ ENTRY(arm6_processor_functions) .word cpu_arm6_dcache_clean_area .word cpu_arm6_switch_mm .word cpu_arm6_set_pte_ext + .word 0 + .word 0 + .word 0 .size arm6_processor_functions, . - arm6_processor_functions /* @@ -301,6 +304,9 @@ ENTRY(arm7_processor_functions) .word cpu_arm7_dcache_clean_area .word cpu_arm7_switch_mm .word cpu_arm7_set_pte_ext + .word 0 + .word 0 + .word 0 .size arm7_processor_functions, . - arm7_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S index c285395f44b2..665266da143c 100644 --- a/arch/arm/mm/proc-arm720.S +++ b/arch/arm/mm/proc-arm720.S @@ -185,6 +185,9 @@ ENTRY(arm720_processor_functions) .word cpu_arm720_dcache_clean_area .word cpu_arm720_switch_mm .word cpu_arm720_set_pte_ext + .word 0 + .word 0 + .word 0 .size arm720_processor_functions, . - arm720_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S index 38b27dcba727..6f9d12effee1 100644 --- a/arch/arm/mm/proc-arm740.S +++ b/arch/arm/mm/proc-arm740.S @@ -130,6 +130,9 @@ ENTRY(arm740_processor_functions) .word cpu_arm740_dcache_clean_area .word cpu_arm740_switch_mm .word 0 @ cpu_*_set_pte + .word 0 + .word 0 + .word 0 .size arm740_processor_functions, . - arm740_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S index 0c9786de20af..e4c165ca6696 100644 --- a/arch/arm/mm/proc-arm7tdmi.S +++ b/arch/arm/mm/proc-arm7tdmi.S @@ -70,6 +70,9 @@ ENTRY(arm7tdmi_processor_functions) .word cpu_arm7tdmi_dcache_clean_area .word cpu_arm7tdmi_switch_mm .word 0 @ cpu_*_set_pte + .word 0 + .word 0 + .word 0 .size arm7tdmi_processor_functions, . - arm7tdmi_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index 6109f278a904..219980ec8b6e 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S @@ -387,6 +387,40 @@ ENTRY(cpu_arm920_set_pte_ext) #endif mov pc, lr +/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ +.globl cpu_arm920_suspend_size +.equ cpu_arm920_suspend_size, 4 * 3 +#ifdef CONFIG_PM +ENTRY(cpu_arm920_do_suspend) + stmfd sp!, {r4 - r7, lr} + mrc p15, 0, r4, c13, c0, 0 @ PID + mrc p15, 0, r5, c3, c0, 0 @ Domain ID + mrc p15, 0, r6, c2, c0, 0 @ TTB address + mrc p15, 0, r7, c1, c0, 0 @ Control register + stmia r0, {r4 - r7} + ldmfd sp!, {r4 - r7, pc} +ENDPROC(cpu_arm920_do_suspend) + +ENTRY(cpu_arm920_do_resume) + mov ip, #0 + mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs + mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches + ldmia r0, {r4 - r7} + mcr p15, 0, r4, c13, c0, 0 @ PID + mcr p15, 0, r5, c3, c0, 0 @ Domain ID + mcr p15, 0, r6, c2, c0, 0 @ TTB address + mov r0, r7 @ control register + mov r2, r6, lsr #14 @ get TTB0 base + mov r2, r2, lsl #14 + ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \ + PMD_SECT_CACHEABLE | PMD_BIT4 | PMD_SECT_AP_WRITE + b cpu_resume_mmu +ENDPROC(cpu_arm920_do_resume) +#else +#define cpu_arm920_do_suspend 0 +#define cpu_arm920_do_resume 0 +#endif + __CPUINIT .type __arm920_setup, #function @@ -432,6 +466,9 @@ arm920_processor_functions: .word cpu_arm920_dcache_clean_area .word cpu_arm920_switch_mm .word cpu_arm920_set_pte_ext + .word cpu_arm920_suspend_size + .word cpu_arm920_do_suspend + .word cpu_arm920_do_resume .size arm920_processor_functions, . - arm920_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S index bb2f0f46a5e6..36154b1e792a 100644 --- a/arch/arm/mm/proc-arm922.S +++ b/arch/arm/mm/proc-arm922.S @@ -436,6 +436,9 @@ arm922_processor_functions: .word cpu_arm922_dcache_clean_area .word cpu_arm922_switch_mm .word cpu_arm922_set_pte_ext + .word 0 + .word 0 + .word 0 .size arm922_processor_functions, . - arm922_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S index c13e01accfe2..89c5e0009c4c 100644 --- a/arch/arm/mm/proc-arm925.S +++ b/arch/arm/mm/proc-arm925.S @@ -503,6 +503,9 @@ arm925_processor_functions: .word cpu_arm925_dcache_clean_area .word cpu_arm925_switch_mm .word cpu_arm925_set_pte_ext + .word 0 + .word 0 + .word 0 .size arm925_processor_functions, . - arm925_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index 42eb4315740b..6a4bdb2c94a7 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S @@ -401,6 +401,40 @@ ENTRY(cpu_arm926_set_pte_ext) #endif mov pc, lr +/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ +.globl cpu_arm926_suspend_size +.equ cpu_arm926_suspend_size, 4 * 3 +#ifdef CONFIG_PM +ENTRY(cpu_arm926_do_suspend) + stmfd sp!, {r4 - r7, lr} + mrc p15, 0, r4, c13, c0, 0 @ PID + mrc p15, 0, r5, c3, c0, 0 @ Domain ID + mrc p15, 0, r6, c2, c0, 0 @ TTB address + mrc p15, 0, r7, c1, c0, 0 @ Control register + stmia r0, {r4 - r7} + ldmfd sp!, {r4 - r7, pc} +ENDPROC(cpu_arm926_do_suspend) + +ENTRY(cpu_arm926_do_resume) + mov ip, #0 + mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs + mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches + ldmia r0, {r4 - r7} + mcr p15, 0, r4, c13, c0, 0 @ PID + mcr p15, 0, r5, c3, c0, 0 @ Domain ID + mcr p15, 0, r6, c2, c0, 0 @ TTB address + mov r0, r7 @ control register + mov r2, r6, lsr #14 @ get TTB0 base + mov r2, r2, lsl #14 + ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \ + PMD_SECT_CACHEABLE | PMD_BIT4 | PMD_SECT_AP_WRITE + b cpu_resume_mmu +ENDPROC(cpu_arm926_do_resume) +#else +#define cpu_arm926_do_suspend 0 +#define cpu_arm926_do_resume 0 +#endif + __CPUINIT .type __arm926_setup, #function @@ -456,6 +490,9 @@ arm926_processor_functions: .word cpu_arm926_dcache_clean_area .word cpu_arm926_switch_mm .word cpu_arm926_set_pte_ext + .word cpu_arm926_suspend_size + .word cpu_arm926_do_suspend + .word cpu_arm926_do_resume .size arm926_processor_functions, . - arm926_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S index 7b11cdb9935f..26aea3f71c26 100644 --- a/arch/arm/mm/proc-arm940.S +++ b/arch/arm/mm/proc-arm940.S @@ -363,6 +363,9 @@ ENTRY(arm940_processor_functions) .word cpu_arm940_dcache_clean_area .word cpu_arm940_switch_mm .word 0 @ cpu_*_set_pte + .word 0 + .word 0 + .word 0 .size arm940_processor_functions, . - arm940_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S index 1a5bbf080342..8063345406fe 100644 --- a/arch/arm/mm/proc-arm946.S +++ b/arch/arm/mm/proc-arm946.S @@ -419,6 +419,9 @@ ENTRY(arm946_processor_functions) .word cpu_arm946_dcache_clean_area .word cpu_arm946_switch_mm .word 0 @ cpu_*_set_pte + .word 0 + .word 0 + .word 0 .size arm946_processor_functions, . - arm946_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S index db67e3134d7a..7b7ebd4d096d 100644 --- a/arch/arm/mm/proc-arm9tdmi.S +++ b/arch/arm/mm/proc-arm9tdmi.S @@ -70,6 +70,9 @@ ENTRY(arm9tdmi_processor_functions) .word cpu_arm9tdmi_dcache_clean_area .word cpu_arm9tdmi_switch_mm .word 0 @ cpu_*_set_pte + .word 0 + .word 0 + .word 0 .size arm9tdmi_processor_functions, . - arm9tdmi_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S index 7c9ad621f0e6..fc2a4ae15cf4 100644 --- a/arch/arm/mm/proc-fa526.S +++ b/arch/arm/mm/proc-fa526.S @@ -195,6 +195,9 @@ fa526_processor_functions: .word cpu_fa526_dcache_clean_area .word cpu_fa526_switch_mm .word cpu_fa526_set_pte_ext + .word 0 + .word 0 + .word 0 .size fa526_processor_functions, . - fa526_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index b4597edbff97..d3883eed7a4a 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S @@ -554,6 +554,9 @@ feroceon_processor_functions: .word cpu_feroceon_dcache_clean_area .word cpu_feroceon_switch_mm .word cpu_feroceon_set_pte_ext + .word 0 + .word 0 + .word 0 .size feroceon_processor_functions, . - feroceon_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S index 4458ee6aa713..9d4f2ae63370 100644 --- a/arch/arm/mm/proc-mohawk.S +++ b/arch/arm/mm/proc-mohawk.S @@ -388,6 +388,9 @@ mohawk_processor_functions: .word cpu_mohawk_dcache_clean_area .word cpu_mohawk_switch_mm .word cpu_mohawk_set_pte_ext + .word 0 + .word 0 + .word 0 .size mohawk_processor_functions, . - mohawk_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S index 5aa8d59c2e85..46f09ed16b98 100644 --- a/arch/arm/mm/proc-sa110.S +++ b/arch/arm/mm/proc-sa110.S @@ -203,6 +203,9 @@ ENTRY(sa110_processor_functions) .word cpu_sa110_dcache_clean_area .word cpu_sa110_switch_mm .word cpu_sa110_set_pte_ext + .word 0 + .word 0 + .word 0 .size sa110_processor_functions, . - sa110_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S index 2ac4e6f10713..74483d1977fe 100644 --- a/arch/arm/mm/proc-sa1100.S +++ b/arch/arm/mm/proc-sa1100.S @@ -169,6 +169,42 @@ ENTRY(cpu_sa1100_set_pte_ext) #endif mov pc, lr +.globl cpu_sa1100_suspend_size +.equ cpu_sa1100_suspend_size, 4*4 +#ifdef CONFIG_PM +ENTRY(cpu_sa1100_do_suspend) + stmfd sp!, {r4 - r7, lr} + mrc p15, 0, r4, c3, c0, 0 @ domain ID + mrc p15, 0, r5, c2, c0, 0 @ translation table base addr + mrc p15, 0, r6, c13, c0, 0 @ PID + mrc p15, 0, r7, c1, c0, 0 @ control reg + stmia r0, {r4 - r7} @ store cp regs + ldmfd sp!, {r4 - r7, pc} +ENDPROC(cpu_sa1100_do_suspend) + +ENTRY(cpu_sa1100_do_resume) + ldmia r0, {r4 - r7} @ load cp regs + mov r1, #0 + mcr p15, 0, r1, c8, c7, 0 @ flush I+D TLBs + mcr p15, 0, r1, c7, c7, 0 @ flush I&D cache + mcr p15, 0, r1, c9, c0, 0 @ invalidate RB + mcr p15, 0, r1, c9, c0, 5 @ allow user space to use RB + + mcr p15, 0, r4, c3, c0, 0 @ domain ID + mcr p15, 0, r5, c2, c0, 0 @ translation table base addr + mcr p15, 0, r6, c13, c0, 0 @ PID + mov r0, r7 @ control register + mov r2, r5, lsr #14 @ get TTB0 base + mov r2, r2, lsl #14 + ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \ + PMD_SECT_CACHEABLE | PMD_SECT_AP_WRITE + b cpu_resume_mmu +ENDPROC(cpu_sa1100_do_resume) +#else +#define cpu_sa1100_do_suspend 0 +#define cpu_sa1100_do_resume 0 +#endif + __CPUINIT .type __sa1100_setup, #function @@ -218,6 +254,9 @@ ENTRY(sa1100_processor_functions) .word cpu_sa1100_dcache_clean_area .word cpu_sa1100_switch_mm .word cpu_sa1100_set_pte_ext + .word cpu_sa1100_suspend_size + .word cpu_sa1100_do_suspend + .word cpu_sa1100_do_resume .size sa1100_processor_functions, . - sa1100_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 59a7e1ffe7bc..832b6bdc192c 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -121,6 +121,53 @@ ENTRY(cpu_v6_set_pte_ext) #endif mov pc, lr +/* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */ +.globl cpu_v6_suspend_size +.equ cpu_v6_suspend_size, 4 * 8 +#ifdef CONFIG_PM +ENTRY(cpu_v6_do_suspend) + stmfd sp!, {r4 - r11, lr} + mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID + mrc p15, 0, r5, c13, c0, 1 @ Context ID + mrc p15, 0, r6, c3, c0, 0 @ Domain ID + mrc p15, 0, r7, c2, c0, 0 @ Translation table base 0 + mrc p15, 0, r8, c2, c0, 1 @ Translation table base 1 + mrc p15, 0, r9, c1, c0, 1 @ auxillary control register + mrc p15, 0, r10, c1, c0, 2 @ co-processor access control + mrc p15, 0, r11, c1, c0, 0 @ control register + stmia r0, {r4 - r11} + ldmfd sp!, {r4- r11, pc} +ENDPROC(cpu_v6_do_suspend) + +ENTRY(cpu_v6_do_resume) + mov ip, #0 + mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache + mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache + mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache + mcr p15, 0, ip, c7, c10, 4 @ drain write buffer + ldmia r0, {r4 - r11} + mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID + mcr p15, 0, r5, c13, c0, 1 @ Context ID + mcr p15, 0, r6, c3, c0, 0 @ Domain ID + mcr p15, 0, r7, c2, c0, 0 @ Translation table base 0 + mcr p15, 0, r8, c2, c0, 1 @ Translation table base 1 + mcr p15, 0, r9, c1, c0, 1 @ auxillary control register + mcr p15, 0, r10, c1, c0, 2 @ co-processor access control + mcr p15, 0, ip, c2, c0, 2 @ TTB control register + mcr p15, 0, ip, c7, c5, 4 @ ISB + mov r0, r11 @ control register + mov r2, r7, lsr #14 @ get TTB0 base + mov r2, r2, lsl #14 + ldr r3, cpu_resume_l1_flags + b cpu_resume_mmu +ENDPROC(cpu_v6_do_resume) +cpu_resume_l1_flags: + ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP) + ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP) +#else +#define cpu_v6_do_suspend 0 +#define cpu_v6_do_resume 0 +#endif .type cpu_v6_name, #object @@ -206,6 +253,9 @@ ENTRY(v6_processor_functions) .word cpu_v6_dcache_clean_area .word cpu_v6_switch_mm .word cpu_v6_set_pte_ext + .word cpu_v6_suspend_size + .word cpu_v6_do_suspend + .word cpu_v6_do_resume .size v6_processor_functions, . - v6_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 8e3356239136..262fa88a7439 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -108,10 +108,16 @@ ENTRY(cpu_v7_switch_mm) #ifdef CONFIG_ARM_ERRATA_430973 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB #endif +#ifdef CONFIG_ARM_ERRATA_754322 + dsb +#endif mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID isb 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 isb +#ifdef CONFIG_ARM_ERRATA_754322 + dsb +#endif mcr p15, 0, r1, c13, c0, 1 @ set context ID isb #endif @@ -171,6 +177,87 @@ cpu_v7_name: .ascii "ARMv7 Processor" .align + /* + * Memory region attributes with SCTLR.TRE=1 + * + * n = TEX[0],C,B + * TR = PRRR[2n+1:2n] - memory type + * IR = NMRR[2n+1:2n] - inner cacheable property + * OR = NMRR[2n+17:2n+16] - outer cacheable property + * + * n TR IR OR + * UNCACHED 000 00 + * BUFFERABLE 001 10 00 00 + * WRITETHROUGH 010 10 10 10 + * WRITEBACK 011 10 11 11 + * reserved 110 + * WRITEALLOC 111 10 01 01 + * DEV_SHARED 100 01 + * DEV_NONSHARED 100 01 + * DEV_WC 001 10 + * DEV_CACHED 011 10 + * + * Other attributes: + * + * DS0 = PRRR[16] = 0 - device shareable property + * DS1 = PRRR[17] = 1 - device shareable property + * NS0 = PRRR[18] = 0 - normal shareable property + * NS1 = PRRR[19] = 1 - normal shareable property + * NOS = PRRR[24+n] = 1 - not outer shareable + */ +.equ PRRR, 0xff0a81a8 +.equ NMRR, 0x40e040e0 + +/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ +.globl cpu_v7_suspend_size +.equ cpu_v7_suspend_size, 4 * 8 +#ifdef CONFIG_PM +ENTRY(cpu_v7_do_suspend) + stmfd sp!, {r4 - r11, lr} + mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID + mrc p15, 0, r5, c13, c0, 1 @ Context ID + mrc p15, 0, r6, c3, c0, 0 @ Domain ID + mrc p15, 0, r7, c2, c0, 0 @ TTB 0 + mrc p15, 0, r8, c2, c0, 1 @ TTB 1 + mrc p15, 0, r9, c1, c0, 0 @ Control register + mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register + mrc p15, 0, r11, c1, c0, 2 @ Co-processor access control + stmia r0, {r4 - r11} + ldmfd sp!, {r4 - r11, pc} +ENDPROC(cpu_v7_do_suspend) + +ENTRY(cpu_v7_do_resume) + mov ip, #0 + mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs + mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache + ldmia r0, {r4 - r11} + mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID + mcr p15, 0, r5, c13, c0, 1 @ Context ID + mcr p15, 0, r6, c3, c0, 0 @ Domain ID + mcr p15, 0, r7, c2, c0, 0 @ TTB 0 + mcr p15, 0, r8, c2, c0, 1 @ TTB 1 + mcr p15, 0, ip, c2, c0, 2 @ TTB control register + mcr p15, 0, r10, c1, c0, 1 @ Auxillary control register + mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control + ldr r4, =PRRR @ PRRR + ldr r5, =NMRR @ NMRR + mcr p15, 0, r4, c10, c2, 0 @ write PRRR + mcr p15, 0, r5, c10, c2, 1 @ write NMRR + isb + mov r0, r9 @ control register + mov r2, r7, lsr #14 @ get TTB0 base + mov r2, r2, lsl #14 + ldr r3, cpu_resume_l1_flags + b cpu_resume_mmu +ENDPROC(cpu_v7_do_resume) +cpu_resume_l1_flags: + ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP) + ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP) +#else +#define cpu_v7_do_suspend 0 +#define cpu_v7_do_resume 0 +#endif + __CPUINIT /* @@ -282,36 +369,8 @@ __v7_setup: ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) ALT_UP(orr r4, r4, #TTB_FLAGS_UP) mcr p15, 0, r4, c2, c0, 1 @ load TTB1 - /* - * Memory region attributes with SCTLR.TRE=1 - * - * n = TEX[0],C,B - * TR = PRRR[2n+1:2n] - memory type - * IR = NMRR[2n+1:2n] - inner cacheable property - * OR = NMRR[2n+17:2n+16] - outer cacheable property - * - * n TR IR OR - * UNCACHED 000 00 - * BUFFERABLE 001 10 00 00 - * WRITETHROUGH 010 10 10 10 - * WRITEBACK 011 10 11 11 - * reserved 110 - * WRITEALLOC 111 10 01 01 - * DEV_SHARED 100 01 - * DEV_NONSHARED 100 01 - * DEV_WC 001 10 - * DEV_CACHED 011 10 - * - * Other attributes: - * - * DS0 = PRRR[16] = 0 - device shareable property - * DS1 = PRRR[17] = 1 - device shareable property - * NS0 = PRRR[18] = 0 - normal shareable property - * NS1 = PRRR[19] = 1 - normal shareable property - * NOS = PRRR[24+n] = 1 - not outer shareable - */ - ldr r5, =0xff0a81a8 @ PRRR - ldr r6, =0x40e040e0 @ NMRR + ldr r5, =PRRR @ PRRR + ldr r6, =NMRR @ NMRR mcr p15, 0, r5, c10, c2, 0 @ write PRRR mcr p15, 0, r6, c10, c2, 1 @ write NMRR #endif @@ -357,6 +416,9 @@ ENTRY(v7_processor_functions) .word cpu_v7_dcache_clean_area .word cpu_v7_switch_mm .word cpu_v7_set_pte_ext + .word 0 + .word 0 + .word 0 .size v7_processor_functions, . - v7_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index ec26355cb7c2..63d8b2044e84 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -413,9 +413,52 @@ ENTRY(cpu_xsc3_set_pte_ext) mov pc, lr .ltorg - .align +.globl cpu_xsc3_suspend_size +.equ cpu_xsc3_suspend_size, 4 * 8 +#ifdef CONFIG_PM +ENTRY(cpu_xsc3_do_suspend) + stmfd sp!, {r4 - r10, lr} + mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode + mrc p15, 0, r5, c15, c1, 0 @ CP access reg + mrc p15, 0, r6, c13, c0, 0 @ PID + mrc p15, 0, r7, c3, c0, 0 @ domain ID + mrc p15, 0, r8, c2, c0, 0 @ translation table base addr + mrc p15, 0, r9, c1, c0, 1 @ auxiliary control reg + mrc p15, 0, r10, c1, c0, 0 @ control reg + bic r4, r4, #2 @ clear frequency change bit + stmia r0, {r1, r4 - r10} @ store v:p offset + cp regs + ldmia sp!, {r4 - r10, pc} +ENDPROC(cpu_xsc3_do_suspend) + +ENTRY(cpu_xsc3_do_resume) + ldmia r0, {r1, r4 - r10} @ load v:p offset + cp regs + mov ip, #0 + mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB + mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer + mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer + mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs + mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode. + mcr p15, 0, r5, c15, c1, 0 @ CP access reg + mcr p15, 0, r6, c13, c0, 0 @ PID + mcr p15, 0, r7, c3, c0, 0 @ domain ID + mcr p15, 0, r8, c2, c0, 0 @ translation table base addr + mcr p15, 0, r9, c1, c0, 1 @ auxiliary control reg + + @ temporarily map resume_turn_on_mmu into the page table, + @ otherwise prefetch abort occurs after MMU is turned on + mov r0, r10 @ control register + mov r2, r8, lsr #14 @ get TTB0 base + mov r2, r2, lsl #14 + ldr r3, =0x542e @ section flags + b cpu_resume_mmu +ENDPROC(cpu_xsc3_do_resume) +#else +#define cpu_xsc3_do_suspend 0 +#define cpu_xsc3_do_resume 0 +#endif + __CPUINIT .type __xsc3_setup, #function @@ -476,6 +519,9 @@ ENTRY(xsc3_processor_functions) .word cpu_xsc3_dcache_clean_area .word cpu_xsc3_switch_mm .word cpu_xsc3_set_pte_ext + .word cpu_xsc3_suspend_size + .word cpu_xsc3_do_suspend + .word cpu_xsc3_do_resume .size xsc3_processor_functions, . - xsc3_processor_functions .section ".rodata" diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 5a37c5e45c41..086038cd86ab 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -513,11 +513,49 @@ ENTRY(cpu_xscale_set_pte_ext) xscale_set_pte_ext_epilogue mov pc, lr - .ltorg - .align +.globl cpu_xscale_suspend_size +.equ cpu_xscale_suspend_size, 4 * 7 +#ifdef CONFIG_PM +ENTRY(cpu_xscale_do_suspend) + stmfd sp!, {r4 - r10, lr} + mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode + mrc p15, 0, r5, c15, c1, 0 @ CP access reg + mrc p15, 0, r6, c13, c0, 0 @ PID + mrc p15, 0, r7, c3, c0, 0 @ domain ID + mrc p15, 0, r8, c2, c0, 0 @ translation table base addr + mrc p15, 0, r9, c1, c1, 0 @ auxiliary control reg + mrc p15, 0, r10, c1, c0, 0 @ control reg + bic r4, r4, #2 @ clear frequency change bit + stmia r0, {r4 - r10} @ store cp regs + ldmfd sp!, {r4 - r10, pc} +ENDPROC(cpu_xscale_do_suspend) + +ENTRY(cpu_xscale_do_resume) + ldmia r0, {r4 - r10} @ load cp regs + mov ip, #0 + mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs + mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB + mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode. + mcr p15, 0, r5, c15, c1, 0 @ CP access reg + mcr p15, 0, r6, c13, c0, 0 @ PID + mcr p15, 0, r7, c3, c0, 0 @ domain ID + mcr p15, 0, r8, c2, c0, 0 @ translation table base addr + mcr p15, 0, r9, c1, c1, 0 @ auxiliary control reg + mov r0, r10 @ control register + mov r2, r8, lsr #14 @ get TTB0 base + mov r2, r2, lsl #14 + ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \ + PMD_SECT_CACHEABLE | PMD_SECT_AP_WRITE + b cpu_resume_mmu +ENDPROC(cpu_xscale_do_resume) +#else +#define cpu_xscale_do_suspend 0 +#define cpu_xscale_do_resume 0 +#endif + __CPUINIT .type __xscale_setup, #function @@ -565,6 +603,9 @@ ENTRY(xscale_processor_functions) .word cpu_xscale_dcache_clean_area .word cpu_xscale_switch_mm .word cpu_xscale_set_pte_ext + .word cpu_xscale_suspend_size + .word cpu_xscale_do_suspend + .word cpu_xscale_do_resume .size xscale_processor_functions, . - xscale_processor_functions .section ".rodata" diff --git a/arch/arm/mm/vmregion.c b/arch/arm/mm/vmregion.c index 935993e1b1ef..036fdbfdd62f 100644 --- a/arch/arm/mm/vmregion.c +++ b/arch/arm/mm/vmregion.c @@ -38,7 +38,7 @@ struct arm_vmregion * arm_vmregion_alloc(struct arm_vmregion_head *head, size_t align, size_t size, gfp_t gfp) { - unsigned long addr = head->vm_start, end = head->vm_end - size; + unsigned long start = head->vm_start, addr = head->vm_end; unsigned long flags; struct arm_vmregion *c, *new; @@ -54,21 +54,20 @@ arm_vmregion_alloc(struct arm_vmregion_head *head, size_t align, spin_lock_irqsave(&head->vm_lock, flags); - list_for_each_entry(c, &head->vm_list, vm_list) { - if ((addr + size) < addr) - goto nospc; - if ((addr + size) <= c->vm_start) + addr = rounddown(addr - size, align); + list_for_each_entry_reverse(c, &head->vm_list, vm_list) { + if (addr >= c->vm_end) goto found; - addr = ALIGN(c->vm_end, align); - if (addr > end) + addr = rounddown(c->vm_start - size, align); + if (addr < start) goto nospc; } found: /* - * Insert this entry _before_ the one we found. + * Insert this entry after the one we found. */ - list_add_tail(&new->vm_list, &c->vm_list); + list_add(&new->vm_list, &c->vm_list); new->vm_start = addr; new->vm_end = addr + size; new->vm_active = 1; diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index 83861408133f..5d51cbb98893 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -23,23 +23,23 @@ #if !defined(CONFIG_RUNTIME_PHYS_OFFSET) # if defined CONFIG_ARCH_MX1 -# define PHYS_OFFSET MX1_PHYS_OFFSET +# define PLAT_PHYS_OFFSET MX1_PHYS_OFFSET # elif defined CONFIG_MACH_MX21 -# define PHYS_OFFSET MX21_PHYS_OFFSET +# define PLAT_PHYS_OFFSET MX21_PHYS_OFFSET # elif defined CONFIG_ARCH_MX25 -# define PHYS_OFFSET MX25_PHYS_OFFSET +# define PLAT_PHYS_OFFSET MX25_PHYS_OFFSET # elif defined CONFIG_MACH_MX27 -# define PHYS_OFFSET MX27_PHYS_OFFSET +# define PLAT_PHYS_OFFSET MX27_PHYS_OFFSET # elif defined CONFIG_ARCH_MX3 -# define PHYS_OFFSET MX3x_PHYS_OFFSET +# define PLAT_PHYS_OFFSET MX3x_PHYS_OFFSET # elif defined CONFIG_ARCH_MXC91231 -# define PHYS_OFFSET MXC91231_PHYS_OFFSET +# define PLAT_PHYS_OFFSET MXC91231_PHYS_OFFSET # elif defined CONFIG_ARCH_MX50 -# define PHYS_OFFSET MX50_PHYS_OFFSET +# define PLAT_PHYS_OFFSET MX50_PHYS_OFFSET # elif defined CONFIG_ARCH_MX51 -# define PHYS_OFFSET MX51_PHYS_OFFSET +# define PLAT_PHYS_OFFSET MX51_PHYS_OFFSET # elif defined CONFIG_ARCH_MX53 -# define PHYS_OFFSET MX53_PHYS_OFFSET +# define PLAT_PHYS_OFFSET MX53_PHYS_OFFSET # endif #endif diff --git a/arch/arm/plat-omap/include/plat/memory.h b/arch/arm/plat-omap/include/plat/memory.h index f8d922fb5584..e6720aa2d553 100644 --- a/arch/arm/plat-omap/include/plat/memory.h +++ b/arch/arm/plat-omap/include/plat/memory.h @@ -37,9 +37,9 @@ * Physical DRAM offset. */ #if defined(CONFIG_ARCH_OMAP1) -#define PHYS_OFFSET UL(0x10000000) +#define PLAT_PHYS_OFFSET UL(0x10000000) #else -#define PHYS_OFFSET UL(0x80000000) +#define PLAT_PHYS_OFFSET UL(0x80000000) #endif /* diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h index cec5d56db2eb..8ff605c83aca 100644 --- a/arch/arm/plat-omap/include/plat/serial.h +++ b/arch/arm/plat-omap/include/plat/serial.h @@ -27,7 +27,7 @@ * 2. We assume printascii is called at least once before paging_init, * and addruart has a chance to read OMAP_UART_INFO */ -#define OMAP_UART_INFO (PHYS_OFFSET + 0x3ffc) +#define OMAP_UART_INFO (PLAT_PHYS_OFFSET + 0x3ffc) /* OMAP1 serial ports */ #define OMAP1_UART1_BASE 0xfffb0000 diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h index 9967d5e855c7..f500fc34d065 100644 --- a/arch/arm/plat-omap/include/plat/sram.h +++ b/arch/arm/plat-omap/include/plat/sram.h @@ -12,7 +12,19 @@ #define __ARCH_ARM_OMAP_SRAM_H #ifndef __ASSEMBLY__ -extern void * omap_sram_push(void * start, unsigned long size); +#include <asm/fncpy.h> + +extern void *omap_sram_push_address(unsigned long size); + +/* Macro to push a function to the internal SRAM, using the fncpy API */ +#define omap_sram_push(funcp, size) ({ \ + typeof(&(funcp)) _res = NULL; \ + void *_sram_address = omap_sram_push_address(size); \ + if (_sram_address) \ + _res = fncpy(_sram_address, &(funcp), size); \ + _res; \ +}) + extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index 450a332f1009..fe449f1a1c14 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h @@ -7,15 +7,12 @@ #include <plat/board.h> #define OMAP3_HS_USB_PORTS 3 -enum ehci_hcd_omap_mode { - EHCI_HCD_OMAP_MODE_UNKNOWN, - EHCI_HCD_OMAP_MODE_PHY, - EHCI_HCD_OMAP_MODE_TLL, - EHCI_HCD_OMAP_MODE_HSIC, -}; -enum ohci_omap3_port_mode { - OMAP_OHCI_PORT_MODE_UNUSED, +enum usbhs_omap_port_mode { + OMAP_USBHS_PORT_MODE_UNUSED, + OMAP_EHCI_PORT_MODE_PHY, + OMAP_EHCI_PORT_MODE_TLL, + OMAP_EHCI_PORT_MODE_HSIC, OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0, OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM, OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0, @@ -25,24 +22,45 @@ enum ohci_omap3_port_mode { OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0, OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM, OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0, - OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM, + OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM }; -struct ehci_hcd_omap_platform_data { - enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS]; - unsigned phy_reset:1; +struct usbhs_omap_board_data { + enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; /* have to be valid if phy_reset is true and portx is in phy mode */ int reset_gpio_port[OMAP3_HS_USB_PORTS]; + + /* Set this to true for ES2.x silicon */ + unsigned es2_compatibility:1; + + unsigned phy_reset:1; + + /* + * Regulators for USB PHYs. + * Each PHY can have a separate regulator. + */ + struct regulator *regulator[OMAP3_HS_USB_PORTS]; }; -struct ohci_hcd_omap_platform_data { - enum ohci_omap3_port_mode port_mode[OMAP3_HS_USB_PORTS]; +struct ehci_hcd_omap_platform_data { + enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; + int reset_gpio_port[OMAP3_HS_USB_PORTS]; + struct regulator *regulator[OMAP3_HS_USB_PORTS]; + unsigned phy_reset:1; +}; - /* Set this to true for ES2.x silicon */ +struct ohci_hcd_omap_platform_data { + enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; unsigned es2_compatibility:1; }; +struct usbhs_omap_platform_data { + enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; + + struct ehci_hcd_omap_platform_data *ehci_data; + struct ohci_hcd_omap_platform_data *ohci_data; +}; /*-------------------------------------------------------------------------*/ #define OMAP1_OTG_BASE 0xfffb0400 @@ -80,18 +98,18 @@ enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI}; extern void usb_musb_init(struct omap_musb_board_data *board_data); -extern void usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata); +extern void usbhs_init(const struct usbhs_omap_board_data *pdata); -extern void usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata); +extern int omap_usbhs_enable(struct device *dev); +extern void omap_usbhs_disable(struct device *dev); extern int omap4430_phy_power(struct device *dev, int ID, int on); extern int omap4430_phy_set_clk(struct device *dev, int on); extern int omap4430_phy_init(struct device *dev); extern int omap4430_phy_exit(struct device *dev); - +extern int omap4430_phy_suspend(struct device *dev, int suspend); #endif - /* * FIXME correct answer depends on hmc_mode, * as does (on omap1) any nonzero value for config->otg port number diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c index 49d3208793e5..69ddc9f76c13 100644 --- a/arch/arm/plat-omap/mailbox.c +++ b/arch/arm/plat-omap/mailbox.c @@ -32,7 +32,6 @@ #include <plat/mailbox.h> -static struct workqueue_struct *mboxd; static struct omap_mbox **mboxes; static int mbox_configured; @@ -197,7 +196,7 @@ static void __mbox_rx_interrupt(struct omap_mbox *mbox) /* no more messages in the fifo. clear IRQ source. */ ack_mbox_irq(mbox, IRQ_RX); nomem: - queue_work(mboxd, &mbox->rxq->work); + schedule_work(&mbox->rxq->work); } static irqreturn_t mbox_interrupt(int irq, void *p) @@ -307,7 +306,7 @@ static void omap_mbox_fini(struct omap_mbox *mbox) if (!--mbox->use_count) { free_irq(mbox->irq, mbox); tasklet_kill(&mbox->txq->tasklet); - flush_work(&mbox->rxq->work); + flush_work_sync(&mbox->rxq->work); mbox_queue_free(mbox->txq); mbox_queue_free(mbox->rxq); } @@ -409,10 +408,6 @@ static int __init omap_mbox_init(void) if (err) return err; - mboxd = create_workqueue("mboxd"); - if (!mboxd) - return -ENOMEM; - /* kfifo size sanity check: alignment and minimal size */ mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t)); mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size, @@ -424,7 +419,6 @@ subsys_initcall(omap_mbox_init); static void __exit omap_mbox_exit(void) { - destroy_workqueue(mboxd); class_unregister(&omap_mbox_class); } module_exit(omap_mbox_exit); diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index e26e50487d60..68fcc7dc56e7 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -242,7 +242,14 @@ static void __init omap_map_sram(void) omap_sram_size - SRAM_BOOTLOADER_SZ); } -void * omap_sram_push(void * start, unsigned long size) +/* + * Memory allocator for SRAM: calculates the new ceiling address + * for pushing a function using the fncpy API. + * + * Note that fncpy requires the returned address to be aligned + * to an 8-byte boundary. + */ +void *omap_sram_push_address(unsigned long size) { if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) { printk(KERN_ERR "Not enough space in SRAM\n"); @@ -250,10 +257,7 @@ void * omap_sram_push(void * start, unsigned long size) } omap_sram_ceil -= size; - omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *)); - memcpy((void *)omap_sram_ceil, start, size); - flush_icache_range((unsigned long)omap_sram_ceil, - (unsigned long)(omap_sram_ceil + size)); + omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, FNCPY_ALIGN); return (void *)omap_sram_ceil; } diff --git a/arch/arm/plat-s3c24xx/cpu-freq.c b/arch/arm/plat-s3c24xx/cpu-freq.c index 25a8fc7f512e..eea75ff81d15 100644 --- a/arch/arm/plat-s3c24xx/cpu-freq.c +++ b/arch/arm/plat-s3c24xx/cpu-freq.c @@ -433,7 +433,7 @@ static int s3c_cpufreq_verify(struct cpufreq_policy *policy) static struct cpufreq_frequency_table suspend_pll; static unsigned int suspend_freq; -static int s3c_cpufreq_suspend(struct cpufreq_policy *policy, pm_message_t pmsg) +static int s3c_cpufreq_suspend(struct cpufreq_policy *policy) { suspend_pll.frequency = clk_get_rate(_clk_mpll); suspend_pll.index = __raw_readl(S3C2410_MPLLCON); diff --git a/arch/arm/plat-s3c24xx/include/plat/udc.h b/arch/arm/plat-s3c24xx/include/plat/udc.h index 546bb4008f49..80457c6414aa 100644 --- a/arch/arm/plat-s3c24xx/include/plat/udc.h +++ b/arch/arm/plat-s3c24xx/include/plat/udc.h @@ -27,6 +27,10 @@ enum s3c2410_udc_cmd_e { struct s3c2410_udc_mach_info { void (*udc_command)(enum s3c2410_udc_cmd_e); void (*vbus_draw)(unsigned int ma); + + unsigned int pullup_pin; + unsigned int pullup_pin_inverted; + unsigned int vbus_pin; unsigned char vbus_pin_inverted; }; diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S index e73e3b6e88d2..fd7032f84ae7 100644 --- a/arch/arm/plat-s3c24xx/sleep.S +++ b/arch/arm/plat-s3c24xx/sleep.S @@ -44,23 +44,13 @@ /* s3c_cpu_save * * entry: - * r0 = save address (virtual addr of s3c_sleep_save_phys) + * r1 = v:p offset */ ENTRY(s3c_cpu_save) stmfd sp!, { r4 - r12, lr } - - @@ store co-processor registers - - mrc p15, 0, r4, c13, c0, 0 @ PID - mrc p15, 0, r5, c3, c0, 0 @ Domain ID - mrc p15, 0, r6, c2, c0, 0 @ translation table base address - mrc p15, 0, r7, c1, c0, 0 @ control register - - stmia r0, { r4 - r13 } - - @@ write our state back to RAM - bl s3c_pm_cb_flushcache + ldr r3, =resume_with_mmu + bl cpu_suspend @@ jump to final code to send system to sleep ldr r0, =pm_cpu_sleep @@ -76,20 +66,6 @@ resume_with_mmu: .ltorg - @@ the next bits sit in the .data segment, even though they - @@ happen to be code... the s3c_sleep_save_phys needs to be - @@ accessed by the resume code before it can restore the MMU. - @@ This means that the variable has to be close enough for the - @@ code to read it... since the .text segment needs to be RO, - @@ the data segment can be the only place to put this code. - - .data - - .global s3c_sleep_save_phys -s3c_sleep_save_phys: - .word 0 - - /* sleep magic, to allow the bootloader to check for an valid * image to resume to. Must be the first word before the * s3c_cpu_resume entry. @@ -100,10 +76,6 @@ s3c_sleep_save_phys: /* s3c_cpu_resume * * resume code entry for bootloader to call - * - * we must put this code here in the data segment as we have no - * other way of restoring the stack pointer after sleep, and we - * must not write to the code segment (code is read-only) */ ENTRY(s3c_cpu_resume) @@ -134,25 +106,4 @@ ENTRY(s3c_cpu_resume) beq 1001b #endif /* CONFIG_DEBUG_RESUME */ - mov r1, #0 - mcr p15, 0, r1, c8, c7, 0 @@ invalidate I & D TLBs - mcr p15, 0, r1, c7, c7, 0 @@ invalidate I & D caches - - ldr r0, s3c_sleep_save_phys @ address of restore block - ldmia r0, { r4 - r13 } - - mcr p15, 0, r4, c13, c0, 0 @ PID - mcr p15, 0, r5, c3, c0, 0 @ Domain ID - mcr p15, 0, r6, c2, c0, 0 @ translation table base - -#ifdef CONFIG_DEBUG_RESUME - mov r3, #'R' - strb r3, [ r2, #S3C2410_UTXH ] -#endif - - ldr r2, =resume_with_mmu - mcr p15, 0, r7, c1, c0, 0 @ turn on MMU, etc - nop @ second-to-last before mmu - mov pc, r2 @ go back to virtual address - - .ltorg + b cpu_resume diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index 30518cc9a67c..937cc2ace517 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h @@ -52,13 +52,11 @@ extern unsigned char pm_uart_udivslot; /* true to save UART UDIVSLOT */ /* from sleep.S */ -extern int s3c_cpu_save(unsigned long *saveblk); +extern int s3c_cpu_save(unsigned long *saveblk, long); extern void s3c_cpu_resume(void); extern void s3c2410_cpu_suspend(void); -extern unsigned long s3c_sleep_save_phys; - /* sleep save info */ /** @@ -181,13 +179,5 @@ extern void s3c_pm_restore_gpios(void); */ extern void s3c_pm_save_gpios(void); -/** - * s3c_pm_cb_flushcache - callback for assembly code - * - * Callback to issue flush_cache_all() as this call is - * not a directly callable object. - */ -extern void s3c_pm_cb_flushcache(void); - extern void s3c_pm_save_core(void); extern void s3c_pm_restore_core(void); diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index 02d531fb3f81..d5b58d31903c 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c @@ -241,8 +241,6 @@ void (*pm_cpu_sleep)(void); static int s3c_pm_enter(suspend_state_t state) { - static unsigned long regs_save[16]; - /* ensure the debug is initialised (if enabled) */ s3c_pm_debug_init(); @@ -266,12 +264,6 @@ static int s3c_pm_enter(suspend_state_t state) return -EINVAL; } - /* store the physical address of the register recovery block */ - - s3c_sleep_save_phys = virt_to_phys(regs_save); - - S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys); - /* save all necessary core registers not covered by the drivers */ s3c_pm_save_gpios(); @@ -305,7 +297,7 @@ static int s3c_pm_enter(suspend_state_t state) * we resume as it saves its own register state and restores it * during the resume. */ - s3c_cpu_save(regs_save); + s3c_cpu_save(0, PLAT_PHYS_OFFSET - PAGE_OFFSET); /* restore the cpu state using the kernel's cpu init code. */ @@ -336,12 +328,6 @@ static int s3c_pm_enter(suspend_state_t state) return 0; } -/* callback from assembly code */ -void s3c_pm_cb_flushcache(void) -{ - flush_cache_all(); -} - static int s3c_pm_prepare(void) { /* prepare check area if configured */ diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile index eb89540aeda9..b4f340b8f1f1 100644 --- a/arch/arm/plat-spear/Makefile +++ b/arch/arm/plat-spear/Makefile @@ -3,6 +3,6 @@ # # Common support -obj-y := clock.o padmux.o time.o +obj-y := clock.o time.o -obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o +obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c index ee4f90e534d8..bdbd7ec9cb6b 100644 --- a/arch/arm/plat-spear/clock.c +++ b/arch/arm/plat-spear/clock.c @@ -12,18 +12,25 @@ */ #include <linux/bug.h> +#include <linux/clk.h> +#include <linux/debugfs.h> #include <linux/err.h> #include <linux/io.h> #include <linux/list.h> #include <linux/module.h> #include <linux/spinlock.h> -#include <mach/misc_regs.h> #include <plat/clock.h> static DEFINE_SPINLOCK(clocks_lock); static LIST_HEAD(root_clks); +#ifdef CONFIG_DEBUG_FS +static LIST_HEAD(clocks); +#endif -static void propagate_rate(struct list_head *); +static void propagate_rate(struct clk *, int on_init); +#ifdef CONFIG_DEBUG_FS +static int clk_debugfs_reparent(struct clk *); +#endif static int generic_clk_enable(struct clk *clk) { @@ -65,6 +72,104 @@ static struct clkops generic_clkops = { .disable = generic_clk_disable, }; +/* returns current programmed clocks clock info structure */ +static struct pclk_info *pclk_info_get(struct clk *clk) +{ + unsigned int val, i; + struct pclk_info *info = NULL; + + val = (readl(clk->pclk_sel->pclk_sel_reg) >> clk->pclk_sel_shift) + & clk->pclk_sel->pclk_sel_mask; + + for (i = 0; i < clk->pclk_sel->pclk_count; i++) { + if (clk->pclk_sel->pclk_info[i].pclk_val == val) + info = &clk->pclk_sel->pclk_info[i]; + } + + return info; +} + +/* + * Set Update pclk, and pclk_info of clk and add clock sibling node to current + * parents children list + */ +static void clk_reparent(struct clk *clk, struct pclk_info *pclk_info) +{ + unsigned long flags; + + spin_lock_irqsave(&clocks_lock, flags); + list_del(&clk->sibling); + list_add(&clk->sibling, &pclk_info->pclk->children); + + clk->pclk = pclk_info->pclk; + spin_unlock_irqrestore(&clocks_lock, flags); + +#ifdef CONFIG_DEBUG_FS + clk_debugfs_reparent(clk); +#endif +} + +static void do_clk_disable(struct clk *clk) +{ + if (!clk) + return; + + if (!clk->usage_count) { + WARN_ON(1); + return; + } + + clk->usage_count--; + + if (clk->usage_count == 0) { + /* + * Surely, there are no active childrens or direct users + * of this clock + */ + if (clk->pclk) + do_clk_disable(clk->pclk); + + if (clk->ops && clk->ops->disable) + clk->ops->disable(clk); + } +} + +static int do_clk_enable(struct clk *clk) +{ + int ret = 0; + + if (!clk) + return -EFAULT; + + if (clk->usage_count == 0) { + if (clk->pclk) { + ret = do_clk_enable(clk->pclk); + if (ret) + goto err; + } + if (clk->ops && clk->ops->enable) { + ret = clk->ops->enable(clk); + if (ret) { + if (clk->pclk) + do_clk_disable(clk->pclk); + goto err; + } + } + /* + * Since the clock is going to be used for the first + * time please reclac + */ + if (clk->recalc) { + ret = clk->recalc(clk); + if (ret) + goto err; + } + } + clk->usage_count++; +err: + return ret; +} + /* * clk_enable - inform the system when the clock source should be running. * @clk: clock source @@ -78,17 +183,9 @@ int clk_enable(struct clk *clk) unsigned long flags; int ret = 0; - if (!clk || IS_ERR(clk)) - return -EFAULT; - spin_lock_irqsave(&clocks_lock, flags); - if (clk->usage_count == 0) { - if (clk->ops && clk->ops->enable) - ret = clk->ops->enable(clk); - } - clk->usage_count++; + ret = do_clk_enable(clk); spin_unlock_irqrestore(&clocks_lock, flags); - return ret; } EXPORT_SYMBOL(clk_enable); @@ -109,17 +206,8 @@ void clk_disable(struct clk *clk) { unsigned long flags; - if (!clk || IS_ERR(clk)) - return; - - WARN_ON(clk->usage_count == 0); - spin_lock_irqsave(&clocks_lock, flags); - clk->usage_count--; - if (clk->usage_count == 0) { - if (clk->ops && clk->ops->disable) - clk->ops->disable(clk); - } + do_clk_disable(clk); spin_unlock_irqrestore(&clocks_lock, flags); } EXPORT_SYMBOL(clk_disable); @@ -153,15 +241,14 @@ int clk_set_parent(struct clk *clk, struct clk *parent) int i, found = 0, val = 0; unsigned long flags; - if (!clk || IS_ERR(clk) || !parent || IS_ERR(parent)) + if (!clk || !parent) return -EFAULT; - if (clk->usage_count) - return -EBUSY; - if (!clk->pclk_sel) - return -EPERM; if (clk->pclk == parent) return 0; + if (!clk->pclk_sel) + return -EPERM; + /* check if requested parent is in clk parent list */ for (i = 0; i < clk->pclk_sel->pclk_count; i++) { if (clk->pclk_sel->pclk_info[i].pclk == parent) { found = 1; @@ -176,25 +263,58 @@ int clk_set_parent(struct clk *clk, struct clk *parent) /* reflect parent change in hardware */ val = readl(clk->pclk_sel->pclk_sel_reg); val &= ~(clk->pclk_sel->pclk_sel_mask << clk->pclk_sel_shift); - val |= clk->pclk_sel->pclk_info[i].pclk_mask << clk->pclk_sel_shift; + val |= clk->pclk_sel->pclk_info[i].pclk_val << clk->pclk_sel_shift; writel(val, clk->pclk_sel->pclk_sel_reg); spin_unlock_irqrestore(&clocks_lock, flags); /* reflect parent change in software */ - clk->recalc(clk); - propagate_rate(&clk->children); + clk_reparent(clk, &clk->pclk_sel->pclk_info[i]); + + propagate_rate(clk, 0); return 0; } EXPORT_SYMBOL(clk_set_parent); +/** + * clk_set_rate - set the clock rate for a clock source + * @clk: clock source + * @rate: desired clock rate in Hz + * + * Returns success (0) or negative errno. + */ +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long flags; + int ret = -EINVAL; + + if (!clk || !rate) + return -EFAULT; + + if (clk->set_rate) { + spin_lock_irqsave(&clocks_lock, flags); + ret = clk->set_rate(clk, rate); + if (!ret) + /* if successful -> propagate */ + propagate_rate(clk, 0); + spin_unlock_irqrestore(&clocks_lock, flags); + } else if (clk->pclk) { + u32 mult = clk->div_factor ? clk->div_factor : 1; + ret = clk_set_rate(clk->pclk, mult * rate); + } + + return ret; +} +EXPORT_SYMBOL(clk_set_rate); + /* registers clock in platform clock framework */ void clk_register(struct clk_lookup *cl) { - struct clk *clk = cl->clk; + struct clk *clk; unsigned long flags; - if (!clk || IS_ERR(clk)) + if (!cl || !cl->clk) return; + clk = cl->clk; spin_lock_irqsave(&clocks_lock, flags); @@ -207,71 +327,173 @@ void clk_register(struct clk_lookup *cl) /* root clock don't have any parents */ if (!clk->pclk && !clk->pclk_sel) { list_add(&clk->sibling, &root_clks); - /* add clocks with only one parent to parent's children list */ } else if (clk->pclk && !clk->pclk_sel) { + /* add clocks with only one parent to parent's children list */ list_add(&clk->sibling, &clk->pclk->children); } else { - /* add clocks with > 1 parent to 1st parent's children list */ - list_add(&clk->sibling, - &clk->pclk_sel->pclk_info[0].pclk->children); + /* clocks with more than one parent */ + struct pclk_info *pclk_info; + + pclk_info = pclk_info_get(clk); + if (!pclk_info) { + pr_err("CLKDEV: invalid pclk info of clk with" + " %s dev_id and %s con_id\n", + cl->dev_id, cl->con_id); + } else { + clk->pclk = pclk_info->pclk; + list_add(&clk->sibling, &pclk_info->pclk->children); + } } + spin_unlock_irqrestore(&clocks_lock, flags); + /* debugfs specific */ +#ifdef CONFIG_DEBUG_FS + list_add(&clk->node, &clocks); + clk->cl = cl; +#endif + /* add clock to arm clockdev framework */ clkdev_add(cl); } /** - * propagate_rate - recalculate and propagate all clocks in list head + * propagate_rate - recalculate and propagate all clocks to children + * @pclk: parent clock required to be propogated + * @on_init: flag for enabling clocks which are ENABLED_ON_INIT. * - * Recalculates all root clocks in list head, which if the clock's .recalc is - * set correctly, should also propagate their rates. + * Recalculates all children clocks */ -static void propagate_rate(struct list_head *lhead) +void propagate_rate(struct clk *pclk, int on_init) { - struct clk *clkp, *_temp; + struct clk *clk, *_temp; + int ret = 0; - list_for_each_entry_safe(clkp, _temp, lhead, sibling) { - if (clkp->recalc) - clkp->recalc(clkp); - propagate_rate(&clkp->children); + list_for_each_entry_safe(clk, _temp, &pclk->children, sibling) { + if (clk->recalc) { + ret = clk->recalc(clk); + /* + * recalc will return error if clk out is not programmed + * In this case configure default rate. + */ + if (ret && clk->set_rate) + clk->set_rate(clk, 0); + } + propagate_rate(clk, on_init); + + if (!on_init) + continue; + + /* Enable clks enabled on init, in software view */ + if (clk->flags & ENABLED_ON_INIT) + do_clk_enable(clk); } } -/* returns current programmed clocks clock info structure */ -static struct pclk_info *pclk_info_get(struct clk *clk) +/** + * round_rate_index - return closest programmable rate index in rate_config tbl + * @clk: ptr to clock structure + * @drate: desired rate + * @rate: final rate will be returned in this variable only. + * + * Finds index in rate_config for highest clk rate which is less than + * requested rate. If there is no clk rate lesser than requested rate then + * -EINVAL is returned. This routine assumes that rate_config is written + * in incrementing order of clk rates. + * If drate passed is zero then default rate is programmed. + */ +static int +round_rate_index(struct clk *clk, unsigned long drate, unsigned long *rate) { - unsigned int mask, i; - unsigned long flags; - struct pclk_info *info = NULL; + unsigned long tmp = 0, prev_rate = 0; + int index; - spin_lock_irqsave(&clocks_lock, flags); - mask = (readl(clk->pclk_sel->pclk_sel_reg) >> clk->pclk_sel_shift) - & clk->pclk_sel->pclk_sel_mask; + if (!clk->calc_rate) + return -EFAULT; - for (i = 0; i < clk->pclk_sel->pclk_count; i++) { - if (clk->pclk_sel->pclk_info[i].pclk_mask == mask) - info = &clk->pclk_sel->pclk_info[i]; + if (!drate) + return -EINVAL; + + /* + * This loops ends on two conditions: + * - as soon as clk is found with rate greater than requested rate. + * - if all clks in rate_config are smaller than requested rate. + */ + for (index = 0; index < clk->rate_config.count; index++) { + prev_rate = tmp; + tmp = clk->calc_rate(clk, index); + if (drate < tmp) { + index--; + break; + } } - spin_unlock_irqrestore(&clocks_lock, flags); + /* return if can't find suitable clock */ + if (index < 0) { + index = -EINVAL; + *rate = 0; + } else if (index == clk->rate_config.count) { + /* program with highest clk rate possible */ + index = clk->rate_config.count - 1; + *rate = tmp; + } else + *rate = prev_rate; - return info; + return index; } -/* - * Set pclk as cclk's parent and add clock sibling node to current parents - * children list +/** + * clk_round_rate - adjust a rate to the exact rate a clock can provide + * @clk: clock source + * @rate: desired clock rate in Hz + * + * Returns rounded clock rate in Hz, or negative errno. */ -static void change_parent(struct clk *cclk, struct clk *pclk) +long clk_round_rate(struct clk *clk, unsigned long drate) { - unsigned long flags; + long rate = 0; + int index; + + /* + * propagate call to parent who supports calc_rate. Similar approach is + * used in clk_set_rate. + */ + if (!clk->calc_rate) { + u32 mult; + if (!clk->pclk) + return clk->rate; + + mult = clk->div_factor ? clk->div_factor : 1; + return clk_round_rate(clk->pclk, mult * drate) / mult; + } - spin_lock_irqsave(&clocks_lock, flags); - list_del(&cclk->sibling); - list_add(&cclk->sibling, &pclk->children); + index = round_rate_index(clk, drate, &rate); + if (index >= 0) + return rate; + else + return index; +} +EXPORT_SYMBOL(clk_round_rate); - cclk->pclk = pclk; - spin_unlock_irqrestore(&clocks_lock, flags); +/*All below functions are called with lock held */ + +/* + * Calculates pll clk rate for specific value of mode, m, n and p + * + * In normal mode + * rate = (2 * M[15:8] * Fin)/(N * 2^P) + * + * In Dithered mode + * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P) + */ +unsigned long pll_calc_rate(struct clk *clk, int index) +{ + unsigned long rate = clk->pclk->rate; + struct pll_rate_tbl *tbls = clk->rate_config.tbls; + unsigned int mode; + + mode = tbls[index].mode ? 256 : 1; + return (((2 * rate / 10000) * tbls[index].m) / + (mode * tbls[index].n * (1 << tbls[index].p))) * 10000; } /* @@ -283,47 +505,146 @@ static void change_parent(struct clk *cclk, struct clk *pclk) * In Dithered mode * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P) */ -void pll1_clk_recalc(struct clk *clk) +int pll_clk_recalc(struct clk *clk) { struct pll_clk_config *config = clk->private_data; unsigned int num = 2, den = 0, val, mode = 0; - unsigned long flags; - spin_lock_irqsave(&clocks_lock, flags); - mode = (readl(config->mode_reg) >> PLL_MODE_SHIFT) & - PLL_MODE_MASK; + mode = (readl(config->mode_reg) >> config->masks->mode_shift) & + config->masks->mode_mask; val = readl(config->cfg_reg); /* calculate denominator */ - den = (val >> PLL_DIV_P_SHIFT) & PLL_DIV_P_MASK; + den = (val >> config->masks->div_p_shift) & config->masks->div_p_mask; den = 1 << den; - den *= (val >> PLL_DIV_N_SHIFT) & PLL_DIV_N_MASK; + den *= (val >> config->masks->div_n_shift) & config->masks->div_n_mask; /* calculate numerator & denominator */ if (!mode) { /* Normal mode */ - num *= (val >> PLL_NORM_FDBK_M_SHIFT) & PLL_NORM_FDBK_M_MASK; + num *= (val >> config->masks->norm_fdbk_m_shift) & + config->masks->norm_fdbk_m_mask; } else { /* Dithered mode */ - num *= (val >> PLL_DITH_FDBK_M_SHIFT) & PLL_DITH_FDBK_M_MASK; + num *= (val >> config->masks->dith_fdbk_m_shift) & + config->masks->dith_fdbk_m_mask; den *= 256; } + if (!den) + return -EINVAL; + clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000; - spin_unlock_irqrestore(&clocks_lock, flags); + return 0; +} + +/* + * Configures new clock rate of pll + */ +int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate) +{ + struct pll_rate_tbl *tbls = clk->rate_config.tbls; + struct pll_clk_config *config = clk->private_data; + unsigned long val, rate; + int i; + + i = round_rate_index(clk, desired_rate, &rate); + if (i < 0) + return i; + + val = readl(config->mode_reg) & + ~(config->masks->mode_mask << config->masks->mode_shift); + val |= (tbls[i].mode & config->masks->mode_mask) << + config->masks->mode_shift; + writel(val, config->mode_reg); + + val = readl(config->cfg_reg) & + ~(config->masks->div_p_mask << config->masks->div_p_shift); + val |= (tbls[i].p & config->masks->div_p_mask) << + config->masks->div_p_shift; + val &= ~(config->masks->div_n_mask << config->masks->div_n_shift); + val |= (tbls[i].n & config->masks->div_n_mask) << + config->masks->div_n_shift; + val &= ~(config->masks->dith_fdbk_m_mask << + config->masks->dith_fdbk_m_shift); + if (tbls[i].mode) + val |= (tbls[i].m & config->masks->dith_fdbk_m_mask) << + config->masks->dith_fdbk_m_shift; + else + val |= (tbls[i].m & config->masks->norm_fdbk_m_mask) << + config->masks->norm_fdbk_m_shift; + + writel(val, config->cfg_reg); + + clk->rate = rate; + + return 0; +} + +/* + * Calculates ahb, apb clk rate for specific value of div + */ +unsigned long bus_calc_rate(struct clk *clk, int index) +{ + unsigned long rate = clk->pclk->rate; + struct bus_rate_tbl *tbls = clk->rate_config.tbls; + + return rate / (tbls[index].div + 1); } /* calculates current programmed rate of ahb or apb bus */ -void bus_clk_recalc(struct clk *clk) +int bus_clk_recalc(struct clk *clk) { struct bus_clk_config *config = clk->private_data; unsigned int div; - unsigned long flags; - spin_lock_irqsave(&clocks_lock, flags); - div = ((readl(config->reg) >> config->shift) & config->mask) + 1; + div = ((readl(config->reg) >> config->masks->shift) & + config->masks->mask) + 1; + + if (!div) + return -EINVAL; + clk->rate = (unsigned long)clk->pclk->rate / div; - spin_unlock_irqrestore(&clocks_lock, flags); + return 0; +} + +/* Configures new clock rate of AHB OR APB bus */ +int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate) +{ + struct bus_rate_tbl *tbls = clk->rate_config.tbls; + struct bus_clk_config *config = clk->private_data; + unsigned long val, rate; + int i; + + i = round_rate_index(clk, desired_rate, &rate); + if (i < 0) + return i; + + val = readl(config->reg) & + ~(config->masks->mask << config->masks->shift); + val |= (tbls[i].div & config->masks->mask) << config->masks->shift; + writel(val, config->reg); + + clk->rate = rate; + + return 0; +} + +/* + * gives rate for different values of eq, x and y + * + * Fout from synthesizer can be given from two equations: + * Fout1 = (Fin * X/Y)/2 EQ1 + * Fout2 = Fin * X/Y EQ2 + */ +unsigned long aux_calc_rate(struct clk *clk, int index) +{ + unsigned long rate = clk->pclk->rate; + struct aux_rate_tbl *tbls = clk->rate_config.tbls; + u8 eq = tbls[index].eq ? 1 : 2; + + return (((rate/10000) * tbls[index].xscale) / + (tbls[index].yscale * eq)) * 10000; } /* @@ -336,44 +657,76 @@ void bus_clk_recalc(struct clk *clk) * * Selection of eqn 1 or 2 is programmed in register */ -void aux_clk_recalc(struct clk *clk) +int aux_clk_recalc(struct clk *clk) { struct aux_clk_config *config = clk->private_data; - struct pclk_info *pclk_info = NULL; unsigned int num = 1, den = 1, val, eqn; - unsigned long flags; - /* get current programmed parent */ - pclk_info = pclk_info_get(clk); - if (!pclk_info) { - spin_lock_irqsave(&clocks_lock, flags); - clk->pclk = NULL; - clk->rate = 0; - spin_unlock_irqrestore(&clocks_lock, flags); - return; - } + val = readl(config->synth_reg); - change_parent(clk, pclk_info->pclk); + eqn = (val >> config->masks->eq_sel_shift) & + config->masks->eq_sel_mask; + if (eqn == config->masks->eq1_mask) + den *= 2; - spin_lock_irqsave(&clocks_lock, flags); - if (pclk_info->scalable) { - val = readl(config->synth_reg); + /* calculate numerator */ + num = (val >> config->masks->xscale_sel_shift) & + config->masks->xscale_sel_mask; - eqn = (val >> AUX_EQ_SEL_SHIFT) & AUX_EQ_SEL_MASK; - if (eqn == AUX_EQ1_SEL) - den *= 2; + /* calculate denominator */ + den *= (val >> config->masks->yscale_sel_shift) & + config->masks->yscale_sel_mask; - /* calculate numerator */ - num = (val >> AUX_XSCALE_SHIFT) & AUX_XSCALE_MASK; + if (!den) + return -EINVAL; - /* calculate denominator */ - den *= (val >> AUX_YSCALE_SHIFT) & AUX_YSCALE_MASK; - val = (((clk->pclk->rate/10000) * num) / den) * 10000; - } else - val = clk->pclk->rate; + clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000; + return 0; +} - clk->rate = val; - spin_unlock_irqrestore(&clocks_lock, flags); +/* Configures new clock rate of auxiliary synthesizers used by: UART, FIRDA*/ +int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate) +{ + struct aux_rate_tbl *tbls = clk->rate_config.tbls; + struct aux_clk_config *config = clk->private_data; + unsigned long val, rate; + int i; + + i = round_rate_index(clk, desired_rate, &rate); + if (i < 0) + return i; + + val = readl(config->synth_reg) & + ~(config->masks->eq_sel_mask << config->masks->eq_sel_shift); + val |= (tbls[i].eq & config->masks->eq_sel_mask) << + config->masks->eq_sel_shift; + val &= ~(config->masks->xscale_sel_mask << + config->masks->xscale_sel_shift); + val |= (tbls[i].xscale & config->masks->xscale_sel_mask) << + config->masks->xscale_sel_shift; + val &= ~(config->masks->yscale_sel_mask << + config->masks->yscale_sel_shift); + val |= (tbls[i].yscale & config->masks->yscale_sel_mask) << + config->masks->yscale_sel_shift; + writel(val, config->synth_reg); + + clk->rate = rate; + + return 0; +} + +/* + * Calculates gpt clk rate for different values of mscale and nscale + * + * Fout= Fin/((2 ^ (N+1)) * (M+1)) + */ +unsigned long gpt_calc_rate(struct clk *clk, int index) +{ + unsigned long rate = clk->pclk->rate; + struct gpt_rate_tbl *tbls = clk->rate_config.tbls; + + return rate / ((1 << (tbls[index].nscale + 1)) * + (tbls[index].mscale + 1)); } /* @@ -381,46 +734,142 @@ void aux_clk_recalc(struct clk *clk) * Fout from synthesizer can be given from below equations: * Fout= Fin/((2 ^ (N+1)) * (M+1)) */ -void gpt_clk_recalc(struct clk *clk) +int gpt_clk_recalc(struct clk *clk) { - struct aux_clk_config *config = clk->private_data; - struct pclk_info *pclk_info = NULL; + struct gpt_clk_config *config = clk->private_data; unsigned int div = 1, val; - unsigned long flags; - pclk_info = pclk_info_get(clk); - if (!pclk_info) { - spin_lock_irqsave(&clocks_lock, flags); - clk->pclk = NULL; - clk->rate = 0; - spin_unlock_irqrestore(&clocks_lock, flags); - return; - } - - change_parent(clk, pclk_info->pclk); + val = readl(config->synth_reg); + div += (val >> config->masks->mscale_sel_shift) & + config->masks->mscale_sel_mask; + div *= 1 << (((val >> config->masks->nscale_sel_shift) & + config->masks->nscale_sel_mask) + 1); - spin_lock_irqsave(&clocks_lock, flags); - if (pclk_info->scalable) { - val = readl(config->synth_reg); - div += (val >> GPT_MSCALE_SHIFT) & GPT_MSCALE_MASK; - div *= 1 << (((val >> GPT_NSCALE_SHIFT) & GPT_NSCALE_MASK) + 1); - } + if (!div) + return -EINVAL; clk->rate = (unsigned long)clk->pclk->rate / div; - spin_unlock_irqrestore(&clocks_lock, flags); + return 0; +} + +/* Configures new clock rate of gptiliary synthesizers used by: UART, FIRDA*/ +int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate) +{ + struct gpt_rate_tbl *tbls = clk->rate_config.tbls; + struct gpt_clk_config *config = clk->private_data; + unsigned long val, rate; + int i; + + i = round_rate_index(clk, desired_rate, &rate); + if (i < 0) + return i; + + val = readl(config->synth_reg) & ~(config->masks->mscale_sel_mask << + config->masks->mscale_sel_shift); + val |= (tbls[i].mscale & config->masks->mscale_sel_mask) << + config->masks->mscale_sel_shift; + val &= ~(config->masks->nscale_sel_mask << + config->masks->nscale_sel_shift); + val |= (tbls[i].nscale & config->masks->nscale_sel_mask) << + config->masks->nscale_sel_shift; + writel(val, config->synth_reg); + + clk->rate = rate; + + return 0; } /* - * Used for clocks that always have same value as the parent clock divided by a + * Calculates clcd clk rate for different values of div + * + * Fout from synthesizer can be given from below equation: + * Fout= Fin/2*div (division factor) + * div is 17 bits:- + * 0-13 (fractional part) + * 14-16 (integer part) + * To calculate Fout we left shift val by 14 bits and divide Fin by + * complete div (including fractional part) and then right shift the + * result by 14 places. + */ +unsigned long clcd_calc_rate(struct clk *clk, int index) +{ + unsigned long rate = clk->pclk->rate; + struct clcd_rate_tbl *tbls = clk->rate_config.tbls; + + rate /= 1000; + rate <<= 12; + rate /= (2 * tbls[index].div); + rate >>= 12; + rate *= 1000; + + return rate; +} + +/* + * calculates current programmed rate of clcd synthesizer + * Fout from synthesizer can be given from below equation: + * Fout= Fin/2*div (division factor) + * div is 17 bits:- + * 0-13 (fractional part) + * 14-16 (integer part) + * To calculate Fout we left shift val by 14 bits and divide Fin by + * complete div (including fractional part) and then right shift the + * result by 14 places. + */ +int clcd_clk_recalc(struct clk *clk) +{ + struct clcd_clk_config *config = clk->private_data; + unsigned int div = 1; + unsigned long prate; + unsigned int val; + + val = readl(config->synth_reg); + div = (val >> config->masks->div_factor_shift) & + config->masks->div_factor_mask; + + if (!div) + return -EINVAL; + + prate = clk->pclk->rate / 1000; /* first level division, make it KHz */ + + clk->rate = (((unsigned long)prate << 12) / (2 * div)) >> 12; + clk->rate *= 1000; + return 0; +} + +/* Configures new clock rate of auxiliary synthesizers used by: UART, FIRDA*/ +int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate) +{ + struct clcd_rate_tbl *tbls = clk->rate_config.tbls; + struct clcd_clk_config *config = clk->private_data; + unsigned long val, rate; + int i; + + i = round_rate_index(clk, desired_rate, &rate); + if (i < 0) + return i; + + val = readl(config->synth_reg) & ~(config->masks->div_factor_mask << + config->masks->div_factor_shift); + val |= (tbls[i].div & config->masks->div_factor_mask) << + config->masks->div_factor_shift; + writel(val, config->synth_reg); + + clk->rate = rate; + + return 0; +} + +/* + * Used for clocks that always have value as the parent clock divided by a * fixed divisor */ -void follow_parent(struct clk *clk) +int follow_parent(struct clk *clk) { - unsigned long flags; + unsigned int div_factor = (clk->div_factor < 1) ? 1 : clk->div_factor; - spin_lock_irqsave(&clocks_lock, flags); - clk->rate = clk->pclk->rate; - spin_unlock_irqrestore(&clocks_lock, flags); + clk->rate = clk->pclk->rate/div_factor; + return 0; } /** @@ -431,5 +880,124 @@ void follow_parent(struct clk *clk) */ void recalc_root_clocks(void) { - propagate_rate(&root_clks); + struct clk *pclk; + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&clocks_lock, flags); + list_for_each_entry(pclk, &root_clks, sibling) { + if (pclk->recalc) { + ret = pclk->recalc(pclk); + /* + * recalc will return error if clk out is not programmed + * In this case configure default clock. + */ + if (ret && pclk->set_rate) + pclk->set_rate(pclk, 0); + } + propagate_rate(pclk, 1); + /* Enable clks enabled on init, in software view */ + if (pclk->flags & ENABLED_ON_INIT) + do_clk_enable(pclk); + } + spin_unlock_irqrestore(&clocks_lock, flags); +} + +#ifdef CONFIG_DEBUG_FS +/* + * debugfs support to trace clock tree hierarchy and attributes + */ +static struct dentry *clk_debugfs_root; +static int clk_debugfs_register_one(struct clk *c) +{ + int err; + struct dentry *d, *child; + struct clk *pa = c->pclk; + char s[255]; + char *p = s; + + if (c) { + if (c->cl->con_id) + p += sprintf(p, "%s", c->cl->con_id); + if (c->cl->dev_id) + p += sprintf(p, "%s", c->cl->dev_id); + } + d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root); + if (!d) + return -ENOMEM; + c->dent = d; + + d = debugfs_create_u32("usage_count", S_IRUGO, c->dent, + (u32 *)&c->usage_count); + if (!d) { + err = -ENOMEM; + goto err_out; + } + d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate); + if (!d) { + err = -ENOMEM; + goto err_out; + } + d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags); + if (!d) { + err = -ENOMEM; + goto err_out; + } + return 0; + +err_out: + d = c->dent; + list_for_each_entry(child, &d->d_subdirs, d_u.d_child) + debugfs_remove(child); + debugfs_remove(c->dent); + return err; +} + +static int clk_debugfs_register(struct clk *c) +{ + int err; + struct clk *pa = c->pclk; + + if (pa && !pa->dent) { + err = clk_debugfs_register(pa); + if (err) + return err; + } + + if (!c->dent) { + err = clk_debugfs_register_one(c); + if (err) + return err; + } + return 0; +} + +static int __init clk_debugfs_init(void) +{ + struct clk *c; + struct dentry *d; + int err; + + d = debugfs_create_dir("clock", NULL); + if (!d) + return -ENOMEM; + clk_debugfs_root = d; + + list_for_each_entry(c, &clocks, node) { + err = clk_debugfs_register(c); + if (err) + goto err_out; + } + return 0; +err_out: + debugfs_remove_recursive(clk_debugfs_root); + return err; +} +late_initcall(clk_debugfs_init); + +static int clk_debugfs_reparent(struct clk *c) +{ + debugfs_remove(c->dent); + return clk_debugfs_register_one(c); } +#endif /* CONFIG_DEBUG_FS */ diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h index 2572260f990f..2ae6606930a6 100644 --- a/arch/arm/plat-spear/include/plat/clock.h +++ b/arch/arm/plat-spear/include/plat/clock.h @@ -21,6 +21,7 @@ /* clk structure flags */ #define ALWAYS_ENABLED (1 << 0) /* clock always enabled */ #define RESET_TO_ENABLE (1 << 1) /* reset register bit to enable clk */ +#define ENABLED_ON_INIT (1 << 2) /* clocks enabled at init */ /** * struct clkops - clock operations @@ -35,13 +36,11 @@ struct clkops { /** * struct pclk_info - parents info * @pclk: pointer to parent clk - * @pclk_mask: value to be written for selecting this parent - * @scalable: Is parent scalable (1 - YES, 0 - NO) + * @pclk_val: value to be written for selecting this parent */ struct pclk_info { struct clk *pclk; - u8 pclk_mask; - u8 scalable; + u8 pclk_val; }; /** @@ -54,11 +53,23 @@ struct pclk_info { struct pclk_sel { struct pclk_info *pclk_info; u8 pclk_count; - unsigned int *pclk_sel_reg; + void __iomem *pclk_sel_reg; unsigned int pclk_sel_mask; }; /** + * struct rate_config - clk rate configurations + * @tbls: array of device specific clk rate tables, in ascending order of rates + * @count: size of tbls array + * @default_index: default setting when originally disabled + */ +struct rate_config { + void *tbls; + u8 count; + u8 default_index; +}; + +/** * struct clk - clock structure * @usage_count: num of users who enabled this clock * @flags: flags for clock properties @@ -67,21 +78,32 @@ struct pclk_sel { * @en_reg_bit: clk enable/disable bit * @ops: clk enable/disable ops - generic_clkops selected if NULL * @recalc: pointer to clock rate recalculate function + * @set_rate: pointer to clock set rate function + * @calc_rate: pointer to clock get rate function for index + * @rate_config: rate configuration information, used by set_rate + * @div_factor: division factor to parent clock. * @pclk: current parent clk * @pclk_sel: pointer to parent selection structure * @pclk_sel_shift: register shift for selecting parent of this clock * @children: list for childrens or this clock * @sibling: node for list of clocks having same parents * @private_data: clock specific private data + * @node: list to maintain clocks linearly + * @cl: clocklook up assoicated with this clock + * @dent: object for debugfs */ struct clk { unsigned int usage_count; unsigned int flags; unsigned long rate; - unsigned int *en_reg; + void __iomem *en_reg; u8 en_reg_bit; const struct clkops *ops; - void (*recalc) (struct clk *); + int (*recalc) (struct clk *); + int (*set_rate) (struct clk *, unsigned long rate); + unsigned long (*calc_rate)(struct clk *, int index); + struct rate_config rate_config; + unsigned int div_factor; struct clk *pclk; struct pclk_sel *pclk_sel; @@ -90,37 +112,137 @@ struct clk { struct list_head children; struct list_head sibling; void *private_data; +#ifdef CONFIG_DEBUG_FS + struct list_head node; + struct clk_lookup *cl; + struct dentry *dent; +#endif }; /* pll configuration structure */ +struct pll_clk_masks { + u32 mode_mask; + u32 mode_shift; + + u32 norm_fdbk_m_mask; + u32 norm_fdbk_m_shift; + u32 dith_fdbk_m_mask; + u32 dith_fdbk_m_shift; + u32 div_p_mask; + u32 div_p_shift; + u32 div_n_mask; + u32 div_n_shift; +}; + struct pll_clk_config { - unsigned int *mode_reg; - unsigned int *cfg_reg; + void __iomem *mode_reg; + void __iomem *cfg_reg; + struct pll_clk_masks *masks; +}; + +/* pll clk rate config structure */ +struct pll_rate_tbl { + u8 mode; + u16 m; + u8 n; + u8 p; }; /* ahb and apb bus configuration structure */ +struct bus_clk_masks { + u32 mask; + u32 shift; +}; + struct bus_clk_config { - unsigned int *reg; - unsigned int mask; - unsigned int shift; + void __iomem *reg; + struct bus_clk_masks *masks; +}; + +/* ahb and apb clk bus rate config structure */ +struct bus_rate_tbl { + u8 div; +}; + +/* Aux clk configuration structure: applicable to UART and FIRDA */ +struct aux_clk_masks { + u32 eq_sel_mask; + u32 eq_sel_shift; + u32 eq1_mask; + u32 eq2_mask; + u32 xscale_sel_mask; + u32 xscale_sel_shift; + u32 yscale_sel_mask; + u32 yscale_sel_shift; }; -/* - * Aux clk configuration structure: applicable to GPT, UART and FIRDA - */ struct aux_clk_config { - unsigned int *synth_reg; + void __iomem *synth_reg; + struct aux_clk_masks *masks; +}; + +/* aux clk rate config structure */ +struct aux_rate_tbl { + u16 xscale; + u16 yscale; + u8 eq; +}; + +/* GPT clk configuration structure */ +struct gpt_clk_masks { + u32 mscale_sel_mask; + u32 mscale_sel_shift; + u32 nscale_sel_mask; + u32 nscale_sel_shift; +}; + +struct gpt_clk_config { + void __iomem *synth_reg; + struct gpt_clk_masks *masks; +}; + +/* gpt clk rate config structure */ +struct gpt_rate_tbl { + u16 mscale; + u16 nscale; +}; + +/* clcd clk configuration structure */ +struct clcd_synth_masks { + u32 div_factor_mask; + u32 div_factor_shift; +}; + +struct clcd_clk_config { + void __iomem *synth_reg; + struct clcd_synth_masks *masks; +}; + +/* clcd clk rate config structure */ +struct clcd_rate_tbl { + u16 div; }; /* platform specific clock functions */ void clk_register(struct clk_lookup *cl); void recalc_root_clocks(void); -/* clock recalc functions */ -void follow_parent(struct clk *clk); -void pll1_clk_recalc(struct clk *clk); -void bus_clk_recalc(struct clk *clk); -void gpt_clk_recalc(struct clk *clk); -void aux_clk_recalc(struct clk *clk); +/* clock recalc & set rate functions */ +int follow_parent(struct clk *clk); +unsigned long pll_calc_rate(struct clk *clk, int index); +int pll_clk_recalc(struct clk *clk); +int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate); +unsigned long bus_calc_rate(struct clk *clk, int index); +int bus_clk_recalc(struct clk *clk); +int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate); +unsigned long gpt_calc_rate(struct clk *clk, int index); +int gpt_clk_recalc(struct clk *clk); +int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate); +unsigned long aux_calc_rate(struct clk *clk, int index); +int aux_clk_recalc(struct clk *clk); +int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate); +unsigned long clcd_calc_rate(struct clk *clk, int index); +int clcd_clk_recalc(struct clk *clk); +int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate); #endif /* __PLAT_CLOCK_H */ diff --git a/arch/arm/plat-spear/include/plat/debug-macro.S b/arch/arm/plat-spear/include/plat/debug-macro.S index e91270e4f640..8501bbf2c092 100644 --- a/arch/arm/plat-spear/include/plat/debug-macro.S +++ b/arch/arm/plat-spear/include/plat/debug-macro.S @@ -12,7 +12,7 @@ */ #include <linux/amba/serial.h> -#include <mach/spear.h> +#include <mach/hardware.h> .macro addruart, rp, rv mov \rp, #SPEAR_DBG_UART_BASE @ Physical base diff --git a/arch/arm/plat-spear/include/plat/hardware.h b/arch/arm/plat-spear/include/plat/hardware.h new file mode 100644 index 000000000000..66d677225d15 --- /dev/null +++ b/arch/arm/plat-spear/include/plat/hardware.h @@ -0,0 +1,23 @@ +/* + * arch/arm/plat-spear/include/plat/hardware.h + * + * Hardware definitions for SPEAr + * + * Copyright (C) 2010 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_HARDWARE_H +#define __PLAT_HARDWARE_H + +#ifndef __ASSEMBLY__ +#define IOMEM(x) ((void __iomem __force *)(x)) +#else +#define IOMEM(x) (x) +#endif + +#endif /* __PLAT_HARDWARE_H */ diff --git a/arch/arm/plat-spear/include/plat/memory.h b/arch/arm/plat-spear/include/plat/memory.h index 27a4aba77343..7e3599e1104e 100644 --- a/arch/arm/plat-spear/include/plat/memory.h +++ b/arch/arm/plat-spear/include/plat/memory.h @@ -15,6 +15,6 @@ #define __PLAT_MEMORY_H /* Physical DRAM offset */ -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif /* __PLAT_MEMORY_H */ diff --git a/arch/arm/plat-spear/include/plat/system.h b/arch/arm/plat-spear/include/plat/system.h index 55a4e405d578..a235fa0ca777 100644 --- a/arch/arm/plat-spear/include/plat/system.h +++ b/arch/arm/plat-spear/include/plat/system.h @@ -14,9 +14,9 @@ #ifndef __PLAT_SYSTEM_H #define __PLAT_SYSTEM_H -#include <asm/hardware/sp810.h> #include <linux/io.h> -#include <mach/spear.h> +#include <asm/hardware/sp810.h> +#include <mach/hardware.h> static inline void arch_idle(void) { diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/plat-spear/include/plat/uncompress.h index 6dd455bafdfd..1bf84527aee4 100644 --- a/arch/arm/plat-spear/include/plat/uncompress.h +++ b/arch/arm/plat-spear/include/plat/uncompress.h @@ -13,7 +13,7 @@ #include <linux/io.h> #include <linux/amba/serial.h> -#include <mach/spear.h> +#include <mach/hardware.h> #ifndef __PLAT_UNCOMPRESS_H #define __PLAT_UNCOMPRESS_H diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c index 839c88df9994..dbb6e4fff79d 100644 --- a/arch/arm/plat-spear/time.c +++ b/arch/arm/plat-spear/time.c @@ -1,7 +1,7 @@ /* * arch/arm/plat-spear/time.c * - * Copyright (C) 2009 ST Microelectronics + * Copyright (C) 2010 ST Microelectronics * Shiraz Hashim<shiraz.hashim@st.com> * * This file is licensed under the terms of the GNU General Public @@ -20,10 +20,9 @@ #include <linux/time.h> #include <linux/irq.h> #include <asm/mach/time.h> -#include <mach/irqs.h> -#include <mach/hardware.h> -#include <mach/spear.h> #include <mach/generic.h> +#include <mach/hardware.h> +#include <mach/irqs.h> /* * We would use TIMER0 and TIMER1 as clockevent and clocksource. @@ -211,7 +210,7 @@ static void __init spear_clockevent_init(void) void __init spear_setup_timer(void) { - struct clk *pll3_clk; + int ret; if (!request_mem_region(SPEAR_GPT0_BASE, SZ_1K, "gpt0")) { pr_err("%s:cannot get IO addr\n", __func__); @@ -230,26 +229,21 @@ void __init spear_setup_timer(void) goto err_iomap; } - pll3_clk = clk_get(NULL, "pll3_48m_clk"); - if (!pll3_clk) { - pr_err("%s:couldn't get PLL3 as parent for gpt\n", __func__); - goto err_iomap; + ret = clk_enable(gpt_clk); + if (ret < 0) { + pr_err("%s:couldn't enable gpt clock\n", __func__); + goto err_clk; } - clk_set_parent(gpt_clk, pll3_clk); - spear_clockevent_init(); spear_clocksource_init(); return; +err_clk: + clk_put(gpt_clk); err_iomap: iounmap(gpt_base); - err_mem: release_mem_region(SPEAR_GPT0_BASE, SZ_1K); } - -struct sys_timer spear_sys_timer = { - .init = spear_setup_timer, -}; diff --git a/arch/arm/plat-stmp3xxx/include/mach/memory.h b/arch/arm/plat-stmp3xxx/include/mach/memory.h index 7b875a07a1a7..61fa54882e12 100644 --- a/arch/arm/plat-stmp3xxx/include/mach/memory.h +++ b/arch/arm/plat-stmp3xxx/include/mach/memory.h @@ -17,6 +17,6 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x40000000) +#define PLAT_PHYS_OFFSET UL(0x40000000) #endif diff --git a/arch/arm/plat-tcc/include/mach/memory.h b/arch/arm/plat-tcc/include/mach/memory.h index cd91ba8a670b..28a6e0cd13b3 100644 --- a/arch/arm/plat-tcc/include/mach/memory.h +++ b/arch/arm/plat-tcc/include/mach/memory.h @@ -13,6 +13,6 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x20000000) +#define PLAT_PHYS_OFFSET UL(0x20000000) #endif diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index 0797cb528b46..bbf3da012afd 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -153,7 +153,7 @@ static struct notifier_block vfp_notifier_block = { * Raise a SIGFPE for the current process. * sicode describes the signal being raised. */ -void vfp_raise_sigfpe(unsigned int sicode, struct pt_regs *regs) +static void vfp_raise_sigfpe(unsigned int sicode, struct pt_regs *regs) { siginfo_t info; @@ -489,8 +489,11 @@ void vfp_flush_hwstate(struct thread_info *thread) /* * VFP hardware can lose all context when a CPU goes offline. - * Safely clear our held state when a CPU has been killed, and - * re-enable access to VFP when the CPU comes back online. + * As we will be running in SMP mode with CPU hotplug, we will save the + * hardware state at every thread switch. We clear our held state when + * a CPU has been killed, indicating that the VFP hardware doesn't contain + * a threads VFP state. When a CPU starts up, we re-enable access to the + * VFP hardware. * * Both CPU_DYING and CPU_STARTING are called on the CPU which * is being offlined/onlined. diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c index c9113619029f..8d73724c0092 100644 --- a/arch/blackfin/kernel/time.c +++ b/arch/blackfin/kernel/time.c @@ -114,16 +114,14 @@ u32 arch_gettimeoffset(void) /* * timer_interrupt() needs to keep up the real-time clock, - * as well as call the "do_timer()" routine every clocktick + * as well as call the "xtime_update()" routine every clocktick */ #ifdef CONFIG_CORE_TIMER_IRQ_L1 __attribute__((l1_text)) #endif irqreturn_t timer_interrupt(int irq, void *dummy) { - write_seqlock(&xtime_lock); - do_timer(1); - write_sequnlock(&xtime_lock); + xtime_update(1); #ifdef CONFIG_IPIPE update_root_process_times(get_irq_regs()); diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S index 4122678529c0..c40d07f708e8 100644 --- a/arch/blackfin/kernel/vmlinux.lds.S +++ b/arch/blackfin/kernel/vmlinux.lds.S @@ -136,7 +136,7 @@ SECTIONS . = ALIGN(16); INIT_DATA_SECTION(16) - PERCPU(4) + PERCPU(32, 4) .exit.data : { diff --git a/arch/cris/arch-v10/kernel/time.c b/arch/cris/arch-v10/kernel/time.c index 00eb36f8debf..20c85b5dc7d0 100644 --- a/arch/cris/arch-v10/kernel/time.c +++ b/arch/cris/arch-v10/kernel/time.c @@ -140,7 +140,7 @@ stop_watchdog(void) /* * timer_interrupt() needs to keep up the real-time clock, - * as well as call the "do_timer()" routine every clocktick + * as well as call the "xtime_update()" routine every clocktick */ //static unsigned short myjiff; /* used by our debug routine print_timestamp */ @@ -176,7 +176,7 @@ timer_interrupt(int irq, void *dev_id) /* call the real timer interrupt handler */ - do_timer(1); + xtime_update(1); cris_do_profile(regs); /* Save profiling information */ return IRQ_HANDLED; diff --git a/arch/cris/arch-v32/kernel/smp.c b/arch/cris/arch-v32/kernel/smp.c index 84fed3b4b079..4c9e3e1ba5d1 100644 --- a/arch/cris/arch-v32/kernel/smp.c +++ b/arch/cris/arch-v32/kernel/smp.c @@ -26,7 +26,9 @@ #define FLUSH_ALL (void*)0xffffffff /* Vector of locks used for various atomic operations */ -spinlock_t cris_atomic_locks[] = { [0 ... LOCK_COUNT - 1] = SPIN_LOCK_UNLOCKED}; +spinlock_t cris_atomic_locks[] = { + [0 ... LOCK_COUNT - 1] = __SPIN_LOCK_UNLOCKED(cris_atomic_locks) +}; /* CPU masks */ cpumask_t phys_cpu_present_map = CPU_MASK_NONE; diff --git a/arch/cris/arch-v32/kernel/time.c b/arch/cris/arch-v32/kernel/time.c index a545211e999d..bb978ede8985 100644 --- a/arch/cris/arch-v32/kernel/time.c +++ b/arch/cris/arch-v32/kernel/time.c @@ -183,7 +183,7 @@ void handle_watchdog_bite(struct pt_regs *regs) /* * timer_interrupt() needs to keep up the real-time clock, - * as well as call the "do_timer()" routine every clocktick. + * as well as call the "xtime_update()" routine every clocktick. */ extern void cris_do_profile(struct pt_regs *regs); @@ -216,9 +216,7 @@ static inline irqreturn_t timer_interrupt(int irq, void *dev_id) return IRQ_HANDLED; /* Call the real timer interrupt handler */ - write_seqlock(&xtime_lock); - do_timer(1); - write_sequnlock(&xtime_lock); + xtime_update(1); return IRQ_HANDLED; } diff --git a/arch/cris/kernel/vmlinux.lds.S b/arch/cris/kernel/vmlinux.lds.S index c49be845f96a..728bbd9e7d4c 100644 --- a/arch/cris/kernel/vmlinux.lds.S +++ b/arch/cris/kernel/vmlinux.lds.S @@ -102,7 +102,7 @@ SECTIONS #endif __vmlinux_end = .; /* Last address of the physical file. */ #ifdef CONFIG_ETRAX_ARCH_V32 - PERCPU(PAGE_SIZE) + PERCPU(32, PAGE_SIZE) .init.ramfs : { INIT_RAM_FS diff --git a/arch/frv/include/asm/futex.h b/arch/frv/include/asm/futex.h index 08b3d1da3583..4bea27f50a7a 100644 --- a/arch/frv/include/asm/futex.h +++ b/arch/frv/include/asm/futex.h @@ -7,10 +7,11 @@ #include <asm/errno.h> #include <asm/uaccess.h> -extern int futex_atomic_op_inuser(int encoded_op, int __user *uaddr); +extern int futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr); static inline int -futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) +futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) { return -ENOSYS; } diff --git a/arch/frv/kernel/futex.c b/arch/frv/kernel/futex.c index 14f64b054c7e..d155ca9e5098 100644 --- a/arch/frv/kernel/futex.c +++ b/arch/frv/kernel/futex.c @@ -18,7 +18,7 @@ * the various futex operations; MMU fault checking is ignored under no-MMU * conditions */ -static inline int atomic_futex_op_xchg_set(int oparg, int __user *uaddr, int *_oldval) +static inline int atomic_futex_op_xchg_set(int oparg, u32 __user *uaddr, int *_oldval) { int oldval, ret; @@ -50,7 +50,7 @@ static inline int atomic_futex_op_xchg_set(int oparg, int __user *uaddr, int *_o return ret; } -static inline int atomic_futex_op_xchg_add(int oparg, int __user *uaddr, int *_oldval) +static inline int atomic_futex_op_xchg_add(int oparg, u32 __user *uaddr, int *_oldval) { int oldval, ret; @@ -83,7 +83,7 @@ static inline int atomic_futex_op_xchg_add(int oparg, int __user *uaddr, int *_o return ret; } -static inline int atomic_futex_op_xchg_or(int oparg, int __user *uaddr, int *_oldval) +static inline int atomic_futex_op_xchg_or(int oparg, u32 __user *uaddr, int *_oldval) { int oldval, ret; @@ -116,7 +116,7 @@ static inline int atomic_futex_op_xchg_or(int oparg, int __user *uaddr, int *_ol return ret; } -static inline int atomic_futex_op_xchg_and(int oparg, int __user *uaddr, int *_oldval) +static inline int atomic_futex_op_xchg_and(int oparg, u32 __user *uaddr, int *_oldval) { int oldval, ret; @@ -149,7 +149,7 @@ static inline int atomic_futex_op_xchg_and(int oparg, int __user *uaddr, int *_o return ret; } -static inline int atomic_futex_op_xchg_xor(int oparg, int __user *uaddr, int *_oldval) +static inline int atomic_futex_op_xchg_xor(int oparg, u32 __user *uaddr, int *_oldval) { int oldval, ret; @@ -186,7 +186,7 @@ static inline int atomic_futex_op_xchg_xor(int oparg, int __user *uaddr, int *_o /* * do the futex operations */ -int futex_atomic_op_inuser(int encoded_op, int __user *uaddr) +int futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr) { int op = (encoded_op >> 28) & 7; int cmp = (encoded_op >> 24) & 15; @@ -197,7 +197,7 @@ int futex_atomic_op_inuser(int encoded_op, int __user *uaddr) if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) oparg = 1 << oparg; - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; pagefault_disable(); diff --git a/arch/frv/kernel/time.c b/arch/frv/kernel/time.c index 0ddbbae83cb2..b457de496b70 100644 --- a/arch/frv/kernel/time.c +++ b/arch/frv/kernel/time.c @@ -50,21 +50,13 @@ static struct irqaction timer_irq = { /* * timer_interrupt() needs to keep up the real-time clock, - * as well as call the "do_timer()" routine every clocktick + * as well as call the "xtime_update()" routine every clocktick */ static irqreturn_t timer_interrupt(int irq, void *dummy) { profile_tick(CPU_PROFILING); - /* - * Here we are in the timer irq handler. We just have irqs locally - * disabled but we don't know if the timer_bh is running on the other - * CPU. We need to avoid to SMP race with it. NOTE: we don't need - * the irq version of write_lock because as just said we have irq - * locally disabled. -arca - */ - write_seqlock(&xtime_lock); - do_timer(1); + xtime_update(1); #ifdef CONFIG_HEARTBEAT static unsigned short n; @@ -72,8 +64,6 @@ static irqreturn_t timer_interrupt(int irq, void *dummy) __set_LEDS(n); #endif /* CONFIG_HEARTBEAT */ - write_sequnlock(&xtime_lock); - update_process_times(user_mode(get_irq_regs())); return IRQ_HANDLED; diff --git a/arch/frv/kernel/vmlinux.lds.S b/arch/frv/kernel/vmlinux.lds.S index 8b973f3cc90e..0daae8af5787 100644 --- a/arch/frv/kernel/vmlinux.lds.S +++ b/arch/frv/kernel/vmlinux.lds.S @@ -37,7 +37,7 @@ SECTIONS _einittext = .; INIT_DATA_SECTION(8) - PERCPU(4096) + PERCPU(L1_CACHE_BYTES, 4096) . = ALIGN(PAGE_SIZE); __init_end = .; diff --git a/arch/h8300/kernel/time.c b/arch/h8300/kernel/time.c index 165005aff9df..32263a138aa6 100644 --- a/arch/h8300/kernel/time.c +++ b/arch/h8300/kernel/time.c @@ -35,9 +35,7 @@ void h8300_timer_tick(void) { if (current->pid) profile_tick(CPU_PROFILING); - write_seqlock(&xtime_lock); - do_timer(1); - write_sequnlock(&xtime_lock); + xtime_update(1); update_process_times(user_mode(get_irq_regs())); } diff --git a/arch/h8300/kernel/timer/timer8.c b/arch/h8300/kernel/timer/timer8.c index 3946c0fa8374..7a1533fad47d 100644 --- a/arch/h8300/kernel/timer/timer8.c +++ b/arch/h8300/kernel/timer/timer8.c @@ -61,7 +61,7 @@ /* * timer_interrupt() needs to keep up the real-time clock, - * as well as call the "do_timer()" routine every clocktick + * as well as call the "xtime_update()" routine every clocktick */ static irqreturn_t timer_interrupt(int irq, void *dev_id) diff --git a/arch/ia64/configs/generic_defconfig b/arch/ia64/configs/generic_defconfig index 3ded8fe62759..1d7bca0a396d 100644 --- a/arch/ia64/configs/generic_defconfig +++ b/arch/ia64/configs/generic_defconfig @@ -233,3 +233,4 @@ CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRC_T10DIF=y +CONFIG_MISC_DEVICES=y diff --git a/arch/ia64/configs/gensparse_defconfig b/arch/ia64/configs/gensparse_defconfig index 3a98b2dd58ac..b11fa880e4b6 100644 --- a/arch/ia64/configs/gensparse_defconfig +++ b/arch/ia64/configs/gensparse_defconfig @@ -208,3 +208,4 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MUTEXES=y CONFIG_CRYPTO_MD5=y +CONFIG_MISC_DEVICES=y diff --git a/arch/ia64/hp/sim/simserial.c b/arch/ia64/hp/sim/simserial.c index 13633da0d3de..bff0824cf8a4 100644 --- a/arch/ia64/hp/sim/simserial.c +++ b/arch/ia64/hp/sim/simserial.c @@ -390,8 +390,7 @@ static void rs_unthrottle(struct tty_struct * tty) } -static int rs_ioctl(struct tty_struct *tty, struct file * file, - unsigned int cmd, unsigned long arg) +static int rs_ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg) { if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGSTRUCT) && diff --git a/arch/ia64/include/asm/dma-mapping.h b/arch/ia64/include/asm/dma-mapping.h index a2e7368a0150..4336d080b241 100644 --- a/arch/ia64/include/asm/dma-mapping.h +++ b/arch/ia64/include/asm/dma-mapping.h @@ -12,6 +12,8 @@ #define ARCH_HAS_DMA_GET_REQUIRED_MASK +#define DMA_ERROR_CODE 0 + extern struct dma_map_ops *dma_ops; extern struct ia64_machine_vector ia64_mv; extern void set_iommu_machvec(void); diff --git a/arch/ia64/include/asm/futex.h b/arch/ia64/include/asm/futex.h index c7f0f062239c..8428525ddb22 100644 --- a/arch/ia64/include/asm/futex.h +++ b/arch/ia64/include/asm/futex.h @@ -46,7 +46,7 @@ do { \ } while (0) static inline int -futex_atomic_op_inuser (int encoded_op, int __user *uaddr) +futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr) { int op = (encoded_op >> 28) & 7; int cmp = (encoded_op >> 24) & 15; @@ -56,7 +56,7 @@ futex_atomic_op_inuser (int encoded_op, int __user *uaddr) if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) oparg = 1 << oparg; - if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int))) + if (! access_ok (VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; pagefault_disable(); @@ -100,23 +100,26 @@ futex_atomic_op_inuser (int encoded_op, int __user *uaddr) } static inline int -futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) +futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) { - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; { - register unsigned long r8 __asm ("r8"); + register unsigned long r8 __asm ("r8") = 0; + unsigned long prev; __asm__ __volatile__( " mf;; \n" " mov ar.ccv=%3;; \n" "[1:] cmpxchg4.acq %0=[%1],%2,ar.ccv \n" " .xdata4 \"__ex_table\", 1b-., 2f-. \n" "[2:]" - : "=r" (r8) + : "=r" (prev) : "r" (uaddr), "r" (newval), "rO" ((long) (unsigned) oldval) : "memory"); + *uval = prev; return r8; } } diff --git a/arch/ia64/include/asm/rwsem.h b/arch/ia64/include/asm/rwsem.h index 215d5454c7d3..3027e7516d85 100644 --- a/arch/ia64/include/asm/rwsem.h +++ b/arch/ia64/include/asm/rwsem.h @@ -25,20 +25,8 @@ #error "Please don't include <asm/rwsem.h> directly, use <linux/rwsem.h> instead." #endif -#include <linux/list.h> -#include <linux/spinlock.h> - #include <asm/intrinsics.h> -/* - * the semaphore definition - */ -struct rw_semaphore { - signed long count; - spinlock_t wait_lock; - struct list_head wait_list; -}; - #define RWSEM_UNLOCKED_VALUE __IA64_UL_CONST(0x0000000000000000) #define RWSEM_ACTIVE_BIAS (1L) #define RWSEM_ACTIVE_MASK (0xffffffffL) @@ -46,26 +34,6 @@ struct rw_semaphore { #define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS #define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS) -#define __RWSEM_INITIALIZER(name) \ - { RWSEM_UNLOCKED_VALUE, __SPIN_LOCK_UNLOCKED((name).wait_lock), \ - LIST_HEAD_INIT((name).wait_list) } - -#define DECLARE_RWSEM(name) \ - struct rw_semaphore name = __RWSEM_INITIALIZER(name) - -extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem); -extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem); -extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem); -extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem); - -static inline void -init_rwsem (struct rw_semaphore *sem) -{ - sem->count = RWSEM_UNLOCKED_VALUE; - spin_lock_init(&sem->wait_lock); - INIT_LIST_HEAD(&sem->wait_list); -} - /* * lock for reading */ @@ -174,9 +142,4 @@ __downgrade_write (struct rw_semaphore *sem) #define rwsem_atomic_add(delta, sem) atomic64_add(delta, (atomic64_t *)(&(sem)->count)) #define rwsem_atomic_update(delta, sem) atomic64_add_return(delta, (atomic64_t *)(&(sem)->count)) -static inline int rwsem_is_locked(struct rw_semaphore *sem) -{ - return (sem->count != 0); -} - #endif /* _ASM_IA64_RWSEM_H */ diff --git a/arch/ia64/kernel/mca.c b/arch/ia64/kernel/mca.c index 1753f6a30d55..80d50b83d419 100644 --- a/arch/ia64/kernel/mca.c +++ b/arch/ia64/kernel/mca.c @@ -582,6 +582,8 @@ out: /* Get the CPE error record and log it */ ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE); + local_irq_disable(); + return IRQ_HANDLED; } @@ -1859,7 +1861,8 @@ ia64_mca_cpu_init(void *cpu_data) data = mca_bootmem(); first_time = 0; } else - data = __get_free_pages(GFP_KERNEL, get_order(sz)); + data = (void *)__get_free_pages(GFP_KERNEL, + get_order(sz)); if (!data) panic("Could not allocate MCA memory for cpu %d\n", cpu); diff --git a/arch/ia64/kernel/time.c b/arch/ia64/kernel/time.c index 9702fa92489e..156ad803d5b7 100644 --- a/arch/ia64/kernel/time.c +++ b/arch/ia64/kernel/time.c @@ -190,19 +190,10 @@ timer_interrupt (int irq, void *dev_id) new_itm += local_cpu_data->itm_delta; - if (smp_processor_id() == time_keeper_id) { - /* - * Here we are in the timer irq handler. We have irqs locally - * disabled, but we don't know if the timer_bh is running on - * another CPU. We need to avoid to SMP race by acquiring the - * xtime_lock. - */ - write_seqlock(&xtime_lock); - do_timer(1); - local_cpu_data->itm_next = new_itm; - write_sequnlock(&xtime_lock); - } else - local_cpu_data->itm_next = new_itm; + if (smp_processor_id() == time_keeper_id) + xtime_update(1); + + local_cpu_data->itm_next = new_itm; if (time_after(new_itm, ia64_get_itc())) break; @@ -222,7 +213,7 @@ skip_process_time_accounting: * comfort, we increase the safety margin by * intentionally dropping the next tick(s). We do NOT * update itm.next because that would force us to call - * do_timer() which in turn would let our clock run + * xtime_update() which in turn would let our clock run * too fast (with the potentially devastating effect * of losing monotony of time). */ diff --git a/arch/ia64/kernel/vmlinux.lds.S b/arch/ia64/kernel/vmlinux.lds.S index 5a4d044dcb1c..787de4a77d82 100644 --- a/arch/ia64/kernel/vmlinux.lds.S +++ b/arch/ia64/kernel/vmlinux.lds.S @@ -198,7 +198,7 @@ SECTIONS { /* Per-cpu data: */ . = ALIGN(PERCPU_PAGE_SIZE); - PERCPU_VADDR(PERCPU_ADDR, :percpu) + PERCPU_VADDR(SMP_CACHE_BYTES, PERCPU_ADDR, :percpu) __phys_per_cpu_start = __per_cpu_load; /* * ensure percpu data fits diff --git a/arch/ia64/sn/kernel/setup.c b/arch/ia64/sn/kernel/setup.c index dbc4cbecb5ed..77db0b514fa4 100644 --- a/arch/ia64/sn/kernel/setup.c +++ b/arch/ia64/sn/kernel/setup.c @@ -592,7 +592,7 @@ void __cpuinit sn_cpu_init(void) /* * Don't check status. The SAL call is not supported on all PROMs * but a failure is harmless. - * Architechtuallly, cpu_init is always called twice on cpu 0. We + * Architecturally, cpu_init is always called twice on cpu 0. We * should set cpu_number on cpu 0 once. */ if (cpuid == 0) { diff --git a/arch/ia64/sn/pci/tioca_provider.c b/arch/ia64/sn/pci/tioca_provider.c index 4d4536e3b6f3..9c271be9919a 100644 --- a/arch/ia64/sn/pci/tioca_provider.c +++ b/arch/ia64/sn/pci/tioca_provider.c @@ -509,7 +509,7 @@ tioca_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir) * use the GART mapped mode. */ static u64 -tioca_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count, int dma_flags) +tioca_dma_map(struct pci_dev *pdev, unsigned long paddr, size_t byte_count, int dma_flags) { u64 mapaddr; diff --git a/arch/ia64/xen/time.c b/arch/ia64/xen/time.c index c1c544513e8d..1f8244a78bee 100644 --- a/arch/ia64/xen/time.c +++ b/arch/ia64/xen/time.c @@ -139,14 +139,11 @@ consider_steal_time(unsigned long new_itm) run_posix_cpu_timers(p); delta_itm += local_cpu_data->itm_delta * (stolen + blocked); - if (cpu == time_keeper_id) { - write_seqlock(&xtime_lock); - do_timer(stolen + blocked); - local_cpu_data->itm_next = delta_itm + new_itm; - write_sequnlock(&xtime_lock); - } else { - local_cpu_data->itm_next = delta_itm + new_itm; - } + if (cpu == time_keeper_id) + xtime_update(stolen + blocked); + + local_cpu_data->itm_next = delta_itm + new_itm; + per_cpu(xen_stolen_time, cpu) += NS_PER_TICK * stolen; per_cpu(xen_blocked_time, cpu) += NS_PER_TICK * blocked; } diff --git a/arch/m32r/kernel/time.c b/arch/m32r/kernel/time.c index bda86820bffd..84dd04048db9 100644 --- a/arch/m32r/kernel/time.c +++ b/arch/m32r/kernel/time.c @@ -107,15 +107,14 @@ u32 arch_gettimeoffset(void) /* * timer_interrupt() needs to keep up the real-time clock, - * as well as call the "do_timer()" routine every clocktick + * as well as call the "xtime_update()" routine every clocktick */ static irqreturn_t timer_interrupt(int irq, void *dev_id) { #ifndef CONFIG_SMP profile_tick(CPU_PROFILING); #endif - /* XXX FIXME. Uh, the xtime_lock should be held here, no? */ - do_timer(1); + xtime_update(1); #ifndef CONFIG_SMP update_process_times(user_mode(get_irq_regs())); diff --git a/arch/m32r/kernel/vmlinux.lds.S b/arch/m32r/kernel/vmlinux.lds.S index 7da94eaa082b..c194d64cdbb9 100644 --- a/arch/m32r/kernel/vmlinux.lds.S +++ b/arch/m32r/kernel/vmlinux.lds.S @@ -53,7 +53,7 @@ SECTIONS __init_begin = .; INIT_TEXT_SECTION(PAGE_SIZE) INIT_DATA_SECTION(16) - PERCPU(PAGE_SIZE) + PERCPU(32, PAGE_SIZE) . = ALIGN(PAGE_SIZE); __init_end = .; /* freed after init ends here */ diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index bc9271b85759..525174d41679 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -18,11 +18,9 @@ config RWSEM_XCHGADD_ALGORITHM config ARCH_HAS_ILOG2_U32 bool - default n config ARCH_HAS_ILOG2_U64 bool - default n config GENERIC_HWEIGHT bool @@ -242,6 +240,37 @@ config SUN3 If you don't want to compile a kernel exclusively for a Sun 3, say N. +config NATFEAT + bool "ARAnyM emulator support" + depends on ATARI + help + This option enables support for ARAnyM native features, such as + access to a disk image as /dev/hda. + +config NFBLOCK + tristate "NatFeat block device support" + depends on BLOCK && NATFEAT + help + Say Y to include support for the ARAnyM NatFeat block device + which allows direct access to the hard drives without using + the hardware emulation. + +config NFCON + tristate "NatFeat console driver" + depends on NATFEAT + help + Say Y to include support for the ARAnyM NatFeat console driver + which allows the console output to be redirected to the stderr + output of ARAnyM. + +config NFETH + tristate "NatFeat Ethernet support" + depends on NET_ETHERNET && NATFEAT + help + Say Y to include support for the ARAnyM NatFeat network device + which will emulate a regular ethernet device while presenting an + ethertap device to the host system. + comment "Processor type" config M68020 @@ -554,14 +583,6 @@ config MVME147_SCC This is the driver for the serial ports on the Motorola MVME147 boards. Everyone using one of these boards should say Y here. -config SERIAL167 - bool "CD2401 support for MVME166/7 serial ports" - depends on MVME16x - help - This is the driver for the serial ports on the Motorola MVME166, - 167, and 172 boards. Everyone using one of these boards should say - Y here. - config MVME162_SCC bool "SCC support for MVME162 serial ports" depends on MVME16x && BROKEN diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile index b06a7e3cbcd6..b793163abc61 100644 --- a/arch/m68k/Makefile +++ b/arch/m68k/Makefile @@ -76,6 +76,7 @@ core-$(CONFIG_MVME16x) += arch/m68k/mvme16x/ core-$(CONFIG_BVME6000) += arch/m68k/bvme6000/ core-$(CONFIG_SUN3X) += arch/m68k/sun3x/ arch/m68k/sun3/ core-$(CONFIG_SUN3) += arch/m68k/sun3/ arch/m68k/sun3/prom/ +core-$(CONFIG_NATFEAT) += arch/m68k/emu/ core-$(CONFIG_M68040) += arch/m68k/fpsp040/ core-$(CONFIG_M68060) += arch/m68k/ifpsp060/ core-$(CONFIG_M68KFPU_EMU) += arch/m68k/math-emu/ diff --git a/arch/m68k/amiga/chipram.c b/arch/m68k/amiga/chipram.c index 61df1d33c050..dd0447db1c90 100644 --- a/arch/m68k/amiga/chipram.c +++ b/arch/m68k/amiga/chipram.c @@ -33,10 +33,6 @@ void __init amiga_chip_init(void) if (!AMIGAHW_PRESENT(CHIP_RAM)) return; - /* - * Remove the first 4 pages where PPC exception handlers will be located - */ - amiga_chip_size -= 0x4000; chipram_res.end = amiga_chip_size-1; request_resource(&iomem_resource, &chipram_res); diff --git a/arch/m68k/bvme6000/config.c b/arch/m68k/bvme6000/config.c index 9fe6fefb5e14..1edd95095cb4 100644 --- a/arch/m68k/bvme6000/config.c +++ b/arch/m68k/bvme6000/config.c @@ -45,8 +45,8 @@ extern int bvme6000_set_clock_mmss (unsigned long); extern void bvme6000_reset (void); void bvme6000_set_vectors (void); -/* Save tick handler routine pointer, will point to do_timer() in - * kernel/sched.c, called via bvme6000_process_int() */ +/* Save tick handler routine pointer, will point to xtime_update() in + * kernel/timer/timekeeping.c, called via bvme6000_process_int() */ static irq_handler_t tick_handler; diff --git a/arch/m68k/emu/Makefile b/arch/m68k/emu/Makefile new file mode 100644 index 000000000000..7dc201080308 --- /dev/null +++ b/arch/m68k/emu/Makefile @@ -0,0 +1,9 @@ +# +# Makefile for Linux arch/m68k/emu source directory +# + +obj-y += natfeat.o + +obj-$(CONFIG_NFBLOCK) += nfblock.o +obj-$(CONFIG_NFCON) += nfcon.o +obj-$(CONFIG_NFETH) += nfeth.o diff --git a/arch/m68k/emu/natfeat.c b/arch/m68k/emu/natfeat.c new file mode 100644 index 000000000000..2291a7d69d49 --- /dev/null +++ b/arch/m68k/emu/natfeat.c @@ -0,0 +1,78 @@ +/* + * natfeat.c - ARAnyM hardware support via Native Features (natfeats) + * + * Copyright (c) 2005 Petr Stehlik of ARAnyM dev team + * + * Reworked for Linux by Roman Zippel <zippel@linux-m68k.org> + * + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL), incorporated herein by reference. + */ + +#include <linux/types.h> +#include <linux/console.h> +#include <linux/string.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/io.h> +#include <asm/machdep.h> +#include <asm/natfeat.h> + +asm("\n" +" .global nf_get_id,nf_call\n" +"nf_get_id:\n" +" .short 0x7300\n" +" rts\n" +"nf_call:\n" +" .short 0x7301\n" +" rts\n" +"1: moveq.l #0,%d0\n" +" rts\n" +" .section __ex_table,\"a\"\n" +" .long nf_get_id,1b\n" +" .long nf_call,1b\n" +" .previous"); +EXPORT_SYMBOL_GPL(nf_get_id); +EXPORT_SYMBOL_GPL(nf_call); + +void nfprint(const char *fmt, ...) +{ + static char buf[256]; + va_list ap; + int n; + + va_start(ap, fmt); + n = vsnprintf(buf, 256, fmt, ap); + nf_call(nf_get_id("NF_STDERR"), buf); + va_end(ap); +} + +static void nf_poweroff(void) +{ + long id = nf_get_id("NF_SHUTDOWN"); + + if (id) + nf_call(id); +} + +void nf_init(void) +{ + unsigned long id, version; + char buf[256]; + + id = nf_get_id("NF_VERSION"); + if (!id) + return; + version = nf_call(id); + + id = nf_get_id("NF_NAME"); + if (!id) + return; + nf_call(id, buf, 256); + buf[255] = 0; + + pr_info("NatFeats found (%s, %lu.%lu)\n", buf, version >> 16, + version & 0xffff); + + mach_power_off = nf_poweroff; +} diff --git a/arch/m68k/emu/nfblock.c b/arch/m68k/emu/nfblock.c new file mode 100644 index 000000000000..48e50f8c1c7e --- /dev/null +++ b/arch/m68k/emu/nfblock.c @@ -0,0 +1,195 @@ +/* + * ARAnyM block device driver + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/init.h> + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/types.h> +#include <linux/genhd.h> +#include <linux/blkdev.h> +#include <linux/hdreg.h> +#include <linux/slab.h> + +#include <asm/natfeat.h> + +static long nfhd_id; + +enum { + /* emulation entry points */ + NFHD_READ_WRITE = 10, + NFHD_GET_CAPACITY = 14, + + /* skip ACSI devices */ + NFHD_DEV_OFFSET = 8, +}; + +static inline s32 nfhd_read_write(u32 major, u32 minor, u32 rwflag, u32 recno, + u32 count, u32 buf) +{ + return nf_call(nfhd_id + NFHD_READ_WRITE, major, minor, rwflag, recno, + count, buf); +} + +static inline s32 nfhd_get_capacity(u32 major, u32 minor, u32 *blocks, + u32 *blocksize) +{ + return nf_call(nfhd_id + NFHD_GET_CAPACITY, major, minor, blocks, + blocksize); +} + +static LIST_HEAD(nfhd_list); + +static int major_num; +module_param(major_num, int, 0); + +struct nfhd_device { + struct list_head list; + int id; + u32 blocks, bsize; + int bshift; + struct request_queue *queue; + struct gendisk *disk; +}; + +static int nfhd_make_request(struct request_queue *queue, struct bio *bio) +{ + struct nfhd_device *dev = queue->queuedata; + struct bio_vec *bvec; + int i, dir, len, shift; + sector_t sec = bio->bi_sector; + + dir = bio_data_dir(bio); + shift = dev->bshift; + bio_for_each_segment(bvec, bio, i) { + len = bvec->bv_len; + len >>= 9; + nfhd_read_write(dev->id, 0, dir, sec >> shift, len >> shift, + bvec_to_phys(bvec)); + sec += len; + } + bio_endio(bio, 0); + return 0; +} + +static int nfhd_getgeo(struct block_device *bdev, struct hd_geometry *geo) +{ + struct nfhd_device *dev = bdev->bd_disk->private_data; + + geo->cylinders = dev->blocks >> (6 - dev->bshift); + geo->heads = 4; + geo->sectors = 16; + + return 0; +} + +static const struct block_device_operations nfhd_ops = { + .owner = THIS_MODULE, + .getgeo = nfhd_getgeo, +}; + +static int __init nfhd_init_one(int id, u32 blocks, u32 bsize) +{ + struct nfhd_device *dev; + int dev_id = id - NFHD_DEV_OFFSET; + + pr_info("nfhd%u: found device with %u blocks (%u bytes)\n", dev_id, + blocks, bsize); + + if (bsize < 512 || (bsize & (bsize - 1))) { + pr_warn("nfhd%u: invalid block size\n", dev_id); + return -EINVAL; + } + + dev = kmalloc(sizeof(struct nfhd_device), GFP_KERNEL); + if (!dev) + goto out; + + dev->id = id; + dev->blocks = blocks; + dev->bsize = bsize; + dev->bshift = ffs(bsize) - 10; + + dev->queue = blk_alloc_queue(GFP_KERNEL); + if (dev->queue == NULL) + goto free_dev; + + dev->queue->queuedata = dev; + blk_queue_make_request(dev->queue, nfhd_make_request); + blk_queue_logical_block_size(dev->queue, bsize); + + dev->disk = alloc_disk(16); + if (!dev->disk) + goto free_queue; + + dev->disk->major = major_num; + dev->disk->first_minor = dev_id * 16; + dev->disk->fops = &nfhd_ops; + dev->disk->private_data = dev; + sprintf(dev->disk->disk_name, "nfhd%u", dev_id); + set_capacity(dev->disk, (sector_t)blocks * (bsize / 512)); + dev->disk->queue = dev->queue; + + add_disk(dev->disk); + + list_add_tail(&dev->list, &nfhd_list); + + return 0; + +free_queue: + blk_cleanup_queue(dev->queue); +free_dev: + kfree(dev); +out: + return -ENOMEM; +} + +static int __init nfhd_init(void) +{ + u32 blocks, bsize; + int i; + + nfhd_id = nf_get_id("XHDI"); + if (!nfhd_id) + return -ENODEV; + + major_num = register_blkdev(major_num, "nfhd"); + if (major_num <= 0) { + pr_warn("nfhd: unable to get major number\n"); + return major_num; + } + + for (i = NFHD_DEV_OFFSET; i < 24; i++) { + if (nfhd_get_capacity(i, 0, &blocks, &bsize)) + continue; + nfhd_init_one(i, blocks, bsize); + } + + return 0; +} + +static void __exit nfhd_exit(void) +{ + struct nfhd_device *dev, *next; + + list_for_each_entry_safe(dev, next, &nfhd_list, list) { + list_del(&dev->list); + del_gendisk(dev->disk); + put_disk(dev->disk); + blk_cleanup_queue(dev->queue); + kfree(dev); + } + unregister_blkdev(major_num, "nfhd"); +} + +module_init(nfhd_init); +module_exit(nfhd_exit); + +MODULE_LICENSE("GPL"); diff --git a/arch/m68k/emu/nfcon.c b/arch/m68k/emu/nfcon.c new file mode 100644 index 000000000000..ab20dc0ff63b --- /dev/null +++ b/arch/m68k/emu/nfcon.c @@ -0,0 +1,162 @@ +/* + * ARAnyM console driver + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/console.h> +#include <linux/tty.h> +#include <linux/tty_driver.h> +#include <linux/tty_flip.h> +#include <linux/slab.h> +#include <linux/err.h> +#include <linux/uaccess.h> + +#include <asm/natfeat.h> + +static int stderr_id; +static struct tty_driver *nfcon_tty_driver; + +static void nfputs(const char *str, unsigned int count) +{ + char buf[68]; + + buf[64] = 0; + while (count > 64) { + memcpy(buf, str, 64); + nf_call(stderr_id, buf); + str += 64; + count -= 64; + } + memcpy(buf, str, count); + buf[count] = 0; + nf_call(stderr_id, buf); +} + +static void nfcon_write(struct console *con, const char *str, + unsigned int count) +{ + nfputs(str, count); +} + +static struct tty_driver *nfcon_device(struct console *con, int *index) +{ + *index = 0; + return (con->flags & CON_ENABLED) ? nfcon_tty_driver : NULL; +} + +static struct console nf_console = { + .name = "nfcon", + .write = nfcon_write, + .device = nfcon_device, + .flags = CON_PRINTBUFFER, + .index = -1, +}; + + +static int nfcon_tty_open(struct tty_struct *tty, struct file *filp) +{ + return 0; +} + +static void nfcon_tty_close(struct tty_struct *tty, struct file *filp) +{ +} + +static int nfcon_tty_write(struct tty_struct *tty, const unsigned char *buf, + int count) +{ + nfputs(buf, count); + return count; +} + +static int nfcon_tty_put_char(struct tty_struct *tty, unsigned char ch) +{ + char temp[2] = { ch, 0 }; + + nf_call(stderr_id, temp); + return 1; +} + +static int nfcon_tty_write_room(struct tty_struct *tty) +{ + return 64; +} + +static const struct tty_operations nfcon_tty_ops = { + .open = nfcon_tty_open, + .close = nfcon_tty_close, + .write = nfcon_tty_write, + .put_char = nfcon_tty_put_char, + .write_room = nfcon_tty_write_room, +}; + +#ifndef MODULE + +static int __init nf_debug_setup(char *arg) +{ + if (strcmp(arg, "nfcon")) + return 0; + + stderr_id = nf_get_id("NF_STDERR"); + if (stderr_id) { + nf_console.flags |= CON_ENABLED; + register_console(&nf_console); + } + + return 0; +} + +early_param("debug", nf_debug_setup); + +#endif /* !MODULE */ + +static int __init nfcon_init(void) +{ + int res; + + stderr_id = nf_get_id("NF_STDERR"); + if (!stderr_id) + return -ENODEV; + + nfcon_tty_driver = alloc_tty_driver(1); + if (!nfcon_tty_driver) + return -ENOMEM; + + nfcon_tty_driver->owner = THIS_MODULE; + nfcon_tty_driver->driver_name = "nfcon"; + nfcon_tty_driver->name = "nfcon"; + nfcon_tty_driver->type = TTY_DRIVER_TYPE_SYSTEM; + nfcon_tty_driver->subtype = SYSTEM_TYPE_TTY; + nfcon_tty_driver->init_termios = tty_std_termios; + nfcon_tty_driver->flags = TTY_DRIVER_REAL_RAW; + + tty_set_operations(nfcon_tty_driver, &nfcon_tty_ops); + res = tty_register_driver(nfcon_tty_driver); + if (res) { + pr_err("failed to register nfcon tty driver\n"); + put_tty_driver(nfcon_tty_driver); + return res; + } + + if (!(nf_console.flags & CON_ENABLED)) + register_console(&nf_console); + + return 0; +} + +static void __exit nfcon_exit(void) +{ + unregister_console(&nf_console); + tty_unregister_driver(nfcon_tty_driver); + put_tty_driver(nfcon_tty_driver); +} + +module_init(nfcon_init); +module_exit(nfcon_exit); + +MODULE_LICENSE("GPL"); diff --git a/arch/m68k/emu/nfeth.c b/arch/m68k/emu/nfeth.c new file mode 100644 index 000000000000..8b6e201b2c20 --- /dev/null +++ b/arch/m68k/emu/nfeth.c @@ -0,0 +1,270 @@ +/* + * atari_nfeth.c - ARAnyM ethernet card driver for GNU/Linux + * + * Copyright (c) 2005 Milan Jurik, Petr Stehlik of ARAnyM dev team + * + * Based on ARAnyM driver for FreeMiNT written by Standa Opichal + * + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL), incorporated herein by reference. + */ + +#define DRV_VERSION "0.3" +#define DRV_RELDATE "10/12/2005" + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include <linux/netdevice.h> +#include <linux/etherdevice.h> +#include <linux/module.h> +#include <asm/natfeat.h> +#include <asm/virtconvert.h> + +enum { + GET_VERSION = 0,/* no parameters, return NFAPI_VERSION in d0 */ + XIF_INTLEVEL, /* no parameters, return Interrupt Level in d0 */ + XIF_IRQ, /* acknowledge interrupt from host */ + XIF_START, /* (ethX), called on 'ifup', start receiver thread */ + XIF_STOP, /* (ethX), called on 'ifdown', stop the thread */ + XIF_READLENGTH, /* (ethX), return size of network data block to read */ + XIF_READBLOCK, /* (ethX, buffer, size), read block of network data */ + XIF_WRITEBLOCK, /* (ethX, buffer, size), write block of network data */ + XIF_GET_MAC, /* (ethX, buffer, size), return MAC HW addr in buffer */ + XIF_GET_IPHOST, /* (ethX, buffer, size), return IP address of host */ + XIF_GET_IPATARI,/* (ethX, buffer, size), return IP address of atari */ + XIF_GET_NETMASK /* (ethX, buffer, size), return IP netmask */ +}; + +#define MAX_UNIT 8 + +/* These identify the driver base version and may not be removed. */ +static const char version[] __devinitdata = + KERN_INFO KBUILD_MODNAME ".c:v" DRV_VERSION " " DRV_RELDATE + " S.Opichal, M.Jurik, P.Stehlik\n" + KERN_INFO " http://aranym.org/\n"; + +MODULE_AUTHOR("Milan Jurik"); +MODULE_DESCRIPTION("Atari NFeth driver"); +MODULE_LICENSE("GPL"); +/* +MODULE_PARM(nfeth_debug, "i"); +MODULE_PARM_DESC(nfeth_debug, "nfeth_debug level (1-2)"); +*/ + + +static long nfEtherID; +static int nfEtherIRQ; + +struct nfeth_private { + int ethX; +}; + +static struct net_device *nfeth_dev[MAX_UNIT]; + +static int nfeth_open(struct net_device *dev) +{ + struct nfeth_private *priv = netdev_priv(dev); + int res; + + res = nf_call(nfEtherID + XIF_START, priv->ethX); + netdev_dbg(dev, "%s: %d\n", __func__, res); + + /* Ready for data */ + netif_start_queue(dev); + + return 0; +} + +static int nfeth_stop(struct net_device *dev) +{ + struct nfeth_private *priv = netdev_priv(dev); + + /* No more data */ + netif_stop_queue(dev); + + nf_call(nfEtherID + XIF_STOP, priv->ethX); + + return 0; +} + +/* + * Read a packet out of the adapter and pass it to the upper layers + */ +static inline void recv_packet(struct net_device *dev) +{ + struct nfeth_private *priv = netdev_priv(dev); + unsigned short pktlen; + struct sk_buff *skb; + + /* read packet length (excluding 32 bit crc) */ + pktlen = nf_call(nfEtherID + XIF_READLENGTH, priv->ethX); + + netdev_dbg(dev, "%s: %u\n", __func__, pktlen); + + if (!pktlen) { + netdev_dbg(dev, "%s: pktlen == 0\n", __func__); + dev->stats.rx_errors++; + return; + } + + skb = dev_alloc_skb(pktlen + 2); + if (!skb) { + netdev_dbg(dev, "%s: out of mem (buf_alloc failed)\n", + __func__); + dev->stats.rx_dropped++; + return; + } + + skb->dev = dev; + skb_reserve(skb, 2); /* 16 Byte align */ + skb_put(skb, pktlen); /* make room */ + nf_call(nfEtherID + XIF_READBLOCK, priv->ethX, virt_to_phys(skb->data), + pktlen); + + skb->protocol = eth_type_trans(skb, dev); + netif_rx(skb); + dev->last_rx = jiffies; + dev->stats.rx_packets++; + dev->stats.rx_bytes += pktlen; + + /* and enqueue packet */ + return; +} + +static irqreturn_t nfeth_interrupt(int irq, void *dev_id) +{ + int i, m, mask; + + mask = nf_call(nfEtherID + XIF_IRQ, 0); + for (i = 0, m = 1; i < MAX_UNIT; m <<= 1, i++) { + if (mask & m && nfeth_dev[i]) { + recv_packet(nfeth_dev[i]); + nf_call(nfEtherID + XIF_IRQ, m); + } + } + return IRQ_HANDLED; +} + +static int nfeth_xmit(struct sk_buff *skb, struct net_device *dev) +{ + unsigned int len; + char *data, shortpkt[ETH_ZLEN]; + struct nfeth_private *priv = netdev_priv(dev); + + data = skb->data; + len = skb->len; + if (len < ETH_ZLEN) { + memset(shortpkt, 0, ETH_ZLEN); + memcpy(shortpkt, data, len); + data = shortpkt; + len = ETH_ZLEN; + } + + netdev_dbg(dev, "%s: send %u bytes\n", __func__, len); + nf_call(nfEtherID + XIF_WRITEBLOCK, priv->ethX, virt_to_phys(data), + len); + + dev->stats.tx_packets++; + dev->stats.tx_bytes += len; + + dev_kfree_skb(skb); + return 0; +} + +static void nfeth_tx_timeout(struct net_device *dev) +{ + dev->stats.tx_errors++; + netif_wake_queue(dev); +} + +static const struct net_device_ops nfeth_netdev_ops = { + .ndo_open = nfeth_open, + .ndo_stop = nfeth_stop, + .ndo_start_xmit = nfeth_xmit, + .ndo_tx_timeout = nfeth_tx_timeout, + .ndo_validate_addr = eth_validate_addr, + .ndo_change_mtu = eth_change_mtu, + .ndo_set_mac_address = eth_mac_addr, +}; + +static struct net_device * __init nfeth_probe(int unit) +{ + struct net_device *dev; + struct nfeth_private *priv; + char mac[ETH_ALEN], host_ip[32], local_ip[32]; + int err; + + if (!nf_call(nfEtherID + XIF_GET_MAC, unit, mac, ETH_ALEN)) + return NULL; + + dev = alloc_etherdev(sizeof(struct nfeth_private)); + if (!dev) + return NULL; + + dev->irq = nfEtherIRQ; + dev->netdev_ops = &nfeth_netdev_ops; + + dev->flags |= NETIF_F_NO_CSUM; + memcpy(dev->dev_addr, mac, ETH_ALEN); + + priv = netdev_priv(dev); + priv->ethX = unit; + + err = register_netdev(dev); + if (err) { + free_netdev(dev); + return NULL; + } + + nf_call(nfEtherID + XIF_GET_IPHOST, unit, + host_ip, sizeof(host_ip)); + nf_call(nfEtherID + XIF_GET_IPATARI, unit, + local_ip, sizeof(local_ip)); + + netdev_info(dev, KBUILD_MODNAME " addr:%s (%s) HWaddr:%pM\n", host_ip, + local_ip, mac); + + return dev; +} + +static int __init nfeth_init(void) +{ + long ver; + int error, i; + + nfEtherID = nf_get_id("ETHERNET"); + if (!nfEtherID) + return -ENODEV; + + ver = nf_call(nfEtherID + GET_VERSION); + pr_info("API %lu\n", ver); + + nfEtherIRQ = nf_call(nfEtherID + XIF_INTLEVEL); + error = request_irq(nfEtherIRQ, nfeth_interrupt, IRQF_SHARED, + "eth emu", nfeth_interrupt); + if (error) { + pr_err("request for irq %d failed %d", nfEtherIRQ, error); + return error; + } + + for (i = 0; i < MAX_UNIT; i++) + nfeth_dev[i] = nfeth_probe(i); + + return 0; +} + +static void __exit nfeth_cleanup(void) +{ + int i; + + for (i = 0; i < MAX_UNIT; i++) { + if (nfeth_dev[i]) { + unregister_netdev(nfeth_dev[0]); + free_netdev(nfeth_dev[0]); + } + } + free_irq(nfEtherIRQ, nfeth_interrupt); +} + +module_init(nfeth_init); +module_exit(nfeth_cleanup); diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h index 213028cbe110..c94557b91448 100644 --- a/arch/m68k/include/asm/coldfire.h +++ b/arch/m68k/include/asm/coldfire.h @@ -14,39 +14,35 @@ /* - * Define master clock frequency. This is essentially done at config - * time now. No point enumerating dozens of possible clock options - * here. Also the peripheral clock (bus clock) divide ratio is set - * at config time too. + * Define master clock frequency. This is done at config time now. + * No point enumerating dozens of possible clock options here. And + * in any case new boards come along from time to time that have yet + * another different clocking frequency. */ #ifdef CONFIG_CLOCK_SET #define MCF_CLK CONFIG_CLOCK_FREQ -#define MCF_BUSCLK (CONFIG_CLOCK_FREQ / CONFIG_CLOCK_DIV) #else #error "Don't know what your ColdFire CPU clock frequency is??" #endif /* - * Define the processor support peripherals base address. - * This is generally setup by the boards start up code. + * Define the processor internal peripherals base address. + * + * The majority of ColdFire parts use an MBAR register to set + * the base address. Some have an IPSBAR register instead, and it + * has slightly different rules on its size and alignment. Some + * parts have fixed addresses and the internal peripherals cannot + * be relocated in the CPU address space. + * + * The value of MBAR or IPSBAR is config time selectable, we no + * longer hard define it here. No MBAR or IPSBAR will be defined if + * this part has a fixed peripheral address map. */ -#define MCF_MBAR 0x10000000 -#define MCF_MBAR2 0x80000000 -#if defined(CONFIG_M54xx) -#define MCF_IPSBAR MCF_MBAR -#elif defined(CONFIG_M520x) -#define MCF_IPSBAR 0xFC000000 -#else -#define MCF_IPSBAR 0x40000000 +#ifdef CONFIG_MBAR +#define MCF_MBAR CONFIG_MBAR #endif - -#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ - defined(CONFIG_M520x) -#undef MCF_MBAR -#define MCF_MBAR MCF_IPSBAR -#elif defined(CONFIG_M532x) -#undef MCF_MBAR -#define MCF_MBAR 0x00000000 +#ifdef CONFIG_IPSBAR +#define MCF_IPSBAR CONFIG_IPSBAR #endif /****************************************************************************/ diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h index 561b03b5ddf8..9015eadd5c00 100644 --- a/arch/m68k/include/asm/m5206sim.h +++ b/arch/m68k/include/asm/m5206sim.h @@ -14,6 +14,7 @@ #define CPU_NAME "COLDFIRE(m5206)" #define CPU_INSTR_PER_JIFFY 3 +#define MCF_BUSCLK MCF_CLK #include <asm/m52xxacr.h> @@ -48,14 +49,14 @@ #define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */ #define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */ -#define MCFSIM_DCRR 0x46 /* DRAM Refresh reg (r/w) */ -#define MCFSIM_DCTR 0x4a /* DRAM Timing reg (r/w) */ -#define MCFSIM_DAR0 0x4c /* DRAM 0 Address reg(r/w) */ -#define MCFSIM_DMR0 0x50 /* DRAM 0 Mask reg (r/w) */ -#define MCFSIM_DCR0 0x57 /* DRAM 0 Control reg (r/w) */ -#define MCFSIM_DAR1 0x58 /* DRAM 1 Address reg (r/w) */ -#define MCFSIM_DMR1 0x5c /* DRAM 1 Mask reg (r/w) */ -#define MCFSIM_DCR1 0x63 /* DRAM 1 Control reg (r/w) */ +#define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */ +#define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */ +#define MCFSIM_DAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */ +#define MCFSIM_DMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */ +#define MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */ +#define MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */ +#define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */ +#define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */ #define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */ #define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */ @@ -89,9 +90,15 @@ #define MCFSIM_PAR 0xcb /* Pin Assignment reg (r/w) */ #endif +#define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */ +#define MCFTIMER_BASE2 (MCF_MBAR + 0x120) /* Base of TIMER2 */ + #define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */ #define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */ +#define MCFDMA_BASE0 (MCF_MBAR + 0x200) /* Base address DMA 0 */ +#define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */ + #if defined(CONFIG_NETtel) #define MCFUART_BASE1 0x180 /* Base address of UART1 */ #define MCFUART_BASE2 0x140 /* Base address of UART2 */ diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h index 88ed8239fe4e..55d5a4c5fe0b 100644 --- a/arch/m68k/include/asm/m520xsim.h +++ b/arch/m68k/include/asm/m520xsim.h @@ -13,13 +13,14 @@ #define CPU_NAME "COLDFIRE(m520x)" #define CPU_INSTR_PER_JIFFY 3 +#define MCF_BUSCLK (MCF_CLK / 2) #include <asm/m52xxacr.h> /* * Define the 520x SIM register set addresses. */ -#define MCFICM_INTC0 0x48000 /* Base for Interrupt Ctrl 0 */ +#define MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */ #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ @@ -35,9 +36,9 @@ * address to the SIMR and CIMR registers (not offsets into IPSBAR). * The 520x family only has a single INTC unit. */ -#define MCFINTC0_SIMR (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_SIMR) -#define MCFINTC0_CIMR (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_CIMR) -#define MCFINTC0_ICR0 (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0) +#define MCFINTC0_SIMR (MCFICM_INTC0 + MCFINTC_SIMR) +#define MCFINTC0_CIMR (MCFICM_INTC0 + MCFINTC_CIMR) +#define MCFINTC0_ICR0 (MCFICM_INTC0 + MCFINTC_ICR0) #define MCFINTC1_SIMR (0) #define MCFINTC1_CIMR (0) #define MCFINTC1_ICR0 (0) @@ -52,19 +53,22 @@ /* * SDRAM configuration registers. */ -#define MCFSIM_SDMR 0x000a8000 /* SDRAM Mode/Extended Mode Register */ -#define MCFSIM_SDCR 0x000a8004 /* SDRAM Control Register */ -#define MCFSIM_SDCFG1 0x000a8008 /* SDRAM Configuration Register 1 */ -#define MCFSIM_SDCFG2 0x000a800c /* SDRAM Configuration Register 2 */ -#define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */ -#define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */ +#define MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */ +#define MCFSIM_SDCR 0xFC0a8004 /* SDRAM Control Register */ +#define MCFSIM_SDCFG1 0xFC0a8008 /* SDRAM Configuration Register 1 */ +#define MCFSIM_SDCFG2 0xFC0a800c /* SDRAM Configuration Register 2 */ +#define MCFSIM_SDCS0 0xFC0a8110 /* SDRAM Chip Select 0 Configuration */ +#define MCFSIM_SDCS1 0xFC0a8114 /* SDRAM Chip Select 1 Configuration */ /* * EPORT and GPIO registers. */ +#define MCFEPORT_EPPAR 0xFC088000 #define MCFEPORT_EPDDR 0xFC088002 +#define MCFEPORT_EPIER 0xFC088003 #define MCFEPORT_EPDR 0xFC088004 #define MCFEPORT_EPPDR 0xFC088005 +#define MCFEPORT_EPFR 0xFC088006 #define MCFGPIO_PODR_BUSCTL 0xFC0A4000 #define MCFGPIO_PODR_BE 0xFC0A4001 @@ -119,10 +123,10 @@ #define MCFGPIO_IRQ_MAX 8 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE -#define MCF_GPIO_PAR_UART (0xA4036) -#define MCF_GPIO_PAR_FECI2C (0xA4033) -#define MCF_GPIO_PAR_QSPI (0xA4034) -#define MCF_GPIO_PAR_FEC (0xA4038) +#define MCF_GPIO_PAR_UART 0xFC0A4036 +#define MCF_GPIO_PAR_FECI2C 0xFC0A4033 +#define MCF_GPIO_PAR_QSPI 0xFC0A4034 +#define MCF_GPIO_PAR_FEC 0xFC0A4038 #define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001) #define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002) @@ -134,11 +138,23 @@ #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) /* + * PIT timer module. + */ +#define MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */ +#define MCFPIT_BASE2 0xFC084000 /* Base address of TIMER2 */ + +/* * UART module. */ -#define MCFUART_BASE1 0x60000 /* Base address of UART1 */ -#define MCFUART_BASE2 0x64000 /* Base address of UART2 */ -#define MCFUART_BASE3 0x68000 /* Base address of UART2 */ +#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */ +#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */ +#define MCFUART_BASE3 0xFC068000 /* Base address of UART2 */ + +/* + * FEC module. + */ +#define MCFFEC_BASE 0xFC030000 /* Base of FEC ethernet */ +#define MCFFEC_SIZE 0x800 /* Register set size */ /* * Reset Controll Unit. diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h index 4ad7a00257a8..8996df62ede4 100644 --- a/arch/m68k/include/asm/m523xsim.h +++ b/arch/m68k/include/asm/m523xsim.h @@ -13,14 +13,16 @@ #define CPU_NAME "COLDFIRE(m523x)" #define CPU_INSTR_PER_JIFFY 3 +#define MCF_BUSCLK (MCF_CLK / 2) #include <asm/m52xxacr.h> /* * Define the 523x SIM register set addresses. */ -#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ -#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */ +#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ +#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */ + #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ @@ -39,11 +41,11 @@ /* * SDRAM configuration registers. */ -#define MCFSIM_DCR 0x44 /* SDRAM control */ -#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ -#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ -#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ -#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ +#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */ +#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */ +#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */ +#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */ +#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */ /* * Reset Controll Unit (relative to IPSBAR). @@ -57,10 +59,19 @@ /* * UART module. */ -#define MCFUART_BASE1 0x200 /* Base address of UART1 */ -#define MCFUART_BASE2 0x240 /* Base address of UART2 */ -#define MCFUART_BASE3 0x280 /* Base address of UART3 */ +#define MCFUART_BASE1 (MCF_IPSBAR + 0x200) +#define MCFUART_BASE2 (MCF_IPSBAR + 0x240) +#define MCFUART_BASE3 (MCF_IPSBAR + 0x280) + +/* + * FEC ethernet module. + */ +#define MCFFEC_BASE (MCF_IPSBAR + 0x1000) +#define MCFFEC_SIZE 0x800 +/* + * GPIO module. + */ #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) #define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) @@ -118,12 +129,22 @@ #define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C) /* - * EPort + * PIT timer base addresses. */ +#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000) +#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000) +#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000) +#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000) +/* + * EPort + */ +#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000) #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) +#define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003) #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) +#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) /* * Generic GPIO support @@ -143,5 +164,14 @@ */ #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) + +/* + * DMA unit base addresses. + */ +#define MCFDMA_BASE0 (MCF_IPSBAR + 0x100) +#define MCFDMA_BASE1 (MCF_IPSBAR + 0x140) +#define MCFDMA_BASE2 (MCF_IPSBAR + 0x180) +#define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0) + /****************************************************************************/ #endif /* m523xsim_h */ diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h index 4908b118f2fd..805714ca8d7d 100644 --- a/arch/m68k/include/asm/m5249sim.h +++ b/arch/m68k/include/asm/m5249sim.h @@ -13,10 +13,16 @@ #define CPU_NAME "COLDFIRE(m5249)" #define CPU_INSTR_PER_JIFFY 3 +#define MCF_BUSCLK (MCF_CLK / 2) #include <asm/m52xxacr.h> /* + * The 5249 has a second MBAR region, define its address. + */ +#define MCF_MBAR2 0x80000000 + +/* * Define the 5249 SIM register set addresses. */ #define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ @@ -55,11 +61,17 @@ #define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ #define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ -#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ -#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ -#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ +#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ +#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ +#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */ +#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */ +#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */ + +/* + * Timer module. + */ +#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ +#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ /* * UART module. @@ -68,6 +80,14 @@ #define MCFUART_BASE2 0x200 /* Base address of UART2 */ /* + * DMA unit base addresses. + */ +#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */ +#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */ +#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */ +#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */ + +/* * Some symbol defines for the above... */ #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h index b7cc50abc831..759c2b07a994 100644 --- a/arch/m68k/include/asm/m5272sim.h +++ b/arch/m68k/include/asm/m5272sim.h @@ -14,6 +14,7 @@ #define CPU_NAME "COLDFIRE(m5272)" #define CPU_INSTR_PER_JIFFY 3 +#define MCF_BUSCLK MCF_CLK #include <asm/m52xxacr.h> @@ -80,6 +81,13 @@ #define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */ #define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */ +#define MCFDMA_BASE0 (MCF_MBAR + 0xe0) /* Base address DMA 0 */ + +#define MCFTIMER_BASE1 (MCF_MBAR + 0x200) /* Base address TIMER1 */ +#define MCFTIMER_BASE2 (MCF_MBAR + 0x220) /* Base address TIMER2 */ +#define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */ +#define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */ + /* * Define system peripheral IRQ usage. */ diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h index e8042e8bc003..74855a66c050 100644 --- a/arch/m68k/include/asm/m527xsim.h +++ b/arch/m68k/include/asm/m527xsim.h @@ -13,14 +13,16 @@ #define CPU_NAME "COLDFIRE(m527x)" #define CPU_INSTR_PER_JIFFY 3 +#define MCF_BUSCLK (MCF_CLK / 2) #include <asm/m52xxacr.h> /* * Define the 5270/5271 SIM register set addresses. */ -#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ -#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */ +#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ +#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */ + #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ @@ -42,29 +44,45 @@ * SDRAM configuration registers. */ #ifdef CONFIG_M5271 -#define MCFSIM_DCR 0x40 /* SDRAM control */ -#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ -#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ -#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ -#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ +#define MCFSIM_DCR (MCF_IPSBAR + 0x40) /* Control */ +#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */ +#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */ +#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */ +#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */ #endif #ifdef CONFIG_M5275 -#define MCFSIM_DMR 0x40 /* SDRAM mode */ -#define MCFSIM_DCR 0x44 /* SDRAM control */ -#define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */ -#define MCFSIM_DCFG2 0x4c /* SDRAM configuration 2 */ -#define MCFSIM_DBAR0 0x50 /* SDRAM base address 0 */ -#define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */ -#define MCFSIM_DBAR1 0x58 /* SDRAM base address 1 */ -#define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */ +#define MCFSIM_DMR (MCF_IPSBAR + 0x40) /* Mode */ +#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */ +#define MCFSIM_DCFG1 (MCF_IPSBAR + 0x48) /* Configuration 1 */ +#define MCFSIM_DCFG2 (MCF_IPSBAR + 0x4c) /* Configuration 2 */ +#define MCFSIM_DBAR0 (MCF_IPSBAR + 0x50) /* Base address 0 */ +#define MCFSIM_DMR0 (MCF_IPSBAR + 0x54) /* Address mask 0 */ +#define MCFSIM_DBAR1 (MCF_IPSBAR + 0x58) /* Base address 1 */ +#define MCFSIM_DMR1 (MCF_IPSBAR + 0x5c) /* Address mask 1 */ #endif /* + * DMA unit base addresses. + */ +#define MCFDMA_BASE0 (MCF_IPSBAR + 0x100) +#define MCFDMA_BASE1 (MCF_IPSBAR + 0x140) +#define MCFDMA_BASE2 (MCF_IPSBAR + 0x180) +#define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0) + +/* * UART module. */ -#define MCFUART_BASE1 0x200 /* Base address of UART1 */ -#define MCFUART_BASE2 0x240 /* Base address of UART2 */ -#define MCFUART_BASE3 0x280 /* Base address of UART3 */ +#define MCFUART_BASE1 (MCF_IPSBAR + 0x200) +#define MCFUART_BASE2 (MCF_IPSBAR + 0x240) +#define MCFUART_BASE3 (MCF_IPSBAR + 0x280) + +/* + * FEC ethernet module. + */ +#define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000) +#define MCFFEC_SIZE0 0x800 +#define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800) +#define MCFFEC_SIZE1 0x800 #ifdef CONFIG_M5271 #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) @@ -231,14 +249,22 @@ #endif /* - * EPort + * PIT timer base addresses. */ +#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000) +#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000) +#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000) +#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000) +/* + * EPort + */ +#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000) #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) +#define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003) #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) - - +#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) /* * GPIO pins setups to enable the UARTs. diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h index a6d2f4d9aaa0..d798bd5df56c 100644 --- a/arch/m68k/include/asm/m528xsim.h +++ b/arch/m68k/include/asm/m528xsim.h @@ -13,14 +13,16 @@ #define CPU_NAME "COLDFIRE(m528x)" #define CPU_INSTR_PER_JIFFY 3 +#define MCF_BUSCLK MCF_CLK #include <asm/m52xxacr.h> /* * Define the 5280/5282 SIM register set addresses. */ -#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ -#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */ +#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ +#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */ + #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ @@ -39,18 +41,32 @@ /* * SDRAM configuration registers. */ -#define MCFSIM_DCR 0x44 /* SDRAM control */ -#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ -#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ -#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ -#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ +#define MCFSIM_DCR (MCF_IPSBAR + 0x00000044) /* Control */ +#define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */ +#define MCFSIM_DMR0 (MCF_IPSBAR + 0x0000004c) /* Address mask 0 */ +#define MCFSIM_DACR1 (MCF_IPSBAR + 0x00000050) /* Base address 1 */ +#define MCFSIM_DMR1 (MCF_IPSBAR + 0x00000054) /* Address mask 1 */ + +/* + * DMA unit base addresses. + */ +#define MCFDMA_BASE0 (MCF_IPSBAR + 0x00000100) +#define MCFDMA_BASE1 (MCF_IPSBAR + 0x00000140) +#define MCFDMA_BASE2 (MCF_IPSBAR + 0x00000180) +#define MCFDMA_BASE3 (MCF_IPSBAR + 0x000001C0) /* * UART module. */ -#define MCFUART_BASE1 0x200 /* Base address of UART1 */ -#define MCFUART_BASE2 0x240 /* Base address of UART2 */ -#define MCFUART_BASE3 0x280 /* Base address of UART3 */ +#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000200) +#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000240) +#define MCFUART_BASE3 (MCF_IPSBAR + 0x00000280) + +/* + * FEC ethernet module. + */ +#define MCFFEC_BASE (MCF_IPSBAR + 0x00001000) +#define MCFFEC_SIZE 0x800 /* * GPIO registers @@ -163,6 +179,14 @@ #define MCFGPIO_PUAPAR (MCF_IPSBAR + 0x0010005C) /* + * PIT timer base addresses. + */ +#define MCFPIT_BASE1 (MCF_IPSBAR + 0x00150000) +#define MCFPIT_BASE2 (MCF_IPSBAR + 0x00160000) +#define MCFPIT_BASE3 (MCF_IPSBAR + 0x00170000) +#define MCFPIT_BASE4 (MCF_IPSBAR + 0x00180000) + +/* * Edge Port registers */ #define MCFEPORT_EPPAR (MCF_IPSBAR + 0x00130000) diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h index 0bf57397e7a9..4c94c01f36c4 100644 --- a/arch/m68k/include/asm/m5307sim.h +++ b/arch/m68k/include/asm/m5307sim.h @@ -16,6 +16,7 @@ #define CPU_NAME "COLDFIRE(m5307)" #define CPU_INSTR_PER_JIFFY 3 +#define MCF_BUSCLK (MCF_CLK / 2) #include <asm/m53xxacr.h> @@ -89,16 +90,30 @@ #define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ #endif /* CONFIG_OLDMASK */ -#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ -#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ -#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ +#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ +#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM Addr/Ctrl 0 */ +#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM Mask 0 */ +#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM Addr/Ctrl 1 */ +#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM Mask 1 */ + +/* + * Timer module. + */ +#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ +#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ #define MCFSIM_PADDR (MCF_MBAR + 0x244) #define MCFSIM_PADAT (MCF_MBAR + 0x248) /* + * DMA unit base addresses. + */ +#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */ +#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */ +#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */ +#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */ + +/* * UART module. */ #if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3) diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h index e6470f8ca324..ba4cc784f574 100644 --- a/arch/m68k/include/asm/m532xsim.h +++ b/arch/m68k/include/asm/m532xsim.h @@ -11,6 +11,7 @@ #define CPU_NAME "COLDFIRE(m532x)" #define CPU_INSTR_PER_JIFFY 3 +#define MCF_BUSCLK (MCF_CLK / 3) #include <asm/m53xxacr.h> @@ -85,6 +86,14 @@ #define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */ #define MCFUART_BASE3 0xFC068000 /* Base address of UART3 */ +/* + * Timer module. + */ +#define MCFTIMER_BASE1 0xFC070000 /* Base address of TIMER1 */ +#define MCFTIMER_BASE2 0xFC074000 /* Base address of TIMER2 */ +#define MCFTIMER_BASE3 0xFC078000 /* Base address of TIMER3 */ +#define MCFTIMER_BASE4 0xFC07C000 /* Base address of TIMER4 */ + /********************************************************************* * * Reset Controller Module diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h index 75f5c28a551d..762c58c89050 100644 --- a/arch/m68k/include/asm/m5407sim.h +++ b/arch/m68k/include/asm/m5407sim.h @@ -16,6 +16,7 @@ #define CPU_NAME "COLDFIRE(m5407)" #define CPU_INSTR_PER_JIFFY 3 +#define MCF_BUSCLK (MCF_CLK / 2) #include <asm/m54xxacr.h> @@ -72,11 +73,17 @@ #define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ #define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ -#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ -#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ -#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ +#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ +#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ +#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */ +#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */ +#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */ + +/* + * Timer module. + */ +#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ +#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ #define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ #define MCFUART_BASE2 0x200 /* Base address of UART2 */ @@ -85,6 +92,14 @@ #define MCFSIM_PADAT (MCF_MBAR + 0x248) /* + * DMA unit base addresses. + */ +#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */ +#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */ +#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */ +#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */ + +/* * Generic GPIO support */ #define MCFGPIO_PIN_MAX 16 diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h index 462ae5328441..1ed8bfb02772 100644 --- a/arch/m68k/include/asm/m54xxsim.h +++ b/arch/m68k/include/asm/m54xxsim.h @@ -7,6 +7,7 @@ #define CPU_NAME "COLDFIRE(m54xx)" #define CPU_INSTR_PER_JIFFY 2 +#define MCF_BUSCLK (MCF_CLK / 2) #include <asm/m54xxacr.h> @@ -15,7 +16,8 @@ /* * Interrupt Controller Registers */ -#define MCFICM_INTC0 0x0700 /* Base for Interrupt Ctrl 0 */ +#define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */ + #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ @@ -48,6 +50,16 @@ #define MCFGPIO_IRQ_VECBASE -1 /* + * EDGE Port support. + */ +#define MCFEPORT_EPPAR (MCF_MBAR + 0xf00) /* Pin assignment */ +#define MCFEPORT_EPDDR (MCF_MBAR + 0xf04) /* Data direction */ +#define MCFEPORT_EPIER (MCF_MBAR + 0xf05) /* Interrupt enable */ +#define MCFEPORT_EPDR (MCF_MBAR + 0xf08) /* Port data (w) */ +#define MCFEPORT_EPPDR (MCF_MBAR + 0xf09) /* Port data (r) */ +#define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */ + +/* * Some PSC related definitions */ #define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3)) diff --git a/arch/m68k/include/asm/mcfdma.h b/arch/m68k/include/asm/mcfdma.h index 705c52c79cd8..10bc7e391c14 100644 --- a/arch/m68k/include/asm/mcfdma.h +++ b/arch/m68k/include/asm/mcfdma.h @@ -11,29 +11,6 @@ #define mcfdma_h /****************************************************************************/ - -/* - * Get address specific defines for this Coldfire member. - */ -#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) -#define MCFDMA_BASE0 0x200 /* Base address of DMA 0 */ -#define MCFDMA_BASE1 0x240 /* Base address of DMA 1 */ -#elif defined(CONFIG_M5272) -#define MCFDMA_BASE0 0x0e0 /* Base address of DMA 0 */ -#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) -/* These are relative to the IPSBAR, not MBAR */ -#define MCFDMA_BASE0 0x100 /* Base address of DMA 0 */ -#define MCFDMA_BASE1 0x140 /* Base address of DMA 1 */ -#define MCFDMA_BASE2 0x180 /* Base address of DMA 2 */ -#define MCFDMA_BASE3 0x1C0 /* Base address of DMA 3 */ -#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) -#define MCFDMA_BASE0 0x300 /* Base address of DMA 0 */ -#define MCFDMA_BASE1 0x340 /* Base address of DMA 1 */ -#define MCFDMA_BASE2 0x380 /* Base address of DMA 2 */ -#define MCFDMA_BASE3 0x3C0 /* Base address of DMA 3 */ -#endif - - #if !defined(CONFIG_M5272) /* diff --git a/arch/m68k/include/asm/mcfpit.h b/arch/m68k/include/asm/mcfpit.h index f570cf64fd29..9fd321ca0725 100644 --- a/arch/m68k/include/asm/mcfpit.h +++ b/arch/m68k/include/asm/mcfpit.h @@ -11,22 +11,8 @@ #define mcfpit_h /****************************************************************************/ - -/* - * Get address specific defines for the 5270/5271, 5280/5282, and 5208. - */ -#if defined(CONFIG_M520x) -#define MCFPIT_BASE1 0x00080000 /* Base address of TIMER1 */ -#define MCFPIT_BASE2 0x00084000 /* Base address of TIMER2 */ -#else -#define MCFPIT_BASE1 0x00150000 /* Base address of TIMER1 */ -#define MCFPIT_BASE2 0x00160000 /* Base address of TIMER2 */ -#define MCFPIT_BASE3 0x00170000 /* Base address of TIMER3 */ -#define MCFPIT_BASE4 0x00180000 /* Base address of TIMER4 */ -#endif - /* - * Define the PIT timer register set addresses. + * Define the PIT timer register address offsets. */ #define MCFPIT_PCSR 0x0 /* PIT control register */ #define MCFPIT_PMR 0x2 /* PIT modulus register */ diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h index 0f90f6d2227a..92b276fe8240 100644 --- a/arch/m68k/include/asm/mcftimer.h +++ b/arch/m68k/include/asm/mcftimer.h @@ -12,29 +12,6 @@ #define mcftimer_h /****************************************************************************/ - -/* - * Get address specific defines for this ColdFire member. - */ -#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) -#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */ -#elif defined(CONFIG_M5272) -#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */ -#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */ -#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */ -#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) -#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */ -#elif defined(CONFIG_M532x) -#define MCFTIMER_BASE1 0xfc070000 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0xfc074000 /* Base address of TIMER2 */ -#define MCFTIMER_BASE3 0xfc078000 /* Base address of TIMER3 */ -#define MCFTIMER_BASE4 0xfc07c000 /* Base address of TIMER4 */ -#endif - - /* * Define the TIMER register set addresses. */ diff --git a/arch/m68k/include/asm/natfeat.h b/arch/m68k/include/asm/natfeat.h new file mode 100644 index 000000000000..a3521b80c3b9 --- /dev/null +++ b/arch/m68k/include/asm/natfeat.h @@ -0,0 +1,22 @@ +/* + * ARAnyM hardware support via Native Features (natfeats) + * + * Copyright (c) 2005 Petr Stehlik of ARAnyM dev team + * + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL), incorporated herein by reference. + */ + +#ifndef _NATFEAT_H +#define _NATFEAT_H + +long nf_get_id(const char *feature_name); +long nf_call(long id, ...); + +void nf_init(void); +void nf_shutdown(void); + +void nfprint(const char *fmt, ...) + __attribute__ ((format (printf, 1, 2))); + +# endif /* _NATFEAT_H */ diff --git a/arch/m68k/include/asm/processor.h b/arch/m68k/include/asm/processor.h index 278c69bad57a..f111b02b704f 100644 --- a/arch/m68k/include/asm/processor.h +++ b/arch/m68k/include/asm/processor.h @@ -113,6 +113,8 @@ static inline void start_thread(struct pt_regs * regs, unsigned long pc, wrusp(usp); } +extern int handle_kernel_fault(struct pt_regs *regs); + #else /* diff --git a/arch/m68k/kernel/setup.c b/arch/m68k/kernel/setup.c index b3963ab3d149..334d83640376 100644 --- a/arch/m68k/kernel/setup.c +++ b/arch/m68k/kernel/setup.c @@ -42,6 +42,7 @@ #ifdef CONFIG_SUN3X #include <asm/dvma.h> #endif +#include <asm/natfeat.h> #if !FPSTATESIZE || !NR_IRQS #warning No CPU/platform type selected, your kernel will not work! @@ -324,6 +325,10 @@ void __init setup_arch(char **cmdline_p) panic("No configuration setup"); } +#ifdef CONFIG_NATFEAT + nf_init(); +#endif + paging_init(); #ifndef CONFIG_SUN3 diff --git a/arch/m68k/kernel/signal.c b/arch/m68k/kernel/signal.c index d12c3b0d9e4f..a0afc239304e 100644 --- a/arch/m68k/kernel/signal.c +++ b/arch/m68k/kernel/signal.c @@ -42,6 +42,7 @@ #include <linux/personality.h> #include <linux/tty.h> #include <linux/binfmts.h> +#include <linux/module.h> #include <asm/setup.h> #include <asm/uaccess.h> @@ -51,7 +52,7 @@ #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) -const int frame_extra_sizes[16] = { +static const int frame_extra_sizes[16] = { [1] = -1, /* sizeof(((struct frame *)0)->un.fmt1), */ [2] = sizeof(((struct frame *)0)->un.fmt2), [3] = sizeof(((struct frame *)0)->un.fmt3), @@ -69,6 +70,27 @@ const int frame_extra_sizes[16] = { [15] = -1, /* sizeof(((struct frame *)0)->un.fmtf), */ }; +int handle_kernel_fault(struct pt_regs *regs) +{ + const struct exception_table_entry *fixup; + struct pt_regs *tregs; + + /* Are we prepared to handle this kernel fault? */ + fixup = search_exception_tables(regs->pc); + if (!fixup) + return 0; + + /* Create a new four word stack frame, discarding the old one. */ + regs->stkadj = frame_extra_sizes[regs->format]; + tregs = (struct pt_regs *)((long)regs + regs->stkadj); + tregs->vector = regs->vector; + tregs->format = 0; + tregs->pc = fixup->fixup; + tregs->sr = regs->sr; + + return 1; +} + /* * Atomically swap in the new signal mask, and wait for a signal. */ diff --git a/arch/m68k/kernel/time.c b/arch/m68k/kernel/time.c index 06438dac08ff..18b34ee5db3b 100644 --- a/arch/m68k/kernel/time.c +++ b/arch/m68k/kernel/time.c @@ -37,11 +37,11 @@ static inline int set_rtc_mmss(unsigned long nowtime) /* * timer_interrupt() needs to keep up the real-time clock, - * as well as call the "do_timer()" routine every clocktick + * as well as call the "xtime_update()" routine every clocktick */ static irqreturn_t timer_interrupt(int irq, void *dummy) { - do_timer(1); + xtime_update(1); update_process_times(user_mode(get_irq_regs())); profile_tick(CPU_PROFILING); diff --git a/arch/m68k/kernel/traps.c b/arch/m68k/kernel/traps.c index ada4f4cca811..4022bbc28878 100644 --- a/arch/m68k/kernel/traps.c +++ b/arch/m68k/kernel/traps.c @@ -48,10 +48,7 @@ asmlinkage void nmihandler(void); asmlinkage void fpu_emu(void); #endif -e_vector vectors[256] = { - [VEC_BUSERR] = buserr, - [VEC_SYS] = system_call, -}; +e_vector vectors[256]; /* nmi handler for the Amiga */ asm(".text\n" @@ -61,10 +58,11 @@ asm(".text\n" /* * this must be called very early as the kernel might * use some instruction that are emulated on the 060 + * and so we're prepared for early probe attempts (e.g. nf_init). */ void __init base_trap_init(void) { - if(MACH_IS_SUN3X) { + if (MACH_IS_SUN3X) { extern e_vector *sun3x_prom_vbr; __asm__ volatile ("movec %%vbr, %0" : "=r" (sun3x_prom_vbr)); @@ -79,6 +77,10 @@ void __init base_trap_init(void) vectors[VEC_UNIMPII] = unimp_vec; } + + vectors[VEC_BUSERR] = buserr; + vectors[VEC_ILLEGAL] = trap; + vectors[VEC_SYS] = system_call; } void __init trap_init (void) @@ -1055,9 +1057,11 @@ asmlinkage void trap_c(struct frame *fp) siginfo_t info; if (fp->ptregs.sr & PS_S) { - if ((fp->ptregs.vector >> 2) == VEC_TRACE) { - /* traced a trapping instruction */ - } else + if (fp->ptregs.vector == VEC_TRACE << 2) { + /* traced a trapping instruction on a 68020/30, + * real exception will be executed afterwards. + */ + } else if (!handle_kernel_fault(&fp->ptregs)) bad_super_trap(fp); return; } diff --git a/arch/m68k/math-emu/Makefile b/arch/m68k/math-emu/Makefile index a0935bf98362..547c23c6e40e 100644 --- a/arch/m68k/math-emu/Makefile +++ b/arch/m68k/math-emu/Makefile @@ -2,8 +2,8 @@ # Makefile for the linux kernel. # -#EXTRA_AFLAGS += -DFPU_EMU_DEBUG -#EXTRA_CFLAGS += -DFPU_EMU_DEBUG +#asflags-y := -DFPU_EMU_DEBUG +#ccflags-y := -DFPU_EMU_DEBUG obj-y := fp_entry.o fp_scan.o fp_util.o fp_move.o fp_movem.o \ fp_cond.o fp_arith.o fp_log.o fp_trig.o diff --git a/arch/m68k/mm/fault.c b/arch/m68k/mm/fault.c index a96394a0333d..2db6099784ba 100644 --- a/arch/m68k/mm/fault.c +++ b/arch/m68k/mm/fault.c @@ -18,7 +18,6 @@ #include <asm/pgalloc.h> extern void die_if_kernel(char *, struct pt_regs *, long); -extern const int frame_extra_sizes[]; /* in m68k/kernel/signal.c */ int send_fault_sig(struct pt_regs *regs) { @@ -35,21 +34,8 @@ int send_fault_sig(struct pt_regs *regs) force_sig_info(siginfo.si_signo, &siginfo, current); } else { - const struct exception_table_entry *fixup; - - /* Are we prepared to handle this kernel fault? */ - if ((fixup = search_exception_tables(regs->pc))) { - struct pt_regs *tregs; - /* Create a new four word stack frame, discarding the old - one. */ - regs->stkadj = frame_extra_sizes[regs->format]; - tregs = (struct pt_regs *)((ulong)regs + regs->stkadj); - tregs->vector = regs->vector; - tregs->format = 0; - tregs->pc = fixup->fixup; - tregs->sr = regs->sr; + if (handle_kernel_fault(regs)) return -1; - } //if (siginfo.si_signo == SIGBUS) // force_sig_info(siginfo.si_signo, diff --git a/arch/m68k/mvme147/config.c b/arch/m68k/mvme147/config.c index 100baaa692a1..6cb9c3a9b6c9 100644 --- a/arch/m68k/mvme147/config.c +++ b/arch/m68k/mvme147/config.c @@ -46,8 +46,8 @@ extern void mvme147_reset (void); static int bcd2int (unsigned char b); -/* Save tick handler routine pointer, will point to do_timer() in - * kernel/sched.c, called via mvme147_process_int() */ +/* Save tick handler routine pointer, will point to xtime_update() in + * kernel/time/timekeeping.c, called via mvme147_process_int() */ irq_handler_t tick_handler; diff --git a/arch/m68k/mvme16x/config.c b/arch/m68k/mvme16x/config.c index 11edf61cc2c4..0b28e2621653 100644 --- a/arch/m68k/mvme16x/config.c +++ b/arch/m68k/mvme16x/config.c @@ -51,8 +51,8 @@ extern void mvme16x_reset (void); int bcd2int (unsigned char b); -/* Save tick handler routine pointer, will point to do_timer() in - * kernel/sched.c, called via mvme16x_process_int() */ +/* Save tick handler routine pointer, will point to xtime_update() in + * kernel/time/timekeeping.c, called via mvme16x_process_int() */ static irq_handler_t tick_handler; diff --git a/arch/m68k/sun3/sun3ints.c b/arch/m68k/sun3/sun3ints.c index 2d9e21bd313a..6464ad3ae3e6 100644 --- a/arch/m68k/sun3/sun3ints.c +++ b/arch/m68k/sun3/sun3ints.c @@ -66,7 +66,7 @@ static irqreturn_t sun3_int5(int irq, void *dev_id) #ifdef CONFIG_SUN3 intersil_clear(); #endif - do_timer(1); + xtime_update(1); update_process_times(user_mode(get_irq_regs())); if (!(kstat_cpu(0).irqs[irq] % 20)) sun3_leds(led_pattern[(kstat_cpu(0).irqs[irq] % 160) / 20]); diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig index 8b9dacaa0f6e..b5424cf948e6 100644 --- a/arch/m68knommu/Kconfig +++ b/arch/m68knommu/Kconfig @@ -3,6 +3,7 @@ config M68K default y select HAVE_IDE select HAVE_GENERIC_HARDIRQS + select GENERIC_HARDIRQS_NO_DEPRECATED config MMU bool @@ -78,6 +79,12 @@ config HAVE_CACHE_SPLIT config HAVE_CACHE_CB bool +config HAVE_MBAR + bool + +config HAVE_IPSBAR + bool + source "init/Kconfig" source "kernel/Kconfig.freezer" @@ -111,12 +118,14 @@ config M68360 config M5206 bool "MCF5206" select COLDFIRE_SW_A7 + select HAVE_MBAR help Motorola ColdFire 5206 processor support. config M5206e bool "MCF5206e" select COLDFIRE_SW_A7 + select HAVE_MBAR help Motorola ColdFire 5206e processor support. @@ -131,30 +140,35 @@ config M523x bool "MCF523x" select GENERIC_CLOCKEVENTS select HAVE_CACHE_SPLIT + select HAVE_IPSBAR help Freescale Coldfire 5230/1/2/4/5 processor support config M5249 bool "MCF5249" select COLDFIRE_SW_A7 + select HAVE_MBAR help Motorola ColdFire 5249 processor support. config M5271 bool "MCF5271" select HAVE_CACHE_SPLIT + select HAVE_IPSBAR help Freescale (Motorola) ColdFire 5270/5271 processor support. config M5272 bool "MCF5272" select COLDFIRE_SW_A7 + select HAVE_MBAR help Motorola ColdFire 5272 processor support. config M5275 bool "MCF5275" select HAVE_CACHE_SPLIT + select HAVE_IPSBAR help Freescale (Motorola) ColdFire 5274/5275 processor support. @@ -162,6 +176,7 @@ config M528x bool "MCF528x" select GENERIC_CLOCKEVENTS select HAVE_CACHE_SPLIT + select HAVE_IPSBAR help Motorola ColdFire 5280/5282 processor support. @@ -169,6 +184,7 @@ config M5307 bool "MCF5307" select COLDFIRE_SW_A7 select HAVE_CACHE_CB + select HAVE_MBAR help Motorola ColdFire 5307 processor support. @@ -182,18 +198,21 @@ config M5407 bool "MCF5407" select COLDFIRE_SW_A7 select HAVE_CACHE_CB + select HAVE_MBAR help Motorola ColdFire 5407 processor support. config M547x bool "MCF547x" select HAVE_CACHE_CB + select HAVE_MBAR help Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support. config M548x bool "MCF548x" select HAVE_CACHE_CB + select HAVE_MBAR help Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support. @@ -241,17 +260,6 @@ config CLOCK_FREQ if it is fitted (there are some exceptions). This value will be specific to the exact CPU that you are using. -config CLOCK_DIV - int "Set the core/bus clock divide ratio" - default "1" - depends on CLOCK_SET - help - On many SoC style CPUs the master CPU clock is also used to drive - on-chip peripherals. The clock that is distributed to these - peripherals is sometimes a fixed ratio of the master clock - frequency. If so then set this to the divider ratio of the - master clock to the peripheral clock. If not sure then select 1. - config OLDMASK bool "Old mask 5307 (1H55J) silicon" depends on M5307 @@ -500,6 +508,12 @@ config M5407C3 help Support for the Motorola M5407C3 board. +config FIREBEE + bool "FireBee board support" + depends on M547x + help + Support for the FireBee ColdFire 5475 based board. + config CLEOPATRA bool "Feith CLEOPATRA board support" depends on (M5307 || M5407) @@ -649,6 +663,28 @@ config VECTORBASE platforms this address is programmed into the VBR register, thus actually setting the address to use. +config MBAR + hex "Address of the MBAR (internal peripherals)" + default "0x10000000" + depends on HAVE_MBAR + help + Define the address of the internal system peripherals. This value + is set in the processors MBAR register. This is generally setup by + the boot loader, and will not be written by the kernel. By far most + ColdFire boards use the default 0x10000000 value, so if unsure then + use this. + +config IPSBAR + hex "Address of the IPSBAR (internal peripherals)" + default "0x40000000" + depends on HAVE_IPSBAR + help + Define the address of the internal system peripherals. This value + is set in the processors IPSBAR register. This is generally setup by + the boot loader, and will not be written by the kernel. By far most + ColdFire boards use the default 0x40000000 value, so if unsure then + use this. + config KERNELBASE hex "Address of the base of kernel code" default "0x400" diff --git a/arch/m68knommu/kernel/irq.c b/arch/m68knommu/kernel/irq.c index c9cac36d4422..c7dd48f37bee 100644 --- a/arch/m68knommu/kernel/irq.c +++ b/arch/m68knommu/kernel/irq.c @@ -38,11 +38,13 @@ int show_interrupts(struct seq_file *p, void *v) seq_puts(p, " CPU0\n"); if (irq < NR_IRQS) { - ap = irq_desc[irq].action; + struct irq_desc *desc = irq_to_desc(irq); + + ap = desc->action; if (ap) { seq_printf(p, "%3d: ", irq); seq_printf(p, "%10u ", kstat_irqs(irq)); - seq_printf(p, "%14s ", irq_desc[irq].chip->name); + seq_printf(p, "%14s ", get_irq_desc_chip(desc)->name); seq_printf(p, "%s", ap->name); for (ap = ap->next; ap; ap = ap->next) diff --git a/arch/m68knommu/kernel/time.c b/arch/m68knommu/kernel/time.c index d6ac2a43453c..6623909f70e6 100644 --- a/arch/m68knommu/kernel/time.c +++ b/arch/m68knommu/kernel/time.c @@ -36,7 +36,7 @@ static inline int set_rtc_mmss(unsigned long nowtime) #ifndef CONFIG_GENERIC_CLOCKEVENTS /* * timer_interrupt() needs to keep up the real-time clock, - * as well as call the "do_timer()" routine every clocktick + * as well as call the "xtime_update()" routine every clocktick */ irqreturn_t arch_timer_interrupt(int irq, void *dummy) { @@ -44,11 +44,7 @@ irqreturn_t arch_timer_interrupt(int irq, void *dummy) if (current->pid) profile_tick(CPU_PROFILING); - write_seqlock(&xtime_lock); - - do_timer(1); - - write_sequnlock(&xtime_lock); + xtime_update(1); update_process_times(user_mode(get_irq_regs())); diff --git a/arch/m68knommu/platform/5206/gpio.c b/arch/m68knommu/platform/5206/gpio.c index 60f779ce1651..b9ab4a120f28 100644 --- a/arch/m68knommu/platform/5206/gpio.c +++ b/arch/m68knommu/platform/5206/gpio.c @@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .set = mcf_gpio_set_value, .ngpio = 8, }, - .pddr = MCFSIM_PADDR, - .podr = MCFSIM_PADAT, - .ppdr = MCFSIM_PADAT, + .pddr = (void __iomem *) MCFSIM_PADDR, + .podr = (void __iomem *) MCFSIM_PADAT, + .ppdr = (void __iomem *) MCFSIM_PADAT, }, }; diff --git a/arch/m68knommu/platform/5206e/gpio.c b/arch/m68knommu/platform/5206e/gpio.c index 60f779ce1651..b9ab4a120f28 100644 --- a/arch/m68knommu/platform/5206e/gpio.c +++ b/arch/m68knommu/platform/5206e/gpio.c @@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .set = mcf_gpio_set_value, .ngpio = 8, }, - .pddr = MCFSIM_PADDR, - .podr = MCFSIM_PADAT, - .ppdr = MCFSIM_PADAT, + .pddr = (void __iomem *) MCFSIM_PADDR, + .podr = (void __iomem *) MCFSIM_PADAT, + .ppdr = (void __iomem *) MCFSIM_PADAT, }, }; diff --git a/arch/m68knommu/platform/520x/config.c b/arch/m68knommu/platform/520x/config.c index 71d2ba474c63..621238f1a219 100644 --- a/arch/m68knommu/platform/520x/config.c +++ b/arch/m68knommu/platform/520x/config.c @@ -27,15 +27,15 @@ static struct mcf_platform_uart m520x_uart_platform[] = { { - .mapbase = MCF_MBAR + MCFUART_BASE1, + .mapbase = MCFUART_BASE1, .irq = MCFINT_VECBASE + MCFINT_UART0, }, { - .mapbase = MCF_MBAR + MCFUART_BASE2, + .mapbase = MCFUART_BASE2, .irq = MCFINT_VECBASE + MCFINT_UART1, }, { - .mapbase = MCF_MBAR + MCFUART_BASE3, + .mapbase = MCFUART_BASE3, .irq = MCFINT_VECBASE + MCFINT_UART2, }, { }, @@ -49,8 +49,8 @@ static struct platform_device m520x_uart = { static struct resource m520x_fec_resources[] = { { - .start = MCF_MBAR + 0x30000, - .end = MCF_MBAR + 0x30000 + 0x7ff, + .start = MCFFEC_BASE, + .end = MCFFEC_BASE + MCFFEC_SIZE - 1, .flags = IORESOURCE_MEM, }, { @@ -208,11 +208,11 @@ static void __init m520x_qspi_init(void) { u16 par; /* setup Port QS for QSPI with gpio CS control */ - writeb(0x3f, MCF_IPSBAR + MCF_GPIO_PAR_QSPI); + writeb(0x3f, MCF_GPIO_PAR_QSPI); /* make U1CTS and U2RTS gpio for cs_control */ - par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART); + par = readw(MCF_GPIO_PAR_UART); par &= 0x00ff; - writew(par, MCF_IPSBAR + MCF_GPIO_PAR_UART); + writew(par, MCF_GPIO_PAR_UART); } #endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */ @@ -234,23 +234,23 @@ static void __init m520x_uart_init_line(int line, int irq) switch (line) { case 0: - par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART); + par = readw(MCF_GPIO_PAR_UART); par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | MCF_GPIO_PAR_UART_PAR_URXD0; - writew(par, MCF_IPSBAR + MCF_GPIO_PAR_UART); + writew(par, MCF_GPIO_PAR_UART); break; case 1: - par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART); + par = readw(MCF_GPIO_PAR_UART); par |= MCF_GPIO_PAR_UART_PAR_UTXD1 | MCF_GPIO_PAR_UART_PAR_URXD1; - writew(par, MCF_IPSBAR + MCF_GPIO_PAR_UART); + writew(par, MCF_GPIO_PAR_UART); break; case 2: - par2 = readb(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C); + par2 = readb(MCF_GPIO_PAR_FECI2C); par2 &= ~0x0F; par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 | MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2; - writeb(par2, MCF_IPSBAR + MCF_GPIO_PAR_FECI2C); + writeb(par2, MCF_GPIO_PAR_FECI2C); break; } } @@ -271,11 +271,11 @@ static void __init m520x_fec_init(void) u8 v; /* Set multi-function pins to ethernet mode */ - v = readb(MCF_IPSBAR + MCF_GPIO_PAR_FEC); - writeb(v | 0xf0, MCF_IPSBAR + MCF_GPIO_PAR_FEC); + v = readb(MCF_GPIO_PAR_FEC); + writeb(v | 0xf0, MCF_GPIO_PAR_FEC); - v = readb(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C); - writeb(v | 0x0f, MCF_IPSBAR + MCF_GPIO_PAR_FECI2C); + v = readb(MCF_GPIO_PAR_FECI2C); + writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C); } /***************************************************************************/ diff --git a/arch/m68knommu/platform/520x/gpio.c b/arch/m68knommu/platform/520x/gpio.c index 15b5bb62a698..d757328563d1 100644 --- a/arch/m68knommu/platform/520x/gpio.c +++ b/arch/m68knommu/platform/520x/gpio.c @@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .set = mcf_gpio_set_value, .ngpio = 8, }, - .pddr = MCFEPORT_EPDDR, - .podr = MCFEPORT_EPDR, - .ppdr = MCFEPORT_EPPDR, + .pddr = (void __iomem *) MCFEPORT_EPDDR, + .podr = (void __iomem *) MCFEPORT_EPDR, + .ppdr = (void __iomem *) MCFEPORT_EPPDR, }, { .gpio_chip = { @@ -48,11 +48,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 8, .ngpio = 4, }, - .pddr = MCFGPIO_PDDR_BUSCTL, - .podr = MCFGPIO_PODR_BUSCTL, - .ppdr = MCFGPIO_PPDSDR_BUSCTL, - .setr = MCFGPIO_PPDSDR_BUSCTL, - .clrr = MCFGPIO_PCLRR_BUSCTL, + .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL, + .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, + .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, + .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL, }, { .gpio_chip = { @@ -66,11 +66,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 16, .ngpio = 4, }, - .pddr = MCFGPIO_PDDR_BE, - .podr = MCFGPIO_PODR_BE, - .ppdr = MCFGPIO_PPDSDR_BE, - .setr = MCFGPIO_PPDSDR_BE, - .clrr = MCFGPIO_PCLRR_BE, + .pddr = (void __iomem *) MCFGPIO_PDDR_BE, + .podr = (void __iomem *) MCFGPIO_PODR_BE, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BE, + .setr = (void __iomem *) MCFGPIO_PPDSDR_BE, + .clrr = (void __iomem *) MCFGPIO_PCLRR_BE, }, { .gpio_chip = { @@ -84,11 +84,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 25, .ngpio = 3, }, - .pddr = MCFGPIO_PDDR_CS, - .podr = MCFGPIO_PODR_CS, - .ppdr = MCFGPIO_PPDSDR_CS, - .setr = MCFGPIO_PPDSDR_CS, - .clrr = MCFGPIO_PCLRR_CS, + .pddr = (void __iomem *) MCFGPIO_PDDR_CS, + .podr = (void __iomem *) MCFGPIO_PODR_CS, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS, + .setr = (void __iomem *) MCFGPIO_PPDSDR_CS, + .clrr = (void __iomem *) MCFGPIO_PCLRR_CS, }, { .gpio_chip = { @@ -102,11 +102,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 32, .ngpio = 4, }, - .pddr = MCFGPIO_PDDR_FECI2C, - .podr = MCFGPIO_PODR_FECI2C, - .ppdr = MCFGPIO_PPDSDR_FECI2C, - .setr = MCFGPIO_PPDSDR_FECI2C, - .clrr = MCFGPIO_PCLRR_FECI2C, + .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C, + .podr = (void __iomem *) MCFGPIO_PODR_FECI2C, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, + .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, + .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C, }, { .gpio_chip = { @@ -120,11 +120,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 40, .ngpio = 4, }, - .pddr = MCFGPIO_PDDR_QSPI, - .podr = MCFGPIO_PODR_QSPI, - .ppdr = MCFGPIO_PPDSDR_QSPI, - .setr = MCFGPIO_PPDSDR_QSPI, - .clrr = MCFGPIO_PCLRR_QSPI, + .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI, + .podr = (void __iomem *) MCFGPIO_PODR_QSPI, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, + .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, + .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI, }, { .gpio_chip = { @@ -138,11 +138,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 48, .ngpio = 4, }, - .pddr = MCFGPIO_PDDR_TIMER, - .podr = MCFGPIO_PODR_TIMER, - .ppdr = MCFGPIO_PPDSDR_TIMER, - .setr = MCFGPIO_PPDSDR_TIMER, - .clrr = MCFGPIO_PCLRR_TIMER, + .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER, + .podr = (void __iomem *) MCFGPIO_PODR_TIMER, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER, + .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER, + .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER, }, { .gpio_chip = { @@ -156,11 +156,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 56, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_UART, - .podr = MCFGPIO_PODR_UART, - .ppdr = MCFGPIO_PPDSDR_UART, - .setr = MCFGPIO_PPDSDR_UART, - .clrr = MCFGPIO_PCLRR_UART, + .pddr = (void __iomem *) MCFGPIO_PDDR_UART, + .podr = (void __iomem *) MCFGPIO_PODR_UART, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UART, + .setr = (void __iomem *) MCFGPIO_PPDSDR_UART, + .clrr = (void __iomem *) MCFGPIO_PCLRR_UART, }, { .gpio_chip = { @@ -174,11 +174,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 64, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_FECH, - .podr = MCFGPIO_PODR_FECH, - .ppdr = MCFGPIO_PPDSDR_FECH, - .setr = MCFGPIO_PPDSDR_FECH, - .clrr = MCFGPIO_PCLRR_FECH, + .pddr = (void __iomem *) MCFGPIO_PDDR_FECH, + .podr = (void __iomem *) MCFGPIO_PODR_FECH, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECH, + .setr = (void __iomem *) MCFGPIO_PPDSDR_FECH, + .clrr = (void __iomem *) MCFGPIO_PCLRR_FECH, }, { .gpio_chip = { @@ -192,11 +192,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 72, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_FECL, - .podr = MCFGPIO_PODR_FECL, - .ppdr = MCFGPIO_PPDSDR_FECL, - .setr = MCFGPIO_PPDSDR_FECL, - .clrr = MCFGPIO_PCLRR_FECL, + .pddr = (void __iomem *) MCFGPIO_PDDR_FECL, + .podr = (void __iomem *) MCFGPIO_PODR_FECL, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECL, + .setr = (void __iomem *) MCFGPIO_PPDSDR_FECL, + .clrr = (void __iomem *) MCFGPIO_PCLRR_FECL, }, }; diff --git a/arch/m68knommu/platform/523x/config.c b/arch/m68knommu/platform/523x/config.c index 8980f6d7715a..418a76feb1e3 100644 --- a/arch/m68knommu/platform/523x/config.c +++ b/arch/m68knommu/platform/523x/config.c @@ -28,15 +28,15 @@ static struct mcf_platform_uart m523x_uart_platform[] = { { - .mapbase = MCF_MBAR + MCFUART_BASE1, + .mapbase = MCFUART_BASE1, .irq = MCFINT_VECBASE + MCFINT_UART0, }, { - .mapbase = MCF_MBAR + MCFUART_BASE2, + .mapbase = MCFUART_BASE2, .irq = MCFINT_VECBASE + MCFINT_UART0 + 1, }, { - .mapbase = MCF_MBAR + MCFUART_BASE3, + .mapbase = MCFUART_BASE3, .irq = MCFINT_VECBASE + MCFINT_UART0 + 2, }, { }, @@ -50,8 +50,8 @@ static struct platform_device m523x_uart = { static struct resource m523x_fec_resources[] = { { - .start = MCF_MBAR + 0x1000, - .end = MCF_MBAR + 0x1000 + 0x7ff, + .start = MCFFEC_BASE, + .end = MCFFEC_BASE + MCFFEC_SIZE - 1, .flags = IORESOURCE_MEM, }, { diff --git a/arch/m68knommu/platform/523x/gpio.c b/arch/m68knommu/platform/523x/gpio.c index a8842dc27839..327ebf142c8e 100644 --- a/arch/m68knommu/platform/523x/gpio.c +++ b/arch/m68knommu/platform/523x/gpio.c @@ -33,9 +33,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 1, .ngpio = 7, }, - .pddr = MCFEPORT_EPDDR, - .podr = MCFEPORT_EPDR, - .ppdr = MCFEPORT_EPPDR, + .pddr = (void __iomem *) MCFEPORT_EPDDR, + .podr = (void __iomem *) MCFEPORT_EPDR, + .ppdr = (void __iomem *) MCFEPORT_EPPDR, }, { .gpio_chip = { @@ -49,11 +49,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 13, .ngpio = 3, }, - .pddr = MCFGPIO_PDDR_ADDR, - .podr = MCFGPIO_PODR_ADDR, - .ppdr = MCFGPIO_PPDSDR_ADDR, - .setr = MCFGPIO_PPDSDR_ADDR, - .clrr = MCFGPIO_PCLRR_ADDR, + .pddr = (void __iomem *) MCFGPIO_PDDR_ADDR, + .podr = (void __iomem *) MCFGPIO_PODR_ADDR, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ADDR, + .setr = (void __iomem *) MCFGPIO_PPDSDR_ADDR, + .clrr = (void __iomem *) MCFGPIO_PCLRR_ADDR, }, { .gpio_chip = { @@ -67,11 +67,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 16, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_DATAH, - .podr = MCFGPIO_PODR_DATAH, - .ppdr = MCFGPIO_PPDSDR_DATAH, - .setr = MCFGPIO_PPDSDR_DATAH, - .clrr = MCFGPIO_PCLRR_DATAH, + .pddr = (void __iomem *) MCFGPIO_PDDR_DATAH, + .podr = (void __iomem *) MCFGPIO_PODR_DATAH, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAH, + .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAH, + .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAH, }, { .gpio_chip = { @@ -85,11 +85,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 24, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_DATAL, - .podr = MCFGPIO_PODR_DATAL, - .ppdr = MCFGPIO_PPDSDR_DATAL, - .setr = MCFGPIO_PPDSDR_DATAL, - .clrr = MCFGPIO_PCLRR_DATAL, + .pddr = (void __iomem *) MCFGPIO_PDDR_DATAL, + .podr = (void __iomem *) MCFGPIO_PODR_DATAL, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAL, + .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAL, + .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAL, }, { .gpio_chip = { @@ -103,11 +103,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 32, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_BUSCTL, - .podr = MCFGPIO_PODR_BUSCTL, - .ppdr = MCFGPIO_PPDSDR_BUSCTL, - .setr = MCFGPIO_PPDSDR_BUSCTL, - .clrr = MCFGPIO_PCLRR_BUSCTL, + .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL, + .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, + .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, + .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL, }, { .gpio_chip = { @@ -121,11 +121,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 40, .ngpio = 4, }, - .pddr = MCFGPIO_PDDR_BS, - .podr = MCFGPIO_PODR_BS, - .ppdr = MCFGPIO_PPDSDR_BS, - .setr = MCFGPIO_PPDSDR_BS, - .clrr = MCFGPIO_PCLRR_BS, + .pddr = (void __iomem *) MCFGPIO_PDDR_BS, + .podr = (void __iomem *) MCFGPIO_PODR_BS, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BS, + .setr = (void __iomem *) MCFGPIO_PPDSDR_BS, + .clrr = (void __iomem *) MCFGPIO_PCLRR_BS, }, { .gpio_chip = { @@ -139,11 +139,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 49, .ngpio = 7, }, - .pddr = MCFGPIO_PDDR_CS, - .podr = MCFGPIO_PODR_CS, - .ppdr = MCFGPIO_PPDSDR_CS, - .setr = MCFGPIO_PPDSDR_CS, - .clrr = MCFGPIO_PCLRR_CS, + .pddr = (void __iomem *) MCFGPIO_PDDR_CS, + .podr = (void __iomem *) MCFGPIO_PODR_CS, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS, + .setr = (void __iomem *) MCFGPIO_PPDSDR_CS, + .clrr = (void __iomem *) MCFGPIO_PCLRR_CS, }, { .gpio_chip = { @@ -157,11 +157,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 56, .ngpio = 6, }, - .pddr = MCFGPIO_PDDR_SDRAM, - .podr = MCFGPIO_PODR_SDRAM, - .ppdr = MCFGPIO_PPDSDR_SDRAM, - .setr = MCFGPIO_PPDSDR_SDRAM, - .clrr = MCFGPIO_PCLRR_SDRAM, + .pddr = (void __iomem *) MCFGPIO_PDDR_SDRAM, + .podr = (void __iomem *) MCFGPIO_PODR_SDRAM, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM, + .setr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM, + .clrr = (void __iomem *) MCFGPIO_PCLRR_SDRAM, }, { .gpio_chip = { @@ -175,11 +175,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 64, .ngpio = 4, }, - .pddr = MCFGPIO_PDDR_FECI2C, - .podr = MCFGPIO_PODR_FECI2C, - .ppdr = MCFGPIO_PPDSDR_FECI2C, - .setr = MCFGPIO_PPDSDR_FECI2C, - .clrr = MCFGPIO_PCLRR_FECI2C, + .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C, + .podr = (void __iomem *) MCFGPIO_PODR_FECI2C, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, + .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, + .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C, }, { .gpio_chip = { @@ -193,11 +193,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 72, .ngpio = 2, }, - .pddr = MCFGPIO_PDDR_UARTH, - .podr = MCFGPIO_PODR_UARTH, - .ppdr = MCFGPIO_PPDSDR_UARTH, - .setr = MCFGPIO_PPDSDR_UARTH, - .clrr = MCFGPIO_PCLRR_UARTH, + .pddr = (void __iomem *) MCFGPIO_PDDR_UARTH, + .podr = (void __iomem *) MCFGPIO_PODR_UARTH, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTH, + .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTH, + .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTH, }, { .gpio_chip = { @@ -211,11 +211,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 80, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_UARTL, - .podr = MCFGPIO_PODR_UARTL, - .ppdr = MCFGPIO_PPDSDR_UARTL, - .setr = MCFGPIO_PPDSDR_UARTL, - .clrr = MCFGPIO_PCLRR_UARTL, + .pddr = (void __iomem *) MCFGPIO_PDDR_UARTL, + .podr = (void __iomem *) MCFGPIO_PODR_UARTL, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTL, + .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTL, + .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTL, }, { .gpio_chip = { @@ -229,11 +229,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 88, .ngpio = 5, }, - .pddr = MCFGPIO_PDDR_QSPI, - .podr = MCFGPIO_PODR_QSPI, - .ppdr = MCFGPIO_PPDSDR_QSPI, - .setr = MCFGPIO_PPDSDR_QSPI, - .clrr = MCFGPIO_PCLRR_QSPI, + .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI, + .podr = (void __iomem *) MCFGPIO_PODR_QSPI, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, + .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, + .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI, }, { .gpio_chip = { @@ -247,11 +247,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 96, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_TIMER, - .podr = MCFGPIO_PODR_TIMER, - .ppdr = MCFGPIO_PPDSDR_TIMER, - .setr = MCFGPIO_PPDSDR_TIMER, - .clrr = MCFGPIO_PCLRR_TIMER, + .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER, + .podr = (void __iomem *) MCFGPIO_PODR_TIMER, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER, + .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER, + .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER, }, { .gpio_chip = { @@ -265,11 +265,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 104, .ngpio = 3, }, - .pddr = MCFGPIO_PDDR_ETPU, - .podr = MCFGPIO_PODR_ETPU, - .ppdr = MCFGPIO_PPDSDR_ETPU, - .setr = MCFGPIO_PPDSDR_ETPU, - .clrr = MCFGPIO_PCLRR_ETPU, + .pddr = (void __iomem *) MCFGPIO_PDDR_ETPU, + .podr = (void __iomem *) MCFGPIO_PODR_ETPU, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ETPU, + .setr = (void __iomem *) MCFGPIO_PPDSDR_ETPU, + .clrr = (void __iomem *) MCFGPIO_PCLRR_ETPU, }, }; diff --git a/arch/m68knommu/platform/5249/gpio.c b/arch/m68knommu/platform/5249/gpio.c index c611eab8b3b6..2b56c6ef65bf 100644 --- a/arch/m68knommu/platform/5249/gpio.c +++ b/arch/m68knommu/platform/5249/gpio.c @@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .set = mcf_gpio_set_value, .ngpio = 32, }, - .pddr = MCFSIM2_GPIOENABLE, - .podr = MCFSIM2_GPIOWRITE, - .ppdr = MCFSIM2_GPIOREAD, + .pddr = (void __iomem *) MCFSIM2_GPIOENABLE, + .podr = (void __iomem *) MCFSIM2_GPIOWRITE, + .ppdr = (void __iomem *) MCFSIM2_GPIOREAD, }, { .gpio_chip = { @@ -48,9 +48,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 32, .ngpio = 32, }, - .pddr = MCFSIM2_GPIO1ENABLE, - .podr = MCFSIM2_GPIO1WRITE, - .ppdr = MCFSIM2_GPIO1READ, + .pddr = (void __iomem *) MCFSIM2_GPIO1ENABLE, + .podr = (void __iomem *) MCFSIM2_GPIO1WRITE, + .ppdr = (void __iomem *) MCFSIM2_GPIO1READ, }, }; diff --git a/arch/m68knommu/platform/5249/intc2.c b/arch/m68knommu/platform/5249/intc2.c index c5151f846591..8f4b63e17366 100644 --- a/arch/m68knommu/platform/5249/intc2.c +++ b/arch/m68knommu/platform/5249/intc2.c @@ -17,32 +17,32 @@ #include <asm/coldfire.h> #include <asm/mcfsim.h> -static void intc2_irq_gpio_mask(unsigned int irq) +static void intc2_irq_gpio_mask(struct irq_data *d) { u32 imr; imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); - imr &= ~(0x1 << (irq - MCFINTC2_GPIOIRQ0)); + imr &= ~(0x1 << (d->irq - MCFINTC2_GPIOIRQ0)); writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); } -static void intc2_irq_gpio_unmask(unsigned int irq) +static void intc2_irq_gpio_unmask(struct irq_data *d) { u32 imr; imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); - imr |= (0x1 << (irq - MCFINTC2_GPIOIRQ0)); + imr |= (0x1 << (d->irq - MCFINTC2_GPIOIRQ0)); writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); } -static void intc2_irq_gpio_ack(unsigned int irq) +static void intc2_irq_gpio_ack(struct irq_data *d) { - writel(0x1 << (irq - MCFINTC2_GPIOIRQ0), MCF_MBAR2 + MCFSIM2_GPIOINTCLEAR); + writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCF_MBAR2 + MCFSIM2_GPIOINTCLEAR); } static struct irq_chip intc2_irq_gpio_chip = { .name = "CF-INTC2", - .mask = intc2_irq_gpio_mask, - .unmask = intc2_irq_gpio_unmask, - .ack = intc2_irq_gpio_ack, + .irq_mask = intc2_irq_gpio_mask, + .irq_unmask = intc2_irq_gpio_unmask, + .irq_ack = intc2_irq_gpio_ack, }; static int __init mcf_intc2_init(void) @@ -51,7 +51,7 @@ static int __init mcf_intc2_init(void) /* GPIO interrupt sources */ for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++) { - irq_desc[irq].chip = &intc2_irq_gpio_chip; + set_irq_chip(irq, &intc2_irq_gpio_chip); set_irq_handler(irq, handle_edge_irq); } diff --git a/arch/m68knommu/platform/5272/gpio.c b/arch/m68knommu/platform/5272/gpio.c index 459db89a89cc..57ac10a5d7f7 100644 --- a/arch/m68knommu/platform/5272/gpio.c +++ b/arch/m68knommu/platform/5272/gpio.c @@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .set = mcf_gpio_set_value, .ngpio = 16, }, - .pddr = MCFSIM_PADDR, - .podr = MCFSIM_PADAT, - .ppdr = MCFSIM_PADAT, + .pddr = (void __iomem *) MCFSIM_PADDR, + .podr = (void __iomem *) MCFSIM_PADAT, + .ppdr = (void __iomem *) MCFSIM_PADAT, }, { .gpio_chip = { @@ -48,9 +48,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 16, .ngpio = 16, }, - .pddr = MCFSIM_PBDDR, - .podr = MCFSIM_PBDAT, - .ppdr = MCFSIM_PBDAT, + .pddr = (void __iomem *) MCFSIM_PBDDR, + .podr = (void __iomem *) MCFSIM_PBDAT, + .ppdr = (void __iomem *) MCFSIM_PBDAT, }, { .gpio_chip = { @@ -64,9 +64,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 32, .ngpio = 16, }, - .pddr = MCFSIM_PCDDR, - .podr = MCFSIM_PCDAT, - .ppdr = MCFSIM_PCDAT, + .pddr = (void __iomem *) MCFSIM_PCDDR, + .podr = (void __iomem *) MCFSIM_PCDAT, + .ppdr = (void __iomem *) MCFSIM_PCDAT, }, }; diff --git a/arch/m68knommu/platform/5272/intc.c b/arch/m68knommu/platform/5272/intc.c index 3cf681c177aa..969ff0a467c6 100644 --- a/arch/m68knommu/platform/5272/intc.c +++ b/arch/m68knommu/platform/5272/intc.c @@ -78,8 +78,10 @@ static struct irqmap intc_irqmap[MCFINT_VECMAX - MCFINT_VECBASE] = { * an interrupt on this irq (for the external irqs). So this mask function * is also an ack_mask function. */ -static void intc_irq_mask(unsigned int irq) +static void intc_irq_mask(struct irq_data *d) { + unsigned int irq = d->irq; + if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { u32 v; irq -= MCFINT_VECBASE; @@ -88,8 +90,10 @@ static void intc_irq_mask(unsigned int irq) } } -static void intc_irq_unmask(unsigned int irq) +static void intc_irq_unmask(struct irq_data *d) { + unsigned int irq = d->irq; + if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { u32 v; irq -= MCFINT_VECBASE; @@ -98,8 +102,10 @@ static void intc_irq_unmask(unsigned int irq) } } -static void intc_irq_ack(unsigned int irq) +static void intc_irq_ack(struct irq_data *d) { + unsigned int irq = d->irq; + /* Only external interrupts are acked */ if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { irq -= MCFINT_VECBASE; @@ -113,8 +119,10 @@ static void intc_irq_ack(unsigned int irq) } } -static int intc_irq_set_type(unsigned int irq, unsigned int type) +static int intc_irq_set_type(struct irq_data *d, unsigned int type) { + unsigned int irq = d->irq; + if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { irq -= MCFINT_VECBASE; if (intc_irqmap[irq].ack) { @@ -137,20 +145,17 @@ static int intc_irq_set_type(unsigned int irq, unsigned int type) */ static void intc_external_irq(unsigned int irq, struct irq_desc *desc) { - kstat_incr_irqs_this_cpu(irq, desc); - desc->status |= IRQ_INPROGRESS; - desc->chip->ack(irq); - handle_IRQ_event(irq, desc->action); - desc->status &= ~IRQ_INPROGRESS; + get_irq_desc_chip(desc)->irq_ack(&desc->irq_data); + handle_simple_irq(irq, desc); } static struct irq_chip intc_irq_chip = { .name = "CF-INTC", - .mask = intc_irq_mask, - .unmask = intc_irq_unmask, - .mask_ack = intc_irq_mask, - .ack = intc_irq_ack, - .set_type = intc_irq_set_type, + .irq_mask = intc_irq_mask, + .irq_unmask = intc_irq_unmask, + .irq_mask_ack = intc_irq_mask, + .irq_ack = intc_irq_ack, + .irq_set_type = intc_irq_set_type, }; void __init init_IRQ(void) diff --git a/arch/m68knommu/platform/527x/config.c b/arch/m68knommu/platform/527x/config.c index 3d9c35c98b98..fa359593b613 100644 --- a/arch/m68knommu/platform/527x/config.c +++ b/arch/m68knommu/platform/527x/config.c @@ -28,15 +28,15 @@ static struct mcf_platform_uart m527x_uart_platform[] = { { - .mapbase = MCF_MBAR + MCFUART_BASE1, + .mapbase = MCFUART_BASE1, .irq = MCFINT_VECBASE + MCFINT_UART0, }, { - .mapbase = MCF_MBAR + MCFUART_BASE2, + .mapbase = MCFUART_BASE2, .irq = MCFINT_VECBASE + MCFINT_UART1, }, { - .mapbase = MCF_MBAR + MCFUART_BASE3, + .mapbase = MCFUART_BASE3, .irq = MCFINT_VECBASE + MCFINT_UART2, }, { }, @@ -50,8 +50,8 @@ static struct platform_device m527x_uart = { static struct resource m527x_fec0_resources[] = { { - .start = MCF_MBAR + 0x1000, - .end = MCF_MBAR + 0x1000 + 0x7ff, + .start = MCFFEC_BASE0, + .end = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1, .flags = IORESOURCE_MEM, }, { @@ -73,8 +73,8 @@ static struct resource m527x_fec0_resources[] = { static struct resource m527x_fec1_resources[] = { { - .start = MCF_MBAR + 0x1800, - .end = MCF_MBAR + 0x1800 + 0x7ff, + .start = MCFFEC_BASE1, + .end = MCFFEC_BASE1 + MCFFEC_SIZE1 - 1, .flags = IORESOURCE_MEM, }, { diff --git a/arch/m68knommu/platform/527x/gpio.c b/arch/m68knommu/platform/527x/gpio.c index 0b56e19db0f8..205da0aa0f2d 100644 --- a/arch/m68knommu/platform/527x/gpio.c +++ b/arch/m68knommu/platform/527x/gpio.c @@ -34,9 +34,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 1, .ngpio = 7, }, - .pddr = MCFEPORT_EPDDR, - .podr = MCFEPORT_EPDR, - .ppdr = MCFEPORT_EPPDR, + .pddr = (void __iomem *) MCFEPORT_EPDDR, + .podr = (void __iomem *) MCFEPORT_EPDR, + .ppdr = (void __iomem *) MCFEPORT_EPPDR, }, { .gpio_chip = { @@ -50,11 +50,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 13, .ngpio = 3, }, - .pddr = MCFGPIO_PDDR_ADDR, - .podr = MCFGPIO_PODR_ADDR, - .ppdr = MCFGPIO_PPDSDR_ADDR, - .setr = MCFGPIO_PPDSDR_ADDR, - .clrr = MCFGPIO_PCLRR_ADDR, + .pddr = (void __iomem *) MCFGPIO_PDDR_ADDR, + .podr = (void __iomem *) MCFGPIO_PODR_ADDR, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ADDR, + .setr = (void __iomem *) MCFGPIO_PPDSDR_ADDR, + .clrr = (void __iomem *) MCFGPIO_PCLRR_ADDR, }, { .gpio_chip = { @@ -68,11 +68,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 16, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_DATAH, - .podr = MCFGPIO_PODR_DATAH, - .ppdr = MCFGPIO_PPDSDR_DATAH, - .setr = MCFGPIO_PPDSDR_DATAH, - .clrr = MCFGPIO_PCLRR_DATAH, + .pddr = (void __iomem *) MCFGPIO_PDDR_DATAH, + .podr = (void __iomem *) MCFGPIO_PODR_DATAH, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAH, + .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAH, + .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAH, }, { .gpio_chip = { @@ -86,11 +86,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 24, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_DATAL, - .podr = MCFGPIO_PODR_DATAL, - .ppdr = MCFGPIO_PPDSDR_DATAL, - .setr = MCFGPIO_PPDSDR_DATAL, - .clrr = MCFGPIO_PCLRR_DATAL, + .pddr = (void __iomem *) MCFGPIO_PDDR_DATAL, + .podr = (void __iomem *) MCFGPIO_PODR_DATAL, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAL, + .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAL, + .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAL, }, { .gpio_chip = { @@ -104,11 +104,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 32, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_BUSCTL, - .podr = MCFGPIO_PODR_BUSCTL, - .ppdr = MCFGPIO_PPDSDR_BUSCTL, - .setr = MCFGPIO_PPDSDR_BUSCTL, - .clrr = MCFGPIO_PCLRR_BUSCTL, + .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL, + .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, + .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, + .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL, }, { .gpio_chip = { @@ -122,11 +122,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 40, .ngpio = 4, }, - .pddr = MCFGPIO_PDDR_BS, - .podr = MCFGPIO_PODR_BS, - .ppdr = MCFGPIO_PPDSDR_BS, - .setr = MCFGPIO_PPDSDR_BS, - .clrr = MCFGPIO_PCLRR_BS, + .pddr = (void __iomem *) MCFGPIO_PDDR_BS, + .podr = (void __iomem *) MCFGPIO_PODR_BS, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BS, + .setr = (void __iomem *) MCFGPIO_PPDSDR_BS, + .clrr = (void __iomem *) MCFGPIO_PCLRR_BS, }, { .gpio_chip = { @@ -140,11 +140,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 49, .ngpio = 7, }, - .pddr = MCFGPIO_PDDR_CS, - .podr = MCFGPIO_PODR_CS, - .ppdr = MCFGPIO_PPDSDR_CS, - .setr = MCFGPIO_PPDSDR_CS, - .clrr = MCFGPIO_PCLRR_CS, + .pddr = (void __iomem *) MCFGPIO_PDDR_CS, + .podr = (void __iomem *) MCFGPIO_PODR_CS, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS, + .setr = (void __iomem *) MCFGPIO_PPDSDR_CS, + .clrr = (void __iomem *) MCFGPIO_PCLRR_CS, }, { .gpio_chip = { @@ -158,11 +158,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 56, .ngpio = 6, }, - .pddr = MCFGPIO_PDDR_SDRAM, - .podr = MCFGPIO_PODR_SDRAM, - .ppdr = MCFGPIO_PPDSDR_SDRAM, - .setr = MCFGPIO_PPDSDR_SDRAM, - .clrr = MCFGPIO_PCLRR_SDRAM, + .pddr = (void __iomem *) MCFGPIO_PDDR_SDRAM, + .podr = (void __iomem *) MCFGPIO_PODR_SDRAM, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM, + .setr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM, + .clrr = (void __iomem *) MCFGPIO_PCLRR_SDRAM, }, { .gpio_chip = { @@ -176,11 +176,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 64, .ngpio = 4, }, - .pddr = MCFGPIO_PDDR_FECI2C, - .podr = MCFGPIO_PODR_FECI2C, - .ppdr = MCFGPIO_PPDSDR_FECI2C, - .setr = MCFGPIO_PPDSDR_FECI2C, - .clrr = MCFGPIO_PCLRR_FECI2C, + .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C, + .podr = (void __iomem *) MCFGPIO_PODR_FECI2C, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, + .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, + .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C, }, { .gpio_chip = { @@ -194,11 +194,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 72, .ngpio = 2, }, - .pddr = MCFGPIO_PDDR_UARTH, - .podr = MCFGPIO_PODR_UARTH, - .ppdr = MCFGPIO_PPDSDR_UARTH, - .setr = MCFGPIO_PPDSDR_UARTH, - .clrr = MCFGPIO_PCLRR_UARTH, + .pddr = (void __iomem *) MCFGPIO_PDDR_UARTH, + .podr = (void __iomem *) MCFGPIO_PODR_UARTH, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTH, + .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTH, + .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTH, }, { .gpio_chip = { @@ -212,11 +212,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 80, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_UARTL, - .podr = MCFGPIO_PODR_UARTL, - .ppdr = MCFGPIO_PPDSDR_UARTL, - .setr = MCFGPIO_PPDSDR_UARTL, - .clrr = MCFGPIO_PCLRR_UARTL, + .pddr = (void __iomem *) MCFGPIO_PDDR_UARTL, + .podr = (void __iomem *) MCFGPIO_PODR_UARTL, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTL, + .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTL, + .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTL, }, { .gpio_chip = { @@ -230,11 +230,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 88, .ngpio = 5, }, - .pddr = MCFGPIO_PDDR_QSPI, - .podr = MCFGPIO_PODR_QSPI, - .ppdr = MCFGPIO_PPDSDR_QSPI, - .setr = MCFGPIO_PPDSDR_QSPI, - .clrr = MCFGPIO_PCLRR_QSPI, + .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI, + .podr = (void __iomem *) MCFGPIO_PODR_QSPI, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, + .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, + .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI, }, { .gpio_chip = { @@ -248,11 +248,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 96, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_TIMER, - .podr = MCFGPIO_PODR_TIMER, - .ppdr = MCFGPIO_PPDSDR_TIMER, - .setr = MCFGPIO_PPDSDR_TIMER, - .clrr = MCFGPIO_PCLRR_TIMER, + .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER, + .podr = (void __iomem *) MCFGPIO_PODR_TIMER, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER, + .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER, + .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER, }, #elif defined(CONFIG_M5275) { @@ -267,9 +267,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 1, .ngpio = 7, }, - .pddr = MCFEPORT_EPDDR, - .podr = MCFEPORT_EPDR, - .ppdr = MCFEPORT_EPPDR, + .pddr = (void __iomem *) MCFEPORT_EPDDR, + .podr = (void __iomem *) MCFEPORT_EPDR, + .ppdr = (void __iomem *) MCFEPORT_EPPDR, }, { .gpio_chip = { @@ -283,11 +283,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 8, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_BUSCTL, - .podr = MCFGPIO_PODR_BUSCTL, - .ppdr = MCFGPIO_PPDSDR_BUSCTL, - .setr = MCFGPIO_PPDSDR_BUSCTL, - .clrr = MCFGPIO_PCLRR_BUSCTL, + .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL, + .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, + .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, + .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL, }, { .gpio_chip = { @@ -301,11 +301,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 21, .ngpio = 3, }, - .pddr = MCFGPIO_PDDR_ADDR, - .podr = MCFGPIO_PODR_ADDR, - .ppdr = MCFGPIO_PPDSDR_ADDR, - .setr = MCFGPIO_PPDSDR_ADDR, - .clrr = MCFGPIO_PCLRR_ADDR, + .pddr = (void __iomem *) MCFGPIO_PDDR_ADDR, + .podr = (void __iomem *) MCFGPIO_PODR_ADDR, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ADDR, + .setr = (void __iomem *) MCFGPIO_PPDSDR_ADDR, + .clrr = (void __iomem *) MCFGPIO_PCLRR_ADDR, }, { .gpio_chip = { @@ -319,11 +319,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 25, .ngpio = 7, }, - .pddr = MCFGPIO_PDDR_CS, - .podr = MCFGPIO_PODR_CS, - .ppdr = MCFGPIO_PPDSDR_CS, - .setr = MCFGPIO_PPDSDR_CS, - .clrr = MCFGPIO_PCLRR_CS, + .pddr = (void __iomem *) MCFGPIO_PDDR_CS, + .podr = (void __iomem *) MCFGPIO_PODR_CS, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS, + .setr = (void __iomem *) MCFGPIO_PPDSDR_CS, + .clrr = (void __iomem *) MCFGPIO_PCLRR_CS, }, { .gpio_chip = { @@ -337,11 +337,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 32, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_FEC0H, - .podr = MCFGPIO_PODR_FEC0H, - .ppdr = MCFGPIO_PPDSDR_FEC0H, - .setr = MCFGPIO_PPDSDR_FEC0H, - .clrr = MCFGPIO_PCLRR_FEC0H, + .pddr = (void __iomem *) MCFGPIO_PDDR_FEC0H, + .podr = (void __iomem *) MCFGPIO_PODR_FEC0H, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC0H, + .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC0H, + .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC0H, }, { .gpio_chip = { @@ -355,11 +355,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 40, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_FEC0L, - .podr = MCFGPIO_PODR_FEC0L, - .ppdr = MCFGPIO_PPDSDR_FEC0L, - .setr = MCFGPIO_PPDSDR_FEC0L, - .clrr = MCFGPIO_PCLRR_FEC0L, + .pddr = (void __iomem *) MCFGPIO_PDDR_FEC0L, + .podr = (void __iomem *) MCFGPIO_PODR_FEC0L, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC0L, + .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC0L, + .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC0L, }, { .gpio_chip = { @@ -373,11 +373,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 48, .ngpio = 6, }, - .pddr = MCFGPIO_PDDR_FECI2C, - .podr = MCFGPIO_PODR_FECI2C, - .ppdr = MCFGPIO_PPDSDR_FECI2C, - .setr = MCFGPIO_PPDSDR_FECI2C, - .clrr = MCFGPIO_PCLRR_FECI2C, + .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C, + .podr = (void __iomem *) MCFGPIO_PODR_FECI2C, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, + .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, + .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C, }, { .gpio_chip = { @@ -391,11 +391,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 56, .ngpio = 7, }, - .pddr = MCFGPIO_PDDR_QSPI, - .podr = MCFGPIO_PODR_QSPI, - .ppdr = MCFGPIO_PPDSDR_QSPI, - .setr = MCFGPIO_PPDSDR_QSPI, - .clrr = MCFGPIO_PCLRR_QSPI, + .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI, + .podr = (void __iomem *) MCFGPIO_PODR_QSPI, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, + .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, + .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI, }, { .gpio_chip = { @@ -409,11 +409,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 64, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_SDRAM, - .podr = MCFGPIO_PODR_SDRAM, - .ppdr = MCFGPIO_PPDSDR_SDRAM, - .setr = MCFGPIO_PPDSDR_SDRAM, - .clrr = MCFGPIO_PCLRR_SDRAM, + .pddr = (void __iomem *) MCFGPIO_PDDR_SDRAM, + .podr = (void __iomem *) MCFGPIO_PODR_SDRAM, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM, + .setr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM, + .clrr = (void __iomem *) MCFGPIO_PCLRR_SDRAM, }, { .gpio_chip = { @@ -427,11 +427,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 72, .ngpio = 4, }, - .pddr = MCFGPIO_PDDR_TIMERH, - .podr = MCFGPIO_PODR_TIMERH, - .ppdr = MCFGPIO_PPDSDR_TIMERH, - .setr = MCFGPIO_PPDSDR_TIMERH, - .clrr = MCFGPIO_PCLRR_TIMERH, + .pddr = (void __iomem *) MCFGPIO_PDDR_TIMERH, + .podr = (void __iomem *) MCFGPIO_PODR_TIMERH, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMERH, + .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMERH, + .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMERH, }, { .gpio_chip = { @@ -445,11 +445,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 80, .ngpio = 4, }, - .pddr = MCFGPIO_PDDR_TIMERL, - .podr = MCFGPIO_PODR_TIMERL, - .ppdr = MCFGPIO_PPDSDR_TIMERL, - .setr = MCFGPIO_PPDSDR_TIMERL, - .clrr = MCFGPIO_PCLRR_TIMERL, + .pddr = (void __iomem *) MCFGPIO_PDDR_TIMERL, + .podr = (void __iomem *) MCFGPIO_PODR_TIMERL, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMERL, + .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMERL, + .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMERL, }, { .gpio_chip = { @@ -463,11 +463,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 88, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_UARTL, - .podr = MCFGPIO_PODR_UARTL, - .ppdr = MCFGPIO_PPDSDR_UARTL, - .setr = MCFGPIO_PPDSDR_UARTL, - .clrr = MCFGPIO_PCLRR_UARTL, + .pddr = (void __iomem *) MCFGPIO_PDDR_UARTL, + .podr = (void __iomem *) MCFGPIO_PODR_UARTL, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTL, + .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTL, + .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTL, }, { .gpio_chip = { @@ -481,11 +481,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 96, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_FEC1H, - .podr = MCFGPIO_PODR_FEC1H, - .ppdr = MCFGPIO_PPDSDR_FEC1H, - .setr = MCFGPIO_PPDSDR_FEC1H, - .clrr = MCFGPIO_PCLRR_FEC1H, + .pddr = (void __iomem *) MCFGPIO_PDDR_FEC1H, + .podr = (void __iomem *) MCFGPIO_PODR_FEC1H, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC1H, + .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC1H, + .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC1H, }, { .gpio_chip = { @@ -499,11 +499,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 104, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_FEC1L, - .podr = MCFGPIO_PODR_FEC1L, - .ppdr = MCFGPIO_PPDSDR_FEC1L, - .setr = MCFGPIO_PPDSDR_FEC1L, - .clrr = MCFGPIO_PCLRR_FEC1L, + .pddr = (void __iomem *) MCFGPIO_PDDR_FEC1L, + .podr = (void __iomem *) MCFGPIO_PODR_FEC1L, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC1L, + .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC1L, + .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC1L, }, { .gpio_chip = { @@ -517,11 +517,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 114, .ngpio = 2, }, - .pddr = MCFGPIO_PDDR_BS, - .podr = MCFGPIO_PODR_BS, - .ppdr = MCFGPIO_PPDSDR_BS, - .setr = MCFGPIO_PPDSDR_BS, - .clrr = MCFGPIO_PCLRR_BS, + .pddr = (void __iomem *) MCFGPIO_PDDR_BS, + .podr = (void __iomem *) MCFGPIO_PODR_BS, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BS, + .setr = (void __iomem *) MCFGPIO_PPDSDR_BS, + .clrr = (void __iomem *) MCFGPIO_PCLRR_BS, }, { .gpio_chip = { @@ -535,11 +535,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 121, .ngpio = 7, }, - .pddr = MCFGPIO_PDDR_IRQ, - .podr = MCFGPIO_PODR_IRQ, - .ppdr = MCFGPIO_PPDSDR_IRQ, - .setr = MCFGPIO_PPDSDR_IRQ, - .clrr = MCFGPIO_PCLRR_IRQ, + .pddr = (void __iomem *) MCFGPIO_PDDR_IRQ, + .podr = (void __iomem *) MCFGPIO_PODR_IRQ, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_IRQ, + .setr = (void __iomem *) MCFGPIO_PPDSDR_IRQ, + .clrr = (void __iomem *) MCFGPIO_PCLRR_IRQ, }, { .gpio_chip = { @@ -553,11 +553,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 128, .ngpio = 1, }, - .pddr = MCFGPIO_PDDR_USBH, - .podr = MCFGPIO_PODR_USBH, - .ppdr = MCFGPIO_PPDSDR_USBH, - .setr = MCFGPIO_PPDSDR_USBH, - .clrr = MCFGPIO_PCLRR_USBH, + .pddr = (void __iomem *) MCFGPIO_PDDR_USBH, + .podr = (void __iomem *) MCFGPIO_PODR_USBH, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_USBH, + .setr = (void __iomem *) MCFGPIO_PPDSDR_USBH, + .clrr = (void __iomem *) MCFGPIO_PCLRR_USBH, }, { .gpio_chip = { @@ -571,11 +571,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 136, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_USBL, - .podr = MCFGPIO_PODR_USBL, - .ppdr = MCFGPIO_PPDSDR_USBL, - .setr = MCFGPIO_PPDSDR_USBL, - .clrr = MCFGPIO_PCLRR_USBL, + .pddr = (void __iomem *) MCFGPIO_PDDR_USBL, + .podr = (void __iomem *) MCFGPIO_PODR_USBL, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_USBL, + .setr = (void __iomem *) MCFGPIO_PPDSDR_USBL, + .clrr = (void __iomem *) MCFGPIO_PCLRR_USBL, }, { .gpio_chip = { @@ -589,11 +589,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 144, .ngpio = 4, }, - .pddr = MCFGPIO_PDDR_UARTH, - .podr = MCFGPIO_PODR_UARTH, - .ppdr = MCFGPIO_PPDSDR_UARTH, - .setr = MCFGPIO_PPDSDR_UARTH, - .clrr = MCFGPIO_PCLRR_UARTH, + .pddr = (void __iomem *) MCFGPIO_PDDR_UARTH, + .podr = (void __iomem *) MCFGPIO_PODR_UARTH, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTH, + .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTH, + .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTH, }, #endif }; diff --git a/arch/m68knommu/platform/528x/config.c b/arch/m68knommu/platform/528x/config.c index 76b743343bfa..ac39fc661219 100644 --- a/arch/m68knommu/platform/528x/config.c +++ b/arch/m68knommu/platform/528x/config.c @@ -29,15 +29,15 @@ static struct mcf_platform_uart m528x_uart_platform[] = { { - .mapbase = MCF_MBAR + MCFUART_BASE1, + .mapbase = MCFUART_BASE1, .irq = MCFINT_VECBASE + MCFINT_UART0, }, { - .mapbase = MCF_MBAR + MCFUART_BASE2, + .mapbase = MCFUART_BASE2, .irq = MCFINT_VECBASE + MCFINT_UART0 + 1, }, { - .mapbase = MCF_MBAR + MCFUART_BASE3, + .mapbase = MCFUART_BASE3, .irq = MCFINT_VECBASE + MCFINT_UART0 + 2, }, { }, @@ -51,8 +51,8 @@ static struct platform_device m528x_uart = { static struct resource m528x_fec_resources[] = { { - .start = MCF_MBAR + 0x1000, - .end = MCF_MBAR + 0x1000 + 0x7ff, + .start = MCFFEC_BASE, + .end = MCFFEC_BASE + MCFFEC_SIZE - 1, .flags = IORESOURCE_MEM, }, { @@ -227,9 +227,9 @@ static void __init m528x_uart_init_line(int line, int irq) /* make sure PUAPAR is set for UART0 and UART1 */ if (line < 2) { - port = readb(MCF_MBAR + MCF5282_GPIO_PUAPAR); + port = readb(MCF5282_GPIO_PUAPAR); port |= (0x03 << (line * 2)); - writeb(port, MCF_MBAR + MCF5282_GPIO_PUAPAR); + writeb(port, MCF5282_GPIO_PUAPAR); } } diff --git a/arch/m68knommu/platform/528x/gpio.c b/arch/m68knommu/platform/528x/gpio.c index eedaf0adbcd7..526db665d87e 100644 --- a/arch/m68knommu/platform/528x/gpio.c +++ b/arch/m68knommu/platform/528x/gpio.c @@ -33,9 +33,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 1, .ngpio = 7, }, - .pddr = MCFEPORT_EPDDR, - .podr = MCFEPORT_EPDR, - .ppdr = MCFEPORT_EPPDR, + .pddr = (void __iomem *)MCFEPORT_EPDDR, + .podr = (void __iomem *)MCFEPORT_EPDR, + .ppdr = (void __iomem *)MCFEPORT_EPPDR, }, { .gpio_chip = { @@ -49,9 +49,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 8, .ngpio = 4, }, - .pddr = MCFGPTA_GPTDDR, - .podr = MCFGPTA_GPTPORT, - .ppdr = MCFGPTB_GPTPORT, + .pddr = (void __iomem *)MCFGPTA_GPTDDR, + .podr = (void __iomem *)MCFGPTA_GPTPORT, + .ppdr = (void __iomem *)MCFGPTB_GPTPORT, }, { .gpio_chip = { @@ -65,9 +65,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 16, .ngpio = 4, }, - .pddr = MCFGPTB_GPTDDR, - .podr = MCFGPTB_GPTPORT, - .ppdr = MCFGPTB_GPTPORT, + .pddr = (void __iomem *)MCFGPTB_GPTDDR, + .podr = (void __iomem *)MCFGPTB_GPTPORT, + .ppdr = (void __iomem *)MCFGPTB_GPTPORT, }, { .gpio_chip = { @@ -81,9 +81,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 24, .ngpio = 4, }, - .pddr = MCFQADC_DDRQA, - .podr = MCFQADC_PORTQA, - .ppdr = MCFQADC_PORTQA, + .pddr = (void __iomem *)MCFQADC_DDRQA, + .podr = (void __iomem *)MCFQADC_PORTQA, + .ppdr = (void __iomem *)MCFQADC_PORTQA, }, { .gpio_chip = { @@ -97,9 +97,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 32, .ngpio = 4, }, - .pddr = MCFQADC_DDRQB, - .podr = MCFQADC_PORTQB, - .ppdr = MCFQADC_PORTQB, + .pddr = (void __iomem *)MCFQADC_DDRQB, + .podr = (void __iomem *)MCFQADC_PORTQB, + .ppdr = (void __iomem *)MCFQADC_PORTQB, }, { .gpio_chip = { @@ -113,11 +113,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 40, .ngpio = 8, }, - .pddr = MCFGPIO_DDRA, - .podr = MCFGPIO_PORTA, - .ppdr = MCFGPIO_PORTAP, - .setr = MCFGPIO_SETA, - .clrr = MCFGPIO_CLRA, + .pddr = (void __iomem *)MCFGPIO_DDRA, + .podr = (void __iomem *)MCFGPIO_PORTA, + .ppdr = (void __iomem *)MCFGPIO_PORTAP, + .setr = (void __iomem *)MCFGPIO_SETA, + .clrr = (void __iomem *)MCFGPIO_CLRA, }, { .gpio_chip = { @@ -131,11 +131,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 48, .ngpio = 8, }, - .pddr = MCFGPIO_DDRB, - .podr = MCFGPIO_PORTB, - .ppdr = MCFGPIO_PORTBP, - .setr = MCFGPIO_SETB, - .clrr = MCFGPIO_CLRB, + .pddr = (void __iomem *)MCFGPIO_DDRB, + .podr = (void __iomem *)MCFGPIO_PORTB, + .ppdr = (void __iomem *)MCFGPIO_PORTBP, + .setr = (void __iomem *)MCFGPIO_SETB, + .clrr = (void __iomem *)MCFGPIO_CLRB, }, { .gpio_chip = { @@ -149,11 +149,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 56, .ngpio = 8, }, - .pddr = MCFGPIO_DDRC, - .podr = MCFGPIO_PORTC, - .ppdr = MCFGPIO_PORTCP, - .setr = MCFGPIO_SETC, - .clrr = MCFGPIO_CLRC, + .pddr = (void __iomem *)MCFGPIO_DDRC, + .podr = (void __iomem *)MCFGPIO_PORTC, + .ppdr = (void __iomem *)MCFGPIO_PORTCP, + .setr = (void __iomem *)MCFGPIO_SETC, + .clrr = (void __iomem *)MCFGPIO_CLRC, }, { .gpio_chip = { @@ -167,11 +167,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 64, .ngpio = 8, }, - .pddr = MCFGPIO_DDRD, - .podr = MCFGPIO_PORTD, - .ppdr = MCFGPIO_PORTDP, - .setr = MCFGPIO_SETD, - .clrr = MCFGPIO_CLRD, + .pddr = (void __iomem *)MCFGPIO_DDRD, + .podr = (void __iomem *)MCFGPIO_PORTD, + .ppdr = (void __iomem *)MCFGPIO_PORTDP, + .setr = (void __iomem *)MCFGPIO_SETD, + .clrr = (void __iomem *)MCFGPIO_CLRD, }, { .gpio_chip = { @@ -185,11 +185,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 72, .ngpio = 8, }, - .pddr = MCFGPIO_DDRE, - .podr = MCFGPIO_PORTE, - .ppdr = MCFGPIO_PORTEP, - .setr = MCFGPIO_SETE, - .clrr = MCFGPIO_CLRE, + .pddr = (void __iomem *)MCFGPIO_DDRE, + .podr = (void __iomem *)MCFGPIO_PORTE, + .ppdr = (void __iomem *)MCFGPIO_PORTEP, + .setr = (void __iomem *)MCFGPIO_SETE, + .clrr = (void __iomem *)MCFGPIO_CLRE, }, { .gpio_chip = { @@ -203,11 +203,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 80, .ngpio = 8, }, - .pddr = MCFGPIO_DDRF, - .podr = MCFGPIO_PORTF, - .ppdr = MCFGPIO_PORTFP, - .setr = MCFGPIO_SETF, - .clrr = MCFGPIO_CLRF, + .pddr = (void __iomem *)MCFGPIO_DDRF, + .podr = (void __iomem *)MCFGPIO_PORTF, + .ppdr = (void __iomem *)MCFGPIO_PORTFP, + .setr = (void __iomem *)MCFGPIO_SETF, + .clrr = (void __iomem *)MCFGPIO_CLRF, }, { .gpio_chip = { @@ -221,11 +221,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 88, .ngpio = 8, }, - .pddr = MCFGPIO_DDRG, - .podr = MCFGPIO_PORTG, - .ppdr = MCFGPIO_PORTGP, - .setr = MCFGPIO_SETG, - .clrr = MCFGPIO_CLRG, + .pddr = (void __iomem *)MCFGPIO_DDRG, + .podr = (void __iomem *)MCFGPIO_PORTG, + .ppdr = (void __iomem *)MCFGPIO_PORTGP, + .setr = (void __iomem *)MCFGPIO_SETG, + .clrr = (void __iomem *)MCFGPIO_CLRG, }, { .gpio_chip = { @@ -239,11 +239,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 96, .ngpio = 8, }, - .pddr = MCFGPIO_DDRH, - .podr = MCFGPIO_PORTH, - .ppdr = MCFGPIO_PORTHP, - .setr = MCFGPIO_SETH, - .clrr = MCFGPIO_CLRH, + .pddr = (void __iomem *)MCFGPIO_DDRH, + .podr = (void __iomem *)MCFGPIO_PORTH, + .ppdr = (void __iomem *)MCFGPIO_PORTHP, + .setr = (void __iomem *)MCFGPIO_SETH, + .clrr = (void __iomem *)MCFGPIO_CLRH, }, { .gpio_chip = { @@ -257,11 +257,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 104, .ngpio = 8, }, - .pddr = MCFGPIO_DDRJ, - .podr = MCFGPIO_PORTJ, - .ppdr = MCFGPIO_PORTJP, - .setr = MCFGPIO_SETJ, - .clrr = MCFGPIO_CLRJ, + .pddr = (void __iomem *)MCFGPIO_DDRJ, + .podr = (void __iomem *)MCFGPIO_PORTJ, + .ppdr = (void __iomem *)MCFGPIO_PORTJP, + .setr = (void __iomem *)MCFGPIO_SETJ, + .clrr = (void __iomem *)MCFGPIO_CLRJ, }, { .gpio_chip = { @@ -275,11 +275,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 112, .ngpio = 8, }, - .pddr = MCFGPIO_DDRDD, - .podr = MCFGPIO_PORTDD, - .ppdr = MCFGPIO_PORTDDP, - .setr = MCFGPIO_SETDD, - .clrr = MCFGPIO_CLRDD, + .pddr = (void __iomem *)MCFGPIO_DDRDD, + .podr = (void __iomem *)MCFGPIO_PORTDD, + .ppdr = (void __iomem *)MCFGPIO_PORTDDP, + .setr = (void __iomem *)MCFGPIO_SETDD, + .clrr = (void __iomem *)MCFGPIO_CLRDD, }, { .gpio_chip = { @@ -293,11 +293,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 120, .ngpio = 8, }, - .pddr = MCFGPIO_DDREH, - .podr = MCFGPIO_PORTEH, - .ppdr = MCFGPIO_PORTEHP, - .setr = MCFGPIO_SETEH, - .clrr = MCFGPIO_CLREH, + .pddr = (void __iomem *)MCFGPIO_DDREH, + .podr = (void __iomem *)MCFGPIO_PORTEH, + .ppdr = (void __iomem *)MCFGPIO_PORTEHP, + .setr = (void __iomem *)MCFGPIO_SETEH, + .clrr = (void __iomem *)MCFGPIO_CLREH, }, { .gpio_chip = { @@ -311,11 +311,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 128, .ngpio = 8, }, - .pddr = MCFGPIO_DDREL, - .podr = MCFGPIO_PORTEL, - .ppdr = MCFGPIO_PORTELP, - .setr = MCFGPIO_SETEL, - .clrr = MCFGPIO_CLREL, + .pddr = (void __iomem *)MCFGPIO_DDREL, + .podr = (void __iomem *)MCFGPIO_PORTEL, + .ppdr = (void __iomem *)MCFGPIO_PORTELP, + .setr = (void __iomem *)MCFGPIO_SETEL, + .clrr = (void __iomem *)MCFGPIO_CLREL, }, { .gpio_chip = { @@ -329,11 +329,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 136, .ngpio = 6, }, - .pddr = MCFGPIO_DDRAS, - .podr = MCFGPIO_PORTAS, - .ppdr = MCFGPIO_PORTASP, - .setr = MCFGPIO_SETAS, - .clrr = MCFGPIO_CLRAS, + .pddr = (void __iomem *)MCFGPIO_DDRAS, + .podr = (void __iomem *)MCFGPIO_PORTAS, + .ppdr = (void __iomem *)MCFGPIO_PORTASP, + .setr = (void __iomem *)MCFGPIO_SETAS, + .clrr = (void __iomem *)MCFGPIO_CLRAS, }, { .gpio_chip = { @@ -347,11 +347,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 144, .ngpio = 7, }, - .pddr = MCFGPIO_DDRQS, - .podr = MCFGPIO_PORTQS, - .ppdr = MCFGPIO_PORTQSP, - .setr = MCFGPIO_SETQS, - .clrr = MCFGPIO_CLRQS, + .pddr = (void __iomem *)MCFGPIO_DDRQS, + .podr = (void __iomem *)MCFGPIO_PORTQS, + .ppdr = (void __iomem *)MCFGPIO_PORTQSP, + .setr = (void __iomem *)MCFGPIO_SETQS, + .clrr = (void __iomem *)MCFGPIO_CLRQS, }, { .gpio_chip = { @@ -365,11 +365,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 152, .ngpio = 6, }, - .pddr = MCFGPIO_DDRSD, - .podr = MCFGPIO_PORTSD, - .ppdr = MCFGPIO_PORTSDP, - .setr = MCFGPIO_SETSD, - .clrr = MCFGPIO_CLRSD, + .pddr = (void __iomem *)MCFGPIO_DDRSD, + .podr = (void __iomem *)MCFGPIO_PORTSD, + .ppdr = (void __iomem *)MCFGPIO_PORTSDP, + .setr = (void __iomem *)MCFGPIO_SETSD, + .clrr = (void __iomem *)MCFGPIO_CLRSD, }, { .gpio_chip = { @@ -383,11 +383,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 160, .ngpio = 4, }, - .pddr = MCFGPIO_DDRTC, - .podr = MCFGPIO_PORTTC, - .ppdr = MCFGPIO_PORTTCP, - .setr = MCFGPIO_SETTC, - .clrr = MCFGPIO_CLRTC, + .pddr = (void __iomem *)MCFGPIO_DDRTC, + .podr = (void __iomem *)MCFGPIO_PORTTC, + .ppdr = (void __iomem *)MCFGPIO_PORTTCP, + .setr = (void __iomem *)MCFGPIO_SETTC, + .clrr = (void __iomem *)MCFGPIO_CLRTC, }, { .gpio_chip = { @@ -401,11 +401,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 168, .ngpio = 4, }, - .pddr = MCFGPIO_DDRTD, - .podr = MCFGPIO_PORTTD, - .ppdr = MCFGPIO_PORTTDP, - .setr = MCFGPIO_SETTD, - .clrr = MCFGPIO_CLRTD, + .pddr = (void __iomem *)MCFGPIO_DDRTD, + .podr = (void __iomem *)MCFGPIO_PORTTD, + .ppdr = (void __iomem *)MCFGPIO_PORTTDP, + .setr = (void __iomem *)MCFGPIO_SETTD, + .clrr = (void __iomem *)MCFGPIO_CLRTD, }, { .gpio_chip = { @@ -419,11 +419,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 176, .ngpio = 4, }, - .pddr = MCFGPIO_DDRUA, - .podr = MCFGPIO_PORTUA, - .ppdr = MCFGPIO_PORTUAP, - .setr = MCFGPIO_SETUA, - .clrr = MCFGPIO_CLRUA, + .pddr = (void __iomem *)MCFGPIO_DDRUA, + .podr = (void __iomem *)MCFGPIO_PORTUA, + .ppdr = (void __iomem *)MCFGPIO_PORTUAP, + .setr = (void __iomem *)MCFGPIO_SETUA, + .clrr = (void __iomem *)MCFGPIO_CLRUA, }, }; diff --git a/arch/m68knommu/platform/5307/gpio.c b/arch/m68knommu/platform/5307/gpio.c index 8da5880e4066..5850612b4a38 100644 --- a/arch/m68knommu/platform/5307/gpio.c +++ b/arch/m68knommu/platform/5307/gpio.c @@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .set = mcf_gpio_set_value, .ngpio = 16, }, - .pddr = MCFSIM_PADDR, - .podr = MCFSIM_PADAT, - .ppdr = MCFSIM_PADAT, + .pddr = (void __iomem *) MCFSIM_PADDR, + .podr = (void __iomem *) MCFSIM_PADAT, + .ppdr = (void __iomem *) MCFSIM_PADAT, }, }; diff --git a/arch/m68knommu/platform/532x/gpio.c b/arch/m68knommu/platform/532x/gpio.c index 184b77382c3d..212a85deac90 100644 --- a/arch/m68knommu/platform/532x/gpio.c +++ b/arch/m68knommu/platform/532x/gpio.c @@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .set = mcf_gpio_set_value, .ngpio = 8, }, - .pddr = MCFEPORT_EPDDR, - .podr = MCFEPORT_EPDR, - .ppdr = MCFEPORT_EPPDR, + .pddr = (void __iomem *) MCFEPORT_EPDDR, + .podr = (void __iomem *) MCFEPORT_EPDR, + .ppdr = (void __iomem *) MCFEPORT_EPPDR, }, { .gpio_chip = { @@ -48,11 +48,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 8, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_FECH, - .podr = MCFGPIO_PODR_FECH, - .ppdr = MCFGPIO_PPDSDR_FECH, - .setr = MCFGPIO_PPDSDR_FECH, - .clrr = MCFGPIO_PCLRR_FECH, + .pddr = (void __iomem *) MCFGPIO_PDDR_FECH, + .podr = (void __iomem *) MCFGPIO_PODR_FECH, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECH, + .setr = (void __iomem *) MCFGPIO_PPDSDR_FECH, + .clrr = (void __iomem *) MCFGPIO_PCLRR_FECH, }, { .gpio_chip = { @@ -66,11 +66,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 16, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_FECL, - .podr = MCFGPIO_PODR_FECL, - .ppdr = MCFGPIO_PPDSDR_FECL, - .setr = MCFGPIO_PPDSDR_FECL, - .clrr = MCFGPIO_PCLRR_FECL, + .pddr = (void __iomem *) MCFGPIO_PDDR_FECL, + .podr = (void __iomem *) MCFGPIO_PODR_FECL, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECL, + .setr = (void __iomem *) MCFGPIO_PPDSDR_FECL, + .clrr = (void __iomem *) MCFGPIO_PCLRR_FECL, }, { .gpio_chip = { @@ -84,11 +84,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 24, .ngpio = 5, }, - .pddr = MCFGPIO_PDDR_SSI, - .podr = MCFGPIO_PODR_SSI, - .ppdr = MCFGPIO_PPDSDR_SSI, - .setr = MCFGPIO_PPDSDR_SSI, - .clrr = MCFGPIO_PCLRR_SSI, + .pddr = (void __iomem *) MCFGPIO_PDDR_SSI, + .podr = (void __iomem *) MCFGPIO_PODR_SSI, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SSI, + .setr = (void __iomem *) MCFGPIO_PPDSDR_SSI, + .clrr = (void __iomem *) MCFGPIO_PCLRR_SSI, }, { .gpio_chip = { @@ -102,11 +102,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 32, .ngpio = 4, }, - .pddr = MCFGPIO_PDDR_BUSCTL, - .podr = MCFGPIO_PODR_BUSCTL, - .ppdr = MCFGPIO_PPDSDR_BUSCTL, - .setr = MCFGPIO_PPDSDR_BUSCTL, - .clrr = MCFGPIO_PCLRR_BUSCTL, + .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL, + .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, + .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, + .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL, }, { .gpio_chip = { @@ -120,11 +120,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 40, .ngpio = 4, }, - .pddr = MCFGPIO_PDDR_BE, - .podr = MCFGPIO_PODR_BE, - .ppdr = MCFGPIO_PPDSDR_BE, - .setr = MCFGPIO_PPDSDR_BE, - .clrr = MCFGPIO_PCLRR_BE, + .pddr = (void __iomem *) MCFGPIO_PDDR_BE, + .podr = (void __iomem *) MCFGPIO_PODR_BE, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BE, + .setr = (void __iomem *) MCFGPIO_PPDSDR_BE, + .clrr = (void __iomem *) MCFGPIO_PCLRR_BE, }, { .gpio_chip = { @@ -138,11 +138,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 49, .ngpio = 5, }, - .pddr = MCFGPIO_PDDR_CS, - .podr = MCFGPIO_PODR_CS, - .ppdr = MCFGPIO_PPDSDR_CS, - .setr = MCFGPIO_PPDSDR_CS, - .clrr = MCFGPIO_PCLRR_CS, + .pddr = (void __iomem *) MCFGPIO_PDDR_CS, + .podr = (void __iomem *) MCFGPIO_PODR_CS, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS, + .setr = (void __iomem *) MCFGPIO_PPDSDR_CS, + .clrr = (void __iomem *) MCFGPIO_PCLRR_CS, }, { .gpio_chip = { @@ -156,11 +156,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 58, .ngpio = 4, }, - .pddr = MCFGPIO_PDDR_PWM, - .podr = MCFGPIO_PODR_PWM, - .ppdr = MCFGPIO_PPDSDR_PWM, - .setr = MCFGPIO_PPDSDR_PWM, - .clrr = MCFGPIO_PCLRR_PWM, + .pddr = (void __iomem *) MCFGPIO_PDDR_PWM, + .podr = (void __iomem *) MCFGPIO_PODR_PWM, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_PWM, + .setr = (void __iomem *) MCFGPIO_PPDSDR_PWM, + .clrr = (void __iomem *) MCFGPIO_PCLRR_PWM, }, { .gpio_chip = { @@ -174,11 +174,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 64, .ngpio = 4, }, - .pddr = MCFGPIO_PDDR_FECI2C, - .podr = MCFGPIO_PODR_FECI2C, - .ppdr = MCFGPIO_PPDSDR_FECI2C, - .setr = MCFGPIO_PPDSDR_FECI2C, - .clrr = MCFGPIO_PCLRR_FECI2C, + .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C, + .podr = (void __iomem *) MCFGPIO_PODR_FECI2C, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, + .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, + .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C, }, { .gpio_chip = { @@ -192,11 +192,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 72, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_UART, - .podr = MCFGPIO_PODR_UART, - .ppdr = MCFGPIO_PPDSDR_UART, - .setr = MCFGPIO_PPDSDR_UART, - .clrr = MCFGPIO_PCLRR_UART, + .pddr = (void __iomem *) MCFGPIO_PDDR_UART, + .podr = (void __iomem *) MCFGPIO_PODR_UART, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UART, + .setr = (void __iomem *) MCFGPIO_PPDSDR_UART, + .clrr = (void __iomem *) MCFGPIO_PCLRR_UART, }, { .gpio_chip = { @@ -210,11 +210,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 80, .ngpio = 6, }, - .pddr = MCFGPIO_PDDR_QSPI, - .podr = MCFGPIO_PODR_QSPI, - .ppdr = MCFGPIO_PPDSDR_QSPI, - .setr = MCFGPIO_PPDSDR_QSPI, - .clrr = MCFGPIO_PCLRR_QSPI, + .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI, + .podr = (void __iomem *) MCFGPIO_PODR_QSPI, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, + .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, + .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI, }, { .gpio_chip = { @@ -228,11 +228,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 88, .ngpio = 4, }, - .pddr = MCFGPIO_PDDR_TIMER, - .podr = MCFGPIO_PODR_TIMER, - .ppdr = MCFGPIO_PPDSDR_TIMER, - .setr = MCFGPIO_PPDSDR_TIMER, - .clrr = MCFGPIO_PCLRR_TIMER, + .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER, + .podr = (void __iomem *) MCFGPIO_PODR_TIMER, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER, + .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER, + .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER, }, { .gpio_chip = { @@ -246,11 +246,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 96, .ngpio = 2, }, - .pddr = MCFGPIO_PDDR_LCDDATAH, - .podr = MCFGPIO_PODR_LCDDATAH, - .ppdr = MCFGPIO_PPDSDR_LCDDATAH, - .setr = MCFGPIO_PPDSDR_LCDDATAH, - .clrr = MCFGPIO_PCLRR_LCDDATAH, + .pddr = (void __iomem *) MCFGPIO_PDDR_LCDDATAH, + .podr = (void __iomem *) MCFGPIO_PODR_LCDDATAH, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAH, + .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAH, + .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDDATAH, }, { .gpio_chip = { @@ -264,11 +264,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 104, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_LCDDATAM, - .podr = MCFGPIO_PODR_LCDDATAM, - .ppdr = MCFGPIO_PPDSDR_LCDDATAM, - .setr = MCFGPIO_PPDSDR_LCDDATAM, - .clrr = MCFGPIO_PCLRR_LCDDATAM, + .pddr = (void __iomem *) MCFGPIO_PDDR_LCDDATAM, + .podr = (void __iomem *) MCFGPIO_PODR_LCDDATAM, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAM, + .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAM, + .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDDATAM, }, { .gpio_chip = { @@ -282,11 +282,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 112, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_LCDDATAL, - .podr = MCFGPIO_PODR_LCDDATAL, - .ppdr = MCFGPIO_PPDSDR_LCDDATAL, - .setr = MCFGPIO_PPDSDR_LCDDATAL, - .clrr = MCFGPIO_PCLRR_LCDDATAL, + .pddr = (void __iomem *) MCFGPIO_PDDR_LCDDATAL, + .podr = (void __iomem *) MCFGPIO_PODR_LCDDATAL, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAL, + .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAL, + .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDDATAL, }, { .gpio_chip = { @@ -300,11 +300,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 120, .ngpio = 1, }, - .pddr = MCFGPIO_PDDR_LCDCTLH, - .podr = MCFGPIO_PODR_LCDCTLH, - .ppdr = MCFGPIO_PPDSDR_LCDCTLH, - .setr = MCFGPIO_PPDSDR_LCDCTLH, - .clrr = MCFGPIO_PCLRR_LCDCTLH, + .pddr = (void __iomem *) MCFGPIO_PDDR_LCDCTLH, + .podr = (void __iomem *) MCFGPIO_PODR_LCDCTLH, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLH, + .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLH, + .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDCTLH, }, { .gpio_chip = { @@ -318,11 +318,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .base = 128, .ngpio = 8, }, - .pddr = MCFGPIO_PDDR_LCDCTLL, - .podr = MCFGPIO_PODR_LCDCTLL, - .ppdr = MCFGPIO_PPDSDR_LCDCTLL, - .setr = MCFGPIO_PPDSDR_LCDCTLL, - .clrr = MCFGPIO_PCLRR_LCDCTLL, + .pddr = (void __iomem *) MCFGPIO_PDDR_LCDCTLL, + .podr = (void __iomem *) MCFGPIO_PODR_LCDCTLL, + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLL, + .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLL, + .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDCTLL, }, }; diff --git a/arch/m68knommu/platform/5407/gpio.c b/arch/m68knommu/platform/5407/gpio.c index 8da5880e4066..5850612b4a38 100644 --- a/arch/m68knommu/platform/5407/gpio.c +++ b/arch/m68knommu/platform/5407/gpio.c @@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .set = mcf_gpio_set_value, .ngpio = 16, }, - .pddr = MCFSIM_PADDR, - .podr = MCFSIM_PADAT, - .ppdr = MCFSIM_PADAT, + .pddr = (void __iomem *) MCFSIM_PADDR, + .podr = (void __iomem *) MCFSIM_PADAT, + .ppdr = (void __iomem *) MCFSIM_PADAT, }, }; diff --git a/arch/m68knommu/platform/54xx/Makefile b/arch/m68knommu/platform/54xx/Makefile index e6035e7a2d3f..6cfd090ec3cd 100644 --- a/arch/m68knommu/platform/54xx/Makefile +++ b/arch/m68knommu/platform/54xx/Makefile @@ -15,4 +15,5 @@ asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 obj-y := config.o +obj-$(CONFIG_FIREBEE) += firebee.o diff --git a/arch/m68knommu/platform/54xx/firebee.c b/arch/m68knommu/platform/54xx/firebee.c new file mode 100644 index 000000000000..46d50534f981 --- /dev/null +++ b/arch/m68knommu/platform/54xx/firebee.c @@ -0,0 +1,86 @@ +/***************************************************************************/ + +/* + * firebee.c -- extra startup code support for the FireBee boards + * + * Copyright (C) 2011, Greg Ungerer (gerg@snapgear.com) + */ + +/***************************************************************************/ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> +#include <asm/coldfire.h> +#include <asm/mcfsim.h> + +/***************************************************************************/ + +/* + * 8MB of NOR flash fitted to the FireBee board. + */ +#define FLASH_PHYS_ADDR 0xe0000000 /* Physical address of flash */ +#define FLASH_PHYS_SIZE 0x00800000 /* Size of flash */ + +#define PART_BOOT_START 0x00000000 /* Start at bottom of flash */ +#define PART_BOOT_SIZE 0x00040000 /* 256k in size */ +#define PART_IMAGE_START 0x00040000 /* Start after boot loader */ +#define PART_IMAGE_SIZE 0x006c0000 /* Most of flash */ +#define PART_FPGA_START 0x00700000 /* Start at offset 7MB */ +#define PART_FPGA_SIZE 0x00100000 /* 1MB in size */ + +static struct mtd_partition firebee_flash_parts[] = { + { + .name = "dBUG", + .offset = PART_BOOT_START, + .size = PART_BOOT_SIZE, + }, + { + .name = "FPGA", + .offset = PART_FPGA_START, + .size = PART_FPGA_SIZE, + }, + { + .name = "image", + .offset = PART_IMAGE_START, + .size = PART_IMAGE_SIZE, + }, +}; + +static struct physmap_flash_data firebee_flash_data = { + .width = 2, + .nr_parts = ARRAY_SIZE(firebee_flash_parts), + .parts = firebee_flash_parts, +}; + +static struct resource firebee_flash_resource = { + .start = FLASH_PHYS_ADDR, + .end = FLASH_PHYS_ADDR + FLASH_PHYS_SIZE, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device firebee_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &firebee_flash_data, + }, + .num_resources = 1, + .resource = &firebee_flash_resource, +}; + +/***************************************************************************/ + +static int __init init_firebee(void) +{ + platform_device_register(&firebee_flash); + return 0; +} + +arch_initcall(init_firebee); + +/***************************************************************************/ diff --git a/arch/m68knommu/platform/68328/ints.c b/arch/m68knommu/platform/68328/ints.c index 2a3af193ccd3..e5631831a200 100644 --- a/arch/m68knommu/platform/68328/ints.c +++ b/arch/m68knommu/platform/68328/ints.c @@ -135,20 +135,20 @@ void process_int(int vec, struct pt_regs *fp) } } -static void intc_irq_unmask(unsigned int irq) +static void intc_irq_unmask(struct irq_data *d) { - IMR &= ~(1<<irq); + IMR &= ~(1 << d->irq); } -static void intc_irq_mask(unsigned int irq) +static void intc_irq_mask(struct irq_data *d) { - IMR |= (1<<irq); + IMR |= (1 << d->irq); } static struct irq_chip intc_irq_chip = { .name = "M68K-INTC", - .mask = intc_irq_mask, - .unmask = intc_irq_unmask, + .irq_mask = intc_irq_mask, + .irq_unmask = intc_irq_unmask, }; /* diff --git a/arch/m68knommu/platform/68360/ints.c b/arch/m68knommu/platform/68360/ints.c index a29041c1a8a0..8de3feb568c6 100644 --- a/arch/m68knommu/platform/68360/ints.c +++ b/arch/m68knommu/platform/68360/ints.c @@ -37,26 +37,26 @@ extern void *_ramvec[]; /* The number of spurious interrupts */ volatile unsigned int num_spurious; -static void intc_irq_unmask(unsigned int irq) +static void intc_irq_unmask(struct irq_data *d) { - pquicc->intr_cimr |= (1 << irq); + pquicc->intr_cimr |= (1 << d->irq); } -static void intc_irq_mask(unsigned int irq) +static void intc_irq_mask(struct irq_data *d) { - pquicc->intr_cimr &= ~(1 << irq); + pquicc->intr_cimr &= ~(1 << d->irq); } -static void intc_irq_ack(unsigned int irq) +static void intc_irq_ack(struct irq_data *d) { - pquicc->intr_cisr = (1 << irq); + pquicc->intr_cisr = (1 << d->irq); } static struct irq_chip intc_irq_chip = { .name = "M68K-INTC", - .mask = intc_irq_mask, - .unmask = intc_irq_unmask, - .ack = intc_irq_ack, + .irq_mask = intc_irq_mask, + .irq_unmask = intc_irq_unmask, + .irq_ack = intc_irq_ack, }; /* diff --git a/arch/m68knommu/platform/coldfire/dma.c b/arch/m68knommu/platform/coldfire/dma.c index 2b30cf1b8f77..e88b95e2cc62 100644 --- a/arch/m68knommu/platform/coldfire/dma.c +++ b/arch/m68knommu/platform/coldfire/dma.c @@ -21,16 +21,16 @@ */ unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS] = { #ifdef MCFDMA_BASE0 - MCF_MBAR + MCFDMA_BASE0, + MCFDMA_BASE0, #endif #ifdef MCFDMA_BASE1 - MCF_MBAR + MCFDMA_BASE1, + MCFDMA_BASE1, #endif #ifdef MCFDMA_BASE2 - MCF_MBAR + MCFDMA_BASE2, + MCFDMA_BASE2, #endif #ifdef MCFDMA_BASE3 - MCF_MBAR + MCFDMA_BASE3, + MCFDMA_BASE3, #endif }; diff --git a/arch/m68knommu/platform/coldfire/head.S b/arch/m68knommu/platform/coldfire/head.S index d5977909ae5f..129bff4956b5 100644 --- a/arch/m68knommu/platform/coldfire/head.S +++ b/arch/m68knommu/platform/coldfire/head.S @@ -41,17 +41,17 @@ * DRAM controller is quite different. */ .macro GET_MEM_SIZE - movel MCF_MBAR+MCFSIM_DMR0,%d0 /* get mask for 1st bank */ + movel MCFSIM_DMR0,%d0 /* get mask for 1st bank */ btst #0,%d0 /* check if region enabled */ beq 1f andl #0xfffc0000,%d0 beq 1f addl #0x00040000,%d0 /* convert mask to size */ 1: - movel MCF_MBAR+MCFSIM_DMR1,%d1 /* get mask for 2nd bank */ + movel MCFSIM_DMR1,%d1 /* get mask for 2nd bank */ btst #0,%d1 /* check if region enabled */ beq 2f - andl #0xfffc0000, %d1 + andl #0xfffc0000,%d1 beq 2f addl #0x00040000,%d1 addl %d1,%d0 /* total mem size in d0 */ @@ -68,14 +68,14 @@ #elif defined(CONFIG_M520x) .macro GET_MEM_SIZE clrl %d0 - movel MCF_MBAR+MCFSIM_SDCS0, %d2 /* Get SDRAM chip select 0 config */ + movel MCFSIM_SDCS0, %d2 /* Get SDRAM chip select 0 config */ andl #0x1f, %d2 /* Get only the chip select size */ beq 3f /* Check if it is enabled */ addql #1, %d2 /* Form exponent */ moveql #1, %d0 lsll %d2, %d0 /* 2 ^ exponent */ 3: - movel MCF_MBAR+MCFSIM_SDCS1, %d2 /* Get SDRAM chip select 1 config */ + movel MCFSIM_SDCS1, %d2 /* Get SDRAM chip select 1 config */ andl #0x1f, %d2 /* Get only the chip select size */ beq 4f /* Check if it is enabled */ addql #1, %d2 /* Form exponent */ diff --git a/arch/m68knommu/platform/coldfire/intc-2.c b/arch/m68knommu/platform/coldfire/intc-2.c index 85daa2b3001a..2cbfbf035db9 100644 --- a/arch/m68knommu/platform/coldfire/intc-2.c +++ b/arch/m68knommu/platform/coldfire/intc-2.c @@ -7,7 +7,10 @@ * family, the 5270, 5271, 5274, 5275, and the 528x family which have two such * controllers, and the 547x and 548x families which have only one of them. * - * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com> + * The external 7 fixed interrupts are part the the Edge Port unit of these + * ColdFire parts. They can be configured as level or edge triggered. + * + * (C) Copyright 2009-2011, Greg Ungerer <gerg@snapgear.com> * * This file is subject to the terms and conditions of the GNU General Public * License. See the file COPYING in the main directory of this archive @@ -31,11 +34,12 @@ #define MCFSIM_ICR_PRI(p) (p) /* Priority p intr */ /* - * Each vector needs a unique priority and level associated with it. - * We don't really care so much what they are, we don't rely on the - * traditional priority interrupt scheme of the m68k/ColdFire. + * The EDGE Port interrupts are the fixed 7 external interrupts. + * They need some special treatment, for example they need to be acked. */ -static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6); +#define EINT0 64 /* Is not actually used, but spot reserved for it */ +#define EINT1 65 /* EDGE Port interrupt 1 */ +#define EINT7 71 /* EDGE Port interrupt 7 */ #ifdef MCFICM_INTC1 #define NR_VECS 128 @@ -43,66 +47,147 @@ static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6); #define NR_VECS 64 #endif -static void intc_irq_mask(unsigned int irq) +static void intc_irq_mask(struct irq_data *d) { - if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) { - unsigned long imraddr; - u32 val, imrbit; + unsigned int irq = d->irq - MCFINT_VECBASE; + unsigned long imraddr; + u32 val, imrbit; - irq -= MCFINT_VECBASE; - imraddr = MCF_IPSBAR; #ifdef MCFICM_INTC1 - imraddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; + imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; #else - imraddr += MCFICM_INTC0; + imraddr = MCFICM_INTC0; #endif - imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL; - imrbit = 0x1 << (irq & 0x1f); + imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL; + imrbit = 0x1 << (irq & 0x1f); - val = __raw_readl(imraddr); - __raw_writel(val | imrbit, imraddr); - } + val = __raw_readl(imraddr); + __raw_writel(val | imrbit, imraddr); +} + +static void intc_irq_unmask(struct irq_data *d) +{ + unsigned int irq = d->irq - MCFINT_VECBASE; + unsigned long imraddr; + u32 val, imrbit; + +#ifdef MCFICM_INTC1 + imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; +#else + imraddr = MCFICM_INTC0; +#endif + imraddr += ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL); + imrbit = 0x1 << (irq & 0x1f); + + /* Don't set the "maskall" bit! */ + if ((irq & 0x20) == 0) + imrbit |= 0x1; + + val = __raw_readl(imraddr); + __raw_writel(val & ~imrbit, imraddr); +} + +/* + * Only the external (or EDGE Port) interrupts need to be acknowledged + * here, as part of the IRQ handler. They only really need to be ack'ed + * if they are in edge triggered mode, but there is no harm in doing it + * for all types. + */ +static void intc_irq_ack(struct irq_data *d) +{ + unsigned int irq = d->irq; + + __raw_writeb(0x1 << (irq - EINT0), MCFEPORT_EPFR); } -static void intc_irq_unmask(unsigned int irq) +/* + * Each vector needs a unique priority and level associated with it. + * We don't really care so much what they are, we don't rely on the + * traditional priority interrupt scheme of the m68k/ColdFire. This + * only needs to be set once for an interrupt, and we will never change + * these values once we have set them. + */ +static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6); + +static unsigned int intc_irq_startup(struct irq_data *d) { - if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) { - unsigned long intaddr, imraddr, icraddr; - u32 val, imrbit; + unsigned int irq = d->irq - MCFINT_VECBASE; + unsigned long icraddr; - irq -= MCFINT_VECBASE; - intaddr = MCF_IPSBAR; #ifdef MCFICM_INTC1 - intaddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; + icraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; #else - intaddr += MCFICM_INTC0; + icraddr = MCFICM_INTC0; #endif - imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL); - icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f); - imrbit = 0x1 << (irq & 0x1f); + icraddr += MCFINTC_ICR0 + (irq & 0x3f); + if (__raw_readb(icraddr) == 0) + __raw_writeb(intc_intpri--, icraddr); - /* Don't set the "maskall" bit! */ - if ((irq & 0x20) == 0) - imrbit |= 0x1; + irq = d->irq; + if ((irq >= EINT1) && (irq <= EINT7)) { + u8 v; - if (__raw_readb(icraddr) == 0) - __raw_writeb(intc_intpri--, icraddr); + irq -= EINT0; - val = __raw_readl(imraddr); - __raw_writel(val & ~imrbit, imraddr); + /* Set EPORT line as input */ + v = __raw_readb(MCFEPORT_EPDDR); + __raw_writeb(v & ~(0x1 << irq), MCFEPORT_EPDDR); + + /* Set EPORT line as interrupt source */ + v = __raw_readb(MCFEPORT_EPIER); + __raw_writeb(v | (0x1 << irq), MCFEPORT_EPIER); } + + intc_irq_unmask(d); + return 0; } -static int intc_irq_set_type(unsigned int irq, unsigned int type) +static int intc_irq_set_type(struct irq_data *d, unsigned int type) { + unsigned int irq = d->irq; + u16 pa, tb; + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + tb = 0x1; + break; + case IRQ_TYPE_EDGE_FALLING: + tb = 0x2; + break; + case IRQ_TYPE_EDGE_BOTH: + tb = 0x3; + break; + default: + /* Level triggered */ + tb = 0; + break; + } + + if (tb) + set_irq_handler(irq, handle_edge_irq); + + irq -= EINT0; + pa = __raw_readw(MCFEPORT_EPPAR); + pa = (pa & ~(0x3 << (irq * 2))) | (tb << (irq * 2)); + __raw_writew(pa, MCFEPORT_EPPAR); + return 0; } static struct irq_chip intc_irq_chip = { .name = "CF-INTC", - .mask = intc_irq_mask, - .unmask = intc_irq_unmask, - .set_type = intc_irq_set_type, + .irq_startup = intc_irq_startup, + .irq_mask = intc_irq_mask, + .irq_unmask = intc_irq_unmask, +}; + +static struct irq_chip intc_irq_chip_edge_port = { + .name = "CF-INTC-EP", + .irq_startup = intc_irq_startup, + .irq_mask = intc_irq_mask, + .irq_unmask = intc_irq_unmask, + .irq_ack = intc_irq_ack, + .irq_set_type = intc_irq_set_type, }; void __init init_IRQ(void) @@ -112,13 +197,16 @@ void __init init_IRQ(void) init_vectors(); /* Mask all interrupt sources */ - __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL); + __raw_writel(0x1, MCFICM_INTC0 + MCFINTC_IMRL); #ifdef MCFICM_INTC1 - __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_IMRL); + __raw_writel(0x1, MCFICM_INTC1 + MCFINTC_IMRL); #endif - for (irq = 0; (irq < NR_IRQS); irq++) { - set_irq_chip(irq, &intc_irq_chip); + for (irq = MCFINT_VECBASE; (irq < MCFINT_VECBASE + NR_VECS); irq++) { + if ((irq >= EINT1) && (irq <=EINT7)) + set_irq_chip(irq, &intc_irq_chip_edge_port); + else + set_irq_chip(irq, &intc_irq_chip); set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); set_irq_handler(irq, handle_level_irq); } diff --git a/arch/m68knommu/platform/coldfire/intc-simr.c b/arch/m68knommu/platform/coldfire/intc-simr.c index bb7048636140..e642b24ab729 100644 --- a/arch/m68knommu/platform/coldfire/intc-simr.c +++ b/arch/m68knommu/platform/coldfire/intc-simr.c @@ -3,7 +3,7 @@ * * Interrupt controller code for the ColdFire 5208, 5207 & 532x parts. * - * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com> + * (C) Copyright 2009-2011, Greg Ungerer <gerg@snapgear.com> * * This file is subject to the terms and conditions of the GNU General Public * License. See the file COPYING in the main directory of this archive @@ -20,47 +20,156 @@ #include <asm/mcfsim.h> #include <asm/traps.h> -static void intc_irq_mask(unsigned int irq) +/* + * The EDGE Port interrupts are the fixed 7 external interrupts. + * They need some special treatment, for example they need to be acked. + */ +#ifdef CONFIG_M520x +/* + * The 520x parts only support a limited range of these external + * interrupts, only 1, 4 and 7 (as interrupts 65, 66 and 67). + */ +#define EINT0 64 /* Is not actually used, but spot reserved for it */ +#define EINT1 65 /* EDGE Port interrupt 1 */ +#define EINT4 66 /* EDGE Port interrupt 4 */ +#define EINT7 67 /* EDGE Port interrupt 7 */ + +static unsigned int irqebitmap[] = { 0, 1, 4, 7 }; +static unsigned int inline irq2ebit(unsigned int irq) { - if (irq >= MCFINT_VECBASE) { - if (irq < MCFINT_VECBASE + 64) - __raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_SIMR); - else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_SIMR) - __raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_SIMR); - } + return irqebitmap[irq - EINT0]; +} + +#else + +/* + * Most of the ColdFire parts with the EDGE Port module just have + * a strait direct mapping of the 7 external interrupts. Although + * there is a bit reserved for 0, it is not used. + */ +#define EINT0 64 /* Is not actually used, but spot reserved for it */ +#define EINT1 65 /* EDGE Port interrupt 1 */ +#define EINT7 71 /* EDGE Port interrupt 7 */ + +static unsigned int inline irq2ebit(unsigned int irq) +{ + return irq - EINT0; +} + +#endif + +/* + * There maybe one or two interrupt control units, each has 64 + * interrupts. If there is no second unit then MCFINTC1_* defines + * will be 0 (and code for them optimized away). + */ + +static void intc_irq_mask(struct irq_data *d) +{ + unsigned int irq = d->irq - MCFINT_VECBASE; + + if (MCFINTC1_SIMR && (irq > 64)) + __raw_writeb(irq - 64, MCFINTC1_SIMR); + else + __raw_writeb(irq, MCFINTC0_SIMR); } -static void intc_irq_unmask(unsigned int irq) +static void intc_irq_unmask(struct irq_data *d) { - if (irq >= MCFINT_VECBASE) { - if (irq < MCFINT_VECBASE + 64) - __raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_CIMR); - else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_CIMR) - __raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_CIMR); + unsigned int irq = d->irq - MCFINT_VECBASE; + + if (MCFINTC1_CIMR && (irq > 64)) + __raw_writeb(irq - 64, MCFINTC1_CIMR); + else + __raw_writeb(irq, MCFINTC0_CIMR); +} + +static void intc_irq_ack(struct irq_data *d) +{ + unsigned int ebit = irq2ebit(d->irq); + + __raw_writeb(0x1 << ebit, MCFEPORT_EPFR); +} + +static unsigned int intc_irq_startup(struct irq_data *d) +{ + unsigned int irq = d->irq; + + if ((irq >= EINT1) && (irq <= EINT7)) { + unsigned int ebit = irq2ebit(irq); + u8 v; + + /* Set EPORT line as input */ + v = __raw_readb(MCFEPORT_EPDDR); + __raw_writeb(v & ~(0x1 << ebit), MCFEPORT_EPDDR); + + /* Set EPORT line as interrupt source */ + v = __raw_readb(MCFEPORT_EPIER); + __raw_writeb(v | (0x1 << ebit), MCFEPORT_EPIER); } + + irq -= MCFINT_VECBASE; + if (MCFINTC1_ICR0 && (irq > 64)) + __raw_writeb(5, MCFINTC1_ICR0 + irq - 64); + else + __raw_writeb(5, MCFINTC0_ICR0 + irq); + + + intc_irq_unmask(d); + return 0; } -static int intc_irq_set_type(unsigned int irq, unsigned int type) +static int intc_irq_set_type(struct irq_data *d, unsigned int type) { - if (irq >= MCFINT_VECBASE) { - if (irq < MCFINT_VECBASE + 64) - __raw_writeb(5, MCFINTC0_ICR0 + irq - MCFINT_VECBASE); - else if ((irq < MCFINT_VECBASE) && MCFINTC1_ICR0) - __raw_writeb(5, MCFINTC1_ICR0 + irq - MCFINT_VECBASE - 64); + unsigned int ebit, irq = d->irq; + u16 pa, tb; + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + tb = 0x1; + break; + case IRQ_TYPE_EDGE_FALLING: + tb = 0x2; + break; + case IRQ_TYPE_EDGE_BOTH: + tb = 0x3; + break; + default: + /* Level triggered */ + tb = 0; + break; } + + if (tb) + set_irq_handler(irq, handle_edge_irq); + + ebit = irq2ebit(irq) * 2; + pa = __raw_readw(MCFEPORT_EPPAR); + pa = (pa & ~(0x3 << ebit)) | (tb << ebit); + __raw_writew(pa, MCFEPORT_EPPAR); + return 0; } static struct irq_chip intc_irq_chip = { .name = "CF-INTC", - .mask = intc_irq_mask, - .unmask = intc_irq_unmask, - .set_type = intc_irq_set_type, + .irq_startup = intc_irq_startup, + .irq_mask = intc_irq_mask, + .irq_unmask = intc_irq_unmask, +}; + +static struct irq_chip intc_irq_chip_edge_port = { + .name = "CF-INTC-EP", + .irq_startup = intc_irq_startup, + .irq_mask = intc_irq_mask, + .irq_unmask = intc_irq_unmask, + .irq_ack = intc_irq_ack, + .irq_set_type = intc_irq_set_type, }; void __init init_IRQ(void) { - int irq; + int irq, eirq; init_vectors(); @@ -69,8 +178,12 @@ void __init init_IRQ(void) if (MCFINTC1_SIMR) __raw_writeb(0xff, MCFINTC1_SIMR); - for (irq = 0; (irq < NR_IRQS); irq++) { - set_irq_chip(irq, &intc_irq_chip); + eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0); + for (irq = MCFINT_VECBASE; (irq < eirq); irq++) { + if ((irq >= EINT1) && (irq <= EINT7)) + set_irq_chip(irq, &intc_irq_chip_edge_port); + else + set_irq_chip(irq, &intc_irq_chip); set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); set_irq_handler(irq, handle_level_irq); } diff --git a/arch/m68knommu/platform/coldfire/intc.c b/arch/m68knommu/platform/coldfire/intc.c index 60d2fcbe182b..d648081a63f6 100644 --- a/arch/m68knommu/platform/coldfire/intc.c +++ b/arch/m68knommu/platform/coldfire/intc.c @@ -111,28 +111,28 @@ void mcf_autovector(int irq) #endif } -static void intc_irq_mask(unsigned int irq) +static void intc_irq_mask(struct irq_data *d) { - if (mcf_irq2imr[irq]) - mcf_setimr(mcf_irq2imr[irq]); + if (mcf_irq2imr[d->irq]) + mcf_setimr(mcf_irq2imr[d->irq]); } -static void intc_irq_unmask(unsigned int irq) +static void intc_irq_unmask(struct irq_data *d) { - if (mcf_irq2imr[irq]) - mcf_clrimr(mcf_irq2imr[irq]); + if (mcf_irq2imr[d->irq]) + mcf_clrimr(mcf_irq2imr[d->irq]); } -static int intc_irq_set_type(unsigned int irq, unsigned int type) +static int intc_irq_set_type(struct irq_data *d, unsigned int type) { return 0; } static struct irq_chip intc_irq_chip = { .name = "CF-INTC", - .mask = intc_irq_mask, - .unmask = intc_irq_unmask, - .set_type = intc_irq_set_type, + .irq_mask = intc_irq_mask, + .irq_unmask = intc_irq_unmask, + .irq_set_type = intc_irq_set_type, }; void __init init_IRQ(void) diff --git a/arch/m68knommu/platform/coldfire/pit.c b/arch/m68knommu/platform/coldfire/pit.c index aebea19abd78..c2b980926bec 100644 --- a/arch/m68knommu/platform/coldfire/pit.c +++ b/arch/m68knommu/platform/coldfire/pit.c @@ -31,7 +31,7 @@ * By default use timer1 as the system clock timer. */ #define FREQ ((MCF_CLK / 2) / 64) -#define TA(a) (MCF_IPSBAR + MCFPIT_BASE1 + (a)) +#define TA(a) (MCFPIT_BASE1 + (a)) #define PIT_CYCLES_PER_JIFFY (FREQ / HZ) static u32 pit_cnt; diff --git a/arch/m68knommu/platform/coldfire/timers.c b/arch/m68knommu/platform/coldfire/timers.c index 2304d736c701..60242f65fea9 100644 --- a/arch/m68knommu/platform/coldfire/timers.c +++ b/arch/m68knommu/platform/coldfire/timers.c @@ -28,7 +28,7 @@ * By default use timer1 as the system clock timer. */ #define FREQ (MCF_BUSCLK / 16) -#define TA(a) (MCF_MBAR + MCFTIMER_BASE1 + (a)) +#define TA(a) (MCFTIMER_BASE1 + (a)) /* * These provide the underlying interrupt vector support. @@ -126,7 +126,7 @@ void hw_timer_init(void) /* * By default use timer2 as the profiler clock timer. */ -#define PA(a) (MCF_MBAR + MCFTIMER_BASE2 + (a)) +#define PA(a) (MCFTIMER_BASE2 + (a)) /* * Choose a reasonably fast profile timer. Make it an odd value to diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 31680032053e..922c4194c7bb 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -17,6 +17,7 @@ config MICROBLAZE select OF_EARLY_FLATTREE select HAVE_GENERIC_HARDIRQS select GENERIC_IRQ_PROBE + select GENERIC_HARDIRQS_NO_DEPRECATED config SWAP def_bool n @@ -183,6 +184,17 @@ config LOWMEM_SIZE hex "Maximum low memory size (in bytes)" if LOWMEM_SIZE_BOOL default "0x30000000" +config MANUAL_RESET_VECTOR + hex "Microblaze reset vector address setup" + default "0x0" + help + Set this option to have the kernel override the CPU Reset vector. + If zero, no change will be made to the MicroBlaze reset vector at + address 0x0. + If non-zero, a jump instruction to this address, will be written + to the reset vector at address 0x0. + If you are unsure, set it to default value 0x0. + config KERNEL_START_BOOL bool "Set custom kernel base address" depends on ADVANCED_OPTIONS @@ -247,7 +259,7 @@ endmenu source "mm/Kconfig" -menu "Exectuable file formats" +menu "Executable file formats" source "fs/Kconfig.binfmt" diff --git a/arch/microblaze/include/asm/cacheflush.h b/arch/microblaze/include/asm/cacheflush.h index 7ebd955460d9..0f553bc009a0 100644 --- a/arch/microblaze/include/asm/cacheflush.h +++ b/arch/microblaze/include/asm/cacheflush.h @@ -84,12 +84,13 @@ do { \ #define flush_dcache_mmap_lock(mapping) do { } while (0) #define flush_dcache_mmap_unlock(mapping) do { } while (0) - #define flush_cache_dup_mm(mm) do { } while (0) #define flush_cache_vmap(start, end) do { } while (0) #define flush_cache_vunmap(start, end) do { } while (0) #define flush_cache_mm(mm) do { } while (0) -#define flush_cache_page(vma, vmaddr, pfn) do { } while (0) + +#define flush_cache_page(vma, vmaddr, pfn) \ + flush_dcache_range(pfn << PAGE_SHIFT, (pfn << PAGE_SHIFT) + PAGE_SIZE); /* MS: kgdb code use this macro, wrong len with FLASH */ #if 0 @@ -104,9 +105,13 @@ do { \ #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ do { \ u32 addr = virt_to_phys(dst); \ - invalidate_icache_range((unsigned) (addr), (unsigned) (addr) + (len));\ memcpy((dst), (src), (len)); \ - flush_dcache_range((unsigned) (addr), (unsigned) (addr) + (len));\ + if (vma->vm_flags & VM_EXEC) { \ + invalidate_icache_range((unsigned) (addr), \ + (unsigned) (addr) + PAGE_SIZE); \ + flush_dcache_range((unsigned) (addr), \ + (unsigned) (addr) + PAGE_SIZE); \ + } \ } while (0) #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ diff --git a/arch/microblaze/include/asm/cpuinfo.h b/arch/microblaze/include/asm/cpuinfo.h index cd257537ae54..d8f013347a9e 100644 --- a/arch/microblaze/include/asm/cpuinfo.h +++ b/arch/microblaze/include/asm/cpuinfo.h @@ -96,8 +96,8 @@ void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu); static inline unsigned int fcpu(struct device_node *cpu, char *n) { - int *val; - return (val = (int *) of_get_property(cpu, n, NULL)) ? + const __be32 *val; + return (val = of_get_property(cpu, n, NULL)) ? be32_to_cpup(val) : 0; } diff --git a/arch/microblaze/include/asm/entry.h b/arch/microblaze/include/asm/entry.h index ec89f2ad0fe1..af0144b91b79 100644 --- a/arch/microblaze/include/asm/entry.h +++ b/arch/microblaze/include/asm/entry.h @@ -31,40 +31,4 @@ DECLARE_PER_CPU(unsigned int, R11_SAVE); /* Temp variable for entry */ DECLARE_PER_CPU(unsigned int, CURRENT_SAVE); /* Saved current pointer */ # endif /* __ASSEMBLY__ */ -#ifndef CONFIG_MMU - -/* noMMU hasn't any space for args */ -# define STATE_SAVE_ARG_SPACE (0) - -#else /* CONFIG_MMU */ - -/* If true, system calls save and restore all registers (except result - * registers, of course). If false, then `call clobbered' registers - * will not be preserved, on the theory that system calls are basically - * function calls anyway, and the caller should be able to deal with it. - * This is a security risk, of course, as `internal' values may leak out - * after a system call, but that certainly doesn't matter very much for - * a processor with no MMU protection! For a protected-mode kernel, it - * would be faster to just zero those registers before returning. - * - * I can not rely on the glibc implementation. If you turn it off make - * sure that r11/r12 is saved in user-space. --KAA - * - * These are special variables using by the kernel trap/interrupt code - * to save registers in, at a time when there are no spare registers we - * can use to do so, and we can't depend on the value of the stack - * pointer. This means that they must be within a signed 16-bit - * displacement of 0x00000000. - */ - -/* A `state save frame' is a struct pt_regs preceded by some extra space - * suitable for a function call stack frame. */ - -/* Amount of room on the stack reserved for arguments and to satisfy the - * C calling conventions, in addition to the space used by the struct - * pt_regs that actually holds saved values. */ -#define STATE_SAVE_ARG_SPACE (6*4) /* Up to six arguments */ - -#endif /* CONFIG_MMU */ - #endif /* _ASM_MICROBLAZE_ENTRY_H */ diff --git a/arch/microblaze/include/asm/exceptions.h b/arch/microblaze/include/asm/exceptions.h index 6479097b802b..e6a8ddea1dca 100644 --- a/arch/microblaze/include/asm/exceptions.h +++ b/arch/microblaze/include/asm/exceptions.h @@ -66,6 +66,9 @@ asmlinkage void full_exception(struct pt_regs *regs, unsigned int type, int fsr, int addr); +asmlinkage void sw_exception(struct pt_regs *regs); +void bad_page_fault(struct pt_regs *regs, unsigned long address, int sig); + void die(const char *str, struct pt_regs *fp, long err); void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr); diff --git a/arch/microblaze/include/asm/futex.h b/arch/microblaze/include/asm/futex.h index ad3fd61b2fe7..b0526d2716fa 100644 --- a/arch/microblaze/include/asm/futex.h +++ b/arch/microblaze/include/asm/futex.h @@ -29,7 +29,7 @@ }) static inline int -futex_atomic_op_inuser(int encoded_op, int __user *uaddr) +futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr) { int op = (encoded_op >> 28) & 7; int cmp = (encoded_op >> 24) & 15; @@ -39,7 +39,7 @@ futex_atomic_op_inuser(int encoded_op, int __user *uaddr) if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) oparg = 1 << oparg; - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; pagefault_disable(); @@ -94,31 +94,34 @@ futex_atomic_op_inuser(int encoded_op, int __user *uaddr) } static inline int -futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) +futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) { - int prev, cmp; + int ret = 0, cmp; + u32 prev; - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; - __asm__ __volatile__ ("1: lwx %0, %2, r0; \ - cmp %1, %0, %3; \ - beqi %1, 3f; \ - 2: swx %4, %2, r0; \ - addic %1, r0, 0; \ - bnei %1, 1b; \ + __asm__ __volatile__ ("1: lwx %1, %3, r0; \ + cmp %2, %1, %4; \ + beqi %2, 3f; \ + 2: swx %5, %3, r0; \ + addic %2, r0, 0; \ + bnei %2, 1b; \ 3: \ .section .fixup,\"ax\"; \ 4: brid 3b; \ - addik %0, r0, %5; \ + addik %0, r0, %6; \ .previous; \ .section __ex_table,\"a\"; \ .word 1b,4b,2b,4b; \ .previous;" \ - : "=&r" (prev), "=&r"(cmp) \ + : "+r" (ret), "=&r" (prev), "=&r"(cmp) \ : "r" (uaddr), "r" (oldval), "r" (newval), "i" (-EFAULT)); - return prev; + *uval = prev; + return ret; } #endif /* __KERNEL__ */ diff --git a/arch/microblaze/include/asm/irq.h b/arch/microblaze/include/asm/irq.h index ec5583d6111c..cc54187f3d38 100644 --- a/arch/microblaze/include/asm/irq.h +++ b/arch/microblaze/include/asm/irq.h @@ -12,8 +12,6 @@ #define NR_IRQS 32 #include <asm-generic/irq.h> -#include <linux/interrupt.h> - /* This type is the placeholder for a hardware interrupt number. It has to * be big enough to enclose whatever representation is used by a given * platform. diff --git a/arch/microblaze/include/asm/pci-bridge.h b/arch/microblaze/include/asm/pci-bridge.h index 0c68764ab547..10717669e0c2 100644 --- a/arch/microblaze/include/asm/pci-bridge.h +++ b/arch/microblaze/include/asm/pci-bridge.h @@ -104,11 +104,22 @@ struct pci_controller { int global_number; /* PCI domain number */ }; +#ifdef CONFIG_PCI static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) { return bus->sysdata; } +static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) +{ + struct pci_controller *host; + + if (bus->self) + return pci_device_to_OF_node(bus->self); + host = pci_bus_to_host(bus); + return host ? host->dn : NULL; +} + static inline int isa_vaddr_is_ioport(void __iomem *address) { /* No specific ISA handling on ppc32 at this stage, it @@ -116,6 +127,7 @@ static inline int isa_vaddr_is_ioport(void __iomem *address) */ return 0; } +#endif /* CONFIG_PCI */ /* These are used for config access before all the PCI probing has been done. */ diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h index 885574a73f01..b2af42311a12 100644 --- a/arch/microblaze/include/asm/pgtable.h +++ b/arch/microblaze/include/asm/pgtable.h @@ -572,7 +572,7 @@ void __init *early_get_page(void); extern unsigned long ioremap_bot, ioremap_base; -void *consistent_alloc(int gfp, size_t size, dma_addr_t *dma_handle); +void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *dma_handle); void consistent_free(size_t size, void *vaddr); void consistent_sync(void *vaddr, size_t size, int direction); void consistent_sync_page(struct page *page, unsigned long offset, diff --git a/arch/microblaze/include/asm/processor.h b/arch/microblaze/include/asm/processor.h index 8eeb09211ece..aed2a6be8e27 100644 --- a/arch/microblaze/include/asm/processor.h +++ b/arch/microblaze/include/asm/processor.h @@ -155,7 +155,7 @@ unsigned long get_wchan(struct task_struct *p); # define task_regs(task) ((struct pt_regs *)task_tos(task) - 1) # define task_pt_regs_plus_args(tsk) \ - (((void *)task_pt_regs(tsk)) - STATE_SAVE_ARG_SPACE) + ((void *)task_pt_regs(tsk)) # define task_sp(task) (task_regs(task)->r1) # define task_pc(task) (task_regs(task)->pc) diff --git a/arch/microblaze/include/asm/prom.h b/arch/microblaze/include/asm/prom.h index 2e72af078b05..d0890d36ef61 100644 --- a/arch/microblaze/include/asm/prom.h +++ b/arch/microblaze/include/asm/prom.h @@ -64,21 +64,6 @@ extern void kdump_move_device_tree(void); /* CPU OF node matching */ struct device_node *of_get_cpu_node(int cpu, unsigned int *thread); -/** - * of_irq_map_pci - Resolve the interrupt for a PCI device - * @pdev: the device whose interrupt is to be resolved - * @out_irq: structure of_irq filled by this function - * - * This function resolves the PCI interrupt for a given PCI device. If a - * device-node exists for a given pci_dev, it will use normal OF tree - * walking. If not, it will implement standard swizzling and walk up the - * PCI tree until an device-node is found, at which point it will finish - * resolving using the OF tree walking. - */ -struct pci_dev; -struct of_irq; -extern int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq); - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/arch/microblaze/include/asm/ptrace.h b/arch/microblaze/include/asm/ptrace.h index d74dbfb92c04..d9b66304d5dd 100644 --- a/arch/microblaze/include/asm/ptrace.h +++ b/arch/microblaze/include/asm/ptrace.h @@ -66,13 +66,13 @@ void show_regs(struct pt_regs *); #else /* __KERNEL__ */ /* pt_regs offsets used by gdbserver etc in ptrace syscalls */ -#define PT_GPR(n) ((n) * sizeof(microblaze_reg_t)) -#define PT_PC (32 * sizeof(microblaze_reg_t)) -#define PT_MSR (33 * sizeof(microblaze_reg_t)) -#define PT_EAR (34 * sizeof(microblaze_reg_t)) -#define PT_ESR (35 * sizeof(microblaze_reg_t)) -#define PT_FSR (36 * sizeof(microblaze_reg_t)) -#define PT_KERNEL_MODE (37 * sizeof(microblaze_reg_t)) +#define PT_GPR(n) ((n) * sizeof(microblaze_reg_t)) +#define PT_PC (32 * sizeof(microblaze_reg_t)) +#define PT_MSR (33 * sizeof(microblaze_reg_t)) +#define PT_EAR (34 * sizeof(microblaze_reg_t)) +#define PT_ESR (35 * sizeof(microblaze_reg_t)) +#define PT_FSR (36 * sizeof(microblaze_reg_t)) +#define PT_KERNEL_MODE (37 * sizeof(microblaze_reg_t)) #endif /* __KERNEL */ diff --git a/arch/microblaze/include/asm/syscall.h b/arch/microblaze/include/asm/syscall.h index 048dfcd8d89d..9bc431783105 100644 --- a/arch/microblaze/include/asm/syscall.h +++ b/arch/microblaze/include/asm/syscall.h @@ -96,4 +96,7 @@ static inline void syscall_set_arguments(struct task_struct *task, microblaze_set_syscall_arg(regs, i++, *args++); } +asmlinkage long do_syscall_trace_enter(struct pt_regs *regs); +asmlinkage void do_syscall_trace_leave(struct pt_regs *regs); + #endif /* __ASM_MICROBLAZE_SYSCALL_H */ diff --git a/arch/microblaze/include/asm/syscalls.h b/arch/microblaze/include/asm/syscalls.h index 720761cc741f..27f2f4c0f39f 100644 --- a/arch/microblaze/include/asm/syscalls.h +++ b/arch/microblaze/include/asm/syscalls.h @@ -1,5 +1,13 @@ #ifndef __ASM_MICROBLAZE_SYSCALLS_H +asmlinkage long microblaze_vfork(struct pt_regs *regs); +asmlinkage long microblaze_clone(int flags, unsigned long stack, + struct pt_regs *regs); +asmlinkage long microblaze_execve(const char __user *filenamei, + const char __user *const __user *argv, + const char __user *const __user *envp, + struct pt_regs *regs); + asmlinkage long sys_clone(int flags, unsigned long stack, struct pt_regs *regs); #define sys_clone sys_clone diff --git a/arch/microblaze/include/asm/uaccess.h b/arch/microblaze/include/asm/uaccess.h index d840f4a2d3c9..5bb95a11880d 100644 --- a/arch/microblaze/include/asm/uaccess.h +++ b/arch/microblaze/include/asm/uaccess.h @@ -120,16 +120,16 @@ static inline unsigned long __must_check __clear_user(void __user *to, { /* normal memset with two words to __ex_table */ __asm__ __volatile__ ( \ - "1: sb r0, %2, r0;" \ + "1: sb r0, %1, r0;" \ " addik %0, %0, -1;" \ " bneid %0, 1b;" \ - " addik %2, %2, 1;" \ + " addik %1, %1, 1;" \ "2: " \ __EX_TABLE_SECTION \ ".word 1b,2b;" \ ".previous;" \ - : "=r"(n) \ - : "0"(n), "r"(to) + : "=r"(n), "=r"(to) \ + : "0"(n), "1"(to) ); return n; } diff --git a/arch/microblaze/include/asm/unaligned.h b/arch/microblaze/include/asm/unaligned.h index 2b97cbe500e9..b162ed880495 100644 --- a/arch/microblaze/include/asm/unaligned.h +++ b/arch/microblaze/include/asm/unaligned.h @@ -12,18 +12,19 @@ # ifdef __KERNEL__ -# include <linux/unaligned/be_byteshift.h> -# include <linux/unaligned/le_byteshift.h> -# include <linux/unaligned/generic.h> - - # ifdef __MICROBLAZEEL__ +# include <linux/unaligned/le_struct.h> +# include <linux/unaligned/be_byteshift.h> # define get_unaligned __get_unaligned_le # define put_unaligned __put_unaligned_le # else +# include <linux/unaligned/be_struct.h> +# include <linux/unaligned/le_byteshift.h> # define get_unaligned __get_unaligned_be # define put_unaligned __put_unaligned_be # endif +# include <linux/unaligned/generic.h> + # endif /* __KERNEL__ */ #endif /* _ASM_MICROBLAZE_UNALIGNED_H */ diff --git a/arch/microblaze/kernel/cpu/cache.c b/arch/microblaze/kernel/cpu/cache.c index 109876e8d643..cf0afd90a2c0 100644 --- a/arch/microblaze/kernel/cpu/cache.c +++ b/arch/microblaze/kernel/cpu/cache.c @@ -519,7 +519,7 @@ static void __flush_dcache_range_wb(unsigned long start, unsigned long end) struct scache *mbc; /* new wb cache model */ -const struct scache wb_msr = { +static const struct scache wb_msr = { .ie = __enable_icache_msr, .id = __disable_icache_msr, .ifl = __flush_icache_all_noirq, @@ -535,7 +535,7 @@ const struct scache wb_msr = { }; /* There is only difference in ie, id, de, dd functions */ -const struct scache wb_nomsr = { +static const struct scache wb_nomsr = { .ie = __enable_icache_nomsr, .id = __disable_icache_nomsr, .ifl = __flush_icache_all_noirq, @@ -551,7 +551,7 @@ const struct scache wb_nomsr = { }; /* Old wt cache model with disabling irq and turn off cache */ -const struct scache wt_msr = { +static const struct scache wt_msr = { .ie = __enable_icache_msr, .id = __disable_icache_msr, .ifl = __flush_icache_all_msr_irq, @@ -566,7 +566,7 @@ const struct scache wt_msr = { .dinr = __invalidate_dcache_range_msr_irq_wt, }; -const struct scache wt_nomsr = { +static const struct scache wt_nomsr = { .ie = __enable_icache_nomsr, .id = __disable_icache_nomsr, .ifl = __flush_icache_all_nomsr_irq, @@ -582,7 +582,7 @@ const struct scache wt_nomsr = { }; /* New wt cache model for newer Microblaze versions */ -const struct scache wt_msr_noirq = { +static const struct scache wt_msr_noirq = { .ie = __enable_icache_msr, .id = __disable_icache_msr, .ifl = __flush_icache_all_noirq, @@ -597,7 +597,7 @@ const struct scache wt_msr_noirq = { .dinr = __invalidate_dcache_range_nomsr_wt, }; -const struct scache wt_nomsr_noirq = { +static const struct scache wt_nomsr_noirq = { .ie = __enable_icache_nomsr, .id = __disable_icache_nomsr, .ifl = __flush_icache_all_noirq, @@ -624,7 +624,7 @@ void microblaze_cache_init(void) if (cpuinfo.dcache_wb) { INFO("wb_msr"); mbc = (struct scache *)&wb_msr; - if (cpuinfo.ver_code < CPUVER_7_20_D) { + if (cpuinfo.ver_code <= CPUVER_7_20_D) { /* MS: problem with signal handling - hw bug */ INFO("WB won't work properly"); } @@ -641,7 +641,7 @@ void microblaze_cache_init(void) if (cpuinfo.dcache_wb) { INFO("wb_nomsr"); mbc = (struct scache *)&wb_nomsr; - if (cpuinfo.ver_code < CPUVER_7_20_D) { + if (cpuinfo.ver_code <= CPUVER_7_20_D) { /* MS: problem with signal handling - hw bug */ INFO("WB won't work properly"); } diff --git a/arch/microblaze/kernel/cpu/cpuinfo.c b/arch/microblaze/kernel/cpu/cpuinfo.c index 2c309fccf230..c1640c52711f 100644 --- a/arch/microblaze/kernel/cpu/cpuinfo.c +++ b/arch/microblaze/kernel/cpu/cpuinfo.c @@ -33,6 +33,7 @@ const struct cpu_ver_key cpu_ver_lookup[] = { {"7.30.b", 0x11}, {"8.00.a", 0x12}, {"8.00.b", 0x13}, + {"8.10.a", 0x14}, {NULL, 0}, }; diff --git a/arch/microblaze/kernel/dma.c b/arch/microblaze/kernel/dma.c index 79c74659f204..393e6b2db688 100644 --- a/arch/microblaze/kernel/dma.c +++ b/arch/microblaze/kernel/dma.c @@ -26,6 +26,7 @@ static inline void __dma_sync_page(unsigned long paddr, unsigned long offset, { switch (direction) { case DMA_TO_DEVICE: + case DMA_BIDIRECTIONAL: flush_dcache_range(paddr + offset, paddr + offset + size); break; case DMA_FROM_DEVICE: diff --git a/arch/microblaze/kernel/entry-nommu.S b/arch/microblaze/kernel/entry-nommu.S index ca84368570b6..34b526f59b43 100644 --- a/arch/microblaze/kernel/entry-nommu.S +++ b/arch/microblaze/kernel/entry-nommu.S @@ -115,7 +115,7 @@ ENTRY(_interrupt) /* restore r31 */ lwi r31, r0, PER_CPU(CURRENT_SAVE) /* prepare the link register, the argument and jump */ - la r15, r0, ret_from_intr - 8 + addik r15, r0, ret_from_intr - 8 addk r6, r0, r15 braid do_IRQ add r5, r0, r1 @@ -283,7 +283,7 @@ ENTRY(_user_exception) add r12, r12, r12 /* convert num -> ptr */ add r12, r12, r12 lwi r12, r12, sys_call_table /* Get function pointer */ - la r15, r0, ret_to_user-8 /* set return address */ + addik r15, r0, ret_to_user-8 /* set return address */ bra r12 /* Make the system call. */ bri 0 /* won't reach here */ 1: diff --git a/arch/microblaze/kernel/entry.S b/arch/microblaze/kernel/entry.S index 41c30cdb2704..ca15bc5c7449 100644 --- a/arch/microblaze/kernel/entry.S +++ b/arch/microblaze/kernel/entry.S @@ -33,11 +33,14 @@ #undef DEBUG -/* The size of a state save frame. */ -#define STATE_SAVE_SIZE (PT_SIZE + STATE_SAVE_ARG_SPACE) - -/* The offset of the struct pt_regs in a `state save frame' on the stack. */ -#define PTO STATE_SAVE_ARG_SPACE /* 24 the space for args */ +#ifdef DEBUG +/* Create space for syscalls counting. */ +.section .data +.global syscall_debug_table +.align 4 +syscall_debug_table: + .space (__NR_syscalls * 4) +#endif /* DEBUG */ #define C_ENTRY(name) .globl name; .align 4; name @@ -172,72 +175,72 @@ 1: #define SAVE_REGS \ - swi r2, r1, PTO+PT_R2; /* Save SDA */ \ - swi r3, r1, PTO+PT_R3; \ - swi r4, r1, PTO+PT_R4; \ - swi r5, r1, PTO+PT_R5; \ - swi r6, r1, PTO+PT_R6; \ - swi r7, r1, PTO+PT_R7; \ - swi r8, r1, PTO+PT_R8; \ - swi r9, r1, PTO+PT_R9; \ - swi r10, r1, PTO+PT_R10; \ - swi r11, r1, PTO+PT_R11; /* save clobbered regs after rval */\ - swi r12, r1, PTO+PT_R12; \ - swi r13, r1, PTO+PT_R13; /* Save SDA2 */ \ - swi r14, r1, PTO+PT_PC; /* PC, before IRQ/trap */ \ - swi r15, r1, PTO+PT_R15; /* Save LP */ \ - swi r16, r1, PTO+PT_R16; \ - swi r17, r1, PTO+PT_R17; \ - swi r18, r1, PTO+PT_R18; /* Save asm scratch reg */ \ - swi r19, r1, PTO+PT_R19; \ - swi r20, r1, PTO+PT_R20; \ - swi r21, r1, PTO+PT_R21; \ - swi r22, r1, PTO+PT_R22; \ - swi r23, r1, PTO+PT_R23; \ - swi r24, r1, PTO+PT_R24; \ - swi r25, r1, PTO+PT_R25; \ - swi r26, r1, PTO+PT_R26; \ - swi r27, r1, PTO+PT_R27; \ - swi r28, r1, PTO+PT_R28; \ - swi r29, r1, PTO+PT_R29; \ - swi r30, r1, PTO+PT_R30; \ - swi r31, r1, PTO+PT_R31; /* Save current task reg */ \ + swi r2, r1, PT_R2; /* Save SDA */ \ + swi r3, r1, PT_R3; \ + swi r4, r1, PT_R4; \ + swi r5, r1, PT_R5; \ + swi r6, r1, PT_R6; \ + swi r7, r1, PT_R7; \ + swi r8, r1, PT_R8; \ + swi r9, r1, PT_R9; \ + swi r10, r1, PT_R10; \ + swi r11, r1, PT_R11; /* save clobbered regs after rval */\ + swi r12, r1, PT_R12; \ + swi r13, r1, PT_R13; /* Save SDA2 */ \ + swi r14, r1, PT_PC; /* PC, before IRQ/trap */ \ + swi r15, r1, PT_R15; /* Save LP */ \ + swi r16, r1, PT_R16; \ + swi r17, r1, PT_R17; \ + swi r18, r1, PT_R18; /* Save asm scratch reg */ \ + swi r19, r1, PT_R19; \ + swi r20, r1, PT_R20; \ + swi r21, r1, PT_R21; \ + swi r22, r1, PT_R22; \ + swi r23, r1, PT_R23; \ + swi r24, r1, PT_R24; \ + swi r25, r1, PT_R25; \ + swi r26, r1, PT_R26; \ + swi r27, r1, PT_R27; \ + swi r28, r1, PT_R28; \ + swi r29, r1, PT_R29; \ + swi r30, r1, PT_R30; \ + swi r31, r1, PT_R31; /* Save current task reg */ \ mfs r11, rmsr; /* save MSR */ \ - swi r11, r1, PTO+PT_MSR; + swi r11, r1, PT_MSR; #define RESTORE_REGS \ - lwi r11, r1, PTO+PT_MSR; \ + lwi r11, r1, PT_MSR; \ mts rmsr , r11; \ - lwi r2, r1, PTO+PT_R2; /* restore SDA */ \ - lwi r3, r1, PTO+PT_R3; \ - lwi r4, r1, PTO+PT_R4; \ - lwi r5, r1, PTO+PT_R5; \ - lwi r6, r1, PTO+PT_R6; \ - lwi r7, r1, PTO+PT_R7; \ - lwi r8, r1, PTO+PT_R8; \ - lwi r9, r1, PTO+PT_R9; \ - lwi r10, r1, PTO+PT_R10; \ - lwi r11, r1, PTO+PT_R11; /* restore clobbered regs after rval */\ - lwi r12, r1, PTO+PT_R12; \ - lwi r13, r1, PTO+PT_R13; /* restore SDA2 */ \ - lwi r14, r1, PTO+PT_PC; /* RESTORE_LINK PC, before IRQ/trap */\ - lwi r15, r1, PTO+PT_R15; /* restore LP */ \ - lwi r16, r1, PTO+PT_R16; \ - lwi r17, r1, PTO+PT_R17; \ - lwi r18, r1, PTO+PT_R18; /* restore asm scratch reg */ \ - lwi r19, r1, PTO+PT_R19; \ - lwi r20, r1, PTO+PT_R20; \ - lwi r21, r1, PTO+PT_R21; \ - lwi r22, r1, PTO+PT_R22; \ - lwi r23, r1, PTO+PT_R23; \ - lwi r24, r1, PTO+PT_R24; \ - lwi r25, r1, PTO+PT_R25; \ - lwi r26, r1, PTO+PT_R26; \ - lwi r27, r1, PTO+PT_R27; \ - lwi r28, r1, PTO+PT_R28; \ - lwi r29, r1, PTO+PT_R29; \ - lwi r30, r1, PTO+PT_R30; \ - lwi r31, r1, PTO+PT_R31; /* Restore cur task reg */ + lwi r2, r1, PT_R2; /* restore SDA */ \ + lwi r3, r1, PT_R3; \ + lwi r4, r1, PT_R4; \ + lwi r5, r1, PT_R5; \ + lwi r6, r1, PT_R6; \ + lwi r7, r1, PT_R7; \ + lwi r8, r1, PT_R8; \ + lwi r9, r1, PT_R9; \ + lwi r10, r1, PT_R10; \ + lwi r11, r1, PT_R11; /* restore clobbered regs after rval */\ + lwi r12, r1, PT_R12; \ + lwi r13, r1, PT_R13; /* restore SDA2 */ \ + lwi r14, r1, PT_PC; /* RESTORE_LINK PC, before IRQ/trap */\ + lwi r15, r1, PT_R15; /* restore LP */ \ + lwi r16, r1, PT_R16; \ + lwi r17, r1, PT_R17; \ + lwi r18, r1, PT_R18; /* restore asm scratch reg */ \ + lwi r19, r1, PT_R19; \ + lwi r20, r1, PT_R20; \ + lwi r21, r1, PT_R21; \ + lwi r22, r1, PT_R22; \ + lwi r23, r1, PT_R23; \ + lwi r24, r1, PT_R24; \ + lwi r25, r1, PT_R25; \ + lwi r26, r1, PT_R26; \ + lwi r27, r1, PT_R27; \ + lwi r28, r1, PT_R28; \ + lwi r29, r1, PT_R29; \ + lwi r30, r1, PT_R30; \ + lwi r31, r1, PT_R31; /* Restore cur task reg */ #define SAVE_STATE \ swi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)); /* save stack */ \ @@ -250,11 +253,11 @@ lwi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)); \ /* FIXME: I can add these two lines to one */ \ /* tophys(r1,r1); */ \ - /* addik r1, r1, -STATE_SAVE_SIZE; */ \ - addik r1, r1, CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - STATE_SAVE_SIZE; \ + /* addik r1, r1, -PT_SIZE; */ \ + addik r1, r1, CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - PT_SIZE; \ SAVE_REGS \ brid 2f; \ - swi r1, r1, PTO+PT_MODE; \ + swi r1, r1, PT_MODE; \ 1: /* User-mode state save. */ \ lwi r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* get saved current */\ tophys(r1,r1); \ @@ -262,12 +265,12 @@ /* MS these three instructions can be added to one */ \ /* addik r1, r1, THREAD_SIZE; */ \ /* tophys(r1,r1); */ \ - /* addik r1, r1, -STATE_SAVE_SIZE; */ \ - addik r1, r1, THREAD_SIZE + CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - STATE_SAVE_SIZE; \ + /* addik r1, r1, -PT_SIZE; */ \ + addik r1, r1, THREAD_SIZE + CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - PT_SIZE; \ SAVE_REGS \ lwi r11, r0, TOPHYS(PER_CPU(ENTRY_SP)); \ - swi r11, r1, PTO+PT_R1; /* Store user SP. */ \ - swi r0, r1, PTO + PT_MODE; /* Was in user-mode. */ \ + swi r11, r1, PT_R1; /* Store user SP. */ \ + swi r0, r1, PT_MODE; /* Was in user-mode. */ \ /* MS: I am clearing UMS even in case when I come from kernel space */ \ clear_ums; \ 2: lwi CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); @@ -299,10 +302,10 @@ C_ENTRY(_user_exception): lwi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)); /* Reload kernel stack-ptr*/ tophys(r1,r1); - addik r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack. */ + addik r1, r1, -PT_SIZE; /* Make room on the stack. */ SAVE_REGS - swi r1, r1, PTO + PT_MODE; /* pt_regs -> kernel mode */ + swi r1, r1, PT_MODE; /* pt_regs -> kernel mode */ brid 2f; nop; /* Fill delay slot */ @@ -315,18 +318,18 @@ C_ENTRY(_user_exception): addik r1, r1, THREAD_SIZE; tophys(r1,r1); - addik r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack. */ + addik r1, r1, -PT_SIZE; /* Make room on the stack. */ SAVE_REGS - swi r0, r1, PTO + PT_R3 - swi r0, r1, PTO + PT_R4 + swi r0, r1, PT_R3 + swi r0, r1, PT_R4 - swi r0, r1, PTO + PT_MODE; /* Was in user-mode. */ + swi r0, r1, PT_MODE; /* Was in user-mode. */ lwi r11, r0, TOPHYS(PER_CPU(ENTRY_SP)); - swi r11, r1, PTO+PT_R1; /* Store user SP. */ + swi r11, r1, PT_R1; /* Store user SP. */ clear_ums; 2: lwi CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* Save away the syscall number. */ - swi r12, r1, PTO+PT_R0; + swi r12, r1, PT_R0; tovirt(r1,r1) /* where the trap should return need -8 to adjust for rtsd r15, 8*/ @@ -345,18 +348,18 @@ C_ENTRY(_user_exception): beqi r11, 4f addik r3, r0, -ENOSYS - swi r3, r1, PTO + PT_R3 + swi r3, r1, PT_R3 brlid r15, do_syscall_trace_enter - addik r5, r1, PTO + PT_R0 + addik r5, r1, PT_R0 # do_syscall_trace_enter returns the new syscall nr. addk r12, r0, r3 - lwi r5, r1, PTO+PT_R5; - lwi r6, r1, PTO+PT_R6; - lwi r7, r1, PTO+PT_R7; - lwi r8, r1, PTO+PT_R8; - lwi r9, r1, PTO+PT_R9; - lwi r10, r1, PTO+PT_R10; + lwi r5, r1, PT_R5; + lwi r6, r1, PT_R6; + lwi r7, r1, PT_R7; + lwi r8, r1, PT_R8; + lwi r9, r1, PT_R9; + lwi r10, r1, PT_R10; 4: /* Jump to the appropriate function for the system call number in r12 * (r12 is not preserved), or return an error if r12 is not valid. @@ -371,10 +374,14 @@ C_ENTRY(_user_exception): add r12, r12, r12; #ifdef DEBUG - /* Trac syscalls and stored them to r0_ram */ - lwi r3, r12, 0x400 + r0_ram + /* Trac syscalls and stored them to syscall_debug_table */ + /* The first syscall location stores total syscall number */ + lwi r3, r0, syscall_debug_table + addi r3, r3, 1 + swi r3, r0, syscall_debug_table + lwi r3, r12, syscall_debug_table addi r3, r3, 1 - swi r3, r12, 0x400 + r0_ram + swi r3, r12, syscall_debug_table #endif # Find and jump into the syscall handler. @@ -391,10 +398,10 @@ C_ENTRY(_user_exception): /* Entry point used to return from a syscall/trap */ /* We re-enable BIP bit before state restore */ C_ENTRY(ret_from_trap): - swi r3, r1, PTO + PT_R3 - swi r4, r1, PTO + PT_R4 + swi r3, r1, PT_R3 + swi r4, r1, PT_R4 - lwi r11, r1, PTO + PT_MODE; + lwi r11, r1, PT_MODE; /* See if returning to kernel mode, if so, skip resched &c. */ bnei r11, 2f; /* We're returning to user mode, so check for various conditions that @@ -406,7 +413,7 @@ C_ENTRY(ret_from_trap): beqi r11, 1f brlid r15, do_syscall_trace_leave - addik r5, r1, PTO + PT_R0 + addik r5, r1, PT_R0 1: /* We're returning to user mode, so check for various conditions that * trigger rescheduling. */ @@ -426,7 +433,7 @@ C_ENTRY(ret_from_trap): andi r11, r11, _TIF_SIGPENDING; beqi r11, 1f; /* Signals to handle, handle them */ - addik r5, r1, PTO; /* Arg 1: struct pt_regs *regs */ + addik r5, r1, 0; /* Arg 1: struct pt_regs *regs */ addi r7, r0, 1; /* Arg 3: int in_syscall */ bralid r15, do_signal; /* Handle any signals */ add r6, r0, r0; /* Arg 2: sigset_t *oldset */ @@ -437,7 +444,7 @@ C_ENTRY(ret_from_trap): VM_OFF; tophys(r1,r1); RESTORE_REGS; - addik r1, r1, STATE_SAVE_SIZE /* Clean up stack space. */ + addik r1, r1, PT_SIZE /* Clean up stack space. */ lwi r1, r1, PT_R1 - PT_SIZE;/* Restore user stack pointer. */ bri 6f; @@ -446,7 +453,7 @@ C_ENTRY(ret_from_trap): VM_OFF; tophys(r1,r1); RESTORE_REGS; - addik r1, r1, STATE_SAVE_SIZE /* Clean up stack space. */ + addik r1, r1, PT_SIZE /* Clean up stack space. */ tovirt(r1,r1); 6: TRAP_return: /* Make global symbol for debugging */ @@ -459,8 +466,8 @@ TRAP_return: /* Make global symbol for debugging */ C_ENTRY(sys_fork_wrapper): addi r5, r0, SIGCHLD /* Arg 0: flags */ - lwi r6, r1, PTO+PT_R1 /* Arg 1: child SP (use parent's) */ - addik r7, r1, PTO /* Arg 2: parent context */ + lwi r6, r1, PT_R1 /* Arg 1: child SP (use parent's) */ + addik r7, r1, 0 /* Arg 2: parent context */ add r8. r0, r0 /* Arg 3: (unused) */ add r9, r0, r0; /* Arg 4: (unused) */ brid do_fork /* Do real work (tail-call) */ @@ -480,12 +487,12 @@ C_ENTRY(ret_from_fork): C_ENTRY(sys_vfork): brid microblaze_vfork /* Do real work (tail-call) */ - addik r5, r1, PTO + addik r5, r1, 0 C_ENTRY(sys_clone): bnei r6, 1f; /* See if child SP arg (arg 1) is 0. */ - lwi r6, r1, PTO + PT_R1; /* If so, use paret's stack ptr */ -1: addik r7, r1, PTO; /* Arg 2: parent context */ + lwi r6, r1, PT_R1; /* If so, use paret's stack ptr */ +1: addik r7, r1, 0; /* Arg 2: parent context */ add r8, r0, r0; /* Arg 3: (unused) */ add r9, r0, r0; /* Arg 4: (unused) */ brid do_fork /* Do real work (tail-call) */ @@ -493,11 +500,11 @@ C_ENTRY(sys_clone): C_ENTRY(sys_execve): brid microblaze_execve; /* Do real work (tail-call).*/ - addik r8, r1, PTO; /* add user context as 4th arg */ + addik r8, r1, 0; /* add user context as 4th arg */ C_ENTRY(sys_rt_sigreturn_wrapper): brid sys_rt_sigreturn /* Do real work */ - addik r5, r1, PTO; /* add user context as 1st arg */ + addik r5, r1, 0; /* add user context as 1st arg */ /* * HW EXCEPTION rutine start @@ -508,7 +515,7 @@ C_ENTRY(full_exception_trap): addik r17, r17, -4 SAVE_STATE /* Save registers */ /* PC, before IRQ/trap - this is one instruction above */ - swi r17, r1, PTO+PT_PC; + swi r17, r1, PT_PC; tovirt(r1,r1) /* FIXME this can be store directly in PT_ESR reg. * I tested it but there is a fault */ @@ -518,7 +525,7 @@ C_ENTRY(full_exception_trap): mfs r7, rfsr; /* save FSR */ mts rfsr, r0; /* Clear sticky fsr */ rted r0, full_exception - addik r5, r1, PTO /* parameter struct pt_regs * regs */ + addik r5, r1, 0 /* parameter struct pt_regs * regs */ /* * Unaligned data trap. @@ -544,14 +551,14 @@ C_ENTRY(unaligned_data_trap): lwi r11, r0, TOPHYS(PER_CPU(ENTRY_SP)); SAVE_STATE /* Save registers.*/ /* PC, before IRQ/trap - this is one instruction above */ - swi r17, r1, PTO+PT_PC; + swi r17, r1, PT_PC; tovirt(r1,r1) /* where the trap should return need -8 to adjust for rtsd r15, 8 */ addik r15, r0, ret_from_exc-8 mfs r3, resr /* ESR */ mfs r4, rear /* EAR */ rtbd r0, _unaligned_data_exception - addik r7, r1, PTO /* parameter struct pt_regs * regs */ + addik r7, r1, 0 /* parameter struct pt_regs * regs */ /* * Page fault traps. @@ -574,30 +581,30 @@ C_ENTRY(unaligned_data_trap): C_ENTRY(page_fault_data_trap): SAVE_STATE /* Save registers.*/ /* PC, before IRQ/trap - this is one instruction above */ - swi r17, r1, PTO+PT_PC; + swi r17, r1, PT_PC; tovirt(r1,r1) /* where the trap should return need -8 to adjust for rtsd r15, 8 */ addik r15, r0, ret_from_exc-8 mfs r6, rear /* parameter unsigned long address */ mfs r7, resr /* parameter unsigned long error_code */ rted r0, do_page_fault - addik r5, r1, PTO /* parameter struct pt_regs * regs */ + addik r5, r1, 0 /* parameter struct pt_regs * regs */ C_ENTRY(page_fault_instr_trap): SAVE_STATE /* Save registers.*/ /* PC, before IRQ/trap - this is one instruction above */ - swi r17, r1, PTO+PT_PC; + swi r17, r1, PT_PC; tovirt(r1,r1) /* where the trap should return need -8 to adjust for rtsd r15, 8 */ addik r15, r0, ret_from_exc-8 mfs r6, rear /* parameter unsigned long address */ ori r7, r0, 0 /* parameter unsigned long error_code */ rted r0, do_page_fault - addik r5, r1, PTO /* parameter struct pt_regs * regs */ + addik r5, r1, 0 /* parameter struct pt_regs * regs */ /* Entry point used to return from an exception. */ C_ENTRY(ret_from_exc): - lwi r11, r1, PTO + PT_MODE; + lwi r11, r1, PT_MODE; bnei r11, 2f; /* See if returning to kernel mode, */ /* ... if so, skip resched &c. */ @@ -629,7 +636,7 @@ C_ENTRY(ret_from_exc): * complete register state. Here we save anything not saved by * the normal entry sequence, so that it may be safely restored * (in a possibly modified form) after do_signal returns. */ - addik r5, r1, PTO; /* Arg 1: struct pt_regs *regs */ + addik r5, r1, 0; /* Arg 1: struct pt_regs *regs */ addi r7, r0, 0; /* Arg 3: int in_syscall */ bralid r15, do_signal; /* Handle any signals */ add r6, r0, r0; /* Arg 2: sigset_t *oldset */ @@ -641,7 +648,7 @@ C_ENTRY(ret_from_exc): tophys(r1,r1); RESTORE_REGS; - addik r1, r1, STATE_SAVE_SIZE /* Clean up stack space. */ + addik r1, r1, PT_SIZE /* Clean up stack space. */ lwi r1, r1, PT_R1 - PT_SIZE; /* Restore user stack pointer. */ bri 6f; @@ -650,7 +657,7 @@ C_ENTRY(ret_from_exc): VM_OFF; tophys(r1,r1); RESTORE_REGS; - addik r1, r1, STATE_SAVE_SIZE /* Clean up stack space. */ + addik r1, r1, PT_SIZE /* Clean up stack space. */ tovirt(r1,r1); 6: @@ -683,10 +690,10 @@ C_ENTRY(_interrupt): tophys(r1,r1); /* MS: I have in r1 physical address where stack is */ /* save registers */ /* MS: Make room on the stack -> activation record */ - addik r1, r1, -STATE_SAVE_SIZE; + addik r1, r1, -PT_SIZE; SAVE_REGS brid 2f; - swi r1, r1, PTO + PT_MODE; /* 0 - user mode, 1 - kernel mode */ + swi r1, r1, PT_MODE; /* 0 - user mode, 1 - kernel mode */ 1: /* User-mode state save. */ /* MS: get the saved current */ @@ -696,23 +703,23 @@ C_ENTRY(_interrupt): addik r1, r1, THREAD_SIZE; tophys(r1,r1); /* save registers */ - addik r1, r1, -STATE_SAVE_SIZE; + addik r1, r1, -PT_SIZE; SAVE_REGS /* calculate mode */ - swi r0, r1, PTO + PT_MODE; + swi r0, r1, PT_MODE; lwi r11, r0, TOPHYS(PER_CPU(ENTRY_SP)); - swi r11, r1, PTO+PT_R1; + swi r11, r1, PT_R1; clear_ums; 2: lwi CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); tovirt(r1,r1) addik r15, r0, irq_call; irq_call:rtbd r0, do_IRQ; - addik r5, r1, PTO; + addik r5, r1, 0; /* MS: we are in virtual mode */ ret_from_irq: - lwi r11, r1, PTO + PT_MODE; + lwi r11, r1, PT_MODE; bnei r11, 2f; lwi r11, CURRENT_TASK, TS_THREAD_INFO; @@ -729,7 +736,7 @@ ret_from_irq: beqid r11, no_intr_resched /* Handle a signal return; Pending signals should be in r18. */ addi r7, r0, 0; /* Arg 3: int in_syscall */ - addik r5, r1, PTO; /* Arg 1: struct pt_regs *regs */ + addik r5, r1, 0; /* Arg 1: struct pt_regs *regs */ bralid r15, do_signal; /* Handle any signals */ add r6, r0, r0; /* Arg 2: sigset_t *oldset */ @@ -741,7 +748,7 @@ no_intr_resched: VM_OFF; tophys(r1,r1); RESTORE_REGS - addik r1, r1, STATE_SAVE_SIZE /* MS: Clean up stack space. */ + addik r1, r1, PT_SIZE /* MS: Clean up stack space. */ lwi r1, r1, PT_R1 - PT_SIZE; bri 6f; /* MS: Return to kernel state. */ @@ -769,7 +776,7 @@ restore: VM_OFF /* MS: turn off MMU */ tophys(r1,r1) RESTORE_REGS - addik r1, r1, STATE_SAVE_SIZE /* MS: Clean up stack space. */ + addik r1, r1, PT_SIZE /* MS: Clean up stack space. */ tovirt(r1,r1); 6: IRQ_return: /* MS: Make global symbol for debugging */ @@ -792,29 +799,29 @@ C_ENTRY(_debug_exception): lwi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)); /* Reload kernel stack-ptr*/ /* BIP bit is set on entry, no interrupts can occur */ - addik r1, r1, CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - STATE_SAVE_SIZE; + addik r1, r1, CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - PT_SIZE; SAVE_REGS; /* save all regs to pt_reg structure */ - swi r0, r1, PTO+PT_R0; /* R0 must be saved too */ - swi r14, r1, PTO+PT_R14 /* rewrite saved R14 value */ - swi r16, r1, PTO+PT_PC; /* PC and r16 are the same */ + swi r0, r1, PT_R0; /* R0 must be saved too */ + swi r14, r1, PT_R14 /* rewrite saved R14 value */ + swi r16, r1, PT_PC; /* PC and r16 are the same */ /* save special purpose registers to pt_regs */ mfs r11, rear; - swi r11, r1, PTO+PT_EAR; + swi r11, r1, PT_EAR; mfs r11, resr; - swi r11, r1, PTO+PT_ESR; + swi r11, r1, PT_ESR; mfs r11, rfsr; - swi r11, r1, PTO+PT_FSR; + swi r11, r1, PT_FSR; /* stack pointer is in physical address at it is decrease - * by STATE_SAVE_SIZE but we need to get correct R1 value */ - addik r11, r1, CONFIG_KERNEL_START - CONFIG_KERNEL_BASE_ADDR + STATE_SAVE_SIZE; - swi r11, r1, PTO+PT_R1 + * by PT_SIZE but we need to get correct R1 value */ + addik r11, r1, CONFIG_KERNEL_START - CONFIG_KERNEL_BASE_ADDR + PT_SIZE; + swi r11, r1, PT_R1 /* MS: r31 - current pointer isn't changed */ tovirt(r1,r1) #ifdef CONFIG_KGDB - addi r5, r1, PTO /* pass pt_reg address as the first arg */ - la r15, r0, dbtrap_call; /* return address */ + addi r5, r1, 0 /* pass pt_reg address as the first arg */ + addik r15, r0, dbtrap_call; /* return address */ rtbd r0, microblaze_kgdb_break nop; #endif @@ -829,16 +836,16 @@ C_ENTRY(_debug_exception): addik r1, r1, THREAD_SIZE; /* calculate kernel stack pointer */ tophys(r1,r1); - addik r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack. */ + addik r1, r1, -PT_SIZE; /* Make room on the stack. */ SAVE_REGS; - swi r16, r1, PTO+PT_PC; /* Save LP */ - swi r0, r1, PTO + PT_MODE; /* Was in user-mode. */ + swi r16, r1, PT_PC; /* Save LP */ + swi r0, r1, PT_MODE; /* Was in user-mode. */ lwi r11, r0, TOPHYS(PER_CPU(ENTRY_SP)); - swi r11, r1, PTO+PT_R1; /* Store user SP. */ + swi r11, r1, PT_R1; /* Store user SP. */ lwi CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); tovirt(r1,r1) set_vms; - addik r5, r1, PTO; + addik r5, r1, 0; addik r15, r0, dbtrap_call; dbtrap_call: /* Return point for kernel/user entry + 8 because of rtsd r15, 8 */ rtbd r0, sw_exception @@ -846,7 +853,7 @@ dbtrap_call: /* Return point for kernel/user entry + 8 because of rtsd r15, 8 */ /* MS: The first instruction for the second part of the gdb/kgdb */ set_bip; /* Ints masked for state restore */ - lwi r11, r1, PTO + PT_MODE; + lwi r11, r1, PT_MODE; bnei r11, 2f; /* MS: Return to user space - gdb */ /* Get current task ptr into r11 */ @@ -865,7 +872,7 @@ dbtrap_call: /* Return point for kernel/user entry + 8 because of rtsd r15, 8 */ andi r11, r11, _TIF_SIGPENDING; beqi r11, 1f; /* Signals to handle, handle them */ - addik r5, r1, PTO; /* Arg 1: struct pt_regs *regs */ + addik r5, r1, 0; /* Arg 1: struct pt_regs *regs */ addi r7, r0, 0; /* Arg 3: int in_syscall */ bralid r15, do_signal; /* Handle any signals */ add r6, r0, r0; /* Arg 2: sigset_t *oldset */ @@ -876,7 +883,7 @@ dbtrap_call: /* Return point for kernel/user entry + 8 because of rtsd r15, 8 */ tophys(r1,r1); /* MS: Restore all regs */ RESTORE_REGS - addik r1, r1, STATE_SAVE_SIZE /* Clean up stack space */ + addik r1, r1, PT_SIZE /* Clean up stack space */ lwi r1, r1, PT_R1 - PT_SIZE; /* Restore user stack pointer */ DBTRAP_return_user: /* MS: Make global symbol for debugging */ rtbd r16, 0; /* MS: Instructions to return from a debug trap */ @@ -887,9 +894,9 @@ DBTRAP_return_user: /* MS: Make global symbol for debugging */ tophys(r1,r1); /* MS: Restore all regs */ RESTORE_REGS - lwi r14, r1, PTO+PT_R14; - lwi r16, r1, PTO+PT_PC; - addik r1, r1, STATE_SAVE_SIZE; /* MS: Clean up stack space */ + lwi r14, r1, PT_R14; + lwi r16, r1, PT_PC; + addik r1, r1, PT_SIZE; /* MS: Clean up stack space */ tovirt(r1,r1); DBTRAP_return_kernel: /* MS: Make global symbol for debugging */ rtbd r16, 0; /* MS: Instructions to return from a debug trap */ @@ -981,20 +988,22 @@ ENTRY(_switch_to) nop ENTRY(_reset) - brai 0x70; /* Jump back to FS-boot */ + brai 0; /* Jump to reset vector */ /* These are compiled and loaded into high memory, then * copied into place in mach_early_setup */ .section .init.ivt, "ax" +#if CONFIG_MANUAL_RESET_VECTOR .org 0x0 - /* this is very important - here is the reset vector */ - /* in current MMU branch you don't care what is here - it is - * used from bootloader site - but this is correct for FS-BOOT */ - brai 0x70 - nop + brai CONFIG_MANUAL_RESET_VECTOR +#endif + .org 0x8 brai TOPHYS(_user_exception); /* syscall handler */ + .org 0x10 brai TOPHYS(_interrupt); /* Interrupt handler */ + .org 0x18 brai TOPHYS(_debug_exception); /* debug trap handler */ + .org 0x20 brai TOPHYS(_hw_exception_handler); /* HW exception handler */ .section .rodata,"a" diff --git a/arch/microblaze/kernel/exceptions.c b/arch/microblaze/kernel/exceptions.c index a7fa6ae76d89..66fad2301221 100644 --- a/arch/microblaze/kernel/exceptions.c +++ b/arch/microblaze/kernel/exceptions.c @@ -50,7 +50,7 @@ void die(const char *str, struct pt_regs *fp, long err) } /* for user application debugging */ -void sw_exception(struct pt_regs *regs) +asmlinkage void sw_exception(struct pt_regs *regs) { _exception(SIGTRAP, regs, TRAP_BRKPT, regs->r16); flush_dcache_range(regs->r16, regs->r16 + 0x4); diff --git a/arch/microblaze/kernel/head.S b/arch/microblaze/kernel/head.S index 778a5ce2e4fc..77320b8fc16a 100644 --- a/arch/microblaze/kernel/head.S +++ b/arch/microblaze/kernel/head.S @@ -39,7 +39,7 @@ #include <asm/mmu.h> #include <asm/processor.h> -.data +.section .data .global empty_zero_page .align 12 empty_zero_page: @@ -50,6 +50,11 @@ swapper_pg_dir: #endif /* CONFIG_MMU */ +.section .rodata +.align 4 +endian_check: + .word 1 + __HEAD ENTRY(_start) #if CONFIG_KERNEL_BASE_ADDR == 0 @@ -79,10 +84,7 @@ real_start: /* Does r7 point to a valid FDT? Load HEADER magic number */ /* Run time Big/Little endian platform */ /* Save 1 as word and load byte - 0 - BIG, 1 - LITTLE */ - addik r11, r0, 0x1 /* BIG/LITTLE checking value */ - /* __bss_start will be zeroed later - it is just temp location */ - swi r11, r0, TOPHYS(__bss_start) - lbui r11, r0, TOPHYS(__bss_start) + lbui r11, r0, TOPHYS(endian_check) beqid r11, big_endian /* DO NOT break delay stop dependency */ lw r11, r0, r7 /* Big endian load in delay slot */ lwr r11, r0, r7 /* Little endian load */ @@ -222,26 +224,26 @@ start_here: #endif /* CONFIG_MMU */ /* Initialize small data anchors */ - la r13, r0, _KERNEL_SDA_BASE_ - la r2, r0, _KERNEL_SDA2_BASE_ + addik r13, r0, _KERNEL_SDA_BASE_ + addik r2, r0, _KERNEL_SDA2_BASE_ /* Initialize stack pointer */ - la r1, r0, init_thread_union + THREAD_SIZE - 4 + addik r1, r0, init_thread_union + THREAD_SIZE - 4 /* Initialize r31 with current task address */ - la r31, r0, init_task + addik r31, r0, init_task /* * Call platform dependent initialize function. * Please see $(ARCH)/mach-$(SUBARCH)/setup.c for * the function. */ - la r9, r0, machine_early_init + addik r9, r0, machine_early_init brald r15, r9 nop #ifndef CONFIG_MMU - la r15, r0, machine_halt + addik r15, r0, machine_halt braid start_kernel nop #else diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S index 782680de3121..56572e923a83 100644 --- a/arch/microblaze/kernel/hw_exception_handler.S +++ b/arch/microblaze/kernel/hw_exception_handler.S @@ -77,6 +77,8 @@ #include <asm/signal.h> #include <asm/asm-offsets.h> +#undef DEBUG + /* Helpful Macros */ #define NUM_TO_REG(num) r ## num @@ -91,7 +93,7 @@ lwi r6, r1, PT_R6; \ lwi r11, r1, PT_R11; \ lwi r31, r1, PT_R31; \ - lwi r1, r0, TOPHYS(r0_ram + 0); + lwi r1, r1, PT_R1; #endif /* CONFIG_MMU */ #define LWREG_NOP \ @@ -206,8 +208,8 @@ * | . | * | . | * - * NO_MMU kernel use the same r0_ram pointed space - look to vmlinux.lds.S - * which is used for storing register values - old style was, that value were + * MMU kernel uses the same 'pt_pool_space' pointed space + * which is used for storing register values - noMMu style was, that values were * stored in stack but in case of failure you lost information about register. * Currently you can see register value in memory in specific place. * In compare to with previous solution the speed should be the same. @@ -226,8 +228,22 @@ */ /* wrappers to restore state before coming to entry.S */ - #ifdef CONFIG_MMU +.section .data +.align 4 +pt_pool_space: + .space PT_SIZE + +#ifdef DEBUG +/* Create space for exception counting. */ +.section .data +.global exception_debug_table +.align 4 +exception_debug_table: + /* Look at exception vector table. There is 32 exceptions * word size */ + .space (32 * 4) +#endif /* DEBUG */ + .section .rodata .align 4 _MB_HW_ExceptionVectorTable: @@ -287,10 +303,10 @@ _hw_exception_handler: #ifndef CONFIG_MMU addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */ #else - swi r1, r0, TOPHYS(r0_ram + 0); /* GET_SP */ + swi r1, r0, TOPHYS(pt_pool_space + PT_R1); /* GET_SP */ /* Save date to kernel memory. Here is the problem * when you came from user space */ - ori r1, r0, TOPHYS(r0_ram + 28); + ori r1, r0, TOPHYS(pt_pool_space); #endif swi r3, r1, PT_R3 swi r4, r1, PT_R4 @@ -329,12 +345,12 @@ not_in_delay_slot: #ifdef DEBUG /* counting which exception happen */ - lwi r5, r0, 0x200 + TOPHYS(r0_ram) + lwi r5, r0, TOPHYS(exception_debug_table) addi r5, r5, 1 - swi r5, r0, 0x200 + TOPHYS(r0_ram) - lwi r5, r6, 0x200 + TOPHYS(r0_ram) + swi r5, r0, TOPHYS(exception_debug_table) + lwi r5, r6, TOPHYS(exception_debug_table) addi r5, r5, 1 - swi r5, r6, 0x200 + TOPHYS(r0_ram) + swi r5, r6, TOPHYS(exception_debug_table) #endif /* end */ /* Load the HW Exception vector */ @@ -474,7 +490,7 @@ ex_lw_tail: /* Get the destination register number into r5 */ lbui r5, r0, TOPHYS(ex_reg_op); /* Form load_word jump table offset (lw_table + (8 * regnum)) */ - la r6, r0, TOPHYS(lw_table); + addik r6, r0, TOPHYS(lw_table); addk r5, r5, r5; addk r5, r5, r5; addk r5, r5, r5; @@ -485,7 +501,7 @@ ex_sw: /* Get the destination register number into r5 */ lbui r5, r0, TOPHYS(ex_reg_op); /* Form store_word jump table offset (sw_table + (8 * regnum)) */ - la r6, r0, TOPHYS(sw_table); + addik r6, r0, TOPHYS(sw_table); add r5, r5, r5; add r5, r5, r5; add r5, r5, r5; @@ -896,7 +912,7 @@ ex_lw_vm: beqid r6, ex_lhw_vm; load1: lbui r5, r4, 0; /* Exception address in r4 - delay slot */ /* Load a word, byte-by-byte from destination address and save it in tmp space*/ - la r6, r0, ex_tmp_data_loc_0; + addik r6, r0, ex_tmp_data_loc_0; sbi r5, r6, 0; load2: lbui r5, r4, 1; sbi r5, r6, 1; @@ -910,7 +926,7 @@ load4: lbui r5, r4, 3; ex_lhw_vm: /* Load a half-word, byte-by-byte from destination address and * save it in tmp space */ - la r6, r0, ex_tmp_data_loc_0; + addik r6, r0, ex_tmp_data_loc_0; sbi r5, r6, 0; load5: lbui r5, r4, 1; sbi r5, r6, 1; @@ -926,7 +942,7 @@ ex_sw_vm: addik r5, r8, sw_table_vm; bra r5; ex_sw_tail_vm: - la r5, r0, ex_tmp_data_loc_0; + addik r5, r0, ex_tmp_data_loc_0; beqid r6, ex_shw_vm; swi r3, r5, 0; /* Get the word - delay slot */ /* Store the word, byte-by-byte into destination address */ @@ -969,7 +985,7 @@ ex_unaligned_fixup: addik r7, r0, SIGSEGV /* call bad_page_fault for finding aligned fixup, fixup address is saved * in PT_PC which is used as return address from exception */ - la r15, r0, ret_from_exc-8 /* setup return address */ + addik r15, r0, ret_from_exc-8 /* setup return address */ brid bad_page_fault nop diff --git a/arch/microblaze/kernel/intc.c b/arch/microblaze/kernel/intc.c index d61ea33aff7c..e4661285118e 100644 --- a/arch/microblaze/kernel/intc.c +++ b/arch/microblaze/kernel/intc.c @@ -40,59 +40,46 @@ unsigned int nr_irq; #define MER_ME (1<<0) #define MER_HIE (1<<1) -static void intc_enable_or_unmask(unsigned int irq) +static void intc_enable_or_unmask(struct irq_data *d) { - unsigned long mask = 1 << irq; - pr_debug("enable_or_unmask: %d\n", irq); + unsigned long mask = 1 << d->irq; + pr_debug("enable_or_unmask: %d\n", d->irq); out_be32(INTC_BASE + SIE, mask); /* ack level irqs because they can't be acked during * ack function since the handle_level_irq function * acks the irq before calling the interrupt handler */ - if (irq_desc[irq].status & IRQ_LEVEL) + if (irq_to_desc(d->irq)->status & IRQ_LEVEL) out_be32(INTC_BASE + IAR, mask); } -static void intc_disable_or_mask(unsigned int irq) +static void intc_disable_or_mask(struct irq_data *d) { - pr_debug("disable: %d\n", irq); - out_be32(INTC_BASE + CIE, 1 << irq); + pr_debug("disable: %d\n", d->irq); + out_be32(INTC_BASE + CIE, 1 << d->irq); } -static void intc_ack(unsigned int irq) +static void intc_ack(struct irq_data *d) { - pr_debug("ack: %d\n", irq); - out_be32(INTC_BASE + IAR, 1 << irq); + pr_debug("ack: %d\n", d->irq); + out_be32(INTC_BASE + IAR, 1 << d->irq); } -static void intc_mask_ack(unsigned int irq) +static void intc_mask_ack(struct irq_data *d) { - unsigned long mask = 1 << irq; - pr_debug("disable_and_ack: %d\n", irq); + unsigned long mask = 1 << d->irq; + pr_debug("disable_and_ack: %d\n", d->irq); out_be32(INTC_BASE + CIE, mask); out_be32(INTC_BASE + IAR, mask); } -static void intc_end(unsigned int irq) -{ - unsigned long mask = 1 << irq; - pr_debug("end: %d\n", irq); - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { - out_be32(INTC_BASE + SIE, mask); - /* ack level sensitive intr */ - if (irq_desc[irq].status & IRQ_LEVEL) - out_be32(INTC_BASE + IAR, mask); - } -} - static struct irq_chip intc_dev = { .name = "Xilinx INTC", - .unmask = intc_enable_or_unmask, - .mask = intc_disable_or_mask, - .ack = intc_ack, - .mask_ack = intc_mask_ack, - .end = intc_end, + .irq_unmask = intc_enable_or_unmask, + .irq_mask = intc_disable_or_mask, + .irq_ack = intc_ack, + .irq_mask_ack = intc_mask_ack, }; unsigned int get_irq(struct pt_regs *regs) @@ -172,11 +159,11 @@ void __init init_IRQ(void) if (intr_type & (0x00000001 << i)) { set_irq_chip_and_handler_name(i, &intc_dev, handle_edge_irq, intc_dev.name); - irq_desc[i].status &= ~IRQ_LEVEL; + irq_clear_status_flags(i, IRQ_LEVEL); } else { set_irq_chip_and_handler_name(i, &intc_dev, handle_level_irq, intc_dev.name); - irq_desc[i].status |= IRQ_LEVEL; + irq_set_status_flags(i, IRQ_LEVEL); } } } diff --git a/arch/microblaze/kernel/irq.c b/arch/microblaze/kernel/irq.c index a9345fb4906a..098822413729 100644 --- a/arch/microblaze/kernel/irq.c +++ b/arch/microblaze/kernel/irq.c @@ -50,6 +50,7 @@ next_irq: int show_interrupts(struct seq_file *p, void *v) { int i = *(loff_t *) v, j; + struct irq_desc *desc; struct irqaction *action; unsigned long flags; @@ -61,8 +62,9 @@ int show_interrupts(struct seq_file *p, void *v) } if (i < nr_irq) { - raw_spin_lock_irqsave(&irq_desc[i].lock, flags); - action = irq_desc[i].action; + desc = irq_to_desc(i); + raw_spin_lock_irqsave(&desc->lock, flags); + action = desc->action; if (!action) goto skip; seq_printf(p, "%3d: ", i); @@ -72,9 +74,9 @@ int show_interrupts(struct seq_file *p, void *v) for_each_online_cpu(j) seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); #endif - seq_printf(p, " %8s", irq_desc[i].status & + seq_printf(p, " %8s", desc->status & IRQ_LEVEL ? "level" : "edge"); - seq_printf(p, " %8s", irq_desc[i].chip->name); + seq_printf(p, " %8s", desc->irq_data.chip->name); seq_printf(p, " %s", action->name); for (action = action->next; action; action = action->next) @@ -82,7 +84,7 @@ int show_interrupts(struct seq_file *p, void *v) seq_putc(p, '\n'); skip: - raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); + raw_spin_unlock_irqrestore(&desc->lock, flags); } return 0; } diff --git a/arch/microblaze/kernel/microblaze_ksyms.c b/arch/microblaze/kernel/microblaze_ksyms.c index 5cb034174005..49faeb429599 100644 --- a/arch/microblaze/kernel/microblaze_ksyms.c +++ b/arch/microblaze/kernel/microblaze_ksyms.c @@ -24,6 +24,7 @@ extern char *_ebss; EXPORT_SYMBOL_GPL(_ebss); + #ifdef CONFIG_FUNCTION_TRACER extern void _mcount(void); EXPORT_SYMBOL(_mcount); @@ -45,3 +46,14 @@ EXPORT_SYMBOL(empty_zero_page); #endif EXPORT_SYMBOL(mbc); + +extern void __divsi3(void); +EXPORT_SYMBOL(__divsi3); +extern void __modsi3(void); +EXPORT_SYMBOL(__modsi3); +extern void __mulsi3(void); +EXPORT_SYMBOL(__mulsi3); +extern void __udivsi3(void); +EXPORT_SYMBOL(__udivsi3); +extern void __umodsi3(void); +EXPORT_SYMBOL(__umodsi3); diff --git a/arch/microblaze/kernel/process.c b/arch/microblaze/kernel/process.c index ba7c4b16ed35..968648a81c1e 100644 --- a/arch/microblaze/kernel/process.c +++ b/arch/microblaze/kernel/process.c @@ -159,7 +159,7 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, } /* FIXME STATE_SAVE_PT_OFFSET; */ - ti->cpu_context.r1 = (unsigned long)childregs - STATE_SAVE_ARG_SPACE; + ti->cpu_context.r1 = (unsigned long)childregs; /* we should consider the fact that childregs is a copy of the parent * regs which were saved immediately after entering the kernel state * before enabling VM. This MSR will be restored in switch_to and diff --git a/arch/microblaze/kernel/prom.c b/arch/microblaze/kernel/prom.c index bceaa5543e39..00ee90f08343 100644 --- a/arch/microblaze/kernel/prom.c +++ b/arch/microblaze/kernel/prom.c @@ -59,7 +59,7 @@ static int __init early_init_dt_scan_serial(unsigned long node, { unsigned long l; char *p; - int *addr; + const __be32 *addr; pr_debug("search \"serial\", depth: %d, uname: %s\n", depth, uname); diff --git a/arch/microblaze/kernel/prom_parse.c b/arch/microblaze/kernel/prom_parse.c index 9ae24f4b882b..47187cc2cf00 100644 --- a/arch/microblaze/kernel/prom_parse.c +++ b/arch/microblaze/kernel/prom_parse.c @@ -2,88 +2,11 @@ #include <linux/kernel.h> #include <linux/string.h> -#include <linux/pci_regs.h> #include <linux/module.h> #include <linux/ioport.h> #include <linux/etherdevice.h> #include <linux/of_address.h> #include <asm/prom.h> -#include <asm/pci-bridge.h> - -#ifdef CONFIG_PCI -int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq) -{ - struct device_node *dn, *ppnode; - struct pci_dev *ppdev; - u32 lspec; - u32 laddr[3]; - u8 pin; - int rc; - - /* Check if we have a device node, if yes, fallback to standard OF - * parsing - */ - dn = pci_device_to_OF_node(pdev); - if (dn) - return of_irq_map_one(dn, 0, out_irq); - - /* Ok, we don't, time to have fun. Let's start by building up an - * interrupt spec. we assume #interrupt-cells is 1, which is standard - * for PCI. If you do different, then don't use that routine. - */ - rc = pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &pin); - if (rc != 0) - return rc; - /* No pin, exit */ - if (pin == 0) - return -ENODEV; - - /* Now we walk up the PCI tree */ - lspec = pin; - for (;;) { - /* Get the pci_dev of our parent */ - ppdev = pdev->bus->self; - - /* Ouch, it's a host bridge... */ - if (ppdev == NULL) { - struct pci_controller *host; - host = pci_bus_to_host(pdev->bus); - ppnode = host ? host->dn : NULL; - /* No node for host bridge ? give up */ - if (ppnode == NULL) - return -EINVAL; - } else - /* We found a P2P bridge, check if it has a node */ - ppnode = pci_device_to_OF_node(ppdev); - - /* Ok, we have found a parent with a device-node, hand over to - * the OF parsing code. - * We build a unit address from the linux device to be used for - * resolution. Note that we use the linux bus number which may - * not match your firmware bus numbering. - * Fortunately, in most cases, interrupt-map-mask doesn't - * include the bus number as part of the matching. - * You should still be careful about that though if you intend - * to rely on this function (you ship a firmware that doesn't - * create device nodes for all PCI devices). - */ - if (ppnode) - break; - - /* We can only get here if we hit a P2P bridge with no node, - * let's do standard swizzling and try again - */ - lspec = pci_swizzle_interrupt_pin(pdev, lspec); - pdev = ppdev; - } - - laddr[0] = (pdev->bus->number << 16) - | (pdev->devfn << 8); - laddr[1] = laddr[2] = 0; - return of_irq_map_raw(ppnode, &lspec, 1, laddr, out_irq); -} -EXPORT_SYMBOL_GPL(of_irq_map_pci); -#endif /* CONFIG_PCI */ void of_parse_dma_window(struct device_node *dn, const void *dma_window_prop, unsigned long *busno, unsigned long *phys, unsigned long *size) diff --git a/arch/microblaze/kernel/ptrace.c b/arch/microblaze/kernel/ptrace.c index 05ac8cc975d5..6a8e0cc5c57d 100644 --- a/arch/microblaze/kernel/ptrace.c +++ b/arch/microblaze/kernel/ptrace.c @@ -39,6 +39,7 @@ #include <linux/uaccess.h> #include <asm/asm-offsets.h> #include <asm/cacheflush.h> +#include <asm/syscall.h> #include <asm/io.h> /* Returns the address where the register at REG_OFFS in P is stashed away. */ @@ -123,7 +124,7 @@ long arch_ptrace(struct task_struct *child, long request, rval = -EIO; if (rval == 0 && request == PTRACE_PEEKUSR) - rval = put_user(val, (unsigned long *)data); + rval = put_user(val, (unsigned long __user *)data); break; default: rval = ptrace_request(child, request, addr, data); diff --git a/arch/microblaze/kernel/setup.c b/arch/microblaze/kernel/setup.c index 9312fbb37efd..8e2c09b7ff26 100644 --- a/arch/microblaze/kernel/setup.c +++ b/arch/microblaze/kernel/setup.c @@ -95,7 +95,8 @@ inline unsigned get_romfs_len(unsigned *addr) void __init machine_early_init(const char *cmdline, unsigned int ram, unsigned int fdt, unsigned int msr) { - unsigned long *src, *dst = (unsigned long *)0x0; + unsigned long *src, *dst; + unsigned int offset = 0; /* If CONFIG_MTD_UCLINUX is defined, assume ROMFS is at the * end of kernel. There are two position which we want to check. @@ -168,7 +169,14 @@ void __init machine_early_init(const char *cmdline, unsigned int ram, "CPU have it %x\n", msr); #endif - for (src = __ivt_start; src < __ivt_end; src++, dst++) + /* Do not copy reset vectors. offset = 0x2 means skip the first + * two instructions. dst is pointer to MB vectors which are placed + * in block ram. If you want to copy reset vector setup offset to 0x0 */ +#if !CONFIG_MANUAL_RESET_VECTOR + offset = 0x2; +#endif + dst = (unsigned long *) (offset * sizeof(u32)); + for (src = __ivt_start + offset; src < __ivt_end; src++, dst++) *dst = *src; /* Initialize global data */ diff --git a/arch/microblaze/kernel/signal.c b/arch/microblaze/kernel/signal.c index d8d3bb396cd6..599671168980 100644 --- a/arch/microblaze/kernel/signal.c +++ b/arch/microblaze/kernel/signal.c @@ -93,7 +93,7 @@ static int restore_sigcontext(struct pt_regs *regs, asmlinkage long sys_rt_sigreturn(struct pt_regs *regs) { struct rt_sigframe __user *frame = - (struct rt_sigframe __user *)(regs->r1 + STATE_SAVE_ARG_SPACE); + (struct rt_sigframe __user *)(regs->r1); sigset_t set; int rval; @@ -197,8 +197,8 @@ static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, /* Create the ucontext. */ err |= __put_user(0, &frame->uc.uc_flags); - err |= __put_user(0, &frame->uc.uc_link); - err |= __put_user((void *)current->sas_ss_sp, + err |= __put_user(NULL, &frame->uc.uc_link); + err |= __put_user((void __user *)current->sas_ss_sp, &frame->uc.uc_stack.ss_sp); err |= __put_user(sas_ss_flags(regs->r1), &frame->uc.uc_stack.ss_flags); @@ -247,7 +247,7 @@ static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, goto give_sigsegv; /* Set up registers for signal handler */ - regs->r1 = (unsigned long) frame - STATE_SAVE_ARG_SPACE; + regs->r1 = (unsigned long) frame; /* Signal handler args: */ regs->r5 = signal; /* arg 0: signum */ diff --git a/arch/microblaze/kernel/sys_microblaze.c b/arch/microblaze/kernel/sys_microblaze.c index 2250fe9d269b..e5b154f24f85 100644 --- a/arch/microblaze/kernel/sys_microblaze.c +++ b/arch/microblaze/kernel/sys_microblaze.c @@ -40,7 +40,8 @@ asmlinkage long microblaze_vfork(struct pt_regs *regs) regs, 0, NULL, NULL); } -asmlinkage long microblaze_clone(int flags, unsigned long stack, struct pt_regs *regs) +asmlinkage long microblaze_clone(int flags, unsigned long stack, + struct pt_regs *regs) { if (!stack) stack = regs->r1; diff --git a/arch/microblaze/kernel/timer.c b/arch/microblaze/kernel/timer.c index a5aa33db1df3..d8a214f11ac2 100644 --- a/arch/microblaze/kernel/timer.c +++ b/arch/microblaze/kernel/timer.c @@ -38,8 +38,8 @@ static unsigned int timer_baseaddr; #define TIMER_BASE timer_baseaddr #endif -unsigned int freq_div_hz; -unsigned int timer_clock_freq; +static unsigned int freq_div_hz; +static unsigned int timer_clock_freq; #define TCSR0 (0x00) #define TLR0 (0x04) @@ -202,7 +202,7 @@ static struct cyclecounter microblaze_cc = { .shift = 8, }; -int __init init_microblaze_timecounter(void) +static int __init init_microblaze_timecounter(void) { microblaze_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC, microblaze_cc.shift); diff --git a/arch/microblaze/kernel/unwind.c b/arch/microblaze/kernel/unwind.c index fefac5c33586..9781a528cfc9 100644 --- a/arch/microblaze/kernel/unwind.c +++ b/arch/microblaze/kernel/unwind.c @@ -183,7 +183,7 @@ static inline void unwind_trap(struct task_struct *task, unsigned long pc, * @trace : Where to store stack backtrace (PC values). * NULL == print backtrace to kernel log */ -void microblaze_unwind_inner(struct task_struct *task, +static void microblaze_unwind_inner(struct task_struct *task, unsigned long pc, unsigned long fp, unsigned long leaf_return, struct stack_trace *trace) diff --git a/arch/microblaze/kernel/vmlinux.lds.S b/arch/microblaze/kernel/vmlinux.lds.S index 3451bdec9f05..ac0e1a5d4782 100644 --- a/arch/microblaze/kernel/vmlinux.lds.S +++ b/arch/microblaze/kernel/vmlinux.lds.S @@ -70,11 +70,6 @@ SECTIONS { RW_DATA_SECTION(32, PAGE_SIZE, THREAD_SIZE) _edata = . ; - /* Reserve some low RAM for r0 based memory references */ - . = ALIGN(0x4) ; - r0_ram = . ; - . = . + PAGE_SIZE; /* a page should be enough */ - /* Under the microblaze ABI, .sdata and .sbss must be contiguous */ . = ALIGN(8); .sdata : AT(ADDR(.sdata) - LOAD_OFFSET) { diff --git a/arch/microblaze/lib/muldi3.c b/arch/microblaze/lib/muldi3.c index d4860e154d29..0585bccb7fad 100644 --- a/arch/microblaze/lib/muldi3.c +++ b/arch/microblaze/lib/muldi3.c @@ -58,3 +58,4 @@ DWtype __muldi3(DWtype u, DWtype v) return w.ll; } +EXPORT_SYMBOL(__muldi3); diff --git a/arch/microblaze/mm/consistent.c b/arch/microblaze/mm/consistent.c index 5a59dad62bd2..a1e2e18e0961 100644 --- a/arch/microblaze/mm/consistent.c +++ b/arch/microblaze/mm/consistent.c @@ -59,7 +59,7 @@ * uncached region. This will no doubt cause big problems if memory allocated * here is not also freed properly. -- JW */ -void *consistent_alloc(int gfp, size_t size, dma_addr_t *dma_handle) +void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *dma_handle) { unsigned long order, vaddr; void *ret; diff --git a/arch/microblaze/mm/fault.c b/arch/microblaze/mm/fault.c index 57bd2a09610c..ae97d2ccdc22 100644 --- a/arch/microblaze/mm/fault.c +++ b/arch/microblaze/mm/fault.c @@ -48,7 +48,7 @@ static int store_updates_sp(struct pt_regs *regs) { unsigned int inst; - if (get_user(inst, (unsigned int *)regs->pc)) + if (get_user(inst, (unsigned int __user *)regs->pc)) return 0; /* check for 1 in the rD field */ if (((inst >> 21) & 0x1f) != 1) diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c index e363615d6798..1e01a1253631 100644 --- a/arch/microblaze/pci/pci-common.c +++ b/arch/microblaze/pci/pci-common.c @@ -29,6 +29,7 @@ #include <linux/slab.h> #include <linux/of.h> #include <linux/of_address.h> +#include <linux/of_pci.h> #include <asm/processor.h> #include <asm/io.h> diff --git a/arch/microblaze/pci/pci_32.c b/arch/microblaze/pci/pci_32.c index 3c3d808d7ce0..92728a6cfd80 100644 --- a/arch/microblaze/pci/pci_32.c +++ b/arch/microblaze/pci/pci_32.c @@ -332,6 +332,7 @@ static void __devinit pcibios_scan_phb(struct pci_controller *hose) hose->global_number); return; } + bus.dev->of_node = of_node_get(node); bus->secondary = hose->first_busno; hose->bus = bus; diff --git a/arch/mips/include/asm/futex.h b/arch/mips/include/asm/futex.h index b9cce90346cf..6ebf1734b411 100644 --- a/arch/mips/include/asm/futex.h +++ b/arch/mips/include/asm/futex.h @@ -75,7 +75,7 @@ } static inline int -futex_atomic_op_inuser(int encoded_op, int __user *uaddr) +futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr) { int op = (encoded_op >> 28) & 7; int cmp = (encoded_op >> 24) & 15; @@ -85,7 +85,7 @@ futex_atomic_op_inuser(int encoded_op, int __user *uaddr) if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) oparg = 1 << oparg; - if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int))) + if (! access_ok (VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; pagefault_disable(); @@ -132,11 +132,13 @@ futex_atomic_op_inuser(int encoded_op, int __user *uaddr) } static inline int -futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) +futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) { - int retval; + int ret = 0; + u32 val; - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; if (cpu_has_llsc && R10000_LLSC_WAR) { @@ -145,25 +147,25 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) " .set push \n" " .set noat \n" " .set mips3 \n" - "1: ll %0, %2 \n" - " bne %0, %z3, 3f \n" + "1: ll %1, %3 \n" + " bne %1, %z4, 3f \n" " .set mips0 \n" - " move $1, %z4 \n" + " move $1, %z5 \n" " .set mips3 \n" - "2: sc $1, %1 \n" + "2: sc $1, %2 \n" " beqzl $1, 1b \n" __WEAK_LLSC_MB "3: \n" " .set pop \n" " .section .fixup,\"ax\" \n" - "4: li %0, %5 \n" + "4: li %0, %6 \n" " j 3b \n" " .previous \n" " .section __ex_table,\"a\" \n" " "__UA_ADDR "\t1b, 4b \n" " "__UA_ADDR "\t2b, 4b \n" " .previous \n" - : "=&r" (retval), "=R" (*uaddr) + : "+r" (ret), "=&r" (val), "=R" (*uaddr) : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT) : "memory"); } else if (cpu_has_llsc) { @@ -172,31 +174,32 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) " .set push \n" " .set noat \n" " .set mips3 \n" - "1: ll %0, %2 \n" - " bne %0, %z3, 3f \n" + "1: ll %1, %3 \n" + " bne %1, %z4, 3f \n" " .set mips0 \n" - " move $1, %z4 \n" + " move $1, %z5 \n" " .set mips3 \n" - "2: sc $1, %1 \n" + "2: sc $1, %2 \n" " beqz $1, 1b \n" __WEAK_LLSC_MB "3: \n" " .set pop \n" " .section .fixup,\"ax\" \n" - "4: li %0, %5 \n" + "4: li %0, %6 \n" " j 3b \n" " .previous \n" " .section __ex_table,\"a\" \n" " "__UA_ADDR "\t1b, 4b \n" " "__UA_ADDR "\t2b, 4b \n" " .previous \n" - : "=&r" (retval), "=R" (*uaddr) + : "+r" (ret), "=&r" (val), "=R" (*uaddr) : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT) : "memory"); } else return -ENOSYS; - return retval; + *uval = val; + return ret; } #endif diff --git a/arch/mips/include/asm/ioctls.h b/arch/mips/include/asm/ioctls.h index d967b8997626..92403c3d6007 100644 --- a/arch/mips/include/asm/ioctls.h +++ b/arch/mips/include/asm/ioctls.h @@ -85,6 +85,7 @@ #define TIOCSPTLCK _IOW('T', 0x31, int) /* Lock/unlock Pty */ #define TIOCGDEV _IOR('T', 0x32, unsigned int) /* Get primary device node of /dev/console */ #define TIOCSIG _IOW('T', 0x36, int) /* Generate signal on Pty slave */ +#define TIOCVHANGUP 0x5437 /* I hope the range from 0x5480 on is free ... */ #define TIOCSCTTY 0x5480 /* become controlling tty */ diff --git a/arch/mips/include/asm/mach-jz4740/platform.h b/arch/mips/include/asm/mach-jz4740/platform.h index 8987a76e9676..564ab81d6cdc 100644 --- a/arch/mips/include/asm/mach-jz4740/platform.h +++ b/arch/mips/include/asm/mach-jz4740/platform.h @@ -30,6 +30,7 @@ extern struct platform_device jz4740_i2s_device; extern struct platform_device jz4740_pcm_device; extern struct platform_device jz4740_codec_device; extern struct platform_device jz4740_adc_device; +extern struct platform_device jz4740_wdt_device; void jz4740_serial_device_register(void); diff --git a/arch/mips/jz4740/platform.c b/arch/mips/jz4740/platform.c index 1cc9e544d16b..10929e2bc6d8 100644 --- a/arch/mips/jz4740/platform.c +++ b/arch/mips/jz4740/platform.c @@ -289,3 +289,19 @@ void jz4740_serial_device_register(void) platform_device_register(&jz4740_uart_device); } + +/* Watchdog */ +static struct resource jz4740_wdt_resources[] = { + { + .start = JZ4740_WDT_BASE_ADDR, + .end = JZ4740_WDT_BASE_ADDR + 0x10 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device jz4740_wdt_device = { + .name = "jz4740-wdt", + .id = -1, + .num_resources = ARRAY_SIZE(jz4740_wdt_resources), + .resource = jz4740_wdt_resources, +}; diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index 570607b376b5..832afbb87588 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -115,7 +115,7 @@ SECTIONS EXIT_DATA } - PERCPU(PAGE_SIZE) + PERCPU(1 << CONFIG_MIPS_L1_CACHE_SHIFT, PAGE_SIZE) . = ALIGN(PAGE_SIZE); __init_end = .; /* freed after init ends here */ diff --git a/arch/mn10300/kernel/time.c b/arch/mn10300/kernel/time.c index 75da468090b9..5b955000626d 100644 --- a/arch/mn10300/kernel/time.c +++ b/arch/mn10300/kernel/time.c @@ -104,8 +104,6 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id) unsigned tsc, elapse; irqreturn_t ret; - write_seqlock(&xtime_lock); - while (tsc = get_cycles(), elapse = tsc - mn10300_last_tsc, /* time elapsed since last * tick */ @@ -114,11 +112,9 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id) mn10300_last_tsc += MN10300_TSC_PER_HZ; /* advance the kernel's time tracking system */ - do_timer(1); + xtime_update(1); } - write_sequnlock(&xtime_lock); - ret = local_timer_interrupt(); #ifdef CONFIG_SMP send_IPI_allbutself(LOCAL_TIMER_IPI); diff --git a/arch/mn10300/kernel/vmlinux.lds.S b/arch/mn10300/kernel/vmlinux.lds.S index febbeee7f2f5..968bcd2cb022 100644 --- a/arch/mn10300/kernel/vmlinux.lds.S +++ b/arch/mn10300/kernel/vmlinux.lds.S @@ -70,7 +70,7 @@ SECTIONS .exit.text : { EXIT_TEXT; } .exit.data : { EXIT_DATA; } - PERCPU(PAGE_SIZE) + PERCPU(32, PAGE_SIZE) . = ALIGN(PAGE_SIZE); __init_end = .; /* freed after init ends here */ diff --git a/arch/parisc/hpux/sys_hpux.c b/arch/parisc/hpux/sys_hpux.c index 30394081d9b6..6ab9580b0b00 100644 --- a/arch/parisc/hpux/sys_hpux.c +++ b/arch/parisc/hpux/sys_hpux.c @@ -185,26 +185,21 @@ struct hpux_statfs { int16_t f_pad; }; -static int do_statfs_hpux(struct path *path, struct hpux_statfs *buf) +static int do_statfs_hpux(struct kstatfs *st, struct hpux_statfs __user *p) { - struct kstatfs st; - int retval; - - retval = vfs_statfs(path, &st); - if (retval) - return retval; - - memset(buf, 0, sizeof(*buf)); - buf->f_type = st.f_type; - buf->f_bsize = st.f_bsize; - buf->f_blocks = st.f_blocks; - buf->f_bfree = st.f_bfree; - buf->f_bavail = st.f_bavail; - buf->f_files = st.f_files; - buf->f_ffree = st.f_ffree; - buf->f_fsid[0] = st.f_fsid.val[0]; - buf->f_fsid[1] = st.f_fsid.val[1]; - + struct hpux_statfs buf; + memset(&buf, 0, sizeof(buf)); + buf.f_type = st->f_type; + buf.f_bsize = st->f_bsize; + buf.f_blocks = st->f_blocks; + buf.f_bfree = st->f_bfree; + buf.f_bavail = st->f_bavail; + buf.f_files = st->f_files; + buf.f_ffree = st->f_ffree; + buf.f_fsid[0] = st->f_fsid.val[0]; + buf.f_fsid[1] = st->f_fsid.val[1]; + if (copy_to_user(p, &buf, sizeof(buf))) + return -EFAULT; return 0; } @@ -212,35 +207,19 @@ static int do_statfs_hpux(struct path *path, struct hpux_statfs *buf) asmlinkage long hpux_statfs(const char __user *pathname, struct hpux_statfs __user *buf) { - struct path path; - int error; - - error = user_path(pathname, &path); - if (!error) { - struct hpux_statfs tmp; - error = do_statfs_hpux(&path, &tmp); - if (!error && copy_to_user(buf, &tmp, sizeof(tmp))) - error = -EFAULT; - path_put(&path); - } + struct kstatfs st; + int error = user_statfs(pathname, &st); + if (!error) + error = do_statfs_hpux(&st, buf); return error; } asmlinkage long hpux_fstatfs(unsigned int fd, struct hpux_statfs __user * buf) { - struct file *file; - struct hpux_statfs tmp; - int error; - - error = -EBADF; - file = fget(fd); - if (!file) - goto out; - error = do_statfs_hpux(&file->f_path, &tmp); - if (!error && copy_to_user(buf, &tmp, sizeof(tmp))) - error = -EFAULT; - fput(file); - out: + struct kstatfs st; + int error = fd_statfs(fd, &st); + if (!error) + error = do_statfs_hpux(&st, buf); return error; } diff --git a/arch/parisc/include/asm/fcntl.h b/arch/parisc/include/asm/fcntl.h index f357fc693c89..0304b92ccfea 100644 --- a/arch/parisc/include/asm/fcntl.h +++ b/arch/parisc/include/asm/fcntl.h @@ -19,6 +19,8 @@ #define O_NOFOLLOW 000000200 /* don't follow links */ #define O_INVISIBLE 004000000 /* invisible I/O, for DMAPI/XDSM */ +#define O_PATH 020000000 + #define F_GETLK64 8 #define F_SETLK64 9 #define F_SETLKW64 10 diff --git a/arch/parisc/include/asm/futex.h b/arch/parisc/include/asm/futex.h index 0c705c3a55ef..67a33cc27ef2 100644 --- a/arch/parisc/include/asm/futex.h +++ b/arch/parisc/include/asm/futex.h @@ -8,7 +8,7 @@ #include <asm/errno.h> static inline int -futex_atomic_op_inuser (int encoded_op, int __user *uaddr) +futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr) { int op = (encoded_op >> 28) & 7; int cmp = (encoded_op >> 24) & 15; @@ -18,7 +18,7 @@ futex_atomic_op_inuser (int encoded_op, int __user *uaddr) if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) oparg = 1 << oparg; - if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int))) + if (! access_ok (VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; pagefault_disable(); @@ -51,10 +51,10 @@ futex_atomic_op_inuser (int encoded_op, int __user *uaddr) /* Non-atomic version */ static inline int -futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) +futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) { - int err = 0; - int uval; + u32 val; /* futex.c wants to do a cmpxchg_inatomic on kernel NULL, which is * our gateway page, and causes no end of trouble... @@ -62,15 +62,15 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) if (segment_eq(KERNEL_DS, get_fs()) && !uaddr) return -EFAULT; - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; - err = get_user(uval, uaddr); - if (err) return -EFAULT; - if (uval == oldval) - err = put_user(newval, uaddr); - if (err) return -EFAULT; - return uval; + if (get_user(val, uaddr)) + return -EFAULT; + if (val == oldval && put_user(newval, uaddr)) + return -EFAULT; + *uval = val; + return 0; } #endif /*__KERNEL__*/ diff --git a/arch/parisc/include/asm/ioctls.h b/arch/parisc/include/asm/ioctls.h index 6ba80d03623a..054ec06f9e23 100644 --- a/arch/parisc/include/asm/ioctls.h +++ b/arch/parisc/include/asm/ioctls.h @@ -54,6 +54,7 @@ #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ #define TIOCGDEV _IOR('T',0x32, int) /* Get primary device node of /dev/console */ #define TIOCSIG _IOW('T',0x36, int) /* Generate signal on Pty slave */ +#define TIOCVHANGUP 0x5437 #define FIONCLEX 0x5450 /* these numbers need to be adjusted. */ #define FIOCLEX 0x5451 diff --git a/arch/parisc/kernel/time.c b/arch/parisc/kernel/time.c index 05511ccb61d2..45b7389d77aa 100644 --- a/arch/parisc/kernel/time.c +++ b/arch/parisc/kernel/time.c @@ -162,11 +162,8 @@ irqreturn_t __irq_entry timer_interrupt(int irq, void *dev_id) update_process_times(user_mode(get_irq_regs())); } - if (cpu == 0) { - write_seqlock(&xtime_lock); - do_timer(ticks_elapsed); - write_sequnlock(&xtime_lock); - } + if (cpu == 0) + xtime_update(ticks_elapsed); return IRQ_HANDLED; } diff --git a/arch/parisc/kernel/vmlinux.lds.S b/arch/parisc/kernel/vmlinux.lds.S index d64a6bbec2aa..8f1e4efd143e 100644 --- a/arch/parisc/kernel/vmlinux.lds.S +++ b/arch/parisc/kernel/vmlinux.lds.S @@ -145,7 +145,7 @@ SECTIONS EXIT_DATA } - PERCPU(PAGE_SIZE) + PERCPU(L1_CACHE_BYTES, PAGE_SIZE) . = ALIGN(PAGE_SIZE); __init_end = .; /* freed after init ends here */ diff --git a/arch/powerpc/include/asm/futex.h b/arch/powerpc/include/asm/futex.h index 7c589ef81fb0..c94e4a3fe2ef 100644 --- a/arch/powerpc/include/asm/futex.h +++ b/arch/powerpc/include/asm/futex.h @@ -30,7 +30,7 @@ : "b" (uaddr), "i" (-EFAULT), "r" (oparg) \ : "cr0", "memory") -static inline int futex_atomic_op_inuser (int encoded_op, int __user *uaddr) +static inline int futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr) { int op = (encoded_op >> 28) & 7; int cmp = (encoded_op >> 24) & 15; @@ -40,7 +40,7 @@ static inline int futex_atomic_op_inuser (int encoded_op, int __user *uaddr) if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) oparg = 1 << oparg; - if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int))) + if (! access_ok (VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; pagefault_disable(); @@ -82,35 +82,38 @@ static inline int futex_atomic_op_inuser (int encoded_op, int __user *uaddr) } static inline int -futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) +futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) { - int prev; + int ret = 0; + u32 prev; - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; __asm__ __volatile__ ( PPC_RELEASE_BARRIER -"1: lwarx %0,0,%2 # futex_atomic_cmpxchg_inatomic\n\ - cmpw 0,%0,%3\n\ +"1: lwarx %1,0,%3 # futex_atomic_cmpxchg_inatomic\n\ + cmpw 0,%1,%4\n\ bne- 3f\n" - PPC405_ERR77(0,%2) -"2: stwcx. %4,0,%2\n\ + PPC405_ERR77(0,%3) +"2: stwcx. %5,0,%3\n\ bne- 1b\n" PPC_ACQUIRE_BARRIER "3: .section .fixup,\"ax\"\n\ -4: li %0,%5\n\ +4: li %0,%6\n\ b 3b\n\ .previous\n\ .section __ex_table,\"a\"\n\ .align 3\n\ " PPC_LONG "1b,4b,2b,4b\n\ .previous" \ - : "=&r" (prev), "+m" (*uaddr) + : "+r" (ret), "=&r" (prev), "+m" (*uaddr) : "r" (uaddr), "r" (oldval), "r" (newval), "i" (-EFAULT) : "cc", "memory"); - return prev; + *uval = prev; + return ret; } #endif /* __KERNEL__ */ diff --git a/arch/powerpc/include/asm/ioctls.h b/arch/powerpc/include/asm/ioctls.h index c7dc17cf84f1..e9b78870aaab 100644 --- a/arch/powerpc/include/asm/ioctls.h +++ b/arch/powerpc/include/asm/ioctls.h @@ -96,6 +96,7 @@ #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ #define TIOCGDEV _IOR('T',0x32, unsigned int) /* Get primary device node of /dev/console */ #define TIOCSIG _IOW('T',0x36, int) /* Generate signal on Pty slave */ +#define TIOCVHANGUP 0x5437 #define TIOCSERCONFIG 0x5453 #define TIOCSERGWILD 0x5454 diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h index 51e9e6f90d12..5e156e034fe2 100644 --- a/arch/powerpc/include/asm/pci-bridge.h +++ b/arch/powerpc/include/asm/pci-bridge.h @@ -164,13 +164,23 @@ extern void setup_indirect_pci(struct pci_controller* hose, resource_size_t cfg_addr, resource_size_t cfg_data, u32 flags); -#ifndef CONFIG_PPC64 - static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) { return bus->sysdata; } +#ifndef CONFIG_PPC64 + +static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) +{ + struct pci_controller *host; + + if (bus->self) + return pci_device_to_OF_node(bus->self); + host = pci_bus_to_host(bus); + return host ? host->dn : NULL; +} + static inline int isa_vaddr_is_ioport(void __iomem *address) { /* No specific ISA handling on ppc32 at this stage, it @@ -218,19 +228,10 @@ extern void * update_dn_pci_info(struct device_node *dn, void *data); /* Get a device_node from a pci_dev. This code must be fast except * in the case where the sysdata is incorrect and needs to be fixed - * up (this will only happen once). - * In this case the sysdata will have been inherited from a PCI host - * bridge or a PCI-PCI bridge further up the tree, so it will point - * to a valid struct pci_dn, just not the one we want. - */ + * up (this will only happen once). */ static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev) { - struct device_node *dn = dev->sysdata; - struct pci_dn *pdn = dn->data; - - if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number) - return dn; /* fast path. sysdata is good */ - return fetch_dev_dn(dev); + return dev->dev.of_node ? dev->dev.of_node : fetch_dev_dn(dev); } static inline int pci_device_from_OF_node(struct device_node *np, @@ -248,7 +249,7 @@ static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) if (bus->self) return pci_device_to_OF_node(bus->self); else - return bus->sysdata; /* Must be root bus (PHB) */ + return bus->dev.of_node; /* Must be root bus (PHB) */ } /** Find the bus corresponding to the indicated device node */ @@ -260,14 +261,6 @@ extern void pcibios_remove_pci_devices(struct pci_bus *bus); /** Discover new pci devices under this bus, and add them */ extern void pcibios_add_pci_devices(struct pci_bus *bus); -static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) -{ - struct device_node *busdn = bus->sysdata; - - BUG_ON(busdn == NULL); - return PCI_DN(busdn)->phb; -} - extern void isa_bridge_find_early(struct pci_controller *hose); diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h index a20a9ad2258b..7d7790954e02 100644 --- a/arch/powerpc/include/asm/pci.h +++ b/arch/powerpc/include/asm/pci.h @@ -201,7 +201,7 @@ extern void pci_resource_to_user(const struct pci_dev *dev, int bar, extern void pcibios_setup_bus_devices(struct pci_bus *bus); extern void pcibios_setup_bus_self(struct pci_bus *bus); extern void pcibios_setup_phb_io_space(struct pci_controller *hose); -extern void pcibios_scan_phb(struct pci_controller *hose, void *sysdata); +extern void pcibios_scan_phb(struct pci_controller *hose); #endif /* __KERNEL__ */ #endif /* __ASM_POWERPC_PCI_H */ diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h index d72757585595..c189aa5fe1f4 100644 --- a/arch/powerpc/include/asm/prom.h +++ b/arch/powerpc/include/asm/prom.h @@ -70,21 +70,6 @@ static inline int of_node_to_nid(struct device_node *device) { return 0; } #endif #define of_node_to_nid of_node_to_nid -/** - * of_irq_map_pci - Resolve the interrupt for a PCI device - * @pdev: the device whose interrupt is to be resolved - * @out_irq: structure of_irq filled by this function - * - * This function resolves the PCI interrupt for a given PCI device. If a - * device-node exists for a given pci_dev, it will use normal OF tree - * walking. If not, it will implement standard swizzling and walk up the - * PCI tree until an device-node is found, at which point it will finish - * resolving using the OF tree walking. - */ -struct pci_dev; -struct of_irq; -extern int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq); - extern void of_instantiate_rtc(void); /* These includes are put at the bottom because they may contain things diff --git a/arch/powerpc/include/asm/rwsem.h b/arch/powerpc/include/asm/rwsem.h index 8447d89fbe72..bb1e2cdeb9bf 100644 --- a/arch/powerpc/include/asm/rwsem.h +++ b/arch/powerpc/include/asm/rwsem.h @@ -13,11 +13,6 @@ * by Paul Mackerras <paulus@samba.org>. */ -#include <linux/list.h> -#include <linux/spinlock.h> -#include <asm/atomic.h> -#include <asm/system.h> - /* * the semaphore definition */ @@ -33,47 +28,6 @@ #define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS #define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS) -struct rw_semaphore { - long count; - spinlock_t wait_lock; - struct list_head wait_list; -#ifdef CONFIG_DEBUG_LOCK_ALLOC - struct lockdep_map dep_map; -#endif -}; - -#ifdef CONFIG_DEBUG_LOCK_ALLOC -# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname } -#else -# define __RWSEM_DEP_MAP_INIT(lockname) -#endif - -#define __RWSEM_INITIALIZER(name) \ -{ \ - RWSEM_UNLOCKED_VALUE, \ - __SPIN_LOCK_UNLOCKED((name).wait_lock), \ - LIST_HEAD_INIT((name).wait_list) \ - __RWSEM_DEP_MAP_INIT(name) \ -} - -#define DECLARE_RWSEM(name) \ - struct rw_semaphore name = __RWSEM_INITIALIZER(name) - -extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem); -extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem); -extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem); -extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem); - -extern void __init_rwsem(struct rw_semaphore *sem, const char *name, - struct lock_class_key *key); - -#define init_rwsem(sem) \ - do { \ - static struct lock_class_key __key; \ - \ - __init_rwsem((sem), #sem, &__key); \ - } while (0) - /* * lock for reading */ @@ -174,10 +128,5 @@ static inline long rwsem_atomic_update(long delta, struct rw_semaphore *sem) return atomic_long_add_return(delta, (atomic_long_t *)&sem->count); } -static inline int rwsem_is_locked(struct rw_semaphore *sem) -{ - return sem->count != 0; -} - #endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_RWSEM_H */ diff --git a/arch/powerpc/kernel/ibmebus.c b/arch/powerpc/kernel/ibmebus.c index f62efdfd1769..c00d4ca1ee15 100644 --- a/arch/powerpc/kernel/ibmebus.c +++ b/arch/powerpc/kernel/ibmebus.c @@ -201,13 +201,14 @@ int ibmebus_register_driver(struct of_platform_driver *drv) /* If the driver uses devices that ibmebus doesn't know, add them */ ibmebus_create_devices(drv->driver.of_match_table); - return of_register_driver(drv, &ibmebus_bus_type); + drv->driver.bus = &ibmebus_bus_type; + return driver_register(&drv->driver); } EXPORT_SYMBOL(ibmebus_register_driver); void ibmebus_unregister_driver(struct of_platform_driver *drv) { - of_unregister_driver(drv); + driver_unregister(&drv->driver); } EXPORT_SYMBOL(ibmebus_unregister_driver); @@ -308,15 +309,410 @@ static ssize_t ibmebus_store_remove(struct bus_type *bus, } } + static struct bus_attribute ibmebus_bus_attrs[] = { __ATTR(probe, S_IWUSR, NULL, ibmebus_store_probe), __ATTR(remove, S_IWUSR, NULL, ibmebus_store_remove), __ATTR_NULL }; +static int ibmebus_bus_bus_match(struct device *dev, struct device_driver *drv) +{ + const struct of_device_id *matches = drv->of_match_table; + + if (!matches) + return 0; + + return of_match_device(matches, dev) != NULL; +} + +static int ibmebus_bus_device_probe(struct device *dev) +{ + int error = -ENODEV; + struct of_platform_driver *drv; + struct platform_device *of_dev; + const struct of_device_id *match; + + drv = to_of_platform_driver(dev->driver); + of_dev = to_platform_device(dev); + + if (!drv->probe) + return error; + + of_dev_get(of_dev); + + match = of_match_device(drv->driver.of_match_table, dev); + if (match) + error = drv->probe(of_dev, match); + if (error) + of_dev_put(of_dev); + + return error; +} + +static int ibmebus_bus_device_remove(struct device *dev) +{ + struct platform_device *of_dev = to_platform_device(dev); + struct of_platform_driver *drv = to_of_platform_driver(dev->driver); + + if (dev->driver && drv->remove) + drv->remove(of_dev); + return 0; +} + +static void ibmebus_bus_device_shutdown(struct device *dev) +{ + struct platform_device *of_dev = to_platform_device(dev); + struct of_platform_driver *drv = to_of_platform_driver(dev->driver); + + if (dev->driver && drv->shutdown) + drv->shutdown(of_dev); +} + +/* + * ibmebus_bus_device_attrs + */ +static ssize_t devspec_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *ofdev; + + ofdev = to_platform_device(dev); + return sprintf(buf, "%s\n", ofdev->dev.of_node->full_name); +} + +static ssize_t name_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *ofdev; + + ofdev = to_platform_device(dev); + return sprintf(buf, "%s\n", ofdev->dev.of_node->name); +} + +static ssize_t modalias_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + ssize_t len = of_device_get_modalias(dev, buf, PAGE_SIZE - 2); + buf[len] = '\n'; + buf[len+1] = 0; + return len+1; +} + +struct device_attribute ibmebus_bus_device_attrs[] = { + __ATTR_RO(devspec), + __ATTR_RO(name), + __ATTR_RO(modalias), + __ATTR_NULL +}; + +#ifdef CONFIG_PM_SLEEP +static int ibmebus_bus_legacy_suspend(struct device *dev, pm_message_t mesg) +{ + struct platform_device *of_dev = to_platform_device(dev); + struct of_platform_driver *drv = to_of_platform_driver(dev->driver); + int ret = 0; + + if (dev->driver && drv->suspend) + ret = drv->suspend(of_dev, mesg); + return ret; +} + +static int ibmebus_bus_legacy_resume(struct device *dev) +{ + struct platform_device *of_dev = to_platform_device(dev); + struct of_platform_driver *drv = to_of_platform_driver(dev->driver); + int ret = 0; + + if (dev->driver && drv->resume) + ret = drv->resume(of_dev); + return ret; +} + +static int ibmebus_bus_pm_prepare(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int ret = 0; + + if (drv && drv->pm && drv->pm->prepare) + ret = drv->pm->prepare(dev); + + return ret; +} + +static void ibmebus_bus_pm_complete(struct device *dev) +{ + struct device_driver *drv = dev->driver; + + if (drv && drv->pm && drv->pm->complete) + drv->pm->complete(dev); +} + +#ifdef CONFIG_SUSPEND + +static int ibmebus_bus_pm_suspend(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int ret = 0; + + if (!drv) + return 0; + + if (drv->pm) { + if (drv->pm->suspend) + ret = drv->pm->suspend(dev); + } else { + ret = ibmebus_bus_legacy_suspend(dev, PMSG_SUSPEND); + } + + return ret; +} + +static int ibmebus_bus_pm_suspend_noirq(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int ret = 0; + + if (!drv) + return 0; + + if (drv->pm) { + if (drv->pm->suspend_noirq) + ret = drv->pm->suspend_noirq(dev); + } + + return ret; +} + +static int ibmebus_bus_pm_resume(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int ret = 0; + + if (!drv) + return 0; + + if (drv->pm) { + if (drv->pm->resume) + ret = drv->pm->resume(dev); + } else { + ret = ibmebus_bus_legacy_resume(dev); + } + + return ret; +} + +static int ibmebus_bus_pm_resume_noirq(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int ret = 0; + + if (!drv) + return 0; + + if (drv->pm) { + if (drv->pm->resume_noirq) + ret = drv->pm->resume_noirq(dev); + } + + return ret; +} + +#else /* !CONFIG_SUSPEND */ + +#define ibmebus_bus_pm_suspend NULL +#define ibmebus_bus_pm_resume NULL +#define ibmebus_bus_pm_suspend_noirq NULL +#define ibmebus_bus_pm_resume_noirq NULL + +#endif /* !CONFIG_SUSPEND */ + +#ifdef CONFIG_HIBERNATION + +static int ibmebus_bus_pm_freeze(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int ret = 0; + + if (!drv) + return 0; + + if (drv->pm) { + if (drv->pm->freeze) + ret = drv->pm->freeze(dev); + } else { + ret = ibmebus_bus_legacy_suspend(dev, PMSG_FREEZE); + } + + return ret; +} + +static int ibmebus_bus_pm_freeze_noirq(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int ret = 0; + + if (!drv) + return 0; + + if (drv->pm) { + if (drv->pm->freeze_noirq) + ret = drv->pm->freeze_noirq(dev); + } + + return ret; +} + +static int ibmebus_bus_pm_thaw(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int ret = 0; + + if (!drv) + return 0; + + if (drv->pm) { + if (drv->pm->thaw) + ret = drv->pm->thaw(dev); + } else { + ret = ibmebus_bus_legacy_resume(dev); + } + + return ret; +} + +static int ibmebus_bus_pm_thaw_noirq(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int ret = 0; + + if (!drv) + return 0; + + if (drv->pm) { + if (drv->pm->thaw_noirq) + ret = drv->pm->thaw_noirq(dev); + } + + return ret; +} + +static int ibmebus_bus_pm_poweroff(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int ret = 0; + + if (!drv) + return 0; + + if (drv->pm) { + if (drv->pm->poweroff) + ret = drv->pm->poweroff(dev); + } else { + ret = ibmebus_bus_legacy_suspend(dev, PMSG_HIBERNATE); + } + + return ret; +} + +static int ibmebus_bus_pm_poweroff_noirq(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int ret = 0; + + if (!drv) + return 0; + + if (drv->pm) { + if (drv->pm->poweroff_noirq) + ret = drv->pm->poweroff_noirq(dev); + } + + return ret; +} + +static int ibmebus_bus_pm_restore(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int ret = 0; + + if (!drv) + return 0; + + if (drv->pm) { + if (drv->pm->restore) + ret = drv->pm->restore(dev); + } else { + ret = ibmebus_bus_legacy_resume(dev); + } + + return ret; +} + +static int ibmebus_bus_pm_restore_noirq(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int ret = 0; + + if (!drv) + return 0; + + if (drv->pm) { + if (drv->pm->restore_noirq) + ret = drv->pm->restore_noirq(dev); + } + + return ret; +} + +#else /* !CONFIG_HIBERNATION */ + +#define ibmebus_bus_pm_freeze NULL +#define ibmebus_bus_pm_thaw NULL +#define ibmebus_bus_pm_poweroff NULL +#define ibmebus_bus_pm_restore NULL +#define ibmebus_bus_pm_freeze_noirq NULL +#define ibmebus_bus_pm_thaw_noirq NULL +#define ibmebus_bus_pm_poweroff_noirq NULL +#define ibmebus_bus_pm_restore_noirq NULL + +#endif /* !CONFIG_HIBERNATION */ + +static struct dev_pm_ops ibmebus_bus_dev_pm_ops = { + .prepare = ibmebus_bus_pm_prepare, + .complete = ibmebus_bus_pm_complete, + .suspend = ibmebus_bus_pm_suspend, + .resume = ibmebus_bus_pm_resume, + .freeze = ibmebus_bus_pm_freeze, + .thaw = ibmebus_bus_pm_thaw, + .poweroff = ibmebus_bus_pm_poweroff, + .restore = ibmebus_bus_pm_restore, + .suspend_noirq = ibmebus_bus_pm_suspend_noirq, + .resume_noirq = ibmebus_bus_pm_resume_noirq, + .freeze_noirq = ibmebus_bus_pm_freeze_noirq, + .thaw_noirq = ibmebus_bus_pm_thaw_noirq, + .poweroff_noirq = ibmebus_bus_pm_poweroff_noirq, + .restore_noirq = ibmebus_bus_pm_restore_noirq, +}; + +#define IBMEBUS_BUS_PM_OPS_PTR (&ibmebus_bus_dev_pm_ops) + +#else /* !CONFIG_PM_SLEEP */ + +#define IBMEBUS_BUS_PM_OPS_PTR NULL + +#endif /* !CONFIG_PM_SLEEP */ + struct bus_type ibmebus_bus_type = { + .name = "ibmebus", .uevent = of_device_uevent, - .bus_attrs = ibmebus_bus_attrs + .bus_attrs = ibmebus_bus_attrs, + .match = ibmebus_bus_bus_match, + .probe = ibmebus_bus_device_probe, + .remove = ibmebus_bus_device_remove, + .shutdown = ibmebus_bus_device_shutdown, + .dev_attrs = ibmebus_bus_device_attrs, + .pm = IBMEBUS_BUS_PM_OPS_PTR, }; EXPORT_SYMBOL(ibmebus_bus_type); @@ -326,7 +722,7 @@ static int __init ibmebus_bus_init(void) printk(KERN_INFO "IBM eBus Device Driver\n"); - err = of_bus_type_init(&ibmebus_bus_type, "ibmebus"); + err = bus_register(&ibmebus_bus_type); if (err) { printk(KERN_ERR "%s: failed to register IBM eBus.\n", __func__); diff --git a/arch/powerpc/kernel/of_platform.c b/arch/powerpc/kernel/of_platform.c index b2c363ef38ad..24582181b6ec 100644 --- a/arch/powerpc/kernel/of_platform.c +++ b/arch/powerpc/kernel/of_platform.c @@ -36,8 +36,7 @@ * lacking some bits needed here. */ -static int __devinit of_pci_phb_probe(struct platform_device *dev, - const struct of_device_id *match) +static int __devinit of_pci_phb_probe(struct platform_device *dev) { struct pci_controller *phb; @@ -74,7 +73,7 @@ static int __devinit of_pci_phb_probe(struct platform_device *dev, #endif /* CONFIG_EEH */ /* Scan the bus */ - pcibios_scan_phb(phb, dev->dev.of_node); + pcibios_scan_phb(phb); if (phb->bus == NULL) return -ENXIO; @@ -104,7 +103,7 @@ static struct of_device_id of_pci_phb_ids[] = { {} }; -static struct of_platform_driver of_pci_phb_driver = { +static struct platform_driver of_pci_phb_driver = { .probe = of_pci_phb_probe, .driver = { .name = "of-pci", @@ -115,7 +114,7 @@ static struct of_platform_driver of_pci_phb_driver = { static __init int of_pci_phb_init(void) { - return of_register_platform_driver(&of_pci_phb_driver); + return platform_driver_register(&of_pci_phb_driver); } device_initcall(of_pci_phb_init); diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c index 10a44e68ef11..3cd85faa8ac6 100644 --- a/arch/powerpc/kernel/pci-common.c +++ b/arch/powerpc/kernel/pci-common.c @@ -22,6 +22,7 @@ #include <linux/init.h> #include <linux/bootmem.h> #include <linux/of_address.h> +#include <linux/of_pci.h> #include <linux/mm.h> #include <linux/list.h> #include <linux/syscalls.h> @@ -1687,13 +1688,8 @@ int early_find_capability(struct pci_controller *hose, int bus, int devfn, /** * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus * @hose: Pointer to the PCI host controller instance structure - * @sysdata: value to use for sysdata pointer. ppc32 and ppc64 differ here - * - * Note: the 'data' pointer is a temporary measure. As 32 and 64 bit - * pci code gets merged, this parameter should become unnecessary because - * both will use the same value. */ -void __devinit pcibios_scan_phb(struct pci_controller *hose, void *sysdata) +void __devinit pcibios_scan_phb(struct pci_controller *hose) { struct pci_bus *bus; struct device_node *node = hose->dn; @@ -1703,13 +1699,13 @@ void __devinit pcibios_scan_phb(struct pci_controller *hose, void *sysdata) node ? node->full_name : "<NO NAME>"); /* Create an empty bus for the toplevel */ - bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, - sysdata); + bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, hose); if (bus == NULL) { pr_err("Failed to create bus for PCI domain %04x\n", hose->global_number); return; } + bus->dev.of_node = of_node_get(node); bus->secondary = hose->first_busno; hose->bus = bus; diff --git a/arch/powerpc/kernel/pci_32.c b/arch/powerpc/kernel/pci_32.c index e7db5b48004a..bedb370459f2 100644 --- a/arch/powerpc/kernel/pci_32.c +++ b/arch/powerpc/kernel/pci_32.c @@ -381,7 +381,7 @@ static int __init pcibios_init(void) if (pci_assign_all_buses) hose->first_busno = next_busno; hose->last_busno = 0xff; - pcibios_scan_phb(hose, hose); + pcibios_scan_phb(hose); pci_bus_add_devices(hose->bus); if (pci_assign_all_buses || next_busno <= hose->last_busno) next_busno = hose->last_busno + pcibios_assign_bus_offset; diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c index 851577608a78..fc6452b6be9f 100644 --- a/arch/powerpc/kernel/pci_64.c +++ b/arch/powerpc/kernel/pci_64.c @@ -64,7 +64,7 @@ static int __init pcibios_init(void) /* Scan all of the recorded PCI controllers. */ list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { - pcibios_scan_phb(hose, hose->dn); + pcibios_scan_phb(hose); pci_bus_add_devices(hose->bus); } @@ -242,10 +242,10 @@ long sys_pciconfig_iobase(long which, unsigned long in_bus, break; bus = NULL; } - if (bus == NULL || bus->sysdata == NULL) + if (bus == NULL || bus->dev.of_node == NULL) return -ENODEV; - hose_node = (struct device_node *)bus->sysdata; + hose_node = bus->dev.of_node; hose = PCI_DN(hose_node)->phb; switch (which) { diff --git a/arch/powerpc/kernel/pci_dn.c b/arch/powerpc/kernel/pci_dn.c index d56b35ee7f74..29852688ceaa 100644 --- a/arch/powerpc/kernel/pci_dn.c +++ b/arch/powerpc/kernel/pci_dn.c @@ -161,7 +161,7 @@ static void *is_devfn_node(struct device_node *dn, void *data) /* * This is the "slow" path for looking up a device_node from a * pci_dev. It will hunt for the device under its parent's - * phb and then update sysdata for a future fastpath. + * phb and then update of_node pointer. * * It may also do fixups on the actual device since this happens * on the first read/write. @@ -170,16 +170,19 @@ static void *is_devfn_node(struct device_node *dn, void *data) * In this case it may probe for real hardware ("just in case") * and add a device_node to the device tree if necessary. * + * Is this function necessary anymore now that dev->dev.of_node is + * used to store the node pointer? + * */ struct device_node *fetch_dev_dn(struct pci_dev *dev) { - struct device_node *orig_dn = dev->sysdata; + struct device_node *orig_dn = dev->dev.of_node; struct device_node *dn; unsigned long searchval = (dev->bus->number << 8) | dev->devfn; dn = traverse_pci_devices(orig_dn, is_devfn_node, (void *)searchval); if (dn) - dev->sysdata = dn; + dev->dev.of_node = dn; return dn; } EXPORT_SYMBOL(fetch_dev_dn); diff --git a/arch/powerpc/kernel/pci_of_scan.c b/arch/powerpc/kernel/pci_of_scan.c index e751506323b4..1e89a72fd030 100644 --- a/arch/powerpc/kernel/pci_of_scan.c +++ b/arch/powerpc/kernel/pci_of_scan.c @@ -135,7 +135,7 @@ struct pci_dev *of_create_pci_dev(struct device_node *node, pr_debug(" create device, devfn: %x, type: %s\n", devfn, type); dev->bus = bus; - dev->sysdata = node; + dev->dev.of_node = of_node_get(node); dev->dev.parent = bus->bridge; dev->dev.bus = &pci_bus_type; dev->devfn = devfn; @@ -238,7 +238,7 @@ void __devinit of_scan_pci_bridge(struct device_node *node, bus->primary = dev->bus->number; bus->subordinate = busrange[1]; bus->bridge_ctl = 0; - bus->sysdata = node; + bus->dev.of_node = of_node_get(node); /* parse ranges property */ /* PCI #address-cells == 3 and #size-cells == 2 always */ diff --git a/arch/powerpc/kernel/prom_parse.c b/arch/powerpc/kernel/prom_parse.c index c2b7a07cc3d3..47187cc2cf00 100644 --- a/arch/powerpc/kernel/prom_parse.c +++ b/arch/powerpc/kernel/prom_parse.c @@ -2,95 +2,11 @@ #include <linux/kernel.h> #include <linux/string.h> -#include <linux/pci_regs.h> #include <linux/module.h> #include <linux/ioport.h> #include <linux/etherdevice.h> #include <linux/of_address.h> #include <asm/prom.h> -#include <asm/pci-bridge.h> - -#ifdef CONFIG_PCI -int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq) -{ - struct device_node *dn, *ppnode; - struct pci_dev *ppdev; - u32 lspec; - u32 laddr[3]; - u8 pin; - int rc; - - /* Check if we have a device node, if yes, fallback to standard OF - * parsing - */ - dn = pci_device_to_OF_node(pdev); - if (dn) { - rc = of_irq_map_one(dn, 0, out_irq); - if (!rc) - return rc; - } - - /* Ok, we don't, time to have fun. Let's start by building up an - * interrupt spec. we assume #interrupt-cells is 1, which is standard - * for PCI. If you do different, then don't use that routine. - */ - rc = pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &pin); - if (rc != 0) - return rc; - /* No pin, exit */ - if (pin == 0) - return -ENODEV; - - /* Now we walk up the PCI tree */ - lspec = pin; - for (;;) { - /* Get the pci_dev of our parent */ - ppdev = pdev->bus->self; - - /* Ouch, it's a host bridge... */ - if (ppdev == NULL) { -#ifdef CONFIG_PPC64 - ppnode = pci_bus_to_OF_node(pdev->bus); -#else - struct pci_controller *host; - host = pci_bus_to_host(pdev->bus); - ppnode = host ? host->dn : NULL; -#endif - /* No node for host bridge ? give up */ - if (ppnode == NULL) - return -EINVAL; - } else - /* We found a P2P bridge, check if it has a node */ - ppnode = pci_device_to_OF_node(ppdev); - - /* Ok, we have found a parent with a device-node, hand over to - * the OF parsing code. - * We build a unit address from the linux device to be used for - * resolution. Note that we use the linux bus number which may - * not match your firmware bus numbering. - * Fortunately, in most cases, interrupt-map-mask doesn't include - * the bus number as part of the matching. - * You should still be careful about that though if you intend - * to rely on this function (you ship a firmware that doesn't - * create device nodes for all PCI devices). - */ - if (ppnode) - break; - - /* We can only get here if we hit a P2P bridge with no node, - * let's do standard swizzling and try again - */ - lspec = pci_swizzle_interrupt_pin(pdev, lspec); - pdev = ppdev; - } - - laddr[0] = (pdev->bus->number << 16) - | (pdev->devfn << 8); - laddr[1] = laddr[2] = 0; - return of_irq_map_raw(ppnode, &lspec, 1, laddr, out_irq); -} -EXPORT_SYMBOL_GPL(of_irq_map_pci); -#endif /* CONFIG_PCI */ void of_parse_dma_window(struct device_node *dn, const void *dma_window_prop, unsigned long *busno, unsigned long *phys, unsigned long *size) diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S index 8a0deefac08d..b9150f07d266 100644 --- a/arch/powerpc/kernel/vmlinux.lds.S +++ b/arch/powerpc/kernel/vmlinux.lds.S @@ -160,7 +160,7 @@ SECTIONS INIT_RAM_FS } - PERCPU(PAGE_SIZE) + PERCPU(L1_CACHE_BYTES, PAGE_SIZE) . = ALIGN(8); .machine.desc : AT(ADDR(.machine.desc) - LOAD_OFFSET) { diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpio.c b/arch/powerpc/platforms/52xx/mpc52xx_gpio.c index 0dad9a935eb5..1757d1db4b51 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_gpio.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_gpio.c @@ -147,8 +147,7 @@ mpc52xx_wkup_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) return 0; } -static int __devinit mpc52xx_wkup_gpiochip_probe(struct platform_device *ofdev, - const struct of_device_id *match) +static int __devinit mpc52xx_wkup_gpiochip_probe(struct platform_device *ofdev) { struct mpc52xx_gpiochip *chip; struct mpc52xx_gpio_wkup __iomem *regs; @@ -191,7 +190,7 @@ static const struct of_device_id mpc52xx_wkup_gpiochip_match[] = { {} }; -static struct of_platform_driver mpc52xx_wkup_gpiochip_driver = { +static struct platform_driver mpc52xx_wkup_gpiochip_driver = { .driver = { .name = "gpio_wkup", .owner = THIS_MODULE, @@ -310,8 +309,7 @@ mpc52xx_simple_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) return 0; } -static int __devinit mpc52xx_simple_gpiochip_probe(struct platform_device *ofdev, - const struct of_device_id *match) +static int __devinit mpc52xx_simple_gpiochip_probe(struct platform_device *ofdev) { struct mpc52xx_gpiochip *chip; struct gpio_chip *gc; @@ -349,7 +347,7 @@ static const struct of_device_id mpc52xx_simple_gpiochip_match[] = { {} }; -static struct of_platform_driver mpc52xx_simple_gpiochip_driver = { +static struct platform_driver mpc52xx_simple_gpiochip_driver = { .driver = { .name = "gpio", .owner = THIS_MODULE, @@ -361,10 +359,10 @@ static struct of_platform_driver mpc52xx_simple_gpiochip_driver = { static int __init mpc52xx_gpio_init(void) { - if (of_register_platform_driver(&mpc52xx_wkup_gpiochip_driver)) + if (platform_driver_register(&mpc52xx_wkup_gpiochip_driver)) printk(KERN_ERR "Unable to register wakeup GPIO driver\n"); - if (of_register_platform_driver(&mpc52xx_simple_gpiochip_driver)) + if (platform_driver_register(&mpc52xx_simple_gpiochip_driver)) printk(KERN_ERR "Unable to register simple GPIO driver\n"); return 0; diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c index e0d703c7fdf7..859abf1c6d4b 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c @@ -721,8 +721,7 @@ static inline int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt, /* --------------------------------------------------------------------- * of_platform bus binding code */ -static int __devinit mpc52xx_gpt_probe(struct platform_device *ofdev, - const struct of_device_id *match) +static int __devinit mpc52xx_gpt_probe(struct platform_device *ofdev) { struct mpc52xx_gpt_priv *gpt; @@ -781,7 +780,7 @@ static const struct of_device_id mpc52xx_gpt_match[] = { {} }; -static struct of_platform_driver mpc52xx_gpt_driver = { +static struct platform_driver mpc52xx_gpt_driver = { .driver = { .name = "mpc52xx-gpt", .owner = THIS_MODULE, @@ -793,10 +792,7 @@ static struct of_platform_driver mpc52xx_gpt_driver = { static int __init mpc52xx_gpt_init(void) { - if (of_register_platform_driver(&mpc52xx_gpt_driver)) - pr_err("error registering MPC52xx GPT driver\n"); - - return 0; + return platform_driver_register(&mpc52xx_gpt_driver); } /* Make sure GPIOs and IRQs get set up before anyone tries to use them */ diff --git a/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c b/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c index f4ac213c89c0..6385d883cb8d 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c @@ -436,8 +436,7 @@ void mpc52xx_lpbfifo_abort(struct mpc52xx_lpbfifo_request *req) } EXPORT_SYMBOL(mpc52xx_lpbfifo_abort); -static int __devinit mpc52xx_lpbfifo_probe(struct platform_device *op, - const struct of_device_id *match) +static int __devinit mpc52xx_lpbfifo_probe(struct platform_device *op) { struct resource res; int rc = -ENOMEM; @@ -536,7 +535,7 @@ static struct of_device_id mpc52xx_lpbfifo_match[] __devinitconst = { {}, }; -static struct of_platform_driver mpc52xx_lpbfifo_driver = { +static struct platform_driver mpc52xx_lpbfifo_driver = { .driver = { .name = "mpc52xx-lpbfifo", .owner = THIS_MODULE, @@ -551,14 +550,12 @@ static struct of_platform_driver mpc52xx_lpbfifo_driver = { */ static int __init mpc52xx_lpbfifo_init(void) { - pr_debug("Registering LocalPlus bus FIFO driver\n"); - return of_register_platform_driver(&mpc52xx_lpbfifo_driver); + return platform_driver_register(&mpc52xx_lpbfifo_driver); } module_init(mpc52xx_lpbfifo_init); static void __exit mpc52xx_lpbfifo_exit(void) { - pr_debug("Unregistering LocalPlus bus FIFO driver\n"); - of_unregister_platform_driver(&mpc52xx_lpbfifo_driver); + platform_driver_unregister(&mpc52xx_lpbfifo_driver); } module_exit(mpc52xx_lpbfifo_exit); diff --git a/arch/powerpc/platforms/82xx/ep8248e.c b/arch/powerpc/platforms/82xx/ep8248e.c index 1565e0446dc8..10ff526cd046 100644 --- a/arch/powerpc/platforms/82xx/ep8248e.c +++ b/arch/powerpc/platforms/82xx/ep8248e.c @@ -111,8 +111,7 @@ static struct mdiobb_ctrl ep8248e_mdio_ctrl = { .ops = &ep8248e_mdio_ops, }; -static int __devinit ep8248e_mdio_probe(struct platform_device *ofdev, - const struct of_device_id *match) +static int __devinit ep8248e_mdio_probe(struct platform_device *ofdev) { struct mii_bus *bus; struct resource res; @@ -167,7 +166,7 @@ static const struct of_device_id ep8248e_mdio_match[] = { {}, }; -static struct of_platform_driver ep8248e_mdio_driver = { +static struct platform_driver ep8248e_mdio_driver = { .driver = { .name = "ep8248e-mdio-bitbang", .owner = THIS_MODULE, @@ -308,7 +307,7 @@ static __initdata struct of_device_id of_bus_ids[] = { static int __init declare_of_platform_devices(void) { of_platform_bus_probe(NULL, of_bus_ids, NULL); - of_register_platform_driver(&ep8248e_mdio_driver); + platform_driver_register(&ep8248e_mdio_driver); return 0; } diff --git a/arch/powerpc/platforms/83xx/suspend.c b/arch/powerpc/platforms/83xx/suspend.c index fd4f2f2f19e6..188272934cfb 100644 --- a/arch/powerpc/platforms/83xx/suspend.c +++ b/arch/powerpc/platforms/83xx/suspend.c @@ -318,14 +318,18 @@ static const struct platform_suspend_ops mpc83xx_suspend_ops = { .end = mpc83xx_suspend_end, }; -static int pmc_probe(struct platform_device *ofdev, - const struct of_device_id *match) +static int pmc_probe(struct platform_device *ofdev) { struct device_node *np = ofdev->dev.of_node; struct resource res; - struct pmc_type *type = match->data; + struct pmc_type *type; int ret = 0; + if (!ofdev->dev.of_match) + return -EINVAL; + + type = ofdev->dev.of_match->data; + if (!of_device_is_available(np)) return -ENODEV; @@ -422,7 +426,7 @@ static struct of_device_id pmc_match[] = { {} }; -static struct of_platform_driver pmc_driver = { +static struct platform_driver pmc_driver = { .driver = { .name = "mpc83xx-pmc", .owner = THIS_MODULE, @@ -434,7 +438,7 @@ static struct of_platform_driver pmc_driver = { static int pmc_init(void) { - return of_register_platform_driver(&pmc_driver); + return platform_driver_register(&pmc_driver); } module_init(pmc_init); diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c index e3e379c6caa7..c35099af340e 100644 --- a/arch/powerpc/platforms/cell/axon_msi.c +++ b/arch/powerpc/platforms/cell/axon_msi.c @@ -328,7 +328,7 @@ static struct irq_host_ops msic_host_ops = { .map = msic_host_map, }; -static int axon_msi_shutdown(struct platform_device *device) +static void axon_msi_shutdown(struct platform_device *device) { struct axon_msic *msic = dev_get_drvdata(&device->dev); u32 tmp; @@ -338,12 +338,9 @@ static int axon_msi_shutdown(struct platform_device *device) tmp = dcr_read(msic->dcr_host, MSIC_CTRL_REG); tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE; msic_dcr_write(msic, MSIC_CTRL_REG, tmp); - - return 0; } -static int axon_msi_probe(struct platform_device *device, - const struct of_device_id *device_id) +static int axon_msi_probe(struct platform_device *device) { struct device_node *dn = device->dev.of_node; struct axon_msic *msic; @@ -446,7 +443,7 @@ static const struct of_device_id axon_msi_device_id[] = { {} }; -static struct of_platform_driver axon_msi_driver = { +static struct platform_driver axon_msi_driver = { .probe = axon_msi_probe, .shutdown = axon_msi_shutdown, .driver = { @@ -458,7 +455,7 @@ static struct of_platform_driver axon_msi_driver = { static int __init axon_msi_init(void) { - return of_register_platform_driver(&axon_msi_driver); + return platform_driver_register(&axon_msi_driver); } subsys_initcall(axon_msi_init); diff --git a/arch/powerpc/platforms/cell/spufs/syscalls.c b/arch/powerpc/platforms/cell/spufs/syscalls.c index 187a7d32f86a..a3d2ce54ea2e 100644 --- a/arch/powerpc/platforms/cell/spufs/syscalls.c +++ b/arch/powerpc/platforms/cell/spufs/syscalls.c @@ -70,7 +70,7 @@ static long do_spu_create(const char __user *pathname, unsigned int flags, if (!IS_ERR(tmp)) { struct nameidata nd; - ret = path_lookup(tmp, LOOKUP_PARENT, &nd); + ret = kern_path_parent(tmp, &nd); if (!ret) { nd.flags |= LOOKUP_OPEN | LOOKUP_CREATE; ret = spufs_create(&nd, flags, mode, neighbor); diff --git a/arch/powerpc/platforms/pasemi/gpio_mdio.c b/arch/powerpc/platforms/pasemi/gpio_mdio.c index a5d907b5a4c2..9886296e08da 100644 --- a/arch/powerpc/platforms/pasemi/gpio_mdio.c +++ b/arch/powerpc/platforms/pasemi/gpio_mdio.c @@ -216,8 +216,7 @@ static int gpio_mdio_reset(struct mii_bus *bus) } -static int __devinit gpio_mdio_probe(struct platform_device *ofdev, - const struct of_device_id *match) +static int __devinit gpio_mdio_probe(struct platform_device *ofdev) { struct device *dev = &ofdev->dev; struct device_node *np = ofdev->dev.of_node; @@ -299,7 +298,7 @@ static struct of_device_id gpio_mdio_match[] = }; MODULE_DEVICE_TABLE(of, gpio_mdio_match); -static struct of_platform_driver gpio_mdio_driver = +static struct platform_driver gpio_mdio_driver = { .probe = gpio_mdio_probe, .remove = gpio_mdio_remove, @@ -326,13 +325,13 @@ int gpio_mdio_init(void) if (!gpio_regs) return -ENODEV; - return of_register_platform_driver(&gpio_mdio_driver); + return platform_driver_register(&gpio_mdio_driver); } module_init(gpio_mdio_init); void gpio_mdio_exit(void) { - of_unregister_platform_driver(&gpio_mdio_driver); + platform_driver_unregister(&gpio_mdio_driver); if (gpio_regs) iounmap(gpio_regs); } diff --git a/arch/powerpc/platforms/powermac/cpufreq_32.c b/arch/powerpc/platforms/powermac/cpufreq_32.c index 415ca6d6b273..04af5f48b4eb 100644 --- a/arch/powerpc/platforms/powermac/cpufreq_32.c +++ b/arch/powerpc/platforms/powermac/cpufreq_32.c @@ -429,7 +429,7 @@ static u32 read_gpio(struct device_node *np) return offset; } -static int pmac_cpufreq_suspend(struct cpufreq_policy *policy, pm_message_t pmsg) +static int pmac_cpufreq_suspend(struct cpufreq_policy *policy) { /* Ok, this could be made a bit smarter, but let's be robust for now. We * always force a speed change to high speed before sleep, to make sure diff --git a/arch/powerpc/platforms/pseries/hotplug-memory.c b/arch/powerpc/platforms/pseries/hotplug-memory.c index bc8803664140..33867ec4a234 100644 --- a/arch/powerpc/platforms/pseries/hotplug-memory.c +++ b/arch/powerpc/platforms/pseries/hotplug-memory.c @@ -17,6 +17,54 @@ #include <asm/pSeries_reconfig.h> #include <asm/sparsemem.h> +static unsigned long get_memblock_size(void) +{ + struct device_node *np; + unsigned int memblock_size = 0; + + np = of_find_node_by_path("/ibm,dynamic-reconfiguration-memory"); + if (np) { + const unsigned long *size; + + size = of_get_property(np, "ibm,lmb-size", NULL); + memblock_size = size ? *size : 0; + + of_node_put(np); + } else { + unsigned int memzero_size = 0; + const unsigned int *regs; + + np = of_find_node_by_path("/memory@0"); + if (np) { + regs = of_get_property(np, "reg", NULL); + memzero_size = regs ? regs[3] : 0; + of_node_put(np); + } + + if (memzero_size) { + /* We now know the size of memory@0, use this to find + * the first memoryblock and get its size. + */ + char buf[64]; + + sprintf(buf, "/memory@%x", memzero_size); + np = of_find_node_by_path(buf); + if (np) { + regs = of_get_property(np, "reg", NULL); + memblock_size = regs ? regs[3] : 0; + of_node_put(np); + } + } + } + + return memblock_size; +} + +unsigned long memory_block_size_bytes(void) +{ + return get_memblock_size(); +} + static int pseries_remove_memblock(unsigned long base, unsigned int memblock_size) { unsigned long start, start_pfn; @@ -127,30 +175,22 @@ static int pseries_add_memory(struct device_node *np) static int pseries_drconf_memory(unsigned long *base, unsigned int action) { - struct device_node *np; - const unsigned long *lmb_size; + unsigned long memblock_size; int rc; - np = of_find_node_by_path("/ibm,dynamic-reconfiguration-memory"); - if (!np) + memblock_size = get_memblock_size(); + if (!memblock_size) return -EINVAL; - lmb_size = of_get_property(np, "ibm,lmb-size", NULL); - if (!lmb_size) { - of_node_put(np); - return -EINVAL; - } - if (action == PSERIES_DRCONF_MEM_ADD) { - rc = memblock_add(*base, *lmb_size); + rc = memblock_add(*base, memblock_size); rc = (rc < 0) ? -EINVAL : 0; } else if (action == PSERIES_DRCONF_MEM_REMOVE) { - rc = pseries_remove_memblock(*base, *lmb_size); + rc = pseries_remove_memblock(*base, memblock_size); } else { rc = -EINVAL; } - of_node_put(np); return rc; } diff --git a/arch/powerpc/platforms/pseries/pci_dlpar.c b/arch/powerpc/platforms/pseries/pci_dlpar.c index 5fcc92a12d3e..3bf4488aaec6 100644 --- a/arch/powerpc/platforms/pseries/pci_dlpar.c +++ b/arch/powerpc/platforms/pseries/pci_dlpar.c @@ -149,7 +149,7 @@ struct pci_controller * __devinit init_phb_dynamic(struct device_node *dn) if (dn->child) eeh_add_device_tree_early(dn); - pcibios_scan_phb(phb, dn); + pcibios_scan_phb(phb); pcibios_finish_adding_to_bus(phb->bus); return phb; diff --git a/arch/powerpc/sysdev/axonram.c b/arch/powerpc/sysdev/axonram.c index 2659a60bd7b8..27402c7d309d 100644 --- a/arch/powerpc/sysdev/axonram.c +++ b/arch/powerpc/sysdev/axonram.c @@ -172,10 +172,9 @@ static const struct block_device_operations axon_ram_devops = { /** * axon_ram_probe - probe() method for platform driver - * @device, @device_id: see of_platform_driver method + * @device: see platform_driver method */ -static int axon_ram_probe(struct platform_device *device, - const struct of_device_id *device_id) +static int axon_ram_probe(struct platform_device *device) { static int axon_ram_bank_id = -1; struct axon_ram_bank *bank; @@ -326,7 +325,7 @@ static struct of_device_id axon_ram_device_id[] = { {} }; -static struct of_platform_driver axon_ram_driver = { +static struct platform_driver axon_ram_driver = { .probe = axon_ram_probe, .remove = axon_ram_remove, .driver = { @@ -350,7 +349,7 @@ axon_ram_init(void) } azfs_minor = 0; - return of_register_platform_driver(&axon_ram_driver); + return platform_driver_register(&axon_ram_driver); } /** @@ -359,7 +358,7 @@ axon_ram_init(void) static void __exit axon_ram_exit(void) { - of_unregister_platform_driver(&axon_ram_driver); + platform_driver_unregister(&axon_ram_driver); unregister_blkdev(azfs_major, AXON_RAM_DEVICE_NAME); } diff --git a/arch/powerpc/sysdev/bestcomm/bestcomm.c b/arch/powerpc/sysdev/bestcomm/bestcomm.c index 650256115064..b3fbb271be87 100644 --- a/arch/powerpc/sysdev/bestcomm/bestcomm.c +++ b/arch/powerpc/sysdev/bestcomm/bestcomm.c @@ -365,8 +365,7 @@ bcom_engine_cleanup(void) /* OF platform driver */ /* ======================================================================== */ -static int __devinit mpc52xx_bcom_probe(struct platform_device *op, - const struct of_device_id *match) +static int __devinit mpc52xx_bcom_probe(struct platform_device *op) { struct device_node *ofn_sram; struct resource res_bcom; @@ -492,7 +491,7 @@ static struct of_device_id mpc52xx_bcom_of_match[] = { MODULE_DEVICE_TABLE(of, mpc52xx_bcom_of_match); -static struct of_platform_driver mpc52xx_bcom_of_platform_driver = { +static struct platform_driver mpc52xx_bcom_of_platform_driver = { .probe = mpc52xx_bcom_probe, .remove = mpc52xx_bcom_remove, .driver = { @@ -510,13 +509,13 @@ static struct of_platform_driver mpc52xx_bcom_of_platform_driver = { static int __init mpc52xx_bcom_init(void) { - return of_register_platform_driver(&mpc52xx_bcom_of_platform_driver); + return platform_driver_register(&mpc52xx_bcom_of_platform_driver); } static void __exit mpc52xx_bcom_exit(void) { - of_unregister_platform_driver(&mpc52xx_bcom_of_platform_driver); + platform_driver_unregister(&mpc52xx_bcom_of_platform_driver); } /* If we're not a module, we must make sure everything is setup before */ diff --git a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c index cc8d6556d799..2b9f0c925326 100644 --- a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c +++ b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c @@ -71,8 +71,7 @@ static int __init get_offset_from_cmdline(char *str) __setup("cache-sram-size=", get_size_from_cmdline); __setup("cache-sram-offset=", get_offset_from_cmdline); -static int __devinit mpc85xx_l2ctlr_of_probe(struct platform_device *dev, - const struct of_device_id *match) +static int __devinit mpc85xx_l2ctlr_of_probe(struct platform_device *dev) { long rval; unsigned int rem; @@ -204,7 +203,7 @@ static struct of_device_id mpc85xx_l2ctlr_of_match[] = { {}, }; -static struct of_platform_driver mpc85xx_l2ctlr_of_platform_driver = { +static struct platform_driver mpc85xx_l2ctlr_of_platform_driver = { .driver = { .name = "fsl-l2ctlr", .owner = THIS_MODULE, @@ -216,12 +215,12 @@ static struct of_platform_driver mpc85xx_l2ctlr_of_platform_driver = { static __init int mpc85xx_l2ctlr_of_init(void) { - return of_register_platform_driver(&mpc85xx_l2ctlr_of_platform_driver); + return platform_driver_register(&mpc85xx_l2ctlr_of_platform_driver); } static void __exit mpc85xx_l2ctlr_of_exit(void) { - of_unregister_platform_driver(&mpc85xx_l2ctlr_of_platform_driver); + platform_driver_unregister(&mpc85xx_l2ctlr_of_platform_driver); } subsys_initcall(mpc85xx_l2ctlr_of_init); diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c index 108d76fa8f1c..ee6a8a52ac71 100644 --- a/arch/powerpc/sysdev/fsl_msi.c +++ b/arch/powerpc/sysdev/fsl_msi.c @@ -273,8 +273,7 @@ static int fsl_of_msi_remove(struct platform_device *ofdev) return 0; } -static int __devinit fsl_of_msi_probe(struct platform_device *dev, - const struct of_device_id *match) +static int __devinit fsl_of_msi_probe(struct platform_device *dev) { struct fsl_msi *msi; struct resource res; @@ -282,11 +281,15 @@ static int __devinit fsl_of_msi_probe(struct platform_device *dev, int rc; int virt_msir; const u32 *p; - struct fsl_msi_feature *features = match->data; + struct fsl_msi_feature *features; struct fsl_msi_cascade_data *cascade_data = NULL; int len; u32 offset; + if (!dev->dev.of_match) + return -EINVAL; + features = dev->dev.of_match->data; + printk(KERN_DEBUG "Setting up Freescale MSI support\n"); msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL); @@ -411,7 +414,7 @@ static const struct of_device_id fsl_of_msi_ids[] = { {} }; -static struct of_platform_driver fsl_of_msi_driver = { +static struct platform_driver fsl_of_msi_driver = { .driver = { .name = "fsl-msi", .owner = THIS_MODULE, @@ -423,7 +426,7 @@ static struct of_platform_driver fsl_of_msi_driver = { static __init int fsl_of_msi_init(void) { - return of_register_platform_driver(&fsl_of_msi_driver); + return platform_driver_register(&fsl_of_msi_driver); } subsys_initcall(fsl_of_msi_init); diff --git a/arch/powerpc/sysdev/fsl_pmc.c b/arch/powerpc/sysdev/fsl_pmc.c index e9381bfefb21..f122e8961d32 100644 --- a/arch/powerpc/sysdev/fsl_pmc.c +++ b/arch/powerpc/sysdev/fsl_pmc.c @@ -58,8 +58,7 @@ static const struct platform_suspend_ops pmc_suspend_ops = { .enter = pmc_suspend_enter, }; -static int pmc_probe(struct platform_device *ofdev, - const struct of_device_id *id) +static int pmc_probe(struct platform_device *ofdev) { pmc_regs = of_iomap(ofdev->dev.of_node, 0); if (!pmc_regs) @@ -76,7 +75,7 @@ static const struct of_device_id pmc_ids[] = { { }, }; -static struct of_platform_driver pmc_driver = { +static struct platform_driver pmc_driver = { .driver = { .name = "fsl-pmc", .owner = THIS_MODULE, @@ -87,6 +86,6 @@ static struct of_platform_driver pmc_driver = { static int __init pmc_init(void) { - return of_register_platform_driver(&pmc_driver); + return platform_driver_register(&pmc_driver); } device_initcall(pmc_init); diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c index 8c6cab013278..3eff2c3a9ad5 100644 --- a/arch/powerpc/sysdev/fsl_rio.c +++ b/arch/powerpc/sysdev/fsl_rio.c @@ -1570,8 +1570,7 @@ err_ops: /* The probe function for RapidIO peer-to-peer network. */ -static int __devinit fsl_of_rio_rpn_probe(struct platform_device *dev, - const struct of_device_id *match) +static int __devinit fsl_of_rio_rpn_probe(struct platform_device *dev) { int rc; printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n", @@ -1594,7 +1593,7 @@ static const struct of_device_id fsl_of_rio_rpn_ids[] = { {}, }; -static struct of_platform_driver fsl_of_rio_rpn_driver = { +static struct platform_driver fsl_of_rio_rpn_driver = { .driver = { .name = "fsl-of-rio", .owner = THIS_MODULE, @@ -1605,7 +1604,7 @@ static struct of_platform_driver fsl_of_rio_rpn_driver = { static __init int fsl_of_rio_rpn_init(void) { - return of_register_platform_driver(&fsl_of_rio_rpn_driver); + return platform_driver_register(&fsl_of_rio_rpn_driver); } subsys_initcall(fsl_of_rio_rpn_init); diff --git a/arch/powerpc/sysdev/pmi.c b/arch/powerpc/sysdev/pmi.c index 4260f368db52..8ce4fc3d9828 100644 --- a/arch/powerpc/sysdev/pmi.c +++ b/arch/powerpc/sysdev/pmi.c @@ -121,8 +121,7 @@ static void pmi_notify_handlers(struct work_struct *work) spin_unlock(&data->handler_spinlock); } -static int pmi_of_probe(struct platform_device *dev, - const struct of_device_id *match) +static int pmi_of_probe(struct platform_device *dev) { struct device_node *np = dev->dev.of_node; int rc; @@ -205,7 +204,7 @@ static int pmi_of_remove(struct platform_device *dev) return 0; } -static struct of_platform_driver pmi_of_platform_driver = { +static struct platform_driver pmi_of_platform_driver = { .probe = pmi_of_probe, .remove = pmi_of_remove, .driver = { @@ -217,13 +216,13 @@ static struct of_platform_driver pmi_of_platform_driver = { static int __init pmi_module_init(void) { - return of_register_platform_driver(&pmi_of_platform_driver); + return platform_driver_register(&pmi_of_platform_driver); } module_init(pmi_module_init); static void __exit pmi_module_exit(void) { - of_unregister_platform_driver(&pmi_of_platform_driver); + platform_driver_unregister(&pmi_of_platform_driver); } module_exit(pmi_module_exit); diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c index 90020de4dcf2..904c6cbaf45b 100644 --- a/arch/powerpc/sysdev/qe_lib/qe.c +++ b/arch/powerpc/sysdev/qe_lib/qe.c @@ -659,8 +659,7 @@ static int qe_resume(struct platform_device *ofdev) return 0; } -static int qe_probe(struct platform_device *ofdev, - const struct of_device_id *id) +static int qe_probe(struct platform_device *ofdev) { return 0; } @@ -670,7 +669,7 @@ static const struct of_device_id qe_ids[] = { { }, }; -static struct of_platform_driver qe_driver = { +static struct platform_driver qe_driver = { .driver = { .name = "fsl-qe", .owner = THIS_MODULE, @@ -682,7 +681,7 @@ static struct of_platform_driver qe_driver = { static int __init qe_drv_init(void) { - return of_register_platform_driver(&qe_driver); + return platform_driver_register(&qe_driver); } device_initcall(qe_drv_init); #endif /* defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx) */ diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index 636bcb81d068..2508a6f31588 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -85,6 +85,7 @@ config S390 select HAVE_KERNEL_BZIP2 select HAVE_KERNEL_LZMA select HAVE_KERNEL_LZO + select HAVE_KERNEL_XZ select HAVE_GET_USER_PAGES_FAST select HAVE_ARCH_MUTEX_CPU_RELAX select ARCH_INLINE_SPIN_TRYLOCK @@ -341,26 +342,16 @@ config STACK_GUARD The minimum size for the stack guard should be 256 for 31 bit and 512 for 64 bit. -config WARN_STACK +config WARN_DYNAMIC_STACK def_bool n - prompt "Emit compiler warnings for function with broken stack usage" + prompt "Emit compiler warnings for function with dynamic stack usage" help - This option enables the compiler options -mwarn-framesize and - -mwarn-dynamicstack. If the compiler supports these options it - will generate warnings for function which either use alloca or - create a stack frame bigger than CONFIG_WARN_STACK_SIZE. + This option enables the compiler option -mwarn-dynamicstack. If the + compiler supports this options generates warnings for functions + that dynamically allocate stack space using alloca. Say N if you are unsure. -config WARN_STACK_SIZE - int "Maximum frame size considered safe (128-2048)" - range 128 2048 - depends on WARN_STACK - default "2048" - help - This allows you to specify the maximum frame size a function may - have without the compiler complaining about it. - config ARCH_POPULATES_NODE_MAP def_bool y diff --git a/arch/s390/Kconfig.debug b/arch/s390/Kconfig.debug index 2b380df95606..d76cef3fef37 100644 --- a/arch/s390/Kconfig.debug +++ b/arch/s390/Kconfig.debug @@ -31,4 +31,7 @@ config DEBUG_STRICT_USER_COPY_CHECKS If unsure, or if you run an older (pre 4.4) gcc, say N. +config DEBUG_SET_MODULE_RONX + def_bool y + depends on MODULES endmenu diff --git a/arch/s390/Makefile b/arch/s390/Makefile index d5b8a6ade525..27a0b5df5ead 100644 --- a/arch/s390/Makefile +++ b/arch/s390/Makefile @@ -80,8 +80,7 @@ endif endif ifeq ($(call cc-option-yn,-mwarn-dynamicstack),y) -cflags-$(CONFIG_WARN_STACK) += -mwarn-dynamicstack -cflags-$(CONFIG_WARN_STACK) += -mwarn-framesize=$(CONFIG_WARN_STACK_SIZE) +cflags-$(CONFIG_WARN_DYNAMIC_STACK) += -mwarn-dynamicstack endif KBUILD_CFLAGS += -mbackchain -msoft-float $(cflags-y) diff --git a/arch/s390/boot/compressed/Makefile b/arch/s390/boot/compressed/Makefile index 1c999f726a58..10e22c4ec4a7 100644 --- a/arch/s390/boot/compressed/Makefile +++ b/arch/s390/boot/compressed/Makefile @@ -7,7 +7,8 @@ BITS := $(if $(CONFIG_64BIT),64,31) targets := vmlinux.lds vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 \ - vmlinux.bin.lzma vmlinux.bin.lzo misc.o piggy.o sizes.h head$(BITS).o + vmlinux.bin.xz vmlinux.bin.lzma vmlinux.bin.lzo misc.o piggy.o \ + sizes.h head$(BITS).o KBUILD_CFLAGS := -m$(BITS) -D__KERNEL__ $(LINUX_INCLUDE) -O2 KBUILD_CFLAGS += $(cflags-y) @@ -48,6 +49,7 @@ suffix-$(CONFIG_KERNEL_GZIP) := gz suffix-$(CONFIG_KERNEL_BZIP2) := bz2 suffix-$(CONFIG_KERNEL_LZMA) := lzma suffix-$(CONFIG_KERNEL_LZO) := lzo +suffix-$(CONFIG_KERNEL_XZ) := xz $(obj)/vmlinux.bin.gz: $(vmlinux.bin.all-y) $(call if_changed,gzip) @@ -57,6 +59,8 @@ $(obj)/vmlinux.bin.lzma: $(vmlinux.bin.all-y) $(call if_changed,lzma) $(obj)/vmlinux.bin.lzo: $(vmlinux.bin.all-y) $(call if_changed,lzo) +$(obj)/vmlinux.bin.xz: $(vmlinux.bin.all-y) + $(call if_changed,xzkern) LDFLAGS_piggy.o := -r --format binary --oformat $(LD_BFD) -T $(obj)/piggy.o: $(obj)/vmlinux.scr $(obj)/vmlinux.bin.$(suffix-y) diff --git a/arch/s390/boot/compressed/misc.c b/arch/s390/boot/compressed/misc.c index 2751b3a8a66f..028f23ea81d1 100644 --- a/arch/s390/boot/compressed/misc.c +++ b/arch/s390/boot/compressed/misc.c @@ -19,6 +19,7 @@ #undef memset #undef memcpy #undef memmove +#define memmove memmove #define memzero(s, n) memset((s), 0, (n)) /* Symbols defined by linker scripts */ @@ -54,6 +55,10 @@ static unsigned long free_mem_end_ptr; #include "../../../../lib/decompress_unlzo.c" #endif +#ifdef CONFIG_KERNEL_XZ +#include "../../../../lib/decompress_unxz.c" +#endif + extern _sclp_print_early(const char *); int puts(const char *s) diff --git a/arch/s390/include/asm/cacheflush.h b/arch/s390/include/asm/cacheflush.h index 7e1f77620624..43a5c78046db 100644 --- a/arch/s390/include/asm/cacheflush.h +++ b/arch/s390/include/asm/cacheflush.h @@ -8,4 +8,8 @@ void kernel_map_pages(struct page *page, int numpages, int enable); #endif +int set_memory_ro(unsigned long addr, int numpages); +int set_memory_rw(unsigned long addr, int numpages); +int set_memory_nx(unsigned long addr, int numpages); + #endif /* _S390_CACHEFLUSH_H */ diff --git a/arch/s390/include/asm/futex.h b/arch/s390/include/asm/futex.h index 5c5d02de49e9..81cf36b691f1 100644 --- a/arch/s390/include/asm/futex.h +++ b/arch/s390/include/asm/futex.h @@ -7,7 +7,7 @@ #include <linux/uaccess.h> #include <asm/errno.h> -static inline int futex_atomic_op_inuser (int encoded_op, int __user *uaddr) +static inline int futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr) { int op = (encoded_op >> 28) & 7; int cmp = (encoded_op >> 24) & 15; @@ -18,7 +18,7 @@ static inline int futex_atomic_op_inuser (int encoded_op, int __user *uaddr) if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) oparg = 1 << oparg; - if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int))) + if (! access_ok (VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; pagefault_disable(); @@ -39,13 +39,13 @@ static inline int futex_atomic_op_inuser (int encoded_op, int __user *uaddr) return ret; } -static inline int futex_atomic_cmpxchg_inatomic(int __user *uaddr, - int oldval, int newval) +static inline int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) { - if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int))) + if (! access_ok (VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; - return uaccess.futex_atomic_cmpxchg(uaddr, oldval, newval); + return uaccess.futex_atomic_cmpxchg(uval, uaddr, oldval, newval); } #endif /* __KERNEL__ */ diff --git a/arch/s390/include/asm/rwsem.h b/arch/s390/include/asm/rwsem.h index 423fdda2322d..d0eb4653cebd 100644 --- a/arch/s390/include/asm/rwsem.h +++ b/arch/s390/include/asm/rwsem.h @@ -43,29 +43,6 @@ #ifdef __KERNEL__ -#include <linux/list.h> -#include <linux/spinlock.h> - -struct rwsem_waiter; - -extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *); -extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *); -extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *); -extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *); -extern struct rw_semaphore *rwsem_downgrade_write(struct rw_semaphore *); - -/* - * the semaphore definition - */ -struct rw_semaphore { - signed long count; - spinlock_t wait_lock; - struct list_head wait_list; -#ifdef CONFIG_DEBUG_LOCK_ALLOC - struct lockdep_map dep_map; -#endif -}; - #ifndef __s390x__ #define RWSEM_UNLOCKED_VALUE 0x00000000 #define RWSEM_ACTIVE_BIAS 0x00000001 @@ -81,41 +58,6 @@ struct rw_semaphore { #define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS) /* - * initialisation - */ - -#ifdef CONFIG_DEBUG_LOCK_ALLOC -# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname } -#else -# define __RWSEM_DEP_MAP_INIT(lockname) -#endif - -#define __RWSEM_INITIALIZER(name) \ - { RWSEM_UNLOCKED_VALUE, __SPIN_LOCK_UNLOCKED((name).wait.lock), \ - LIST_HEAD_INIT((name).wait_list) __RWSEM_DEP_MAP_INIT(name) } - -#define DECLARE_RWSEM(name) \ - struct rw_semaphore name = __RWSEM_INITIALIZER(name) - -static inline void init_rwsem(struct rw_semaphore *sem) -{ - sem->count = RWSEM_UNLOCKED_VALUE; - spin_lock_init(&sem->wait_lock); - INIT_LIST_HEAD(&sem->wait_list); -} - -extern void __init_rwsem(struct rw_semaphore *sem, const char *name, - struct lock_class_key *key); - -#define init_rwsem(sem) \ -do { \ - static struct lock_class_key __key; \ - \ - __init_rwsem((sem), #sem, &__key); \ -} while (0) - - -/* * lock for reading */ static inline void __down_read(struct rw_semaphore *sem) @@ -377,10 +319,5 @@ static inline long rwsem_atomic_update(long delta, struct rw_semaphore *sem) return new; } -static inline int rwsem_is_locked(struct rw_semaphore *sem) -{ - return (sem->count != 0); -} - #endif /* __KERNEL__ */ #endif /* _S390_RWSEM_H */ diff --git a/arch/s390/include/asm/uaccess.h b/arch/s390/include/asm/uaccess.h index d6b1ed0ec52b..2d9ea11f919a 100644 --- a/arch/s390/include/asm/uaccess.h +++ b/arch/s390/include/asm/uaccess.h @@ -83,8 +83,8 @@ struct uaccess_ops { size_t (*clear_user)(size_t, void __user *); size_t (*strnlen_user)(size_t, const char __user *); size_t (*strncpy_from_user)(size_t, const char __user *, char *); - int (*futex_atomic_op)(int op, int __user *, int oparg, int *old); - int (*futex_atomic_cmpxchg)(int __user *, int old, int new); + int (*futex_atomic_op)(int op, u32 __user *, int oparg, int *old); + int (*futex_atomic_cmpxchg)(u32 *, u32 __user *, u32 old, u32 new); }; extern struct uaccess_ops uaccess; diff --git a/arch/s390/kernel/machine_kexec.c b/arch/s390/kernel/machine_kexec.c index a922d51df6bf..b09b9c62573e 100644 --- a/arch/s390/kernel/machine_kexec.c +++ b/arch/s390/kernel/machine_kexec.c @@ -12,6 +12,7 @@ #include <linux/kexec.h> #include <linux/delay.h> #include <linux/reboot.h> +#include <linux/ftrace.h> #include <asm/cio.h> #include <asm/setup.h> #include <asm/pgtable.h> @@ -71,6 +72,7 @@ static void __machine_kexec(void *data) void machine_kexec(struct kimage *image) { + tracer_disable(); smp_send_stop(); smp_switch_to_ipl_cpu(__machine_kexec, image); } diff --git a/arch/s390/kernel/vmlinux.lds.S b/arch/s390/kernel/vmlinux.lds.S index a68ac10213b2..1bc18cdb525b 100644 --- a/arch/s390/kernel/vmlinux.lds.S +++ b/arch/s390/kernel/vmlinux.lds.S @@ -77,7 +77,7 @@ SECTIONS . = ALIGN(PAGE_SIZE); INIT_DATA_SECTION(0x100) - PERCPU(PAGE_SIZE) + PERCPU(0x100, PAGE_SIZE) . = ALIGN(PAGE_SIZE); __init_end = .; /* freed after init ends here */ diff --git a/arch/s390/lib/uaccess.h b/arch/s390/lib/uaccess.h index 126011df14f1..1d2536cb630b 100644 --- a/arch/s390/lib/uaccess.h +++ b/arch/s390/lib/uaccess.h @@ -12,12 +12,12 @@ extern size_t copy_from_user_std(size_t, const void __user *, void *); extern size_t copy_to_user_std(size_t, void __user *, const void *); extern size_t strnlen_user_std(size_t, const char __user *); extern size_t strncpy_from_user_std(size_t, const char __user *, char *); -extern int futex_atomic_cmpxchg_std(int __user *, int, int); -extern int futex_atomic_op_std(int, int __user *, int, int *); +extern int futex_atomic_cmpxchg_std(u32 *, u32 __user *, u32, u32); +extern int futex_atomic_op_std(int, u32 __user *, int, int *); extern size_t copy_from_user_pt(size_t, const void __user *, void *); extern size_t copy_to_user_pt(size_t, void __user *, const void *); -extern int futex_atomic_op_pt(int, int __user *, int, int *); -extern int futex_atomic_cmpxchg_pt(int __user *, int, int); +extern int futex_atomic_op_pt(int, u32 __user *, int, int *); +extern int futex_atomic_cmpxchg_pt(u32 *, u32 __user *, u32, u32); #endif /* __ARCH_S390_LIB_UACCESS_H */ diff --git a/arch/s390/lib/uaccess_pt.c b/arch/s390/lib/uaccess_pt.c index 404f2de296dc..74833831417f 100644 --- a/arch/s390/lib/uaccess_pt.c +++ b/arch/s390/lib/uaccess_pt.c @@ -302,7 +302,7 @@ fault: : "0" (-EFAULT), "d" (oparg), "a" (uaddr), \ "m" (*uaddr) : "cc" ); -static int __futex_atomic_op_pt(int op, int __user *uaddr, int oparg, int *old) +static int __futex_atomic_op_pt(int op, u32 __user *uaddr, int oparg, int *old) { int oldval = 0, newval, ret; @@ -335,7 +335,7 @@ static int __futex_atomic_op_pt(int op, int __user *uaddr, int oparg, int *old) return ret; } -int futex_atomic_op_pt(int op, int __user *uaddr, int oparg, int *old) +int futex_atomic_op_pt(int op, u32 __user *uaddr, int oparg, int *old) { int ret; @@ -354,26 +354,29 @@ int futex_atomic_op_pt(int op, int __user *uaddr, int oparg, int *old) return ret; } -static int __futex_atomic_cmpxchg_pt(int __user *uaddr, int oldval, int newval) +static int __futex_atomic_cmpxchg_pt(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) { int ret; asm volatile("0: cs %1,%4,0(%5)\n" - "1: lr %0,%1\n" + "1: la %0,0\n" "2:\n" EX_TABLE(0b,2b) EX_TABLE(1b,2b) : "=d" (ret), "+d" (oldval), "=m" (*uaddr) : "0" (-EFAULT), "d" (newval), "a" (uaddr), "m" (*uaddr) : "cc", "memory" ); + *uval = oldval; return ret; } -int futex_atomic_cmpxchg_pt(int __user *uaddr, int oldval, int newval) +int futex_atomic_cmpxchg_pt(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) { int ret; if (segment_eq(get_fs(), KERNEL_DS)) - return __futex_atomic_cmpxchg_pt(uaddr, oldval, newval); + return __futex_atomic_cmpxchg_pt(uval, uaddr, oldval, newval); spin_lock(¤t->mm->page_table_lock); uaddr = (int __user *) __dat_user_addr((unsigned long) uaddr); if (!uaddr) { @@ -382,7 +385,7 @@ int futex_atomic_cmpxchg_pt(int __user *uaddr, int oldval, int newval) } get_page(virt_to_page(uaddr)); spin_unlock(¤t->mm->page_table_lock); - ret = __futex_atomic_cmpxchg_pt(uaddr, oldval, newval); + ret = __futex_atomic_cmpxchg_pt(uval, uaddr, oldval, newval); put_page(virt_to_page(uaddr)); return ret; } diff --git a/arch/s390/lib/uaccess_std.c b/arch/s390/lib/uaccess_std.c index a6c4f7ed24a4..bb1a7eed42ce 100644 --- a/arch/s390/lib/uaccess_std.c +++ b/arch/s390/lib/uaccess_std.c @@ -255,7 +255,7 @@ size_t strncpy_from_user_std(size_t size, const char __user *src, char *dst) : "0" (-EFAULT), "d" (oparg), "a" (uaddr), \ "m" (*uaddr) : "cc"); -int futex_atomic_op_std(int op, int __user *uaddr, int oparg, int *old) +int futex_atomic_op_std(int op, u32 __user *uaddr, int oparg, int *old) { int oldval = 0, newval, ret; @@ -287,19 +287,21 @@ int futex_atomic_op_std(int op, int __user *uaddr, int oparg, int *old) return ret; } -int futex_atomic_cmpxchg_std(int __user *uaddr, int oldval, int newval) +int futex_atomic_cmpxchg_std(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) { int ret; asm volatile( " sacf 256\n" "0: cs %1,%4,0(%5)\n" - "1: lr %0,%1\n" + "1: la %0,0\n" "2: sacf 0\n" EX_TABLE(0b,2b) EX_TABLE(1b,2b) : "=d" (ret), "+d" (oldval), "=m" (*uaddr) : "0" (-EFAULT), "d" (newval), "a" (uaddr), "m" (*uaddr) : "cc", "memory" ); + *uval = oldval; return ret; } diff --git a/arch/s390/mm/Makefile b/arch/s390/mm/Makefile index 6fbc6f3fbdf2..d98fe9004a52 100644 --- a/arch/s390/mm/Makefile +++ b/arch/s390/mm/Makefile @@ -6,3 +6,4 @@ obj-y := init.o fault.o extmem.o mmap.o vmem.o pgtable.o maccess.o \ page-states.o gup.o obj-$(CONFIG_CMM) += cmm.o obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o +obj-$(CONFIG_DEBUG_SET_MODULE_RONX) += pageattr.o diff --git a/arch/s390/mm/pageattr.c b/arch/s390/mm/pageattr.c new file mode 100644 index 000000000000..122ffbd08ce0 --- /dev/null +++ b/arch/s390/mm/pageattr.c @@ -0,0 +1,55 @@ +/* + * Copyright IBM Corp. 2011 + * Author(s): Jan Glauber <jang@linux.vnet.ibm.com> + */ +#include <linux/module.h> +#include <linux/mm.h> +#include <linux/hugetlb.h> +#include <asm/pgtable.h> + +static void change_page_attr(unsigned long addr, int numpages, + pte_t (*set) (pte_t)) +{ + pte_t *ptep, pte; + pmd_t *pmdp; + pud_t *pudp; + pgd_t *pgdp; + int i; + + for (i = 0; i < numpages; i++) { + pgdp = pgd_offset(&init_mm, addr); + pudp = pud_offset(pgdp, addr); + pmdp = pmd_offset(pudp, addr); + if (pmd_huge(*pmdp)) { + WARN_ON_ONCE(1); + continue; + } + ptep = pte_offset_kernel(pmdp, addr + i * PAGE_SIZE); + + pte = *ptep; + pte = set(pte); + ptep_invalidate(&init_mm, addr + i * PAGE_SIZE, ptep); + *ptep = pte; + } +} + +int set_memory_ro(unsigned long addr, int numpages) +{ + change_page_attr(addr, numpages, pte_wrprotect); + return 0; +} +EXPORT_SYMBOL_GPL(set_memory_ro); + +int set_memory_rw(unsigned long addr, int numpages) +{ + change_page_attr(addr, numpages, pte_mkwrite); + return 0; +} +EXPORT_SYMBOL_GPL(set_memory_rw); + +/* not possible */ +int set_memory_nx(unsigned long addr, int numpages) +{ + return 0; +} +EXPORT_SYMBOL_GPL(set_memory_nx); diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 8a9011dced14..2d264fa84959 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -25,6 +25,7 @@ config SUPERH select GENERIC_ATOMIC64 # Support the deprecated APIs until MFD and GPIOLIB catch up. select GENERIC_HARDIRQS_NO_DEPRECATED if !MFD_SUPPORT && !GPIOLIB + select GENERIC_IRQ_SHOW help The SuperH is a RISC processor targeted for use in embedded systems and consumer electronics; it was also used in the Sega Dreamcast @@ -434,6 +435,8 @@ config CPU_SUBTYPE_SH7757 select CPU_SH4A select CPU_SHX2 select ARCH_WANT_OPTIONAL_GPIOLIB + select USB_ARCH_HAS_OHCI + select USB_ARCH_HAS_EHCI help Select SH7757 if you have a SH4A SH7757 CPU. diff --git a/arch/sh/boards/board-espt.c b/arch/sh/boards/board-espt.c index d5ce5e18eb37..9da92ac36533 100644 --- a/arch/sh/boards/board-espt.c +++ b/arch/sh/boards/board-espt.c @@ -66,6 +66,11 @@ static struct resource sh_eth_resources[] = { .end = 0xFEE00F7C - 1, .flags = IORESOURCE_MEM, }, { + .start = 0xFEE01800, /* TSU */ + .end = 0xFEE01FFF, + .flags = IORESOURCE_MEM, + }, { + .start = 57, /* irq number */ .flags = IORESOURCE_IRQ, }, @@ -74,6 +79,8 @@ static struct resource sh_eth_resources[] = { static struct sh_eth_plat_data sh7763_eth_pdata = { .phy = 0, .edmac_endian = EDMAC_LITTLE_ENDIAN, + .register_type = SH_ETH_REG_GIGABIT, + .phy_interface = PHY_INTERFACE_MODE_MII, }; static struct platform_device espt_eth_device = { diff --git a/arch/sh/boards/board-sh7757lcr.c b/arch/sh/boards/board-sh7757lcr.c index c475f1056ab4..a9e33569ad38 100644 --- a/arch/sh/boards/board-sh7757lcr.c +++ b/arch/sh/boards/board-sh7757lcr.c @@ -15,6 +15,9 @@ #include <linux/spi/spi.h> #include <linux/spi/flash.h> #include <linux/io.h> +#include <linux/mmc/host.h> +#include <linux/mmc/sh_mmcif.h> +#include <linux/mfd/sh_mobile_sdhi.h> #include <cpu/sh7757.h> #include <asm/sh_eth.h> #include <asm/heartbeat.h> @@ -44,6 +47,17 @@ static struct platform_device heartbeat_device = { }; /* Fast Ethernet */ +#define GBECONT 0xffc10100 +#define GBECONT_RMII1 BIT(17) +#define GBECONT_RMII0 BIT(16) +static void sh7757_eth_set_mdio_gate(unsigned long addr) +{ + if ((addr & 0x00000fff) < 0x0800) + writel(readl(GBECONT) | GBECONT_RMII0, GBECONT); + else + writel(readl(GBECONT) | GBECONT_RMII1, GBECONT); +} + static struct resource sh_eth0_resources[] = { { .start = 0xfef00000, @@ -59,6 +73,8 @@ static struct resource sh_eth0_resources[] = { static struct sh_eth_plat_data sh7757_eth0_pdata = { .phy = 1, .edmac_endian = EDMAC_LITTLE_ENDIAN, + .register_type = SH_ETH_REG_FAST_SH4, + .set_mdio_gate = sh7757_eth_set_mdio_gate, }; static struct platform_device sh7757_eth0_device = { @@ -86,6 +102,8 @@ static struct resource sh_eth1_resources[] = { static struct sh_eth_plat_data sh7757_eth1_pdata = { .phy = 1, .edmac_endian = EDMAC_LITTLE_ENDIAN, + .register_type = SH_ETH_REG_FAST_SH4, + .set_mdio_gate = sh7757_eth_set_mdio_gate, }; static struct platform_device sh7757_eth1_device = { @@ -98,10 +116,173 @@ static struct platform_device sh7757_eth1_device = { }, }; +static void sh7757_eth_giga_set_mdio_gate(unsigned long addr) +{ + if ((addr & 0x00000fff) < 0x0800) { + gpio_set_value(GPIO_PTT4, 1); + writel(readl(GBECONT) & ~GBECONT_RMII0, GBECONT); + } else { + gpio_set_value(GPIO_PTT4, 0); + writel(readl(GBECONT) & ~GBECONT_RMII1, GBECONT); + } +} + +static struct resource sh_eth_giga0_resources[] = { + { + .start = 0xfee00000, + .end = 0xfee007ff, + .flags = IORESOURCE_MEM, + }, { + /* TSU */ + .start = 0xfee01800, + .end = 0xfee01fff, + .flags = IORESOURCE_MEM, + }, { + .start = 315, + .end = 315, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_eth_plat_data sh7757_eth_giga0_pdata = { + .phy = 18, + .edmac_endian = EDMAC_LITTLE_ENDIAN, + .register_type = SH_ETH_REG_GIGABIT, + .set_mdio_gate = sh7757_eth_giga_set_mdio_gate, + .phy_interface = PHY_INTERFACE_MODE_RGMII_ID, +}; + +static struct platform_device sh7757_eth_giga0_device = { + .name = "sh-eth", + .resource = sh_eth_giga0_resources, + .id = 2, + .num_resources = ARRAY_SIZE(sh_eth_giga0_resources), + .dev = { + .platform_data = &sh7757_eth_giga0_pdata, + }, +}; + +static struct resource sh_eth_giga1_resources[] = { + { + .start = 0xfee00800, + .end = 0xfee00fff, + .flags = IORESOURCE_MEM, + }, { + .start = 316, + .end = 316, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_eth_plat_data sh7757_eth_giga1_pdata = { + .phy = 19, + .edmac_endian = EDMAC_LITTLE_ENDIAN, + .register_type = SH_ETH_REG_GIGABIT, + .set_mdio_gate = sh7757_eth_giga_set_mdio_gate, + .phy_interface = PHY_INTERFACE_MODE_RGMII_ID, +}; + +static struct platform_device sh7757_eth_giga1_device = { + .name = "sh-eth", + .resource = sh_eth_giga1_resources, + .id = 3, + .num_resources = ARRAY_SIZE(sh_eth_giga1_resources), + .dev = { + .platform_data = &sh7757_eth_giga1_pdata, + }, +}; + +/* SH_MMCIF */ +static struct resource sh_mmcif_resources[] = { + [0] = { + .start = 0xffcb0000, + .end = 0xffcb00ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 211, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = 212, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_mmcif_dma sh7757lcr_mmcif_dma = { + .chan_priv_tx = SHDMA_SLAVE_MMCIF_TX, + .chan_priv_rx = SHDMA_SLAVE_MMCIF_RX, +}; + +static struct sh_mmcif_plat_data sh_mmcif_plat = { + .dma = &sh7757lcr_mmcif_dma, + .sup_pclk = 0x0f, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .ocr = MMC_VDD_32_33 | MMC_VDD_33_34, +}; + +static struct platform_device sh_mmcif_device = { + .name = "sh_mmcif", + .id = 0, + .dev = { + .platform_data = &sh_mmcif_plat, + }, + .num_resources = ARRAY_SIZE(sh_mmcif_resources), + .resource = sh_mmcif_resources, +}; + +/* SDHI0 */ +static struct sh_mobile_sdhi_info sdhi_info = { + .dma_slave_tx = SHDMA_SLAVE_SDHI_TX, + .dma_slave_rx = SHDMA_SLAVE_SDHI_RX, + .tmio_caps = MMC_CAP_SD_HIGHSPEED, +}; + +static struct resource sdhi_resources[] = { + [0] = { + .start = 0xffe50000, + .end = 0xffe501ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 20, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sdhi_device = { + .name = "sh_mobile_sdhi", + .num_resources = ARRAY_SIZE(sdhi_resources), + .resource = sdhi_resources, + .id = 0, + .dev = { + .platform_data = &sdhi_info, + }, +}; + static struct platform_device *sh7757lcr_devices[] __initdata = { &heartbeat_device, &sh7757_eth0_device, &sh7757_eth1_device, + &sh7757_eth_giga0_device, + &sh7757_eth_giga1_device, + &sh_mmcif_device, + &sdhi_device, +}; + +static struct flash_platform_data spi_flash_data = { + .name = "m25p80", + .type = "m25px64", +}; + +static struct spi_board_info spi_board_info[] = { + { + .modalias = "m25p80", + .max_speed_hz = 25000000, + .bus_num = 0, + .chip_select = 1, + .platform_data = &spi_flash_data, + }, }; static int __init sh7757lcr_devices_setup(void) @@ -332,6 +513,10 @@ static int __init sh7757lcr_devices_setup(void) gpio_request(GPIO_PTT5, NULL); /* eMMC_PRST# */ gpio_direction_output(GPIO_PTT5, 1); + /* register SPI device information */ + spi_register_board_info(spi_board_info, + ARRAY_SIZE(spi_board_info)); + /* General platform */ return platform_add_devices(sh7757lcr_devices, ARRAY_SIZE(sh7757lcr_devices)); diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c index 701667acfd89..3b71d2190de1 100644 --- a/arch/sh/boards/mach-ecovec24/setup.c +++ b/arch/sh/boards/mach-ecovec24/setup.c @@ -142,6 +142,8 @@ static struct resource sh_eth_resources[] = { static struct sh_eth_plat_data sh_eth_plat = { .phy = 0x1f, /* SMSC LAN8700 */ .edmac_endian = EDMAC_LITTLE_ENDIAN, + .register_type = SH_ETH_REG_FAST_SH4, + .phy_interface = PHY_INTERFACE_MODE_MII, .ether_link_active_low = 1 }; diff --git a/arch/sh/boards/mach-sh7763rdp/setup.c b/arch/sh/boards/mach-sh7763rdp/setup.c index f64a6918224c..f3d828f133e5 100644 --- a/arch/sh/boards/mach-sh7763rdp/setup.c +++ b/arch/sh/boards/mach-sh7763rdp/setup.c @@ -75,6 +75,10 @@ static struct resource sh_eth_resources[] = { .end = 0xFEE00F7C - 1, .flags = IORESOURCE_MEM, }, { + .start = 0xFEE01800, /* TSU */ + .end = 0xFEE01FFF, + .flags = IORESOURCE_MEM, + }, { .start = 57, /* irq number */ .flags = IORESOURCE_IRQ, }, @@ -83,6 +87,8 @@ static struct resource sh_eth_resources[] = { static struct sh_eth_plat_data sh7763_eth_pdata = { .phy = 1, .edmac_endian = EDMAC_LITTLE_ENDIAN, + .register_type = SH_ETH_REG_GIGABIT, + .phy_interface = PHY_INTERFACE_MODE_MII, }; static struct platform_device sh7763rdp_eth_device = { diff --git a/arch/sh/boot/compressed/Makefile b/arch/sh/boot/compressed/Makefile index e0b0293bae63..780e083e4d17 100644 --- a/arch/sh/boot/compressed/Makefile +++ b/arch/sh/boot/compressed/Makefile @@ -11,6 +11,8 @@ targets := vmlinux vmlinux.bin vmlinux.bin.gz \ OBJECTS = $(obj)/head_$(BITS).o $(obj)/misc.o $(obj)/cache.o +GCOV_PROFILE := n + # # IMAGE_OFFSET is the load offset of the compression loader # diff --git a/arch/sh/configs/sh7757lcr_defconfig b/arch/sh/configs/sh7757lcr_defconfig index 5f7f667b9f3b..fa0ecf87034c 100644 --- a/arch/sh/configs/sh7757lcr_defconfig +++ b/arch/sh/configs/sh7757lcr_defconfig @@ -38,7 +38,15 @@ CONFIG_IPV6=y # CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set +CONFIG_MTD=y +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_M25P80=y CONFIG_BLK_DEV_RAM=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y CONFIG_NETDEVICES=y CONFIG_VITESSE_PHY=y CONFIG_NET_ETHERNET=y @@ -53,8 +61,17 @@ CONFIG_SERIAL_SH_SCI_NR_UARTS=3 CONFIG_SERIAL_SH_SCI_CONSOLE=y # CONFIG_LEGACY_PTYS is not set # CONFIG_HW_RANDOM is not set +CONFIG_SPI=y +CONFIG_SPI_SH=y # CONFIG_HWMON is not set -# CONFIG_USB_SUPPORT is not set +CONFIG_MFD_SH_MOBILE_SDHI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_MMC=y +CONFIG_MMC_TMIO=y +CONFIG_MMC_SH_MMCIF=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_ISO9660_FS=y diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index 96e9b058aa1d..4418f9070ed1 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -1,16 +1,19 @@ /* * Low-Level PCI Express Support for the SH7786 * - * Copyright (C) 2009 - 2010 Paul Mundt + * Copyright (C) 2009 - 2011 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. */ +#define pr_fmt(fmt) "PCI: " fmt + #include <linux/pci.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/io.h> +#include <linux/async.h> #include <linux/delay.h> #include <linux/slab.h> #include <linux/clk.h> @@ -31,7 +34,7 @@ static unsigned int nr_ports; static struct sh7786_pcie_hwops { int (*core_init)(void); - int (*port_init_hw)(struct sh7786_pcie_port *port); + async_func_ptr *port_init_hw; } *sh7786_pcie_hwops; static struct resource sh7786_pci0_resources[] = { @@ -474,8 +477,9 @@ static int __init sh7786_pcie_core_init(void) return test_mode_pin(MODE_PIN12) ? 3 : 2; } -static int __init sh7786_pcie_init_hw(struct sh7786_pcie_port *port) +static void __init sh7786_pcie_init_hw(void *data, async_cookie_t cookie) { + struct sh7786_pcie_port *port = data; int ret; /* @@ -488,18 +492,30 @@ static int __init sh7786_pcie_init_hw(struct sh7786_pcie_port *port) * Setup clocks, needed both for PHY and PCIe registers. */ ret = pcie_clk_init(port); - if (unlikely(ret < 0)) - return ret; + if (unlikely(ret < 0)) { + pr_err("clock initialization failed for port#%d\n", + port->index); + return; + } ret = phy_init(port); - if (unlikely(ret < 0)) - return ret; + if (unlikely(ret < 0)) { + pr_err("phy initialization failed for port#%d\n", + port->index); + return; + } ret = pcie_init(port); - if (unlikely(ret < 0)) - return ret; + if (unlikely(ret < 0)) { + pr_err("core initialization failed for port#%d\n", + port->index); + return; + } - return register_pci_controller(port->hose); + /* In the interest of preserving device ordering, synchronize */ + async_synchronize_cookie(cookie); + + register_pci_controller(port->hose); } static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = { @@ -510,7 +526,7 @@ static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = { static int __init sh7786_pcie_init(void) { struct clk *platclk; - int ret = 0, i; + int i; printk(KERN_NOTICE "PCI: Starting initialization.\n"); @@ -552,14 +568,10 @@ static int __init sh7786_pcie_init(void) port->hose = sh7786_pci_channels + i; port->hose->io_map_base = port->hose->resources[0].start; - ret |= sh7786_pcie_hwops->port_init_hw(port); + async_schedule(sh7786_pcie_hwops->port_init_hw, port); } - if (unlikely(ret)) { - clk_disable(platclk); - clk_put(platclk); - return ret; - } + async_synchronize_full(); return 0; } diff --git a/arch/sh/include/asm/futex-irq.h b/arch/sh/include/asm/futex-irq.h index a9f16a7f9aea..6cb9f193a95e 100644 --- a/arch/sh/include/asm/futex-irq.h +++ b/arch/sh/include/asm/futex-irq.h @@ -3,7 +3,7 @@ #include <asm/system.h> -static inline int atomic_futex_op_xchg_set(int oparg, int __user *uaddr, +static inline int atomic_futex_op_xchg_set(int oparg, u32 __user *uaddr, int *oldval) { unsigned long flags; @@ -20,7 +20,7 @@ static inline int atomic_futex_op_xchg_set(int oparg, int __user *uaddr, return ret; } -static inline int atomic_futex_op_xchg_add(int oparg, int __user *uaddr, +static inline int atomic_futex_op_xchg_add(int oparg, u32 __user *uaddr, int *oldval) { unsigned long flags; @@ -37,7 +37,7 @@ static inline int atomic_futex_op_xchg_add(int oparg, int __user *uaddr, return ret; } -static inline int atomic_futex_op_xchg_or(int oparg, int __user *uaddr, +static inline int atomic_futex_op_xchg_or(int oparg, u32 __user *uaddr, int *oldval) { unsigned long flags; @@ -54,7 +54,7 @@ static inline int atomic_futex_op_xchg_or(int oparg, int __user *uaddr, return ret; } -static inline int atomic_futex_op_xchg_and(int oparg, int __user *uaddr, +static inline int atomic_futex_op_xchg_and(int oparg, u32 __user *uaddr, int *oldval) { unsigned long flags; @@ -71,7 +71,7 @@ static inline int atomic_futex_op_xchg_and(int oparg, int __user *uaddr, return ret; } -static inline int atomic_futex_op_xchg_xor(int oparg, int __user *uaddr, +static inline int atomic_futex_op_xchg_xor(int oparg, u32 __user *uaddr, int *oldval) { unsigned long flags; @@ -88,11 +88,13 @@ static inline int atomic_futex_op_xchg_xor(int oparg, int __user *uaddr, return ret; } -static inline int atomic_futex_op_cmpxchg_inatomic(int __user *uaddr, - int oldval, int newval) +static inline int atomic_futex_op_cmpxchg_inatomic(u32 *uval, + u32 __user *uaddr, + u32 oldval, u32 newval) { unsigned long flags; - int ret, prev = 0; + int ret; + u32 prev = 0; local_irq_save(flags); @@ -102,10 +104,8 @@ static inline int atomic_futex_op_cmpxchg_inatomic(int __user *uaddr, local_irq_restore(flags); - if (ret) - return ret; - - return prev; + *uval = prev; + return ret; } #endif /* __ASM_SH_FUTEX_IRQ_H */ diff --git a/arch/sh/include/asm/futex.h b/arch/sh/include/asm/futex.h index 68256ec5fa35..7be39a646fbd 100644 --- a/arch/sh/include/asm/futex.h +++ b/arch/sh/include/asm/futex.h @@ -10,7 +10,7 @@ /* XXX: UP variants, fix for SH-4A and SMP.. */ #include <asm/futex-irq.h> -static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr) +static inline int futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr) { int op = (encoded_op >> 28) & 7; int cmp = (encoded_op >> 24) & 15; @@ -21,7 +21,7 @@ static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr) if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) oparg = 1 << oparg; - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; pagefault_disable(); @@ -65,12 +65,13 @@ static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr) } static inline int -futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) +futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) { - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; - return atomic_futex_op_cmpxchg_inatomic(uaddr, oldval, newval); + return atomic_futex_op_cmpxchg_inatomic(uval, uaddr, oldval, newval); } #endif /* __KERNEL__ */ diff --git a/arch/sh/include/asm/ioctls.h b/arch/sh/include/asm/ioctls.h index 84e85a792638..a6769f352bf6 100644 --- a/arch/sh/include/asm/ioctls.h +++ b/arch/sh/include/asm/ioctls.h @@ -87,6 +87,7 @@ #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ #define TIOCGDEV _IOR('T',0x32, unsigned int) /* Get primary device node of /dev/console */ #define TIOCSIG _IOW('T',0x36, int) /* Generate signal on Pty slave */ +#define TIOCVHANGUP _IO('T', 0x37) #define TIOCSERCONFIG _IO('T', 83) /* 0x5453 */ #define TIOCSERGWILD _IOR('T', 84, int) /* 0x5454 */ diff --git a/arch/sh/include/asm/rwsem.h b/arch/sh/include/asm/rwsem.h index 06e2251a5e48..edab57265293 100644 --- a/arch/sh/include/asm/rwsem.h +++ b/arch/sh/include/asm/rwsem.h @@ -11,64 +11,13 @@ #endif #ifdef __KERNEL__ -#include <linux/list.h> -#include <linux/spinlock.h> -#include <asm/atomic.h> -#include <asm/system.h> -/* - * the semaphore definition - */ -struct rw_semaphore { - long count; #define RWSEM_UNLOCKED_VALUE 0x00000000 #define RWSEM_ACTIVE_BIAS 0x00000001 #define RWSEM_ACTIVE_MASK 0x0000ffff #define RWSEM_WAITING_BIAS (-0x00010000) #define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS #define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS) - spinlock_t wait_lock; - struct list_head wait_list; -#ifdef CONFIG_DEBUG_LOCK_ALLOC - struct lockdep_map dep_map; -#endif -}; - -#ifdef CONFIG_DEBUG_LOCK_ALLOC -# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname } -#else -# define __RWSEM_DEP_MAP_INIT(lockname) -#endif - -#define __RWSEM_INITIALIZER(name) \ - { RWSEM_UNLOCKED_VALUE, __SPIN_LOCK_UNLOCKED((name).wait_lock), \ - LIST_HEAD_INIT((name).wait_list) \ - __RWSEM_DEP_MAP_INIT(name) } - -#define DECLARE_RWSEM(name) \ - struct rw_semaphore name = __RWSEM_INITIALIZER(name) - -extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem); -extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem); -extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem); -extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem); - -extern void __init_rwsem(struct rw_semaphore *sem, const char *name, - struct lock_class_key *key); - -#define init_rwsem(sem) \ -do { \ - static struct lock_class_key __key; \ - \ - __init_rwsem((sem), #sem, &__key); \ -} while (0) - -static inline void init_rwsem(struct rw_semaphore *sem) -{ - sem->count = RWSEM_UNLOCKED_VALUE; - spin_lock_init(&sem->wait_lock); - INIT_LIST_HEAD(&sem->wait_list); -} /* * lock for reading @@ -179,10 +128,5 @@ static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem) return atomic_add_return(delta, (atomic_t *)(&sem->count)); } -static inline int rwsem_is_locked(struct rw_semaphore *sem) -{ - return (sem->count != 0); -} - #endif /* __KERNEL__ */ #endif /* _ASM_SH_RWSEM_H */ diff --git a/arch/sh/include/asm/sh_eth.h b/arch/sh/include/asm/sh_eth.h index f739061e2ee4..0f325da0f923 100644 --- a/arch/sh/include/asm/sh_eth.h +++ b/arch/sh/include/asm/sh_eth.h @@ -1,11 +1,21 @@ #ifndef __ASM_SH_ETH_H__ #define __ASM_SH_ETH_H__ +#include <linux/phy.h> + enum {EDMAC_LITTLE_ENDIAN, EDMAC_BIG_ENDIAN}; +enum { + SH_ETH_REG_GIGABIT, + SH_ETH_REG_FAST_SH4, + SH_ETH_REG_FAST_SH3_SH2 +}; struct sh_eth_plat_data { int phy; int edmac_endian; + int register_type; + phy_interface_t phy_interface; + void (*set_mdio_gate)(unsigned long addr); unsigned char mac_addr[6]; unsigned no_ether_link:1; diff --git a/arch/sh/include/asm/unistd_32.h b/arch/sh/include/asm/unistd_32.h index d6741fca89a4..b5a74e88028d 100644 --- a/arch/sh/include/asm/unistd_32.h +++ b/arch/sh/include/asm/unistd_32.h @@ -369,8 +369,11 @@ #define __NR_recvmsg 356 #define __NR_recvmmsg 357 #define __NR_accept4 358 +#define __NR_name_to_handle_at 359 +#define __NR_open_by_handle_at 360 +#define __NR_clock_adjtime 361 -#define NR_syscalls 359 +#define NR_syscalls 362 #ifdef __KERNEL__ diff --git a/arch/sh/include/asm/unistd_64.h b/arch/sh/include/asm/unistd_64.h index 09aa93f9eb70..953da4a52199 100644 --- a/arch/sh/include/asm/unistd_64.h +++ b/arch/sh/include/asm/unistd_64.h @@ -390,10 +390,13 @@ #define __NR_fanotify_init 367 #define __NR_fanotify_mark 368 #define __NR_prlimit64 369 +#define __NR_name_to_handle_at 370 +#define __NR_open_by_handle_at 371 +#define __NR_clock_adjtime 372 #ifdef __KERNEL__ -#define NR_syscalls 370 +#define NR_syscalls 373 #define __ARCH_WANT_IPC_PARSE_VERSION #define __ARCH_WANT_OLD_READDIR diff --git a/arch/sh/include/cpu-sh4/cpu/dma-register.h b/arch/sh/include/cpu-sh4/cpu/dma-register.h index 9a6125eb0079..18fa80aba15e 100644 --- a/arch/sh/include/cpu-sh4/cpu/dma-register.h +++ b/arch/sh/include/cpu-sh4/cpu/dma-register.h @@ -40,6 +40,11 @@ #define CHCR_TS_LOW_SHIFT 3 #define CHCR_TS_HIGH_MASK 0 #define CHCR_TS_HIGH_SHIFT 0 +#elif defined(CONFIG_CPU_SUBTYPE_SH7757) +#define CHCR_TS_LOW_MASK 0x00000018 +#define CHCR_TS_LOW_SHIFT 3 +#define CHCR_TS_HIGH_MASK 0x00100000 +#define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */ #elif defined(CONFIG_CPU_SUBTYPE_SH7780) #define CHCR_TS_LOW_MASK 0x00000018 #define CHCR_TS_LOW_SHIFT 3 diff --git a/arch/sh/include/cpu-sh4/cpu/sh7757.h b/arch/sh/include/cpu-sh4/cpu/sh7757.h index 15f3de11c55a..05b8196c7753 100644 --- a/arch/sh/include/cpu-sh4/cpu/sh7757.h +++ b/arch/sh/include/cpu-sh4/cpu/sh7757.h @@ -251,4 +251,36 @@ enum { GPIO_FN_ON_DQ3, GPIO_FN_ON_DQ2, GPIO_FN_ON_DQ1, GPIO_FN_ON_DQ0, }; +enum { + SHDMA_SLAVE_SDHI_TX, + SHDMA_SLAVE_SDHI_RX, + SHDMA_SLAVE_MMCIF_TX, + SHDMA_SLAVE_MMCIF_RX, + SHDMA_SLAVE_SCIF2_TX, + SHDMA_SLAVE_SCIF2_RX, + SHDMA_SLAVE_SCIF3_TX, + SHDMA_SLAVE_SCIF3_RX, + SHDMA_SLAVE_SCIF4_TX, + SHDMA_SLAVE_SCIF4_RX, + SHDMA_SLAVE_RIIC0_TX, + SHDMA_SLAVE_RIIC0_RX, + SHDMA_SLAVE_RIIC1_TX, + SHDMA_SLAVE_RIIC1_RX, + SHDMA_SLAVE_RIIC2_TX, + SHDMA_SLAVE_RIIC2_RX, + SHDMA_SLAVE_RIIC3_TX, + SHDMA_SLAVE_RIIC3_RX, + SHDMA_SLAVE_RIIC4_TX, + SHDMA_SLAVE_RIIC4_RX, + SHDMA_SLAVE_RIIC5_TX, + SHDMA_SLAVE_RIIC5_RX, + SHDMA_SLAVE_RIIC6_TX, + SHDMA_SLAVE_RIIC6_RX, + SHDMA_SLAVE_RIIC7_TX, + SHDMA_SLAVE_RIIC7_RX, + SHDMA_SLAVE_RIIC8_TX, + SHDMA_SLAVE_RIIC8_RX, + SHDMA_SLAVE_RIIC9_TX, + SHDMA_SLAVE_RIIC9_RX, +}; #endif /* __ASM_SH7757_H__ */ diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c index e073e3eb4c3d..eedddad13835 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c @@ -77,9 +77,10 @@ struct clk div4_clks[DIV4_NR] = { #define MSTPCR0 0xffc80030 #define MSTPCR1 0xffc80034 +#define MSTPCR2 0xffc10028 enum { MSTP004, MSTP000, MSTP114, MSTP113, MSTP112, - MSTP111, MSTP110, MSTP103, MSTP102, + MSTP111, MSTP110, MSTP103, MSTP102, MSTP220, MSTP_NR }; static struct clk mstp_clks[MSTP_NR] = { @@ -95,6 +96,9 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0), [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0), [MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0), + + /* MSTPCR2 */ + [MSTP220] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 20, 0), }; #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } @@ -140,6 +144,7 @@ static struct clk_lookup lookups[] = { .clk = &mstp_clks[MSTP110], }, CLKDEV_CON_ID("usb0", &mstp_clks[MSTP102]), + CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP220]), }; int __init arch_clk_init(void) diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c index 9c1de2633ac3..423dabf542d3 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c @@ -1,7 +1,7 @@ /* * SH7757 Setup * - * Copyright (C) 2009 Renesas Solutions Corp. + * Copyright (C) 2009, 2011 Renesas Solutions Corp. * * based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt * @@ -16,6 +16,10 @@ #include <linux/io.h> #include <linux/mm.h> #include <linux/sh_timer.h> +#include <linux/sh_dma.h> + +#include <cpu/dma-register.h> +#include <cpu/sh7757.h> static struct plat_sci_port scif2_platform_data = { .mapbase = 0xfe4b0000, /* SCIF2 */ @@ -124,12 +128,548 @@ static struct platform_device tmu1_device = { .num_resources = ARRAY_SIZE(tmu1_resources), }; +static struct resource spi0_resources[] = { + [0] = { + .start = 0xfe002000, + .end = 0xfe0020ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 86, + .flags = IORESOURCE_IRQ, + }, +}; + +/* DMA */ +static const struct sh_dmae_slave_config sh7757_dmae0_slaves[] = { + { + .slave_id = SHDMA_SLAVE_SDHI_TX, + .addr = 0x1fe50030, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_16BIT), + .mid_rid = 0xc5, + }, + { + .slave_id = SHDMA_SLAVE_SDHI_RX, + .addr = 0x1fe50030, + .chcr = DM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_16BIT), + .mid_rid = 0xc6, + }, + { + .slave_id = SHDMA_SLAVE_MMCIF_TX, + .addr = 0x1fcb0034, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0xd3, + }, + { + .slave_id = SHDMA_SLAVE_MMCIF_RX, + .addr = 0x1fcb0034, + .chcr = DM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0xd7, + }, +}; + +static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = { + { + .slave_id = SHDMA_SLAVE_SCIF2_TX, + .addr = 0x1f4b000c, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x21, + }, + { + .slave_id = SHDMA_SLAVE_SCIF2_RX, + .addr = 0x1f4b0014, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x22, + }, + { + .slave_id = SHDMA_SLAVE_SCIF3_TX, + .addr = 0x1f4c000c, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x29, + }, + { + .slave_id = SHDMA_SLAVE_SCIF3_RX, + .addr = 0x1f4c0014, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x2a, + }, + { + .slave_id = SHDMA_SLAVE_SCIF4_TX, + .addr = 0x1f4d000c, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x41, + }, + { + .slave_id = SHDMA_SLAVE_SCIF4_RX, + .addr = 0x1f4d0014, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x42, + }, +}; + +static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = { + { + .slave_id = SHDMA_SLAVE_RIIC0_TX, + .addr = 0x1e500012, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x21, + }, + { + .slave_id = SHDMA_SLAVE_RIIC0_RX, + .addr = 0x1e500013, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x22, + }, + { + .slave_id = SHDMA_SLAVE_RIIC1_TX, + .addr = 0x1e510012, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x29, + }, + { + .slave_id = SHDMA_SLAVE_RIIC1_RX, + .addr = 0x1e510013, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x2a, + }, + { + .slave_id = SHDMA_SLAVE_RIIC2_TX, + .addr = 0x1e520012, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0xa1, + }, + { + .slave_id = SHDMA_SLAVE_RIIC2_RX, + .addr = 0x1e520013, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0xa2, + }, + { + .slave_id = SHDMA_SLAVE_RIIC3_TX, + .addr = 0x1e530012, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0xab, + }, + { + .slave_id = SHDMA_SLAVE_RIIC3_RX, + .addr = 0x1e530013, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0xaf, + }, + { + .slave_id = SHDMA_SLAVE_RIIC4_TX, + .addr = 0x1e540012, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0xc1, + }, + { + .slave_id = SHDMA_SLAVE_RIIC4_RX, + .addr = 0x1e540013, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0xc2, + }, +}; + +static const struct sh_dmae_slave_config sh7757_dmae3_slaves[] = { + { + .slave_id = SHDMA_SLAVE_RIIC5_TX, + .addr = 0x1e550012, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x21, + }, + { + .slave_id = SHDMA_SLAVE_RIIC5_RX, + .addr = 0x1e550013, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x22, + }, + { + .slave_id = SHDMA_SLAVE_RIIC6_TX, + .addr = 0x1e560012, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x29, + }, + { + .slave_id = SHDMA_SLAVE_RIIC6_RX, + .addr = 0x1e560013, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x2a, + }, + { + .slave_id = SHDMA_SLAVE_RIIC7_TX, + .addr = 0x1e570012, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x41, + }, + { + .slave_id = SHDMA_SLAVE_RIIC7_RX, + .addr = 0x1e570013, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x42, + }, + { + .slave_id = SHDMA_SLAVE_RIIC8_TX, + .addr = 0x1e580012, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x45, + }, + { + .slave_id = SHDMA_SLAVE_RIIC8_RX, + .addr = 0x1e580013, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x46, + }, + { + .slave_id = SHDMA_SLAVE_RIIC9_TX, + .addr = 0x1e590012, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x51, + }, + { + .slave_id = SHDMA_SLAVE_RIIC9_RX, + .addr = 0x1e590013, + .chcr = SM_INC | 0x800 | 0x40000000 | + TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x52, + }, +}; + +static const struct sh_dmae_channel sh7757_dmae_channels[] = { + { + .offset = 0, + .dmars = 0, + .dmars_bit = 0, + }, { + .offset = 0x10, + .dmars = 0, + .dmars_bit = 8, + }, { + .offset = 0x20, + .dmars = 4, + .dmars_bit = 0, + }, { + .offset = 0x30, + .dmars = 4, + .dmars_bit = 8, + }, { + .offset = 0x50, + .dmars = 8, + .dmars_bit = 0, + }, { + .offset = 0x60, + .dmars = 8, + .dmars_bit = 8, + } +}; + +static const unsigned int ts_shift[] = TS_SHIFT; + +static struct sh_dmae_pdata dma0_platform_data = { + .slave = sh7757_dmae0_slaves, + .slave_num = ARRAY_SIZE(sh7757_dmae0_slaves), + .channel = sh7757_dmae_channels, + .channel_num = ARRAY_SIZE(sh7757_dmae_channels), + .ts_low_shift = CHCR_TS_LOW_SHIFT, + .ts_low_mask = CHCR_TS_LOW_MASK, + .ts_high_shift = CHCR_TS_HIGH_SHIFT, + .ts_high_mask = CHCR_TS_HIGH_MASK, + .ts_shift = ts_shift, + .ts_shift_num = ARRAY_SIZE(ts_shift), + .dmaor_init = DMAOR_INIT, +}; + +static struct sh_dmae_pdata dma1_platform_data = { + .slave = sh7757_dmae1_slaves, + .slave_num = ARRAY_SIZE(sh7757_dmae1_slaves), + .channel = sh7757_dmae_channels, + .channel_num = ARRAY_SIZE(sh7757_dmae_channels), + .ts_low_shift = CHCR_TS_LOW_SHIFT, + .ts_low_mask = CHCR_TS_LOW_MASK, + .ts_high_shift = CHCR_TS_HIGH_SHIFT, + .ts_high_mask = CHCR_TS_HIGH_MASK, + .ts_shift = ts_shift, + .ts_shift_num = ARRAY_SIZE(ts_shift), + .dmaor_init = DMAOR_INIT, +}; + +static struct sh_dmae_pdata dma2_platform_data = { + .slave = sh7757_dmae2_slaves, + .slave_num = ARRAY_SIZE(sh7757_dmae2_slaves), + .channel = sh7757_dmae_channels, + .channel_num = ARRAY_SIZE(sh7757_dmae_channels), + .ts_low_shift = CHCR_TS_LOW_SHIFT, + .ts_low_mask = CHCR_TS_LOW_MASK, + .ts_high_shift = CHCR_TS_HIGH_SHIFT, + .ts_high_mask = CHCR_TS_HIGH_MASK, + .ts_shift = ts_shift, + .ts_shift_num = ARRAY_SIZE(ts_shift), + .dmaor_init = DMAOR_INIT, +}; + +static struct sh_dmae_pdata dma3_platform_data = { + .slave = sh7757_dmae3_slaves, + .slave_num = ARRAY_SIZE(sh7757_dmae3_slaves), + .channel = sh7757_dmae_channels, + .channel_num = ARRAY_SIZE(sh7757_dmae_channels), + .ts_low_shift = CHCR_TS_LOW_SHIFT, + .ts_low_mask = CHCR_TS_LOW_MASK, + .ts_high_shift = CHCR_TS_HIGH_SHIFT, + .ts_high_mask = CHCR_TS_HIGH_MASK, + .ts_shift = ts_shift, + .ts_shift_num = ARRAY_SIZE(ts_shift), + .dmaor_init = DMAOR_INIT, +}; + +/* channel 0 to 5 */ +static struct resource sh7757_dmae0_resources[] = { + [0] = { + /* Channel registers and DMAOR */ + .start = 0xff608020, + .end = 0xff60808f, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* DMARSx */ + .start = 0xff609000, + .end = 0xff60900b, + .flags = IORESOURCE_MEM, + }, + { + .start = 34, + .end = 34, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, +}; + +/* channel 6 to 11 */ +static struct resource sh7757_dmae1_resources[] = { + [0] = { + /* Channel registers and DMAOR */ + .start = 0xff618020, + .end = 0xff61808f, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* DMARSx */ + .start = 0xff619000, + .end = 0xff61900b, + .flags = IORESOURCE_MEM, + }, + { + /* DMA error */ + .start = 34, + .end = 34, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, + { + /* IRQ for channels 4 */ + .start = 46, + .end = 46, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, + { + /* IRQ for channels 5 */ + .start = 46, + .end = 46, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, + { + /* IRQ for channels 6 */ + .start = 88, + .end = 88, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, + { + /* IRQ for channels 7 */ + .start = 88, + .end = 88, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, + { + /* IRQ for channels 8 */ + .start = 88, + .end = 88, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, + { + /* IRQ for channels 9 */ + .start = 88, + .end = 88, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, + { + /* IRQ for channels 10 */ + .start = 88, + .end = 88, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, + { + /* IRQ for channels 11 */ + .start = 88, + .end = 88, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, +}; + +/* channel 12 to 17 */ +static struct resource sh7757_dmae2_resources[] = { + [0] = { + /* Channel registers and DMAOR */ + .start = 0xff708020, + .end = 0xff70808f, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* DMARSx */ + .start = 0xff709000, + .end = 0xff70900b, + .flags = IORESOURCE_MEM, + }, + { + /* DMA error */ + .start = 323, + .end = 323, + .flags = IORESOURCE_IRQ, + }, + { + /* IRQ for channels 12 to 16 */ + .start = 272, + .end = 276, + .flags = IORESOURCE_IRQ, + }, + { + /* IRQ for channel 17 */ + .start = 279, + .end = 279, + .flags = IORESOURCE_IRQ, + }, +}; + +/* channel 18 to 23 */ +static struct resource sh7757_dmae3_resources[] = { + [0] = { + /* Channel registers and DMAOR */ + .start = 0xff718020, + .end = 0xff71808f, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* DMARSx */ + .start = 0xff719000, + .end = 0xff71900b, + .flags = IORESOURCE_MEM, + }, + { + /* DMA error */ + .start = 324, + .end = 324, + .flags = IORESOURCE_IRQ, + }, + { + /* IRQ for channels 18 to 22 */ + .start = 280, + .end = 284, + .flags = IORESOURCE_IRQ, + }, + { + /* IRQ for channel 23 */ + .start = 288, + .end = 288, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dma0_device = { + .name = "sh-dma-engine", + .id = 0, + .resource = sh7757_dmae0_resources, + .num_resources = ARRAY_SIZE(sh7757_dmae0_resources), + .dev = { + .platform_data = &dma0_platform_data, + }, +}; + +static struct platform_device dma1_device = { + .name = "sh-dma-engine", + .id = 1, + .resource = sh7757_dmae1_resources, + .num_resources = ARRAY_SIZE(sh7757_dmae1_resources), + .dev = { + .platform_data = &dma1_platform_data, + }, +}; + +static struct platform_device dma2_device = { + .name = "sh-dma-engine", + .id = 2, + .resource = sh7757_dmae2_resources, + .num_resources = ARRAY_SIZE(sh7757_dmae2_resources), + .dev = { + .platform_data = &dma2_platform_data, + }, +}; + +static struct platform_device dma3_device = { + .name = "sh-dma-engine", + .id = 3, + .resource = sh7757_dmae3_resources, + .num_resources = ARRAY_SIZE(sh7757_dmae3_resources), + .dev = { + .platform_data = &dma3_platform_data, + }, +}; + +static struct platform_device spi0_device = { + .name = "sh_spi", + .id = 0, + .dev = { + .dma_mask = NULL, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(spi0_resources), + .resource = spi0_resources, +}; + static struct platform_device *sh7757_devices[] __initdata = { &scif2_device, &scif3_device, &scif4_device, &tmu0_device, &tmu1_device, + &dma0_device, + &dma1_device, + &dma2_device, + &dma3_device, + &spi0_device, }; static int __init sh7757_devices_setup(void) diff --git a/arch/sh/kernel/cpu/shmobile/cpuidle.c b/arch/sh/kernel/cpu/shmobile/cpuidle.c index c19e2a940e3f..e4469e7233cb 100644 --- a/arch/sh/kernel/cpu/shmobile/cpuidle.c +++ b/arch/sh/kernel/cpu/shmobile/cpuidle.c @@ -75,7 +75,7 @@ void sh_mobile_setup_cpuidle(void) i = CPUIDLE_DRIVER_STATE_START; state = &dev->states[i++]; - snprintf(state->name, CPUIDLE_NAME_LEN, "C0"); + snprintf(state->name, CPUIDLE_NAME_LEN, "C1"); strncpy(state->desc, "SuperH Sleep Mode", CPUIDLE_DESC_LEN); state->exit_latency = 1; state->target_residency = 1 * 2; @@ -88,7 +88,7 @@ void sh_mobile_setup_cpuidle(void) if (sh_mobile_sleep_supported & SUSP_SH_SF) { state = &dev->states[i++]; - snprintf(state->name, CPUIDLE_NAME_LEN, "C1"); + snprintf(state->name, CPUIDLE_NAME_LEN, "C2"); strncpy(state->desc, "SuperH Sleep Mode [SF]", CPUIDLE_DESC_LEN); state->exit_latency = 100; @@ -101,7 +101,7 @@ void sh_mobile_setup_cpuidle(void) if (sh_mobile_sleep_supported & SUSP_SH_STANDBY) { state = &dev->states[i++]; - snprintf(state->name, CPUIDLE_NAME_LEN, "C2"); + snprintf(state->name, CPUIDLE_NAME_LEN, "C3"); strncpy(state->desc, "SuperH Mobile Standby Mode [SF]", CPUIDLE_DESC_LEN); state->exit_latency = 2300; diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c index 68ecbe6c881a..64ea0b165399 100644 --- a/arch/sh/kernel/irq.c +++ b/arch/sh/kernel/irq.c @@ -34,9 +34,9 @@ void ack_bad_irq(unsigned int irq) #if defined(CONFIG_PROC_FS) /* - * /proc/interrupts printing: + * /proc/interrupts printing for arch specific interrupts */ -static int show_other_interrupts(struct seq_file *p, int prec) +int arch_show_interrupts(struct seq_file *p, int prec) { int j; @@ -49,63 +49,6 @@ static int show_other_interrupts(struct seq_file *p, int prec) return 0; } - -int show_interrupts(struct seq_file *p, void *v) -{ - unsigned long flags, any_count = 0; - int i = *(loff_t *)v, j, prec; - struct irqaction *action; - struct irq_desc *desc; - struct irq_data *data; - struct irq_chip *chip; - - if (i > nr_irqs) - return 0; - - for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec) - j *= 10; - - if (i == nr_irqs) - return show_other_interrupts(p, prec); - - if (i == 0) { - seq_printf(p, "%*s", prec + 8, ""); - for_each_online_cpu(j) - seq_printf(p, "CPU%-8d", j); - seq_putc(p, '\n'); - } - - desc = irq_to_desc(i); - if (!desc) - return 0; - - data = irq_get_irq_data(i); - chip = irq_data_get_irq_chip(data); - - raw_spin_lock_irqsave(&desc->lock, flags); - for_each_online_cpu(j) - any_count |= kstat_irqs_cpu(i, j); - action = desc->action; - if (!action && !any_count) - goto out; - - seq_printf(p, "%*d: ", prec, i); - for_each_online_cpu(j) - seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); - seq_printf(p, " %14s", chip->name); - seq_printf(p, "-%-8s", desc->name); - - if (action) { - seq_printf(p, " %s", action->name); - while ((action = action->next) != NULL) - seq_printf(p, ", %s", action->name); - } - - seq_putc(p, '\n'); -out: - raw_spin_unlock_irqrestore(&desc->lock, flags); - return 0; -} #endif #ifdef CONFIG_IRQSTACKS diff --git a/arch/sh/kernel/syscalls_32.S b/arch/sh/kernel/syscalls_32.S index 6fc347ebe59d..768fb33fdd35 100644 --- a/arch/sh/kernel/syscalls_32.S +++ b/arch/sh/kernel/syscalls_32.S @@ -376,3 +376,6 @@ ENTRY(sys_call_table) .long sys_recvmsg .long sys_recvmmsg .long sys_accept4 + .long sys_name_to_handle_at + .long sys_open_by_handle_at /* 360 */ + .long sys_clock_adjtime diff --git a/arch/sh/kernel/syscalls_64.S b/arch/sh/kernel/syscalls_64.S index 66585708ce90..44e7b00c8067 100644 --- a/arch/sh/kernel/syscalls_64.S +++ b/arch/sh/kernel/syscalls_64.S @@ -396,3 +396,6 @@ sys_call_table: .long sys_fanotify_init .long sys_fanotify_mark .long sys_prlimit64 + .long sys_name_to_handle_at /* 370 */ + .long sys_open_by_handle_at + .long sys_clock_adjtime diff --git a/arch/sh/kernel/vmlinux.lds.S b/arch/sh/kernel/vmlinux.lds.S index 7f8a709c3ada..af4d46187a79 100644 --- a/arch/sh/kernel/vmlinux.lds.S +++ b/arch/sh/kernel/vmlinux.lds.S @@ -66,7 +66,7 @@ SECTIONS __machvec_end = .; } - PERCPU(PAGE_SIZE) + PERCPU(L1_CACHE_BYTES, PAGE_SIZE) /* * .exit.text is discarded at runtime, not link time, to deal with diff --git a/arch/sh/mm/Makefile b/arch/sh/mm/Makefile index 150aa326afff..2228c8cee4d6 100644 --- a/arch/sh/mm/Makefile +++ b/arch/sh/mm/Makefile @@ -42,6 +42,8 @@ obj-$(CONFIG_IOREMAP_FIXED) += ioremap_fixed.o obj-$(CONFIG_UNCACHED_MAPPING) += uncached.o obj-$(CONFIG_HAVE_SRAM_POOL) += sram.o +GCOV_PROFILE_pmb.o := n + # Special flags for fault_64.o. This puts restrictions on the number of # caller-save registers that the compiler can target when building this file. # This is required because the code is called from a context in entry.S where diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index 95695e97703e..e48f471be547 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -51,6 +51,7 @@ config SPARC64 select HAVE_PERF_EVENTS select PERF_USE_VMALLOC select HAVE_GENERIC_HARDIRQS + select GENERIC_HARDIRQS_NO_DEPRECATED config ARCH_DEFCONFIG string @@ -460,6 +461,39 @@ config SPARC_LEON from www.gaisler.com. You can download a sparc-linux cross-compilation toolchain at www.gaisler.com. +if SPARC_LEON +menu "U-Boot options" + +config UBOOT_LOAD_ADDR + hex "uImage Load Address" + default 0x40004000 + ---help--- + U-Boot kernel load address, the address in physical address space + where u-boot will place the Linux kernel before booting it. + This address is normally the base address of main memory + 0x4000. + +config UBOOT_FLASH_ADDR + hex "uImage.o Load Address" + default 0x00080000 + ---help--- + Optional setting only affecting the uImage.o ELF-image used to + download the uImage file to the target using a ELF-loader other than + U-Boot. It may for example be used to download an uImage to FLASH with + the GRMON utility before even starting u-boot. + +config UBOOT_ENTRY_ADDR + hex "uImage Entry Address" + default 0xf0004000 + ---help--- + Do not change this unless you know what you're doing. This is + hardcoded by the SPARC32 and LEON port. + + This is the virtual address u-boot jumps to when booting the Linux + Kernel. + +endmenu +endif + endmenu menu "Bus options (PCI etc.)" diff --git a/arch/sparc/Makefile b/arch/sparc/Makefile index 113225b241e0..ad1fb5d969f3 100644 --- a/arch/sparc/Makefile +++ b/arch/sparc/Makefile @@ -88,7 +88,7 @@ boot := arch/sparc/boot # Default target all: zImage -image zImage tftpboot.img vmlinux.aout: vmlinux +image zImage uImage tftpboot.img vmlinux.aout: vmlinux $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ archclean: @@ -102,6 +102,7 @@ ifeq ($(ARCH),sparc) define archhelp echo '* image - kernel image ($(boot)/image)' echo '* zImage - stripped kernel image ($(boot)/zImage)' + echo ' uImage - U-Boot SPARC32 Image (only for LEON)' echo ' tftpboot.img - image prepared for tftp' endef else diff --git a/arch/sparc/boot/Makefile b/arch/sparc/boot/Makefile index a2c5898c1ab1..9205416b1e67 100644 --- a/arch/sparc/boot/Makefile +++ b/arch/sparc/boot/Makefile @@ -5,6 +5,7 @@ ROOT_IMG := /usr/src/root.img ELFTOAOUT := elftoaout +MKIMAGE := $(srctree)/scripts/mkuboot.sh hostprogs-y := piggyback btfixupprep targets := tftpboot.img btfix.o btfix.S image zImage vmlinux.aout @@ -77,6 +78,36 @@ $(obj)/zImage: $(obj)/image $(obj)/vmlinux.aout: vmlinux FORCE $(call if_changed,elftoaout) @echo ' kernel: $@ is ready' +else + +# The following lines make a readable image for U-Boot. +# uImage - Binary file read by U-boot +# uImage.o - object file of uImage for loading with a +# flash programmer understanding ELF. + +OBJCOPYFLAGS_image.bin := -S -O binary -R .note -R .comment +$(obj)/image.bin: $(obj)/image FORCE + $(call if_changed,objcopy) + +$(obj)/image.gz: $(obj)/image.bin + $(call if_changed,gzip) + +quiet_cmd_uimage = UIMAGE $@ + cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A sparc -O linux -T kernel \ + -C gzip -a $(CONFIG_UBOOT_LOAD_ADDR) \ + -e $(CONFIG_UBOOT_ENTRY_ADDR) -n 'Linux-$(KERNELRELEASE)' \ + -d $< $@ + +quiet_cmd_uimage.o = UIMAGE.O $@ + cmd_uimage.o = $(LD) -Tdata $(CONFIG_UBOOT_FLASH_ADDR) \ + -r -b binary $@ -o $@.o + +targets += uImage +$(obj)/uImage: $(obj)/image.gz + $(call if_changed,uimage) + $(call if_changed,uimage.o) + @echo ' Image $@ is ready' + endif $(obj)/tftpboot.img: $(obj)/image $(obj)/piggyback System.map $(ROOT_IMG) FORCE diff --git a/arch/sparc/include/asm/fcntl.h b/arch/sparc/include/asm/fcntl.h index 38f37b333cc7..d0b83f66f356 100644 --- a/arch/sparc/include/asm/fcntl.h +++ b/arch/sparc/include/asm/fcntl.h @@ -34,6 +34,8 @@ #define __O_SYNC 0x800000 #define O_SYNC (__O_SYNC|O_DSYNC) +#define O_PATH 0x1000000 + #define F_GETOWN 5 /* for sockets. */ #define F_SETOWN 6 /* for sockets. */ #define F_GETLK 7 diff --git a/arch/sparc/include/asm/futex_64.h b/arch/sparc/include/asm/futex_64.h index 47f95839dc69..444e7bea23bc 100644 --- a/arch/sparc/include/asm/futex_64.h +++ b/arch/sparc/include/asm/futex_64.h @@ -30,7 +30,7 @@ : "r" (uaddr), "r" (oparg), "i" (-EFAULT) \ : "memory") -static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr) +static inline int futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr) { int op = (encoded_op >> 28) & 7; int cmp = (encoded_op >> 24) & 15; @@ -38,7 +38,7 @@ static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr) int cmparg = (encoded_op << 20) >> 20; int oldval = 0, ret, tem; - if (unlikely(!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))) + if (unlikely(!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))) return -EFAULT; if (unlikely((((unsigned long) uaddr) & 0x3UL))) return -EINVAL; @@ -85,26 +85,30 @@ static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr) } static inline int -futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) +futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) { + int ret = 0; + __asm__ __volatile__( - "\n1: casa [%3] %%asi, %2, %0\n" + "\n1: casa [%4] %%asi, %3, %1\n" "2:\n" " .section .fixup,#alloc,#execinstr\n" " .align 4\n" "3: sethi %%hi(2b), %0\n" " jmpl %0 + %%lo(2b), %%g0\n" - " mov %4, %0\n" + " mov %5, %0\n" " .previous\n" " .section __ex_table,\"a\"\n" " .align 4\n" " .word 1b, 3b\n" " .previous\n" - : "=r" (newval) - : "0" (newval), "r" (oldval), "r" (uaddr), "i" (-EFAULT) + : "+r" (ret), "=r" (newval) + : "1" (newval), "r" (oldval), "r" (uaddr), "i" (-EFAULT) : "memory"); - return newval; + *uval = newval; + return ret; } #endif /* !(_SPARC64_FUTEX_H) */ diff --git a/arch/sparc/include/asm/ioctls.h b/arch/sparc/include/asm/ioctls.h index ed3807b96bb5..28d0c8b02cc3 100644 --- a/arch/sparc/include/asm/ioctls.h +++ b/arch/sparc/include/asm/ioctls.h @@ -20,6 +20,7 @@ #define TCSETSW2 _IOW('T', 14, struct termios2) #define TCSETSF2 _IOW('T', 15, struct termios2) #define TIOCGDEV _IOR('T',0x32, unsigned int) /* Get primary device node of /dev/console */ +#define TIOCVHANGUP _IO('T', 0x37) /* Note that all the ioctls that are not available in Linux have a * double underscore on the front to: a) avoid some programs to diff --git a/arch/sparc/include/asm/irq_64.h b/arch/sparc/include/asm/irq_64.h index a0b443cb3c1f..4f09666f0798 100644 --- a/arch/sparc/include/asm/irq_64.h +++ b/arch/sparc/include/asm/irq_64.h @@ -33,34 +33,34 @@ /* The largest number of unique interrupt sources we support. * If this needs to ever be larger than 255, you need to change - * the type of ino_bucket->virt_irq as appropriate. + * the type of ino_bucket->irq as appropriate. * - * ino_bucket->virt_irq allocation is made during {sun4v_,}build_irq(). + * ino_bucket->irq allocation is made during {sun4v_,}build_irq(). */ #define NR_IRQS 255 -extern void irq_install_pre_handler(int virt_irq, +extern void irq_install_pre_handler(int irq, void (*func)(unsigned int, void *, void *), void *arg1, void *arg2); #define irq_canonicalize(irq) (irq) extern unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap); extern unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino); extern unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino); -extern unsigned int sun4v_build_msi(u32 devhandle, unsigned int *virt_irq_p, +extern unsigned int sun4v_build_msi(u32 devhandle, unsigned int *irq_p, unsigned int msi_devino_start, unsigned int msi_devino_end); -extern void sun4v_destroy_msi(unsigned int virt_irq); -extern unsigned int sun4u_build_msi(u32 portid, unsigned int *virt_irq_p, +extern void sun4v_destroy_msi(unsigned int irq); +extern unsigned int sun4u_build_msi(u32 portid, unsigned int *irq_p, unsigned int msi_devino_start, unsigned int msi_devino_end, unsigned long imap_base, unsigned long iclr_base); -extern void sun4u_destroy_msi(unsigned int virt_irq); +extern void sun4u_destroy_msi(unsigned int irq); -extern unsigned char virt_irq_alloc(unsigned int dev_handle, +extern unsigned char irq_alloc(unsigned int dev_handle, unsigned int dev_ino); #ifdef CONFIG_PCI_MSI -extern void virt_irq_free(unsigned int virt_irq); +extern void irq_free(unsigned int irq); #endif extern void __init init_IRQ(void); diff --git a/arch/sparc/include/asm/leon.h b/arch/sparc/include/asm/leon.h index 8580d1764f90..c04f96fb753c 100644 --- a/arch/sparc/include/asm/leon.h +++ b/arch/sparc/include/asm/leon.h @@ -375,9 +375,6 @@ void leon_enable_irq_cpu(unsigned int irq_nr, unsigned int cpu); extern unsigned int real_irq_entry[], smpleon_ticker[]; extern unsigned int patchme_maybe_smp_msg[]; -extern unsigned long trapbase_cpu1[]; -extern unsigned long trapbase_cpu2[]; -extern unsigned long trapbase_cpu3[]; extern unsigned int t_nmi[], linux_trap_ipi15_leon[]; extern unsigned int linux_trap_ipi15_sun4m[]; diff --git a/arch/sparc/include/asm/leon_amba.h b/arch/sparc/include/asm/leon_amba.h index 263c719e96f5..e50f326e71bd 100644 --- a/arch/sparc/include/asm/leon_amba.h +++ b/arch/sparc/include/asm/leon_amba.h @@ -180,6 +180,7 @@ struct amba_ahb_device { struct device_node; void _amba_init(struct device_node *dp, struct device_node ***nextp); +extern unsigned long amba_system_id; extern struct leon3_irqctrl_regs_map *leon3_irqctrl_regs; extern struct leon3_gptimer_regs_map *leon3_gptimer_regs; extern struct amba_apb_device leon_percpu_timer_dev[16]; @@ -254,6 +255,11 @@ extern unsigned int sparc_leon_eirq; #define GAISLER_L2C 0xffe /* internal device: leon2compat */ #define GAISLER_PLUGPLAY 0xfff /* internal device: plug & play configarea */ +/* Chip IDs */ +#define AEROFLEX_UT699 0x0699 +#define LEON4_NEXTREME1 0x0102 +#define GAISLER_GR712RC 0x0712 + #define amba_vendor(x) (((x) >> 24) & 0xff) #define amba_device(x) (((x) >> 12) & 0xfff) diff --git a/arch/sparc/include/asm/mmu_32.h b/arch/sparc/include/asm/mmu_32.h index ccd36d26615a..6f056e535cf8 100644 --- a/arch/sparc/include/asm/mmu_32.h +++ b/arch/sparc/include/asm/mmu_32.h @@ -4,4 +4,7 @@ /* Default "unsigned long" context */ typedef unsigned long mm_context_t; +/* mm/srmmu.c */ +extern ctxd_t *srmmu_ctx_table_phys; + #endif diff --git a/arch/sparc/include/asm/parport.h b/arch/sparc/include/asm/parport.h index aa4c82648d88..cb33608cc68f 100644 --- a/arch/sparc/include/asm/parport.h +++ b/arch/sparc/include/asm/parport.h @@ -103,7 +103,7 @@ static inline unsigned int get_dma_residue(unsigned int dmanr) return ebus_dma_residue(&sparc_ebus_dmas[dmanr].info); } -static int __devinit ecpp_probe(struct platform_device *op, const struct of_device_id *match) +static int __devinit ecpp_probe(struct platform_device *op) { unsigned long base = op->resource[0].start; unsigned long config = op->resource[1].start; @@ -235,7 +235,7 @@ static const struct of_device_id ecpp_match[] = { {}, }; -static struct of_platform_driver ecpp_driver = { +static struct platform_driver ecpp_driver = { .driver = { .name = "ecpp", .owner = THIS_MODULE, @@ -247,7 +247,7 @@ static struct of_platform_driver ecpp_driver = { static int parport_pc_find_nonpci_ports(int autoirq, int autodma) { - return of_register_platform_driver(&ecpp_driver); + return platform_driver_register(&ecpp_driver); } #endif /* !(_ASM_SPARC64_PARPORT_H */ diff --git a/arch/sparc/include/asm/rwsem.h b/arch/sparc/include/asm/rwsem.h index a2b4302869bc..069bf4d663a1 100644 --- a/arch/sparc/include/asm/rwsem.h +++ b/arch/sparc/include/asm/rwsem.h @@ -13,53 +13,12 @@ #ifdef __KERNEL__ -#include <linux/list.h> -#include <linux/spinlock.h> - -struct rwsem_waiter; - -struct rw_semaphore { - signed long count; #define RWSEM_UNLOCKED_VALUE 0x00000000L #define RWSEM_ACTIVE_BIAS 0x00000001L #define RWSEM_ACTIVE_MASK 0xffffffffL #define RWSEM_WAITING_BIAS (-RWSEM_ACTIVE_MASK-1) #define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS #define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS) - spinlock_t wait_lock; - struct list_head wait_list; -#ifdef CONFIG_DEBUG_LOCK_ALLOC - struct lockdep_map dep_map; -#endif -}; - -#ifdef CONFIG_DEBUG_LOCK_ALLOC -# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname } -#else -# define __RWSEM_DEP_MAP_INIT(lockname) -#endif - -#define __RWSEM_INITIALIZER(name) \ -{ RWSEM_UNLOCKED_VALUE, __SPIN_LOCK_UNLOCKED((name).wait_lock), \ - LIST_HEAD_INIT((name).wait_list) __RWSEM_DEP_MAP_INIT(name) } - -#define DECLARE_RWSEM(name) \ - struct rw_semaphore name = __RWSEM_INITIALIZER(name) - -extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem); -extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem); -extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem); -extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem); - -extern void __init_rwsem(struct rw_semaphore *sem, const char *name, - struct lock_class_key *key); - -#define init_rwsem(sem) \ -do { \ - static struct lock_class_key __key; \ - \ - __init_rwsem((sem), #sem, &__key); \ -} while (0) /* * lock for reading @@ -160,11 +119,6 @@ static inline long rwsem_atomic_update(long delta, struct rw_semaphore *sem) return atomic64_add_return(delta, (atomic64_t *)(&sem->count)); } -static inline int rwsem_is_locked(struct rw_semaphore *sem) -{ - return (sem->count != 0); -} - #endif /* __KERNEL__ */ #endif /* _SPARC64_RWSEM_H */ diff --git a/arch/sparc/include/asm/smp_32.h b/arch/sparc/include/asm/smp_32.h index 841905c10215..d82d7f4c0a79 100644 --- a/arch/sparc/include/asm/smp_32.h +++ b/arch/sparc/include/asm/smp_32.h @@ -29,10 +29,16 @@ */ extern unsigned char boot_cpu_id; +extern volatile unsigned long cpu_callin_map[NR_CPUS]; +extern cpumask_t smp_commenced_mask; +extern struct linux_prom_registers smp_penguin_ctable; typedef void (*smpfunc_t)(unsigned long, unsigned long, unsigned long, unsigned long, unsigned long); +void cpu_panic(void); +extern void smp4m_irq_rotate(int cpu); + /* * General functions that each host system must provide. */ diff --git a/arch/sparc/kernel/Makefile b/arch/sparc/kernel/Makefile index 599398fbbc7c..99aa4db6e9c2 100644 --- a/arch/sparc/kernel/Makefile +++ b/arch/sparc/kernel/Makefile @@ -42,7 +42,6 @@ obj-$(CONFIG_SPARC32) += windows.o obj-y += cpu.o obj-$(CONFIG_SPARC32) += devices.o obj-$(CONFIG_SPARC32) += tadpole.o -obj-$(CONFIG_SPARC32) += tick14.o obj-y += ptrace_$(BITS).o obj-y += unaligned_$(BITS).o obj-y += una_asm_$(BITS).o @@ -54,6 +53,7 @@ obj-y += of_device_$(BITS).o obj-$(CONFIG_SPARC64) += prom_irqtrans.o obj-$(CONFIG_SPARC_LEON)+= leon_kernel.o +obj-$(CONFIG_SPARC_LEON)+= leon_pmc.o obj-$(CONFIG_SPARC64) += reboot.o obj-$(CONFIG_SPARC64) += sysfs.o diff --git a/arch/sparc/kernel/apc.c b/arch/sparc/kernel/apc.c index 52de4a9424e8..f679c57644d5 100644 --- a/arch/sparc/kernel/apc.c +++ b/arch/sparc/kernel/apc.c @@ -137,8 +137,7 @@ static const struct file_operations apc_fops = { static struct miscdevice apc_miscdev = { APC_MINOR, APC_DEVNAME, &apc_fops }; -static int __devinit apc_probe(struct platform_device *op, - const struct of_device_id *match) +static int __devinit apc_probe(struct platform_device *op) { int err; @@ -174,7 +173,7 @@ static struct of_device_id __initdata apc_match[] = { }; MODULE_DEVICE_TABLE(of, apc_match); -static struct of_platform_driver apc_driver = { +static struct platform_driver apc_driver = { .driver = { .name = "apc", .owner = THIS_MODULE, @@ -185,7 +184,7 @@ static struct of_platform_driver apc_driver = { static int __init apc_init(void) { - return of_register_platform_driver(&apc_driver); + return platform_driver_register(&apc_driver); } /* This driver is not critical to the boot process diff --git a/arch/sparc/kernel/auxio_64.c b/arch/sparc/kernel/auxio_64.c index 3efd3c5af6a9..2abace076c7d 100644 --- a/arch/sparc/kernel/auxio_64.c +++ b/arch/sparc/kernel/auxio_64.c @@ -102,8 +102,7 @@ static struct of_device_id __initdata auxio_match[] = { MODULE_DEVICE_TABLE(of, auxio_match); -static int __devinit auxio_probe(struct platform_device *dev, - const struct of_device_id *match) +static int __devinit auxio_probe(struct platform_device *dev) { struct device_node *dp = dev->dev.of_node; unsigned long size; @@ -132,7 +131,7 @@ static int __devinit auxio_probe(struct platform_device *dev, return 0; } -static struct of_platform_driver auxio_driver = { +static struct platform_driver auxio_driver = { .probe = auxio_probe, .driver = { .name = "auxio", @@ -143,7 +142,7 @@ static struct of_platform_driver auxio_driver = { static int __init auxio_init(void) { - return of_register_platform_driver(&auxio_driver); + return platform_driver_register(&auxio_driver); } /* Must be after subsys_initcall() so that busses are probed. Must diff --git a/arch/sparc/kernel/central.c b/arch/sparc/kernel/central.c index cfa2624c5332..136d3718a74a 100644 --- a/arch/sparc/kernel/central.c +++ b/arch/sparc/kernel/central.c @@ -59,8 +59,7 @@ static int __devinit clock_board_calc_nslots(struct clock_board *p) } } -static int __devinit clock_board_probe(struct platform_device *op, - const struct of_device_id *match) +static int __devinit clock_board_probe(struct platform_device *op) { struct clock_board *p = kzalloc(sizeof(*p), GFP_KERNEL); int err = -ENOMEM; @@ -148,7 +147,7 @@ static struct of_device_id __initdata clock_board_match[] = { {}, }; -static struct of_platform_driver clock_board_driver = { +static struct platform_driver clock_board_driver = { .probe = clock_board_probe, .driver = { .name = "clock_board", @@ -157,8 +156,7 @@ static struct of_platform_driver clock_board_driver = { }, }; -static int __devinit fhc_probe(struct platform_device *op, - const struct of_device_id *match) +static int __devinit fhc_probe(struct platform_device *op) { struct fhc *p = kzalloc(sizeof(*p), GFP_KERNEL); int err = -ENOMEM; @@ -254,7 +252,7 @@ static struct of_device_id __initdata fhc_match[] = { {}, }; -static struct of_platform_driver fhc_driver = { +static struct platform_driver fhc_driver = { .probe = fhc_probe, .driver = { .name = "fhc", @@ -265,8 +263,8 @@ static struct of_platform_driver fhc_driver = { static int __init sunfire_init(void) { - (void) of_register_platform_driver(&fhc_driver); - (void) of_register_platform_driver(&clock_board_driver); + (void) platform_driver_register(&fhc_driver); + (void) platform_driver_register(&clock_board_driver); return 0; } diff --git a/arch/sparc/kernel/chmc.c b/arch/sparc/kernel/chmc.c index 08c466ebb32b..668c7be5d365 100644 --- a/arch/sparc/kernel/chmc.c +++ b/arch/sparc/kernel/chmc.c @@ -392,8 +392,7 @@ static void __devinit jbusmc_construct_dimm_groups(struct jbusmc *p, } } -static int __devinit jbusmc_probe(struct platform_device *op, - const struct of_device_id *match) +static int __devinit jbusmc_probe(struct platform_device *op) { const struct linux_prom64_registers *mem_regs; struct device_node *mem_node; @@ -690,8 +689,7 @@ static void chmc_fetch_decode_regs(struct chmc *p) chmc_read_mcreg(p, CHMCTRL_DECODE4)); } -static int __devinit chmc_probe(struct platform_device *op, - const struct of_device_id *match) +static int __devinit chmc_probe(struct platform_device *op) { struct device_node *dp = op->dev.of_node; unsigned long ver; @@ -765,13 +763,12 @@ out_free: goto out; } -static int __devinit us3mc_probe(struct platform_device *op, - const struct of_device_id *match) +static int __devinit us3mc_probe(struct platform_device *op) { if (mc_type == MC_TYPE_SAFARI) - return chmc_probe(op, match); + return chmc_probe(op); else if (mc_type == MC_TYPE_JBUS) - return jbusmc_probe(op, match); + return jbusmc_probe(op); return -ENODEV; } @@ -810,7 +807,7 @@ static const struct of_device_id us3mc_match[] = { }; MODULE_DEVICE_TABLE(of, us3mc_match); -static struct of_platform_driver us3mc_driver = { +static struct platform_driver us3mc_driver = { .driver = { .name = "us3mc", .owner = THIS_MODULE, @@ -848,7 +845,7 @@ static int __init us3mc_init(void) ret = register_dimm_printer(us3mc_dimm_printer); if (!ret) { - ret = of_register_platform_driver(&us3mc_driver); + ret = platform_driver_register(&us3mc_driver); if (ret) unregister_dimm_printer(us3mc_dimm_printer); } @@ -859,7 +856,7 @@ static void __exit us3mc_cleanup(void) { if (us3mc_platform()) { unregister_dimm_printer(us3mc_dimm_printer); - of_unregister_platform_driver(&us3mc_driver); + platform_driver_unregister(&us3mc_driver); } } diff --git a/arch/sparc/kernel/cpu.c b/arch/sparc/kernel/cpu.c index 0dc714fa23d8..7925c54f4133 100644 --- a/arch/sparc/kernel/cpu.c +++ b/arch/sparc/kernel/cpu.c @@ -324,7 +324,7 @@ void __cpuinit cpu_probe(void) psr = get_psr(); put_psr(psr | PSR_EF); #ifdef CONFIG_SPARC_LEON - fpu_vers = 7; + fpu_vers = get_psr() & PSR_EF ? ((get_fsr() >> 17) & 0x7) : 7; #else fpu_vers = ((get_fsr() >> 17) & 0x7); #endif diff --git a/arch/sparc/kernel/entry.h b/arch/sparc/kernel/entry.h index c011b932bb17..d1f1361c4167 100644 --- a/arch/sparc/kernel/entry.h +++ b/arch/sparc/kernel/entry.h @@ -213,8 +213,8 @@ extern struct cheetah_err_info *cheetah_error_log; struct ino_bucket { /*0x00*/unsigned long __irq_chain_pa; - /* Virtual interrupt number assigned to this INO. */ -/*0x08*/unsigned int __virt_irq; + /* Interrupt number assigned to this INO. */ +/*0x08*/unsigned int __irq; /*0x0c*/unsigned int __pad; }; diff --git a/arch/sparc/kernel/iommu.c b/arch/sparc/kernel/iommu.c index 72509d0e34be..6f01e8c83197 100644 --- a/arch/sparc/kernel/iommu.c +++ b/arch/sparc/kernel/iommu.c @@ -333,13 +333,10 @@ static void dma_4u_free_coherent(struct device *dev, size_t size, void *cpu, dma_addr_t dvma) { struct iommu *iommu; - iopte_t *iopte; unsigned long flags, order, npages; npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT; iommu = dev->archdata.iommu; - iopte = iommu->page_table + - ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT); spin_lock_irqsave(&iommu->lock, flags); diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c index 41f7e4e0f72a..c6ce9a6a4790 100644 --- a/arch/sparc/kernel/ioport.c +++ b/arch/sparc/kernel/ioport.c @@ -50,10 +50,14 @@ #include <asm/io-unit.h> #include <asm/leon.h> -#ifdef CONFIG_SPARC_LEON -#define mmu_inval_dma_area(p, l) leon_flush_dcache_all() -#else +#ifndef CONFIG_SPARC_LEON #define mmu_inval_dma_area(p, l) /* Anton pulled it out for 2.4.0-xx */ +#else +static inline void mmu_inval_dma_area(void *va, unsigned long len) +{ + if (!sparc_leon3_snooping_enabled()) + leon_flush_dcache_all(); +} #endif static struct resource *_sparc_find_resource(struct resource *r, @@ -254,7 +258,7 @@ static void *sbus_alloc_coherent(struct device *dev, size_t len, dma_addr_t *dma_addrp, gfp_t gfp) { struct platform_device *op = to_platform_device(dev); - unsigned long len_total = (len + PAGE_SIZE-1) & PAGE_MASK; + unsigned long len_total = PAGE_ALIGN(len); unsigned long va; struct resource *res; int order; @@ -280,7 +284,8 @@ static void *sbus_alloc_coherent(struct device *dev, size_t len, printk("sbus_alloc_consistent: cannot occupy 0x%lx", len_total); goto err_nova; } - mmu_inval_dma_area(va, len_total); + mmu_inval_dma_area((void *)va, len_total); + // XXX The mmu_map_dma_area does this for us below, see comments. // sparc_mapiorange(0, virt_to_phys(va), res->start, len_total); /* @@ -297,9 +302,9 @@ static void *sbus_alloc_coherent(struct device *dev, size_t len, err_noiommu: release_resource(res); err_nova: - free_pages(va, order); -err_nomem: kfree(res); +err_nomem: + free_pages(va, order); err_nopages: return NULL; } @@ -321,7 +326,7 @@ static void sbus_free_coherent(struct device *dev, size_t n, void *p, return; } - n = (n + PAGE_SIZE-1) & PAGE_MASK; + n = PAGE_ALIGN(n); if ((res->end-res->start)+1 != n) { printk("sbus_free_consistent: region 0x%lx asked 0x%zx\n", (long)((res->end-res->start)+1), n); @@ -408,9 +413,6 @@ struct dma_map_ops sbus_dma_ops = { .sync_sg_for_device = sbus_sync_sg_for_device, }; -struct dma_map_ops *dma_ops = &sbus_dma_ops; -EXPORT_SYMBOL(dma_ops); - static int __init sparc_register_ioport(void) { register_proc_sparc_ioport(); @@ -422,7 +424,9 @@ arch_initcall(sparc_register_ioport); #endif /* CONFIG_SBUS */ -#ifdef CONFIG_PCI + +/* LEON reuses PCI DMA ops */ +#if defined(CONFIG_PCI) || defined(CONFIG_SPARC_LEON) /* Allocate and map kernel buffer using consistent mode DMA for a device. * hwdev should be valid struct pci_dev pointer for PCI devices. @@ -430,8 +434,8 @@ arch_initcall(sparc_register_ioport); static void *pci32_alloc_coherent(struct device *dev, size_t len, dma_addr_t *pba, gfp_t gfp) { - unsigned long len_total = (len + PAGE_SIZE-1) & PAGE_MASK; - unsigned long va; + unsigned long len_total = PAGE_ALIGN(len); + void *va; struct resource *res; int order; @@ -443,34 +447,34 @@ static void *pci32_alloc_coherent(struct device *dev, size_t len, } order = get_order(len_total); - va = __get_free_pages(GFP_KERNEL, order); - if (va == 0) { + va = (void *) __get_free_pages(GFP_KERNEL, order); + if (va == NULL) { printk("pci_alloc_consistent: no %ld pages\n", len_total>>PAGE_SHIFT); - return NULL; + goto err_nopages; } if ((res = kzalloc(sizeof(struct resource), GFP_KERNEL)) == NULL) { - free_pages(va, order); printk("pci_alloc_consistent: no core\n"); - return NULL; + goto err_nomem; } if (allocate_resource(&_sparc_dvma, res, len_total, _sparc_dvma.start, _sparc_dvma.end, PAGE_SIZE, NULL, NULL) != 0) { printk("pci_alloc_consistent: cannot occupy 0x%lx", len_total); - free_pages(va, order); - kfree(res); - return NULL; + goto err_nova; } mmu_inval_dma_area(va, len_total); -#if 0 -/* P3 */ printk("pci_alloc_consistent: kva %lx uncva %lx phys %lx size %lx\n", - (long)va, (long)res->start, (long)virt_to_phys(va), len_total); -#endif sparc_mapiorange(0, virt_to_phys(va), res->start, len_total); *pba = virt_to_phys(va); /* equals virt_to_bus (R.I.P.) for us. */ return (void *) res->start; + +err_nova: + kfree(res); +err_nomem: + free_pages((unsigned long)va, order); +err_nopages: + return NULL; } /* Free and unmap a consistent DMA buffer. @@ -485,7 +489,7 @@ static void pci32_free_coherent(struct device *dev, size_t n, void *p, dma_addr_t ba) { struct resource *res; - unsigned long pgp; + void *pgp; if ((res = _sparc_find_resource(&_sparc_dvma, (unsigned long)p)) == NULL) { @@ -498,21 +502,21 @@ static void pci32_free_coherent(struct device *dev, size_t n, void *p, return; } - n = (n + PAGE_SIZE-1) & PAGE_MASK; + n = PAGE_ALIGN(n); if ((res->end-res->start)+1 != n) { printk("pci_free_consistent: region 0x%lx asked 0x%lx\n", (long)((res->end-res->start)+1), (long)n); return; } - pgp = (unsigned long) phys_to_virt(ba); /* bus_to_virt actually */ + pgp = phys_to_virt(ba); /* bus_to_virt actually */ mmu_inval_dma_area(pgp, n); sparc_unmapiorange((unsigned long)p, n); release_resource(res); kfree(res); - free_pages(pgp, get_order(n)); + free_pages((unsigned long)pgp, get_order(n)); } /* @@ -527,6 +531,13 @@ static dma_addr_t pci32_map_page(struct device *dev, struct page *page, return page_to_phys(page) + offset; } +static void pci32_unmap_page(struct device *dev, dma_addr_t ba, size_t size, + enum dma_data_direction dir, struct dma_attrs *attrs) +{ + if (dir != PCI_DMA_TODEVICE) + mmu_inval_dma_area(phys_to_virt(ba), PAGE_ALIGN(size)); +} + /* Map a set of buffers described by scatterlist in streaming * mode for DMA. This is the scather-gather version of the * above pci_map_single interface. Here the scatter gather list @@ -572,9 +583,8 @@ static void pci32_unmap_sg(struct device *dev, struct scatterlist *sgl, if (dir != PCI_DMA_TODEVICE) { for_each_sg(sgl, sg, nents, n) { BUG_ON(page_address(sg_page(sg)) == NULL); - mmu_inval_dma_area( - (unsigned long) page_address(sg_page(sg)), - (sg->length + PAGE_SIZE-1) & PAGE_MASK); + mmu_inval_dma_area(page_address(sg_page(sg)), + PAGE_ALIGN(sg->length)); } } } @@ -593,8 +603,8 @@ static void pci32_sync_single_for_cpu(struct device *dev, dma_addr_t ba, size_t size, enum dma_data_direction dir) { if (dir != PCI_DMA_TODEVICE) { - mmu_inval_dma_area((unsigned long)phys_to_virt(ba), - (size + PAGE_SIZE-1) & PAGE_MASK); + mmu_inval_dma_area(phys_to_virt(ba), + PAGE_ALIGN(size)); } } @@ -602,8 +612,8 @@ static void pci32_sync_single_for_device(struct device *dev, dma_addr_t ba, size_t size, enum dma_data_direction dir) { if (dir != PCI_DMA_TODEVICE) { - mmu_inval_dma_area((unsigned long)phys_to_virt(ba), - (size + PAGE_SIZE-1) & PAGE_MASK); + mmu_inval_dma_area(phys_to_virt(ba), + PAGE_ALIGN(size)); } } @@ -622,9 +632,8 @@ static void pci32_sync_sg_for_cpu(struct device *dev, struct scatterlist *sgl, if (dir != PCI_DMA_TODEVICE) { for_each_sg(sgl, sg, nents, n) { BUG_ON(page_address(sg_page(sg)) == NULL); - mmu_inval_dma_area( - (unsigned long) page_address(sg_page(sg)), - (sg->length + PAGE_SIZE-1) & PAGE_MASK); + mmu_inval_dma_area(page_address(sg_page(sg)), + PAGE_ALIGN(sg->length)); } } } @@ -638,9 +647,8 @@ static void pci32_sync_sg_for_device(struct device *device, struct scatterlist * if (dir != PCI_DMA_TODEVICE) { for_each_sg(sgl, sg, nents, n) { BUG_ON(page_address(sg_page(sg)) == NULL); - mmu_inval_dma_area( - (unsigned long) page_address(sg_page(sg)), - (sg->length + PAGE_SIZE-1) & PAGE_MASK); + mmu_inval_dma_area(page_address(sg_page(sg)), + PAGE_ALIGN(sg->length)); } } } @@ -649,6 +657,7 @@ struct dma_map_ops pci32_dma_ops = { .alloc_coherent = pci32_alloc_coherent, .free_coherent = pci32_free_coherent, .map_page = pci32_map_page, + .unmap_page = pci32_unmap_page, .map_sg = pci32_map_sg, .unmap_sg = pci32_unmap_sg, .sync_single_for_cpu = pci32_sync_single_for_cpu, @@ -658,7 +667,16 @@ struct dma_map_ops pci32_dma_ops = { }; EXPORT_SYMBOL(pci32_dma_ops); -#endif /* CONFIG_PCI */ +#endif /* CONFIG_PCI || CONFIG_SPARC_LEON */ + +#ifdef CONFIG_SPARC_LEON +struct dma_map_ops *dma_ops = &pci32_dma_ops; +#elif defined(CONFIG_SBUS) +struct dma_map_ops *dma_ops = &sbus_dma_ops; +#endif + +EXPORT_SYMBOL(dma_ops); + /* * Return whether the given PCI device DMA address mask can be @@ -717,7 +735,7 @@ static const struct file_operations sparc_io_proc_fops = { static struct resource *_sparc_find_resource(struct resource *root, unsigned long hit) { - struct resource *tmp; + struct resource *tmp; for (tmp = root->child; tmp != 0; tmp = tmp->sibling) { if (tmp->start <= hit && tmp->end >= hit) diff --git a/arch/sparc/kernel/irq.h b/arch/sparc/kernel/irq.h index db7513881530..008453b798ec 100644 --- a/arch/sparc/kernel/irq.h +++ b/arch/sparc/kernel/irq.h @@ -1,5 +1,41 @@ +#include <linux/platform_device.h> + #include <asm/btfixup.h> +/* sun4m specific type definitions */ + +/* This maps direct to CPU specific interrupt registers */ +struct sun4m_irq_percpu { + u32 pending; + u32 clear; + u32 set; +}; + +/* This maps direct to global interrupt registers */ +struct sun4m_irq_global { + u32 pending; + u32 mask; + u32 mask_clear; + u32 mask_set; + u32 interrupt_target; +}; + +extern struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS]; +extern struct sun4m_irq_global __iomem *sun4m_irq_global; + +/* + * Platform specific irq configuration + * The individual platforms assign their platform + * specifics in their init functions. + */ +struct sparc_irq_config { + void (*init_timers)(irq_handler_t); + unsigned int (*build_device_irq)(struct platform_device *op, + unsigned int real_irq); +}; +extern struct sparc_irq_config sparc_irq_config; + + /* Dave Redman (djhr@tadpole.co.uk) * changed these to function pointers.. it saves cycles and will allow * the irq dependencies to be split into different files at a later date @@ -45,12 +81,6 @@ static inline void load_profile_irq(int cpu, int limit) BTFIXUP_CALL(load_profile_irq)(cpu, limit); } -extern void (*sparc_init_timers)(irq_handler_t lvl10_irq); - -extern void claim_ticker14(irq_handler_t irq_handler, - int irq, - unsigned int timeout); - #ifdef CONFIG_SMP BTFIXUPDEF_CALL(void, set_cpu_int, int, int) BTFIXUPDEF_CALL(void, clear_cpu_int, int, int) diff --git a/arch/sparc/kernel/irq_32.c b/arch/sparc/kernel/irq_32.c index 5ad6e5c5dbb3..7c93df4099cb 100644 --- a/arch/sparc/kernel/irq_32.c +++ b/arch/sparc/kernel/irq_32.c @@ -1,8 +1,8 @@ /* - * arch/sparc/kernel/irq.c: Interrupt request handling routines. On the - * Sparc the IRQs are basically 'cast in stone' - * and you are supposed to probe the prom's device - * node trees to find out who's got which IRQ. + * Interrupt request handling routines. On the + * Sparc the IRQs are basically 'cast in stone' + * and you are supposed to probe the prom's device + * node trees to find out who's got which IRQ. * * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx) @@ -11,40 +11,11 @@ * Copyright (C) 1998-2000 Anton Blanchard (anton@samba.org) */ -#include <linux/module.h> -#include <linux/sched.h> -#include <linux/ptrace.h> -#include <linux/errno.h> -#include <linux/linkage.h> #include <linux/kernel_stat.h> -#include <linux/signal.h> -#include <linux/interrupt.h> -#include <linux/slab.h> -#include <linux/random.h> -#include <linux/init.h> -#include <linux/smp.h> -#include <linux/delay.h> -#include <linux/threads.h> -#include <linux/spinlock.h> #include <linux/seq_file.h> -#include <asm/ptrace.h> -#include <asm/processor.h> -#include <asm/system.h> -#include <asm/psr.h> -#include <asm/smp.h> -#include <asm/vaddrs.h> -#include <asm/timer.h> -#include <asm/openprom.h> -#include <asm/oplib.h> -#include <asm/traps.h> -#include <asm/irq.h> -#include <asm/io.h> -#include <asm/pgalloc.h> -#include <asm/pgtable.h> -#include <asm/pcic.h> #include <asm/cacheflush.h> -#include <asm/irq_regs.h> +#include <asm/pcic.h> #include <asm/leon.h> #include "kernel.h" @@ -57,6 +28,10 @@ #define SMP_NOP2 #define SMP_NOP3 #endif /* SMP */ + +/* platform specific irq setup */ +struct sparc_irq_config sparc_irq_config; + unsigned long arch_local_irq_save(void) { unsigned long retval; @@ -128,15 +103,7 @@ EXPORT_SYMBOL(arch_local_irq_restore); * */ -static void irq_panic(void) -{ - extern char *cputypval; - prom_printf("machine: %s doesn't have irq handlers defined!\n",cputypval); - prom_halt(); -} -void (*sparc_init_timers)(irq_handler_t ) = - (void (*)(irq_handler_t )) irq_panic; /* * Dave Redman (djhr@tadpole.co.uk) @@ -145,7 +112,7 @@ void (*sparc_init_timers)(irq_handler_t ) = * instead, because some of the devices attach very early, I do something * equally sucky but at least we'll never try to free statically allocated * space or call kmalloc before kmalloc_init :(. - * + * * In fact it's the timer10 that attaches first.. then timer14 * then kmalloc_init is called.. then the tty interrupts attach. * hmmm.... @@ -166,22 +133,20 @@ DEFINE_SPINLOCK(irq_action_lock); int show_interrupts(struct seq_file *p, void *v) { - int i = *(loff_t *) v; - struct irqaction * action; + int i = *(loff_t *)v; + struct irqaction *action; unsigned long flags; #ifdef CONFIG_SMP int j; #endif - if (sparc_cpu_model == sun4d) { - extern int show_sun4d_interrupts(struct seq_file *, void *); - + if (sparc_cpu_model == sun4d) return show_sun4d_interrupts(p, v); - } + spin_lock_irqsave(&irq_action_lock, flags); if (i < NR_IRQS) { action = sparc_irq[i].action; - if (!action) + if (!action) goto out_unlock; seq_printf(p, "%3d: ", i); #ifndef CONFIG_SMP @@ -195,7 +160,7 @@ int show_interrupts(struct seq_file *p, void *v) seq_printf(p, " %c %s", (action->flags & IRQF_DISABLED) ? '+' : ' ', action->name); - for (action=action->next; action; action = action->next) { + for (action = action->next; action; action = action->next) { seq_printf(p, ",%s %s", (action->flags & IRQF_DISABLED) ? " +" : "", action->name); @@ -209,22 +174,20 @@ out_unlock: void free_irq(unsigned int irq, void *dev_id) { - struct irqaction * action; + struct irqaction *action; struct irqaction **actionp; - unsigned long flags; + unsigned long flags; unsigned int cpu_irq; - + if (sparc_cpu_model == sun4d) { - extern void sun4d_free_irq(unsigned int, void *); - sun4d_free_irq(irq, dev_id); return; } cpu_irq = irq & (NR_IRQS - 1); - if (cpu_irq > 14) { /* 14 irq levels on the sparc */ - printk("Trying to free bogus IRQ %d\n", irq); - return; - } + if (cpu_irq > 14) { /* 14 irq levels on the sparc */ + printk(KERN_ERR "Trying to free bogus IRQ %d\n", irq); + return; + } spin_lock_irqsave(&irq_action_lock, flags); @@ -232,7 +195,7 @@ void free_irq(unsigned int irq, void *dev_id) action = *actionp; if (!action->handler) { - printk("Trying to free free IRQ%d\n",irq); + printk(KERN_ERR "Trying to free free IRQ%d\n", irq); goto out_unlock; } if (dev_id) { @@ -242,19 +205,21 @@ void free_irq(unsigned int irq, void *dev_id) actionp = &action->next; } if (!action) { - printk("Trying to free free shared IRQ%d\n",irq); + printk(KERN_ERR "Trying to free free shared IRQ%d\n", + irq); goto out_unlock; } } else if (action->flags & IRQF_SHARED) { - printk("Trying to free shared IRQ%d with NULL device ID\n", irq); + printk(KERN_ERR "Trying to free shared IRQ%d with NULL device ID\n", + irq); goto out_unlock; } - if (action->flags & SA_STATIC_ALLOC) - { - /* This interrupt is marked as specially allocated + if (action->flags & SA_STATIC_ALLOC) { + /* + * This interrupt is marked as specially allocated * so it is a bad idea to free it. */ - printk("Attempt to free statically allocated IRQ%d (%s)\n", + printk(KERN_ERR "Attempt to free statically allocated IRQ%d (%s)\n", irq, action->name); goto out_unlock; } @@ -275,7 +240,6 @@ void free_irq(unsigned int irq, void *dev_id) out_unlock: spin_unlock_irqrestore(&irq_action_lock, flags); } - EXPORT_SYMBOL(free_irq); /* @@ -297,64 +261,62 @@ void synchronize_irq(unsigned int irq) EXPORT_SYMBOL(synchronize_irq); #endif /* SMP */ -void unexpected_irq(int irq, void *dev_id, struct pt_regs * regs) +void unexpected_irq(int irq, void *dev_id, struct pt_regs *regs) { - int i; - struct irqaction * action; + int i; + struct irqaction *action; unsigned int cpu_irq; - + cpu_irq = irq & (NR_IRQS - 1); action = sparc_irq[cpu_irq].action; - printk("IO device interrupt, irq = %d\n", irq); - printk("PC = %08lx NPC = %08lx FP=%08lx\n", regs->pc, + printk(KERN_ERR "IO device interrupt, irq = %d\n", irq); + printk(KERN_ERR "PC = %08lx NPC = %08lx FP=%08lx\n", regs->pc, regs->npc, regs->u_regs[14]); if (action) { - printk("Expecting: "); - for (i = 0; i < 16; i++) - if (action->handler) - printk("[%s:%d:0x%x] ", action->name, - (int) i, (unsigned int) action->handler); + printk(KERN_ERR "Expecting: "); + for (i = 0; i < 16; i++) + if (action->handler) + printk(KERN_CONT "[%s:%d:0x%x] ", action->name, + i, (unsigned int)action->handler); } - printk("AIEEE\n"); + printk(KERN_ERR "AIEEE\n"); panic("bogus interrupt received"); } -void handler_irq(int irq, struct pt_regs * regs) +void handler_irq(int pil, struct pt_regs *regs) { struct pt_regs *old_regs; - struct irqaction * action; + struct irqaction *action; int cpu = smp_processor_id(); -#ifdef CONFIG_SMP - extern void smp4m_irq_rotate(int cpu); -#endif old_regs = set_irq_regs(regs); irq_enter(); - disable_pil_irq(irq); + disable_pil_irq(pil); #ifdef CONFIG_SMP /* Only rotate on lower priority IRQs (scsi, ethernet, etc.). */ - if((sparc_cpu_model==sun4m) && (irq < 10)) + if ((sparc_cpu_model==sun4m) && (pil < 10)) smp4m_irq_rotate(cpu); #endif - action = sparc_irq[irq].action; - sparc_irq[irq].flags |= SPARC_IRQ_INPROGRESS; - kstat_cpu(cpu).irqs[irq]++; + action = sparc_irq[pil].action; + sparc_irq[pil].flags |= SPARC_IRQ_INPROGRESS; + kstat_cpu(cpu).irqs[pil]++; do { if (!action || !action->handler) - unexpected_irq(irq, NULL, regs); - action->handler(irq, action->dev_id); + unexpected_irq(pil, NULL, regs); + action->handler(pil, action->dev_id); action = action->next; } while (action); - sparc_irq[irq].flags &= ~SPARC_IRQ_INPROGRESS; - enable_pil_irq(irq); + sparc_irq[pil].flags &= ~SPARC_IRQ_INPROGRESS; + enable_pil_irq(pil); irq_exit(); set_irq_regs(old_regs); } #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE) -/* Fast IRQs on the Sparc can only have one routine attached to them, +/* + * Fast IRQs on the Sparc can only have one routine attached to them, * thus no sharing possible. */ static int request_fast_irq(unsigned int irq, @@ -367,15 +329,13 @@ static int request_fast_irq(unsigned int irq, int ret; #if defined CONFIG_SMP && !defined CONFIG_SPARC_LEON struct tt_entry *trap_table; - extern struct tt_entry trapbase_cpu1, trapbase_cpu2, trapbase_cpu3; #endif - cpu_irq = irq & (NR_IRQS - 1); - if(cpu_irq > 14) { + if (cpu_irq > 14) { ret = -EINVAL; goto out; } - if(!handler) { + if (!handler) { ret = -EINVAL; goto out; } @@ -383,34 +343,33 @@ static int request_fast_irq(unsigned int irq, spin_lock_irqsave(&irq_action_lock, flags); action = sparc_irq[cpu_irq].action; - if(action) { - if(action->flags & IRQF_SHARED) + if (action) { + if (action->flags & IRQF_SHARED) panic("Trying to register fast irq when already shared.\n"); - if(irqflags & IRQF_SHARED) + if (irqflags & IRQF_SHARED) panic("Trying to register fast irq as shared.\n"); /* Anyway, someone already owns it so cannot be made fast. */ - printk("request_fast_irq: Trying to register yet already owned.\n"); + printk(KERN_ERR "request_fast_irq: Trying to register yet already owned.\n"); ret = -EBUSY; goto out_unlock; } - /* If this is flagged as statically allocated then we use our + /* + * If this is flagged as statically allocated then we use our * private struct which is never freed. */ if (irqflags & SA_STATIC_ALLOC) { - if (static_irq_count < MAX_STATIC_ALLOC) - action = &static_irqaction[static_irq_count++]; - else - printk("Fast IRQ%d (%s) SA_STATIC_ALLOC failed using kmalloc\n", - irq, devname); + if (static_irq_count < MAX_STATIC_ALLOC) + action = &static_irqaction[static_irq_count++]; + else + printk(KERN_ERR "Fast IRQ%d (%s) SA_STATIC_ALLOC failed using kmalloc\n", + irq, devname); } - + if (action == NULL) - action = kmalloc(sizeof(struct irqaction), - GFP_ATOMIC); - - if (!action) { + action = kmalloc(sizeof(struct irqaction), GFP_ATOMIC); + if (!action) { ret = -ENOMEM; goto out_unlock; } @@ -426,9 +385,12 @@ static int request_fast_irq(unsigned int irq, INSTANTIATE(sparc_ttable) #if defined CONFIG_SMP && !defined CONFIG_SPARC_LEON - trap_table = &trapbase_cpu1; INSTANTIATE(trap_table) - trap_table = &trapbase_cpu2; INSTANTIATE(trap_table) - trap_table = &trapbase_cpu3; INSTANTIATE(trap_table) + trap_table = &trapbase_cpu1; + INSTANTIATE(trap_table) + trap_table = &trapbase_cpu2; + INSTANTIATE(trap_table) + trap_table = &trapbase_cpu3; + INSTANTIATE(trap_table) #endif #undef INSTANTIATE /* @@ -454,7 +416,8 @@ out: return ret; } -/* These variables are used to access state from the assembler +/* + * These variables are used to access state from the assembler * interrupt handler, floppy_hardint, so we cannot put these in * the floppy driver image because that would not work in the * modular case. @@ -477,8 +440,6 @@ EXPORT_SYMBOL(pdma_base); unsigned long pdma_areasize; EXPORT_SYMBOL(pdma_areasize); -extern void floppy_hardint(void); - static irq_handler_t floppy_irq_handler; void sparc_floppy_irq(int irq, void *dev_id, struct pt_regs *regs) @@ -494,9 +455,11 @@ void sparc_floppy_irq(int irq, void *dev_id, struct pt_regs *regs) irq_exit(); enable_pil_irq(irq); set_irq_regs(old_regs); - // XXX Eek, it's totally changed with preempt_count() and such - // if (softirq_pending(cpu)) - // do_softirq(); + /* + * XXX Eek, it's totally changed with preempt_count() and such + * if (softirq_pending(cpu)) + * do_softirq(); + */ } int sparc_floppy_request_irq(int irq, unsigned long flags, @@ -511,21 +474,18 @@ EXPORT_SYMBOL(sparc_floppy_request_irq); int request_irq(unsigned int irq, irq_handler_t handler, - unsigned long irqflags, const char * devname, void *dev_id) + unsigned long irqflags, const char *devname, void *dev_id) { - struct irqaction * action, **actionp; + struct irqaction *action, **actionp; unsigned long flags; unsigned int cpu_irq; int ret; - - if (sparc_cpu_model == sun4d) { - extern int sun4d_request_irq(unsigned int, - irq_handler_t , - unsigned long, const char *, void *); + + if (sparc_cpu_model == sun4d) return sun4d_request_irq(irq, handler, irqflags, devname, dev_id); - } + cpu_irq = irq & (NR_IRQS - 1); - if(cpu_irq > 14) { + if (cpu_irq > 14) { ret = -EINVAL; goto out; } @@ -533,7 +493,7 @@ int request_irq(unsigned int irq, ret = -EINVAL; goto out; } - + spin_lock_irqsave(&irq_action_lock, flags); actionp = &sparc_irq[cpu_irq].action; @@ -544,7 +504,8 @@ int request_irq(unsigned int irq, goto out_unlock; } if ((action->flags & IRQF_DISABLED) != (irqflags & IRQF_DISABLED)) { - printk("Attempt to mix fast and slow interrupts on IRQ%d denied\n", irq); + printk(KERN_ERR "Attempt to mix fast and slow interrupts on IRQ%d denied\n", + irq); ret = -EBUSY; goto out_unlock; } @@ -559,14 +520,12 @@ int request_irq(unsigned int irq, if (static_irq_count < MAX_STATIC_ALLOC) action = &static_irqaction[static_irq_count++]; else - printk("Request for IRQ%d (%s) SA_STATIC_ALLOC failed using kmalloc\n", irq, devname); + printk(KERN_ERR "Request for IRQ%d (%s) SA_STATIC_ALLOC failed using kmalloc\n", + irq, devname); } - if (action == NULL) - action = kmalloc(sizeof(struct irqaction), - GFP_ATOMIC); - - if (!action) { + action = kmalloc(sizeof(struct irqaction), GFP_ATOMIC); + if (!action) { ret = -ENOMEM; goto out_unlock; } @@ -587,7 +546,6 @@ out_unlock: out: return ret; } - EXPORT_SYMBOL(request_irq); void disable_irq_nosync(unsigned int irq) @@ -606,26 +564,30 @@ void enable_irq(unsigned int irq) { __enable_irq(irq); } - EXPORT_SYMBOL(enable_irq); -/* We really don't need these at all on the Sparc. We only have +/* + * We really don't need these at all on the Sparc. We only have * stubs here because they are exported to modules. */ unsigned long probe_irq_on(void) { return 0; } - EXPORT_SYMBOL(probe_irq_on); int probe_irq_off(unsigned long mask) { return 0; } - EXPORT_SYMBOL(probe_irq_off); +static unsigned int build_device_irq(struct platform_device *op, + unsigned int real_irq) +{ + return real_irq; +} + /* djhr * This could probably be made indirect too and assigned in the CPU * bits of the code. That would be much nicer I think and would also @@ -636,11 +598,9 @@ EXPORT_SYMBOL(probe_irq_off); void __init init_IRQ(void) { - extern void sun4c_init_IRQ( void ); - extern void sun4m_init_IRQ( void ); - extern void sun4d_init_IRQ( void ); + sparc_irq_config.build_device_irq = build_device_irq; - switch(sparc_cpu_model) { + switch (sparc_cpu_model) { case sun4c: case sun4: sun4c_init_IRQ(); @@ -656,7 +616,7 @@ void __init init_IRQ(void) #endif sun4m_init_IRQ(); break; - + case sun4d: sun4d_init_IRQ(); break; diff --git a/arch/sparc/kernel/irq_64.c b/arch/sparc/kernel/irq_64.c index 830d70a3e20b..eb16e3b8a2dd 100644 --- a/arch/sparc/kernel/irq_64.c +++ b/arch/sparc/kernel/irq_64.c @@ -82,7 +82,7 @@ static void bucket_clear_chain_pa(unsigned long bucket_pa) "i" (ASI_PHYS_USE_EC)); } -static unsigned int bucket_get_virt_irq(unsigned long bucket_pa) +static unsigned int bucket_get_irq(unsigned long bucket_pa) { unsigned int ret; @@ -90,21 +90,20 @@ static unsigned int bucket_get_virt_irq(unsigned long bucket_pa) : "=&r" (ret) : "r" (bucket_pa + offsetof(struct ino_bucket, - __virt_irq)), + __irq)), "i" (ASI_PHYS_USE_EC)); return ret; } -static void bucket_set_virt_irq(unsigned long bucket_pa, - unsigned int virt_irq) +static void bucket_set_irq(unsigned long bucket_pa, unsigned int irq) { __asm__ __volatile__("stwa %0, [%1] %2" : /* no outputs */ - : "r" (virt_irq), + : "r" (irq), "r" (bucket_pa + offsetof(struct ino_bucket, - __virt_irq)), + __irq)), "i" (ASI_PHYS_USE_EC)); } @@ -114,50 +113,49 @@ static struct { unsigned int dev_handle; unsigned int dev_ino; unsigned int in_use; -} virt_irq_table[NR_IRQS]; -static DEFINE_SPINLOCK(virt_irq_alloc_lock); +} irq_table[NR_IRQS]; +static DEFINE_SPINLOCK(irq_alloc_lock); -unsigned char virt_irq_alloc(unsigned int dev_handle, - unsigned int dev_ino) +unsigned char irq_alloc(unsigned int dev_handle, unsigned int dev_ino) { unsigned long flags; unsigned char ent; BUILD_BUG_ON(NR_IRQS >= 256); - spin_lock_irqsave(&virt_irq_alloc_lock, flags); + spin_lock_irqsave(&irq_alloc_lock, flags); for (ent = 1; ent < NR_IRQS; ent++) { - if (!virt_irq_table[ent].in_use) + if (!irq_table[ent].in_use) break; } if (ent >= NR_IRQS) { printk(KERN_ERR "IRQ: Out of virtual IRQs.\n"); ent = 0; } else { - virt_irq_table[ent].dev_handle = dev_handle; - virt_irq_table[ent].dev_ino = dev_ino; - virt_irq_table[ent].in_use = 1; + irq_table[ent].dev_handle = dev_handle; + irq_table[ent].dev_ino = dev_ino; + irq_table[ent].in_use = 1; } - spin_unlock_irqrestore(&virt_irq_alloc_lock, flags); + spin_unlock_irqrestore(&irq_alloc_lock, flags); return ent; } #ifdef CONFIG_PCI_MSI -void virt_irq_free(unsigned int virt_irq) +void irq_free(unsigned int irq) { unsigned long flags; - if (virt_irq >= NR_IRQS) + if (irq >= NR_IRQS) return; - spin_lock_irqsave(&virt_irq_alloc_lock, flags); + spin_lock_irqsave(&irq_alloc_lock, flags); - virt_irq_table[virt_irq].in_use = 0; + irq_table[irq].in_use = 0; - spin_unlock_irqrestore(&virt_irq_alloc_lock, flags); + spin_unlock_irqrestore(&irq_alloc_lock, flags); } #endif @@ -190,7 +188,7 @@ int show_interrupts(struct seq_file *p, void *v) for_each_online_cpu(j) seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); #endif - seq_printf(p, " %9s", irq_desc[i].chip->name); + seq_printf(p, " %9s", irq_desc[i].irq_data.chip->name); seq_printf(p, " %s", action->name); for (action=action->next; action; action = action->next) @@ -253,39 +251,38 @@ struct irq_handler_data { }; #ifdef CONFIG_SMP -static int irq_choose_cpu(unsigned int virt_irq, const struct cpumask *affinity) +static int irq_choose_cpu(unsigned int irq, const struct cpumask *affinity) { cpumask_t mask; int cpuid; cpumask_copy(&mask, affinity); if (cpus_equal(mask, cpu_online_map)) { - cpuid = map_to_cpu(virt_irq); + cpuid = map_to_cpu(irq); } else { cpumask_t tmp; cpus_and(tmp, cpu_online_map, mask); - cpuid = cpus_empty(tmp) ? map_to_cpu(virt_irq) : first_cpu(tmp); + cpuid = cpus_empty(tmp) ? map_to_cpu(irq) : first_cpu(tmp); } return cpuid; } #else -#define irq_choose_cpu(virt_irq, affinity) \ +#define irq_choose_cpu(irq, affinity) \ real_hard_smp_processor_id() #endif -static void sun4u_irq_enable(unsigned int virt_irq) +static void sun4u_irq_enable(struct irq_data *data) { - struct irq_handler_data *data = get_irq_chip_data(virt_irq); + struct irq_handler_data *handler_data = data->handler_data; - if (likely(data)) { + if (likely(handler_data)) { unsigned long cpuid, imap, val; unsigned int tid; - cpuid = irq_choose_cpu(virt_irq, - irq_desc[virt_irq].affinity); - imap = data->imap; + cpuid = irq_choose_cpu(data->irq, data->affinity); + imap = handler_data->imap; tid = sun4u_compute_tid(imap, cpuid); @@ -294,21 +291,21 @@ static void sun4u_irq_enable(unsigned int virt_irq) IMAP_AID_SAFARI | IMAP_NID_SAFARI); val |= tid | IMAP_VALID; upa_writeq(val, imap); - upa_writeq(ICLR_IDLE, data->iclr); + upa_writeq(ICLR_IDLE, handler_data->iclr); } } -static int sun4u_set_affinity(unsigned int virt_irq, - const struct cpumask *mask) +static int sun4u_set_affinity(struct irq_data *data, + const struct cpumask *mask, bool force) { - struct irq_handler_data *data = get_irq_chip_data(virt_irq); + struct irq_handler_data *handler_data = data->handler_data; - if (likely(data)) { + if (likely(handler_data)) { unsigned long cpuid, imap, val; unsigned int tid; - cpuid = irq_choose_cpu(virt_irq, mask); - imap = data->imap; + cpuid = irq_choose_cpu(data->irq, mask); + imap = handler_data->imap; tid = sun4u_compute_tid(imap, cpuid); @@ -317,7 +314,7 @@ static int sun4u_set_affinity(unsigned int virt_irq, IMAP_AID_SAFARI | IMAP_NID_SAFARI); val |= tid | IMAP_VALID; upa_writeq(val, imap); - upa_writeq(ICLR_IDLE, data->iclr); + upa_writeq(ICLR_IDLE, handler_data->iclr); } return 0; @@ -340,27 +337,26 @@ static int sun4u_set_affinity(unsigned int virt_irq, * sees that, it also hooks up a default ->shutdown method which * invokes ->mask() which we do not want. See irq_chip_set_defaults(). */ -static void sun4u_irq_disable(unsigned int virt_irq) +static void sun4u_irq_disable(struct irq_data *data) { } -static void sun4u_irq_eoi(unsigned int virt_irq) +static void sun4u_irq_eoi(struct irq_data *data) { - struct irq_handler_data *data = get_irq_chip_data(virt_irq); - struct irq_desc *desc = irq_desc + virt_irq; + struct irq_handler_data *handler_data = data->handler_data; + struct irq_desc *desc = irq_desc + data->irq; if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) return; - if (likely(data)) - upa_writeq(ICLR_IDLE, data->iclr); + if (likely(handler_data)) + upa_writeq(ICLR_IDLE, handler_data->iclr); } -static void sun4v_irq_enable(unsigned int virt_irq) +static void sun4v_irq_enable(struct irq_data *data) { - unsigned int ino = virt_irq_table[virt_irq].dev_ino; - unsigned long cpuid = irq_choose_cpu(virt_irq, - irq_desc[virt_irq].affinity); + unsigned int ino = irq_table[data->irq].dev_ino; + unsigned long cpuid = irq_choose_cpu(data->irq, data->affinity); int err; err = sun4v_intr_settarget(ino, cpuid); @@ -377,11 +373,11 @@ static void sun4v_irq_enable(unsigned int virt_irq) ino, err); } -static int sun4v_set_affinity(unsigned int virt_irq, - const struct cpumask *mask) +static int sun4v_set_affinity(struct irq_data *data, + const struct cpumask *mask, bool force) { - unsigned int ino = virt_irq_table[virt_irq].dev_ino; - unsigned long cpuid = irq_choose_cpu(virt_irq, mask); + unsigned int ino = irq_table[data->irq].dev_ino; + unsigned long cpuid = irq_choose_cpu(data->irq, mask); int err; err = sun4v_intr_settarget(ino, cpuid); @@ -392,9 +388,9 @@ static int sun4v_set_affinity(unsigned int virt_irq, return 0; } -static void sun4v_irq_disable(unsigned int virt_irq) +static void sun4v_irq_disable(struct irq_data *data) { - unsigned int ino = virt_irq_table[virt_irq].dev_ino; + unsigned int ino = irq_table[data->irq].dev_ino; int err; err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED); @@ -403,10 +399,10 @@ static void sun4v_irq_disable(unsigned int virt_irq) "err(%d)\n", ino, err); } -static void sun4v_irq_eoi(unsigned int virt_irq) +static void sun4v_irq_eoi(struct irq_data *data) { - unsigned int ino = virt_irq_table[virt_irq].dev_ino; - struct irq_desc *desc = irq_desc + virt_irq; + unsigned int ino = irq_table[data->irq].dev_ino; + struct irq_desc *desc = irq_desc + data->irq; int err; if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) @@ -418,15 +414,15 @@ static void sun4v_irq_eoi(unsigned int virt_irq) "err(%d)\n", ino, err); } -static void sun4v_virq_enable(unsigned int virt_irq) +static void sun4v_virq_enable(struct irq_data *data) { unsigned long cpuid, dev_handle, dev_ino; int err; - cpuid = irq_choose_cpu(virt_irq, irq_desc[virt_irq].affinity); + cpuid = irq_choose_cpu(data->irq, data->affinity); - dev_handle = virt_irq_table[virt_irq].dev_handle; - dev_ino = virt_irq_table[virt_irq].dev_ino; + dev_handle = irq_table[data->irq].dev_handle; + dev_ino = irq_table[data->irq].dev_ino; err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid); if (err != HV_EOK) @@ -447,16 +443,16 @@ static void sun4v_virq_enable(unsigned int virt_irq) dev_handle, dev_ino, err); } -static int sun4v_virt_set_affinity(unsigned int virt_irq, - const struct cpumask *mask) +static int sun4v_virt_set_affinity(struct irq_data *data, + const struct cpumask *mask, bool force) { unsigned long cpuid, dev_handle, dev_ino; int err; - cpuid = irq_choose_cpu(virt_irq, mask); + cpuid = irq_choose_cpu(data->irq, mask); - dev_handle = virt_irq_table[virt_irq].dev_handle; - dev_ino = virt_irq_table[virt_irq].dev_ino; + dev_handle = irq_table[data->irq].dev_handle; + dev_ino = irq_table[data->irq].dev_ino; err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid); if (err != HV_EOK) @@ -467,13 +463,13 @@ static int sun4v_virt_set_affinity(unsigned int virt_irq, return 0; } -static void sun4v_virq_disable(unsigned int virt_irq) +static void sun4v_virq_disable(struct irq_data *data) { unsigned long dev_handle, dev_ino; int err; - dev_handle = virt_irq_table[virt_irq].dev_handle; - dev_ino = virt_irq_table[virt_irq].dev_ino; + dev_handle = irq_table[data->irq].dev_handle; + dev_ino = irq_table[data->irq].dev_ino; err = sun4v_vintr_set_valid(dev_handle, dev_ino, HV_INTR_DISABLED); @@ -483,17 +479,17 @@ static void sun4v_virq_disable(unsigned int virt_irq) dev_handle, dev_ino, err); } -static void sun4v_virq_eoi(unsigned int virt_irq) +static void sun4v_virq_eoi(struct irq_data *data) { - struct irq_desc *desc = irq_desc + virt_irq; + struct irq_desc *desc = irq_desc + data->irq; unsigned long dev_handle, dev_ino; int err; if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) return; - dev_handle = virt_irq_table[virt_irq].dev_handle; - dev_ino = virt_irq_table[virt_irq].dev_ino; + dev_handle = irq_table[data->irq].dev_handle; + dev_ino = irq_table[data->irq].dev_ino; err = sun4v_vintr_set_state(dev_handle, dev_ino, HV_INTR_STATE_IDLE); @@ -504,50 +500,49 @@ static void sun4v_virq_eoi(unsigned int virt_irq) } static struct irq_chip sun4u_irq = { - .name = "sun4u", - .enable = sun4u_irq_enable, - .disable = sun4u_irq_disable, - .eoi = sun4u_irq_eoi, - .set_affinity = sun4u_set_affinity, + .name = "sun4u", + .irq_enable = sun4u_irq_enable, + .irq_disable = sun4u_irq_disable, + .irq_eoi = sun4u_irq_eoi, + .irq_set_affinity = sun4u_set_affinity, }; static struct irq_chip sun4v_irq = { - .name = "sun4v", - .enable = sun4v_irq_enable, - .disable = sun4v_irq_disable, - .eoi = sun4v_irq_eoi, - .set_affinity = sun4v_set_affinity, + .name = "sun4v", + .irq_enable = sun4v_irq_enable, + .irq_disable = sun4v_irq_disable, + .irq_eoi = sun4v_irq_eoi, + .irq_set_affinity = sun4v_set_affinity, }; static struct irq_chip sun4v_virq = { - .name = "vsun4v", - .enable = sun4v_virq_enable, - .disable = sun4v_virq_disable, - .eoi = sun4v_virq_eoi, - .set_affinity = sun4v_virt_set_affinity, + .name = "vsun4v", + .irq_enable = sun4v_virq_enable, + .irq_disable = sun4v_virq_disable, + .irq_eoi = sun4v_virq_eoi, + .irq_set_affinity = sun4v_virt_set_affinity, }; -static void pre_flow_handler(unsigned int virt_irq, - struct irq_desc *desc) +static void pre_flow_handler(unsigned int irq, struct irq_desc *desc) { - struct irq_handler_data *data = get_irq_chip_data(virt_irq); - unsigned int ino = virt_irq_table[virt_irq].dev_ino; + struct irq_handler_data *handler_data = get_irq_data(irq); + unsigned int ino = irq_table[irq].dev_ino; - data->pre_handler(ino, data->arg1, data->arg2); + handler_data->pre_handler(ino, handler_data->arg1, handler_data->arg2); - handle_fasteoi_irq(virt_irq, desc); + handle_fasteoi_irq(irq, desc); } -void irq_install_pre_handler(int virt_irq, +void irq_install_pre_handler(int irq, void (*func)(unsigned int, void *, void *), void *arg1, void *arg2) { - struct irq_handler_data *data = get_irq_chip_data(virt_irq); - struct irq_desc *desc = irq_desc + virt_irq; + struct irq_handler_data *handler_data = get_irq_data(irq); + struct irq_desc *desc = irq_desc + irq; - data->pre_handler = func; - data->arg1 = arg1; - data->arg2 = arg2; + handler_data->pre_handler = func; + handler_data->arg1 = arg1; + handler_data->arg2 = arg2; desc->handle_irq = pre_flow_handler; } @@ -555,81 +550,81 @@ void irq_install_pre_handler(int virt_irq, unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) { struct ino_bucket *bucket; - struct irq_handler_data *data; - unsigned int virt_irq; + struct irq_handler_data *handler_data; + unsigned int irq; int ino; BUG_ON(tlb_type == hypervisor); ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup; bucket = &ivector_table[ino]; - virt_irq = bucket_get_virt_irq(__pa(bucket)); - if (!virt_irq) { - virt_irq = virt_irq_alloc(0, ino); - bucket_set_virt_irq(__pa(bucket), virt_irq); - set_irq_chip_and_handler_name(virt_irq, + irq = bucket_get_irq(__pa(bucket)); + if (!irq) { + irq = irq_alloc(0, ino); + bucket_set_irq(__pa(bucket), irq); + set_irq_chip_and_handler_name(irq, &sun4u_irq, handle_fasteoi_irq, "IVEC"); } - data = get_irq_chip_data(virt_irq); - if (unlikely(data)) + handler_data = get_irq_data(irq); + if (unlikely(handler_data)) goto out; - data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); - if (unlikely(!data)) { + handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); + if (unlikely(!handler_data)) { prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); prom_halt(); } - set_irq_chip_data(virt_irq, data); + set_irq_data(irq, handler_data); - data->imap = imap; - data->iclr = iclr; + handler_data->imap = imap; + handler_data->iclr = iclr; out: - return virt_irq; + return irq; } static unsigned int sun4v_build_common(unsigned long sysino, struct irq_chip *chip) { struct ino_bucket *bucket; - struct irq_handler_data *data; - unsigned int virt_irq; + struct irq_handler_data *handler_data; + unsigned int irq; BUG_ON(tlb_type != hypervisor); bucket = &ivector_table[sysino]; - virt_irq = bucket_get_virt_irq(__pa(bucket)); - if (!virt_irq) { - virt_irq = virt_irq_alloc(0, sysino); - bucket_set_virt_irq(__pa(bucket), virt_irq); - set_irq_chip_and_handler_name(virt_irq, chip, + irq = bucket_get_irq(__pa(bucket)); + if (!irq) { + irq = irq_alloc(0, sysino); + bucket_set_irq(__pa(bucket), irq); + set_irq_chip_and_handler_name(irq, chip, handle_fasteoi_irq, "IVEC"); } - data = get_irq_chip_data(virt_irq); - if (unlikely(data)) + handler_data = get_irq_data(irq); + if (unlikely(handler_data)) goto out; - data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); - if (unlikely(!data)) { + handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); + if (unlikely(!handler_data)) { prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); prom_halt(); } - set_irq_chip_data(virt_irq, data); + set_irq_data(irq, handler_data); /* Catch accidental accesses to these things. IMAP/ICLR handling * is done by hypervisor calls on sun4v platforms, not by direct * register accesses. */ - data->imap = ~0UL; - data->iclr = ~0UL; + handler_data->imap = ~0UL; + handler_data->iclr = ~0UL; out: - return virt_irq; + return irq; } unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino) @@ -641,11 +636,11 @@ unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino) unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino) { - struct irq_handler_data *data; + struct irq_handler_data *handler_data; unsigned long hv_err, cookie; struct ino_bucket *bucket; struct irq_desc *desc; - unsigned int virt_irq; + unsigned int irq; bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC); if (unlikely(!bucket)) @@ -662,32 +657,32 @@ unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino) ((unsigned long) bucket + sizeof(struct ino_bucket))); - virt_irq = virt_irq_alloc(devhandle, devino); - bucket_set_virt_irq(__pa(bucket), virt_irq); + irq = irq_alloc(devhandle, devino); + bucket_set_irq(__pa(bucket), irq); - set_irq_chip_and_handler_name(virt_irq, &sun4v_virq, + set_irq_chip_and_handler_name(irq, &sun4v_virq, handle_fasteoi_irq, "IVEC"); - data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); - if (unlikely(!data)) + handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); + if (unlikely(!handler_data)) return 0; /* In order to make the LDC channel startup sequence easier, * especially wrt. locking, we do not let request_irq() enable * the interrupt. */ - desc = irq_desc + virt_irq; + desc = irq_desc + irq; desc->status |= IRQ_NOAUTOEN; - set_irq_chip_data(virt_irq, data); + set_irq_data(irq, handler_data); /* Catch accidental accesses to these things. IMAP/ICLR handling * is done by hypervisor calls on sun4v platforms, not by direct * register accesses. */ - data->imap = ~0UL; - data->iclr = ~0UL; + handler_data->imap = ~0UL; + handler_data->iclr = ~0UL; cookie = ~__pa(bucket); hv_err = sun4v_vintr_set_cookie(devhandle, devino, cookie); @@ -697,30 +692,30 @@ unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino) prom_halt(); } - return virt_irq; + return irq; } -void ack_bad_irq(unsigned int virt_irq) +void ack_bad_irq(unsigned int irq) { - unsigned int ino = virt_irq_table[virt_irq].dev_ino; + unsigned int ino = irq_table[irq].dev_ino; if (!ino) ino = 0xdeadbeef; - printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n", - ino, virt_irq); + printk(KERN_CRIT "Unexpected IRQ from ino[%x] irq[%u]\n", + ino, irq); } void *hardirq_stack[NR_CPUS]; void *softirq_stack[NR_CPUS]; -void __irq_entry handler_irq(int irq, struct pt_regs *regs) +void __irq_entry handler_irq(int pil, struct pt_regs *regs) { unsigned long pstate, bucket_pa; struct pt_regs *old_regs; void *orig_sp; - clear_softint(1 << irq); + clear_softint(1 << pil); old_regs = set_irq_regs(regs); irq_enter(); @@ -741,16 +736,16 @@ void __irq_entry handler_irq(int irq, struct pt_regs *regs) while (bucket_pa) { struct irq_desc *desc; unsigned long next_pa; - unsigned int virt_irq; + unsigned int irq; next_pa = bucket_get_chain_pa(bucket_pa); - virt_irq = bucket_get_virt_irq(bucket_pa); + irq = bucket_get_irq(bucket_pa); bucket_clear_chain_pa(bucket_pa); - desc = irq_desc + virt_irq; + desc = irq_desc + irq; if (!(desc->status & IRQ_DISABLED)) - desc->handle_irq(virt_irq, desc); + desc->handle_irq(irq, desc); bucket_pa = next_pa; } @@ -798,9 +793,12 @@ void fixup_irqs(void) raw_spin_lock_irqsave(&irq_desc[irq].lock, flags); if (irq_desc[irq].action && !(irq_desc[irq].status & IRQ_PER_CPU)) { - if (irq_desc[irq].chip->set_affinity) - irq_desc[irq].chip->set_affinity(irq, - irq_desc[irq].affinity); + struct irq_data *data = irq_get_irq_data(irq); + + if (data->chip->irq_set_affinity) + data->chip->irq_set_affinity(data, + data->affinity, + false); } raw_spin_unlock_irqrestore(&irq_desc[irq].lock, flags); } diff --git a/arch/sparc/kernel/kernel.h b/arch/sparc/kernel/kernel.h index 15d8a3f645c9..24ad449886be 100644 --- a/arch/sparc/kernel/kernel.h +++ b/arch/sparc/kernel/kernel.h @@ -3,6 +3,8 @@ #include <linux/interrupt.h> +#include <asm/traps.h> + /* cpu.c */ extern const char *sparc_cpu_type; extern const char *sparc_pmu_type; @@ -26,6 +28,53 @@ extern int static_irq_count; extern spinlock_t irq_action_lock; extern void unexpected_irq(int irq, void *dev_id, struct pt_regs * regs); +extern void init_IRQ(void); + +/* sun4c_irq.c */ +extern void sun4c_init_IRQ(void); + +/* sun4m_irq.c */ +extern unsigned int lvl14_resolution; + +extern void sun4m_init_IRQ(void); +extern void sun4m_clear_profile_irq(int cpu); + +/* sun4d_irq.c */ +extern spinlock_t sun4d_imsk_lock; + +extern void sun4d_init_IRQ(void); +extern int sun4d_request_irq(unsigned int irq, + irq_handler_t handler, + unsigned long irqflags, + const char *devname, void *dev_id); +extern int show_sun4d_interrupts(struct seq_file *, void *); +extern void sun4d_distribute_irqs(void); +extern void sun4d_free_irq(unsigned int irq, void *dev_id); + +/* head_32.S */ +extern unsigned int t_nmi[]; +extern unsigned int linux_trap_ipi15_sun4d[]; +extern unsigned int linux_trap_ipi15_sun4m[]; + +extern struct tt_entry trapbase_cpu1; +extern struct tt_entry trapbase_cpu2; +extern struct tt_entry trapbase_cpu3; + +extern char cputypval[]; + +/* entry.S */ +extern unsigned long lvl14_save[4]; +extern unsigned int real_irq_entry[]; +extern unsigned int smp4d_ticker[]; +extern unsigned int patchme_maybe_smp_msg[]; + +extern void floppy_hardint(void); + +/* trampoline_32.S */ +extern int __smp4m_processor_id(void); +extern int __smp4d_processor_id(void); +extern unsigned long sun4m_cpu_startup; +extern unsigned long sun4d_cpu_startup; #else /* CONFIG_SPARC32 */ #endif /* CONFIG_SPARC32 */ diff --git a/arch/sparc/kernel/ldc.c b/arch/sparc/kernel/ldc.c index df39a0f0d27a..732b0bce6001 100644 --- a/arch/sparc/kernel/ldc.c +++ b/arch/sparc/kernel/ldc.c @@ -790,16 +790,20 @@ static void send_events(struct ldc_channel *lp, unsigned int event_mask) static irqreturn_t ldc_rx(int irq, void *dev_id) { struct ldc_channel *lp = dev_id; - unsigned long orig_state, hv_err, flags; + unsigned long orig_state, flags; unsigned int event_mask; spin_lock_irqsave(&lp->lock, flags); orig_state = lp->chan_state; - hv_err = sun4v_ldc_rx_get_state(lp->id, - &lp->rx_head, - &lp->rx_tail, - &lp->chan_state); + + /* We should probably check for hypervisor errors here and + * reset the LDC channel if we get one. + */ + sun4v_ldc_rx_get_state(lp->id, + &lp->rx_head, + &lp->rx_tail, + &lp->chan_state); ldcdbg(RX, "RX state[0x%02lx:0x%02lx] head[0x%04lx] tail[0x%04lx]\n", orig_state, lp->chan_state, lp->rx_head, lp->rx_tail); @@ -904,16 +908,20 @@ out: static irqreturn_t ldc_tx(int irq, void *dev_id) { struct ldc_channel *lp = dev_id; - unsigned long flags, hv_err, orig_state; + unsigned long flags, orig_state; unsigned int event_mask = 0; spin_lock_irqsave(&lp->lock, flags); orig_state = lp->chan_state; - hv_err = sun4v_ldc_tx_get_state(lp->id, - &lp->tx_head, - &lp->tx_tail, - &lp->chan_state); + + /* We should probably check for hypervisor errors here and + * reset the LDC channel if we get one. + */ + sun4v_ldc_tx_get_state(lp->id, + &lp->tx_head, + &lp->tx_tail, + &lp->chan_state); ldcdbg(TX, " TX state[0x%02lx:0x%02lx] head[0x%04lx] tail[0x%04lx]\n", orig_state, lp->chan_state, lp->tx_head, lp->tx_tail); diff --git a/arch/sparc/kernel/leon_kernel.c b/arch/sparc/kernel/leon_kernel.c index fdab7f854f80..2969f777fa11 100644 --- a/arch/sparc/kernel/leon_kernel.c +++ b/arch/sparc/kernel/leon_kernel.c @@ -30,6 +30,7 @@ struct amba_apb_device leon_percpu_timer_dev[16]; int leondebug_irq_disable; int leon_debug_irqout; static int dummy_master_l10_counter; +unsigned long amba_system_id; unsigned long leon3_gptimer_irq; /* interrupt controller irq number */ unsigned long leon3_gptimer_idx; /* Timer Index (0..6) within Timer Core */ @@ -117,10 +118,16 @@ void __init leon_init_timers(irq_handler_t counter_fn) master_l10_counter = (unsigned int *)&dummy_master_l10_counter; dummy_master_l10_counter = 0; - /*Find IRQMP IRQ Controller Registers base address otherwise bail out.*/ rootnp = of_find_node_by_path("/ambapp0"); if (!rootnp) goto bad; + + /* Find System ID: GRLIB build ID and optional CHIP ID */ + pp = of_find_property(rootnp, "systemid", &len); + if (pp) + amba_system_id = *(unsigned long *)pp->value; + + /* Find IRQMP IRQ Controller Registers base adr otherwise bail out */ np = of_find_node_by_name(rootnp, "GAISLER_IRQMP"); if (!np) { np = of_find_node_by_name(rootnp, "01_00d"); @@ -340,7 +347,7 @@ void leon_enable_irq_cpu(unsigned int irq_nr, unsigned int cpu) void __init leon_init_IRQ(void) { - sparc_init_timers = leon_init_timers; + sparc_irq_config.init_timers = leon_init_timers; BTFIXUPSET_CALL(enable_irq, leon_enable_irq, BTFIXUPCALL_NORM); BTFIXUPSET_CALL(disable_irq, leon_disable_irq, BTFIXUPCALL_NORM); diff --git a/arch/sparc/kernel/leon_pmc.c b/arch/sparc/kernel/leon_pmc.c new file mode 100644 index 000000000000..519ca923f59f --- /dev/null +++ b/arch/sparc/kernel/leon_pmc.c @@ -0,0 +1,82 @@ +/* leon_pmc.c: LEON Power-down cpu_idle() handler + * + * Copyright (C) 2011 Daniel Hellstrom (daniel@gaisler.com) Aeroflex Gaisler AB + */ + +#include <linux/init.h> +#include <linux/pm.h> + +#include <asm/leon_amba.h> +#include <asm/leon.h> + +/* List of Systems that need fixup instructions around power-down instruction */ +unsigned int pmc_leon_fixup_ids[] = { + AEROFLEX_UT699, + GAISLER_GR712RC, + LEON4_NEXTREME1, + 0 +}; + +int pmc_leon_need_fixup(void) +{ + unsigned int systemid = amba_system_id >> 16; + unsigned int *id; + + id = &pmc_leon_fixup_ids[0]; + while (*id != 0) { + if (*id == systemid) + return 1; + id++; + } + + return 0; +} + +/* + * CPU idle callback function for systems that need some extra handling + * See .../arch/sparc/kernel/process.c + */ +void pmc_leon_idle_fixup(void) +{ + /* Prepare an address to a non-cachable region. APB is always + * none-cachable. One instruction is executed after the Sleep + * instruction, we make sure to read the bus and throw away the + * value by accessing a non-cachable area, also we make sure the + * MMU does not get a TLB miss here by using the MMU BYPASS ASI. + */ + register unsigned int address = (unsigned int)leon3_irqctrl_regs; + __asm__ __volatile__ ( + "mov %%g0, %%asr19\n" + "lda [%0] %1, %%g0\n" + : + : "r"(address), "i"(ASI_LEON_BYPASS)); +} + +/* + * CPU idle callback function + * See .../arch/sparc/kernel/process.c + */ +void pmc_leon_idle(void) +{ + /* For systems without power-down, this will be no-op */ + __asm__ __volatile__ ("mov %g0, %asr19\n\t"); +} + +/* Install LEON Power Down function */ +static int __init leon_pmc_install(void) +{ + /* Assign power management IDLE handler */ + if (pmc_leon_need_fixup()) + pm_idle = pmc_leon_idle_fixup; + else + pm_idle = pmc_leon_idle; + + printk(KERN_INFO "leon: power management initialized\n"); + + return 0; +} + +/* This driver is not critical to the boot process, don't care + * if initialized late. + */ +late_initcall(leon_pmc_install); diff --git a/arch/sparc/kernel/leon_smp.c b/arch/sparc/kernel/leon_smp.c index 16582d85368a..8f5de4aa3c0a 100644 --- a/arch/sparc/kernel/leon_smp.c +++ b/arch/sparc/kernel/leon_smp.c @@ -41,6 +41,8 @@ #include <asm/leon.h> #include <asm/leon_amba.h> +#include "kernel.h" + #ifdef CONFIG_SPARC_LEON #include "irq.h" @@ -261,23 +263,23 @@ void __init leon_smp_done(void) /* Free unneeded trap tables */ if (!cpu_isset(1, cpu_present_map)) { - ClearPageReserved(virt_to_page(trapbase_cpu1)); - init_page_count(virt_to_page(trapbase_cpu1)); - free_page((unsigned long)trapbase_cpu1); + ClearPageReserved(virt_to_page(&trapbase_cpu1)); + init_page_count(virt_to_page(&trapbase_cpu1)); + free_page((unsigned long)&trapbase_cpu1); totalram_pages++; num_physpages++; } if (!cpu_isset(2, cpu_present_map)) { - ClearPageReserved(virt_to_page(trapbase_cpu2)); - init_page_count(virt_to_page(trapbase_cpu2)); - free_page((unsigned long)trapbase_cpu2); + ClearPageReserved(virt_to_page(&trapbase_cpu2)); + init_page_count(virt_to_page(&trapbase_cpu2)); + free_page((unsigned long)&trapbase_cpu2); totalram_pages++; num_physpages++; } if (!cpu_isset(3, cpu_present_map)) { - ClearPageReserved(virt_to_page(trapbase_cpu3)); - init_page_count(virt_to_page(trapbase_cpu3)); - free_page((unsigned long)trapbase_cpu3); + ClearPageReserved(virt_to_page(&trapbase_cpu3)); + init_page_count(virt_to_page(&trapbase_cpu3)); + free_page((unsigned long)&trapbase_cpu3); totalram_pages++; num_physpages++; } @@ -437,15 +439,6 @@ void __init leon_blackbox_current(unsigned *addr) } -/* - * CPU idle callback function - * See .../arch/sparc/kernel/process.c - */ -void pmc_leon_idle(void) -{ - __asm__ volatile ("mov %g0, %asr19"); -} - void __init leon_init_smp(void) { /* Patch ipi15 trap table */ @@ -456,13 +449,6 @@ void __init leon_init_smp(void) BTFIXUPSET_CALL(smp_cross_call, leon_cross_call, BTFIXUPCALL_NORM); BTFIXUPSET_CALL(__hard_smp_processor_id, __leon_processor_id, BTFIXUPCALL_NORM); - -#ifndef PMC_NO_IDLE - /* Assign power management IDLE handler */ - pm_idle = pmc_leon_idle; - printk(KERN_INFO "leon: power management initialized\n"); -#endif - } #endif /* CONFIG_SPARC_LEON */ diff --git a/arch/sparc/kernel/of_device_32.c b/arch/sparc/kernel/of_device_32.c index 2d055a1e9cc2..a312af40ea84 100644 --- a/arch/sparc/kernel/of_device_32.c +++ b/arch/sparc/kernel/of_device_32.c @@ -13,6 +13,7 @@ #include <asm/leon_amba.h> #include "of_device_common.h" +#include "irq.h" /* * PCI bus specific translator @@ -355,7 +356,8 @@ static struct platform_device * __init scan_one_device(struct device_node *dp, if (intr) { op->archdata.num_irqs = len / sizeof(struct linux_prom_irqs); for (i = 0; i < op->archdata.num_irqs; i++) - op->archdata.irqs[i] = intr[i].pri; + op->archdata.irqs[i] = + sparc_irq_config.build_device_irq(op, intr[i].pri); } else { const unsigned int *irq = of_get_property(dp, "interrupts", &len); @@ -363,64 +365,13 @@ static struct platform_device * __init scan_one_device(struct device_node *dp, if (irq) { op->archdata.num_irqs = len / sizeof(unsigned int); for (i = 0; i < op->archdata.num_irqs; i++) - op->archdata.irqs[i] = irq[i]; + op->archdata.irqs[i] = + sparc_irq_config.build_device_irq(op, irq[i]); } else { op->archdata.num_irqs = 0; } } - if (sparc_cpu_model == sun4d) { - static int pil_to_sbus[] = { - 0, 0, 1, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0, 0, - }; - struct device_node *io_unit, *sbi = dp->parent; - const struct linux_prom_registers *regs; - int board, slot; - - while (sbi) { - if (!strcmp(sbi->name, "sbi")) - break; - - sbi = sbi->parent; - } - if (!sbi) - goto build_resources; - - regs = of_get_property(dp, "reg", NULL); - if (!regs) - goto build_resources; - - slot = regs->which_io; - - /* If SBI's parent is not io-unit or the io-unit lacks - * a "board#" property, something is very wrong. - */ - if (!sbi->parent || strcmp(sbi->parent->name, "io-unit")) { - printk("%s: Error, parent is not io-unit.\n", - sbi->full_name); - goto build_resources; - } - io_unit = sbi->parent; - board = of_getintprop_default(io_unit, "board#", -1); - if (board == -1) { - printk("%s: Error, lacks board# property.\n", - io_unit->full_name); - goto build_resources; - } - - for (i = 0; i < op->archdata.num_irqs; i++) { - int this_irq = op->archdata.irqs[i]; - int sbusl = pil_to_sbus[this_irq]; - - if (sbusl) - this_irq = (((board + 1) << 5) + - (sbusl << 2) + - slot); - - op->archdata.irqs[i] = this_irq; - } - } -build_resources: build_device_resources(op, parent); op->dev.parent = parent; diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c index 4137579d9adc..44f41e312f73 100644 --- a/arch/sparc/kernel/pci.c +++ b/arch/sparc/kernel/pci.c @@ -675,6 +675,7 @@ static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus) * humanoid. */ err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr); + (void) err; } list_for_each_entry(child_bus, &bus->children, node) pci_bus_register_of_sysfs(child_bus); @@ -1001,22 +1002,22 @@ EXPORT_SYMBOL(pci_domain_nr); int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) { struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; - unsigned int virt_irq; + unsigned int irq; if (!pbm->setup_msi_irq) return -EINVAL; - return pbm->setup_msi_irq(&virt_irq, pdev, desc); + return pbm->setup_msi_irq(&irq, pdev, desc); } -void arch_teardown_msi_irq(unsigned int virt_irq) +void arch_teardown_msi_irq(unsigned int irq) { - struct msi_desc *entry = get_irq_msi(virt_irq); + struct msi_desc *entry = get_irq_msi(irq); struct pci_dev *pdev = entry->dev; struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; if (pbm->teardown_msi_irq) - pbm->teardown_msi_irq(virt_irq, pdev); + pbm->teardown_msi_irq(irq, pdev); } #endif /* !(CONFIG_PCI_MSI) */ diff --git a/arch/sparc/kernel/pci_common.c b/arch/sparc/kernel/pci_common.c index 6c7a33af3ba6..6e3874b64488 100644 --- a/arch/sparc/kernel/pci_common.c +++ b/arch/sparc/kernel/pci_common.c @@ -295,14 +295,17 @@ static int sun4v_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, unsigned int bus = bus_dev->number; unsigned int device = PCI_SLOT(devfn); unsigned int func = PCI_FUNC(devfn); - unsigned long ret; if (config_out_of_range(pbm, bus, devfn, where)) { /* Do nothing. */ } else { - ret = pci_sun4v_config_put(devhandle, - HV_PCI_DEVICE_BUILD(bus, device, func), - where, size, value); + /* We don't check for hypervisor errors here, but perhaps + * we should and influence our return value depending upon + * what kind of error is thrown. + */ + pci_sun4v_config_put(devhandle, + HV_PCI_DEVICE_BUILD(bus, device, func), + where, size, value); } return PCIBIOS_SUCCESSFUL; } diff --git a/arch/sparc/kernel/pci_fire.c b/arch/sparc/kernel/pci_fire.c index efb896d68754..3d70f8326efd 100644 --- a/arch/sparc/kernel/pci_fire.c +++ b/arch/sparc/kernel/pci_fire.c @@ -214,11 +214,9 @@ static int pci_fire_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid, static int pci_fire_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi) { - unsigned long msiqid; u64 val; val = upa_readq(pbm->pbm_regs + MSI_MAP(msi)); - msiqid = (val & MSI_MAP_EQNUM); val &= ~MSI_MAP_VALID; @@ -277,7 +275,7 @@ static int pci_fire_msiq_build_irq(struct pci_pbm_info *pbm, { unsigned long cregs = (unsigned long) pbm->pbm_regs; unsigned long imap_reg, iclr_reg, int_ctrlr; - unsigned int virt_irq; + unsigned int irq; int fixup; u64 val; @@ -293,14 +291,14 @@ static int pci_fire_msiq_build_irq(struct pci_pbm_info *pbm, fixup = ((pbm->portid << 6) | devino) - int_ctrlr; - virt_irq = build_irq(fixup, iclr_reg, imap_reg); - if (!virt_irq) + irq = build_irq(fixup, iclr_reg, imap_reg); + if (!irq) return -ENOMEM; upa_writeq(EVENT_QUEUE_CONTROL_SET_EN, pbm->pbm_regs + EVENT_QUEUE_CONTROL_SET(msiqid)); - return virt_irq; + return irq; } static const struct sparc64_msiq_ops pci_fire_msiq_ops = { @@ -455,8 +453,7 @@ static int __devinit pci_fire_pbm_init(struct pci_pbm_info *pbm, return 0; } -static int __devinit fire_probe(struct platform_device *op, - const struct of_device_id *match) +static int __devinit fire_probe(struct platform_device *op) { struct device_node *dp = op->dev.of_node; struct pci_pbm_info *pbm; @@ -507,7 +504,7 @@ static struct of_device_id __initdata fire_match[] = { {}, }; -static struct of_platform_driver fire_driver = { +static struct platform_driver fire_driver = { .driver = { .name = DRIVER_NAME, .owner = THIS_MODULE, @@ -518,7 +515,7 @@ static struct of_platform_driver fire_driver = { static int __init fire_init(void) { - return of_register_platform_driver(&fire_driver); + return platform_driver_register(&fire_driver); } subsys_initcall(fire_init); diff --git a/arch/sparc/kernel/pci_impl.h b/arch/sparc/kernel/pci_impl.h index e20ed5f06e9c..6beb60df31d0 100644 --- a/arch/sparc/kernel/pci_impl.h +++ b/arch/sparc/kernel/pci_impl.h @@ -131,9 +131,9 @@ struct pci_pbm_info { void *msi_queues; unsigned long *msi_bitmap; unsigned int *msi_irq_table; - int (*setup_msi_irq)(unsigned int *virt_irq_p, struct pci_dev *pdev, + int (*setup_msi_irq)(unsigned int *irq_p, struct pci_dev *pdev, struct msi_desc *entry); - void (*teardown_msi_irq)(unsigned int virt_irq, struct pci_dev *pdev); + void (*teardown_msi_irq)(unsigned int irq, struct pci_dev *pdev); const struct sparc64_msiq_ops *msi_ops; #endif /* !(CONFIG_PCI_MSI) */ diff --git a/arch/sparc/kernel/pci_msi.c b/arch/sparc/kernel/pci_msi.c index b210416ace7b..550e937720e7 100644 --- a/arch/sparc/kernel/pci_msi.c +++ b/arch/sparc/kernel/pci_msi.c @@ -31,12 +31,12 @@ static irqreturn_t sparc64_msiq_interrupt(int irq, void *cookie) err = ops->dequeue_msi(pbm, msiqid, &head, &msi); if (likely(err > 0)) { struct irq_desc *desc; - unsigned int virt_irq; + unsigned int irq; - virt_irq = pbm->msi_irq_table[msi - pbm->msi_first]; - desc = irq_desc + virt_irq; + irq = pbm->msi_irq_table[msi - pbm->msi_first]; + desc = irq_desc + irq; - desc->handle_irq(virt_irq, desc); + desc->handle_irq(irq, desc); } if (unlikely(err < 0)) @@ -121,7 +121,7 @@ static struct irq_chip msi_irq = { /* XXX affinity XXX */ }; -static int sparc64_setup_msi_irq(unsigned int *virt_irq_p, +static int sparc64_setup_msi_irq(unsigned int *irq_p, struct pci_dev *pdev, struct msi_desc *entry) { @@ -131,17 +131,17 @@ static int sparc64_setup_msi_irq(unsigned int *virt_irq_p, int msi, err; u32 msiqid; - *virt_irq_p = virt_irq_alloc(0, 0); + *irq_p = irq_alloc(0, 0); err = -ENOMEM; - if (!*virt_irq_p) + if (!*irq_p) goto out_err; - set_irq_chip_and_handler_name(*virt_irq_p, &msi_irq, + set_irq_chip_and_handler_name(*irq_p, &msi_irq, handle_simple_irq, "MSI"); err = alloc_msi(pbm); if (unlikely(err < 0)) - goto out_virt_irq_free; + goto out_irq_free; msi = err; @@ -152,7 +152,7 @@ static int sparc64_setup_msi_irq(unsigned int *virt_irq_p, if (err) goto out_msi_free; - pbm->msi_irq_table[msi - pbm->msi_first] = *virt_irq_p; + pbm->msi_irq_table[msi - pbm->msi_first] = *irq_p; if (entry->msi_attrib.is_64) { msg.address_hi = pbm->msi64_start >> 32; @@ -163,24 +163,24 @@ static int sparc64_setup_msi_irq(unsigned int *virt_irq_p, } msg.data = msi; - set_irq_msi(*virt_irq_p, entry); - write_msi_msg(*virt_irq_p, &msg); + set_irq_msi(*irq_p, entry); + write_msi_msg(*irq_p, &msg); return 0; out_msi_free: free_msi(pbm, msi); -out_virt_irq_free: - set_irq_chip(*virt_irq_p, NULL); - virt_irq_free(*virt_irq_p); - *virt_irq_p = 0; +out_irq_free: + set_irq_chip(*irq_p, NULL); + irq_free(*irq_p); + *irq_p = 0; out_err: return err; } -static void sparc64_teardown_msi_irq(unsigned int virt_irq, +static void sparc64_teardown_msi_irq(unsigned int irq, struct pci_dev *pdev) { struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; @@ -189,12 +189,12 @@ static void sparc64_teardown_msi_irq(unsigned int virt_irq, int i, err; for (i = 0; i < pbm->msi_num; i++) { - if (pbm->msi_irq_table[i] == virt_irq) + if (pbm->msi_irq_table[i] == irq) break; } if (i >= pbm->msi_num) { printk(KERN_ERR "%s: teardown: No MSI for irq %u\n", - pbm->name, virt_irq); + pbm->name, irq); return; } @@ -205,14 +205,14 @@ static void sparc64_teardown_msi_irq(unsigned int virt_irq, if (err) { printk(KERN_ERR "%s: teardown: ops->teardown() on MSI %u, " "irq %u, gives error %d\n", - pbm->name, msi_num, virt_irq, err); + pbm->name, msi_num, irq, err); return; } free_msi(pbm, msi_num); - set_irq_chip(virt_irq, NULL); - virt_irq_free(virt_irq); + set_irq_chip(irq, NULL); + irq_free(irq); } static int msi_bitmap_alloc(struct pci_pbm_info *pbm) diff --git a/arch/sparc/kernel/pci_psycho.c b/arch/sparc/kernel/pci_psycho.c index 22eab7cf3b11..56ee745064de 100644 --- a/arch/sparc/kernel/pci_psycho.c +++ b/arch/sparc/kernel/pci_psycho.c @@ -503,8 +503,7 @@ static struct pci_pbm_info * __devinit psycho_find_sibling(u32 upa_portid) #define PSYCHO_CONFIGSPACE 0x001000000UL -static int __devinit psycho_probe(struct platform_device *op, - const struct of_device_id *match) +static int __devinit psycho_probe(struct platform_device *op) { const struct linux_prom64_registers *pr_regs; struct device_node *dp = op->dev.of_node; @@ -601,7 +600,7 @@ static struct of_device_id __initdata psycho_match[] = { {}, }; -static struct of_platform_driver psycho_driver = { +static struct platform_driver psycho_driver = { .driver = { .name = DRIVER_NAME, .owner = THIS_MODULE, @@ -612,7 +611,7 @@ static struct of_platform_driver psycho_driver = { static int __init psycho_init(void) { - return of_register_platform_driver(&psycho_driver); + return platform_driver_register(&psycho_driver); } subsys_initcall(psycho_init); diff --git a/arch/sparc/kernel/pci_sabre.c b/arch/sparc/kernel/pci_sabre.c index 5c3f5ec4cabc..2857073342d2 100644 --- a/arch/sparc/kernel/pci_sabre.c +++ b/arch/sparc/kernel/pci_sabre.c @@ -452,8 +452,7 @@ static void __devinit sabre_pbm_init(struct pci_pbm_info *pbm, sabre_scan_bus(pbm, &op->dev); } -static int __devinit sabre_probe(struct platform_device *op, - const struct of_device_id *match) +static int __devinit sabre_probe(struct platform_device *op) { const struct linux_prom64_registers *pr_regs; struct device_node *dp = op->dev.of_node; @@ -464,7 +463,7 @@ static int __devinit sabre_probe(struct platform_device *op, const u32 *vdma; u64 clear_irq; - hummingbird_p = (match->data != NULL); + hummingbird_p = op->dev.of_match && (op->dev.of_match->data != NULL); if (!hummingbird_p) { struct device_node *cpu_dp; @@ -595,7 +594,7 @@ static struct of_device_id __initdata sabre_match[] = { {}, }; -static struct of_platform_driver sabre_driver = { +static struct platform_driver sabre_driver = { .driver = { .name = DRIVER_NAME, .owner = THIS_MODULE, @@ -606,7 +605,7 @@ static struct of_platform_driver sabre_driver = { static int __init sabre_init(void) { - return of_register_platform_driver(&sabre_driver); + return platform_driver_register(&sabre_driver); } subsys_initcall(sabre_init); diff --git a/arch/sparc/kernel/pci_schizo.c b/arch/sparc/kernel/pci_schizo.c index 445a47a2fb3d..1d41af73a92f 100644 --- a/arch/sparc/kernel/pci_schizo.c +++ b/arch/sparc/kernel/pci_schizo.c @@ -1313,7 +1313,7 @@ static int __devinit schizo_pbm_init(struct pci_pbm_info *pbm, const struct linux_prom64_registers *regs; struct device_node *dp = op->dev.of_node; const char *chipset_name; - int is_pbm_a, err; + int err; switch (chip_type) { case PBM_CHIP_TYPE_TOMATILLO: @@ -1343,8 +1343,6 @@ static int __devinit schizo_pbm_init(struct pci_pbm_info *pbm, */ regs = of_get_property(dp, "reg", NULL); - is_pbm_a = ((regs[0].phys_addr & 0x00700000) == 0x00600000); - pbm->next = pci_pbm_root; pci_pbm_root = pbm; @@ -1460,10 +1458,11 @@ out_err: return err; } -static int __devinit schizo_probe(struct platform_device *op, - const struct of_device_id *match) +static int __devinit schizo_probe(struct platform_device *op) { - return __schizo_init(op, (unsigned long) match->data); + if (!op->dev.of_match) + return -EINVAL; + return __schizo_init(op, (unsigned long) op->dev.of_match->data); } /* The ordering of this table is very important. Some Tomatillo @@ -1490,7 +1489,7 @@ static struct of_device_id __initdata schizo_match[] = { {}, }; -static struct of_platform_driver schizo_driver = { +static struct platform_driver schizo_driver = { .driver = { .name = DRIVER_NAME, .owner = THIS_MODULE, @@ -1501,7 +1500,7 @@ static struct of_platform_driver schizo_driver = { static int __init schizo_init(void) { - return of_register_platform_driver(&schizo_driver); + return platform_driver_register(&schizo_driver); } subsys_initcall(schizo_init); diff --git a/arch/sparc/kernel/pci_sun4v.c b/arch/sparc/kernel/pci_sun4v.c index 743344aa6d8a..6cf534681788 100644 --- a/arch/sparc/kernel/pci_sun4v.c +++ b/arch/sparc/kernel/pci_sun4v.c @@ -580,7 +580,7 @@ static int __devinit pci_sun4v_iommu_init(struct pci_pbm_info *pbm) { static const u32 vdma_default[] = { 0x80000000, 0x80000000 }; struct iommu *iommu = pbm->iommu; - unsigned long num_tsb_entries, sz, tsbsize; + unsigned long num_tsb_entries, sz; u32 dma_mask, dma_offset; const u32 *vdma; @@ -596,7 +596,6 @@ static int __devinit pci_sun4v_iommu_init(struct pci_pbm_info *pbm) dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL); num_tsb_entries = vdma[1] / IO_PAGE_SIZE; - tsbsize = num_tsb_entries * sizeof(iopte_t); dma_offset = vdma[0]; @@ -844,9 +843,9 @@ static int pci_sun4v_msiq_build_irq(struct pci_pbm_info *pbm, unsigned long msiqid, unsigned long devino) { - unsigned int virt_irq = sun4v_build_irq(pbm->devhandle, devino); + unsigned int irq = sun4v_build_irq(pbm->devhandle, devino); - if (!virt_irq) + if (!irq) return -ENOMEM; if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE)) @@ -854,7 +853,7 @@ static int pci_sun4v_msiq_build_irq(struct pci_pbm_info *pbm, if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID)) return -EINVAL; - return virt_irq; + return irq; } static const struct sparc64_msiq_ops pci_sun4v_msiq_ops = { @@ -918,8 +917,7 @@ static int __devinit pci_sun4v_pbm_init(struct pci_pbm_info *pbm, return 0; } -static int __devinit pci_sun4v_probe(struct platform_device *op, - const struct of_device_id *match) +static int __devinit pci_sun4v_probe(struct platform_device *op) { const struct linux_prom64_registers *regs; static int hvapi_negotiated = 0; @@ -1008,7 +1006,7 @@ static struct of_device_id __initdata pci_sun4v_match[] = { {}, }; -static struct of_platform_driver pci_sun4v_driver = { +static struct platform_driver pci_sun4v_driver = { .driver = { .name = DRIVER_NAME, .owner = THIS_MODULE, @@ -1019,7 +1017,7 @@ static struct of_platform_driver pci_sun4v_driver = { static int __init pci_sun4v_init(void) { - return of_register_platform_driver(&pci_sun4v_driver); + return platform_driver_register(&pci_sun4v_driver); } subsys_initcall(pci_sun4v_init); diff --git a/arch/sparc/kernel/pcic.c b/arch/sparc/kernel/pcic.c index aeaa09a3c655..2cdc131b50ac 100644 --- a/arch/sparc/kernel/pcic.c +++ b/arch/sparc/kernel/pcic.c @@ -700,10 +700,8 @@ static void pcic_clear_clock_irq(void) static irqreturn_t pcic_timer_handler (int irq, void *h) { - write_seqlock(&xtime_lock); /* Dummy, to show that we remember */ pcic_clear_clock_irq(); - do_timer(1); - write_sequnlock(&xtime_lock); + xtime_update(1); #ifndef CONFIG_SMP update_process_times(user_mode(get_irq_regs())); #endif diff --git a/arch/sparc/kernel/pcr.c b/arch/sparc/kernel/pcr.c index 7c2ced612b8f..8ac23e660080 100644 --- a/arch/sparc/kernel/pcr.c +++ b/arch/sparc/kernel/pcr.c @@ -81,7 +81,7 @@ static void n2_pcr_write(u64 val) unsigned long ret; ret = sun4v_niagara2_setperf(HV_N2_PERF_SPARC_CTL, val); - if (val != HV_EOK) + if (ret != HV_EOK) write_pcr(val); } diff --git a/arch/sparc/kernel/pmc.c b/arch/sparc/kernel/pmc.c index 94536a85f161..93d7b4465f8d 100644 --- a/arch/sparc/kernel/pmc.c +++ b/arch/sparc/kernel/pmc.c @@ -51,8 +51,7 @@ static void pmc_swift_idle(void) #endif } -static int __devinit pmc_probe(struct platform_device *op, - const struct of_device_id *match) +static int __devinit pmc_probe(struct platform_device *op) { regs = of_ioremap(&op->resource[0], 0, resource_size(&op->resource[0]), PMC_OBPNAME); @@ -78,7 +77,7 @@ static struct of_device_id __initdata pmc_match[] = { }; MODULE_DEVICE_TABLE(of, pmc_match); -static struct of_platform_driver pmc_driver = { +static struct platform_driver pmc_driver = { .driver = { .name = "pmc", .owner = THIS_MODULE, @@ -89,7 +88,7 @@ static struct of_platform_driver pmc_driver = { static int __init pmc_init(void) { - return of_register_platform_driver(&pmc_driver); + return platform_driver_register(&pmc_driver); } /* This driver is not critical to the boot process diff --git a/arch/sparc/kernel/power.c b/arch/sparc/kernel/power.c index 2c59f4d387dd..cd725fe238b2 100644 --- a/arch/sparc/kernel/power.c +++ b/arch/sparc/kernel/power.c @@ -33,7 +33,7 @@ static int __devinit has_button_interrupt(unsigned int irq, struct device_node * return 1; } -static int __devinit power_probe(struct platform_device *op, const struct of_device_id *match) +static int __devinit power_probe(struct platform_device *op) { struct resource *res = &op->resource[0]; unsigned int irq = op->archdata.irqs[0]; @@ -59,7 +59,7 @@ static struct of_device_id __initdata power_match[] = { {}, }; -static struct of_platform_driver power_driver = { +static struct platform_driver power_driver = { .probe = power_probe, .driver = { .name = "power", @@ -70,7 +70,7 @@ static struct of_platform_driver power_driver = { static int __init power_init(void) { - return of_register_platform_driver(&power_driver); + return platform_driver_register(&power_driver); } device_initcall(power_init); diff --git a/arch/sparc/kernel/prom_irqtrans.c b/arch/sparc/kernel/prom_irqtrans.c index ce651147fabc..570b98f6e897 100644 --- a/arch/sparc/kernel/prom_irqtrans.c +++ b/arch/sparc/kernel/prom_irqtrans.c @@ -227,7 +227,7 @@ static unsigned int sabre_irq_build(struct device_node *dp, unsigned long imap, iclr; unsigned long imap_off, iclr_off; int inofixup = 0; - int virt_irq; + int irq; ino &= 0x3f; if (ino < SABRE_ONBOARD_IRQ_BASE) { @@ -247,7 +247,7 @@ static unsigned int sabre_irq_build(struct device_node *dp, if ((ino & 0x20) == 0) inofixup = ino & 0x03; - virt_irq = build_irq(inofixup, iclr, imap); + irq = build_irq(inofixup, iclr, imap); /* If the parent device is a PCI<->PCI bridge other than * APB, we have to install a pre-handler to ensure that @@ -256,13 +256,13 @@ static unsigned int sabre_irq_build(struct device_node *dp, */ regs = of_get_property(dp, "reg", NULL); if (regs && sabre_device_needs_wsync(dp)) { - irq_install_pre_handler(virt_irq, + irq_install_pre_handler(irq, sabre_wsync_handler, (void *) (long) regs->phys_hi, (void *) irq_data); } - return virt_irq; + return irq; } static void __init sabre_irq_trans_init(struct device_node *dp) @@ -382,7 +382,7 @@ static unsigned int schizo_irq_build(struct device_node *dp, unsigned long pbm_regs = irq_data->pbm_regs; unsigned long imap, iclr; int ign_fixup; - int virt_irq; + int irq; int is_tomatillo; ino &= 0x3f; @@ -409,17 +409,17 @@ static unsigned int schizo_irq_build(struct device_node *dp, ign_fixup = (1 << 6); } - virt_irq = build_irq(ign_fixup, iclr, imap); + irq = build_irq(ign_fixup, iclr, imap); if (is_tomatillo) { - irq_install_pre_handler(virt_irq, + irq_install_pre_handler(irq, tomatillo_wsync_handler, ((irq_data->chip_version <= 4) ? (void *) 1 : (void *) 0), (void *) irq_data->sync_reg); } - return virt_irq; + return irq; } static void __init __schizo_irq_trans_init(struct device_node *dp, diff --git a/arch/sparc/kernel/ptrace_64.c b/arch/sparc/kernel/ptrace_64.c index 9ccc812bc09e..96ee50a80661 100644 --- a/arch/sparc/kernel/ptrace_64.c +++ b/arch/sparc/kernel/ptrace_64.c @@ -1086,6 +1086,7 @@ asmlinkage int syscall_trace_enter(struct pt_regs *regs) asmlinkage void syscall_trace_leave(struct pt_regs *regs) { +#ifdef CONFIG_AUDITSYSCALL if (unlikely(current->audit_context)) { unsigned long tstate = regs->tstate; int result = AUDITSC_SUCCESS; @@ -1095,7 +1096,7 @@ asmlinkage void syscall_trace_leave(struct pt_regs *regs) audit_syscall_exit(result, regs->u_regs[UREG_I0]); } - +#endif if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) trace_sys_exit(regs, regs->u_regs[UREG_G1]); diff --git a/arch/sparc/kernel/setup_32.c b/arch/sparc/kernel/setup_32.c index 648f2161b851..7b8b76c9557f 100644 --- a/arch/sparc/kernel/setup_32.c +++ b/arch/sparc/kernel/setup_32.c @@ -184,7 +184,6 @@ static void __init boot_flags_init(char *commands) */ extern void sun4c_probe_vac(void); -extern char cputypval; extern unsigned short root_flags; extern unsigned short root_dev; @@ -218,21 +217,21 @@ void __init setup_arch(char **cmdline_p) /* Set sparc_cpu_model */ sparc_cpu_model = sun_unknown; - if (!strcmp(&cputypval,"sun4 ")) + if (!strcmp(&cputypval[0], "sun4 ")) sparc_cpu_model = sun4; - if (!strcmp(&cputypval,"sun4c")) + if (!strcmp(&cputypval[0], "sun4c")) sparc_cpu_model = sun4c; - if (!strcmp(&cputypval,"sun4m")) + if (!strcmp(&cputypval[0], "sun4m")) sparc_cpu_model = sun4m; - if (!strcmp(&cputypval,"sun4s")) + if (!strcmp(&cputypval[0], "sun4s")) sparc_cpu_model = sun4m; /* CP-1200 with PROM 2.30 -E */ - if (!strcmp(&cputypval,"sun4d")) + if (!strcmp(&cputypval[0], "sun4d")) sparc_cpu_model = sun4d; - if (!strcmp(&cputypval,"sun4e")) + if (!strcmp(&cputypval[0], "sun4e")) sparc_cpu_model = sun4e; - if (!strcmp(&cputypval,"sun4u")) + if (!strcmp(&cputypval[0], "sun4u")) sparc_cpu_model = sun4u; - if (!strncmp(&cputypval, "leon" , 4)) + if (!strncmp(&cputypval[0], "leon" , 4)) sparc_cpu_model = sparc_leon; printk("ARCH: "); @@ -335,7 +334,7 @@ static int show_cpuinfo(struct seq_file *m, void *__unused) prom_rev, romvec->pv_printrev >> 16, romvec->pv_printrev & 0xffff, - &cputypval, + &cputypval[0], ncpus_probed, num_online_cpus() #ifndef CONFIG_SMP diff --git a/arch/sparc/kernel/smp_64.c b/arch/sparc/kernel/smp_64.c index 555a76d1f4a1..3e94a8c23238 100644 --- a/arch/sparc/kernel/smp_64.c +++ b/arch/sparc/kernel/smp_64.c @@ -189,7 +189,7 @@ static inline long get_delta (long *rt, long *master) void smp_synchronize_tick_client(void) { long i, delta, adj, adjust_latency = 0, done = 0; - unsigned long flags, rt, master_time_stamp, bound; + unsigned long flags, rt, master_time_stamp; #if DEBUG_TICK_SYNC struct { long rt; /* roundtrip time */ @@ -208,10 +208,8 @@ void smp_synchronize_tick_client(void) { for (i = 0; i < NUM_ROUNDS; i++) { delta = get_delta(&rt, &master_time_stamp); - if (delta == 0) { + if (delta == 0) done = 1; /* let's lock on to this... */ - bound = rt; - } if (!done) { if (i > 0) { @@ -933,13 +931,12 @@ void smp_flush_dcache_page_impl(struct page *page, int cpu) void flush_dcache_page_all(struct mm_struct *mm, struct page *page) { void *pg_addr; - int this_cpu; u64 data0; if (tlb_type == hypervisor) return; - this_cpu = get_cpu(); + preempt_disable(); #ifdef CONFIG_DEBUG_DCFLUSH atomic_inc(&dcpage_flushes); @@ -964,7 +961,7 @@ void flush_dcache_page_all(struct mm_struct *mm, struct page *page) } __local_flush_dcache_page(page); - put_cpu(); + preempt_enable(); } void __irq_entry smp_new_mmu_context_version_client(int irq, struct pt_regs *regs) diff --git a/arch/sparc/kernel/sun4c_irq.c b/arch/sparc/kernel/sun4c_irq.c index 892fb884910a..90eea38ad66f 100644 --- a/arch/sparc/kernel/sun4c_irq.c +++ b/arch/sparc/kernel/sun4c_irq.c @@ -1,5 +1,5 @@ -/* sun4c_irq.c - * arch/sparc/kernel/sun4c_irq.c: +/* + * sun4c irq support * * djhr: Hacked out of irq.c into a CPU dependent version. * @@ -9,31 +9,41 @@ * Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk) */ -#include <linux/errno.h> -#include <linux/linkage.h> -#include <linux/kernel_stat.h> -#include <linux/signal.h> -#include <linux/sched.h> -#include <linux/ptrace.h> -#include <linux/interrupt.h> #include <linux/init.h> -#include <linux/of.h> -#include <linux/of_device.h> -#include "irq.h" -#include <asm/ptrace.h> -#include <asm/processor.h> -#include <asm/system.h> -#include <asm/psr.h> -#include <asm/vaddrs.h> -#include <asm/timer.h> -#include <asm/openprom.h> #include <asm/oplib.h> -#include <asm/traps.h> +#include <asm/timer.h> #include <asm/irq.h> #include <asm/io.h> -#include <asm/idprom.h> -#include <asm/machines.h> + +#include "irq.h" + +/* Sun4c interrupts are typically laid out as follows: + * + * 1 - Software interrupt, SBUS level 1 + * 2 - SBUS level 2 + * 3 - ESP SCSI, SBUS level 3 + * 4 - Software interrupt + * 5 - Lance ethernet, SBUS level 4 + * 6 - Software interrupt + * 7 - Graphics card, SBUS level 5 + * 8 - SBUS level 6 + * 9 - SBUS level 7 + * 10 - Counter timer + * 11 - Floppy + * 12 - Zilog uart + * 13 - CS4231 audio + * 14 - Profiling timer + * 15 - NMI + * + * The interrupt enable bits in the interrupt mask register are + * really only used to enable/disable the timer interrupts, and + * for signalling software interrupts. There is also a master + * interrupt enable bit in this register. + * + * Interrupts are enabled by setting the SUN4C_INT_* bits, they + * are disabled by clearing those bits. + */ /* * Bit field defines for the interrupt registers on various @@ -49,26 +59,21 @@ #define SUN4C_INT_E4 0x04 /* Enable level 4 IRQ. */ #define SUN4C_INT_E1 0x02 /* Enable level 1 IRQ. */ -/* Pointer to the interrupt enable byte - * - * Dave Redman (djhr@tadpole.co.uk) - * What you may not be aware of is that entry.S requires this variable. - * - * --- linux_trap_nmi_sun4c -- - * - * so don't go making it static, like I tried. sigh. +/* + * Pointer to the interrupt enable byte + * Used by entry.S */ -unsigned char __iomem *interrupt_enable = NULL; +unsigned char __iomem *interrupt_enable; static void sun4c_disable_irq(unsigned int irq_nr) { unsigned long flags; unsigned char current_mask, new_mask; - + local_irq_save(flags); irq_nr &= (NR_IRQS - 1); current_mask = sbus_readb(interrupt_enable); - switch(irq_nr) { + switch (irq_nr) { case 1: new_mask = ((current_mask) & (~(SUN4C_INT_E1))); break; @@ -93,11 +98,11 @@ static void sun4c_enable_irq(unsigned int irq_nr) { unsigned long flags; unsigned char current_mask, new_mask; - + local_irq_save(flags); irq_nr &= (NR_IRQS - 1); current_mask = sbus_readb(interrupt_enable); - switch(irq_nr) { + switch (irq_nr) { case 1: new_mask = ((current_mask) | SUN4C_INT_E1); break; @@ -180,12 +185,14 @@ static void __init sun4c_init_timers(irq_handler_t counter_fn) prom_printf("sun4c_init_timers: request_irq() fails with %d\n", err); prom_halt(); } - + sun4c_disable_irq(irq[1].pri); } #ifdef CONFIG_SMP -static void sun4c_nop(void) {} +static void sun4c_nop(void) +{ +} #endif void __init sun4c_init_IRQ(void) @@ -214,7 +221,9 @@ void __init sun4c_init_IRQ(void) BTFIXUPSET_CALL(disable_pil_irq, sun4c_disable_irq, BTFIXUPCALL_NORM); BTFIXUPSET_CALL(clear_clock_irq, sun4c_clear_clock_irq, BTFIXUPCALL_NORM); BTFIXUPSET_CALL(load_profile_irq, sun4c_load_profile_irq, BTFIXUPCALL_NOP); - sparc_init_timers = sun4c_init_timers; + + sparc_irq_config.init_timers = sun4c_init_timers; + #ifdef CONFIG_SMP BTFIXUPSET_CALL(set_cpu_int, sun4c_nop, BTFIXUPCALL_NOP); BTFIXUPSET_CALL(clear_cpu_int, sun4c_nop, BTFIXUPCALL_NOP); diff --git a/arch/sparc/kernel/sun4d_irq.c b/arch/sparc/kernel/sun4d_irq.c index e11b4612dabb..77b4a8992710 100644 --- a/arch/sparc/kernel/sun4d_irq.c +++ b/arch/sparc/kernel/sun4d_irq.c @@ -1,50 +1,42 @@ /* - * arch/sparc/kernel/sun4d_irq.c: - * SS1000/SC2000 interrupt handling. + * SS1000/SC2000 interrupt handling. * * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) * Heavily based on arch/sparc/kernel/irq.c. */ -#include <linux/errno.h> -#include <linux/linkage.h> #include <linux/kernel_stat.h> -#include <linux/signal.h> -#include <linux/sched.h> -#include <linux/ptrace.h> -#include <linux/interrupt.h> -#include <linux/slab.h> -#include <linux/random.h> -#include <linux/init.h> -#include <linux/smp.h> -#include <linux/spinlock.h> #include <linux/seq_file.h> -#include <linux/of.h> -#include <linux/of_device.h> - -#include <asm/ptrace.h> -#include <asm/processor.h> -#include <asm/system.h> -#include <asm/psr.h> -#include <asm/smp.h> -#include <asm/vaddrs.h> + #include <asm/timer.h> -#include <asm/openprom.h> -#include <asm/oplib.h> #include <asm/traps.h> #include <asm/irq.h> #include <asm/io.h> -#include <asm/pgalloc.h> -#include <asm/pgtable.h> #include <asm/sbi.h> #include <asm/cacheflush.h> -#include <asm/irq_regs.h> #include "kernel.h" #include "irq.h" -/* If you trust current SCSI layer to handle different SCSI IRQs, enable this. I don't trust it... -jj */ -/* #define DISTRIBUTE_IRQS */ +/* Sun4d interrupts fall roughly into two categories. SBUS and + * cpu local. CPU local interrupts cover the timer interrupts + * and whatnot, and we encode those as normal PILs between + * 0 and 15. + * + * SBUS interrupts are encoded integers including the board number + * (plus one), the SBUS level, and the SBUS slot number. Sun4D + * IRQ dispatch is done by: + * + * 1) Reading the BW local interrupt table in order to get the bus + * interrupt mask. + * + * This table is indexed by SBUS interrupt level which can be + * derived from the PIL we got interrupted on. + * + * 2) For each bus showing interrupt pending from #1, read the + * SBI interrupt state register. This will indicate which slots + * have interrupts pending for that SBUS interrupt level. + */ struct sun4d_timer_regs { u32 l10_timer_limit; @@ -59,11 +51,9 @@ static struct sun4d_timer_regs __iomem *sun4d_timers; #define TIMER_IRQ 10 #define MAX_STATIC_ALLOC 4 -extern int static_irq_count; static unsigned char sbus_tid[32]; static struct irqaction *irq_action[NR_IRQS]; -extern spinlock_t irq_action_lock; static struct sbus_action { struct irqaction *action; @@ -71,11 +61,33 @@ static struct sbus_action { } *sbus_actions; static int pil_to_sbus[] = { - 0, 0, 1, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0, 0, + 0, + 0, + 1, + 2, + 0, + 3, + 0, + 4, + 0, + 5, + 0, + 6, + 0, + 7, + 0, + 0, }; static int sbus_to_pil[] = { - 0, 2, 3, 5, 7, 9, 11, 13, + 0, + 2, + 3, + 5, + 7, + 9, + 11, + 13, }; static int nsbi; @@ -86,7 +98,7 @@ DEFINE_SPINLOCK(sun4d_imsk_lock); int show_sun4d_interrupts(struct seq_file *p, void *v) { int i = *(loff_t *) v, j = 0, k = 0, sbusl; - struct irqaction * action; + struct irqaction *action; unsigned long flags; #ifdef CONFIG_SMP int x; @@ -96,13 +108,14 @@ int show_sun4d_interrupts(struct seq_file *p, void *v) if (i < NR_IRQS) { sbusl = pil_to_sbus[i]; if (!sbusl) { - action = *(i + irq_action); - if (!action) - goto out_unlock; + action = *(i + irq_action); + if (!action) + goto out_unlock; } else { for (j = 0; j < nsbi; j++) { for (k = 0; k < 4; k++) - if ((action = sbus_actions [(j << 5) + (sbusl << 2) + k].action)) + action = sbus_actions[(j << 5) + (sbusl << 2) + k].action; + if (action) goto found_it; } goto out_unlock; @@ -125,15 +138,17 @@ found_it: seq_printf(p, "%3d: ", i); (action->flags & IRQF_DISABLED) ? " +" : "", action->name); } - if (!sbusl) break; + if (!sbusl) + break; k++; - if (k < 4) - action = sbus_actions [(j << 5) + (sbusl << 2) + k].action; - else { + if (k < 4) { + action = sbus_actions[(j << 5) + (sbusl << 2) + k].action; + } else { j++; - if (j == nsbi) break; + if (j == nsbi) + break; k = 0; - action = sbus_actions [(j << 5) + (sbusl << 2)].action; + action = sbus_actions[(j << 5) + (sbusl << 2)].action; } } seq_putc(p, '\n'); @@ -147,7 +162,7 @@ void sun4d_free_irq(unsigned int irq, void *dev_id) { struct irqaction *action, **actionp; struct irqaction *tmp = NULL; - unsigned long flags; + unsigned long flags; spin_lock_irqsave(&irq_action_lock, flags); if (irq < 15) @@ -156,7 +171,7 @@ void sun4d_free_irq(unsigned int irq, void *dev_id) actionp = &(sbus_actions[irq - (1 << 5)].action); action = *actionp; if (!action) { - printk("Trying to free free IRQ%d\n",irq); + printk(KERN_ERR "Trying to free free IRQ%d\n", irq); goto out_unlock; } if (dev_id) { @@ -166,23 +181,25 @@ void sun4d_free_irq(unsigned int irq, void *dev_id) tmp = action; } if (!action) { - printk("Trying to free free shared IRQ%d\n",irq); + printk(KERN_ERR "Trying to free free shared IRQ%d\n", + irq); goto out_unlock; } } else if (action->flags & IRQF_SHARED) { - printk("Trying to free shared IRQ%d with NULL device ID\n", irq); + printk(KERN_ERR "Trying to free shared IRQ%d with NULL device ID\n", + irq); goto out_unlock; } - if (action->flags & SA_STATIC_ALLOC) - { - /* This interrupt is marked as specially allocated + if (action->flags & SA_STATIC_ALLOC) { + /* + * This interrupt is marked as specially allocated * so it is a bad idea to free it. */ - printk("Attempt to free statically allocated IRQ%d (%s)\n", + printk(KERN_ERR "Attempt to free statically allocated IRQ%d (%s)\n", irq, action->name); goto out_unlock; } - + if (tmp) tmp->next = action->next; else @@ -203,30 +220,28 @@ out_unlock: spin_unlock_irqrestore(&irq_action_lock, flags); } -extern void unexpected_irq(int, void *, struct pt_regs *); - -void sun4d_handler_irq(int irq, struct pt_regs * regs) +void sun4d_handler_irq(int pil, struct pt_regs *regs) { struct pt_regs *old_regs; - struct irqaction * action; + struct irqaction *action; int cpu = smp_processor_id(); /* SBUS IRQ level (1 - 7) */ - int sbusl = pil_to_sbus[irq]; - + int sbusl = pil_to_sbus[pil]; + /* FIXME: Is this necessary?? */ cc_get_ipen(); - - cc_set_iclr(1 << irq); - + + cc_set_iclr(1 << pil); + old_regs = set_irq_regs(regs); irq_enter(); - kstat_cpu(cpu).irqs[irq]++; + kstat_cpu(cpu).irqs[pil]++; if (!sbusl) { - action = *(irq + irq_action); + action = *(pil + irq_action); if (!action) - unexpected_irq(irq, NULL, regs); + unexpected_irq(pil, NULL, regs); do { - action->handler(irq, action->dev_id); + action->handler(pil, action->dev_id); action = action->next; } while (action); } else { @@ -235,9 +250,9 @@ void sun4d_handler_irq(int irq, struct pt_regs * regs) struct sbus_action *actionp; unsigned mask, slot; int sbil = (sbusl << 2); - + bw_clear_intr_mask(sbusl, bus_mask); - + /* Loop for each pending SBI */ for (sbino = 0; bus_mask; sbino++, bus_mask >>= 1) if (bus_mask & 1) { @@ -249,11 +264,11 @@ void sun4d_handler_irq(int irq, struct pt_regs * regs) if (mask & slot) { mask &= ~slot; action = actionp->action; - + if (!action) - unexpected_irq(irq, NULL, regs); + unexpected_irq(pil, NULL, regs); do { - action->handler(irq, action->dev_id); + action->handler(pil, action->dev_id); action = action->next; } while (action); release_sbi(SBI2DEVID(sbino), slot); @@ -266,13 +281,13 @@ void sun4d_handler_irq(int irq, struct pt_regs * regs) int sun4d_request_irq(unsigned int irq, irq_handler_t handler, - unsigned long irqflags, const char * devname, void *dev_id) + unsigned long irqflags, const char *devname, void *dev_id) { struct irqaction *action, *tmp = NULL, **actionp; unsigned long flags; int ret; - - if(irq > 14 && irq < (1 << 5)) { + + if (irq > 14 && irq < (1 << 5)) { ret = -EINVAL; goto out; } @@ -289,16 +304,18 @@ int sun4d_request_irq(unsigned int irq, else actionp = irq + irq_action; action = *actionp; - + if (action) { if ((action->flags & IRQF_SHARED) && (irqflags & IRQF_SHARED)) { - for (tmp = action; tmp->next; tmp = tmp->next); + for (tmp = action; tmp->next; tmp = tmp->next) + /* find last entry - tmp used below */; } else { ret = -EBUSY; goto out_unlock; } if ((action->flags & IRQF_DISABLED) ^ (irqflags & IRQF_DISABLED)) { - printk("Attempt to mix fast and slow interrupts on IRQ%d denied\n", irq); + printk(KERN_ERR "Attempt to mix fast and slow interrupts on IRQ%d denied\n", + irq); ret = -EBUSY; goto out_unlock; } @@ -312,14 +329,14 @@ int sun4d_request_irq(unsigned int irq, if (static_irq_count < MAX_STATIC_ALLOC) action = &static_irqaction[static_irq_count++]; else - printk("Request for IRQ%d (%s) SA_STATIC_ALLOC failed using kmalloc\n", irq, devname); + printk(KERN_ERR "Request for IRQ%d (%s) SA_STATIC_ALLOC failed using kmalloc\n", + irq, devname); } - + if (action == NULL) - action = kmalloc(sizeof(struct irqaction), - GFP_ATOMIC); - - if (!action) { + action = kmalloc(sizeof(struct irqaction), GFP_ATOMIC); + + if (!action) { ret = -ENOMEM; goto out_unlock; } @@ -334,7 +351,7 @@ int sun4d_request_irq(unsigned int irq, tmp->next = action; else *actionp = action; - + __enable_irq(irq); ret = 0; @@ -348,7 +365,7 @@ static void sun4d_disable_irq(unsigned int irq) { int tid = sbus_tid[(irq >> 5) - 1]; unsigned long flags; - + if (irq < NR_IRQS) return; @@ -361,7 +378,7 @@ static void sun4d_enable_irq(unsigned int irq) { int tid = sbus_tid[(irq >> 5) - 1]; unsigned long flags; - + if (irq < NR_IRQS) return; @@ -389,44 +406,6 @@ void __init sun4d_distribute_irqs(void) { struct device_node *dp; -#ifdef DISTRIBUTE_IRQS - cpumask_t sbus_serving_map; - - sbus_serving_map = cpu_present_map; - for_each_node_by_name(dp, "sbi") { - int board = of_getintprop_default(dp, "board#", 0); - - if ((board * 2) == boot_cpu_id && cpu_isset(board * 2 + 1, cpu_present_map)) - sbus_tid[board] = (board * 2 + 1); - else if (cpu_isset(board * 2, cpu_present_map)) - sbus_tid[board] = (board * 2); - else if (cpu_isset(board * 2 + 1, cpu_present_map)) - sbus_tid[board] = (board * 2 + 1); - else - sbus_tid[board] = 0xff; - if (sbus_tid[board] != 0xff) - cpu_clear(sbus_tid[board], sbus_serving_map); - } - for_each_node_by_name(dp, "sbi") { - int board = of_getintprop_default(dp, "board#", 0); - if (sbus_tid[board] == 0xff) { - int i = 31; - - if (cpus_empty(sbus_serving_map)) - sbus_serving_map = cpu_present_map; - while (cpu_isset(i, sbus_serving_map)) - i--; - sbus_tid[board] = i; - cpu_clear(i, sbus_serving_map); - } - } - for_each_node_by_name(dp, "sbi") { - int devid = of_getintprop_default(dp, "device-id", 0); - int board = of_getintprop_default(dp, "board#", 0); - printk("sbus%d IRQs directed to CPU%d\n", board, sbus_tid[board]); - set_sbi_tid(devid, sbus_tid[board] << 3); - } -#else int cpuid = cpu_logical_map(1); if (cpuid == -1) @@ -437,11 +416,10 @@ void __init sun4d_distribute_irqs(void) sbus_tid[board] = cpuid; set_sbi_tid(devid, cpuid << 3); } - printk("All sbus IRQs directed to CPU%d\n", cpuid); -#endif + printk(KERN_ERR "All sbus IRQs directed to CPU%d\n", cpuid); } #endif - + static void sun4d_clear_clock_irq(void) { sbus_readl(&sun4d_timers->l10_timer_limit); @@ -462,14 +440,61 @@ static void __init sun4d_load_profile_irqs(void) } } +unsigned int sun4d_build_device_irq(struct platform_device *op, + unsigned int real_irq) +{ + static int pil_to_sbus[] = { + 0, 0, 1, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0, 0, + }; + struct device_node *dp = op->dev.of_node; + struct device_node *io_unit, *sbi = dp->parent; + const struct linux_prom_registers *regs; + int board, slot; + int sbusl; + + while (sbi) { + if (!strcmp(sbi->name, "sbi")) + break; + + sbi = sbi->parent; + } + if (!sbi) + goto err_out; + + regs = of_get_property(dp, "reg", NULL); + if (!regs) + goto err_out; + + slot = regs->which_io; + + /* + * If SBI's parent is not io-unit or the io-unit lacks + * a "board#" property, something is very wrong. + */ + if (!sbi->parent || strcmp(sbi->parent->name, "io-unit")) { + printk("%s: Error, parent is not io-unit.\n", sbi->full_name); + goto err_out; + } + io_unit = sbi->parent; + board = of_getintprop_default(io_unit, "board#", -1); + if (board == -1) { + printk("%s: Error, lacks board# property.\n", io_unit->full_name); + goto err_out; + } + + sbusl = pil_to_sbus[real_irq]; + if (sbusl) + return (((board + 1) << 5) + (sbusl << 2) + slot); + +err_out: + return real_irq; +} + static void __init sun4d_fixup_trap_table(void) { #ifdef CONFIG_SMP unsigned long flags; - extern unsigned long lvl14_save[4]; struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)]; - extern unsigned int real_irq_entry[], smp4d_ticker[]; - extern unsigned int patchme_maybe_smp_msg[]; /* Adjust so that we jump directly to smp4d_ticker */ lvl14_save[2] += smp4d_ticker - real_irq_entry; @@ -531,7 +556,8 @@ static void __init sun4d_init_timers(irq_handler_t counter_fn) (IRQF_DISABLED | SA_STATIC_ALLOC), "timer", NULL); if (err) { - prom_printf("sun4d_init_timers: request_irq() failed with %d\n", err); + prom_printf("sun4d_init_timers: request_irq() failed with %d\n", + err); prom_halt(); } sun4d_load_profile_irqs(); @@ -550,7 +576,7 @@ void __init sun4d_init_sbi_irq(void) nsbi = 0; for_each_node_by_name(dp, "sbi") nsbi++; - sbus_actions = kzalloc (nsbi * 8 * 4 * sizeof(struct sbus_action), GFP_ATOMIC); + sbus_actions = kzalloc(nsbi * 8 * 4 * sizeof(struct sbus_action), GFP_ATOMIC); if (!sbus_actions) { prom_printf("SUN4D: Cannot allocate sbus_actions, halting.\n"); prom_halt(); @@ -566,7 +592,8 @@ void __init sun4d_init_sbi_irq(void) /* Get rid of pending irqs from PROM */ mask = acquire_sbi(devid, 0xffffffff); if (mask) { - printk ("Clearing pending IRQs %08x on SBI %d\n", mask, board); + printk(KERN_ERR "Clearing pending IRQs %08x on SBI %d\n", + mask, board); release_sbi(devid, mask); } } @@ -580,7 +607,10 @@ void __init sun4d_init_IRQ(void) BTFIXUPSET_CALL(disable_irq, sun4d_disable_irq, BTFIXUPCALL_NORM); BTFIXUPSET_CALL(clear_clock_irq, sun4d_clear_clock_irq, BTFIXUPCALL_NORM); BTFIXUPSET_CALL(load_profile_irq, sun4d_load_profile_irq, BTFIXUPCALL_NORM); - sparc_init_timers = sun4d_init_timers; + + sparc_irq_config.init_timers = sun4d_init_timers; + sparc_irq_config.build_device_irq = sun4d_build_device_irq; + #ifdef CONFIG_SMP BTFIXUPSET_CALL(set_cpu_int, sun4d_set_cpu_int, BTFIXUPCALL_NORM); BTFIXUPSET_CALL(clear_cpu_int, sun4d_clear_ipi, BTFIXUPCALL_NOP); diff --git a/arch/sparc/kernel/sun4d_smp.c b/arch/sparc/kernel/sun4d_smp.c index 482f2ab92692..475d50b96cd0 100644 --- a/arch/sparc/kernel/sun4d_smp.c +++ b/arch/sparc/kernel/sun4d_smp.c @@ -1,4 +1,4 @@ -/* sun4d_smp.c: Sparc SS1000/SC2000 SMP support. +/* Sparc SS1000/SC2000 SMP support. * * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) * @@ -6,59 +6,23 @@ * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) */ -#include <asm/head.h> - -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/threads.h> -#include <linux/smp.h> #include <linux/interrupt.h> -#include <linux/kernel_stat.h> -#include <linux/init.h> -#include <linux/spinlock.h> -#include <linux/mm.h> -#include <linux/swap.h> #include <linux/profile.h> #include <linux/delay.h> #include <linux/cpu.h> -#include <asm/ptrace.h> -#include <asm/atomic.h> -#include <asm/irq_regs.h> - -#include <asm/irq.h> -#include <asm/page.h> -#include <asm/pgalloc.h> -#include <asm/pgtable.h> -#include <asm/oplib.h> #include <asm/sbi.h> +#include <asm/mmu.h> #include <asm/tlbflush.h> #include <asm/cacheflush.h> -#include <asm/cpudata.h> +#include "kernel.h" #include "irq.h" -#define IRQ_CROSS_CALL 15 -extern ctxd_t *srmmu_ctx_table_phys; +#define IRQ_CROSS_CALL 15 -static volatile int smp_processors_ready = 0; +static volatile int smp_processors_ready; static int smp_highest_cpu; -extern volatile unsigned long cpu_callin_map[NR_CPUS]; -extern cpuinfo_sparc cpu_data[NR_CPUS]; -extern unsigned char boot_cpu_id; -extern volatile int smp_process_available; - -extern cpumask_t smp_commenced_mask; - -extern int __smp4d_processor_id(void); - -/* #define SMP_DEBUG */ - -#ifdef SMP_DEBUG -#define SMP_PRINTK(x) printk x -#else -#define SMP_PRINTK(x) -#endif static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned long val) { @@ -69,8 +33,6 @@ static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned lon } static void smp_setup_percpu_timer(void); -extern void cpu_probe(void); -extern void sun4d_distribute_irqs(void); static unsigned char cpu_leds[32]; @@ -86,9 +48,8 @@ static inline void show_leds(int cpuid) void __cpuinit smp4d_callin(void) { int cpuid = hard_smp4d_processor_id(); - extern spinlock_t sun4d_imsk_lock; unsigned long flags; - + /* Show we are alive */ cpu_leds[cpuid] = 0x6; show_leds(cpuid); @@ -118,15 +79,15 @@ void __cpuinit smp4d_callin(void) sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1); local_flush_cache_all(); local_flush_tlb_all(); - + cpu_probe(); - while((unsigned long)current_set[cpuid] < PAGE_OFFSET) + while ((unsigned long)current_set[cpuid] < PAGE_OFFSET) barrier(); - - while(current_set[cpuid]->cpu != cpuid) + + while (current_set[cpuid]->cpu != cpuid) barrier(); - + /* Fix idle thread fields. */ __asm__ __volatile__("ld [%0], %%g6\n\t" : : "r" (¤t_set[cpuid]) @@ -134,16 +95,16 @@ void __cpuinit smp4d_callin(void) cpu_leds[cpuid] = 0x9; show_leds(cpuid); - + /* Attach to the address space of init_task. */ atomic_inc(&init_mm.mm_count); current->active_mm = &init_mm; local_flush_cache_all(); local_flush_tlb_all(); - + local_irq_enable(); /* We don't allow PIL 14 yet */ - + while (!cpu_isset(cpuid, smp_commenced_mask)) barrier(); @@ -154,15 +115,9 @@ void __cpuinit smp4d_callin(void) } -extern void init_IRQ(void); -extern void cpu_panic(void); - /* * Cycle through the processors asking the PROM to start each one. */ - -extern struct linux_prom_registers smp_penguin_ctable; - void __init smp4d_boot_cpus(void) { if (boot_cpu_id) @@ -173,43 +128,42 @@ void __init smp4d_boot_cpus(void) int __cpuinit smp4d_boot_one_cpu(int i) { - extern unsigned long sun4d_cpu_startup; - unsigned long *entry = &sun4d_cpu_startup; - struct task_struct *p; - int timeout; - int cpu_node; + unsigned long *entry = &sun4d_cpu_startup; + struct task_struct *p; + int timeout; + int cpu_node; - cpu_find_by_instance(i, &cpu_node,NULL); - /* Cook up an idler for this guy. */ - p = fork_idle(i); - current_set[i] = task_thread_info(p); + cpu_find_by_instance(i, &cpu_node, NULL); + /* Cook up an idler for this guy. */ + p = fork_idle(i); + current_set[i] = task_thread_info(p); + + /* + * Initialize the contexts table + * Since the call to prom_startcpu() trashes the structure, + * we need to re-initialize it for each cpu + */ + smp_penguin_ctable.which_io = 0; + smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys; + smp_penguin_ctable.reg_size = 0; + + /* whirrr, whirrr, whirrrrrrrrr... */ + printk(KERN_INFO "Starting CPU %d at %p\n", i, entry); + local_flush_cache_all(); + prom_startcpu(cpu_node, + &smp_penguin_ctable, 0, (char *)entry); + + printk(KERN_INFO "prom_startcpu returned :)\n"); + + /* wheee... it's going... */ + for (timeout = 0; timeout < 10000; timeout++) { + if (cpu_callin_map[i]) + break; + udelay(200); + } - /* - * Initialize the contexts table - * Since the call to prom_startcpu() trashes the structure, - * we need to re-initialize it for each cpu - */ - smp_penguin_ctable.which_io = 0; - smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys; - smp_penguin_ctable.reg_size = 0; - - /* whirrr, whirrr, whirrrrrrrrr... */ - SMP_PRINTK(("Starting CPU %d at %p\n", i, entry)); - local_flush_cache_all(); - prom_startcpu(cpu_node, - &smp_penguin_ctable, 0, (char *)entry); - - SMP_PRINTK(("prom_startcpu returned :)\n")); - - /* wheee... it's going... */ - for(timeout = 0; timeout < 10000; timeout++) { - if(cpu_callin_map[i]) - break; - udelay(200); - } - if (!(cpu_callin_map[i])) { - printk("Processor %d is stuck.\n", i); + printk(KERN_ERR "Processor %d is stuck.\n", i); return -ENODEV; } @@ -255,14 +209,17 @@ static void smp4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, unsigned long arg2, unsigned long arg3, unsigned long arg4) { - if(smp_processors_ready) { + if (smp_processors_ready) { register int high = smp_highest_cpu; unsigned long flags; spin_lock_irqsave(&cross_call_lock, flags); { - /* If you make changes here, make sure gcc generates proper code... */ + /* + * If you make changes here, make sure + * gcc generates proper code... + */ register smpfunc_t f asm("i0") = func; register unsigned long a1 asm("i1") = arg1; register unsigned long a2 asm("i2") = arg2; @@ -284,7 +241,7 @@ static void smp4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, cpu_clear(smp_processor_id(), mask); cpus_and(mask, cpu_online_map, mask); - for(i = 0; i <= high; i++) { + for (i = 0; i <= high; i++) { if (cpu_isset(i, mask)) { ccall_info.processors_in[i] = 0; ccall_info.processors_out[i] = 0; @@ -300,17 +257,17 @@ static void smp4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, do { if (!cpu_isset(i, mask)) continue; - while(!ccall_info.processors_in[i]) + while (!ccall_info.processors_in[i]) barrier(); - } while(++i <= high); + } while (++i <= high); i = 0; do { if (!cpu_isset(i, mask)) continue; - while(!ccall_info.processors_out[i]) + while (!ccall_info.processors_out[i]) barrier(); - } while(++i <= high); + } while (++i <= high); } spin_unlock_irqrestore(&cross_call_lock, flags); @@ -336,7 +293,7 @@ void smp4d_percpu_timer_interrupt(struct pt_regs *regs) static char led_mask[] = { 0xe, 0xd, 0xb, 0x7, 0xb, 0xd }; old_regs = set_irq_regs(regs); - bw_get_prof_limit(cpu); + bw_get_prof_limit(cpu); bw_clear_intr_mask(0, 1); /* INTR_TABLE[0] & 1 is Profile IRQ */ cpu_tick[cpu]++; @@ -349,7 +306,7 @@ void smp4d_percpu_timer_interrupt(struct pt_regs *regs) profile_tick(CPU_PROFILING); - if(!--prof_counter(cpu)) { + if (!--prof_counter(cpu)) { int user = user_mode(regs); irq_enter(); @@ -361,8 +318,6 @@ void smp4d_percpu_timer_interrupt(struct pt_regs *regs) set_irq_regs(old_regs); } -extern unsigned int lvl14_resolution; - static void __cpuinit smp_setup_percpu_timer(void) { int cpu = hard_smp4d_processor_id(); @@ -374,16 +329,16 @@ static void __cpuinit smp_setup_percpu_timer(void) void __init smp4d_blackbox_id(unsigned *addr) { int rd = *addr & 0x3e000000; - + addr[0] = 0xc0800800 | rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */ - addr[1] = 0x01000000; /* nop */ - addr[2] = 0x01000000; /* nop */ + addr[1] = 0x01000000; /* nop */ + addr[2] = 0x01000000; /* nop */ } void __init smp4d_blackbox_current(unsigned *addr) { int rd = *addr & 0x3e000000; - + addr[0] = 0xc0800800 | rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */ addr[2] = 0x81282002 | rd | (rd >> 11); /* sll reg, 2, reg */ addr[4] = 0x01000000; /* nop */ @@ -392,17 +347,16 @@ void __init smp4d_blackbox_current(unsigned *addr) void __init sun4d_init_smp(void) { int i; - extern unsigned int t_nmi[], linux_trap_ipi15_sun4d[], linux_trap_ipi15_sun4m[]; /* Patch ipi15 trap table */ t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_sun4d - linux_trap_ipi15_sun4m); - + /* And set btfixup... */ BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4d_blackbox_id); BTFIXUPSET_BLACKBOX(load_current, smp4d_blackbox_current); BTFIXUPSET_CALL(smp_cross_call, smp4d_cross_call, BTFIXUPCALL_NORM); BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4d_processor_id, BTFIXUPCALL_NORM); - + for (i = 0; i < NR_CPUS; i++) { ccall_info.processors_in[i] = 1; ccall_info.processors_out[i] = 1; diff --git a/arch/sparc/kernel/sun4m_irq.c b/arch/sparc/kernel/sun4m_irq.c index 7f3b97ff62c1..69df6257a32e 100644 --- a/arch/sparc/kernel/sun4m_irq.c +++ b/arch/sparc/kernel/sun4m_irq.c @@ -1,5 +1,5 @@ -/* sun4m_irq.c - * arch/sparc/kernel/sun4m_irq.c: +/* + * sun4m irq support * * djhr: Hacked out of irq.c into a CPU dependent version. * @@ -9,101 +9,44 @@ * Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk) */ -#include <linux/errno.h> -#include <linux/linkage.h> -#include <linux/kernel_stat.h> -#include <linux/signal.h> -#include <linux/sched.h> -#include <linux/ptrace.h> -#include <linux/smp.h> -#include <linux/interrupt.h> -#include <linux/init.h> -#include <linux/ioport.h> -#include <linux/of.h> -#include <linux/of_device.h> - -#include <asm/ptrace.h> -#include <asm/processor.h> -#include <asm/system.h> -#include <asm/psr.h> -#include <asm/vaddrs.h> #include <asm/timer.h> -#include <asm/openprom.h> -#include <asm/oplib.h> #include <asm/traps.h> #include <asm/pgalloc.h> #include <asm/pgtable.h> -#include <asm/smp.h> #include <asm/irq.h> #include <asm/io.h> #include <asm/cacheflush.h> #include "irq.h" +#include "kernel.h" -struct sun4m_irq_percpu { - u32 pending; - u32 clear; - u32 set; -}; - -struct sun4m_irq_global { - u32 pending; - u32 mask; - u32 mask_clear; - u32 mask_set; - u32 interrupt_target; -}; - -/* Code in entry.S needs to get at these register mappings. */ -struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS]; -struct sun4m_irq_global __iomem *sun4m_irq_global; - -/* Dave Redman (djhr@tadpole.co.uk) - * The sun4m interrupt registers. - */ -#define SUN4M_INT_ENABLE 0x80000000 -#define SUN4M_INT_E14 0x00000080 -#define SUN4M_INT_E10 0x00080000 - -#define SUN4M_HARD_INT(x) (0x000000001 << (x)) -#define SUN4M_SOFT_INT(x) (0x000010000 << (x)) - -#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */ -#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */ -#define SUN4M_INT_M2S_WRITE_ERR 0x20000000 /* write buffer error */ -#define SUN4M_INT_ECC_ERR 0x10000000 /* ecc memory error */ -#define SUN4M_INT_VME_ERR 0x08000000 /* vme async error */ -#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */ -#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */ -#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */ -#define SUN4M_INT_REALTIME 0x00080000 /* system timer */ -#define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */ -#define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */ -#define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */ -#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */ -#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */ -#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */ -#define SUN4M_INT_VMEBITS 0x0000007F /* vme int bits */ - -#define SUN4M_INT_ERROR (SUN4M_INT_MODULE_ERR | \ - SUN4M_INT_M2S_WRITE_ERR | \ - SUN4M_INT_ECC_ERR | \ - SUN4M_INT_VME_ERR) - -#define SUN4M_INT_SBUS(x) (1 << (x+7)) -#define SUN4M_INT_VME(x) (1 << (x)) - -/* Interrupt levels used by OBP */ -#define OBP_INT_LEVEL_SOFT 0x10 -#define OBP_INT_LEVEL_ONBOARD 0x20 -#define OBP_INT_LEVEL_SBUS 0x30 -#define OBP_INT_LEVEL_VME 0x40 - -/* Interrupt level assignment on sun4m: +/* Sample sun4m IRQ layout: + * + * 0x22 - Power + * 0x24 - ESP SCSI + * 0x26 - Lance ethernet + * 0x2b - Floppy + * 0x2c - Zilog uart + * 0x32 - SBUS level 0 + * 0x33 - Parallel port, SBUS level 1 + * 0x35 - SBUS level 2 + * 0x37 - SBUS level 3 + * 0x39 - Audio, Graphics card, SBUS level 4 + * 0x3b - SBUS level 5 + * 0x3d - SBUS level 6 + * + * Each interrupt source has a mask bit in the interrupt registers. + * When the mask bit is set, this blocks interrupt deliver. So you + * clear the bit to enable the interrupt. + * + * Interrupts numbered less than 0x10 are software triggered interrupts + * and unused by Linux. + * + * Interrupt level assignment on sun4m: * * level source * ------------------------------------------------------------ - * 1 softint-1 + * 1 softint-1 * 2 softint-2, VME/SBUS level 1 * 3 softint-3, VME/SBUS level 2 * 4 softint-4, onboard SCSI @@ -138,10 +81,10 @@ struct sun4m_irq_global __iomem *sun4m_irq_global; * 'intr' property IRQ priority values from ss4, ss5, ss10, ss20, and * Tadpole S3 GX systems. * - * esp: 0x24 onboard ESP SCSI - * le: 0x26 onboard Lance ETHERNET + * esp: 0x24 onboard ESP SCSI + * le: 0x26 onboard Lance ETHERNET * p9100: 0x32 SBUS level 1 P9100 video - * bpp: 0x33 SBUS level 2 BPP parallel port device + * bpp: 0x33 SBUS level 2 BPP parallel port device * DBRI: 0x39 SBUS level 5 DBRI ISDN audio * SUNW,leo: 0x39 SBUS level 5 LEO video * pcmcia: 0x3b SBUS level 6 PCMCIA controller @@ -152,8 +95,57 @@ struct sun4m_irq_global __iomem *sun4m_irq_global; * power: 0x22 onboard power device (XXX unknown mask bit XXX) */ + +/* Code in entry.S needs to get at these register mappings. */ +struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS]; +struct sun4m_irq_global __iomem *sun4m_irq_global; + +/* Dave Redman (djhr@tadpole.co.uk) + * The sun4m interrupt registers. + */ +#define SUN4M_INT_ENABLE 0x80000000 +#define SUN4M_INT_E14 0x00000080 +#define SUN4M_INT_E10 0x00080000 + +#define SUN4M_HARD_INT(x) (0x000000001 << (x)) +#define SUN4M_SOFT_INT(x) (0x000010000 << (x)) + +#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */ +#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */ +#define SUN4M_INT_M2S_WRITE_ERR 0x20000000 /* write buffer error */ +#define SUN4M_INT_ECC_ERR 0x10000000 /* ecc memory error */ +#define SUN4M_INT_VME_ERR 0x08000000 /* vme async error */ +#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */ +#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */ +#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */ +#define SUN4M_INT_REALTIME 0x00080000 /* system timer */ +#define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */ +#define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */ +#define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */ +#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */ +#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */ +#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */ +#define SUN4M_INT_VMEBITS 0x0000007F /* vme int bits */ + +#define SUN4M_INT_ERROR (SUN4M_INT_MODULE_ERR | \ + SUN4M_INT_M2S_WRITE_ERR | \ + SUN4M_INT_ECC_ERR | \ + SUN4M_INT_VME_ERR) + +#define SUN4M_INT_SBUS(x) (1 << (x+7)) +#define SUN4M_INT_VME(x) (1 << (x)) + +/* Interrupt levels used by OBP */ +#define OBP_INT_LEVEL_SOFT 0x10 +#define OBP_INT_LEVEL_ONBOARD 0x20 +#define OBP_INT_LEVEL_SBUS 0x30 +#define OBP_INT_LEVEL_VME 0x40 + +#define SUN4M_TIMER_IRQ (OBP_INT_LEVEL_ONBOARD | 10) +#define SUM4M_PROFILE_IRQ (OBP_INT_LEVEL_ONBOARD | 14) + static unsigned long irq_mask[0x50] = { - /* SMP */ + /* 0x00 - SMP */ 0, SUN4M_SOFT_INT(1), SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3), SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5), @@ -162,7 +154,7 @@ static unsigned long irq_mask[0x50] = { SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11), SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13), SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15), - /* soft */ + /* 0x10 - soft */ 0, SUN4M_SOFT_INT(1), SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3), SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5), @@ -171,19 +163,19 @@ static unsigned long irq_mask[0x50] = { SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11), SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13), SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15), - /* onboard */ + /* 0x20 - onboard */ 0, 0, 0, 0, SUN4M_INT_SCSI, 0, SUN4M_INT_ETHERNET, 0, SUN4M_INT_VIDEO, SUN4M_INT_MODULE, SUN4M_INT_REALTIME, SUN4M_INT_FLOPPY, (SUN4M_INT_SERIAL | SUN4M_INT_KBDMS), SUN4M_INT_AUDIO, 0, SUN4M_INT_MODULE_ERR, - /* sbus */ + /* 0x30 - sbus */ 0, 0, SUN4M_INT_SBUS(0), SUN4M_INT_SBUS(1), 0, SUN4M_INT_SBUS(2), 0, SUN4M_INT_SBUS(3), 0, SUN4M_INT_SBUS(4), 0, SUN4M_INT_SBUS(5), 0, SUN4M_INT_SBUS(6), 0, 0, - /* vme */ + /* 0x40 - vme */ 0, 0, SUN4M_INT_VME(0), SUN4M_INT_VME(1), 0, SUN4M_INT_VME(2), 0, SUN4M_INT_VME(3), 0, SUN4M_INT_VME(4), 0, SUN4M_INT_VME(5), @@ -193,7 +185,7 @@ static unsigned long irq_mask[0x50] = { static unsigned long sun4m_get_irqmask(unsigned int irq) { unsigned long mask; - + if (irq < 0x50) mask = irq_mask[irq]; else @@ -217,7 +209,7 @@ static void sun4m_disable_irq(unsigned int irq_nr) sbus_writel(mask, &sun4m_irq_global->mask_set); else sbus_writel(mask, &sun4m_irq_percpu[cpu]->set); - local_irq_restore(flags); + local_irq_restore(flags); } static void sun4m_enable_irq(unsigned int irq_nr) @@ -226,17 +218,17 @@ static void sun4m_enable_irq(unsigned int irq_nr) int cpu = smp_processor_id(); /* Dreadful floppy hack. When we use 0x2b instead of - * 0x0b the system blows (it starts to whistle!). - * So we continue to use 0x0b. Fixme ASAP. --P3 - */ - if (irq_nr != 0x0b) { + * 0x0b the system blows (it starts to whistle!). + * So we continue to use 0x0b. Fixme ASAP. --P3 + */ + if (irq_nr != 0x0b) { mask = sun4m_get_irqmask(irq_nr); local_irq_save(flags); if (irq_nr > 15) sbus_writel(mask, &sun4m_irq_global->mask_clear); else sbus_writel(mask, &sun4m_irq_percpu[cpu]->clear); - local_irq_restore(flags); + local_irq_restore(flags); } else { local_irq_save(flags); sbus_writel(SUN4M_INT_FLOPPY, &sun4m_irq_global->mask_clear); @@ -260,7 +252,7 @@ static unsigned long cpu_pil_to_imask[16] = { /*12*/ SUN4M_INT_SERIAL | SUN4M_INT_KBDMS, /*13*/ SUN4M_INT_SBUS(6) | SUN4M_INT_VME(6) | SUN4M_INT_AUDIO, /*14*/ SUN4M_INT_E14, -/*15*/ SUN4M_INT_ERROR +/*15*/ SUN4M_INT_ERROR, }; /* We assume the caller has disabled local interrupts when these are called, @@ -280,12 +272,14 @@ static void sun4m_enable_pil_irq(unsigned int pil) static void sun4m_send_ipi(int cpu, int level) { unsigned long mask = sun4m_get_irqmask(level); + sbus_writel(mask, &sun4m_irq_percpu[cpu]->set); } static void sun4m_clear_ipi(int cpu, int level) { unsigned long mask = sun4m_get_irqmask(level); + sbus_writel(mask, &sun4m_irq_percpu[cpu]->clear); } @@ -314,7 +308,6 @@ struct sun4m_timer_global { static struct sun4m_timer_global __iomem *timers_global; -#define TIMER_IRQ (OBP_INT_LEVEL_ONBOARD | 10) unsigned int lvl14_resolution = (((1000000/HZ) + 1) << 10); @@ -391,7 +384,7 @@ static void __init sun4m_init_timers(irq_handler_t counter_fn) master_l10_counter = &timers_global->l10_count; - err = request_irq(TIMER_IRQ, counter_fn, + err = request_irq(SUN4M_TIMER_IRQ, counter_fn, (IRQF_DISABLED | SA_STATIC_ALLOC), "timer", NULL); if (err) { printk(KERN_ERR "sun4m_init_timers: Register IRQ error %d.\n", @@ -407,7 +400,6 @@ static void __init sun4m_init_timers(irq_handler_t counter_fn) #ifdef CONFIG_SMP { unsigned long flags; - extern unsigned long lvl14_save[4]; struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)]; /* For SMP we use the level 14 ticker, however the bootup code @@ -466,7 +458,9 @@ void __init sun4m_init_IRQ(void) BTFIXUPSET_CALL(disable_pil_irq, sun4m_disable_pil_irq, BTFIXUPCALL_NORM); BTFIXUPSET_CALL(clear_clock_irq, sun4m_clear_clock_irq, BTFIXUPCALL_NORM); BTFIXUPSET_CALL(load_profile_irq, sun4m_load_profile_irq, BTFIXUPCALL_NORM); - sparc_init_timers = sun4m_init_timers; + + sparc_irq_config.init_timers = sun4m_init_timers; + #ifdef CONFIG_SMP BTFIXUPSET_CALL(set_cpu_int, sun4m_send_ipi, BTFIXUPCALL_NORM); BTFIXUPSET_CALL(clear_cpu_int, sun4m_clear_ipi, BTFIXUPCALL_NORM); diff --git a/arch/sparc/kernel/sun4m_smp.c b/arch/sparc/kernel/sun4m_smp.c index 762d6eedd944..5cc7dc51de3d 100644 --- a/arch/sparc/kernel/sun4m_smp.c +++ b/arch/sparc/kernel/sun4m_smp.c @@ -1,59 +1,22 @@ -/* sun4m_smp.c: Sparc SUN4M SMP support. +/* + * sun4m SMP support. * * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) */ -#include <asm/head.h> - -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/threads.h> -#include <linux/smp.h> #include <linux/interrupt.h> -#include <linux/kernel_stat.h> -#include <linux/init.h> -#include <linux/spinlock.h> -#include <linux/mm.h> -#include <linux/swap.h> #include <linux/profile.h> #include <linux/delay.h> #include <linux/cpu.h> #include <asm/cacheflush.h> #include <asm/tlbflush.h> -#include <asm/irq_regs.h> - -#include <asm/ptrace.h> -#include <asm/atomic.h> - -#include <asm/irq.h> -#include <asm/page.h> -#include <asm/pgalloc.h> -#include <asm/pgtable.h> -#include <asm/oplib.h> -#include <asm/cpudata.h> #include "irq.h" +#include "kernel.h" #define IRQ_CROSS_CALL 15 -extern ctxd_t *srmmu_ctx_table_phys; - -extern volatile unsigned long cpu_callin_map[NR_CPUS]; -extern unsigned char boot_cpu_id; - -extern cpumask_t smp_commenced_mask; - -extern int __smp4m_processor_id(void); - -/*#define SMP_DEBUG*/ - -#ifdef SMP_DEBUG -#define SMP_PRINTK(x) printk x -#else -#define SMP_PRINTK(x) -#endif - static inline unsigned long swap_ulong(volatile unsigned long *ptr, unsigned long val) { @@ -64,7 +27,6 @@ swap_ulong(volatile unsigned long *ptr, unsigned long val) } static void smp_setup_percpu_timer(void); -extern void cpu_probe(void); void __cpuinit smp4m_callin(void) { @@ -96,7 +58,7 @@ void __cpuinit smp4m_callin(void) /* XXX: What's up with all the flushes? */ local_flush_cache_all(); local_flush_tlb_all(); - + cpu_probe(); /* Fix idle thread fields. */ @@ -119,9 +81,6 @@ void __cpuinit smp4m_callin(void) /* * Cycle through the processors asking the PROM to start each one. */ - -extern struct linux_prom_registers smp_penguin_ctable; - void __init smp4m_boot_cpus(void) { smp_setup_percpu_timer(); @@ -130,7 +89,6 @@ void __init smp4m_boot_cpus(void) int __cpuinit smp4m_boot_one_cpu(int i) { - extern unsigned long sun4m_cpu_startup; unsigned long *entry = &sun4m_cpu_startup; struct task_struct *p; int timeout; @@ -142,7 +100,7 @@ int __cpuinit smp4m_boot_one_cpu(int i) p = fork_idle(i); current_set[i] = task_thread_info(p); /* See trampoline.S for details... */ - entry += ((i-1) * 3); + entry += ((i - 1) * 3); /* * Initialize the contexts table @@ -154,20 +112,19 @@ int __cpuinit smp4m_boot_one_cpu(int i) smp_penguin_ctable.reg_size = 0; /* whirrr, whirrr, whirrrrrrrrr... */ - printk("Starting CPU %d at %p\n", i, entry); + printk(KERN_INFO "Starting CPU %d at %p\n", i, entry); local_flush_cache_all(); - prom_startcpu(cpu_node, - &smp_penguin_ctable, 0, (char *)entry); + prom_startcpu(cpu_node, &smp_penguin_ctable, 0, (char *)entry); /* wheee... it's going... */ - for(timeout = 0; timeout < 10000; timeout++) { - if(cpu_callin_map[i]) + for (timeout = 0; timeout < 10000; timeout++) { + if (cpu_callin_map[i]) break; udelay(200); } if (!(cpu_callin_map[i])) { - printk("Processor %d is stuck.\n", i); + printk(KERN_ERR "Processor %d is stuck.\n", i); return -ENODEV; } @@ -202,6 +159,7 @@ void __init smp4m_smp_done(void) void smp4m_irq_rotate(int cpu) { int next = cpu_data(cpu).next; + if (next != cpu) set_irq_udt(next); } @@ -243,7 +201,7 @@ static void smp4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, cpu_clear(smp_processor_id(), mask); cpus_and(mask, cpu_online_map, mask); - for(i = 0; i < ncpus; i++) { + for (i = 0; i < ncpus; i++) { if (cpu_isset(i, mask)) { ccall_info.processors_in[i] = 0; ccall_info.processors_out[i] = 0; @@ -262,19 +220,18 @@ static void smp4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, do { if (!cpu_isset(i, mask)) continue; - while(!ccall_info.processors_in[i]) + while (!ccall_info.processors_in[i]) barrier(); - } while(++i < ncpus); + } while (++i < ncpus); i = 0; do { if (!cpu_isset(i, mask)) continue; - while(!ccall_info.processors_out[i]) + while (!ccall_info.processors_out[i]) barrier(); - } while(++i < ncpus); + } while (++i < ncpus); } - spin_unlock_irqrestore(&cross_call_lock, flags); } @@ -289,8 +246,6 @@ void smp4m_cross_call_irq(void) ccall_info.processors_out[i] = 1; } -extern void sun4m_clear_profile_irq(int cpu); - void smp4m_percpu_timer_interrupt(struct pt_regs *regs) { struct pt_regs *old_regs; @@ -302,7 +257,7 @@ void smp4m_percpu_timer_interrupt(struct pt_regs *regs) profile_tick(CPU_PROFILING); - if(!--prof_counter(cpu)) { + if (!--prof_counter(cpu)) { int user = user_mode(regs); irq_enter(); @@ -314,8 +269,6 @@ void smp4m_percpu_timer_interrupt(struct pt_regs *regs) set_irq_regs(old_regs); } -extern unsigned int lvl14_resolution; - static void __cpuinit smp_setup_percpu_timer(void) { int cpu = smp_processor_id(); @@ -323,7 +276,7 @@ static void __cpuinit smp_setup_percpu_timer(void) prof_counter(cpu) = prof_multiplier(cpu) = 1; load_profile_irq(cpu, lvl14_resolution); - if(cpu == boot_cpu_id) + if (cpu == boot_cpu_id) enable_pil_irq(14); } @@ -331,9 +284,9 @@ static void __init smp4m_blackbox_id(unsigned *addr) { int rd = *addr & 0x3e000000; int rs1 = rd >> 11; - + addr[0] = 0x81580000 | rd; /* rd %tbr, reg */ - addr[1] = 0x8130200c | rd | rs1; /* srl reg, 0xc, reg */ + addr[1] = 0x8130200c | rd | rs1; /* srl reg, 0xc, reg */ addr[2] = 0x80082003 | rd | rs1; /* and reg, 3, reg */ } @@ -341,9 +294,9 @@ static void __init smp4m_blackbox_current(unsigned *addr) { int rd = *addr & 0x3e000000; int rs1 = rd >> 11; - + addr[0] = 0x81580000 | rd; /* rd %tbr, reg */ - addr[2] = 0x8130200a | rd | rs1; /* srl reg, 0xa, reg */ + addr[2] = 0x8130200a | rd | rs1; /* srl reg, 0xa, reg */ addr[4] = 0x8008200c | rd | rs1; /* and reg, 0xc, reg */ } diff --git a/arch/sparc/kernel/sys_sparc_64.c b/arch/sparc/kernel/sys_sparc_64.c index f836f4e93afe..96082d30def0 100644 --- a/arch/sparc/kernel/sys_sparc_64.c +++ b/arch/sparc/kernel/sys_sparc_64.c @@ -360,20 +360,25 @@ unsigned long get_fb_unmapped_area(struct file *filp, unsigned long orig_addr, u } EXPORT_SYMBOL(get_fb_unmapped_area); -/* Essentially the same as PowerPC... */ -void arch_pick_mmap_layout(struct mm_struct *mm) +/* Essentially the same as PowerPC. */ +static unsigned long mmap_rnd(void) { - unsigned long random_factor = 0UL; - unsigned long gap; + unsigned long rnd = 0UL; if (current->flags & PF_RANDOMIZE) { - random_factor = get_random_int(); + unsigned long val = get_random_int(); if (test_thread_flag(TIF_32BIT)) - random_factor &= ((1 * 1024 * 1024) - 1); + rnd = (val % (1UL << (22UL-PAGE_SHIFT))); else - random_factor = ((random_factor << PAGE_SHIFT) & - 0xffffffffUL); + rnd = (val % (1UL << (29UL-PAGE_SHIFT))); } + return (rnd << PAGE_SHIFT) * 2; +} + +void arch_pick_mmap_layout(struct mm_struct *mm) +{ + unsigned long random_factor = mmap_rnd(); + unsigned long gap; /* * Fall back to the standard layout if the personality diff --git a/arch/sparc/kernel/tick14.c b/arch/sparc/kernel/tick14.c deleted file mode 100644 index 138bbf5f8724..000000000000 --- a/arch/sparc/kernel/tick14.c +++ /dev/null @@ -1,39 +0,0 @@ -/* tick14.c - * - * Copyright (C) 1996 David Redman (djhr@tadpole.co.uk) - * - * This file handles the Sparc specific level14 ticker - * This is really useful for profiling OBP uses it for keyboard - * aborts and other stuff. - */ -#include <linux/kernel.h> - -extern unsigned long lvl14_save[5]; -static unsigned long *linux_lvl14 = NULL; -static unsigned long obp_lvl14[4]; - -/* - * Call with timer IRQ closed. - * First time we do it with disable_irq, later prom code uses spin_lock_irq(). - */ -void install_linux_ticker(void) -{ - - if (!linux_lvl14) - return; - linux_lvl14[0] = lvl14_save[0]; - linux_lvl14[1] = lvl14_save[1]; - linux_lvl14[2] = lvl14_save[2]; - linux_lvl14[3] = lvl14_save[3]; -} - -void install_obp_ticker(void) -{ - - if (!linux_lvl14) - return; - linux_lvl14[0] = obp_lvl14[0]; - linux_lvl14[1] = obp_lvl14[1]; - linux_lvl14[2] = obp_lvl14[2]; - linux_lvl14[3] = obp_lvl14[3]; -} diff --git a/arch/sparc/kernel/time_32.c b/arch/sparc/kernel/time_32.c index 9c743b1886ff..8237dd4dfeb4 100644 --- a/arch/sparc/kernel/time_32.c +++ b/arch/sparc/kernel/time_32.c @@ -85,7 +85,7 @@ int update_persistent_clock(struct timespec now) /* * timer_interrupt() needs to keep up the real-time clock, - * as well as call the "do_timer()" routine every clocktick + * as well as call the "xtime_update()" routine every clocktick */ #define TICK_SIZE (tick_nsec / 1000) @@ -96,14 +96,9 @@ static irqreturn_t timer_interrupt(int dummy, void *dev_id) profile_tick(CPU_PROFILING); #endif - /* Protect counter clear so that do_gettimeoffset works */ - write_seqlock(&xtime_lock); - clear_clock_irq(); - do_timer(1); - - write_sequnlock(&xtime_lock); + xtime_update(1); #ifndef CONFIG_SMP update_process_times(user_mode(get_irq_regs())); @@ -142,7 +137,7 @@ static struct platform_device m48t59_rtc = { }, }; -static int __devinit clock_probe(struct platform_device *op, const struct of_device_id *match) +static int __devinit clock_probe(struct platform_device *op) { struct device_node *dp = op->dev.of_node; const char *model = of_get_property(dp, "model", NULL); @@ -176,7 +171,7 @@ static struct of_device_id __initdata clock_match[] = { {}, }; -static struct of_platform_driver clock_driver = { +static struct platform_driver clock_driver = { .probe = clock_probe, .driver = { .name = "rtc", @@ -189,7 +184,7 @@ static struct of_platform_driver clock_driver = { /* Probe for the mostek real time clock chip. */ static int __init clock_init(void) { - return of_register_platform_driver(&clock_driver); + return platform_driver_register(&clock_driver); } /* Must be after subsys_initcall() so that busses are probed. Must * be before device_initcall() because things like the RTC driver @@ -224,7 +219,7 @@ static void __init sbus_time_init(void) btfixup(); - sparc_init_timers(timer_interrupt); + sparc_irq_config.init_timers(timer_interrupt); } void __init time_init(void) diff --git a/arch/sparc/kernel/time_64.c b/arch/sparc/kernel/time_64.c index 3bc9c9979b92..95ec25faba39 100644 --- a/arch/sparc/kernel/time_64.c +++ b/arch/sparc/kernel/time_64.c @@ -419,7 +419,7 @@ static struct platform_device rtc_cmos_device = { .num_resources = 1, }; -static int __devinit rtc_probe(struct platform_device *op, const struct of_device_id *match) +static int __devinit rtc_probe(struct platform_device *op) { struct resource *r; @@ -462,7 +462,7 @@ static struct of_device_id __initdata rtc_match[] = { {}, }; -static struct of_platform_driver rtc_driver = { +static struct platform_driver rtc_driver = { .probe = rtc_probe, .driver = { .name = "rtc", @@ -477,7 +477,7 @@ static struct platform_device rtc_bq4802_device = { .num_resources = 1, }; -static int __devinit bq4802_probe(struct platform_device *op, const struct of_device_id *match) +static int __devinit bq4802_probe(struct platform_device *op) { printk(KERN_INFO "%s: BQ4802 regs at 0x%llx\n", @@ -495,7 +495,7 @@ static struct of_device_id __initdata bq4802_match[] = { {}, }; -static struct of_platform_driver bq4802_driver = { +static struct platform_driver bq4802_driver = { .probe = bq4802_probe, .driver = { .name = "bq4802", @@ -534,7 +534,7 @@ static struct platform_device m48t59_rtc = { }, }; -static int __devinit mostek_probe(struct platform_device *op, const struct of_device_id *match) +static int __devinit mostek_probe(struct platform_device *op) { struct device_node *dp = op->dev.of_node; @@ -559,7 +559,7 @@ static struct of_device_id __initdata mostek_match[] = { {}, }; -static struct of_platform_driver mostek_driver = { +static struct platform_driver mostek_driver = { .probe = mostek_probe, .driver = { .name = "mostek", @@ -586,9 +586,9 @@ static int __init clock_init(void) if (tlb_type == hypervisor) return platform_device_register(&rtc_sun4v_device); - (void) of_register_platform_driver(&rtc_driver); - (void) of_register_platform_driver(&mostek_driver); - (void) of_register_platform_driver(&bq4802_driver); + (void) platform_driver_register(&rtc_driver); + (void) platform_driver_register(&mostek_driver); + (void) platform_driver_register(&bq4802_driver); return 0; } @@ -816,14 +816,12 @@ void __init time_init(void) clocksource_hz2mult(freq, SPARC64_NSEC_PER_CYC_SHIFT); clocksource_tick.name = tick_ops->name; - clocksource_calc_mult_shift(&clocksource_tick, freq, 4); clocksource_tick.read = clocksource_tick_read; + clocksource_register_hz(&clocksource_tick, freq); printk("clocksource: mult[%x] shift[%d]\n", clocksource_tick.mult, clocksource_tick.shift); - clocksource_register(&clocksource_tick); - sparc64_clockevent.name = tick_ops->name; clockevents_calc_mult_shift(&sparc64_clockevent, freq, 4); diff --git a/arch/sparc/kernel/traps_64.c b/arch/sparc/kernel/traps_64.c index 1e9770936c3b..1ed547bd850f 100644 --- a/arch/sparc/kernel/traps_64.c +++ b/arch/sparc/kernel/traps_64.c @@ -2152,7 +2152,7 @@ static void user_instruction_dump(unsigned int __user *pc) void show_stack(struct task_struct *tsk, unsigned long *_ksp) { - unsigned long fp, thread_base, ksp; + unsigned long fp, ksp; struct thread_info *tp; int count = 0; #ifdef CONFIG_FUNCTION_GRAPH_TRACER @@ -2173,7 +2173,6 @@ void show_stack(struct task_struct *tsk, unsigned long *_ksp) flushw_all(); fp = ksp + STACK_BIAS; - thread_base = (unsigned long) tp; printk("Call Trace:\n"); do { diff --git a/arch/sparc/kernel/una_asm_64.S b/arch/sparc/kernel/una_asm_64.S index be183fe41443..1c8d33228b2a 100644 --- a/arch/sparc/kernel/una_asm_64.S +++ b/arch/sparc/kernel/una_asm_64.S @@ -127,7 +127,7 @@ do_int_load: wr %o5, 0x0, %asi retl mov 0, %o0 - .size __do_int_load, .-__do_int_load + .size do_int_load, .-do_int_load .section __ex_table,"a" .word 4b, __retl_efault diff --git a/arch/sparc/kernel/vmlinux.lds.S b/arch/sparc/kernel/vmlinux.lds.S index 0c1e6783657f..92b557afe535 100644 --- a/arch/sparc/kernel/vmlinux.lds.S +++ b/arch/sparc/kernel/vmlinux.lds.S @@ -108,7 +108,7 @@ SECTIONS __sun4v_2insn_patch_end = .; } - PERCPU(PAGE_SIZE) + PERCPU(SMP_CACHE_BYTES, PAGE_SIZE) . = ALIGN(PAGE_SIZE); __init_end = .; diff --git a/arch/sparc/lib/atomic32.c b/arch/sparc/lib/atomic32.c index cbddeb38ffda..d3c7a12ad879 100644 --- a/arch/sparc/lib/atomic32.c +++ b/arch/sparc/lib/atomic32.c @@ -16,7 +16,7 @@ #define ATOMIC_HASH(a) (&__atomic_hash[(((unsigned long)a)>>8) & (ATOMIC_HASH_SIZE-1)]) spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] = { - [0 ... (ATOMIC_HASH_SIZE-1)] = SPIN_LOCK_UNLOCKED + [0 ... (ATOMIC_HASH_SIZE-1)] = __SPIN_LOCK_UNLOCKED(__atomic_hash) }; #else /* SMP */ diff --git a/arch/sparc/mm/fault_32.c b/arch/sparc/mm/fault_32.c index 5b836f5aea90..b10ac4d62378 100644 --- a/arch/sparc/mm/fault_32.c +++ b/arch/sparc/mm/fault_32.c @@ -240,11 +240,10 @@ asmlinkage void do_sparc_fault(struct pt_regs *regs, int text_fault, int write, * only copy the information from the master page table, * nothing more. */ + code = SEGV_MAPERR; if (!ARCH_SUN4C && address >= TASK_SIZE) goto vmalloc_fault; - code = SEGV_MAPERR; - /* * If we're in an interrupt or have no user * context, we must not take the fault.. diff --git a/arch/sparc/prom/misc_32.c b/arch/sparc/prom/misc_32.c index 8c278c311ba4..677b6a10fbde 100644 --- a/arch/sparc/prom/misc_32.c +++ b/arch/sparc/prom/misc_32.c @@ -54,15 +54,11 @@ EXPORT_SYMBOL(prom_feval); void prom_cmdline(void) { - extern void install_obp_ticker(void); - extern void install_linux_ticker(void); unsigned long flags; spin_lock_irqsave(&prom_lock, flags); - install_obp_ticker(); (*(romvec->pv_abort))(); restore_current(); - install_linux_ticker(); spin_unlock_irqrestore(&prom_lock, flags); set_auxio(AUXIO_LED, 0); } diff --git a/arch/tile/include/asm/futex.h b/arch/tile/include/asm/futex.h index fe0d10dcae57..d03ec124a598 100644 --- a/arch/tile/include/asm/futex.h +++ b/arch/tile/include/asm/futex.h @@ -29,16 +29,16 @@ #include <linux/uaccess.h> #include <linux/errno.h> -extern struct __get_user futex_set(int __user *v, int i); -extern struct __get_user futex_add(int __user *v, int n); -extern struct __get_user futex_or(int __user *v, int n); -extern struct __get_user futex_andn(int __user *v, int n); -extern struct __get_user futex_cmpxchg(int __user *v, int o, int n); +extern struct __get_user futex_set(u32 __user *v, int i); +extern struct __get_user futex_add(u32 __user *v, int n); +extern struct __get_user futex_or(u32 __user *v, int n); +extern struct __get_user futex_andn(u32 __user *v, int n); +extern struct __get_user futex_cmpxchg(u32 __user *v, int o, int n); #ifndef __tilegx__ -extern struct __get_user futex_xor(int __user *v, int n); +extern struct __get_user futex_xor(u32 __user *v, int n); #else -static inline struct __get_user futex_xor(int __user *uaddr, int n) +static inline struct __get_user futex_xor(u32 __user *uaddr, int n) { struct __get_user asm_ret = __get_user_4(uaddr); if (!asm_ret.err) { @@ -53,7 +53,7 @@ static inline struct __get_user futex_xor(int __user *uaddr, int n) } #endif -static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr) +static inline int futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr) { int op = (encoded_op >> 28) & 7; int cmp = (encoded_op >> 24) & 15; @@ -65,7 +65,7 @@ static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr) if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) oparg = 1 << oparg; - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; pagefault_disable(); @@ -119,16 +119,17 @@ static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr) return ret; } -static inline int futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, - int newval) +static inline int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) { struct __get_user asm_ret; - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; asm_ret = futex_cmpxchg(uaddr, oldval, newval); - return asm_ret.err ? asm_ret.err : asm_ret.val; + *uval = asm_ret.val; + return asm_ret.err; } #ifndef __tilegx__ diff --git a/arch/tile/kernel/vmlinux.lds.S b/arch/tile/kernel/vmlinux.lds.S index 25fdc0c1839a..c6ce378e0678 100644 --- a/arch/tile/kernel/vmlinux.lds.S +++ b/arch/tile/kernel/vmlinux.lds.S @@ -63,7 +63,7 @@ SECTIONS *(.init.page) } :data =0 INIT_DATA_SECTION(16) - PERCPU(PAGE_SIZE) + PERCPU(L2_CACHE_BYTES, PAGE_SIZE) . = ALIGN(PAGE_SIZE); VMLINUX_SYMBOL(_einitdata) = .; diff --git a/arch/um/Kconfig.common b/arch/um/Kconfig.common index e351e14b4339..1e78940218c0 100644 --- a/arch/um/Kconfig.common +++ b/arch/um/Kconfig.common @@ -7,6 +7,7 @@ config UML bool default y select HAVE_GENERIC_HARDIRQS + select GENERIC_HARDIRQS_NO_DEPRECATED config MMU bool diff --git a/arch/um/Kconfig.x86 b/arch/um/Kconfig.x86 index 5ee328099c63..02fb017fed47 100644 --- a/arch/um/Kconfig.x86 +++ b/arch/um/Kconfig.x86 @@ -10,6 +10,8 @@ endmenu config UML_X86 def_bool y + select GENERIC_FIND_FIRST_BIT + select GENERIC_FIND_NEXT_BIT config 64BIT bool @@ -19,6 +21,9 @@ config X86_32 def_bool !64BIT select HAVE_AOUT +config X86_64 + def_bool 64BIT + config RWSEM_XCHGADD_ALGORITHM def_bool X86_XADD diff --git a/arch/um/drivers/mconsole_kern.c b/arch/um/drivers/mconsole_kern.c index 975613b23dcf..c70e047eed72 100644 --- a/arch/um/drivers/mconsole_kern.c +++ b/arch/um/drivers/mconsole_kern.c @@ -124,35 +124,18 @@ void mconsole_log(struct mc_request *req) #if 0 void mconsole_proc(struct mc_request *req) { - struct nameidata nd; struct vfsmount *mnt = current->nsproxy->pid_ns->proc_mnt; struct file *file; - int n, err; + int n; char *ptr = req->request.data, *buf; mm_segment_t old_fs = get_fs(); ptr += strlen("proc"); ptr = skip_spaces(ptr); - err = vfs_path_lookup(mnt->mnt_root, mnt, ptr, LOOKUP_FOLLOW, &nd); - if (err) { - mconsole_reply(req, "Failed to look up file", 1, 0); - goto out; - } - - err = may_open(&nd.path, MAY_READ, O_RDONLY); - if (result) { - mconsole_reply(req, "Failed to open file", 1, 0); - path_put(&nd.path); - goto out; - } - - file = dentry_open(nd.path.dentry, nd.path.mnt, O_RDONLY, - current_cred()); - err = PTR_ERR(file); + file = file_open_root(mnt->mnt_root, mnt, ptr, O_RDONLY); if (IS_ERR(file)) { mconsole_reply(req, "Failed to open file", 1, 0); - path_put(&nd.path); goto out; } diff --git a/arch/um/drivers/ubd_kern.c b/arch/um/drivers/ubd_kern.c index ba4a98ba39c0..620f5b70957d 100644 --- a/arch/um/drivers/ubd_kern.c +++ b/arch/um/drivers/ubd_kern.c @@ -185,7 +185,7 @@ struct ubd { .no_cow = 0, \ .shared = 0, \ .cow = DEFAULT_COW, \ - .lock = SPIN_LOCK_UNLOCKED, \ + .lock = __SPIN_LOCK_UNLOCKED(ubd_devs.lock), \ .request = NULL, \ .start_sg = 0, \ .end_sg = 0, \ diff --git a/arch/um/include/asm/common.lds.S b/arch/um/include/asm/common.lds.S index ac55b9efa1ce..34bede8aad4a 100644 --- a/arch/um/include/asm/common.lds.S +++ b/arch/um/include/asm/common.lds.S @@ -42,7 +42,7 @@ INIT_SETUP(0) } - PERCPU(32) + PERCPU(32, 32) .initcall.init : { INIT_CALLS diff --git a/arch/um/kernel/irq.c b/arch/um/kernel/irq.c index 3f0ac9e0c966..64cfea80cfe2 100644 --- a/arch/um/kernel/irq.c +++ b/arch/um/kernel/irq.c @@ -35,8 +35,10 @@ int show_interrupts(struct seq_file *p, void *v) } if (i < NR_IRQS) { - raw_spin_lock_irqsave(&irq_desc[i].lock, flags); - action = irq_desc[i].action; + struct irq_desc *desc = irq_to_desc(i); + + raw_spin_lock_irqsave(&desc->lock, flags); + action = desc->action; if (!action) goto skip; seq_printf(p, "%3d: ",i); @@ -46,7 +48,7 @@ int show_interrupts(struct seq_file *p, void *v) for_each_online_cpu(j) seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); #endif - seq_printf(p, " %14s", irq_desc[i].chip->name); + seq_printf(p, " %14s", get_irq_desc_chip(desc)->name); seq_printf(p, " %s", action->name); for (action=action->next; action; action = action->next) @@ -54,7 +56,7 @@ int show_interrupts(struct seq_file *p, void *v) seq_putc(p, '\n'); skip: - raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); + raw_spin_unlock_irqrestore(&desc->lock, flags); } else if (i == NR_IRQS) seq_putc(p, '\n'); @@ -360,10 +362,10 @@ EXPORT_SYMBOL(um_request_irq); EXPORT_SYMBOL(reactivate_fd); /* - * irq_chip must define (startup || enable) && - * (shutdown || disable) && end + * irq_chip must define at least enable/disable and ack when + * the edge handler is used. */ -static void dummy(unsigned int irq) +static void dummy(struct irq_data *d) { } @@ -371,20 +373,17 @@ static void dummy(unsigned int irq) static struct irq_chip normal_irq_type = { .name = "SIGIO", .release = free_irq_by_irq_and_dev, - .disable = dummy, - .enable = dummy, - .ack = dummy, - .end = dummy + .irq_disable = dummy, + .irq_enable = dummy, + .irq_ack = dummy, }; static struct irq_chip SIGVTALRM_irq_type = { .name = "SIGVTALRM", .release = free_irq_by_irq_and_dev, - .shutdown = dummy, /* never called */ - .disable = dummy, - .enable = dummy, - .ack = dummy, - .end = dummy + .irq_disable = dummy, + .irq_enable = dummy, + .irq_ack = dummy, }; void __init init_IRQ(void) diff --git a/arch/unicore32/.gitignore b/arch/unicore32/.gitignore new file mode 100644 index 000000000000..947e99c2a957 --- /dev/null +++ b/arch/unicore32/.gitignore @@ -0,0 +1,21 @@ +# +# Generated include files +# +include/generated +# +# Generated ld script file +# +kernel/vmlinux.lds +# +# Generated images in boot +# +boot/Image +boot/zImage +boot/uImage +# +# Generated files in boot/compressed +# +boot/compressed/piggy.S +boot/compressed/piggy.gzip +boot/compressed/vmlinux +boot/compressed/vmlinux.lds diff --git a/arch/unicore32/Kconfig b/arch/unicore32/Kconfig new file mode 100644 index 000000000000..4a36db45fb3d --- /dev/null +++ b/arch/unicore32/Kconfig @@ -0,0 +1,275 @@ +config UNICORE32 + def_bool y + select HAVE_MEMBLOCK + select HAVE_GENERIC_DMA_COHERENT + select HAVE_GENERIC_HARDIRQS + select HAVE_DMA_ATTRS + select HAVE_KERNEL_GZIP + select HAVE_KERNEL_BZIP2 + select HAVE_KERNEL_LZO + select HAVE_KERNEL_LZMA + select GENERIC_FIND_FIRST_BIT + select GENERIC_IRQ_PROBE + select GENERIC_HARDIRQS_NO_DEPRECATED + select ARCH_WANT_FRAME_POINTERS + help + UniCore-32 is 32-bit Instruction Set Architecture, + including a series of low-power-consumption RISC chip + designs licensed by PKUnity Ltd. + Please see web page at <http://www.pkunity.com/>. + +config HAVE_PWM + bool + +config GENERIC_GPIO + def_bool y + +config GENERIC_CLOCKEVENTS + bool + +config GENERIC_CSUM + def_bool y + +config GENERIC_IOMAP + def_bool y + +config NO_IOPORT + bool + +config STACKTRACE_SUPPORT + def_bool y + +config HAVE_LATENCYTOP_SUPPORT + def_bool y + +config LOCKDEP_SUPPORT + def_bool y + +config RWSEM_GENERIC_SPINLOCK + def_bool y + +config RWSEM_XCHGADD_ALGORITHM + bool + +config ARCH_HAS_ILOG2_U32 + bool + +config ARCH_HAS_ILOG2_U64 + bool + +config ARCH_HAS_CPUFREQ + bool + +config GENERIC_HWEIGHT + def_bool y + +config GENERIC_CALIBRATE_DELAY + def_bool y + +config ARCH_MAY_HAVE_PC_FDC + bool + +config NEED_DMA_MAP_STATE + def_bool y + +source "init/Kconfig" + +source "kernel/Kconfig.freezer" + +menu "System Type" + +config MMU + def_bool y + +config ARCH_FPGA + bool + +config ARCH_PUV3 + def_bool y + select CPU_UCV2 + select GENERIC_CLOCKEVENTS + select HAVE_CLK + select ARCH_REQUIRE_GPIOLIB + select ARCH_HAS_CPUFREQ + +# CONFIGs for ARCH_PUV3 + +if ARCH_PUV3 + +choice + prompt "Board Selection" + default PUV3_DB0913 + +config PUV3_FPGA_DLX200 + select ARCH_FPGA + bool "FPGA board" + +config PUV3_DB0913 + bool "DEBUG board (0913)" + +config PUV3_NB0916 + bool "NetBook board (0916)" + select HAVE_PWM + +config PUV3_SMW0919 + bool "Security Mini-Workstation board (0919)" + +endchoice + +config PUV3_PM + def_bool y if !ARCH_FPGA + +endif + +source "arch/unicore32/mm/Kconfig" + +comment "Floating poing support" + +config UNICORE_FPU_F64 + def_bool y if !ARCH_FPGA + +endmenu + +menu "Bus support" + +config PCI + bool "PCI Support" + help + Find out whether you have a PCI motherboard. PCI is the name of a + bus system, i.e. the way the CPU talks to the other stuff inside + your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or + VESA. If you have PCI, say Y, otherwise N. + +source "drivers/pci/Kconfig" + +source "drivers/pcmcia/Kconfig" + +endmenu + +menu "Kernel Features" + +source "kernel/time/Kconfig" + +source "kernel/Kconfig.preempt" + +source "kernel/Kconfig.hz" + +source "mm/Kconfig" + +config LEDS + def_bool y + depends on GENERIC_GPIO + +config ALIGNMENT_TRAP + def_bool y + help + Unicore processors can not fetch/store information which is not + naturally aligned on the bus, i.e., a 4 byte fetch must start at an + address divisible by 4. On 32-bit Unicore processors, these non-aligned + fetch/store instructions will be emulated in software if you say + here, which has a severe performance impact. This is necessary for + correct operation of some network protocols. With an IP-only + configuration it is safe to say N, otherwise say Y. + +endmenu + +menu "Boot options" + +config CMDLINE + string "Default kernel command string" + default "" + +config CMDLINE_FORCE + bool "Always use the default kernel command string" + depends on CMDLINE != "" + help + Always use the default kernel command string, even if the boot + loader passes other arguments to the kernel. + This is useful if you cannot or don't want to change the + command-line options your boot loader passes to the kernel. + + If unsure, say N. + +endmenu + +menu "Userspace binary formats" + +source "fs/Kconfig.binfmt" + +endmenu + +menu "Power management options" + +source "kernel/power/Kconfig" + +if ARCH_HAS_CPUFREQ +source "drivers/cpufreq/Kconfig" +endif + +config ARCH_SUSPEND_POSSIBLE + def_bool y if !ARCH_FPGA + +config ARCH_HIBERNATION_POSSIBLE + def_bool y if !ARCH_FPGA + +endmenu + +source "net/Kconfig" + +if ARCH_PUV3 + +config PUV3_GPIO + bool + depends on !ARCH_FPGA + select GENERIC_GPIO + select GPIO_SYSFS if EXPERIMENTAL + default y + +config PUV3_PWM + tristate + default BACKLIGHT_PWM + help + Enable support for NB0916 PWM controllers + +config PUV3_RTC + tristate "PKUnity v3 RTC Support" + depends on !ARCH_FPGA + +if PUV3_NB0916 + +menu "PKUnity NetBook-0916 Features" + +config I2C_BATTERY_BQ27200 + tristate "I2C Battery BQ27200 Support" + select PUV3_I2C + select POWER_SUPPLY + select BATTERY_BQ27x00 + +config I2C_EEPROM_AT24 + tristate "I2C EEPROMs AT24 support" + select PUV3_I2C + select MISC_DEVICES + select EEPROM_AT24 + +config LCD_BACKLIGHT + tristate "LCD Backlight support" + select BACKLIGHT_LCD_SUPPORT + select BACKLIGHT_PWM + +endmenu + +endif + +endif + +source "drivers/Kconfig" + +source "fs/Kconfig" + +source "arch/unicore32/Kconfig.debug" + +source "security/Kconfig" + +source "crypto/Kconfig" + +source "lib/Kconfig" diff --git a/arch/unicore32/Kconfig.debug b/arch/unicore32/Kconfig.debug new file mode 100644 index 000000000000..3140151ede45 --- /dev/null +++ b/arch/unicore32/Kconfig.debug @@ -0,0 +1,68 @@ +menu "Kernel hacking" + +source "lib/Kconfig.debug" + +config STRICT_DEVMEM + bool "Filter access to /dev/mem" + depends on MMU + ---help--- + If this option is disabled, you allow userspace (root) access to all + of memory, including kernel and userspace memory. Accidental + access to this is obviously disastrous, but specific access can + be used by people debugging the kernel. + + If this option is switched on, the /dev/mem file only allows + userspace access to memory mapped peripherals. + + If in doubt, say Y. + +config EARLY_PRINTK + def_bool DEBUG_OCD + help + Write kernel log output directly into the ocd or to a serial port. + + This is useful for kernel debugging when your machine crashes very + early before the console code is initialized. For normal operation + it is not recommended because it looks ugly and doesn't cooperate + with klogd/syslogd or the X server. You should normally N here, + unless you want to debug such a crash. + +config DEBUG_STACK_USAGE + bool "Enable stack utilization instrumentation" + depends on DEBUG_KERNEL + help + Enables the display of the minimum amount of free stack which each + task has ever had available in the sysrq-T output. + +# These options are only for real kernel hackers who want to get their hands dirty. +config DEBUG_LL + bool "Kernel low-level debugging functions" + depends on DEBUG_KERNEL + help + Say Y here to include definitions of printascii, printch, printhex + in the kernel. This is helpful if you are debugging code that + executes before the console is initialized. + +config DEBUG_OCD + bool "Kernel low-level debugging via On-Chip-Debugger" + depends on DEBUG_LL + default y + help + Say Y here if you want the debug print routines to direct their + output to the UniCore On-Chip-Debugger channel using CP #1. + +config DEBUG_OCD_BREAKPOINT + bool "Breakpoint support via On-Chip-Debugger" + depends on DEBUG_OCD + +config DEBUG_UART + int "Kernel low-level debugging messages via serial port" + depends on DEBUG_LL + range 0 1 + default "0" + help + Choice for UART for kernel low-level using PKUnity UARTS, + should be between zero and one. The port must have been + initialised by the boot-loader before use. + +endmenu diff --git a/arch/unicore32/Makefile b/arch/unicore32/Makefile new file mode 100644 index 000000000000..e08d6d370a8a --- /dev/null +++ b/arch/unicore32/Makefile @@ -0,0 +1,95 @@ +# +# arch/unicore32/Makefile +# +# This file is included by the global makefile so that you can add your own +# architecture-specific flags and dependencies. +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# +# Copyright (C) 2002~2010 by Guan Xue-tao +# +ifneq ($(SUBARCH),$(ARCH)) + ifeq ($(CROSS_COMPILE),) + CROSS_COMPILE := $(call cc-cross-prefix, unicore32-linux-) + endif +endif + +LDFLAGS_vmlinux := -p --no-undefined -X + +OBJCOPYFLAGS := -O binary -R .note -R .note.gnu.build-id -R .comment -S + +# Never generate .eh_frame +KBUILD_CFLAGS += $(call cc-option,-fno-dwarf2-cfi-asm) + +# Never use hard float in kernel +KBUILD_CFLAGS += -msoft-float + +ifeq ($(CONFIG_FRAME_POINTER),y) +KBUILD_CFLAGS += -mno-sched-prolog +endif + +CHECKFLAGS += -D__unicore32__ + +head-y := arch/unicore32/kernel/head.o +head-y += arch/unicore32/kernel/init_task.o + +core-y += arch/unicore32/kernel/ +core-y += arch/unicore32/mm/ + +libs-y += arch/unicore32/lib/ + +ASM_GENERATED_DIR := $(srctree)/arch/unicore32/include/generated +LINUXINCLUDE += -I$(ASM_GENERATED_DIR) + +ASM_GENERIC_HEADERS := atomic.h auxvec.h +ASM_GENERIC_HEADERS += bitsperlong.h bug.h bugs.h +ASM_GENERIC_HEADERS += cputime.h current.h +ASM_GENERIC_HEADERS += device.h div64.h +ASM_GENERIC_HEADERS += emergency-restart.h errno.h +ASM_GENERIC_HEADERS += fb.h fcntl.h ftrace.h +ASM_GENERIC_HEADERS += hardirq.h hw_irq.h +ASM_GENERIC_HEADERS += ioctl.h ioctls.h ipcbuf.h irq_regs.h +ASM_GENERIC_HEADERS += kdebug.h kmap_types.h +ASM_GENERIC_HEADERS += local.h +ASM_GENERIC_HEADERS += mman.h module.h msgbuf.h +ASM_GENERIC_HEADERS += param.h parport.h percpu.h poll.h posix_types.h +ASM_GENERIC_HEADERS += resource.h +ASM_GENERIC_HEADERS += scatterlist.h sections.h segment.h sembuf.h serial.h +ASM_GENERIC_HEADERS += setup.h shmbuf.h shmparam.h +ASM_GENERIC_HEADERS += siginfo.h signal.h sizes.h +ASM_GENERIC_HEADERS += socket.h sockios.h stat.h statfs.h swab.h syscalls.h +ASM_GENERIC_HEADERS += termbits.h termios.h topology.h types.h +ASM_GENERIC_HEADERS += ucontext.h unaligned.h user.h +ASM_GENERIC_HEADERS += vga.h +ASM_GENERIC_HEADERS += xor.h + +archprepare: +ifneq ($(ASM_GENERATED_DIR), $(wildcard $(ASM_GENERATED_DIR))) + $(Q)mkdir -p $(ASM_GENERATED_DIR)/asm + $(Q)$(foreach a, $(ASM_GENERIC_HEADERS), \ + echo '#include <asm-generic/$a>' \ + > $(ASM_GENERATED_DIR)/asm/$a; ) +endif + +boot := arch/unicore32/boot + +# Default target when executing plain make +KBUILD_IMAGE := zImage + +all: $(KBUILD_IMAGE) + +zImage Image uImage: vmlinux + $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ + +MRPROPER_DIRS += $(ASM_GENERATED_DIR) + +archclean: + $(Q)$(MAKE) $(clean)=$(boot) + +define archhelp + echo '* zImage - Compressed kernel image (arch/$(ARCH)/boot/zImage)' + echo ' Image - Uncompressed kernel image (arch/$(ARCH)/boot/Image)' + echo ' uImage - U-Boot wrapped zImage' +endef diff --git a/arch/unicore32/boot/Makefile b/arch/unicore32/boot/Makefile new file mode 100644 index 000000000000..79e5f88845d9 --- /dev/null +++ b/arch/unicore32/boot/Makefile @@ -0,0 +1,47 @@ +# +# arch/unicore32/boot/Makefile +# +# This file is included by the global makefile so that you can add your own +# architecture-specific flags and dependencies. +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# +# Copyright (C) 2001~2010 GUAN Xue-tao +# + +MKIMAGE := $(srctree)/scripts/mkuboot.sh + +targets := Image zImage uImage + +$(obj)/Image: vmlinux FORCE + $(call if_changed,objcopy) + @echo ' Kernel: $@ is ready' + +$(obj)/compressed/vmlinux: $(obj)/Image FORCE + $(Q)$(MAKE) $(build)=$(obj)/compressed $@ + +$(obj)/zImage: $(obj)/compressed/vmlinux FORCE + $(call if_changed,objcopy) + @echo ' Kernel: $@ is ready' + +quiet_cmd_uimage = UIMAGE $@ + cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A unicore -O linux -T kernel \ + -C none -a $(LOADADDR) -e $(STARTADDR) \ + -n 'Linux-$(KERNELRELEASE)' -d $< $@ + +$(obj)/uImage: LOADADDR=0x0 + +$(obj)/uImage: STARTADDR=$(LOADADDR) + +$(obj)/uImage: $(obj)/zImage FORCE + $(call if_changed,uimage) + @echo ' Image $@ is ready' + +PHONY += initrd FORCE +initrd: + @test "$(INITRD)" != "" || \ + (echo You must specify INITRD; exit -1) + +subdir- := compressed diff --git a/arch/unicore32/boot/compressed/Makefile b/arch/unicore32/boot/compressed/Makefile new file mode 100644 index 000000000000..95373428cb3d --- /dev/null +++ b/arch/unicore32/boot/compressed/Makefile @@ -0,0 +1,68 @@ +# +# linux/arch/unicore32/boot/compressed/Makefile +# +# create a compressed vmlinuz image from the original vmlinux +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# +# Copyright (C) 2001~2010 GUAN Xue-tao +# + +EXTRA_CFLAGS := -fpic -fno-builtin +EXTRA_AFLAGS := -Wa,-march=all + +OBJS := misc.o + +# font.c and font.o +CFLAGS_font.o := -Dstatic= +$(obj)/font.c: $(srctree)/drivers/video/console/font_8x8.c + $(call cmd,shipped) + +# piggy.S and piggy.o +suffix_$(CONFIG_KERNEL_GZIP) := gzip +suffix_$(CONFIG_KERNEL_BZIP2) := bz2 +suffix_$(CONFIG_KERNEL_LZO) := lzo +suffix_$(CONFIG_KERNEL_LZMA) := lzma + +$(obj)/piggy.$(suffix_y): $(obj)/../Image FORCE + $(call if_changed,$(suffix_y)) + +SEDFLAGS_piggy = s/DECOMP_SUFFIX/$(suffix_y)/ +$(obj)/piggy.S: $(obj)/piggy.S.in + @sed "$(SEDFLAGS_piggy)" < $< > $@ + +$(obj)/piggy.o: $(obj)/piggy.$(suffix_y) $(obj)/piggy.S FORCE + +targets := vmlinux vmlinux.lds font.o font.c head.o misc.o \ + piggy.$(suffix_y) piggy.o piggy.S \ + +# Make sure files are removed during clean +extra-y += piggy.gzip piggy.bz2 piggy.lzo piggy.lzma + +# ? +LDFLAGS_vmlinux += -p +# Report unresolved symbol references +LDFLAGS_vmlinux += --no-undefined +# Delete all temporary local symbols +LDFLAGS_vmlinux += -X +# Next argument is a linker script +LDFLAGS_vmlinux += -T + +# For uidivmod +$(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/head.o $(obj)/piggy.o \ + $(obj)/misc.o FORCE + $(call if_changed,ld) + @: + +# We now have a PIC decompressor implementation. Decompressors running +# from RAM should not define ZTEXTADDR. Decompressors running directly +# from ROM or Flash must define ZTEXTADDR (preferably via the config) +ZTEXTADDR := 0 +ZBSSADDR := ALIGN(4) + +SEDFLAGS_lds = s/TEXT_START/$(ZTEXTADDR)/;s/BSS_START/$(ZBSSADDR)/ +$(obj)/vmlinux.lds: $(obj)/vmlinux.lds.in arch/unicore32/boot/Makefile $(KCONFIG_CONFIG) + @sed "$(SEDFLAGS_lds)" < $< > $@ + diff --git a/arch/unicore32/boot/compressed/head.S b/arch/unicore32/boot/compressed/head.S new file mode 100644 index 000000000000..fbd1e374c685 --- /dev/null +++ b/arch/unicore32/boot/compressed/head.S @@ -0,0 +1,204 @@ +/* + * linux/arch/unicore32/boot/compressed/head.S + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/linkage.h> +#include <mach/memory.h> + +#define csub cmpsub +#define cand cmpand +#define nop8 nop; nop; nop; nop; nop; nop; nop; nop + + .section ".start", #alloc, #execinstr + .text +start: + .type start,#function + + /* Initialize ASR, PRIV mode and INTR off */ + mov r0, #0xD3 + mov.a asr, r0 + + adr r0, LC0 + ldm (r1, r2, r3, r5, r6, r7, r8), [r0]+ + ldw sp, [r0+], #28 + sub.a r0, r0, r1 @ calculate the delta offset + + /* + * if delta is zero, we are running at the address + * we were linked at. + */ + beq not_relocated + + /* + * We're running at a different address. We need to fix + * up various pointers: + * r5 - zImage base address (_start) + * r7 - GOT start + * r8 - GOT end + */ + add r5, r5, r0 + add r7, r7, r0 + add r8, r8, r0 + + /* + * we need to fix up pointers into the BSS region. + * r2 - BSS start + * r3 - BSS end + * sp - stack pointer + */ + add r2, r2, r0 + add r3, r3, r0 + add sp, sp, r0 + + /* + * Relocate all entries in the GOT table. + * This fixes up the C references. + * r7 - GOT start + * r8 - GOT end + */ +1001: ldw r1, [r7+], #0 + add r1, r1, r0 + stw.w r1, [r7]+, #4 + csub.a r7, r8 + bub 1001b + +not_relocated: + /* + * Clear BSS region. + * r2 - BSS start + * r3 - BSS end + */ + mov r0, #0 +1002: stw.w r0, [r2]+, #4 + csub.a r2, r3 + bub 1002b + + /* + * Turn on the cache. + */ + mov r0, #0 + movc p0.c5, r0, #28 @ cache invalidate all + nop8 + movc p0.c6, r0, #6 @ tlb invalidate all + nop8 + + mov r0, #0x1c @ en icache and wb dcache + movc p0.c1, r0, #0 + nop8 + + /* + * Set up some pointers, for starting decompressing. + */ + + mov r1, sp @ malloc space above stack + add r2, sp, #0x10000 @ 64k max + + /* + * Check to see if we will overwrite ourselves. + * r4 = final kernel address + * r5 = start of this image + * r6 = size of decompressed image + * r2 = end of malloc space (and therefore this image) + * We basically want: + * r4 >= r2 -> OK + * r4 + image length <= r5 -> OK + */ + ldw r4, =KERNEL_IMAGE_START + csub.a r4, r2 + bea wont_overwrite + add r0, r4, r6 + csub.a r0, r5 + beb wont_overwrite + + /* + * If overwrite, just print error message + */ + b __error_overwrite + + /* + * We're not in danger of overwriting ourselves. + * Do this the simple way. + */ +wont_overwrite: + /* + * decompress_kernel: + * r0: output_start + * r1: free_mem_ptr_p + * r2: free_mem_ptr_end_p + */ + mov r0, r4 + b.l decompress_kernel @ C functions + + /* + * Clean and flush the cache to maintain consistency. + */ + mov r0, #0 + movc p0.c5, r0, #14 @ flush dcache + nop8 + movc p0.c5, r0, #20 @ icache invalidate all + nop8 + + /* + * Turn off the Cache and MMU. + */ + mov r0, #0 @ disable i/d cache and MMU + movc p0.c1, r0, #0 + nop8 + + mov r0, #0 @ must be zero + ldw r4, =KERNEL_IMAGE_START + mov pc, r4 @ call kernel + + + .align 2 + .type LC0, #object +LC0: .word LC0 @ r1 + .word __bss_start @ r2 + .word _end @ r3 + .word _start @ r5 + .word _image_size @ r6 + .word _got_start @ r7 + .word _got_end @ r8 + .word decompress_stack_end @ sp + .size LC0, . - LC0 + +print_string: +#ifdef CONFIG_DEBUG_OCD +2001: ldb.w r1, [r0]+, #1 + csub.a r1, #0 + bne 2002f + mov pc, lr +2002: + movc r2, p1.c0, #0 + cand.a r2, #2 + bne 2002b + movc p1.c1, r1, #1 + csub.a r1, #'\n' + cmoveq r1, #'\r' + beq 2002b + b 2001b +#else + mov pc, lr +#endif + +__error_overwrite: + adr r0, str_error + b.l print_string +2001: nop8 + b 2001b +str_error: .asciz "\nError: Kernel address OVERWRITE\n" + .align + + .ltorg + + .align 4 + .section ".stack", "aw", %nobits +decompress_stack: .space 4096 +decompress_stack_end: diff --git a/arch/unicore32/boot/compressed/misc.c b/arch/unicore32/boot/compressed/misc.c new file mode 100644 index 000000000000..176d5bda3559 --- /dev/null +++ b/arch/unicore32/boot/compressed/misc.c @@ -0,0 +1,126 @@ +/* + * linux/arch/unicore32/boot/compressed/misc.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <asm/unaligned.h> +#include <mach/uncompress.h> + +/* + * gzip delarations + */ +unsigned char *output_data; +unsigned long output_ptr; + +unsigned int free_mem_ptr; +unsigned int free_mem_end_ptr; + +#define STATIC static +#define STATIC_RW_DATA /* non-static please */ + +/* + * arch-dependent implementations + */ +#ifndef ARCH_HAVE_DECOMP_ERROR +#define arch_decomp_error(x) +#endif + +#ifndef ARCH_HAVE_DECOMP_SETUP +#define arch_decomp_setup() +#endif + +#ifndef ARCH_HAVE_DECOMP_PUTS +#define arch_decomp_puts(p) +#endif + +void *memcpy(void *dest, const void *src, size_t n) +{ + int i = 0; + unsigned char *d = (unsigned char *)dest, *s = (unsigned char *)src; + + for (i = n >> 3; i > 0; i--) { + *d++ = *s++; + *d++ = *s++; + *d++ = *s++; + *d++ = *s++; + *d++ = *s++; + *d++ = *s++; + *d++ = *s++; + *d++ = *s++; + } + + if (n & 1 << 2) { + *d++ = *s++; + *d++ = *s++; + *d++ = *s++; + *d++ = *s++; + } + + if (n & 1 << 1) { + *d++ = *s++; + *d++ = *s++; + } + + if (n & 1) + *d++ = *s++; + + return dest; +} + +void error(char *x) +{ + arch_decomp_puts("\n\n"); + arch_decomp_puts(x); + arch_decomp_puts("\n\n -- System halted"); + + arch_decomp_error(x); + + for (;;) + ; /* Halt */ +} + +/* Heap size should be adjusted for different decompress method */ +#ifdef CONFIG_KERNEL_GZIP +#include "../../../../lib/decompress_inflate.c" +#endif + +#ifdef CONFIG_KERNEL_BZIP2 +#include "../../../../lib/decompress_bunzip2.c" +#endif + +#ifdef CONFIG_KERNEL_LZO +#include "../../../../lib/decompress_unlzo.c" +#endif + +#ifdef CONFIG_KERNEL_LZMA +#include "../../../../lib/decompress_unlzma.c" +#endif + +unsigned long decompress_kernel(unsigned long output_start, + unsigned long free_mem_ptr_p, + unsigned long free_mem_ptr_end_p) +{ + unsigned char *tmp; + + output_data = (unsigned char *)output_start; + free_mem_ptr = free_mem_ptr_p; + free_mem_end_ptr = free_mem_ptr_end_p; + + arch_decomp_setup(); + + tmp = (unsigned char *) (((unsigned long)input_data_end) - 4); + output_ptr = get_unaligned_le32(tmp); + + arch_decomp_puts("Uncompressing Linux..."); + decompress(input_data, input_data_end - input_data, NULL, NULL, + output_data, NULL, error); + arch_decomp_puts(" done, booting the kernel.\n"); + return output_ptr; +} diff --git a/arch/unicore32/boot/compressed/piggy.S.in b/arch/unicore32/boot/compressed/piggy.S.in new file mode 100644 index 000000000000..b79704d58026 --- /dev/null +++ b/arch/unicore32/boot/compressed/piggy.S.in @@ -0,0 +1,6 @@ + .section .piggydata,#alloc + .globl input_data +input_data: + .incbin "arch/unicore32/boot/compressed/piggy.DECOMP_SUFFIX" + .globl input_data_end +input_data_end: diff --git a/arch/unicore32/boot/compressed/vmlinux.lds.in b/arch/unicore32/boot/compressed/vmlinux.lds.in new file mode 100644 index 000000000000..d5a3ce296239 --- /dev/null +++ b/arch/unicore32/boot/compressed/vmlinux.lds.in @@ -0,0 +1,61 @@ +/* + * linux/arch/unicore/boot/compressed/vmlinux.lds.in + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +OUTPUT_ARCH(unicore32) +ENTRY(_start) +SECTIONS +{ + /DISCARD/ : { + /* + * Discard any r/w data - this produces a link error if we have any, + * which is required for PIC decompression. Local data generates + * GOTOFF relocations, which prevents it being relocated independently + * of the text/got segments. + */ + *(.data) + } + + . = TEXT_START; + _text = .; + + .text : { + _start = .; + *(.start) + *(.text) + *(.text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata) + *(.rodata.*) + *(.piggydata) + . = ALIGN(4); + } + + _etext = .; + + /* Assume size of decompressed image is 4x the compressed image */ + _image_size = (_etext - _text) * 4; + + _got_start = .; + .got : { *(.got) } + _got_end = .; + .got.plt : { *(.got.plt) } + _edata = .; + + . = BSS_START; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + + .stack : { *(.stack) } + .comment 0 : { *(.comment) } +} + diff --git a/arch/unicore32/configs/debug_defconfig b/arch/unicore32/configs/debug_defconfig new file mode 100644 index 000000000000..b5fbde9f1cb2 --- /dev/null +++ b/arch/unicore32/configs/debug_defconfig @@ -0,0 +1,215 @@ +### General setup +CONFIG_EXPERIMENTAL=y +CONFIG_LOCALVERSION="-debug" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_HOTPLUG=y +# Initial RAM filesystem and RAM disk (initramfs/initrd) support +#CONFIG_BLK_DEV_INITRD=y +#CONFIG_INITRAMFS_SOURCE="arch/unicore/ramfs/ramfs_config" + +### Enable loadable module support +CONFIG_MODULES=n +CONFIG_MODULE_UNLOAD=y + +### System Type +CONFIG_ARCH_PUV3=y +# Board Selection +CONFIG_PUV3_NB0916=y +# Processor Features +CONFIG_CPU_DCACHE_LINE_DISABLE=y +CONFIG_CPU_TLB_SINGLE_ENTRY_DISABLE=n + +### Bus support +CONFIG_PCI=y +CONFIG_PCI_LEGACY=n + +### Boot options +# for debug, adding: earlyprintk=ocd,keep initcall_debug +# others support: test_suspend=mem root=/dev/sda +# hibernate support: resume=/dev/sda3 +CONFIG_CMDLINE="earlyprintk=ocd,keep ignore_loglevel" +# TODO: mem=512M video=unifb:1024x600-16@75 +# for nfs: root=/dev/nfs rw nfsroot=192.168.10.88:/home/udb/nfs/,rsize=1024,wsize=1024 +# ip=192.168.10.83:192.168.10.88:192.168.10.1:255.255.255.0::eth0:off +CONFIG_CMDLINE_FORCE=y + +### Power management options +CONFIG_PM=y +CONFIG_HIBERNATION=y +CONFIG_PM_STD_PARTITION="/dev/sda3" +CONFIG_CPU_FREQ=n +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y + +### Networking support +CONFIG_NET=y +# Networking options +CONFIG_PACKET=m +CONFIG_UNIX=m +# TCP/IP networking +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IPV6=n +# Wireless +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_MAC80211=m + +### PKUnity SoC Features +CONFIG_USB_WLAN_HED_AQ3=n +CONFIG_USB_CMMB_INNOFIDEI=n +CONFIG_I2C_BATTERY_BQ27200=n +CONFIG_I2C_EEPROM_AT24=n +CONFIG_LCD_BACKLIGHT=n + +CONFIG_PUV3_RTC=y +CONFIG_PUV3_UMAL=y +CONFIG_PUV3_MUSB=n +CONFIG_PUV3_AC97=n +CONFIG_PUV3_NAND=n +CONFIG_PUV3_MMC=n +CONFIG_PUV3_UART=n + +### Device Drivers +# Memory Technology Device (MTD) support +CONFIG_MTD=m +CONFIG_MTD_UBI=m +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_CHAR=m +CONFIG_MTD_BLKDEVS=m +# RAM/ROM/Flash chip drivers +CONFIG_MTD_CFI=m +CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_CFI_AMDSTD=m +# Mapping drivers for chip access +CONFIG_MTD_PHYSMAP=m + +# Block devices +CONFIG_BLK_DEV_LOOP=m + +# SCSI device support +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m + +# Serial ATA (prod) and Parallel ATA (experimental) drivers +CONFIG_ATA=y +CONFIG_SATA_VIA=y + +# Network device support +CONFIG_NETDEVICES=y +CONFIG_NET_ETHERNET=y +CONFIG_NETDEV_1000=y +# Wireless LAN +CONFIG_WLAN_80211=n +CONFIG_RT2X00=n +CONFIG_RT73USB=n + +# Input device support +CONFIG_INPUT_EVDEV=m +# Keyboards +CONFIG_KEYBOARD_GPIO=m + +# I2C support +CONFIG_I2C=y +CONFIG_I2C_PUV3=y + +# Hardware Monitoring support +#CONFIG_SENSORS_LM75=m +# Generic Thermal sysfs driver +#CONFIG_THERMAL=m +#CONFIG_THERMAL_HWMON=y + +# Multimedia support +CONFIG_MEDIA_SUPPORT=n +CONFIG_VIDEO_DEV=n +CONFIG_USB_VIDEO_CLASS=n + +# Graphics support +CONFIG_FB=y +CONFIG_FB_PUV3_UNIGFX=y +# Console display driver support +CONFIG_VGA_CONSOLE=n +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# Bootup logo +CONFIG_LOGO=n + +# Sound card support +CONFIG_SOUND=m +# Advanced Linux Sound Architecture +CONFIG_SND=m +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m + +# USB support +CONFIG_USB_ARCH_HAS_HCD=n +CONFIG_USB=n +CONFIG_USB_DEVICEFS=n +CONFIG_USB_PRINTER=n +CONFIG_USB_STORAGE=n +# Inventra Highspeed Dual Role Controller +CONFIG_USB_MUSB_HDRC=n + +# LED Support +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +# LED Triggers +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_IDE_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y + +# Real Time Clock +CONFIG_RTC_LIB=m +CONFIG_RTC_CLASS=m + +### File systems +CONFIG_EXT2_FS=m +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS=y +CONFIG_FUSE_FS=m +# CD-ROM/DVD Filesystems +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_UDF_FS=m +# DOS/FAT/NT Filesystems +CONFIG_VFAT_FS=m +# Pseudo filesystems +CONFIG_PROC_FS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# Miscellaneous filesystems +CONFIG_MISC_FILESYSTEMS=y +CONFIG_JFFS2_FS=m +CONFIG_UBIFS_FS=m +# Network File Systems +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +# Partition Types +CONFIG_PARTITION_ADVANCED=y +CONFIG_MSDOS_PARTITION=y +# Native language support +CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_UTF8=m + +### Kernel hacking +CONFIG_FRAME_WARN=8096 +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +CONFIG_PROVE_LOCKING=n +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +CONFIG_DEBUG_LL=y + diff --git a/arch/unicore32/include/asm/Kbuild b/arch/unicore32/include/asm/Kbuild new file mode 100644 index 000000000000..b200fdaca44d --- /dev/null +++ b/arch/unicore32/include/asm/Kbuild @@ -0,0 +1,2 @@ +include include/asm-generic/Kbuild.asm + diff --git a/arch/unicore32/include/asm/assembler.h b/arch/unicore32/include/asm/assembler.h new file mode 100644 index 000000000000..8e87ed7faeba --- /dev/null +++ b/arch/unicore32/include/asm/assembler.h @@ -0,0 +1,131 @@ +/* + * linux/arch/unicore32/include/asm/assembler.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Do not include any C declarations in this file - it is included by + * assembler source. + */ +#ifndef __ASSEMBLY__ +#error "Only include this from assembly code" +#endif + +#include <asm/ptrace.h> + +/* + * Little Endian independent macros for shifting bytes within registers. + */ +#define pull >> +#define push << +#define get_byte_0 << #0 +#define get_byte_1 >> #8 +#define get_byte_2 >> #16 +#define get_byte_3 >> #24 +#define put_byte_0 << #0 +#define put_byte_1 << #8 +#define put_byte_2 << #16 +#define put_byte_3 << #24 + +#define cadd cmpadd +#define cand cmpand +#define csub cmpsub +#define cxor cmpxor + +/* + * Enable and disable interrupts + */ + .macro disable_irq, temp + mov \temp, asr + andn \temp, \temp, #0xFF + or \temp, \temp, #PSR_I_BIT | PRIV_MODE + mov.a asr, \temp + .endm + + .macro enable_irq, temp + mov \temp, asr + andn \temp, \temp, #0xFF + or \temp, \temp, #PRIV_MODE + mov.a asr, \temp + .endm + +#define USER(x...) \ +9999: x; \ + .pushsection __ex_table, "a"; \ + .align 3; \ + .long 9999b, 9001f; \ + .popsection + + .macro notcond, cond, nexti = .+8 + .ifc \cond, eq + bne \nexti + .else; .ifc \cond, ne + beq \nexti + .else; .ifc \cond, ea + bub \nexti + .else; .ifc \cond, ub + bea \nexti + .else; .ifc \cond, fs + bns \nexti + .else; .ifc \cond, ns + bfs \nexti + .else; .ifc \cond, fv + bnv \nexti + .else; .ifc \cond, nv + bfv \nexti + .else; .ifc \cond, ua + beb \nexti + .else; .ifc \cond, eb + bua \nexti + .else; .ifc \cond, eg + bsl \nexti + .else; .ifc \cond, sl + beg \nexti + .else; .ifc \cond, sg + bel \nexti + .else; .ifc \cond, el + bsg \nexti + .else; .ifnc \cond, al + .error "Unknown cond in notcond macro argument" + .endif; .endif; .endif; .endif; .endif; .endif; .endif + .endif; .endif; .endif; .endif; .endif; .endif; .endif + .endif + .endm + + .macro usracc, instr, reg, ptr, inc, cond, rept, abort + .rept \rept + notcond \cond, .+8 +9999 : + .if \inc == 1 + \instr\()b.u \reg, [\ptr], #\inc + .elseif \inc == 4 + \instr\()w.u \reg, [\ptr], #\inc + .else + .error "Unsupported inc macro argument" + .endif + + .pushsection __ex_table, "a" + .align 3 + .long 9999b, \abort + .popsection + .endr + .endm + + .macro strusr, reg, ptr, inc, cond = al, rept = 1, abort = 9001f + usracc st, \reg, \ptr, \inc, \cond, \rept, \abort + .endm + + .macro ldrusr, reg, ptr, inc, cond = al, rept = 1, abort = 9001f + usracc ld, \reg, \ptr, \inc, \cond, \rept, \abort + .endm + + .macro nop8 + .rept 8 + nop + .endr + .endm diff --git a/arch/unicore32/include/asm/bitops.h b/arch/unicore32/include/asm/bitops.h new file mode 100644 index 000000000000..1628a6328994 --- /dev/null +++ b/arch/unicore32/include/asm/bitops.h @@ -0,0 +1,47 @@ +/* + * linux/arch/unicore32/include/asm/bitops.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __UNICORE_BITOPS_H__ +#define __UNICORE_BITOPS_H__ + +#define find_next_bit __uc32_find_next_bit +#define find_next_zero_bit __uc32_find_next_zero_bit + +#define find_first_bit __uc32_find_first_bit +#define find_first_zero_bit __uc32_find_first_zero_bit + +#define _ASM_GENERIC_BITOPS_FLS_H_ +#define _ASM_GENERIC_BITOPS___FLS_H_ +#define _ASM_GENERIC_BITOPS_FFS_H_ +#define _ASM_GENERIC_BITOPS___FFS_H_ +/* + * On UNICORE, those functions can be implemented around + * the cntlz instruction for much better code efficiency. + */ + +static inline int fls(int x) +{ + int ret; + + asm("cntlz\t%0, %1" : "=r" (ret) : "r" (x) : "cc"); + ret = 32 - ret; + + return ret; +} + +#define __fls(x) (fls(x) - 1) +#define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); }) +#define __ffs(x) (ffs(x) - 1) + +#include <asm-generic/bitops.h> + +#endif /* __UNICORE_BITOPS_H__ */ diff --git a/arch/unicore32/include/asm/byteorder.h b/arch/unicore32/include/asm/byteorder.h new file mode 100644 index 000000000000..ebe1b3fef3e3 --- /dev/null +++ b/arch/unicore32/include/asm/byteorder.h @@ -0,0 +1,24 @@ +/* + * linux/arch/unicore32/include/asm/byteorder.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * UniCore ONLY support Little Endian mode, the data bus is connected such + * that byte accesses appear as: + * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 + * and word accesses (data or instruction) appear as: + * d0...d31 + */ +#ifndef __UNICORE_BYTEORDER_H__ +#define __UNICORE_BYTEORDER_H__ + +#include <linux/byteorder/little_endian.h> + +#endif + diff --git a/arch/unicore32/include/asm/cache.h b/arch/unicore32/include/asm/cache.h new file mode 100644 index 000000000000..ad8f795d86ca --- /dev/null +++ b/arch/unicore32/include/asm/cache.h @@ -0,0 +1,27 @@ +/* + * linux/arch/unicore32/include/asm/cache.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_CACHE_H__ +#define __UNICORE_CACHE_H__ + +#define L1_CACHE_SHIFT (5) +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) + +/* + * Memory returned by kmalloc() may be used for DMA, so we must make + * sure that all such allocations are cache aligned. Otherwise, + * unrelated code may cause parts of the buffer to be read into the + * cache before the transfer is done, causing old data to be seen by + * the CPU. + */ +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES + +#endif diff --git a/arch/unicore32/include/asm/cacheflush.h b/arch/unicore32/include/asm/cacheflush.h new file mode 100644 index 000000000000..c0301e6c8b81 --- /dev/null +++ b/arch/unicore32/include/asm/cacheflush.h @@ -0,0 +1,211 @@ +/* + * linux/arch/unicore32/include/asm/cacheflush.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_CACHEFLUSH_H__ +#define __UNICORE_CACHEFLUSH_H__ + +#include <linux/mm.h> + +#include <asm/shmparam.h> + +#define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT) + +/* + * This flag is used to indicate that the page pointed to by a pte is clean + * and does not require cleaning before returning it to the user. + */ +#define PG_dcache_clean PG_arch_1 + +/* + * MM Cache Management + * =================== + * + * The arch/unicore32/mm/cache.S files implement these methods. + * + * Start addresses are inclusive and end addresses are exclusive; + * start addresses should be rounded down, end addresses up. + * + * See Documentation/cachetlb.txt for more information. + * Please note that the implementation of these, and the required + * effects are cache-type (VIVT/VIPT/PIPT) specific. + * + * flush_icache_all() + * + * Unconditionally clean and invalidate the entire icache. + * Currently only needed for cache-v6.S and cache-v7.S, see + * __flush_icache_all for the generic implementation. + * + * flush_kern_all() + * + * Unconditionally clean and invalidate the entire cache. + * + * flush_user_all() + * + * Clean and invalidate all user space cache entries + * before a change of page tables. + * + * flush_user_range(start, end, flags) + * + * Clean and invalidate a range of cache entries in the + * specified address space before a change of page tables. + * - start - user start address (inclusive, page aligned) + * - end - user end address (exclusive, page aligned) + * - flags - vma->vm_flags field + * + * coherent_kern_range(start, end) + * + * Ensure coherency between the Icache and the Dcache in the + * region described by start, end. If you have non-snooping + * Harvard caches, you need to implement this function. + * - start - virtual start address + * - end - virtual end address + * + * coherent_user_range(start, end) + * + * Ensure coherency between the Icache and the Dcache in the + * region described by start, end. If you have non-snooping + * Harvard caches, you need to implement this function. + * - start - virtual start address + * - end - virtual end address + * + * flush_kern_dcache_area(kaddr, size) + * + * Ensure that the data held in page is written back. + * - kaddr - page address + * - size - region size + * + * DMA Cache Coherency + * =================== + * + * dma_flush_range(start, end) + * + * Clean and invalidate the specified virtual address range. + * - start - virtual start address + * - end - virtual end address + */ + +extern void __cpuc_flush_icache_all(void); +extern void __cpuc_flush_kern_all(void); +extern void __cpuc_flush_user_all(void); +extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int); +extern void __cpuc_coherent_kern_range(unsigned long, unsigned long); +extern void __cpuc_coherent_user_range(unsigned long, unsigned long); +extern void __cpuc_flush_dcache_area(void *, size_t); +extern void __cpuc_flush_kern_dcache_area(void *addr, size_t size); + +/* + * These are private to the dma-mapping API. Do not use directly. + * Their sole purpose is to ensure that data held in the cache + * is visible to DMA, or data written by DMA to system memory is + * visible to the CPU. + */ +extern void __cpuc_dma_clean_range(unsigned long, unsigned long); +extern void __cpuc_dma_flush_range(unsigned long, unsigned long); + +/* + * Copy user data from/to a page which is mapped into a different + * processes address space. Really, we want to allow our "user + * space" model to handle this. + */ +extern void copy_to_user_page(struct vm_area_struct *, struct page *, + unsigned long, void *, const void *, unsigned long); +#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ + do { \ + memcpy(dst, src, len); \ + } while (0) + +/* + * Convert calls to our calling convention. + */ +/* Invalidate I-cache */ +static inline void __flush_icache_all(void) +{ + asm("movc p0.c5, %0, #20;\n" + "nop; nop; nop; nop; nop; nop; nop; nop\n" + : + : "r" (0)); +} + +#define flush_cache_all() __cpuc_flush_kern_all() + +extern void flush_cache_mm(struct mm_struct *mm); +extern void flush_cache_range(struct vm_area_struct *vma, + unsigned long start, unsigned long end); +extern void flush_cache_page(struct vm_area_struct *vma, + unsigned long user_addr, unsigned long pfn); + +#define flush_cache_dup_mm(mm) flush_cache_mm(mm) + +/* + * flush_cache_user_range is used when we want to ensure that the + * Harvard caches are synchronised for the user space address range. + * This is used for the UniCore private sys_cacheflush system call. + */ +#define flush_cache_user_range(vma, start, end) \ + __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end)) + +/* + * Perform necessary cache operations to ensure that data previously + * stored within this range of addresses can be executed by the CPU. + */ +#define flush_icache_range(s, e) __cpuc_coherent_kern_range(s, e) + +/* + * Perform necessary cache operations to ensure that the TLB will + * see data written in the specified area. + */ +#define clean_dcache_area(start, size) cpu_dcache_clean_area(start, size) + +/* + * flush_dcache_page is used when the kernel has written to the page + * cache page at virtual address page->virtual. + * + * If this page isn't mapped (ie, page_mapping == NULL), or it might + * have userspace mappings, then we _must_ always clean + invalidate + * the dcache entries associated with the kernel mapping. + * + * Otherwise we can defer the operation, and clean the cache when we are + * about to change to user space. This is the same method as used on SPARC64. + * See update_mmu_cache for the user space part. + */ +#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 +extern void flush_dcache_page(struct page *); + +#define flush_dcache_mmap_lock(mapping) \ + spin_lock_irq(&(mapping)->tree_lock) +#define flush_dcache_mmap_unlock(mapping) \ + spin_unlock_irq(&(mapping)->tree_lock) + +#define flush_icache_user_range(vma, page, addr, len) \ + flush_dcache_page(page) + +/* + * We don't appear to need to do anything here. In fact, if we did, we'd + * duplicate cache flushing elsewhere performed by flush_dcache_page(). + */ +#define flush_icache_page(vma, page) do { } while (0) + +/* + * flush_cache_vmap() is used when creating mappings (eg, via vmap, + * vmalloc, ioremap etc) in kernel space for pages. On non-VIPT + * caches, since the direct-mappings of these pages may contain cached + * data, we need to do a full cache flush to ensure that writebacks + * don't corrupt data placed into these pages via the new mappings. + */ +static inline void flush_cache_vmap(unsigned long start, unsigned long end) +{ +} + +static inline void flush_cache_vunmap(unsigned long start, unsigned long end) +{ +} + +#endif diff --git a/arch/unicore32/include/asm/checksum.h b/arch/unicore32/include/asm/checksum.h new file mode 100644 index 000000000000..f55c3f937c3e --- /dev/null +++ b/arch/unicore32/include/asm/checksum.h @@ -0,0 +1,41 @@ +/* + * linux/arch/unicore32/include/asm/checksum.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * IP checksum routines + */ +#ifndef __UNICORE_CHECKSUM_H__ +#define __UNICORE_CHECKSUM_H__ + +/* + * computes the checksum of the TCP/UDP pseudo-header + * returns a 16-bit checksum, already complemented + */ + +static inline __wsum +csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, + unsigned short proto, __wsum sum) +{ + __asm__( + "add.a %0, %1, %2\n" + "addc.a %0, %0, %3\n" + "addc.a %0, %0, %4 << #8\n" + "addc.a %0, %0, %5\n" + "addc %0, %0, #0\n" + : "=&r"(sum) + : "r" (sum), "r" (daddr), "r" (saddr), "r" (len), "Ir" (htons(proto)) + : "cc"); + return sum; +} +#define csum_tcpudp_nofold csum_tcpudp_nofold + +#include <asm-generic/checksum.h> + +#endif diff --git a/arch/unicore32/include/asm/cpu-single.h b/arch/unicore32/include/asm/cpu-single.h new file mode 100644 index 000000000000..0f55d1823439 --- /dev/null +++ b/arch/unicore32/include/asm/cpu-single.h @@ -0,0 +1,45 @@ +/* + * linux/arch/unicore32/include/asm/cpu-single.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_CPU_SINGLE_H__ +#define __UNICORE_CPU_SINGLE_H__ + +#include <asm/page.h> +#include <asm/memory.h> + +#ifdef __KERNEL__ +#ifndef __ASSEMBLY__ + +#define cpu_switch_mm(pgd, mm) cpu_do_switch_mm(virt_to_phys(pgd), mm) + +#define cpu_get_pgd() \ + ({ \ + unsigned long pg; \ + __asm__("movc %0, p0.c2, #0" \ + : "=r" (pg) : : "cc"); \ + pg &= ~0x0fff; \ + (pgd_t *)phys_to_virt(pg); \ + }) + +struct mm_struct; + +/* declare all the functions as extern */ +extern void cpu_proc_fin(void); +extern int cpu_do_idle(void); +extern void cpu_dcache_clean_area(void *, int); +extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm); +extern void cpu_set_pte(pte_t *ptep, pte_t pte); +extern void cpu_reset(unsigned long addr) __attribute__((noreturn)); + +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL__ */ + +#endif /* __UNICORE_CPU_SINGLE_H__ */ diff --git a/arch/unicore32/include/asm/cputype.h b/arch/unicore32/include/asm/cputype.h new file mode 100644 index 000000000000..ec1a30f98077 --- /dev/null +++ b/arch/unicore32/include/asm/cputype.h @@ -0,0 +1,33 @@ +/* + * linux/arch/unicore32/include/asm/cputype.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_CPUTYPE_H__ +#define __UNICORE_CPUTYPE_H__ + +#include <linux/stringify.h> + +#define CPUID_CPUID 0 +#define CPUID_CACHETYPE 1 + +#define read_cpuid(reg) \ + ({ \ + unsigned int __val; \ + asm("movc %0, p0.c0, #" __stringify(reg) \ + : "=r" (__val) \ + : \ + : "cc"); \ + __val; \ + }) + +#define uc32_cpuid read_cpuid(CPUID_CPUID) +#define uc32_cachetype read_cpuid(CPUID_CACHETYPE) + +#endif diff --git a/arch/unicore32/include/asm/delay.h b/arch/unicore32/include/asm/delay.h new file mode 100644 index 000000000000..164ae61cd6f7 --- /dev/null +++ b/arch/unicore32/include/asm/delay.h @@ -0,0 +1,52 @@ +/* + * linux/arch/unicore32/include/asm/delay.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Delay routines, using a pre-computed "loops_per_second" value. + */ +#ifndef __UNICORE_DELAY_H__ +#define __UNICORE_DELAY_H__ + +#include <asm/param.h> /* HZ */ + +extern void __delay(int loops); + +/* + * This function intentionally does not exist; if you see references to + * it, it means that you're calling udelay() with an out of range value. + * + * With currently imposed limits, this means that we support a max delay + * of 2000us. Further limits: HZ<=1000 and bogomips<=3355 + */ +extern void __bad_udelay(void); + +/* + * division by multiplication: you don't have to worry about + * loss of precision. + * + * Use only for very small delays ( < 1 msec). Should probably use a + * lookup table, really, as the multiplications take much too long with + * short delays. This is a "reasonable" implementation, though (and the + * first constant multiplications gets optimized away if the delay is + * a constant) + */ +extern void __udelay(unsigned long usecs); +extern void __const_udelay(unsigned long); + +#define MAX_UDELAY_MS 2 + +#define udelay(n) \ + (__builtin_constant_p(n) ? \ + ((n) > (MAX_UDELAY_MS * 1000) ? __bad_udelay() : \ + __const_udelay((n) * ((2199023U*HZ)>>11))) : \ + __udelay(n)) + +#endif /* __UNICORE_DELAY_H__ */ + diff --git a/arch/unicore32/include/asm/dma-mapping.h b/arch/unicore32/include/asm/dma-mapping.h new file mode 100644 index 000000000000..9258e592f414 --- /dev/null +++ b/arch/unicore32/include/asm/dma-mapping.h @@ -0,0 +1,124 @@ +/* + * linux/arch/unicore32/include/asm/dma-mapping.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_DMA_MAPPING_H__ +#define __UNICORE_DMA_MAPPING_H__ + +#ifdef __KERNEL__ + +#include <linux/mm_types.h> +#include <linux/scatterlist.h> +#include <linux/swiotlb.h> + +#include <asm-generic/dma-coherent.h> + +#include <asm/memory.h> +#include <asm/cacheflush.h> + +extern struct dma_map_ops swiotlb_dma_map_ops; + +static inline struct dma_map_ops *get_dma_ops(struct device *dev) +{ + return &swiotlb_dma_map_ops; +} + +static inline int dma_supported(struct device *dev, u64 mask) +{ + struct dma_map_ops *dma_ops = get_dma_ops(dev); + + if (unlikely(dma_ops == NULL)) + return 0; + + return dma_ops->dma_supported(dev, mask); +} + +static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) +{ + struct dma_map_ops *dma_ops = get_dma_ops(dev); + + if (dma_ops->mapping_error) + return dma_ops->mapping_error(dev, dma_addr); + + return 0; +} + +#include <asm-generic/dma-mapping-common.h> + +static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) +{ + if (dev && dev->dma_mask) + return addr + size - 1 <= *dev->dma_mask; + + return 1; +} + +static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) +{ + return paddr; +} + +static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr) +{ + return daddr; +} + +static inline void dma_mark_clean(void *addr, size_t size) {} + +static inline int dma_set_mask(struct device *dev, u64 dma_mask) +{ + if (!dev->dma_mask || !dma_supported(dev, dma_mask)) + return -EIO; + + *dev->dma_mask = dma_mask; + + return 0; +} + +static inline void *dma_alloc_coherent(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t flag) +{ + struct dma_map_ops *dma_ops = get_dma_ops(dev); + + return dma_ops->alloc_coherent(dev, size, dma_handle, flag); +} + +static inline void dma_free_coherent(struct device *dev, size_t size, + void *cpu_addr, dma_addr_t dma_handle) +{ + struct dma_map_ops *dma_ops = get_dma_ops(dev); + + dma_ops->free_coherent(dev, size, cpu_addr, dma_handle); +} + +#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) +#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) + +static inline void dma_cache_sync(struct device *dev, void *vaddr, + size_t size, enum dma_data_direction direction) +{ + unsigned long start = (unsigned long)vaddr; + unsigned long end = start + size; + + switch (direction) { + case DMA_NONE: + BUG(); + case DMA_FROM_DEVICE: + case DMA_BIDIRECTIONAL: /* writeback and invalidate */ + __cpuc_dma_flush_range(start, end); + break; + case DMA_TO_DEVICE: /* writeback only */ + __cpuc_dma_clean_range(start, end); + break; + } +} + +#endif /* __KERNEL__ */ +#endif diff --git a/arch/unicore32/include/asm/dma.h b/arch/unicore32/include/asm/dma.h new file mode 100644 index 000000000000..38dfff9df32f --- /dev/null +++ b/arch/unicore32/include/asm/dma.h @@ -0,0 +1,23 @@ +/* + * linux/arch/unicore32/include/asm/dma.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __UNICORE_DMA_H__ +#define __UNICORE_DMA_H__ + +#include <asm/memory.h> +#include <asm-generic/dma.h> + +#ifdef CONFIG_PCI +extern int isa_dma_bridge_buggy; +#endif + +#endif /* __UNICORE_DMA_H__ */ diff --git a/arch/unicore32/include/asm/elf.h b/arch/unicore32/include/asm/elf.h new file mode 100644 index 000000000000..829042d07722 --- /dev/null +++ b/arch/unicore32/include/asm/elf.h @@ -0,0 +1,94 @@ +/* + * linux/arch/unicore32/include/asm/elf.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __UNICORE_ELF_H__ +#define __UNICORE_ELF_H__ + +#include <asm/hwcap.h> + +/* + * ELF register definitions.. + */ +#include <asm/ptrace.h> + +typedef unsigned long elf_greg_t; +typedef unsigned long elf_freg_t[3]; + +#define ELF_NGREG (sizeof(struct pt_regs) / sizeof(elf_greg_t)) +typedef elf_greg_t elf_gregset_t[ELF_NGREG]; + +typedef struct fp_state elf_fpregset_t; + +#define EM_UNICORE 110 + +#define R_UNICORE_NONE 0 +#define R_UNICORE_PC24 1 +#define R_UNICORE_ABS32 2 +#define R_UNICORE_CALL 28 +#define R_UNICORE_JUMP24 29 + +/* + * These are used to set parameters in the core dumps. + */ +#define ELF_CLASS ELFCLASS32 +#define ELF_DATA ELFDATA2LSB +#define ELF_ARCH EM_UNICORE + +/* + * This yields a string that ld.so will use to load implementation + * specific libraries for optimization. This is more specific in + * intent than poking at uname or /proc/cpuinfo. + * + */ +#define ELF_PLATFORM_SIZE 8 +#define ELF_PLATFORM (elf_platform) + +extern char elf_platform[]; + +struct elf32_hdr; + +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +extern int elf_check_arch(const struct elf32_hdr *); +#define elf_check_arch elf_check_arch + +struct task_struct; +int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs); +#define ELF_CORE_COPY_TASK_REGS dump_task_regs + +#define ELF_EXEC_PAGESIZE 4096 + +/* This is the location that an ET_DYN program is loaded if exec'ed. Typical + use of this is to invoke "./ld.so someprog" to test out a new version of + the loader. We need to make sure that it is out of the way of the program + that it will "exec", and that there is sufficient room for the brk. */ + +#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) + +/* When the program starts, a1 contains a pointer to a function to be + registered with atexit, as per the SVR4 ABI. A value of 0 means we + have no such handler. */ +#define ELF_PLAT_INIT(_r, load_addr) {(_r)->UCreg_00 = 0; } + +extern void elf_set_personality(const struct elf32_hdr *); +#define SET_PERSONALITY(ex) elf_set_personality(&(ex)) + +struct mm_struct; +extern unsigned long arch_randomize_brk(struct mm_struct *mm); +#define arch_randomize_brk arch_randomize_brk + +extern int vectors_user_mapping(void); +#define arch_setup_additional_pages(bprm, uses_interp) vectors_user_mapping() +#define ARCH_HAS_SETUP_ADDITIONAL_PAGES + +#endif diff --git a/arch/unicore32/include/asm/fpstate.h b/arch/unicore32/include/asm/fpstate.h new file mode 100644 index 000000000000..ba97fac6220d --- /dev/null +++ b/arch/unicore32/include/asm/fpstate.h @@ -0,0 +1,26 @@ +/* + * linux/arch/unicore32/include/asm/fpstate.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __UNICORE_FPSTATE_H__ +#define __UNICORE_FPSTATE_H__ + +#ifndef __ASSEMBLY__ + +#define FP_REGS_NUMBER 33 + +struct fp_state { + unsigned int regs[FP_REGS_NUMBER]; +} __attribute__((aligned(8))); + +#endif + +#endif diff --git a/arch/unicore32/include/asm/fpu-ucf64.h b/arch/unicore32/include/asm/fpu-ucf64.h new file mode 100644 index 000000000000..16c1457882ee --- /dev/null +++ b/arch/unicore32/include/asm/fpu-ucf64.h @@ -0,0 +1,53 @@ +/* + * linux/arch/unicore32/include/asm/fpu-ucf64.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn> + * Copyright (C) 2001-2010 Guan Xuetao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#define FPSCR s31 + +/* FPSCR bits */ +#define FPSCR_DEFAULT_NAN (1<<25) + +#define FPSCR_CMPINSTR_BIT (1<<31) + +#define FPSCR_CON (1<<29) +#define FPSCR_TRAP (1<<27) + +/* RND mode */ +#define FPSCR_ROUND_NEAREST (0<<0) +#define FPSCR_ROUND_PLUSINF (2<<0) +#define FPSCR_ROUND_MINUSINF (3<<0) +#define FPSCR_ROUND_TOZERO (1<<0) +#define FPSCR_RMODE_BIT (0) +#define FPSCR_RMODE_MASK (7 << FPSCR_RMODE_BIT) + +/* trap enable */ +#define FPSCR_IOE (1<<16) +#define FPSCR_OFE (1<<14) +#define FPSCR_UFE (1<<13) +#define FPSCR_IXE (1<<12) +#define FPSCR_HIE (1<<11) +#define FPSCR_NDE (1<<10) /* non denomal */ + +/* flags */ +#define FPSCR_IDC (1<<24) +#define FPSCR_HIC (1<<23) +#define FPSCR_IXC (1<<22) +#define FPSCR_OFC (1<<21) +#define FPSCR_UFC (1<<20) +#define FPSCR_IOC (1<<19) + +/* stick bits */ +#define FPSCR_IOS (1<<9) +#define FPSCR_OFS (1<<7) +#define FPSCR_UFS (1<<6) +#define FPSCR_IXS (1<<5) +#define FPSCR_HIS (1<<4) +#define FPSCR_NDS (1<<3) /*non denomal */ diff --git a/arch/unicore32/include/asm/futex.h b/arch/unicore32/include/asm/futex.h new file mode 100644 index 000000000000..07dea6170558 --- /dev/null +++ b/arch/unicore32/include/asm/futex.h @@ -0,0 +1,143 @@ +/* + * linux/arch/unicore32/include/asm/futex.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __UNICORE_FUTEX_H__ +#define __UNICORE_FUTEX_H__ + +#ifdef __KERNEL__ + +#include <linux/futex.h> +#include <linux/preempt.h> +#include <linux/uaccess.h> +#include <linux/errno.h> + +#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ + __asm__ __volatile__( \ + "1: ldw.u %1, [%2]\n" \ + " " insn "\n" \ + "2: stw.u %0, [%2]\n" \ + " mov %0, #0\n" \ + "3:\n" \ + " .pushsection __ex_table,\"a\"\n" \ + " .align 3\n" \ + " .long 1b, 4f, 2b, 4f\n" \ + " .popsection\n" \ + " .pushsection .fixup,\"ax\"\n" \ + "4: mov %0, %4\n" \ + " b 3b\n" \ + " .popsection" \ + : "=&r" (ret), "=&r" (oldval) \ + : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ + : "cc", "memory") + +static inline int +futex_atomic_op_inuser(int encoded_op, int __user *uaddr) +{ + int op = (encoded_op >> 28) & 7; + int cmp = (encoded_op >> 24) & 15; + int oparg = (encoded_op << 8) >> 20; + int cmparg = (encoded_op << 20) >> 20; + int oldval = 0, ret; + + if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) + oparg = 1 << oparg; + + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + return -EFAULT; + + pagefault_disable(); /* implies preempt_disable() */ + + switch (op) { + case FUTEX_OP_SET: + __futex_atomic_op("mov %0, %3", ret, oldval, uaddr, oparg); + break; + case FUTEX_OP_ADD: + __futex_atomic_op("add %0, %1, %3", ret, oldval, uaddr, oparg); + break; + case FUTEX_OP_OR: + __futex_atomic_op("or %0, %1, %3", ret, oldval, uaddr, oparg); + break; + case FUTEX_OP_ANDN: + __futex_atomic_op("and %0, %1, %3", + ret, oldval, uaddr, ~oparg); + break; + case FUTEX_OP_XOR: + __futex_atomic_op("xor %0, %1, %3", ret, oldval, uaddr, oparg); + break; + default: + ret = -ENOSYS; + } + + pagefault_enable(); /* subsumes preempt_enable() */ + + if (!ret) { + switch (cmp) { + case FUTEX_OP_CMP_EQ: + ret = (oldval == cmparg); + break; + case FUTEX_OP_CMP_NE: + ret = (oldval != cmparg); + break; + case FUTEX_OP_CMP_LT: + ret = (oldval < cmparg); + break; + case FUTEX_OP_CMP_GE: + ret = (oldval >= cmparg); + break; + case FUTEX_OP_CMP_LE: + ret = (oldval <= cmparg); + break; + case FUTEX_OP_CMP_GT: + ret = (oldval > cmparg); + break; + default: + ret = -ENOSYS; + } + } + return ret; +} + +static inline int +futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) +{ + int val; + + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + return -EFAULT; + + pagefault_disable(); /* implies preempt_disable() */ + + __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n" + "1: ldw.u %0, [%3]\n" + " cmpxor.a %0, %1\n" + " bne 3f\n" + "2: stw.u %2, [%3]\n" + "3:\n" + " .pushsection __ex_table,\"a\"\n" + " .align 3\n" + " .long 1b, 4f, 2b, 4f\n" + " .popsection\n" + " .pushsection .fixup,\"ax\"\n" + "4: mov %0, %4\n" + " b 3b\n" + " .popsection" + : "=&r" (val) + : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT) + : "cc", "memory"); + + pagefault_enable(); /* subsumes preempt_enable() */ + + return val; +} + +#endif /* __KERNEL__ */ +#endif /* __UNICORE_FUTEX_H__ */ diff --git a/arch/unicore32/include/asm/gpio.h b/arch/unicore32/include/asm/gpio.h new file mode 100644 index 000000000000..2716f14e3ff6 --- /dev/null +++ b/arch/unicore32/include/asm/gpio.h @@ -0,0 +1,104 @@ +/* + * linux/arch/unicore32/include/asm/gpio.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __UNICORE_GPIO_H__ +#define __UNICORE_GPIO_H__ + +#include <linux/io.h> +#include <asm/irq.h> +#include <mach/hardware.h> +#include <asm-generic/gpio.h> + +#define GPI_OTP_INT 0 +#define GPI_PCI_INTA 1 +#define GPI_PCI_INTB 2 +#define GPI_PCI_INTC 3 +#define GPI_PCI_INTD 4 +#define GPI_BAT_DET 5 +#define GPI_SD_CD 6 +#define GPI_SOFF_REQ 7 +#define GPI_SD_WP 8 +#define GPI_LCD_CASE_OFF 9 +#define GPO_WIFI_EN 10 +#define GPO_HDD_LED 11 +#define GPO_VGA_EN 12 +#define GPO_LCD_EN 13 +#define GPO_LED_DATA 14 +#define GPO_LED_CLK 15 +#define GPO_CAM_PWR_EN 16 +#define GPO_LCD_VCC_EN 17 +#define GPO_SOFT_OFF 18 +#define GPO_BT_EN 19 +#define GPO_FAN_ON 20 +#define GPO_SPKR 21 +#define GPO_SET_V1 23 +#define GPO_SET_V2 24 +#define GPO_CPU_HEALTH 25 +#define GPO_LAN_SEL 26 + +#ifdef CONFIG_PUV3_NB0916 +#define GPI_BTN_TOUCH 14 +#define GPIO_IN 0x000043ff /* 1 for input */ +#define GPIO_OUT 0x0fffbc00 /* 1 for output */ +#endif /* CONFIG_PUV3_NB0916 */ + +#ifdef CONFIG_PUV3_SMW0919 +#define GPIO_IN 0x000003ff /* 1 for input */ +#define GPIO_OUT 0x0ffffc00 /* 1 for output */ +#endif /* CONFIG_PUV3_SMW0919 */ + +#ifdef CONFIG_PUV3_DB0913 +#define GPIO_IN 0x000001df /* 1 for input */ +#define GPIO_OUT 0x03fee800 /* 1 for output */ +#endif /* CONFIG_PUV3_DB0913 */ + +#define GPIO_DIR (~((GPIO_IN) | 0xf0000000)) + /* 0 input, 1 output */ + +static inline int gpio_get_value(unsigned gpio) +{ + if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX)) + return readl(GPIO_GPLR) & GPIO_GPIO(gpio); + else + return __gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX)) + if (value) + writel(GPIO_GPIO(gpio), GPIO_GPSR); + else + writel(GPIO_GPIO(gpio), GPIO_GPCR); + else + __gpio_set_value(gpio, value); +} + +#define gpio_cansleep __gpio_cansleep + +static inline unsigned gpio_to_irq(unsigned gpio) +{ + if ((gpio < IRQ_GPIOHIGH) && (FIELD(1, 1, gpio) & readl(GPIO_GPIR))) + return IRQ_GPIOLOW0 + gpio; + else + return IRQ_GPIO0 + gpio; +} + +static inline unsigned irq_to_gpio(unsigned irq) +{ + if (irq < IRQ_GPIOHIGH) + return irq - IRQ_GPIOLOW0; + else + return irq - IRQ_GPIO0; +} + +#endif /* __UNICORE_GPIO_H__ */ diff --git a/arch/unicore32/include/asm/hwcap.h b/arch/unicore32/include/asm/hwcap.h new file mode 100644 index 000000000000..97bd40fdd4ac --- /dev/null +++ b/arch/unicore32/include/asm/hwcap.h @@ -0,0 +1,32 @@ +/* + * linux/arch/unicore32/include/asm/hwcap.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_HWCAP_H__ +#define __UNICORE_HWCAP_H__ + +/* + * HWCAP flags + */ +#define HWCAP_MSP 1 +#define HWCAP_UNICORE16 2 +#define HWCAP_CMOV 4 +#define HWCAP_UNICORE_F64 8 +#define HWCAP_TLS 0x80 + +#if defined(__KERNEL__) && !defined(__ASSEMBLY__) +/* + * This yields a mask that user programs can use to figure out what + * instruction set this cpu supports. + */ +#define ELF_HWCAP (HWCAP_CMOV | HWCAP_UNICORE_F64) +#endif + +#endif diff --git a/arch/unicore32/include/asm/io.h b/arch/unicore32/include/asm/io.h new file mode 100644 index 000000000000..4bd87f3d13d4 --- /dev/null +++ b/arch/unicore32/include/asm/io.h @@ -0,0 +1,55 @@ +/* + * linux/arch/unicore32/include/asm/io.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_IO_H__ +#define __UNICORE_IO_H__ + +#ifdef __KERNEL__ + +#include <asm/byteorder.h> +#include <asm/memory.h> +#include <asm/system.h> + +#define PCI_IOBASE PKUNITY_PCILIO_BASE +#include <asm-generic/io.h> + +/* + * __uc32_ioremap and __uc32_ioremap_cached takes CPU physical address. + */ +extern void __iomem *__uc32_ioremap(unsigned long, size_t); +extern void __iomem *__uc32_ioremap_cached(unsigned long, size_t); +extern void __uc32_iounmap(volatile void __iomem *addr); + +/* + * ioremap and friends. + * + * ioremap takes a PCI memory address, as specified in + * Documentation/IO-mapping.txt. + * + */ +#define ioremap(cookie, size) __uc32_ioremap(cookie, size) +#define ioremap_cached(cookie, size) __uc32_ioremap_cached(cookie, size) +#define iounmap(cookie) __uc32_iounmap(cookie) + +/* + * Convert a physical pointer to a virtual kernel pointer for /dev/mem + * access + */ +#undef xlate_dev_mem_ptr +#define xlate_dev_mem_ptr(p) __va(p) + +#define HAVE_ARCH_PIO_SIZE +#define PIO_OFFSET (unsigned int)(PCI_IOBASE) +#define PIO_MASK (unsigned int)(IO_SPACE_LIMIT) +#define PIO_RESERVED (PIO_OFFSET + PIO_MASK + 1) + +#endif /* __KERNEL__ */ +#endif /* __UNICORE_IO_H__ */ diff --git a/arch/unicore32/include/asm/irq.h b/arch/unicore32/include/asm/irq.h new file mode 100644 index 000000000000..baea93e2a6e6 --- /dev/null +++ b/arch/unicore32/include/asm/irq.h @@ -0,0 +1,105 @@ +/* + * linux/arch/unicore32/include/asm/irq.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_IRQ_H__ +#define __UNICORE_IRQ_H__ + +#include <asm-generic/irq.h> + +#define IRQ_GPIOLOW0 0x00 +#define IRQ_GPIOLOW1 0x01 +#define IRQ_GPIOLOW2 0x02 +#define IRQ_GPIOLOW3 0x03 +#define IRQ_GPIOLOW4 0x04 +#define IRQ_GPIOLOW5 0x05 +#define IRQ_GPIOLOW6 0x06 +#define IRQ_GPIOLOW7 0x07 +#define IRQ_GPIOHIGH 0x08 +#define IRQ_USB 0x09 +#define IRQ_SDC 0x0a +#define IRQ_AC97 0x0b +#define IRQ_SATA 0x0c +#define IRQ_MME 0x0d +#define IRQ_PCI_BRIDGE 0x0e +#define IRQ_DDR 0x0f +#define IRQ_SPI 0x10 +#define IRQ_UNIGFX 0x11 +#define IRQ_I2C 0x11 +#define IRQ_UART1 0x12 +#define IRQ_UART0 0x13 +#define IRQ_UMAL 0x14 +#define IRQ_NAND 0x15 +#define IRQ_PS2_KBD 0x16 +#define IRQ_PS2_AUX 0x17 +#define IRQ_DMA 0x18 +#define IRQ_DMAERR 0x19 +#define IRQ_TIMER0 0x1a +#define IRQ_TIMER1 0x1b +#define IRQ_TIMER2 0x1c +#define IRQ_TIMER3 0x1d +#define IRQ_RTC 0x1e +#define IRQ_RTCAlarm 0x1f + +#define IRQ_GPIO0 0x20 +#define IRQ_GPIO1 0x21 +#define IRQ_GPIO2 0x22 +#define IRQ_GPIO3 0x23 +#define IRQ_GPIO4 0x24 +#define IRQ_GPIO5 0x25 +#define IRQ_GPIO6 0x26 +#define IRQ_GPIO7 0x27 +#define IRQ_GPIO8 0x28 +#define IRQ_GPIO9 0x29 +#define IRQ_GPIO10 0x2a +#define IRQ_GPIO11 0x2b +#define IRQ_GPIO12 0x2c +#define IRQ_GPIO13 0x2d +#define IRQ_GPIO14 0x2e +#define IRQ_GPIO15 0x2f +#define IRQ_GPIO16 0x30 +#define IRQ_GPIO17 0x31 +#define IRQ_GPIO18 0x32 +#define IRQ_GPIO19 0x33 +#define IRQ_GPIO20 0x34 +#define IRQ_GPIO21 0x35 +#define IRQ_GPIO22 0x36 +#define IRQ_GPIO23 0x37 +#define IRQ_GPIO24 0x38 +#define IRQ_GPIO25 0x39 +#define IRQ_GPIO26 0x3a +#define IRQ_GPIO27 0x3b + +#ifdef CONFIG_ARCH_FPGA +#define IRQ_PCIINTA IRQ_GPIOLOW2 +#define IRQ_PCIINTB IRQ_GPIOLOW1 +#define IRQ_PCIINTC IRQ_GPIOLOW0 +#define IRQ_PCIINTD IRQ_GPIOLOW6 +#endif + +#if defined(CONFIG_PUV3_DB0913) || defined(CONFIG_PUV3_NB0916) \ + || defined(CONFIG_PUV3_SMW0919) +#define IRQ_PCIINTA IRQ_GPIOLOW1 +#define IRQ_PCIINTB IRQ_GPIOLOW2 +#define IRQ_PCIINTC IRQ_GPIOLOW3 +#define IRQ_PCIINTD IRQ_GPIOLOW4 +#endif + +#define IRQ_SD_CD IRQ_GPIO6 /* falling or rising trigger */ + +#ifndef __ASSEMBLY__ +struct pt_regs; + +extern void asm_do_IRQ(unsigned int, struct pt_regs *); + +#endif + +#endif + diff --git a/arch/unicore32/include/asm/irqflags.h b/arch/unicore32/include/asm/irqflags.h new file mode 100644 index 000000000000..6d8a28dfdbae --- /dev/null +++ b/arch/unicore32/include/asm/irqflags.h @@ -0,0 +1,53 @@ +/* + * linux/arch/unicore32/include/asm/irqflags.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_IRQFLAGS_H__ +#define __UNICORE_IRQFLAGS_H__ + +#ifdef __KERNEL__ + +#include <asm/ptrace.h> + +#define ARCH_IRQ_DISABLED (PRIV_MODE | PSR_I_BIT) +#define ARCH_IRQ_ENABLED (PRIV_MODE) + +/* + * Save the current interrupt enable state. + */ +static inline unsigned long arch_local_save_flags(void) +{ + unsigned long temp; + + asm volatile("mov %0, asr" : "=r" (temp) : : "memory", "cc"); + + return temp & PSR_c; +} + +/* + * restore saved IRQ state + */ +static inline void arch_local_irq_restore(unsigned long flags) +{ + unsigned long temp; + + asm volatile( + "mov %0, asr\n" + "mov.a asr, %1\n" + "mov.f asr, %0" + : "=&r" (temp) + : "r" (flags) + : "memory", "cc"); +} + +#include <asm-generic/irqflags.h> + +#endif +#endif diff --git a/arch/unicore32/include/asm/linkage.h b/arch/unicore32/include/asm/linkage.h new file mode 100644 index 000000000000..d1618bd35b67 --- /dev/null +++ b/arch/unicore32/include/asm/linkage.h @@ -0,0 +1,22 @@ +/* + * linux/arch/unicore32/include/asm/linkage.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_LINKAGE_H__ +#define __UNICORE_LINKAGE_H__ + +#define __ALIGN .align 0 +#define __ALIGN_STR ".align 0" + +#define ENDPROC(name) \ + .type name, %function; \ + END(name) + +#endif diff --git a/arch/unicore32/include/asm/memblock.h b/arch/unicore32/include/asm/memblock.h new file mode 100644 index 000000000000..a8a5d8d0a26e --- /dev/null +++ b/arch/unicore32/include/asm/memblock.h @@ -0,0 +1,46 @@ +/* + * linux/arch/unicore32/include/asm/memblock.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __UNICORE_MEMBLOCK_H__ +#define __UNICORE_MEMBLOCK_H__ + +/* + * Memory map description + */ +# define NR_BANKS 8 + +struct membank { + unsigned long start; + unsigned long size; + unsigned int highmem; +}; + +struct meminfo { + int nr_banks; + struct membank bank[NR_BANKS]; +}; + +extern struct meminfo meminfo; + +#define for_each_bank(iter, mi) \ + for (iter = 0; iter < (mi)->nr_banks; iter++) + +#define bank_pfn_start(bank) __phys_to_pfn((bank)->start) +#define bank_pfn_end(bank) __phys_to_pfn((bank)->start + (bank)->size) +#define bank_pfn_size(bank) ((bank)->size >> PAGE_SHIFT) +#define bank_phys_start(bank) ((bank)->start) +#define bank_phys_end(bank) ((bank)->start + (bank)->size) +#define bank_phys_size(bank) ((bank)->size) + +extern void uc32_memblock_init(struct meminfo *); + +#endif diff --git a/arch/unicore32/include/asm/memory.h b/arch/unicore32/include/asm/memory.h new file mode 100644 index 000000000000..5eddb997defe --- /dev/null +++ b/arch/unicore32/include/asm/memory.h @@ -0,0 +1,123 @@ +/* + * linux/arch/unicore32/include/asm/memory.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Note: this file should not be included by non-asm/.h files + */ +#ifndef __UNICORE_MEMORY_H__ +#define __UNICORE_MEMORY_H__ + +#include <linux/compiler.h> +#include <linux/const.h> +#include <asm/sizes.h> +#include <mach/memory.h> + +/* + * Allow for constants defined here to be used from assembly code + * by prepending the UL suffix only with actual C code compilation. + */ +#define UL(x) _AC(x, UL) + +/* + * PAGE_OFFSET - the virtual address of the start of the kernel image + * TASK_SIZE - the maximum size of a user space task. + * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area + */ +#define PAGE_OFFSET UL(0xC0000000) +#define TASK_SIZE (PAGE_OFFSET - UL(0x41000000)) +#define TASK_UNMAPPED_BASE (PAGE_OFFSET / 3) + +/* + * The module space lives between the addresses given by TASK_SIZE + * and PAGE_OFFSET - it must be within 32MB of the kernel text. + */ +#define MODULES_VADDR (PAGE_OFFSET - 16*1024*1024) +#if TASK_SIZE > MODULES_VADDR +#error Top of user space clashes with start of module space +#endif + +#define MODULES_END (PAGE_OFFSET) + +/* + * Allow 16MB-aligned ioremap pages + */ +#define IOREMAP_MAX_ORDER 24 + +/* + * Physical vs virtual RAM address space conversion. These are + * private definitions which should NOT be used outside memory.h + * files. Use virt_to_phys/phys_to_virt/__pa/__va instead. + */ +#ifndef __virt_to_phys +#define __virt_to_phys(x) ((x) - PAGE_OFFSET + PHYS_OFFSET) +#define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET) +#endif + +/* + * Convert a physical address to a Page Frame Number and back + */ +#define __phys_to_pfn(paddr) ((paddr) >> PAGE_SHIFT) +#define __pfn_to_phys(pfn) ((pfn) << PAGE_SHIFT) + +/* + * Convert a page to/from a physical address + */ +#define page_to_phys(page) (__pfn_to_phys(page_to_pfn(page))) +#define phys_to_page(phys) (pfn_to_page(__phys_to_pfn(phys))) + +#ifndef __ASSEMBLY__ + +#ifndef arch_adjust_zones +#define arch_adjust_zones(size, holes) do { } while (0) +#endif + +/* + * PFNs are used to describe any physical page; this means + * PFN 0 == physical address 0. + * + * This is the PFN of the first RAM page in the kernel + * direct-mapped view. We assume this is the first page + * of RAM in the mem_map as well. + */ +#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT) + +/* + * Drivers should NOT use these either. + */ +#define __pa(x) __virt_to_phys((unsigned long)(x)) +#define __va(x) ((void *)__phys_to_virt((unsigned long)(x))) +#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) + +/* + * Conversion between a struct page and a physical address. + * + * Note: when converting an unknown physical address to a + * struct page, the resulting pointer must be validated + * using VALID_PAGE(). It must return an invalid struct page + * for any physical address not corresponding to a system + * RAM address. + * + * page_to_pfn(page) convert a struct page * to a PFN number + * pfn_to_page(pfn) convert a _valid_ PFN number to struct page * + * + * virt_to_page(k) convert a _valid_ virtual address to struct page * + * virt_addr_valid(k) indicates whether a virtual address is valid + */ +#define ARCH_PFN_OFFSET PHYS_PFN_OFFSET + +#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) +#define virt_addr_valid(kaddr) ((unsigned long)(kaddr) >= PAGE_OFFSET && \ + (unsigned long)(kaddr) < (unsigned long)high_memory) + +#endif + +#include <asm-generic/memory_model.h> + +#endif diff --git a/arch/unicore32/include/asm/mmu.h b/arch/unicore32/include/asm/mmu.h new file mode 100644 index 000000000000..66fa341dc2c6 --- /dev/null +++ b/arch/unicore32/include/asm/mmu.h @@ -0,0 +1,17 @@ +/* + * linux/arch/unicore32/include/asm/mmu.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_MMU_H__ +#define __UNICORE_MMU_H__ + +typedef unsigned long mm_context_t; + +#endif diff --git a/arch/unicore32/include/asm/mmu_context.h b/arch/unicore32/include/asm/mmu_context.h new file mode 100644 index 000000000000..fb5e4c658f7a --- /dev/null +++ b/arch/unicore32/include/asm/mmu_context.h @@ -0,0 +1,87 @@ +/* + * linux/arch/unicore32/include/asm/mmu_context.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_MMU_CONTEXT_H__ +#define __UNICORE_MMU_CONTEXT_H__ + +#include <linux/compiler.h> +#include <linux/sched.h> +#include <linux/io.h> + +#include <asm/cacheflush.h> +#include <asm/cpu-single.h> + +#define init_new_context(tsk, mm) 0 + +#define destroy_context(mm) do { } while (0) + +/* + * This is called when "tsk" is about to enter lazy TLB mode. + * + * mm: describes the currently active mm context + * tsk: task which is entering lazy tlb + * cpu: cpu number which is entering lazy tlb + * + * tsk->mm will be NULL + */ +static inline void +enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) +{ +} + +/* + * This is the actual mm switch as far as the scheduler + * is concerned. No registers are touched. We avoid + * calling the CPU specific function when the mm hasn't + * actually changed. + */ +static inline void +switch_mm(struct mm_struct *prev, struct mm_struct *next, + struct task_struct *tsk) +{ + unsigned int cpu = smp_processor_id(); + + if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) + cpu_switch_mm(next->pgd, next); +} + +#define deactivate_mm(tsk, mm) do { } while (0) +#define activate_mm(prev, next) switch_mm(prev, next, NULL) + +/* + * We are inserting a "fake" vma for the user-accessible vector page so + * gdb and friends can get to it through ptrace and /proc/<pid>/mem. + * But we also want to remove it before the generic code gets to see it + * during process exit or the unmapping of it would cause total havoc. + * (the macro is used as remove_vma() is static to mm/mmap.c) + */ +#define arch_exit_mmap(mm) \ +do { \ + struct vm_area_struct *high_vma = find_vma(mm, 0xffff0000); \ + if (high_vma) { \ + BUG_ON(high_vma->vm_next); /* it should be last */ \ + if (high_vma->vm_prev) \ + high_vma->vm_prev->vm_next = NULL; \ + else \ + mm->mmap = NULL; \ + rb_erase(&high_vma->vm_rb, &mm->mm_rb); \ + mm->mmap_cache = NULL; \ + mm->map_count--; \ + remove_vma(high_vma); \ + } \ +} while (0) + +static inline void arch_dup_mmap(struct mm_struct *oldmm, + struct mm_struct *mm) +{ +} + +#endif diff --git a/arch/unicore32/include/asm/mutex.h b/arch/unicore32/include/asm/mutex.h new file mode 100644 index 000000000000..fab7d0e8adf6 --- /dev/null +++ b/arch/unicore32/include/asm/mutex.h @@ -0,0 +1,20 @@ +/* + * linux/arch/unicore32/include/asm/mutex.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * UniCore optimized mutex locking primitives + * + * Please look into asm-generic/mutex-xchg.h for a formal definition. + */ +#ifndef __UNICORE_MUTEX_H__ +#define __UNICORE_MUTEX_H__ + +# include <asm-generic/mutex-xchg.h> +#endif diff --git a/arch/unicore32/include/asm/page.h b/arch/unicore32/include/asm/page.h new file mode 100644 index 000000000000..594b3226250e --- /dev/null +++ b/arch/unicore32/include/asm/page.h @@ -0,0 +1,80 @@ +/* + * linux/arch/unicore32/include/asm/page.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_PAGE_H__ +#define __UNICORE_PAGE_H__ + +/* PAGE_SHIFT determines the page size */ +#define PAGE_SHIFT 12 +#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE-1)) + +#ifndef __ASSEMBLY__ + +struct page; +struct vm_area_struct; + +#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) +extern void copy_page(void *to, const void *from); + +#define clear_user_page(page, vaddr, pg) clear_page(page) +#define copy_user_page(to, from, vaddr, pg) copy_page(to, from) + +#undef STRICT_MM_TYPECHECKS + +#ifdef STRICT_MM_TYPECHECKS +/* + * These are used to make use of C type-checking.. + */ +typedef struct { unsigned long pte; } pte_t; +typedef struct { unsigned long pgd; } pgd_t; +typedef struct { unsigned long pgprot; } pgprot_t; + +#define pte_val(x) ((x).pte) +#define pgd_val(x) ((x).pgd) +#define pgprot_val(x) ((x).pgprot) + +#define __pte(x) ((pte_t) { (x) }) +#define __pgd(x) ((pgd_t) { (x) }) +#define __pgprot(x) ((pgprot_t) { (x) }) + +#else +/* + * .. while these make it easier on the compiler + */ +typedef unsigned long pte_t; +typedef unsigned long pgd_t; +typedef unsigned long pgprot_t; + +#define pte_val(x) (x) +#define pgd_val(x) (x) +#define pgprot_val(x) (x) + +#define __pte(x) (x) +#define __pgd(x) (x) +#define __pgprot(x) (x) + +#endif /* STRICT_MM_TYPECHECKS */ + +typedef struct page *pgtable_t; + +extern int pfn_valid(unsigned long); + +#include <asm/memory.h> + +#endif /* !__ASSEMBLY__ */ + +#define VM_DATA_DEFAULT_FLAGS \ + (VM_READ | VM_WRITE | VM_EXEC | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) + +#include <asm-generic/getorder.h> + +#endif diff --git a/arch/unicore32/include/asm/pci.h b/arch/unicore32/include/asm/pci.h new file mode 100644 index 000000000000..c5b28b459535 --- /dev/null +++ b/arch/unicore32/include/asm/pci.h @@ -0,0 +1,46 @@ +/* + * linux/arch/unicore32/include/asm/pci.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_PCI_H__ +#define __UNICORE_PCI_H__ + +#ifdef __KERNEL__ +#include <asm-generic/pci-dma-compat.h> +#include <asm-generic/pci.h> +#include <mach/hardware.h> /* for PCIBIOS_MIN_* */ + +static inline void pcibios_set_master(struct pci_dev *dev) +{ + /* No special bus mastering setup handling */ +} + +static inline void pcibios_penalize_isa_irq(int irq, int active) +{ + /* We don't do dynamic PCI IRQ allocation */ +} + +#ifdef CONFIG_PCI +static inline void pci_dma_burst_advice(struct pci_dev *pdev, + enum pci_dma_burst_strategy *strat, + unsigned long *strategy_parameter) +{ + *strat = PCI_DMA_BURST_INFINITY; + *strategy_parameter = ~0UL; +} +#endif + +#define HAVE_PCI_MMAP +extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, + enum pci_mmap_state mmap_state, int write_combine); + +#endif /* __KERNEL__ */ + +#endif diff --git a/arch/unicore32/include/asm/pgalloc.h b/arch/unicore32/include/asm/pgalloc.h new file mode 100644 index 000000000000..0213e373a895 --- /dev/null +++ b/arch/unicore32/include/asm/pgalloc.h @@ -0,0 +1,110 @@ +/* + * linux/arch/unicore32/include/asm/pgalloc.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_PGALLOC_H__ +#define __UNICORE_PGALLOC_H__ + +#include <asm/pgtable-hwdef.h> +#include <asm/processor.h> +#include <asm/cacheflush.h> +#include <asm/tlbflush.h> + +#define check_pgt_cache() do { } while (0) + +#define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_PRESENT) +#define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_PRESENT) + +extern pgd_t *get_pgd_slow(struct mm_struct *mm); +extern void free_pgd_slow(struct mm_struct *mm, pgd_t *pgd); + +#define pgd_alloc(mm) get_pgd_slow(mm) +#define pgd_free(mm, pgd) free_pgd_slow(mm, pgd) + +#define PGALLOC_GFP (GFP_KERNEL | __GFP_NOTRACK | __GFP_REPEAT | __GFP_ZERO) + +/* + * Allocate one PTE table. + */ +static inline pte_t * +pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr) +{ + pte_t *pte; + + pte = (pte_t *)__get_free_page(PGALLOC_GFP); + if (pte) + clean_dcache_area(pte, PTRS_PER_PTE * sizeof(pte_t)); + + return pte; +} + +static inline pgtable_t +pte_alloc_one(struct mm_struct *mm, unsigned long addr) +{ + struct page *pte; + + pte = alloc_pages(PGALLOC_GFP, 0); + if (pte) { + if (!PageHighMem(pte)) { + void *page = page_address(pte); + clean_dcache_area(page, PTRS_PER_PTE * sizeof(pte_t)); + } + pgtable_page_ctor(pte); + } + + return pte; +} + +/* + * Free one PTE table. + */ +static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) +{ + if (pte) + free_page((unsigned long)pte); +} + +static inline void pte_free(struct mm_struct *mm, pgtable_t pte) +{ + pgtable_page_dtor(pte); + __free_page(pte); +} + +static inline void __pmd_populate(pmd_t *pmdp, unsigned long pmdval) +{ + set_pmd(pmdp, __pmd(pmdval)); + flush_pmd_entry(pmdp); +} + +/* + * Populate the pmdp entry with a pointer to the pte. This pmd is part + * of the mm address space. + */ +static inline void +pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep) +{ + unsigned long pte_ptr = (unsigned long)ptep; + + /* + * The pmd must be loaded with the physical + * address of the PTE table + */ + __pmd_populate(pmdp, __pa(pte_ptr) | _PAGE_KERNEL_TABLE); +} + +static inline void +pmd_populate(struct mm_struct *mm, pmd_t *pmdp, pgtable_t ptep) +{ + __pmd_populate(pmdp, + page_to_pfn(ptep) << PAGE_SHIFT | _PAGE_USER_TABLE); +} +#define pmd_pgtable(pmd) pmd_page(pmd) + +#endif diff --git a/arch/unicore32/include/asm/pgtable-hwdef.h b/arch/unicore32/include/asm/pgtable-hwdef.h new file mode 100644 index 000000000000..7314e859cca0 --- /dev/null +++ b/arch/unicore32/include/asm/pgtable-hwdef.h @@ -0,0 +1,55 @@ +/* + * linux/arch/unicore32/include/asm/pgtable-hwdef.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_PGTABLE_HWDEF_H__ +#define __UNICORE_PGTABLE_HWDEF_H__ + +/* + * Hardware page table definitions. + * + * + Level 1 descriptor (PMD) + * - common + */ +#define PMD_TYPE_MASK (3 << 0) +#define PMD_TYPE_TABLE (0 << 0) +/*#define PMD_TYPE_LARGE (1 << 0) */ +#define PMD_TYPE_INVALID (2 << 0) +#define PMD_TYPE_SECT (3 << 0) + +#define PMD_PRESENT (1 << 2) +#define PMD_YOUNG (1 << 3) + +/*#define PMD_SECT_DIRTY (1 << 4) */ +#define PMD_SECT_CACHEABLE (1 << 5) +#define PMD_SECT_EXEC (1 << 6) +#define PMD_SECT_WRITE (1 << 7) +#define PMD_SECT_READ (1 << 8) + +/* + * + Level 2 descriptor (PTE) + * - common + */ +#define PTE_TYPE_MASK (3 << 0) +#define PTE_TYPE_SMALL (0 << 0) +#define PTE_TYPE_MIDDLE (1 << 0) +#define PTE_TYPE_LARGE (2 << 0) +#define PTE_TYPE_INVALID (3 << 0) + +#define PTE_PRESENT (1 << 2) +#define PTE_FILE (1 << 3) /* only when !PRESENT */ +#define PTE_YOUNG (1 << 3) +#define PTE_DIRTY (1 << 4) +#define PTE_CACHEABLE (1 << 5) +#define PTE_EXEC (1 << 6) +#define PTE_WRITE (1 << 7) +#define PTE_READ (1 << 8) + +#endif diff --git a/arch/unicore32/include/asm/pgtable.h b/arch/unicore32/include/asm/pgtable.h new file mode 100644 index 000000000000..68b2f297ac97 --- /dev/null +++ b/arch/unicore32/include/asm/pgtable.h @@ -0,0 +1,317 @@ +/* + * linux/arch/unicore32/include/asm/pgtable.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_PGTABLE_H__ +#define __UNICORE_PGTABLE_H__ + +#include <asm-generic/pgtable-nopmd.h> +#include <asm/cpu-single.h> + +#include <asm/memory.h> +#include <asm/pgtable-hwdef.h> + +/* + * Just any arbitrary offset to the start of the vmalloc VM area: the + * current 8MB value just means that there will be a 8MB "hole" after the + * physical memory until the kernel virtual memory starts. That means that + * any out-of-bounds memory accesses will hopefully be caught. + * The vmalloc() routines leaves a hole of 4kB between each vmalloced + * area for the same reason. ;) + * + * Note that platforms may override VMALLOC_START, but they must provide + * VMALLOC_END. VMALLOC_END defines the (exclusive) limit of this space, + * which may not overlap IO space. + */ +#ifndef VMALLOC_START +#define VMALLOC_OFFSET SZ_8M +#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) \ + & ~(VMALLOC_OFFSET-1)) +#define VMALLOC_END (0xff000000UL) +#endif + +#define PTRS_PER_PTE 1024 +#define PTRS_PER_PGD 1024 + +/* + * PGDIR_SHIFT determines what a third-level page table entry can map + */ +#define PGDIR_SHIFT 22 + +#ifndef __ASSEMBLY__ +extern void __pte_error(const char *file, int line, unsigned long val); +extern void __pgd_error(const char *file, int line, unsigned long val); + +#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) +#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) +#endif /* !__ASSEMBLY__ */ + +#define PGDIR_SIZE (1UL << PGDIR_SHIFT) +#define PGDIR_MASK (~(PGDIR_SIZE-1)) + +/* + * This is the lowest virtual address we can permit any user space + * mapping to be mapped at. This is particularly important for + * non-high vector CPUs. + */ +#define FIRST_USER_ADDRESS PAGE_SIZE + +#define FIRST_USER_PGD_NR 1 +#define USER_PTRS_PER_PGD ((TASK_SIZE/PGDIR_SIZE) - FIRST_USER_PGD_NR) + +/* + * section address mask and size definitions. + */ +#define SECTION_SHIFT 22 +#define SECTION_SIZE (1UL << SECTION_SHIFT) +#define SECTION_MASK (~(SECTION_SIZE-1)) + +#ifndef __ASSEMBLY__ + +/* + * The pgprot_* and protection_map entries will be fixed up in runtime + * to include the cachable bits based on memory policy, as well as any + * architecture dependent bits. + */ +#define _PTE_DEFAULT (PTE_PRESENT | PTE_YOUNG | PTE_CACHEABLE) + +extern pgprot_t pgprot_user; +extern pgprot_t pgprot_kernel; + +#define PAGE_NONE pgprot_user +#define PAGE_SHARED __pgprot(pgprot_val(pgprot_user | PTE_READ \ + | PTE_WRITE) +#define PAGE_SHARED_EXEC __pgprot(pgprot_val(pgprot_user | PTE_READ \ + | PTE_WRITE \ + | PTE_EXEC) +#define PAGE_COPY __pgprot(pgprot_val(pgprot_user | PTE_READ) +#define PAGE_COPY_EXEC __pgprot(pgprot_val(pgprot_user | PTE_READ \ + | PTE_EXEC) +#define PAGE_READONLY __pgprot(pgprot_val(pgprot_user | PTE_READ) +#define PAGE_READONLY_EXEC __pgprot(pgprot_val(pgprot_user | PTE_READ \ + | PTE_EXEC) +#define PAGE_KERNEL pgprot_kernel +#define PAGE_KERNEL_EXEC __pgprot(pgprot_val(pgprot_kernel | PTE_EXEC)) + +#define __PAGE_NONE __pgprot(_PTE_DEFAULT) +#define __PAGE_SHARED __pgprot(_PTE_DEFAULT | PTE_READ \ + | PTE_WRITE) +#define __PAGE_SHARED_EXEC __pgprot(_PTE_DEFAULT | PTE_READ \ + | PTE_WRITE \ + | PTE_EXEC) +#define __PAGE_COPY __pgprot(_PTE_DEFAULT | PTE_READ) +#define __PAGE_COPY_EXEC __pgprot(_PTE_DEFAULT | PTE_READ \ + | PTE_EXEC) +#define __PAGE_READONLY __pgprot(_PTE_DEFAULT | PTE_READ) +#define __PAGE_READONLY_EXEC __pgprot(_PTE_DEFAULT | PTE_READ \ + | PTE_EXEC) + +#endif /* __ASSEMBLY__ */ + +/* + * The table below defines the page protection levels that we insert into our + * Linux page table version. These get translated into the best that the + * architecture can perform. Note that on UniCore hardware: + * 1) We cannot do execute protection + * 2) If we could do execute protection, then read is implied + * 3) write implies read permissions + */ +#define __P000 __PAGE_NONE +#define __P001 __PAGE_READONLY +#define __P010 __PAGE_COPY +#define __P011 __PAGE_COPY +#define __P100 __PAGE_READONLY_EXEC +#define __P101 __PAGE_READONLY_EXEC +#define __P110 __PAGE_COPY_EXEC +#define __P111 __PAGE_COPY_EXEC + +#define __S000 __PAGE_NONE +#define __S001 __PAGE_READONLY +#define __S010 __PAGE_SHARED +#define __S011 __PAGE_SHARED +#define __S100 __PAGE_READONLY_EXEC +#define __S101 __PAGE_READONLY_EXEC +#define __S110 __PAGE_SHARED_EXEC +#define __S111 __PAGE_SHARED_EXEC + +#ifndef __ASSEMBLY__ +/* + * ZERO_PAGE is a global shared page that is always zero: used + * for zero-mapped memory areas etc.. + */ +extern struct page *empty_zero_page; +#define ZERO_PAGE(vaddr) (empty_zero_page) + +#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) +#define pfn_pte(pfn, prot) (__pte(((pfn) << PAGE_SHIFT) \ + | pgprot_val(prot))) + +#define pte_none(pte) (!pte_val(pte)) +#define pte_clear(mm, addr, ptep) set_pte(ptep, __pte(0)) +#define pte_page(pte) (pfn_to_page(pte_pfn(pte))) +#define pte_offset_kernel(dir, addr) (pmd_page_vaddr(*(dir)) \ + + __pte_index(addr)) + +#define pte_offset_map(dir, addr) (pmd_page_vaddr(*(dir)) \ + + __pte_index(addr)) +#define pte_unmap(pte) do { } while (0) + +#define set_pte(ptep, pte) cpu_set_pte(ptep, pte) + +#define set_pte_at(mm, addr, ptep, pteval) \ + do { \ + set_pte(ptep, pteval); \ + } while (0) + +/* + * The following only work if pte_present() is true. + * Undefined behaviour if not.. + */ +#define pte_present(pte) (pte_val(pte) & PTE_PRESENT) +#define pte_write(pte) (pte_val(pte) & PTE_WRITE) +#define pte_dirty(pte) (pte_val(pte) & PTE_DIRTY) +#define pte_young(pte) (pte_val(pte) & PTE_YOUNG) +#define pte_exec(pte) (pte_val(pte) & PTE_EXEC) +#define pte_special(pte) (0) + +#define PTE_BIT_FUNC(fn, op) \ +static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; } + +PTE_BIT_FUNC(wrprotect, &= ~PTE_WRITE); +PTE_BIT_FUNC(mkwrite, |= PTE_WRITE); +PTE_BIT_FUNC(mkclean, &= ~PTE_DIRTY); +PTE_BIT_FUNC(mkdirty, |= PTE_DIRTY); +PTE_BIT_FUNC(mkold, &= ~PTE_YOUNG); +PTE_BIT_FUNC(mkyoung, |= PTE_YOUNG); + +static inline pte_t pte_mkspecial(pte_t pte) { return pte; } + +/* + * Mark the prot value as uncacheable. + */ +#define pgprot_noncached(prot) \ + __pgprot(pgprot_val(prot) & ~PTE_CACHEABLE) +#define pgprot_writecombine(prot) \ + __pgprot(pgprot_val(prot) & ~PTE_CACHEABLE) +#define pgprot_dmacoherent(prot) \ + __pgprot(pgprot_val(prot) & ~PTE_CACHEABLE) + +#define pmd_none(pmd) (!pmd_val(pmd)) +#define pmd_present(pmd) (pmd_val(pmd) & PMD_PRESENT) +#define pmd_bad(pmd) (((pmd_val(pmd) & \ + (PMD_PRESENT | PMD_TYPE_MASK)) \ + != (PMD_PRESENT | PMD_TYPE_TABLE))) + +#define set_pmd(pmdpd, pmdval) \ + do { \ + *(pmdpd) = pmdval; \ + } while (0) + +#define pmd_clear(pmdp) \ + do { \ + set_pmd(pmdp, __pmd(0));\ + clean_pmd_entry(pmdp); \ + } while (0) + +#define pmd_page_vaddr(pmd) ((pte_t *)__va(pmd_val(pmd) & PAGE_MASK)) +#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd))) + +/* + * Conversion functions: convert a page and protection to a page entry, + * and a page entry and page directory to the page they refer to. + */ +#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) + +/* to find an entry in a page-table-directory */ +#define pgd_index(addr) ((addr) >> PGDIR_SHIFT) + +#define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr)) + +/* to find an entry in a kernel page-table-directory */ +#define pgd_offset_k(addr) pgd_offset(&init_mm, addr) + +/* Find an entry in the third-level page table.. */ +#define __pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) + +static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) +{ + const unsigned long mask = PTE_EXEC | PTE_WRITE | PTE_READ; + pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); + return pte; +} + +extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; + +/* + * Encode and decode a swap entry. Swap entries are stored in the Linux + * page tables as follows: + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * <--------------- offset --------------> <--- type --> 0 0 0 0 0 + * + * This gives us up to 127 swap files and 32GB per swap file. Note that + * the offset field is always non-zero. + */ +#define __SWP_TYPE_SHIFT 5 +#define __SWP_TYPE_BITS 7 +#define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) +#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) + +#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) \ + & __SWP_TYPE_MASK) +#define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) +#define __swp_entry(type, offset) ((swp_entry_t) { \ + ((type) << __SWP_TYPE_SHIFT) | \ + ((offset) << __SWP_OFFSET_SHIFT) }) + +#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) +#define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) + +/* + * It is an error for the kernel to have more swap files than we can + * encode in the PTEs. This ensures that we know when MAX_SWAPFILES + * is increased beyond what we presently support. + */ +#define MAX_SWAPFILES_CHECK() \ + BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) + +/* + * Encode and decode a file entry. File entries are stored in the Linux + * page tables as follows: + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * <----------------------- offset ----------------------> 1 0 0 0 + */ +#define pte_file(pte) (pte_val(pte) & PTE_FILE) +#define pte_to_pgoff(x) (pte_val(x) >> 4) +#define pgoff_to_pte(x) __pte(((x) << 4) | PTE_FILE) + +#define PTE_FILE_MAX_BITS 28 + +/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ +/* FIXME: this is not correct */ +#define kern_addr_valid(addr) (1) + +#include <asm-generic/pgtable.h> + +/* + * remap a physical page `pfn' of size `size' with page protection `prot' + * into virtual address `from' + */ +#define io_remap_pfn_range(vma, from, pfn, size, prot) \ + remap_pfn_range(vma, from, pfn, size, prot) + +#define pgtable_cache_init() do { } while (0) + +#endif /* !__ASSEMBLY__ */ + +#endif /* __UNICORE_PGTABLE_H__ */ diff --git a/arch/unicore32/include/asm/processor.h b/arch/unicore32/include/asm/processor.h new file mode 100644 index 000000000000..e11cb0786578 --- /dev/null +++ b/arch/unicore32/include/asm/processor.h @@ -0,0 +1,92 @@ +/* + * linux/arch/unicore32/include/asm/processor.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __UNICORE_PROCESSOR_H__ +#define __UNICORE_PROCESSOR_H__ + +/* + * Default implementation of macro that returns current + * instruction pointer ("program counter"). + */ +#define current_text_addr() ({ __label__ _l; _l: &&_l; }) + +#ifdef __KERNEL__ + +#include <asm/ptrace.h> +#include <asm/types.h> + +#ifdef __KERNEL__ +#define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX TASK_SIZE +#endif + +struct debug_entry { + u32 address; + u32 insn; +}; + +struct debug_info { + int nsaved; + struct debug_entry bp[2]; +}; + +struct thread_struct { + /* fault info */ + unsigned long address; + unsigned long trap_no; + unsigned long error_code; + /* debugging */ + struct debug_info debug; +}; + +#define INIT_THREAD { } + +#define start_thread(regs, pc, sp) \ +({ \ + unsigned long *stack = (unsigned long *)sp; \ + set_fs(USER_DS); \ + memset(regs->uregs, 0, sizeof(regs->uregs)); \ + regs->UCreg_asr = USER_MODE; \ + regs->UCreg_pc = pc & ~1; /* pc */ \ + regs->UCreg_sp = sp; /* sp */ \ + regs->UCreg_02 = stack[2]; /* r2 (envp) */ \ + regs->UCreg_01 = stack[1]; /* r1 (argv) */ \ + regs->UCreg_00 = stack[0]; /* r0 (argc) */ \ +}) + +/* Forward declaration, a strange C thing */ +struct task_struct; + +/* Free all resources held by a thread. */ +extern void release_thread(struct task_struct *); + +/* Prepare to copy thread state - unlazy all lazy status */ +#define prepare_to_copy(tsk) do { } while (0) + +unsigned long get_wchan(struct task_struct *p); + +#define cpu_relax() barrier() + +/* + * Create a new kernel thread + */ +extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); + +#define task_pt_regs(p) \ + ((struct pt_regs *)(THREAD_START_SP + task_stack_page(p)) - 1) + +#define KSTK_EIP(tsk) (task_pt_regs(tsk)->UCreg_pc) +#define KSTK_ESP(tsk) (task_pt_regs(tsk)->UCreg_sp) + +#endif + +#endif /* __UNICORE_PROCESSOR_H__ */ diff --git a/arch/unicore32/include/asm/ptrace.h b/arch/unicore32/include/asm/ptrace.h new file mode 100644 index 000000000000..b9caf9b0997b --- /dev/null +++ b/arch/unicore32/include/asm/ptrace.h @@ -0,0 +1,133 @@ +/* + * linux/arch/unicore32/include/asm/ptrace.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_PTRACE_H__ +#define __UNICORE_PTRACE_H__ + +#define PTRACE_GET_THREAD_AREA 22 + +/* + * PSR bits + */ +#define USER_MODE 0x00000010 +#define REAL_MODE 0x00000011 +#define INTR_MODE 0x00000012 +#define PRIV_MODE 0x00000013 +#define ABRT_MODE 0x00000017 +#define EXTN_MODE 0x0000001b +#define SUSR_MODE 0x0000001f +#define MODE_MASK 0x0000001f +#define PSR_R_BIT 0x00000040 +#define PSR_I_BIT 0x00000080 +#define PSR_V_BIT 0x10000000 +#define PSR_C_BIT 0x20000000 +#define PSR_Z_BIT 0x40000000 +#define PSR_S_BIT 0x80000000 + +/* + * Groups of PSR bits + */ +#define PSR_f 0xff000000 /* Flags */ +#define PSR_c 0x000000ff /* Control */ + +#ifndef __ASSEMBLY__ + +/* + * This struct defines the way the registers are stored on the + * stack during a system call. Note that sizeof(struct pt_regs) + * has to be a multiple of 8. + */ +struct pt_regs { + unsigned long uregs[34]; +}; + +#define UCreg_asr uregs[32] +#define UCreg_pc uregs[31] +#define UCreg_lr uregs[30] +#define UCreg_sp uregs[29] +#define UCreg_ip uregs[28] +#define UCreg_fp uregs[27] +#define UCreg_26 uregs[26] +#define UCreg_25 uregs[25] +#define UCreg_24 uregs[24] +#define UCreg_23 uregs[23] +#define UCreg_22 uregs[22] +#define UCreg_21 uregs[21] +#define UCreg_20 uregs[20] +#define UCreg_19 uregs[19] +#define UCreg_18 uregs[18] +#define UCreg_17 uregs[17] +#define UCreg_16 uregs[16] +#define UCreg_15 uregs[15] +#define UCreg_14 uregs[14] +#define UCreg_13 uregs[13] +#define UCreg_12 uregs[12] +#define UCreg_11 uregs[11] +#define UCreg_10 uregs[10] +#define UCreg_09 uregs[9] +#define UCreg_08 uregs[8] +#define UCreg_07 uregs[7] +#define UCreg_06 uregs[6] +#define UCreg_05 uregs[5] +#define UCreg_04 uregs[4] +#define UCreg_03 uregs[3] +#define UCreg_02 uregs[2] +#define UCreg_01 uregs[1] +#define UCreg_00 uregs[0] +#define UCreg_ORIG_00 uregs[33] + +#ifdef __KERNEL__ + +#define user_mode(regs) \ + (processor_mode(regs) == USER_MODE) + +#define processor_mode(regs) \ + ((regs)->UCreg_asr & MODE_MASK) + +#define interrupts_enabled(regs) \ + (!((regs)->UCreg_asr & PSR_I_BIT)) + +#define fast_interrupts_enabled(regs) \ + (!((regs)->UCreg_asr & PSR_R_BIT)) + +/* Are the current registers suitable for user mode? + * (used to maintain security in signal handlers) + */ +static inline int valid_user_regs(struct pt_regs *regs) +{ + unsigned long mode = regs->UCreg_asr & MODE_MASK; + + /* + * Always clear the R (REAL) bits + */ + regs->UCreg_asr &= ~(PSR_R_BIT); + + if ((regs->UCreg_asr & PSR_I_BIT) == 0) { + if (mode == USER_MODE) + return 1; + } + + /* + * Force ASR to something logical... + */ + regs->UCreg_asr &= PSR_f | USER_MODE; + + return 0; +} + +#define instruction_pointer(regs) ((regs)->UCreg_pc) + +#endif /* __KERNEL__ */ + +#endif /* __ASSEMBLY__ */ + +#endif + diff --git a/arch/unicore32/include/asm/sigcontext.h b/arch/unicore32/include/asm/sigcontext.h new file mode 100644 index 000000000000..6a2d7671c052 --- /dev/null +++ b/arch/unicore32/include/asm/sigcontext.h @@ -0,0 +1,29 @@ +/* + * linux/arch/unicore32/include/asm/sigcontext.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_SIGCONTEXT_H__ +#define __UNICORE_SIGCONTEXT_H__ + +#include <asm/ptrace.h> +/* + * Signal context structure - contains all info to do with the state + * before the signal handler was invoked. Note: only add new entries + * to the end of the structure. + */ +struct sigcontext { + unsigned long trap_no; + unsigned long error_code; + unsigned long oldmask; + unsigned long fault_address; + struct pt_regs regs; +}; + +#endif diff --git a/arch/unicore32/include/asm/stacktrace.h b/arch/unicore32/include/asm/stacktrace.h new file mode 100644 index 000000000000..76edc65a5871 --- /dev/null +++ b/arch/unicore32/include/asm/stacktrace.h @@ -0,0 +1,31 @@ +/* + * linux/arch/unicore32/include/asm/stacktrace.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __UNICORE_STACKTRACE_H__ +#define __UNICORE_STACKTRACE_H__ + +struct stackframe { + unsigned long fp; + unsigned long sp; + unsigned long lr; + unsigned long pc; +}; + +#ifdef CONFIG_FRAME_POINTER +extern int unwind_frame(struct stackframe *frame); +#else +#define unwind_frame(f) (-EINVAL) +#endif +extern void walk_stackframe(struct stackframe *frame, + int (*fn)(struct stackframe *, void *), void *data); + +#endif /* __UNICORE_STACKTRACE_H__ */ diff --git a/arch/unicore32/include/asm/string.h b/arch/unicore32/include/asm/string.h new file mode 100644 index 000000000000..55264c84369a --- /dev/null +++ b/arch/unicore32/include/asm/string.h @@ -0,0 +1,38 @@ +/* + * linux/arch/unicore32/include/asm/string.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_STRING_H__ +#define __UNICORE_STRING_H__ + +/* + * We don't do inline string functions, since the + * optimised inline asm versions are not small. + */ + +#define __HAVE_ARCH_STRRCHR +extern char *strrchr(const char *s, int c); + +#define __HAVE_ARCH_STRCHR +extern char *strchr(const char *s, int c); + +#define __HAVE_ARCH_MEMCPY +extern void *memcpy(void *, const void *, __kernel_size_t); + +#define __HAVE_ARCH_MEMMOVE +extern void *memmove(void *, const void *, __kernel_size_t); + +#define __HAVE_ARCH_MEMCHR +extern void *memchr(const void *, int, __kernel_size_t); + +#define __HAVE_ARCH_MEMSET +extern void *memset(void *, int, __kernel_size_t); + +#endif diff --git a/arch/unicore32/include/asm/suspend.h b/arch/unicore32/include/asm/suspend.h new file mode 100644 index 000000000000..88a9c0f32b21 --- /dev/null +++ b/arch/unicore32/include/asm/suspend.h @@ -0,0 +1,30 @@ +/* + * linux/arch/unicore32/include/asm/suspend.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __UNICORE_SUSPEND_H__ +#define __UNICORE_SUSPEND_H__ + +#ifndef __ASSEMBLY__ +static inline int arch_prepare_suspend(void) { return 0; } + +#include <asm/ptrace.h> + +struct swsusp_arch_regs { + struct cpu_context_save cpu_context; /* cpu context */ +#ifdef CONFIG_UNICORE_FPU_F64 + struct fp_state fpstate __attribute__((aligned(8))); +#endif +}; +#endif + +#endif /* __UNICORE_SUSPEND_H__ */ + diff --git a/arch/unicore32/include/asm/system.h b/arch/unicore32/include/asm/system.h new file mode 100644 index 000000000000..246b71c17fda --- /dev/null +++ b/arch/unicore32/include/asm/system.h @@ -0,0 +1,161 @@ +/* + * linux/arch/unicore32/include/asm/system.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_SYSTEM_H__ +#define __UNICORE_SYSTEM_H__ + +#ifdef __KERNEL__ + +/* + * CR1 bits (CP#0 CR1) + */ +#define CR_M (1 << 0) /* MMU enable */ +#define CR_A (1 << 1) /* Alignment abort enable */ +#define CR_D (1 << 2) /* Dcache enable */ +#define CR_I (1 << 3) /* Icache enable */ +#define CR_B (1 << 4) /* Dcache write mechanism: write back */ +#define CR_T (1 << 5) /* Burst enable */ +#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ + +#ifndef __ASSEMBLY__ + +#include <linux/linkage.h> +#include <linux/irqflags.h> + +struct thread_info; +struct task_struct; + +struct pt_regs; + +void die(const char *msg, struct pt_regs *regs, int err); + +struct siginfo; +void uc32_notify_die(const char *str, struct pt_regs *regs, + struct siginfo *info, unsigned long err, unsigned long trap); + +void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, + struct pt_regs *), + int sig, int code, const char *name); + +#define xchg(ptr, x) \ + ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))) + +extern asmlinkage void __backtrace(void); +extern asmlinkage void c_backtrace(unsigned long fp, int pmode); + +struct mm_struct; +extern void show_pte(struct mm_struct *mm, unsigned long addr); +extern void __show_regs(struct pt_regs *); + +extern int cpu_architecture(void); +extern void cpu_init(void); + +#define vectors_high() (cr_alignment & CR_V) + +#define isb() __asm__ __volatile__ ("" : : : "memory") +#define dsb() __asm__ __volatile__ ("" : : : "memory") +#define dmb() __asm__ __volatile__ ("" : : : "memory") + +#define mb() barrier() +#define rmb() barrier() +#define wmb() barrier() +#define smp_mb() barrier() +#define smp_rmb() barrier() +#define smp_wmb() barrier() +#define read_barrier_depends() do { } while (0) +#define smp_read_barrier_depends() do { } while (0) + +#define set_mb(var, value) do { var = value; smp_mb(); } while (0) +#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); + +extern unsigned long cr_no_alignment; /* defined in entry-unicore.S */ +extern unsigned long cr_alignment; /* defined in entry-unicore.S */ + +static inline unsigned int get_cr(void) +{ + unsigned int val; + asm("movc %0, p0.c1, #0" : "=r" (val) : : "cc"); + return val; +} + +static inline void set_cr(unsigned int val) +{ + asm volatile("movc p0.c1, %0, #0 @set CR" + : : "r" (val) : "cc"); + isb(); +} + +extern void adjust_cr(unsigned long mask, unsigned long set); + +/* + * switch_to(prev, next) should switch from task `prev' to `next' + * `prev' will never be the same as `next'. schedule() itself + * contains the memory barrier to tell GCC not to cache `current'. + */ +extern struct task_struct *__switch_to(struct task_struct *, + struct thread_info *, struct thread_info *); +extern void panic(const char *fmt, ...); + +#define switch_to(prev, next, last) \ +do { \ + last = __switch_to(prev, \ + task_thread_info(prev), task_thread_info(next)); \ +} while (0) + +static inline unsigned long +__xchg(unsigned long x, volatile void *ptr, int size) +{ + unsigned long ret; + + switch (size) { + case 1: + asm volatile("@ __xchg1\n" + " swapb %0, %1, [%2]" + : "=&r" (ret) + : "r" (x), "r" (ptr) + : "memory", "cc"); + break; + case 4: + asm volatile("@ __xchg4\n" + " swapw %0, %1, [%2]" + : "=&r" (ret) + : "r" (x), "r" (ptr) + : "memory", "cc"); + break; + default: + panic("xchg: bad data size: ptr 0x%p, size %d\n", + ptr, size); + } + + return ret; +} + +#include <asm-generic/cmpxchg-local.h> + +/* + * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make + * them available. + */ +#define cmpxchg_local(ptr, o, n) \ + ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), \ + (unsigned long)(o), (unsigned long)(n), sizeof(*(ptr)))) +#define cmpxchg64_local(ptr, o, n) \ + __cmpxchg64_local_generic((ptr), (o), (n)) + +#include <asm-generic/cmpxchg.h> + +#endif /* __ASSEMBLY__ */ + +#define arch_align_stack(x) (x) + +#endif /* __KERNEL__ */ + +#endif diff --git a/arch/unicore32/include/asm/thread_info.h b/arch/unicore32/include/asm/thread_info.h new file mode 100644 index 000000000000..c270e9e04861 --- /dev/null +++ b/arch/unicore32/include/asm/thread_info.h @@ -0,0 +1,154 @@ +/* + * linux/arch/unicore32/include/asm/thread_info.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_THREAD_INFO_H__ +#define __UNICORE_THREAD_INFO_H__ + +#ifdef __KERNEL__ + +#include <linux/compiler.h> +#include <asm/fpstate.h> + +#define THREAD_SIZE_ORDER 1 +#define THREAD_SIZE 8192 +#define THREAD_START_SP (THREAD_SIZE - 8) + +#ifndef __ASSEMBLY__ + +struct task_struct; +struct exec_domain; + +#include <asm/types.h> + +typedef struct { + unsigned long seg; +} mm_segment_t; + +struct cpu_context_save { + __u32 r4; + __u32 r5; + __u32 r6; + __u32 r7; + __u32 r8; + __u32 r9; + __u32 r10; + __u32 r11; + __u32 r12; + __u32 r13; + __u32 r14; + __u32 r15; + __u32 r16; + __u32 r17; + __u32 r18; + __u32 r19; + __u32 r20; + __u32 r21; + __u32 r22; + __u32 r23; + __u32 r24; + __u32 r25; + __u32 r26; + __u32 fp; + __u32 sp; + __u32 pc; +}; + +/* + * low level task data that entry.S needs immediate access to. + * __switch_to() assumes cpu_context follows immediately after cpu_domain. + */ +struct thread_info { + unsigned long flags; /* low level flags */ + int preempt_count; /* 0 => preemptable */ + /* <0 => bug */ + mm_segment_t addr_limit; /* address limit */ + struct task_struct *task; /* main task structure */ + struct exec_domain *exec_domain; /* execution domain */ + __u32 cpu; /* cpu */ + struct cpu_context_save cpu_context; /* cpu context */ + __u32 syscall; /* syscall number */ + __u8 used_cp[16]; /* thread used copro */ +#ifdef CONFIG_UNICORE_FPU_F64 + struct fp_state fpstate __attribute__((aligned(8))); +#endif + struct restart_block restart_block; +}; + +#define INIT_THREAD_INFO(tsk) \ +{ \ + .task = &tsk, \ + .exec_domain = &default_exec_domain, \ + .flags = 0, \ + .preempt_count = INIT_PREEMPT_COUNT, \ + .addr_limit = KERNEL_DS, \ + .restart_block = { \ + .fn = do_no_restart_syscall, \ + }, \ +} + +#define init_thread_info (init_thread_union.thread_info) +#define init_stack (init_thread_union.stack) + +/* + * how to get the thread information struct from C + */ +static inline struct thread_info *current_thread_info(void) __attribute_const__; + +static inline struct thread_info *current_thread_info(void) +{ + register unsigned long sp asm ("sp"); + return (struct thread_info *)(sp & ~(THREAD_SIZE - 1)); +} + +#define thread_saved_pc(tsk) \ + ((unsigned long)(task_thread_info(tsk)->cpu_context.pc)) +#define thread_saved_sp(tsk) \ + ((unsigned long)(task_thread_info(tsk)->cpu_context.sp)) +#define thread_saved_fp(tsk) \ + ((unsigned long)(task_thread_info(tsk)->cpu_context.fp)) + +#endif + +/* + * We use bit 30 of the preempt_count to indicate that kernel + * preemption is occurring. See <asm/hardirq.h>. + */ +#define PREEMPT_ACTIVE 0x40000000 + +/* + * thread information flags: + * TIF_SYSCALL_TRACE - syscall trace active + * TIF_SIGPENDING - signal pending + * TIF_NEED_RESCHED - rescheduling necessary + * TIF_NOTIFY_RESUME - callback before returning to user + */ +#define TIF_SIGPENDING 0 +#define TIF_NEED_RESCHED 1 +#define TIF_NOTIFY_RESUME 2 /* callback before returning to user */ +#define TIF_SYSCALL_TRACE 8 +#define TIF_MEMDIE 18 +#define TIF_FREEZE 19 +#define TIF_RESTORE_SIGMASK 20 + +#define _TIF_SIGPENDING (1 << TIF_SIGPENDING) +#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) +#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) +#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) +#define _TIF_FREEZE (1 << TIF_FREEZE) +#define _TIF_RESTORE_SIGMASK (1 << TIF_RESTORE_SIGMASK) + +/* + * Change these and you break ASM code in entry-common.S + */ +#define _TIF_WORK_MASK 0x000000ff + +#endif /* __KERNEL__ */ +#endif /* __UNICORE_THREAD_INFO_H__ */ diff --git a/arch/unicore32/include/asm/timex.h b/arch/unicore32/include/asm/timex.h new file mode 100644 index 000000000000..faf16ba46544 --- /dev/null +++ b/arch/unicore32/include/asm/timex.h @@ -0,0 +1,34 @@ +/* + * linux/arch/unicore32/include/asm/timex.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __UNICORE_TIMEX_H__ +#define __UNICORE_TIMEX_H__ + +#ifdef CONFIG_ARCH_FPGA + +/* in FPGA, APB clock is 33M, and OST clock is 32K, */ +/* so, 1M is selected for timer interrupt correctly */ +#define CLOCK_TICK_RATE (32*1024) + +#endif + +#if defined(CONFIG_PUV3_DB0913) \ + || defined(CONFIG_PUV3_NB0916) \ + || defined(CONFIG_PUV3_SMW0919) + +#define CLOCK_TICK_RATE (14318000) + +#endif + +#include <asm-generic/timex.h> + +#endif diff --git a/arch/unicore32/include/asm/tlb.h b/arch/unicore32/include/asm/tlb.h new file mode 100644 index 000000000000..9cca15cdae94 --- /dev/null +++ b/arch/unicore32/include/asm/tlb.h @@ -0,0 +1,28 @@ +/* + * linux/arch/unicore32/include/asm/tlb.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_TLB_H__ +#define __UNICORE_TLB_H__ + +#define tlb_start_vma(tlb, vma) do { } while (0) +#define tlb_end_vma(tlb, vma) do { } while (0) +#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0) +#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) + +#define __pte_free_tlb(tlb, pte, addr) \ + do { \ + pgtable_page_dtor(pte); \ + tlb_remove_page((tlb), (pte)); \ + } while (0) + +#include <asm-generic/tlb.h> + +#endif diff --git a/arch/unicore32/include/asm/tlbflush.h b/arch/unicore32/include/asm/tlbflush.h new file mode 100644 index 000000000000..e446ac8bb9e5 --- /dev/null +++ b/arch/unicore32/include/asm/tlbflush.h @@ -0,0 +1,195 @@ +/* + * linux/arch/unicore32/include/asm/tlbflush.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_TLBFLUSH_H__ +#define __UNICORE_TLBFLUSH_H__ + +#ifndef __ASSEMBLY__ + +#include <linux/sched.h> + +extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, + struct vm_area_struct *); +extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long); + +/* + * TLB Management + * ============== + * + * The arch/unicore/mm/tlb-*.S files implement these methods. + * + * The TLB specific code is expected to perform whatever tests it + * needs to determine if it should invalidate the TLB for each + * call. Start addresses are inclusive and end addresses are + * exclusive; it is safe to round these addresses down. + * + * flush_tlb_all() + * + * Invalidate the entire TLB. + * + * flush_tlb_mm(mm) + * + * Invalidate all TLB entries in a particular address + * space. + * - mm - mm_struct describing address space + * + * flush_tlb_range(mm,start,end) + * + * Invalidate a range of TLB entries in the specified + * address space. + * - mm - mm_struct describing address space + * - start - start address (may not be aligned) + * - end - end address (exclusive, may not be aligned) + * + * flush_tlb_page(vaddr,vma) + * + * Invalidate the specified page in the specified address range. + * - vaddr - virtual address (may not be aligned) + * - vma - vma_struct describing address range + * + * flush_kern_tlb_page(kaddr) + * + * Invalidate the TLB entry for the specified page. The address + * will be in the kernels virtual memory space. Current uses + * only require the D-TLB to be invalidated. + * - kaddr - Kernel virtual memory address + */ + +static inline void local_flush_tlb_all(void) +{ + const int zero = 0; + + /* TLB invalidate all */ + asm("movc p0.c6, %0, #6; nop; nop; nop; nop; nop; nop; nop; nop" + : : "r" (zero) : "cc"); +} + +static inline void local_flush_tlb_mm(struct mm_struct *mm) +{ + const int zero = 0; + + if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) { + /* TLB invalidate all */ + asm("movc p0.c6, %0, #6; nop; nop; nop; nop; nop; nop; nop; nop" + : : "r" (zero) : "cc"); + } + put_cpu(); +} + +static inline void +local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) +{ + if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) { +#ifndef CONFIG_CPU_TLB_SINGLE_ENTRY_DISABLE + /* iTLB invalidate page */ + asm("movc p0.c6, %0, #5; nop; nop; nop; nop; nop; nop; nop; nop" + : : "r" (uaddr & PAGE_MASK) : "cc"); + /* dTLB invalidate page */ + asm("movc p0.c6, %0, #3; nop; nop; nop; nop; nop; nop; nop; nop" + : : "r" (uaddr & PAGE_MASK) : "cc"); +#else + /* TLB invalidate all */ + asm("movc p0.c6, %0, #6; nop; nop; nop; nop; nop; nop; nop; nop" + : : "r" (uaddr & PAGE_MASK) : "cc"); +#endif + } +} + +static inline void local_flush_tlb_kernel_page(unsigned long kaddr) +{ +#ifndef CONFIG_CPU_TLB_SINGLE_ENTRY_DISABLE + /* iTLB invalidate page */ + asm("movc p0.c6, %0, #5; nop; nop; nop; nop; nop; nop; nop; nop" + : : "r" (kaddr & PAGE_MASK) : "cc"); + /* dTLB invalidate page */ + asm("movc p0.c6, %0, #3; nop; nop; nop; nop; nop; nop; nop; nop" + : : "r" (kaddr & PAGE_MASK) : "cc"); +#else + /* TLB invalidate all */ + asm("movc p0.c6, %0, #6; nop; nop; nop; nop; nop; nop; nop; nop" + : : "r" (kaddr & PAGE_MASK) : "cc"); +#endif +} + +/* + * flush_pmd_entry + * + * Flush a PMD entry (word aligned, or double-word aligned) to + * RAM if the TLB for the CPU we are running on requires this. + * This is typically used when we are creating PMD entries. + * + * clean_pmd_entry + * + * Clean (but don't drain the write buffer) if the CPU requires + * these operations. This is typically used when we are removing + * PMD entries. + */ +static inline void flush_pmd_entry(pmd_t *pmd) +{ +#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE + /* flush dcache line, see dcacheline_flush in proc-macros.S */ + asm("mov r1, %0 << #20\n" + "ldw r2, =_stext\n" + "add r2, r2, r1 >> #20\n" + "ldw r1, [r2+], #0x0000\n" + "ldw r1, [r2+], #0x1000\n" + "ldw r1, [r2+], #0x2000\n" + "ldw r1, [r2+], #0x3000\n" + : : "r" (pmd) : "r1", "r2"); +#else + /* flush dcache all */ + asm("movc p0.c5, %0, #14; nop; nop; nop; nop; nop; nop; nop; nop" + : : "r" (pmd) : "cc"); +#endif +} + +static inline void clean_pmd_entry(pmd_t *pmd) +{ +#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE + /* clean dcache line */ + asm("movc p0.c5, %0, #11; nop; nop; nop; nop; nop; nop; nop; nop" + : : "r" (__pa(pmd) & ~(L1_CACHE_BYTES - 1)) : "cc"); +#else + /* clean dcache all */ + asm("movc p0.c5, %0, #10; nop; nop; nop; nop; nop; nop; nop; nop" + : : "r" (pmd) : "cc"); +#endif +} + +/* + * Convert calls to our calling convention. + */ +#define local_flush_tlb_range(vma, start, end) \ + __cpu_flush_user_tlb_range(start, end, vma) +#define local_flush_tlb_kernel_range(s, e) \ + __cpu_flush_kern_tlb_range(s, e) + +#define flush_tlb_all local_flush_tlb_all +#define flush_tlb_mm local_flush_tlb_mm +#define flush_tlb_page local_flush_tlb_page +#define flush_tlb_kernel_page local_flush_tlb_kernel_page +#define flush_tlb_range local_flush_tlb_range +#define flush_tlb_kernel_range local_flush_tlb_kernel_range + +/* + * if PG_dcache_clean is not set for the page, we need to ensure that any + * cache entries for the kernels virtual memory range are written + * back to the page. + */ +extern void update_mmu_cache(struct vm_area_struct *vma, + unsigned long addr, pte_t *ptep); + +extern void do_bad_area(unsigned long addr, unsigned int fsr, + struct pt_regs *regs); + +#endif + +#endif diff --git a/arch/unicore32/include/asm/traps.h b/arch/unicore32/include/asm/traps.h new file mode 100644 index 000000000000..66e17a724bfe --- /dev/null +++ b/arch/unicore32/include/asm/traps.h @@ -0,0 +1,21 @@ +/* + * linux/arch/unicore32/include/asm/traps.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_TRAP_H__ +#define __UNICORE_TRAP_H__ + +extern void __init early_trap_init(void); +extern void dump_backtrace_entry(unsigned long where, + unsigned long from, unsigned long frame); + +extern void do_DataAbort(unsigned long addr, unsigned int fsr, + struct pt_regs *regs); +#endif diff --git a/arch/unicore32/include/asm/uaccess.h b/arch/unicore32/include/asm/uaccess.h new file mode 100644 index 000000000000..2acda503a6d9 --- /dev/null +++ b/arch/unicore32/include/asm/uaccess.h @@ -0,0 +1,47 @@ +/* + * linux/arch/unicore32/include/asm/uaccess.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_UACCESS_H__ +#define __UNICORE_UACCESS_H__ + +#include <linux/thread_info.h> +#include <linux/errno.h> + +#include <asm/memory.h> +#include <asm/system.h> + +#define __copy_from_user __copy_from_user +#define __copy_to_user __copy_to_user +#define __strncpy_from_user __strncpy_from_user +#define __strnlen_user __strnlen_user +#define __clear_user __clear_user + +#define __kernel_ok (segment_eq(get_fs(), KERNEL_DS)) +#define __user_ok(addr, size) (((size) <= TASK_SIZE) \ + && ((addr) <= TASK_SIZE - (size))) +#define __access_ok(addr, size) (__kernel_ok || __user_ok((addr), (size))) + +extern unsigned long __must_check +__copy_from_user(void *to, const void __user *from, unsigned long n); +extern unsigned long __must_check +__copy_to_user(void __user *to, const void *from, unsigned long n); +extern unsigned long __must_check +__clear_user(void __user *addr, unsigned long n); +extern unsigned long __must_check +__strncpy_from_user(char *to, const char __user *from, unsigned long count); +extern unsigned long +__strnlen_user(const char __user *s, long n); + +#include <asm-generic/uaccess.h> + +extern int fixup_exception(struct pt_regs *regs); + +#endif /* __UNICORE_UACCESS_H__ */ diff --git a/arch/unicore32/include/asm/unistd.h b/arch/unicore32/include/asm/unistd.h new file mode 100644 index 000000000000..9b2428019961 --- /dev/null +++ b/arch/unicore32/include/asm/unistd.h @@ -0,0 +1,18 @@ +/* + * linux/arch/unicore32/include/asm/unistd.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#if !defined(__UNICORE_UNISTD_H__) || defined(__SYSCALL) +#define __UNICORE_UNISTD_H__ + +/* Use the standard ABI for syscalls. */ +#include <asm-generic/unistd.h> + +#endif /* __UNICORE_UNISTD_H__ */ diff --git a/arch/unicore32/include/mach/PKUnity.h b/arch/unicore32/include/mach/PKUnity.h new file mode 100644 index 000000000000..a18bdc3810e6 --- /dev/null +++ b/arch/unicore32/include/mach/PKUnity.h @@ -0,0 +1,108 @@ +/* + * linux/arch/unicore32/include/mach/PKUnity.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* Be sure that virtual mapping is defined right */ +#ifndef __MACH_PUV3_HARDWARE_H__ +#error You must include hardware.h not PKUnity.h +#endif + +#include "bitfield.h" + +/* + * Memory Definitions + */ +#define PKUNITY_SDRAM_BASE 0x00000000 /* 0x00000000 - 0x7FFFFFFF 2GB */ +#define PKUNITY_MMIO_BASE 0x80000000 /* 0x80000000 - 0xFFFFFFFF 2GB */ + +/* + * PKUNITY Memory Map Addresses: 0x0D000000 - 0x0EFFFFFF (32MB) + * 0x0D000000 - 0x0DFFFFFF 16MB: for UVC + * 0x0E000000 - 0x0EFFFFFF 16MB: for UNIGFX + */ +#define PKUNITY_UVC_MMAP_BASE 0x0D000000 +#define PKUNITY_UVC_MMAP_SIZE 0x01000000 /* 16MB */ +#define PKUNITY_UNIGFX_MMAP_BASE 0x0E000000 +#define PKUNITY_UNIGFX_MMAP_SIZE 0x01000000 /* 16MB */ + +/* + * PKUNITY System Bus Addresses (PCI): 0x80000000 - 0xBFFFFFFF (1GB) + * 0x80000000 - 0x8000000B 12B PCI Configuration regs + * 0x80010000 - 0x80010250 592B PCI Bridge Base + * 0x80030000 - 0x8003FFFF 64KB PCI Legacy IO + * 0x90000000 - 0x97FFFFFF 128MB PCI AHB-PCI MEM-mapping + * 0x98000000 - 0x9FFFFFFF 128MB PCI PCI-AHB MEM-mapping + */ +#define PKUNITY_PCI_BASE io_p2v(0x80000000) /* 0x80000000 - 0xBFFFFFFF 1GB */ +#include "regs-pci.h" + +#define PKUNITY_PCICFG_BASE (PKUNITY_PCI_BASE + 0x0) +#define PKUNITY_PCIBRI_BASE (PKUNITY_PCI_BASE + 0x00010000) +#define PKUNITY_PCILIO_BASE (PKUNITY_PCI_BASE + 0x00030000) +#define PKUNITY_PCIMEM_BASE (PKUNITY_PCI_BASE + 0x10000000) +#define PKUNITY_PCIAHB_BASE (PKUNITY_PCI_BASE + 0x18000000) + +/* + * PKUNITY System Bus Addresses (AHB): 0xC0000000 - 0xEDFFFFFF (640MB) + */ +#define PKUNITY_AHB_BASE io_p2v(0xC0000000) + +/* AHB-0 is DDR2 SDRAM */ +/* AHB-1 is PCI Space */ +#define PKUNITY_ARBITER_BASE (PKUNITY_AHB_BASE + 0x000000) /* AHB-2 */ +#define PKUNITY_DDR2CTRL_BASE (PKUNITY_AHB_BASE + 0x100000) /* AHB-3 */ +#define PKUNITY_DMAC_BASE (PKUNITY_AHB_BASE + 0x200000) /* AHB-4 */ +#include "regs-dmac.h" +#define PKUNITY_UMAL_BASE (PKUNITY_AHB_BASE + 0x300000) /* AHB-5 */ +#include "regs-umal.h" +#define PKUNITY_USB_BASE (PKUNITY_AHB_BASE + 0x400000) /* AHB-6 */ +#define PKUNITY_SATA_BASE (PKUNITY_AHB_BASE + 0x500000) /* AHB-7 */ +#define PKUNITY_SMC_BASE (PKUNITY_AHB_BASE + 0x600000) /* AHB-8 */ +/* AHB-9 is for APB bridge */ +#define PKUNITY_MME_BASE (PKUNITY_AHB_BASE + 0x700000) /* AHB-10 */ +#define PKUNITY_UNIGFX_BASE (PKUNITY_AHB_BASE + 0x800000) /* AHB-11 */ +#include "regs-unigfx.h" +#define PKUNITY_NAND_BASE (PKUNITY_AHB_BASE + 0x900000) /* AHB-12 */ +#include "regs-nand.h" +#define PKUNITY_H264D_BASE (PKUNITY_AHB_BASE + 0xA00000) /* AHB-13 */ +#define PKUNITY_H264E_BASE (PKUNITY_AHB_BASE + 0xB00000) /* AHB-14 */ + +/* + * PKUNITY Peripheral Bus Addresses (APB): 0xEE000000 - 0xEFFFFFFF (128MB) + */ +#define PKUNITY_APB_BASE io_p2v(0xEE000000) + +#define PKUNITY_UART0_BASE (PKUNITY_APB_BASE + 0x000000) /* APB-0 */ +#define PKUNITY_UART1_BASE (PKUNITY_APB_BASE + 0x100000) /* APB-1 */ +#include "regs-uart.h" +#define PKUNITY_I2C_BASE (PKUNITY_APB_BASE + 0x200000) /* APB-2 */ +#include "regs-i2c.h" +#define PKUNITY_SPI_BASE (PKUNITY_APB_BASE + 0x300000) /* APB-3 */ +#include "regs-spi.h" +#define PKUNITY_AC97_BASE (PKUNITY_APB_BASE + 0x400000) /* APB-4 */ +#include "regs-ac97.h" +#define PKUNITY_GPIO_BASE (PKUNITY_APB_BASE + 0x500000) /* APB-5 */ +#include "regs-gpio.h" +#define PKUNITY_INTC_BASE (PKUNITY_APB_BASE + 0x600000) /* APB-6 */ +#include "regs-intc.h" +#define PKUNITY_RTC_BASE (PKUNITY_APB_BASE + 0x700000) /* APB-7 */ +#include "regs-rtc.h" +#define PKUNITY_OST_BASE (PKUNITY_APB_BASE + 0x800000) /* APB-8 */ +#include "regs-ost.h" +#define PKUNITY_RESETC_BASE (PKUNITY_APB_BASE + 0x900000) /* APB-9 */ +#include "regs-resetc.h" +#define PKUNITY_PM_BASE (PKUNITY_APB_BASE + 0xA00000) /* APB-10 */ +#include "regs-pm.h" +#define PKUNITY_PS2_BASE (PKUNITY_APB_BASE + 0xB00000) /* APB-11 */ +#include "regs-ps2.h" +#define PKUNITY_SDC_BASE (PKUNITY_APB_BASE + 0xC00000) /* APB-12 */ +#include "regs-sdc.h" + diff --git a/arch/unicore32/include/mach/bitfield.h b/arch/unicore32/include/mach/bitfield.h new file mode 100644 index 000000000000..128a70281efc --- /dev/null +++ b/arch/unicore32/include/mach/bitfield.h @@ -0,0 +1,24 @@ +/* + * linux/arch/unicore32/include/mach/bitfield.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __MACH_PUV3_BITFIELD_H__ +#define __MACH_PUV3_BITFIELD_H__ + +#ifndef __ASSEMBLY__ +#define UData(Data) ((unsigned long) (Data)) +#else +#define UData(Data) (Data) +#endif + +#define FIELD(val, vmask, vshift) (((val) & ((UData(1) << (vmask)) - 1)) << (vshift)) +#define FMASK(vmask, vshift) (((UData(1) << (vmask)) - 1) << (vshift)) + +#endif /* __MACH_PUV3_BITFIELD_H__ */ diff --git a/arch/unicore32/include/mach/dma.h b/arch/unicore32/include/mach/dma.h new file mode 100644 index 000000000000..d655c1b6e083 --- /dev/null +++ b/arch/unicore32/include/mach/dma.h @@ -0,0 +1,48 @@ +/* + * linux/arch/unicore32/include/mach/dma.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __MACH_PUV3_DMA_H__ +#define __MACH_PUV3_DMA_H__ + +/* + * The PKUnity has six internal DMA channels. + */ +#define MAX_DMA_CHANNELS 6 + +typedef enum { + DMA_PRIO_HIGH = 0, + DMA_PRIO_MEDIUM = 1, + DMA_PRIO_LOW = 2 +} puv3_dma_prio; + +/* + * DMA registration + */ + +extern int puv3_request_dma(char *name, + puv3_dma_prio prio, + void (*irq_handler)(int, void *), + void (*err_handler)(int, void *), + void *data); + +extern void puv3_free_dma(int dma_ch); + +static inline void puv3_stop_dma(int ch) +{ + writel(readl(DMAC_CONFIG(ch)) & ~DMAC_CONFIG_EN, DMAC_CONFIG(ch)); +} + +static inline void puv3_resume_dma(int ch) +{ + writel(readl(DMAC_CONFIG(ch)) | DMAC_CONFIG_EN, DMAC_CONFIG(ch)); +} + +#endif /* __MACH_PUV3_DMA_H__ */ diff --git a/arch/unicore32/include/mach/hardware.h b/arch/unicore32/include/mach/hardware.h new file mode 100644 index 000000000000..930bea6e129a --- /dev/null +++ b/arch/unicore32/include/mach/hardware.h @@ -0,0 +1,38 @@ +/* + * linux/arch/unicore32/include/mach/hardware.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This file contains the hardware definitions for PKUnity architecture + */ + +#ifndef __MACH_PUV3_HARDWARE_H__ +#define __MACH_PUV3_HARDWARE_H__ + +#include "PKUnity.h" + +#ifndef __ASSEMBLY__ +#define io_p2v(x) (void __iomem *)((x) - PKUNITY_MMIO_BASE) +#define io_v2p(x) (phys_addr_t)((x) + PKUNITY_MMIO_BASE) +#else +#define io_p2v(x) ((x) - PKUNITY_MMIO_BASE) +#define io_v2p(x) ((x) + PKUNITY_MMIO_BASE) +#endif + +#define PCIBIOS_MIN_IO 0x4000 /* should lower than 64KB */ +#define PCIBIOS_MIN_MEM io_v2p(PKUNITY_PCIMEM_BASE) + +/* + * We override the standard dma-mask routines for bouncing. + */ +#define HAVE_ARCH_PCI_SET_DMA_MASK + +#define pcibios_assign_all_busses() 1 + +#endif /* __MACH_PUV3_HARDWARE_H__ */ diff --git a/arch/unicore32/include/mach/map.h b/arch/unicore32/include/mach/map.h new file mode 100644 index 000000000000..55c936573741 --- /dev/null +++ b/arch/unicore32/include/mach/map.h @@ -0,0 +1,20 @@ +/* + * linux/arch/unicore32/include/mach/map.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Page table mapping constructs and function prototypes + */ +#define MT_DEVICE 0 +#define MT_DEVICE_CACHED 2 +#define MT_KUSER 7 +#define MT_HIGH_VECTORS 8 +#define MT_MEMORY 9 +#define MT_ROM 10 + diff --git a/arch/unicore32/include/mach/memory.h b/arch/unicore32/include/mach/memory.h new file mode 100644 index 000000000000..0bf21c944710 --- /dev/null +++ b/arch/unicore32/include/mach/memory.h @@ -0,0 +1,58 @@ +/* + * linux/arch/unicore32/include/mach/memory.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __MACH_PUV3_MEMORY_H__ +#define __MACH_PUV3_MEMORY_H__ + +#include <mach/hardware.h> + +/* Physical DRAM offset. */ +#define PHYS_OFFSET UL(0x00000000) +/* The base address of exception vectors. */ +#define VECTORS_BASE UL(0xffff0000) +/* The base address of kuser area. */ +#define KUSER_BASE UL(0x80000000) + +#ifdef __ASSEMBLY__ +/* The byte offset of the kernel image in RAM from the start of RAM. */ +#define KERNEL_IMAGE_START 0x00408000 +#endif + +#if !defined(__ASSEMBLY__) && defined(CONFIG_PCI) + +void puv3_pci_adjust_zones(unsigned long *size, unsigned long *holes); + +#define arch_adjust_zones(size, holes) \ + puv3_pci_adjust_zones(size, holes) + +#endif + +/* + * PCI controller in PKUnity-3 masks highest 5-bit for upstream channel, + * so we must limit the DMA allocation within 128M physical memory for + * supporting PCI devices. + */ +#define PCI_DMA_THRESHOLD (PHYS_OFFSET + SZ_128M - 1) + +#define is_pcibus_device(dev) (dev && \ + (strncmp(dev->bus->name, "pci", 3) == 0)) + +#define __virt_to_pcibus(x) (__virt_to_phys((x) + PKUNITY_PCIAHB_BASE)) +#define __pcibus_to_virt(x) (__phys_to_virt(x) - PKUNITY_PCIAHB_BASE) + +/* kuser area */ +#define KUSER_VECPAGE_BASE (KUSER_BASE + UL(0x3fff0000)) +#define KUSER_UNIGFX_BASE (PAGE_OFFSET + PKUNITY_UNIGFX_MMAP_BASE) +/* kuser_vecpage (0xbfff0000) is ro, and vectors page (0xffff0000) is rw */ +#define kuser_vecpage_to_vectors(x) ((x) - (KUSER_VECPAGE_BASE) \ + + (VECTORS_BASE)) + +#endif diff --git a/arch/unicore32/include/mach/ocd.h b/arch/unicore32/include/mach/ocd.h new file mode 100644 index 000000000000..189fd71bfa34 --- /dev/null +++ b/arch/unicore32/include/mach/ocd.h @@ -0,0 +1,36 @@ +/* + * linux/arch/unicore32/include/mach/ocd.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_PUV3_OCD_H__ +#define __MACH_PUV3_OCD_H__ + +#if defined(CONFIG_DEBUG_OCD) +static inline void ocd_putc(unsigned int c) +{ + int status, i = 0x2000000; + + do { + if (--i < 0) + return; + + asm volatile ("movc %0, p1.c0, #0" : "=r" (status)); + } while (status & 2); + + asm("movc p1.c1, %0, #1" : : "r" (c)); +} + +#define putc(ch) ocd_putc(ch) +#else +#define putc(ch) +#endif + +#endif diff --git a/arch/unicore32/include/mach/pm.h b/arch/unicore32/include/mach/pm.h new file mode 100644 index 000000000000..4dcd34ae194c --- /dev/null +++ b/arch/unicore32/include/mach/pm.h @@ -0,0 +1,43 @@ +/* + * linux/arch/unicore/include/mach/pm.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __PUV3_PM_H__ +#define __PUV3_PM_H__ + +#include <linux/suspend.h> + +struct puv3_cpu_pm_fns { + int save_count; + void (*save)(unsigned long *); + void (*restore)(unsigned long *); + int (*valid)(suspend_state_t state); + void (*enter)(suspend_state_t state); + int (*prepare)(void); + void (*finish)(void); +}; + +extern struct puv3_cpu_pm_fns *puv3_cpu_pm_fns; + +/* sleep.S */ +extern void puv3_cpu_suspend(unsigned int); + +extern void puv3_cpu_resume(void); + +extern int puv3_pm_enter(suspend_state_t state); + +/* Defined in hibernate_asm.S */ +extern int restore_image(pgd_t *resume_pg_dir, struct pbe *restore_pblist); + +/* References to section boundaries */ +extern const void __nosave_begin, __nosave_end; + +extern struct pbe *restore_pblist; +#endif diff --git a/arch/unicore32/include/mach/regs-ac97.h b/arch/unicore32/include/mach/regs-ac97.h new file mode 100644 index 000000000000..b7563e9d6503 --- /dev/null +++ b/arch/unicore32/include/mach/regs-ac97.h @@ -0,0 +1,32 @@ +/* + * PKUnity AC97 Registers + */ + +#define PKUNITY_AC97_CONR (PKUNITY_AC97_BASE + 0x0000) +#define PKUNITY_AC97_OCR (PKUNITY_AC97_BASE + 0x0004) +#define PKUNITY_AC97_ICR (PKUNITY_AC97_BASE + 0x0008) +#define PKUNITY_AC97_CRAC (PKUNITY_AC97_BASE + 0x000C) +#define PKUNITY_AC97_INTR (PKUNITY_AC97_BASE + 0x0010) +#define PKUNITY_AC97_INTRSTAT (PKUNITY_AC97_BASE + 0x0014) +#define PKUNITY_AC97_INTRCLEAR (PKUNITY_AC97_BASE + 0x0018) +#define PKUNITY_AC97_ENABLE (PKUNITY_AC97_BASE + 0x001C) +#define PKUNITY_AC97_OUT_FIFO (PKUNITY_AC97_BASE + 0x0020) +#define PKUNITY_AC97_IN_FIFO (PKUNITY_AC97_BASE + 0x0030) + +#define AC97_CODEC_REG(v) FIELD((v), 7, 16) +#define AC97_CODEC_VAL(v) FIELD((v), 16, 0) +#define AC97_CODEC_WRITECOMPLETE FIELD(1, 1, 2) + +/* + * VAR PLAY SAMPLE RATE + */ +#define AC97_CMD_VPSAMPLE (FIELD(3, 2, 16) | FIELD(3, 2, 0)) + +/* + * FIX CAPTURE SAMPLE RATE + */ +#define AC97_CMD_FCSAMPLE FIELD(7, 3, 0) + +#define AC97_CMD_RESET FIELD(1, 1, 0) +#define AC97_CMD_ENABLE FIELD(1, 1, 0) +#define AC97_CMD_DISABLE FIELD(0, 1, 0) diff --git a/arch/unicore32/include/mach/regs-dmac.h b/arch/unicore32/include/mach/regs-dmac.h new file mode 100644 index 000000000000..66de9e7d1c8f --- /dev/null +++ b/arch/unicore32/include/mach/regs-dmac.h @@ -0,0 +1,81 @@ +/* + * PKUnity Direct Memory Access Controller (DMAC) + */ + +/* + * Interrupt Status Reg DMAC_ISR. + */ +#define DMAC_ISR (PKUNITY_DMAC_BASE + 0x0020) +/* + * Interrupt Transfer Complete Status Reg DMAC_ITCSR. + */ +#define DMAC_ITCSR (PKUNITY_DMAC_BASE + 0x0050) +/* + * Interrupt Transfer Complete Clear Reg DMAC_ITCCR. + */ +#define DMAC_ITCCR (PKUNITY_DMAC_BASE + 0x0060) +/* + * Interrupt Error Status Reg DMAC_IESR. + */ +#define DMAC_IESR (PKUNITY_DMAC_BASE + 0x0080) +/* + * Interrupt Error Clear Reg DMAC_IECR. + */ +#define DMAC_IECR (PKUNITY_DMAC_BASE + 0x0090) +/* + * Enable Channels Reg DMAC_ENCH. + */ +#define DMAC_ENCH (PKUNITY_DMAC_BASE + 0x00B0) + +/* + * DMA control reg. Space [byte] + */ +#define DMASp 0x00000100 + +/* + * Source Addr DMAC_SRCADDR(ch). + */ +#define DMAC_SRCADDR(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x00) +/* + * Destination Addr DMAC_DESTADDR(ch). + */ +#define DMAC_DESTADDR(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x04) +/* + * Control Reg DMAC_CONTROL(ch). + */ +#define DMAC_CONTROL(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x0C) +/* + * Configuration Reg DMAC_CONFIG(ch). + */ +#define DMAC_CONFIG(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x10) + +#define DMAC_IR_MASK FMASK(6, 0) +/* + * select channel (ch) + */ +#define DMAC_CHANNEL(ch) FIELD(1, 1, (ch)) + +#define DMAC_CONTROL_SIZE_BYTE(v) (FIELD((v), 12, 14) | \ + FIELD(0, 3, 9) | FIELD(0, 3, 6)) +#define DMAC_CONTROL_SIZE_HWORD(v) (FIELD((v) >> 1, 12, 14) | \ + FIELD(1, 3, 9) | FIELD(1, 3, 6)) +#define DMAC_CONTROL_SIZE_WORD(v) (FIELD((v) >> 2, 12, 14) | \ + FIELD(2, 3, 9) | FIELD(2, 3, 6)) +#define DMAC_CONTROL_DI FIELD(1, 1, 13) +#define DMAC_CONTROL_SI FIELD(1, 1, 12) +#define DMAC_CONTROL_BURST_1BYTE (FIELD(0, 3, 3) | FIELD(0, 3, 0)) +#define DMAC_CONTROL_BURST_4BYTE (FIELD(3, 3, 3) | FIELD(3, 3, 0)) +#define DMAC_CONTROL_BURST_8BYTE (FIELD(5, 3, 3) | FIELD(5, 3, 0)) +#define DMAC_CONTROL_BURST_16BYTE (FIELD(7, 3, 3) | FIELD(7, 3, 0)) + +#define DMAC_CONFIG_UART0_WR (FIELD(2, 4, 11) | FIELD(1, 2, 1)) +#define DMAC_CONFIG_UART0_RD (FIELD(2, 4, 7) | FIELD(2, 2, 1)) +#define DMAC_CONFIG_UART1_WR (FIELD(3, 4, 11) | FIELD(1, 2, 1)) +#define DMAC_CONFIG_UART1RD (FIELD(3, 4, 7) | FIELD(2, 2, 1)) +#define DMAC_CONFIG_AC97WR (FIELD(4, 4, 11) | FIELD(1, 2, 1)) +#define DMAC_CONFIG_AC97RD (FIELD(4, 4, 7) | FIELD(2, 2, 1)) +#define DMAC_CONFIG_MMCWR (FIELD(7, 4, 11) | FIELD(1, 2, 1)) +#define DMAC_CONFIG_MMCRD (FIELD(7, 4, 7) | FIELD(2, 2, 1)) +#define DMAC_CONFIG_MASKITC FIELD(1, 1, 4) +#define DMAC_CONFIG_MASKIE FIELD(1, 1, 3) +#define DMAC_CONFIG_EN FIELD(1, 1, 0) diff --git a/arch/unicore32/include/mach/regs-gpio.h b/arch/unicore32/include/mach/regs-gpio.h new file mode 100644 index 000000000000..0273b861ef96 --- /dev/null +++ b/arch/unicore32/include/mach/regs-gpio.h @@ -0,0 +1,70 @@ +/* + * PKUnity General-Purpose Input/Output (GPIO) Registers + */ + +/* + * Voltage Status Reg GPIO_GPLR. + */ +#define GPIO_GPLR (PKUNITY_GPIO_BASE + 0x0000) +/* + * Pin Direction Reg GPIO_GPDR. + */ +#define GPIO_GPDR (PKUNITY_GPIO_BASE + 0x0004) +/* + * Output Pin Set Reg GPIO_GPSR. + */ +#define GPIO_GPSR (PKUNITY_GPIO_BASE + 0x0008) +/* + * Output Pin Clear Reg GPIO_GPCR. + */ +#define GPIO_GPCR (PKUNITY_GPIO_BASE + 0x000C) +/* + * Raise Edge Detect Reg GPIO_GRER. + */ +#define GPIO_GRER (PKUNITY_GPIO_BASE + 0x0010) +/* + * Fall Edge Detect Reg GPIO_GFER. + */ +#define GPIO_GFER (PKUNITY_GPIO_BASE + 0x0014) +/* + * Edge Status Reg GPIO_GEDR. + */ +#define GPIO_GEDR (PKUNITY_GPIO_BASE + 0x0018) +/* + * Sepcial Voltage Detect Reg GPIO_GPIR. + */ +#define GPIO_GPIR (PKUNITY_GPIO_BASE + 0x0020) + +#define GPIO_MIN (0) +#define GPIO_MAX (27) + +#define GPIO_GPIO(Nb) (0x00000001 << (Nb)) /* GPIO [0..27] */ +#define GPIO_GPIO0 GPIO_GPIO(0) /* GPIO [0] */ +#define GPIO_GPIO1 GPIO_GPIO(1) /* GPIO [1] */ +#define GPIO_GPIO2 GPIO_GPIO(2) /* GPIO [2] */ +#define GPIO_GPIO3 GPIO_GPIO(3) /* GPIO [3] */ +#define GPIO_GPIO4 GPIO_GPIO(4) /* GPIO [4] */ +#define GPIO_GPIO5 GPIO_GPIO(5) /* GPIO [5] */ +#define GPIO_GPIO6 GPIO_GPIO(6) /* GPIO [6] */ +#define GPIO_GPIO7 GPIO_GPIO(7) /* GPIO [7] */ +#define GPIO_GPIO8 GPIO_GPIO(8) /* GPIO [8] */ +#define GPIO_GPIO9 GPIO_GPIO(9) /* GPIO [9] */ +#define GPIO_GPIO10 GPIO_GPIO(10) /* GPIO [10] */ +#define GPIO_GPIO11 GPIO_GPIO(11) /* GPIO [11] */ +#define GPIO_GPIO12 GPIO_GPIO(12) /* GPIO [12] */ +#define GPIO_GPIO13 GPIO_GPIO(13) /* GPIO [13] */ +#define GPIO_GPIO14 GPIO_GPIO(14) /* GPIO [14] */ +#define GPIO_GPIO15 GPIO_GPIO(15) /* GPIO [15] */ +#define GPIO_GPIO16 GPIO_GPIO(16) /* GPIO [16] */ +#define GPIO_GPIO17 GPIO_GPIO(17) /* GPIO [17] */ +#define GPIO_GPIO18 GPIO_GPIO(18) /* GPIO [18] */ +#define GPIO_GPIO19 GPIO_GPIO(19) /* GPIO [19] */ +#define GPIO_GPIO20 GPIO_GPIO(20) /* GPIO [20] */ +#define GPIO_GPIO21 GPIO_GPIO(21) /* GPIO [21] */ +#define GPIO_GPIO22 GPIO_GPIO(22) /* GPIO [22] */ +#define GPIO_GPIO23 GPIO_GPIO(23) /* GPIO [23] */ +#define GPIO_GPIO24 GPIO_GPIO(24) /* GPIO [24] */ +#define GPIO_GPIO25 GPIO_GPIO(25) /* GPIO [25] */ +#define GPIO_GPIO26 GPIO_GPIO(26) /* GPIO [26] */ +#define GPIO_GPIO27 GPIO_GPIO(27) /* GPIO [27] */ + diff --git a/arch/unicore32/include/mach/regs-i2c.h b/arch/unicore32/include/mach/regs-i2c.h new file mode 100644 index 000000000000..463d108f8bfb --- /dev/null +++ b/arch/unicore32/include/mach/regs-i2c.h @@ -0,0 +1,63 @@ +/* + * PKUnity Inter-integrated Circuit (I2C) Registers + */ + +/* + * Control Reg I2C_CON. + */ +#define I2C_CON (PKUNITY_I2C_BASE + 0x0000) +/* + * Target Address Reg I2C_TAR. + */ +#define I2C_TAR (PKUNITY_I2C_BASE + 0x0004) +/* + * Data buffer and command Reg I2C_DATACMD. + */ +#define I2C_DATACMD (PKUNITY_I2C_BASE + 0x0010) +/* + * Enable Reg I2C_ENABLE. + */ +#define I2C_ENABLE (PKUNITY_I2C_BASE + 0x006C) +/* + * Status Reg I2C_STATUS. + */ +#define I2C_STATUS (PKUNITY_I2C_BASE + 0x0070) +/* + * Tx FIFO Length Reg I2C_TXFLR. + */ +#define I2C_TXFLR (PKUNITY_I2C_BASE + 0x0074) +/* + * Rx FIFO Length Reg I2C_RXFLR. + */ +#define I2C_RXFLR (PKUNITY_I2C_BASE + 0x0078) +/* + * Enable Status Reg I2C_ENSTATUS. + */ +#define I2C_ENSTATUS (PKUNITY_I2C_BASE + 0x009C) + +#define I2C_CON_MASTER FIELD(1, 1, 0) +#define I2C_CON_SPEED_STD FIELD(1, 2, 1) +#define I2C_CON_SPEED_FAST FIELD(2, 2, 1) +#define I2C_CON_RESTART FIELD(1, 1, 5) +#define I2C_CON_SLAVEDISABLE FIELD(1, 1, 6) + +#define I2C_DATACMD_READ FIELD(1, 1, 8) +#define I2C_DATACMD_WRITE FIELD(0, 1, 8) +#define I2C_DATACMD_DAT_MASK FMASK(8, 0) +#define I2C_DATACMD_DAT(v) FIELD((v), 8, 0) + +#define I2C_ENABLE_ENABLE FIELD(1, 1, 0) +#define I2C_ENABLE_DISABLE FIELD(0, 1, 0) + +#define I2C_STATUS_RFF FIELD(1, 1, 4) +#define I2C_STATUS_RFNE FIELD(1, 1, 3) +#define I2C_STATUS_TFE FIELD(1, 1, 2) +#define I2C_STATUS_TFNF FIELD(1, 1, 1) +#define I2C_STATUS_ACTIVITY FIELD(1, 1, 0) + +#define I2C_ENSTATUS_ENABLE FIELD(1, 1, 0) + +#define I2C_TAR_THERMAL 0x4f +#define I2C_TAR_SPD 0x50 +#define I2C_TAR_PWIC 0x55 +#define I2C_TAR_EEPROM 0x57 diff --git a/arch/unicore32/include/mach/regs-intc.h b/arch/unicore32/include/mach/regs-intc.h new file mode 100644 index 000000000000..25648f89cbd3 --- /dev/null +++ b/arch/unicore32/include/mach/regs-intc.h @@ -0,0 +1,28 @@ +/* + * PKUNITY Interrupt Controller (INTC) Registers + */ +/* + * INTC Level Reg INTC_ICLR. + */ +#define INTC_ICLR (PKUNITY_INTC_BASE + 0x0000) +/* + * INTC Mask Reg INTC_ICMR. + */ +#define INTC_ICMR (PKUNITY_INTC_BASE + 0x0004) +/* + * INTC Pending Reg INTC_ICPR. + */ +#define INTC_ICPR (PKUNITY_INTC_BASE + 0x0008) +/* + * INTC IRQ Pending Reg INTC_ICIP. + */ +#define INTC_ICIP (PKUNITY_INTC_BASE + 0x000C) +/* + * INTC REAL Pending Reg INTC_ICFP. + */ +#define INTC_ICFP (PKUNITY_INTC_BASE + 0x0010) +/* + * INTC Control Reg INTC_ICCR. + */ +#define INTC_ICCR (PKUNITY_INTC_BASE + 0x0014) + diff --git a/arch/unicore32/include/mach/regs-nand.h b/arch/unicore32/include/mach/regs-nand.h new file mode 100644 index 000000000000..a7c5563bb550 --- /dev/null +++ b/arch/unicore32/include/mach/regs-nand.h @@ -0,0 +1,79 @@ +/* + * PKUnity NAND Controller Registers + */ +/* + * ID Reg. 0 NAND_IDR0 + */ +#define NAND_IDR0 (PKUNITY_NAND_BASE + 0x0000) +/* + * ID Reg. 1 NAND_IDR1 + */ +#define NAND_IDR1 (PKUNITY_NAND_BASE + 0x0004) +/* + * ID Reg. 2 NAND_IDR2 + */ +#define NAND_IDR2 (PKUNITY_NAND_BASE + 0x0008) +/* + * ID Reg. 3 NAND_IDR3 + */ +#define NAND_IDR3 (PKUNITY_NAND_BASE + 0x000C) +/* + * Page Address Reg 0 NAND_PAR0 + */ +#define NAND_PAR0 (PKUNITY_NAND_BASE + 0x0010) +/* + * Page Address Reg 1 NAND_PAR1 + */ +#define NAND_PAR1 (PKUNITY_NAND_BASE + 0x0014) +/* + * Page Address Reg 2 NAND_PAR2 + */ +#define NAND_PAR2 (PKUNITY_NAND_BASE + 0x0018) +/* + * ECC Enable Reg NAND_ECCEN + */ +#define NAND_ECCEN (PKUNITY_NAND_BASE + 0x001C) +/* + * Buffer Reg NAND_BUF + */ +#define NAND_BUF (PKUNITY_NAND_BASE + 0x0020) +/* + * ECC Status Reg NAND_ECCSR + */ +#define NAND_ECCSR (PKUNITY_NAND_BASE + 0x0024) +/* + * Command Reg NAND_CMD + */ +#define NAND_CMD (PKUNITY_NAND_BASE + 0x0028) +/* + * DMA Configure Reg NAND_DMACR + */ +#define NAND_DMACR (PKUNITY_NAND_BASE + 0x002C) +/* + * Interrupt Reg NAND_IR + */ +#define NAND_IR (PKUNITY_NAND_BASE + 0x0030) +/* + * Interrupt Mask Reg NAND_IMR + */ +#define NAND_IMR (PKUNITY_NAND_BASE + 0x0034) +/* + * Chip Enable Reg NAND_CHIPEN + */ +#define NAND_CHIPEN (PKUNITY_NAND_BASE + 0x0038) +/* + * Address Reg NAND_ADDR + */ +#define NAND_ADDR (PKUNITY_NAND_BASE + 0x003C) + +/* + * Command bits NAND_CMD_CMD_MASK + */ +#define NAND_CMD_CMD_MASK FMASK(4, 4) +#define NAND_CMD_CMD_READPAGE FIELD(0x0, 4, 4) +#define NAND_CMD_CMD_ERASEBLOCK FIELD(0x6, 4, 4) +#define NAND_CMD_CMD_READSTATUS FIELD(0x7, 4, 4) +#define NAND_CMD_CMD_WRITEPAGE FIELD(0x8, 4, 4) +#define NAND_CMD_CMD_READID FIELD(0x9, 4, 4) +#define NAND_CMD_CMD_RESET FIELD(0xf, 4, 4) + diff --git a/arch/unicore32/include/mach/regs-ost.h b/arch/unicore32/include/mach/regs-ost.h new file mode 100644 index 000000000000..7b91fe698eed --- /dev/null +++ b/arch/unicore32/include/mach/regs-ost.h @@ -0,0 +1,92 @@ +/* + * PKUnity Operating System Timer (OST) Registers + */ +/* + * Match Reg 0 OST_OSMR0 + */ +#define OST_OSMR0 (PKUNITY_OST_BASE + 0x0000) +/* + * Match Reg 1 OST_OSMR1 + */ +#define OST_OSMR1 (PKUNITY_OST_BASE + 0x0004) +/* + * Match Reg 2 OST_OSMR2 + */ +#define OST_OSMR2 (PKUNITY_OST_BASE + 0x0008) +/* + * Match Reg 3 OST_OSMR3 + */ +#define OST_OSMR3 (PKUNITY_OST_BASE + 0x000C) +/* + * Counter Reg OST_OSCR + */ +#define OST_OSCR (PKUNITY_OST_BASE + 0x0010) +/* + * Status Reg OST_OSSR + */ +#define OST_OSSR (PKUNITY_OST_BASE + 0x0014) +/* + * Watchdog Enable Reg OST_OWER + */ +#define OST_OWER (PKUNITY_OST_BASE + 0x0018) +/* + * Interrupt Enable Reg OST_OIER + */ +#define OST_OIER (PKUNITY_OST_BASE + 0x001C) +/* + * PWM Pulse Width Control Reg OST_PWMPWCR + */ +#define OST_PWMPWCR (PKUNITY_OST_BASE + 0x0080) +/* + * PWM Duty Cycle Control Reg OST_PWMDCCR + */ +#define OST_PWMDCCR (PKUNITY_OST_BASE + 0x0084) +/* + * PWM Period Control Reg OST_PWMPCR + */ +#define OST_PWMPCR (PKUNITY_OST_BASE + 0x0088) + +/* + * Match detected 0 OST_OSSR_M0 + */ +#define OST_OSSR_M0 FIELD(1, 1, 0) +/* + * Match detected 1 OST_OSSR_M1 + */ +#define OST_OSSR_M1 FIELD(1, 1, 1) +/* + * Match detected 2 OST_OSSR_M2 + */ +#define OST_OSSR_M2 FIELD(1, 1, 2) +/* + * Match detected 3 OST_OSSR_M3 + */ +#define OST_OSSR_M3 FIELD(1, 1, 3) + +/* + * Interrupt enable 0 OST_OIER_E0 + */ +#define OST_OIER_E0 FIELD(1, 1, 0) +/* + * Interrupt enable 1 OST_OIER_E1 + */ +#define OST_OIER_E1 FIELD(1, 1, 1) +/* + * Interrupt enable 2 OST_OIER_E2 + */ +#define OST_OIER_E2 FIELD(1, 1, 2) +/* + * Interrupt enable 3 OST_OIER_E3 + */ +#define OST_OIER_E3 FIELD(1, 1, 3) + +/* + * Watchdog Match Enable OST_OWER_WME + */ +#define OST_OWER_WME FIELD(1, 1, 0) + +/* + * PWM Full Duty Cycle OST_PWMDCCR_FDCYCLE + */ +#define OST_PWMDCCR_FDCYCLE FIELD(1, 1, 10) + diff --git a/arch/unicore32/include/mach/regs-pci.h b/arch/unicore32/include/mach/regs-pci.h new file mode 100644 index 000000000000..6a9341686bf8 --- /dev/null +++ b/arch/unicore32/include/mach/regs-pci.h @@ -0,0 +1,94 @@ +/* + * PKUnity AHB-PCI Bridge Registers + */ + +/* + * AHB/PCI fixed physical address for pci addess configuration + */ +/* + * PCICFG Bridge Base Reg. + */ +#define PCICFG_BRIBASE (PKUNITY_PCICFG_BASE + 0x0000) +/* + * PCICFG Address Reg. + */ +#define PCICFG_ADDR (PKUNITY_PCICFG_BASE + 0x0004) +/* + * PCICFG Address Reg. + */ +#define PCICFG_DATA (PKUNITY_PCICFG_BASE + 0x0008) + +/* + * PCI Bridge configuration space + */ +#define PCIBRI_ID (PKUNITY_PCIBRI_BASE + 0x0000) +#define PCIBRI_CMD (PKUNITY_PCIBRI_BASE + 0x0004) +#define PCIBRI_CLASS (PKUNITY_PCIBRI_BASE + 0x0008) +#define PCIBRI_LTR (PKUNITY_PCIBRI_BASE + 0x000C) +#define PCIBRI_BAR0 (PKUNITY_PCIBRI_BASE + 0x0010) +#define PCIBRI_BAR1 (PKUNITY_PCIBRI_BASE + 0x0014) +#define PCIBRI_BAR2 (PKUNITY_PCIBRI_BASE + 0x0018) +#define PCIBRI_BAR3 (PKUNITY_PCIBRI_BASE + 0x001C) +#define PCIBRI_BAR4 (PKUNITY_PCIBRI_BASE + 0x0020) +#define PCIBRI_BAR5 (PKUNITY_PCIBRI_BASE + 0x0024) + +#define PCIBRI_PCICTL0 (PKUNITY_PCIBRI_BASE + 0x0100) +#define PCIBRI_PCIBAR0 (PKUNITY_PCIBRI_BASE + 0x0104) +#define PCIBRI_PCIAMR0 (PKUNITY_PCIBRI_BASE + 0x0108) +#define PCIBRI_PCITAR0 (PKUNITY_PCIBRI_BASE + 0x010C) +#define PCIBRI_PCICTL1 (PKUNITY_PCIBRI_BASE + 0x0110) +#define PCIBRI_PCIBAR1 (PKUNITY_PCIBRI_BASE + 0x0114) +#define PCIBRI_PCIAMR1 (PKUNITY_PCIBRI_BASE + 0x0118) +#define PCIBRI_PCITAR1 (PKUNITY_PCIBRI_BASE + 0x011C) +#define PCIBRI_PCICTL2 (PKUNITY_PCIBRI_BASE + 0x0120) +#define PCIBRI_PCIBAR2 (PKUNITY_PCIBRI_BASE + 0x0124) +#define PCIBRI_PCIAMR2 (PKUNITY_PCIBRI_BASE + 0x0128) +#define PCIBRI_PCITAR2 (PKUNITY_PCIBRI_BASE + 0x012C) +#define PCIBRI_PCICTL3 (PKUNITY_PCIBRI_BASE + 0x0130) +#define PCIBRI_PCIBAR3 (PKUNITY_PCIBRI_BASE + 0x0134) +#define PCIBRI_PCIAMR3 (PKUNITY_PCIBRI_BASE + 0x0138) +#define PCIBRI_PCITAR3 (PKUNITY_PCIBRI_BASE + 0x013C) +#define PCIBRI_PCICTL4 (PKUNITY_PCIBRI_BASE + 0x0140) +#define PCIBRI_PCIBAR4 (PKUNITY_PCIBRI_BASE + 0x0144) +#define PCIBRI_PCIAMR4 (PKUNITY_PCIBRI_BASE + 0x0148) +#define PCIBRI_PCITAR4 (PKUNITY_PCIBRI_BASE + 0x014C) +#define PCIBRI_PCICTL5 (PKUNITY_PCIBRI_BASE + 0x0150) +#define PCIBRI_PCIBAR5 (PKUNITY_PCIBRI_BASE + 0x0154) +#define PCIBRI_PCIAMR5 (PKUNITY_PCIBRI_BASE + 0x0158) +#define PCIBRI_PCITAR5 (PKUNITY_PCIBRI_BASE + 0x015C) + +#define PCIBRI_AHBCTL0 (PKUNITY_PCIBRI_BASE + 0x0180) +#define PCIBRI_AHBBAR0 (PKUNITY_PCIBRI_BASE + 0x0184) +#define PCIBRI_AHBAMR0 (PKUNITY_PCIBRI_BASE + 0x0188) +#define PCIBRI_AHBTAR0 (PKUNITY_PCIBRI_BASE + 0x018C) +#define PCIBRI_AHBCTL1 (PKUNITY_PCIBRI_BASE + 0x0190) +#define PCIBRI_AHBBAR1 (PKUNITY_PCIBRI_BASE + 0x0194) +#define PCIBRI_AHBAMR1 (PKUNITY_PCIBRI_BASE + 0x0198) +#define PCIBRI_AHBTAR1 (PKUNITY_PCIBRI_BASE + 0x019C) +#define PCIBRI_AHBCTL2 (PKUNITY_PCIBRI_BASE + 0x01A0) +#define PCIBRI_AHBBAR2 (PKUNITY_PCIBRI_BASE + 0x01A4) +#define PCIBRI_AHBAMR2 (PKUNITY_PCIBRI_BASE + 0x01A8) +#define PCIBRI_AHBTAR2 (PKUNITY_PCIBRI_BASE + 0x01AC) +#define PCIBRI_AHBCTL3 (PKUNITY_PCIBRI_BASE + 0x01B0) +#define PCIBRI_AHBBAR3 (PKUNITY_PCIBRI_BASE + 0x01B4) +#define PCIBRI_AHBAMR3 (PKUNITY_PCIBRI_BASE + 0x01B8) +#define PCIBRI_AHBTAR3 (PKUNITY_PCIBRI_BASE + 0x01BC) +#define PCIBRI_AHBCTL4 (PKUNITY_PCIBRI_BASE + 0x01C0) +#define PCIBRI_AHBBAR4 (PKUNITY_PCIBRI_BASE + 0x01C4) +#define PCIBRI_AHBAMR4 (PKUNITY_PCIBRI_BASE + 0x01C8) +#define PCIBRI_AHBTAR4 (PKUNITY_PCIBRI_BASE + 0x01CC) +#define PCIBRI_AHBCTL5 (PKUNITY_PCIBRI_BASE + 0x01D0) +#define PCIBRI_AHBBAR5 (PKUNITY_PCIBRI_BASE + 0x01D4) +#define PCIBRI_AHBAMR5 (PKUNITY_PCIBRI_BASE + 0x01D8) +#define PCIBRI_AHBTAR5 (PKUNITY_PCIBRI_BASE + 0x01DC) + +#define PCIBRI_CTLx_AT FIELD(1, 1, 2) +#define PCIBRI_CTLx_PREF FIELD(1, 1, 1) +#define PCIBRI_CTLx_MRL FIELD(1, 1, 0) + +#define PCIBRI_BARx_ADDR FIELD(0xFFFFFFFC, 30, 2) +#define PCIBRI_BARx_IO FIELD(1, 1, 0) +#define PCIBRI_BARx_MEM FIELD(0, 1, 0) + +#define PCIBRI_CMD_IO FIELD(1, 1, 0) +#define PCIBRI_CMD_MEM FIELD(1, 1, 1) diff --git a/arch/unicore32/include/mach/regs-pm.h b/arch/unicore32/include/mach/regs-pm.h new file mode 100644 index 000000000000..854844aa8f4b --- /dev/null +++ b/arch/unicore32/include/mach/regs-pm.h @@ -0,0 +1,126 @@ +/* + * PKUNITY Power Manager (PM) Registers + */ +/* + * PM Control Reg PM_PMCR + */ +#define PM_PMCR (PKUNITY_PM_BASE + 0x0000) +/* + * PM General Conf. Reg PM_PGCR + */ +#define PM_PGCR (PKUNITY_PM_BASE + 0x0004) +/* + * PM PLL Conf. Reg PM_PPCR + */ +#define PM_PPCR (PKUNITY_PM_BASE + 0x0008) +/* + * PM Wakeup Enable Reg PM_PWER + */ +#define PM_PWER (PKUNITY_PM_BASE + 0x000C) +/* + * PM GPIO Sleep Status Reg PM_PGSR + */ +#define PM_PGSR (PKUNITY_PM_BASE + 0x0010) +/* + * PM Clock Gate Reg PM_PCGR + */ +#define PM_PCGR (PKUNITY_PM_BASE + 0x0014) +/* + * PM SYS PLL Conf. Reg PM_PLLSYSCFG + */ +#define PM_PLLSYSCFG (PKUNITY_PM_BASE + 0x0018) +/* + * PM DDR PLL Conf. Reg PM_PLLDDRCFG + */ +#define PM_PLLDDRCFG (PKUNITY_PM_BASE + 0x001C) +/* + * PM VGA PLL Conf. Reg PM_PLLVGACFG + */ +#define PM_PLLVGACFG (PKUNITY_PM_BASE + 0x0020) +/* + * PM Div Conf. Reg PM_DIVCFG + */ +#define PM_DIVCFG (PKUNITY_PM_BASE + 0x0024) +/* + * PM SYS PLL Status Reg PM_PLLSYSSTATUS + */ +#define PM_PLLSYSSTATUS (PKUNITY_PM_BASE + 0x0028) +/* + * PM DDR PLL Status Reg PM_PLLDDRSTATUS + */ +#define PM_PLLDDRSTATUS (PKUNITY_PM_BASE + 0x002C) +/* + * PM VGA PLL Status Reg PM_PLLVGASTATUS + */ +#define PM_PLLVGASTATUS (PKUNITY_PM_BASE + 0x0030) +/* + * PM Div Status Reg PM_DIVSTATUS + */ +#define PM_DIVSTATUS (PKUNITY_PM_BASE + 0x0034) +/* + * PM Software Reset Reg PM_SWRESET + */ +#define PM_SWRESET (PKUNITY_PM_BASE + 0x0038) +/* + * PM DDR2 PAD Start Reg PM_DDR2START + */ +#define PM_DDR2START (PKUNITY_PM_BASE + 0x003C) +/* + * PM DDR2 PAD Status Reg PM_DDR2CAL0 + */ +#define PM_DDR2CAL0 (PKUNITY_PM_BASE + 0x0040) +/* + * PM PLL DFC Done Reg PM_PLLDFCDONE + */ +#define PM_PLLDFCDONE (PKUNITY_PM_BASE + 0x0044) + +#define PM_PMCR_SFB FIELD(1, 1, 0) +#define PM_PMCR_IFB FIELD(1, 1, 1) +#define PM_PMCR_CFBSYS FIELD(1, 1, 2) +#define PM_PMCR_CFBDDR FIELD(1, 1, 3) +#define PM_PMCR_CFBVGA FIELD(1, 1, 4) +#define PM_PMCR_CFBDIVBCLK FIELD(1, 1, 5) + +/* + * GPIO 8~27 wake-up enable PM_PWER_GPIOHIGH + */ +#define PM_PWER_GPIOHIGH FIELD(1, 1, 8) +/* + * RTC alarm wake-up enable PM_PWER_RTC + */ +#define PM_PWER_RTC FIELD(1, 1, 31) + +#define PM_PCGR_BCLK64DDR FIELD(1, 1, 0) +#define PM_PCGR_BCLK64VGA FIELD(1, 1, 1) +#define PM_PCGR_BCLKDDR FIELD(1, 1, 2) +#define PM_PCGR_BCLKPCI FIELD(1, 1, 4) +#define PM_PCGR_BCLKDMAC FIELD(1, 1, 5) +#define PM_PCGR_BCLKUMAL FIELD(1, 1, 6) +#define PM_PCGR_BCLKUSB FIELD(1, 1, 7) +#define PM_PCGR_BCLKMME FIELD(1, 1, 10) +#define PM_PCGR_BCLKNAND FIELD(1, 1, 11) +#define PM_PCGR_BCLKH264E FIELD(1, 1, 12) +#define PM_PCGR_BCLKVGA FIELD(1, 1, 13) +#define PM_PCGR_BCLKH264D FIELD(1, 1, 14) +#define PM_PCGR_VECLK FIELD(1, 1, 15) +#define PM_PCGR_HECLK FIELD(1, 1, 16) +#define PM_PCGR_HDCLK FIELD(1, 1, 17) +#define PM_PCGR_NANDCLK FIELD(1, 1, 18) +#define PM_PCGR_GECLK FIELD(1, 1, 19) +#define PM_PCGR_VGACLK FIELD(1, 1, 20) +#define PM_PCGR_PCICLK FIELD(1, 1, 21) +#define PM_PCGR_SATACLK FIELD(1, 1, 25) + +/* + * [23:20]PM_DIVCFG_VGACLK(v) + */ +#define PM_DIVCFG_VGACLK_MASK FMASK(4, 20) +#define PM_DIVCFG_VGACLK(v) FIELD((v), 4, 20) + +#define PM_SWRESET_USB FIELD(1, 1, 6) +#define PM_SWRESET_VGADIV FIELD(1, 1, 26) +#define PM_SWRESET_GEDIV FIELD(1, 1, 27) + +#define PM_PLLDFCDONE_SYSDFC FIELD(1, 1, 0) +#define PM_PLLDFCDONE_DDRDFC FIELD(1, 1, 1) +#define PM_PLLDFCDONE_VGADFC FIELD(1, 1, 2) diff --git a/arch/unicore32/include/mach/regs-ps2.h b/arch/unicore32/include/mach/regs-ps2.h new file mode 100644 index 000000000000..17d4e6dc0069 --- /dev/null +++ b/arch/unicore32/include/mach/regs-ps2.h @@ -0,0 +1,20 @@ +/* + * PKUnity PS2 Controller Registers + */ +/* + * the same as I8042_DATA_REG PS2_DATA + */ +#define PS2_DATA (PKUNITY_PS2_BASE + 0x0060) +/* + * the same as I8042_COMMAND_REG PS2_COMMAND + */ +#define PS2_COMMAND (PKUNITY_PS2_BASE + 0x0064) +/* + * the same as I8042_STATUS_REG PS2_STATUS + */ +#define PS2_STATUS (PKUNITY_PS2_BASE + 0x0064) +/* + * counter reg PS2_CNT + */ +#define PS2_CNT (PKUNITY_PS2_BASE + 0x0068) + diff --git a/arch/unicore32/include/mach/regs-resetc.h b/arch/unicore32/include/mach/regs-resetc.h new file mode 100644 index 000000000000..39900cf4c936 --- /dev/null +++ b/arch/unicore32/include/mach/regs-resetc.h @@ -0,0 +1,34 @@ +/* + * PKUnity Reset Controller (RC) Registers + */ +/* + * Software Reset Register + */ +#define RESETC_SWRR (PKUNITY_RESETC_BASE + 0x0000) +/* + * Reset Status Register + */ +#define RESETC_RSSR (PKUNITY_RESETC_BASE + 0x0004) + +/* + * Software Reset Bit + */ +#define RESETC_SWRR_SRB FIELD(1, 1, 0) + +/* + * Hardware Reset + */ +#define RESETC_RSSR_HWR FIELD(1, 1, 0) +/* + * Software Reset + */ +#define RESETC_RSSR_SWR FIELD(1, 1, 1) +/* + * Watchdog Reset + */ +#define RESETC_RSSR_WDR FIELD(1, 1, 2) +/* + * Sleep Mode Reset + */ +#define RESETC_RSSR_SMR FIELD(1, 1, 3) + diff --git a/arch/unicore32/include/mach/regs-rtc.h b/arch/unicore32/include/mach/regs-rtc.h new file mode 100644 index 000000000000..e94ca193271d --- /dev/null +++ b/arch/unicore32/include/mach/regs-rtc.h @@ -0,0 +1,37 @@ +/* + * PKUnity Real-Time Clock (RTC) control registers + */ +/* + * RTC Alarm Reg RTC_RTAR + */ +#define RTC_RTAR (PKUNITY_RTC_BASE + 0x0000) +/* + * RTC Count Reg RTC_RCNR + */ +#define RTC_RCNR (PKUNITY_RTC_BASE + 0x0004) +/* + * RTC Trim Reg RTC_RTTR + */ +#define RTC_RTTR (PKUNITY_RTC_BASE + 0x0008) +/* + * RTC Status Reg RTC_RTSR + */ +#define RTC_RTSR (PKUNITY_RTC_BASE + 0x0010) + +/* + * ALarm detected RTC_RTSR_AL + */ +#define RTC_RTSR_AL FIELD(1, 1, 0) +/* + * 1 Hz clock detected RTC_RTSR_HZ + */ +#define RTC_RTSR_HZ FIELD(1, 1, 1) +/* + * ALarm interrupt Enable RTC_RTSR_ALE + */ +#define RTC_RTSR_ALE FIELD(1, 1, 2) +/* + * 1 Hz clock interrupt Enable RTC_RTSR_HZE + */ +#define RTC_RTSR_HZE FIELD(1, 1, 3) + diff --git a/arch/unicore32/include/mach/regs-sdc.h b/arch/unicore32/include/mach/regs-sdc.h new file mode 100644 index 000000000000..1303ecf660ba --- /dev/null +++ b/arch/unicore32/include/mach/regs-sdc.h @@ -0,0 +1,156 @@ +/* + * PKUnity Multi-Media Card and Security Digital Card (MMC/SD) Registers + */ +/* + * Clock Control Reg SDC_CCR + */ +#define SDC_CCR (PKUNITY_SDC_BASE + 0x0000) +/* + * Software Reset Reg SDC_SRR + */ +#define SDC_SRR (PKUNITY_SDC_BASE + 0x0004) +/* + * Argument Reg SDC_ARGUMENT + */ +#define SDC_ARGUMENT (PKUNITY_SDC_BASE + 0x0008) +/* + * Command Reg SDC_COMMAND + */ +#define SDC_COMMAND (PKUNITY_SDC_BASE + 0x000C) +/* + * Block Size Reg SDC_BLOCKSIZE + */ +#define SDC_BLOCKSIZE (PKUNITY_SDC_BASE + 0x0010) +/* + * Block Cound Reg SDC_BLOCKCOUNT + */ +#define SDC_BLOCKCOUNT (PKUNITY_SDC_BASE + 0x0014) +/* + * Transfer Mode Reg SDC_TMR + */ +#define SDC_TMR (PKUNITY_SDC_BASE + 0x0018) +/* + * Response Reg. 0 SDC_RES0 + */ +#define SDC_RES0 (PKUNITY_SDC_BASE + 0x001C) +/* + * Response Reg. 1 SDC_RES1 + */ +#define SDC_RES1 (PKUNITY_SDC_BASE + 0x0020) +/* + * Response Reg. 2 SDC_RES2 + */ +#define SDC_RES2 (PKUNITY_SDC_BASE + 0x0024) +/* + * Response Reg. 3 SDC_RES3 + */ +#define SDC_RES3 (PKUNITY_SDC_BASE + 0x0028) +/* + * Read Timeout Control Reg SDC_RTCR + */ +#define SDC_RTCR (PKUNITY_SDC_BASE + 0x002C) +/* + * Interrupt Status Reg SDC_ISR + */ +#define SDC_ISR (PKUNITY_SDC_BASE + 0x0030) +/* + * Interrupt Status Mask Reg SDC_ISMR + */ +#define SDC_ISMR (PKUNITY_SDC_BASE + 0x0034) +/* + * RX FIFO SDC_RXFIFO + */ +#define SDC_RXFIFO (PKUNITY_SDC_BASE + 0x0038) +/* + * TX FIFO SDC_TXFIFO + */ +#define SDC_TXFIFO (PKUNITY_SDC_BASE + 0x003C) + +/* + * SD Clock Enable SDC_CCR_CLKEN + */ +#define SDC_CCR_CLKEN FIELD(1, 1, 2) +/* + * [15:8] SDC_CCR_PDIV(v) + */ +#define SDC_CCR_PDIV(v) FIELD((v), 8, 8) + +/* + * Software reset enable SDC_SRR_ENABLE + */ +#define SDC_SRR_ENABLE FIELD(0, 1, 0) +/* + * Software reset disable SDC_SRR_DISABLE + */ +#define SDC_SRR_DISABLE FIELD(1, 1, 0) + +/* + * Response type SDC_COMMAND_RESTYPE_MASK + */ +#define SDC_COMMAND_RESTYPE_MASK FMASK(2, 0) +/* + * No response SDC_COMMAND_RESTYPE_NONE + */ +#define SDC_COMMAND_RESTYPE_NONE FIELD(0, 2, 0) +/* + * 136-bit long response SDC_COMMAND_RESTYPE_LONG + */ +#define SDC_COMMAND_RESTYPE_LONG FIELD(1, 2, 0) +/* + * 48-bit short response SDC_COMMAND_RESTYPE_SHORT + */ +#define SDC_COMMAND_RESTYPE_SHORT FIELD(2, 2, 0) +/* + * 48-bit short and test if busy response SDC_COMMAND_RESTYPE_SHORTBUSY + */ +#define SDC_COMMAND_RESTYPE_SHORTBUSY FIELD(3, 2, 0) +/* + * data ready SDC_COMMAND_DATAREADY + */ +#define SDC_COMMAND_DATAREADY FIELD(1, 1, 2) +#define SDC_COMMAND_CMDEN FIELD(1, 1, 3) +/* + * [10:5] SDC_COMMAND_CMDINDEX(v) + */ +#define SDC_COMMAND_CMDINDEX(v) FIELD((v), 6, 5) + +/* + * [10:0] SDC_BLOCKSIZE_BSMASK(v) + */ +#define SDC_BLOCKSIZE_BSMASK(v) FIELD((v), 11, 0) +/* + * [11:0] SDC_BLOCKCOUNT_BCMASK(v) + */ +#define SDC_BLOCKCOUNT_BCMASK(v) FIELD((v), 12, 0) + +/* + * Data Width 1bit SDC_TMR_WTH_1BIT + */ +#define SDC_TMR_WTH_1BIT FIELD(0, 1, 0) +/* + * Data Width 4bit SDC_TMR_WTH_4BIT + */ +#define SDC_TMR_WTH_4BIT FIELD(1, 1, 0) +/* + * Read SDC_TMR_DIR_READ + */ +#define SDC_TMR_DIR_READ FIELD(0, 1, 1) +/* + * Write SDC_TMR_DIR_WRITE + */ +#define SDC_TMR_DIR_WRITE FIELD(1, 1, 1) + +#define SDC_IR_MASK FMASK(13, 0) +#define SDC_IR_RESTIMEOUT FIELD(1, 1, 0) +#define SDC_IR_WRITECRC FIELD(1, 1, 1) +#define SDC_IR_READCRC FIELD(1, 1, 2) +#define SDC_IR_TXFIFOREAD FIELD(1, 1, 3) +#define SDC_IR_RXFIFOWRITE FIELD(1, 1, 4) +#define SDC_IR_READTIMEOUT FIELD(1, 1, 5) +#define SDC_IR_DATACOMPLETE FIELD(1, 1, 6) +#define SDC_IR_CMDCOMPLETE FIELD(1, 1, 7) +#define SDC_IR_RXFIFOFULL FIELD(1, 1, 8) +#define SDC_IR_RXFIFOEMPTY FIELD(1, 1, 9) +#define SDC_IR_TXFIFOFULL FIELD(1, 1, 10) +#define SDC_IR_TXFIFOEMPTY FIELD(1, 1, 11) +#define SDC_IR_ENDCMDWITHRES FIELD(1, 1, 12) diff --git a/arch/unicore32/include/mach/regs-spi.h b/arch/unicore32/include/mach/regs-spi.h new file mode 100644 index 000000000000..de16895e2dc0 --- /dev/null +++ b/arch/unicore32/include/mach/regs-spi.h @@ -0,0 +1,98 @@ +/* + * PKUnity Serial Peripheral Interface (SPI) Registers + */ +/* + * Control reg. 0 SPI_CR0 + */ +#define SPI_CR0 (PKUNITY_SPI_BASE + 0x0000) +/* + * Control reg. 1 SPI_CR1 + */ +#define SPI_CR1 (PKUNITY_SPI_BASE + 0x0004) +/* + * Enable reg SPI_SSIENR + */ +#define SPI_SSIENR (PKUNITY_SPI_BASE + 0x0008) +/* + * Status reg SPI_SR + */ +#define SPI_SR (PKUNITY_SPI_BASE + 0x0028) +/* + * Interrupt Mask reg SPI_IMR + */ +#define SPI_IMR (PKUNITY_SPI_BASE + 0x002C) +/* + * Interrupt Status reg SPI_ISR + */ +#define SPI_ISR (PKUNITY_SPI_BASE + 0x0030) + +/* + * Enable SPI Controller SPI_SSIENR_EN + */ +#define SPI_SSIENR_EN FIELD(1, 1, 0) + +/* + * SPI Busy SPI_SR_BUSY + */ +#define SPI_SR_BUSY FIELD(1, 1, 0) +/* + * Transmit FIFO Not Full SPI_SR_TFNF + */ +#define SPI_SR_TFNF FIELD(1, 1, 1) +/* + * Transmit FIFO Empty SPI_SR_TFE + */ +#define SPI_SR_TFE FIELD(1, 1, 2) +/* + * Receive FIFO Not Empty SPI_SR_RFNE + */ +#define SPI_SR_RFNE FIELD(1, 1, 3) +/* + * Receive FIFO Full SPI_SR_RFF + */ +#define SPI_SR_RFF FIELD(1, 1, 4) + +/* + * Trans. FIFO Empty Interrupt Status SPI_ISR_TXEIS + */ +#define SPI_ISR_TXEIS FIELD(1, 1, 0) +/* + * Trans. FIFO Overflow Interrupt Status SPI_ISR_TXOIS + */ +#define SPI_ISR_TXOIS FIELD(1, 1, 1) +/* + * Receiv. FIFO Underflow Interrupt Status SPI_ISR_RXUIS + */ +#define SPI_ISR_RXUIS FIELD(1, 1, 2) +/* + * Receiv. FIFO Overflow Interrupt Status SPI_ISR_RXOIS + */ +#define SPI_ISR_RXOIS FIELD(1, 1, 3) +/* + * Receiv. FIFO Full Interrupt Status SPI_ISR_RXFIS + */ +#define SPI_ISR_RXFIS FIELD(1, 1, 4) +#define SPI_ISR_MSTIS FIELD(1, 1, 5) + +/* + * Trans. FIFO Empty Interrupt Mask SPI_IMR_TXEIM + */ +#define SPI_IMR_TXEIM FIELD(1, 1, 0) +/* + * Trans. FIFO Overflow Interrupt Mask SPI_IMR_TXOIM + */ +#define SPI_IMR_TXOIM FIELD(1, 1, 1) +/* + * Receiv. FIFO Underflow Interrupt Mask SPI_IMR_RXUIM + */ +#define SPI_IMR_RXUIM FIELD(1, 1, 2) +/* + * Receiv. FIFO Overflow Interrupt Mask SPI_IMR_RXOIM + */ +#define SPI_IMR_RXOIM FIELD(1, 1, 3) +/* + * Receiv. FIFO Full Interrupt Mask SPI_IMR_RXFIM + */ +#define SPI_IMR_RXFIM FIELD(1, 1, 4) +#define SPI_IMR_MSTIM FIELD(1, 1, 5) + diff --git a/arch/unicore32/include/mach/regs-uart.h b/arch/unicore32/include/mach/regs-uart.h new file mode 100644 index 000000000000..9fa6b1938b77 --- /dev/null +++ b/arch/unicore32/include/mach/regs-uart.h @@ -0,0 +1,3 @@ +/* + * PKUnity Universal Asynchronous Receiver/Transmitter (UART) Registers + */ diff --git a/arch/unicore32/include/mach/regs-umal.h b/arch/unicore32/include/mach/regs-umal.h new file mode 100644 index 000000000000..885bb62fee71 --- /dev/null +++ b/arch/unicore32/include/mach/regs-umal.h @@ -0,0 +1,229 @@ +/* + * PKUnity Ultra Media Access Layer (UMAL) Ethernet MAC Registers + */ + +/* MAC module of UMAL */ +/* UMAL's MAC module includes G/MII interface, several additional PHY + * interfaces, and MAC control sub-layer, which provides support for control + * frames (e.g. PAUSE frames). + */ +/* + * TX/RX reset and control UMAL_CFG1 + */ +#define UMAL_CFG1 (PKUNITY_UMAL_BASE + 0x0000) +/* + * MAC interface mode control UMAL_CFG2 + */ +#define UMAL_CFG2 (PKUNITY_UMAL_BASE + 0x0004) +/* + * Inter Packet/Frame Gap UMAL_IPGIFG + */ +#define UMAL_IPGIFG (PKUNITY_UMAL_BASE + 0x0008) +/* + * Collision retry or backoff UMAL_HALFDUPLEX + */ +#define UMAL_HALFDUPLEX (PKUNITY_UMAL_BASE + 0x000c) +/* + * Maximum Frame Length UMAL_MAXFRAME + */ +#define UMAL_MAXFRAME (PKUNITY_UMAL_BASE + 0x0010) +/* + * Test Regsiter UMAL_TESTREG + */ +#define UMAL_TESTREG (PKUNITY_UMAL_BASE + 0x001c) +/* + * MII Management Configure UMAL_MIICFG + */ +#define UMAL_MIICFG (PKUNITY_UMAL_BASE + 0x0020) +/* + * MII Management Command UMAL_MIICMD + */ +#define UMAL_MIICMD (PKUNITY_UMAL_BASE + 0x0024) +/* + * MII Management Address UMAL_MIIADDR + */ +#define UMAL_MIIADDR (PKUNITY_UMAL_BASE + 0x0028) +/* + * MII Management Control UMAL_MIICTRL + */ +#define UMAL_MIICTRL (PKUNITY_UMAL_BASE + 0x002c) +/* + * MII Management Status UMAL_MIISTATUS + */ +#define UMAL_MIISTATUS (PKUNITY_UMAL_BASE + 0x0030) +/* + * MII Managment Indicator UMAL_MIIIDCT + */ +#define UMAL_MIIIDCT (PKUNITY_UMAL_BASE + 0x0034) +/* + * Interface Control UMAL_IFCTRL + */ +#define UMAL_IFCTRL (PKUNITY_UMAL_BASE + 0x0038) +/* + * Interface Status UMAL_IFSTATUS + */ +#define UMAL_IFSTATUS (PKUNITY_UMAL_BASE + 0x003c) +/* + * MAC address (high 4 bytes) UMAL_STADDR1 + */ +#define UMAL_STADDR1 (PKUNITY_UMAL_BASE + 0x0040) +/* + * MAC address (low 2 bytes) UMAL_STADDR2 + */ +#define UMAL_STADDR2 (PKUNITY_UMAL_BASE + 0x0044) + +/* FIFO MODULE OF UMAL */ +/* UMAL's FIFO module provides data queuing for increased system level + * throughput + */ +#define UMAL_FIFOCFG0 (PKUNITY_UMAL_BASE + 0x0048) +#define UMAL_FIFOCFG1 (PKUNITY_UMAL_BASE + 0x004c) +#define UMAL_FIFOCFG2 (PKUNITY_UMAL_BASE + 0x0050) +#define UMAL_FIFOCFG3 (PKUNITY_UMAL_BASE + 0x0054) +#define UMAL_FIFOCFG4 (PKUNITY_UMAL_BASE + 0x0058) +#define UMAL_FIFOCFG5 (PKUNITY_UMAL_BASE + 0x005c) +#define UMAL_FIFORAM0 (PKUNITY_UMAL_BASE + 0x0060) +#define UMAL_FIFORAM1 (PKUNITY_UMAL_BASE + 0x0064) +#define UMAL_FIFORAM2 (PKUNITY_UMAL_BASE + 0x0068) +#define UMAL_FIFORAM3 (PKUNITY_UMAL_BASE + 0x006c) +#define UMAL_FIFORAM4 (PKUNITY_UMAL_BASE + 0x0070) +#define UMAL_FIFORAM5 (PKUNITY_UMAL_BASE + 0x0074) +#define UMAL_FIFORAM6 (PKUNITY_UMAL_BASE + 0x0078) +#define UMAL_FIFORAM7 (PKUNITY_UMAL_BASE + 0x007c) + +/* MAHBE MODUEL OF UMAL */ +/* UMAL's MAHBE module interfaces to the host system through 32-bit AHB Master + * and Slave ports.Registers within the M-AHBE provide Control and Status + * information concerning these transfers. + */ +/* + * Transmit Control UMAL_DMATxCtrl + */ +#define UMAL_DMATxCtrl (PKUNITY_UMAL_BASE + 0x0180) +/* + * Pointer to TX Descripter UMAL_DMATxDescriptor + */ +#define UMAL_DMATxDescriptor (PKUNITY_UMAL_BASE + 0x0184) +/* + * Status of Tx Packet Transfers UMAL_DMATxStatus + */ +#define UMAL_DMATxStatus (PKUNITY_UMAL_BASE + 0x0188) +/* + * Receive Control UMAL_DMARxCtrl + */ +#define UMAL_DMARxCtrl (PKUNITY_UMAL_BASE + 0x018c) +/* + * Pointer to Rx Descriptor UMAL_DMARxDescriptor + */ +#define UMAL_DMARxDescriptor (PKUNITY_UMAL_BASE + 0x0190) +/* + * Status of Rx Packet Transfers UMAL_DMARxStatus + */ +#define UMAL_DMARxStatus (PKUNITY_UMAL_BASE + 0x0194) +/* + * Interrupt Mask UMAL_DMAIntrMask + */ +#define UMAL_DMAIntrMask (PKUNITY_UMAL_BASE + 0x0198) +/* + * Interrupts, read only UMAL_DMAInterrupt + */ +#define UMAL_DMAInterrupt (PKUNITY_UMAL_BASE + 0x019c) + +/* + * Commands for UMAL_CFG1 register + */ +#define UMAL_CFG1_TXENABLE FIELD(1, 1, 0) +#define UMAL_CFG1_RXENABLE FIELD(1, 1, 2) +#define UMAL_CFG1_TXFLOWCTL FIELD(1, 1, 4) +#define UMAL_CFG1_RXFLOWCTL FIELD(1, 1, 5) +#define UMAL_CFG1_CONFLPBK FIELD(1, 1, 8) +#define UMAL_CFG1_RESET FIELD(1, 1, 31) +#define UMAL_CFG1_CONFFLCTL (MAC_TX_FLOW_CTL | MAC_RX_FLOW_CTL) + +/* + * Commands for UMAL_CFG2 register + */ +#define UMAL_CFG2_FULLDUPLEX FIELD(1, 1, 0) +#define UMAL_CFG2_CRCENABLE FIELD(1, 1, 1) +#define UMAL_CFG2_PADCRC FIELD(1, 1, 2) +#define UMAL_CFG2_LENGTHCHECK FIELD(1, 1, 4) +#define UMAL_CFG2_MODEMASK FMASK(2, 8) +#define UMAL_CFG2_NIBBLEMODE FIELD(1, 2, 8) +#define UMAL_CFG2_BYTEMODE FIELD(2, 2, 8) +#define UMAL_CFG2_PREAMBLENMASK FMASK(4, 12) +#define UMAL_CFG2_DEFPREAMBLEN FIELD(7, 4, 12) +#define UMAL_CFG2_FD100 (UMAL_CFG2_DEFPREAMBLEN | UMAL_CFG2_NIBBLEMODE \ + | UMAL_CFG2_LENGTHCHECK | UMAL_CFG2_PADCRC \ + | UMAL_CFG2_CRCENABLE | UMAL_CFG2_FULLDUPLEX) +#define UMAL_CFG2_FD1000 (UMAL_CFG2_DEFPREAMBLEN | UMAL_CFG2_BYTEMODE \ + | UMAL_CFG2_LENGTHCHECK | UMAL_CFG2_PADCRC \ + | UMAL_CFG2_CRCENABLE | UMAL_CFG2_FULLDUPLEX) +#define UMAL_CFG2_HD100 (UMAL_CFG2_DEFPREAMBLEN | UMAL_CFG2_NIBBLEMODE \ + | UMAL_CFG2_LENGTHCHECK | UMAL_CFG2_PADCRC \ + | UMAL_CFG2_CRCENABLE) + +/* + * Command for UMAL_IFCTRL register + */ +#define UMAL_IFCTRL_RESET FIELD(1, 1, 31) + +/* + * Command for UMAL_MIICFG register + */ +#define UMAL_MIICFG_RESET FIELD(1, 1, 31) + +/* + * Command for UMAL_MIICMD register + */ +#define UMAL_MIICMD_READ FIELD(1, 1, 0) + +/* + * Command for UMAL_MIIIDCT register + */ +#define UMAL_MIIIDCT_BUSY FIELD(1, 1, 0) +#define UMAL_MIIIDCT_NOTVALID FIELD(1, 1, 2) + +/* + * Commands for DMATxCtrl regesters + */ +#define UMAL_DMA_Enable FIELD(1, 1, 0) + +/* + * Commands for DMARxCtrl regesters + */ +#define UMAL_DMAIntrMask_ENABLEHALFWORD FIELD(1, 1, 16) + +/* + * Command for DMARxStatus + */ +#define CLR_RX_BUS_ERR FIELD(1, 1, 3) +#define CLR_RX_OVERFLOW FIELD(1, 1, 2) +#define CLR_RX_PKT FIELD(1, 1, 0) + +/* + * Command for DMATxStatus + */ +#define CLR_TX_BUS_ERR FIELD(1, 1, 3) +#define CLR_TX_UNDERRUN FIELD(1, 1, 1) +#define CLR_TX_PKT FIELD(1, 1, 0) + +/* + * Commands for DMAIntrMask and DMAInterrupt register + */ +#define INT_RX_MASK FIELD(0xd, 4, 4) +#define INT_TX_MASK FIELD(0xb, 4, 0) + +#define INT_RX_BUS_ERR FIELD(1, 1, 7) +#define INT_RX_OVERFLOW FIELD(1, 1, 6) +#define INT_RX_PKT FIELD(1, 1, 4) +#define INT_TX_BUS_ERR FIELD(1, 1, 3) +#define INT_TX_UNDERRUN FIELD(1, 1, 1) +#define INT_TX_PKT FIELD(1, 1, 0) + +/* + * MARCOS of UMAL's descriptors + */ +#define UMAL_DESC_PACKETSIZE_EMPTY FIELD(1, 1, 31) +#define UMAL_DESC_PACKETSIZE_NONEMPTY FIELD(0, 1, 31) +#define UMAL_DESC_PACKETSIZE_SIZEMASK FMASK(12, 0) + diff --git a/arch/unicore32/include/mach/regs-unigfx.h b/arch/unicore32/include/mach/regs-unigfx.h new file mode 100644 index 000000000000..faf8b287fccf --- /dev/null +++ b/arch/unicore32/include/mach/regs-unigfx.h @@ -0,0 +1,200 @@ +/* + * PKUnity UNIGFX Registers + */ + +#define UDE_BASE (PKUNITY_UNIGFX_BASE + 0x1400) +#define UGE_BASE (PKUNITY_UNIGFX_BASE + 0x0000) + +/* + * command reg for UNIGFX DE + */ +/* + * control reg UDE_CFG + */ +#define UDE_CFG (UDE_BASE + 0x0000) +/* + * framebuffer start address reg UDE_FSA + */ +#define UDE_FSA (UDE_BASE + 0x0004) +/* + * line size reg UDE_LS + */ +#define UDE_LS (UDE_BASE + 0x0008) +/* + * pitch size reg UDE_PS + */ +#define UDE_PS (UDE_BASE + 0x000C) +/* + * horizontal active time reg UDE_HAT + */ +#define UDE_HAT (UDE_BASE + 0x0010) +/* + * horizontal blank time reg UDE_HBT + */ +#define UDE_HBT (UDE_BASE + 0x0014) +/* + * horizontal sync time reg UDE_HST + */ +#define UDE_HST (UDE_BASE + 0x0018) +/* + * vertival active time reg UDE_VAT + */ +#define UDE_VAT (UDE_BASE + 0x001C) +/* + * vertival blank time reg UDE_VBT + */ +#define UDE_VBT (UDE_BASE + 0x0020) +/* + * vertival sync time reg UDE_VST + */ +#define UDE_VST (UDE_BASE + 0x0024) +/* + * cursor position UDE_CXY + */ +#define UDE_CXY (UDE_BASE + 0x0028) +/* + * cursor front color UDE_CC0 + */ +#define UDE_CC0 (UDE_BASE + 0x002C) +/* + * cursor background color UDE_CC1 + */ +#define UDE_CC1 (UDE_BASE + 0x0030) +/* + * video position UDE_VXY + */ +#define UDE_VXY (UDE_BASE + 0x0034) +/* + * video start address reg UDE_VSA + */ +#define UDE_VSA (UDE_BASE + 0x0040) +/* + * video size reg UDE_VS + */ +#define UDE_VS (UDE_BASE + 0x004C) + +/* + * command reg for UNIGFX GE + */ +/* + * src xy reg UGE_SRCXY + */ +#define UGE_SRCXY (UGE_BASE + 0x0000) +/* + * dst xy reg UGE_DSTXY + */ +#define UGE_DSTXY (UGE_BASE + 0x0004) +/* + * pitch reg UGE_PITCH + */ +#define UGE_PITCH (UGE_BASE + 0x0008) +/* + * src start reg UGE_SRCSTART + */ +#define UGE_SRCSTART (UGE_BASE + 0x000C) +/* + * dst start reg UGE_DSTSTART + */ +#define UGE_DSTSTART (UGE_BASE + 0x0010) +/* + * width height reg UGE_WIDHEIGHT + */ +#define UGE_WIDHEIGHT (UGE_BASE + 0x0014) +/* + * rop alpah reg UGE_ROPALPHA + */ +#define UGE_ROPALPHA (UGE_BASE + 0x0018) +/* + * front color UGE_FCOLOR + */ +#define UGE_FCOLOR (UGE_BASE + 0x001C) +/* + * background color UGE_BCOLOR + */ +#define UGE_BCOLOR (UGE_BASE + 0x0020) +/* + * src color key for high value UGE_SCH + */ +#define UGE_SCH (UGE_BASE + 0x0024) +/* + * dst color key for high value UGE_DCH + */ +#define UGE_DCH (UGE_BASE + 0x0028) +/* + * src color key for low value UGE_SCL + */ +#define UGE_SCL (UGE_BASE + 0x002C) +/* + * dst color key for low value UGE_DCL + */ +#define UGE_DCL (UGE_BASE + 0x0030) +/* + * clip 0 reg UGE_CLIP0 + */ +#define UGE_CLIP0 (UGE_BASE + 0x0034) +/* + * clip 1 reg UGE_CLIP1 + */ +#define UGE_CLIP1 (UGE_BASE + 0x0038) +/* + * command reg UGE_COMMAND + */ +#define UGE_COMMAND (UGE_BASE + 0x003C) +/* + * pattern 0 UGE_P0 + */ +#define UGE_P0 (UGE_BASE + 0x0040) +#define UGE_P1 (UGE_BASE + 0x0044) +#define UGE_P2 (UGE_BASE + 0x0048) +#define UGE_P3 (UGE_BASE + 0x004C) +#define UGE_P4 (UGE_BASE + 0x0050) +#define UGE_P5 (UGE_BASE + 0x0054) +#define UGE_P6 (UGE_BASE + 0x0058) +#define UGE_P7 (UGE_BASE + 0x005C) +#define UGE_P8 (UGE_BASE + 0x0060) +#define UGE_P9 (UGE_BASE + 0x0064) +#define UGE_P10 (UGE_BASE + 0x0068) +#define UGE_P11 (UGE_BASE + 0x006C) +#define UGE_P12 (UGE_BASE + 0x0070) +#define UGE_P13 (UGE_BASE + 0x0074) +#define UGE_P14 (UGE_BASE + 0x0078) +#define UGE_P15 (UGE_BASE + 0x007C) +#define UGE_P16 (UGE_BASE + 0x0080) +#define UGE_P17 (UGE_BASE + 0x0084) +#define UGE_P18 (UGE_BASE + 0x0088) +#define UGE_P19 (UGE_BASE + 0x008C) +#define UGE_P20 (UGE_BASE + 0x0090) +#define UGE_P21 (UGE_BASE + 0x0094) +#define UGE_P22 (UGE_BASE + 0x0098) +#define UGE_P23 (UGE_BASE + 0x009C) +#define UGE_P24 (UGE_BASE + 0x00A0) +#define UGE_P25 (UGE_BASE + 0x00A4) +#define UGE_P26 (UGE_BASE + 0x00A8) +#define UGE_P27 (UGE_BASE + 0x00AC) +#define UGE_P28 (UGE_BASE + 0x00B0) +#define UGE_P29 (UGE_BASE + 0x00B4) +#define UGE_P30 (UGE_BASE + 0x00B8) +#define UGE_P31 (UGE_BASE + 0x00BC) + +#define UDE_CFG_DST_MASK FMASK(2, 8) +#define UDE_CFG_DST8 FIELD(0x0, 2, 8) +#define UDE_CFG_DST16 FIELD(0x1, 2, 8) +#define UDE_CFG_DST24 FIELD(0x2, 2, 8) +#define UDE_CFG_DST32 FIELD(0x3, 2, 8) + +/* + * GDEN enable UDE_CFG_GDEN_ENABLE + */ +#define UDE_CFG_GDEN_ENABLE FIELD(1, 1, 3) +/* + * VDEN enable UDE_CFG_VDEN_ENABLE + */ +#define UDE_CFG_VDEN_ENABLE FIELD(1, 1, 4) +/* + * CDEN enable UDE_CFG_CDEN_ENABLE + */ +#define UDE_CFG_CDEN_ENABLE FIELD(1, 1, 5) +/* + * TIMEUP enable UDE_CFG_TIMEUP_ENABLE + */ +#define UDE_CFG_TIMEUP_ENABLE FIELD(1, 1, 6) diff --git a/arch/unicore32/include/mach/uncompress.h b/arch/unicore32/include/mach/uncompress.h new file mode 100644 index 000000000000..142d3e7958a9 --- /dev/null +++ b/arch/unicore32/include/mach/uncompress.h @@ -0,0 +1,34 @@ +/* + * linux/arch/unicore32/include/mach/uncompress.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_PUV3_UNCOMPRESS_H__ +#define __MACH_PUV3_UNCOMPRESS_H__ + +#include "hardware.h" +#include "ocd.h" + +extern char input_data[]; +extern char input_data_end[]; + +static void arch_decomp_puts(const char *ptr) +{ + char c; + + while ((c = *ptr++) != '\0') { + if (c == '\n') + putc('\r'); + putc(c); + } +} +#define ARCH_HAVE_DECOMP_PUTS + +#endif /* __MACH_PUV3_UNCOMPRESS_H__ */ diff --git a/arch/unicore32/kernel/Makefile b/arch/unicore32/kernel/Makefile new file mode 100644 index 000000000000..ec23a2fb2f50 --- /dev/null +++ b/arch/unicore32/kernel/Makefile @@ -0,0 +1,33 @@ +# +# Makefile for the linux kernel. +# + +# Object file lists. +obj-y := dma.o elf.o entry.o process.o ptrace.o +obj-y += setup.o signal.o sys.o stacktrace.o traps.o + +obj-$(CONFIG_MODULES) += ksyms.o module.o +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + +obj-$(CONFIG_CPU_FREQ) += cpu-ucv2.o +obj-$(CONFIG_UNICORE_FPU_F64) += fpu-ucf64.o + +# obj-y for architecture PKUnity v3 +obj-$(CONFIG_ARCH_PUV3) += clock.o irq.o time.o + +obj-$(CONFIG_PUV3_GPIO) += gpio.o +obj-$(CONFIG_PUV3_RTC) += rtc.o +obj-$(CONFIG_PUV3_PWM) += pwm.o +obj-$(CONFIG_PUV3_PM) += pm.o sleep.o +obj-$(CONFIG_HIBERNATION) += hibernate.o hibernate_asm.o + +obj-$(CONFIG_PCI) += pci.o + +# obj-y for specific machines +obj-$(CONFIG_ARCH_PUV3) += puv3-core.o +obj-$(CONFIG_PUV3_NB0916) += puv3-nb0916.o + +head-y := head.o +obj-$(CONFIG_DEBUG_LL) += debug.o + +extra-y := $(head-y) init_task.o vmlinux.lds diff --git a/arch/unicore32/kernel/asm-offsets.c b/arch/unicore32/kernel/asm-offsets.c new file mode 100644 index 000000000000..ffcbe7536ca7 --- /dev/null +++ b/arch/unicore32/kernel/asm-offsets.c @@ -0,0 +1,112 @@ +/* + * linux/arch/unicore32/kernel/asm-offsets.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * Generate definitions needed by assembly language modules. + * This code generates raw asm output which is post-processed to extract + * and format the required data. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/sched.h> +#include <linux/mm.h> +#include <linux/dma-mapping.h> +#include <linux/kbuild.h> +#include <linux/suspend.h> +#include <linux/thread_info.h> +#include <asm/memory.h> +#include <asm/suspend.h> + +/* + * GCC 3.0, 3.1: general bad code generation. + * GCC 3.2.0: incorrect function argument offset calculation. + * GCC 3.2.x: miscompiles NEW_AUX_ENT in fs/binfmt_elf.c + * (http://gcc.gnu.org/PR8896) and incorrect structure + * initialisation in fs/jffs2/erase.c + */ +#if (__GNUC__ < 4) +#error Your compiler should upgrade to uc4 +#error Known good compilers: 4.2.2 +#endif + +int main(void) +{ + DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm)); + BLANK(); + DEFINE(TI_FLAGS, offsetof(struct thread_info, flags)); + DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count)); + DEFINE(TI_ADDR_LIMIT, offsetof(struct thread_info, addr_limit)); + DEFINE(TI_TASK, offsetof(struct thread_info, task)); + DEFINE(TI_EXEC_DOMAIN, offsetof(struct thread_info, exec_domain)); + DEFINE(TI_CPU, offsetof(struct thread_info, cpu)); + DEFINE(TI_CPU_SAVE, offsetof(struct thread_info, cpu_context)); + DEFINE(TI_USED_CP, offsetof(struct thread_info, used_cp)); +#ifdef CONFIG_UNICORE_FPU_F64 + DEFINE(TI_FPSTATE, offsetof(struct thread_info, fpstate)); +#endif + BLANK(); + DEFINE(S_R0, offsetof(struct pt_regs, UCreg_00)); + DEFINE(S_R1, offsetof(struct pt_regs, UCreg_01)); + DEFINE(S_R2, offsetof(struct pt_regs, UCreg_02)); + DEFINE(S_R3, offsetof(struct pt_regs, UCreg_03)); + DEFINE(S_R4, offsetof(struct pt_regs, UCreg_04)); + DEFINE(S_R5, offsetof(struct pt_regs, UCreg_05)); + DEFINE(S_R6, offsetof(struct pt_regs, UCreg_06)); + DEFINE(S_R7, offsetof(struct pt_regs, UCreg_07)); + DEFINE(S_R8, offsetof(struct pt_regs, UCreg_08)); + DEFINE(S_R9, offsetof(struct pt_regs, UCreg_09)); + DEFINE(S_R10, offsetof(struct pt_regs, UCreg_10)); + DEFINE(S_R11, offsetof(struct pt_regs, UCreg_11)); + DEFINE(S_R12, offsetof(struct pt_regs, UCreg_12)); + DEFINE(S_R13, offsetof(struct pt_regs, UCreg_13)); + DEFINE(S_R14, offsetof(struct pt_regs, UCreg_14)); + DEFINE(S_R15, offsetof(struct pt_regs, UCreg_15)); + DEFINE(S_R16, offsetof(struct pt_regs, UCreg_16)); + DEFINE(S_R17, offsetof(struct pt_regs, UCreg_17)); + DEFINE(S_R18, offsetof(struct pt_regs, UCreg_18)); + DEFINE(S_R19, offsetof(struct pt_regs, UCreg_19)); + DEFINE(S_R20, offsetof(struct pt_regs, UCreg_20)); + DEFINE(S_R21, offsetof(struct pt_regs, UCreg_21)); + DEFINE(S_R22, offsetof(struct pt_regs, UCreg_22)); + DEFINE(S_R23, offsetof(struct pt_regs, UCreg_23)); + DEFINE(S_R24, offsetof(struct pt_regs, UCreg_24)); + DEFINE(S_R25, offsetof(struct pt_regs, UCreg_25)); + DEFINE(S_R26, offsetof(struct pt_regs, UCreg_26)); + DEFINE(S_FP, offsetof(struct pt_regs, UCreg_fp)); + DEFINE(S_IP, offsetof(struct pt_regs, UCreg_ip)); + DEFINE(S_SP, offsetof(struct pt_regs, UCreg_sp)); + DEFINE(S_LR, offsetof(struct pt_regs, UCreg_lr)); + DEFINE(S_PC, offsetof(struct pt_regs, UCreg_pc)); + DEFINE(S_PSR, offsetof(struct pt_regs, UCreg_asr)); + DEFINE(S_OLD_R0, offsetof(struct pt_regs, UCreg_ORIG_00)); + DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs)); + BLANK(); + DEFINE(VMA_VM_MM, offsetof(struct vm_area_struct, vm_mm)); + DEFINE(VMA_VM_FLAGS, offsetof(struct vm_area_struct, vm_flags)); + BLANK(); + DEFINE(VM_EXEC, VM_EXEC); + BLANK(); + DEFINE(PAGE_SZ, PAGE_SIZE); + BLANK(); + DEFINE(SYS_ERROR0, 0x9f0000); + BLANK(); + DEFINE(PBE_ADDRESS, offsetof(struct pbe, address)); + DEFINE(PBE_ORIN_ADDRESS, offsetof(struct pbe, orig_address)); + DEFINE(PBE_NEXT, offsetof(struct pbe, next)); + DEFINE(SWSUSP_CPU, offsetof(struct swsusp_arch_regs, \ + cpu_context)); +#ifdef CONFIG_UNICORE_FPU_F64 + DEFINE(SWSUSP_FPSTATE, offsetof(struct swsusp_arch_regs, \ + fpstate)); +#endif + BLANK(); + DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL); + DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE); + DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE); + return 0; +} diff --git a/arch/unicore32/kernel/clock.c b/arch/unicore32/kernel/clock.c new file mode 100644 index 000000000000..18d4563e6fa5 --- /dev/null +++ b/arch/unicore32/kernel/clock.c @@ -0,0 +1,390 @@ +/* + * linux/arch/unicore32/kernel/clock.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn> + * Copyright (C) 2001-2010 Guan Xuetao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/device.h> +#include <linux/list.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/string.h> +#include <linux/clk.h> +#include <linux/mutex.h> +#include <linux/delay.h> +#include <linux/io.h> + +#include <mach/hardware.h> + +/* + * Very simple clock implementation + */ +struct clk { + struct list_head node; + unsigned long rate; + const char *name; +}; + +static struct clk clk_ost_clk = { + .name = "OST_CLK", + .rate = CLOCK_TICK_RATE, +}; + +static struct clk clk_mclk_clk = { + .name = "MAIN_CLK", +}; + +static struct clk clk_bclk32_clk = { + .name = "BUS32_CLK", +}; + +static struct clk clk_ddr_clk = { + .name = "DDR_CLK", +}; + +static struct clk clk_vga_clk = { + .name = "VGA_CLK", +}; + +static LIST_HEAD(clocks); +static DEFINE_MUTEX(clocks_mutex); + +struct clk *clk_get(struct device *dev, const char *id) +{ + struct clk *p, *clk = ERR_PTR(-ENOENT); + + mutex_lock(&clocks_mutex); + list_for_each_entry(p, &clocks, node) { + if (strcmp(id, p->name) == 0) { + clk = p; + break; + } + } + mutex_unlock(&clocks_mutex); + + return clk; +} +EXPORT_SYMBOL(clk_get); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return clk->rate; +} +EXPORT_SYMBOL(clk_get_rate); + +struct { + unsigned long rate; + unsigned long cfg; + unsigned long div; +} vga_clk_table[] = { + {.rate = 25175000, .cfg = 0x00002001, .div = 0x9}, + {.rate = 31500000, .cfg = 0x00002001, .div = 0x7}, + {.rate = 40000000, .cfg = 0x00003801, .div = 0x9}, + {.rate = 49500000, .cfg = 0x00003801, .div = 0x7}, + {.rate = 65000000, .cfg = 0x00002c01, .div = 0x4}, + {.rate = 78750000, .cfg = 0x00002400, .div = 0x7}, + {.rate = 108000000, .cfg = 0x00002c01, .div = 0x2}, + {.rate = 106500000, .cfg = 0x00003c01, .div = 0x3}, + {.rate = 50650000, .cfg = 0x00106400, .div = 0x9}, + {.rate = 61500000, .cfg = 0x00106400, .div = 0xa}, + {.rate = 85500000, .cfg = 0x00002800, .div = 0x6}, +}; + +struct { + unsigned long mrate; + unsigned long prate; +} mclk_clk_table[] = { + {.mrate = 500000000, .prate = 0x00109801}, + {.mrate = 525000000, .prate = 0x00104C00}, + {.mrate = 550000000, .prate = 0x00105000}, + {.mrate = 575000000, .prate = 0x00105400}, + {.mrate = 600000000, .prate = 0x00105800}, + {.mrate = 625000000, .prate = 0x00105C00}, + {.mrate = 650000000, .prate = 0x00106000}, + {.mrate = 675000000, .prate = 0x00106400}, + {.mrate = 700000000, .prate = 0x00106800}, + {.mrate = 725000000, .prate = 0x00106C00}, + {.mrate = 750000000, .prate = 0x00107000}, + {.mrate = 775000000, .prate = 0x00107400}, + {.mrate = 800000000, .prate = 0x00107800}, +}; + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + if (clk == &clk_vga_clk) { + unsigned long pll_vgacfg, pll_vgadiv; + int ret, i; + + /* lookup vga_clk_table */ + ret = -EINVAL; + for (i = 0; i < ARRAY_SIZE(vga_clk_table); i++) { + if (rate == vga_clk_table[i].rate) { + pll_vgacfg = vga_clk_table[i].cfg; + pll_vgadiv = vga_clk_table[i].div; + ret = 0; + break; + } + } + + if (ret) + return ret; + + if (readl(PM_PLLVGACFG) == pll_vgacfg) + return 0; + + /* set pll vga cfg reg. */ + writel(pll_vgacfg, PM_PLLVGACFG); + + writel(PM_PMCR_CFBVGA, PM_PMCR); + while ((readl(PM_PLLDFCDONE) & PM_PLLDFCDONE_VGADFC) + != PM_PLLDFCDONE_VGADFC) + udelay(100); /* about 1ms */ + + /* set div cfg reg. */ + writel(readl(PM_PCGR) | PM_PCGR_VGACLK, PM_PCGR); + + writel((readl(PM_DIVCFG) & ~PM_DIVCFG_VGACLK_MASK) + | PM_DIVCFG_VGACLK(pll_vgadiv), PM_DIVCFG); + + writel(readl(PM_SWRESET) | PM_SWRESET_VGADIV, PM_SWRESET); + while ((readl(PM_SWRESET) & PM_SWRESET_VGADIV) + == PM_SWRESET_VGADIV) + udelay(100); /* 65536 bclk32, about 320us */ + + writel(readl(PM_PCGR) & ~PM_PCGR_VGACLK, PM_PCGR); + } +#ifdef CONFIG_CPU_FREQ + if (clk == &clk_mclk_clk) { + u32 pll_rate, divstatus = PM_DIVSTATUS; + int ret, i; + + /* lookup mclk_clk_table */ + ret = -EINVAL; + for (i = 0; i < ARRAY_SIZE(mclk_clk_table); i++) { + if (rate == mclk_clk_table[i].mrate) { + pll_rate = mclk_clk_table[i].prate; + clk_mclk_clk.rate = mclk_clk_table[i].mrate; + ret = 0; + break; + } + } + + if (ret) + return ret; + + if (clk_mclk_clk.rate) + clk_bclk32_clk.rate = clk_mclk_clk.rate + / (((divstatus & 0x0000f000) >> 12) + 1); + + /* set pll sys cfg reg. */ + PM_PLLSYSCFG = pll_rate; + + PM_PMCR = PM_PMCR_CFBSYS; + while ((PM_PLLDFCDONE & PM_PLLDFCDONE_SYSDFC) + != PM_PLLDFCDONE_SYSDFC) + udelay(100); + /* about 1ms */ + } +#endif + return 0; +} +EXPORT_SYMBOL(clk_set_rate); + +int clk_register(struct clk *clk) +{ + mutex_lock(&clocks_mutex); + list_add(&clk->node, &clocks); + mutex_unlock(&clocks_mutex); + printk(KERN_DEFAULT "PKUnity PM: %s %lu.%02luM\n", clk->name, + (clk->rate)/1000000, (clk->rate)/10000 % 100); + return 0; +} +EXPORT_SYMBOL(clk_register); + +void clk_unregister(struct clk *clk) +{ + mutex_lock(&clocks_mutex); + list_del(&clk->node); + mutex_unlock(&clocks_mutex); +} +EXPORT_SYMBOL(clk_unregister); + +struct { + unsigned long prate; + unsigned long rate; +} pllrate_table[] = { + {.prate = 0x00002001, .rate = 250000000}, + {.prate = 0x00104801, .rate = 250000000}, + {.prate = 0x00104C01, .rate = 262500000}, + {.prate = 0x00002401, .rate = 275000000}, + {.prate = 0x00105001, .rate = 275000000}, + {.prate = 0x00105401, .rate = 287500000}, + {.prate = 0x00002801, .rate = 300000000}, + {.prate = 0x00105801, .rate = 300000000}, + {.prate = 0x00105C01, .rate = 312500000}, + {.prate = 0x00002C01, .rate = 325000000}, + {.prate = 0x00106001, .rate = 325000000}, + {.prate = 0x00106401, .rate = 337500000}, + {.prate = 0x00003001, .rate = 350000000}, + {.prate = 0x00106801, .rate = 350000000}, + {.prate = 0x00106C01, .rate = 362500000}, + {.prate = 0x00003401, .rate = 375000000}, + {.prate = 0x00107001, .rate = 375000000}, + {.prate = 0x00107401, .rate = 387500000}, + {.prate = 0x00003801, .rate = 400000000}, + {.prate = 0x00107801, .rate = 400000000}, + {.prate = 0x00107C01, .rate = 412500000}, + {.prate = 0x00003C01, .rate = 425000000}, + {.prate = 0x00108001, .rate = 425000000}, + {.prate = 0x00108401, .rate = 437500000}, + {.prate = 0x00004001, .rate = 450000000}, + {.prate = 0x00108801, .rate = 450000000}, + {.prate = 0x00108C01, .rate = 462500000}, + {.prate = 0x00004401, .rate = 475000000}, + {.prate = 0x00109001, .rate = 475000000}, + {.prate = 0x00109401, .rate = 487500000}, + {.prate = 0x00004801, .rate = 500000000}, + {.prate = 0x00109801, .rate = 500000000}, + {.prate = 0x00104C00, .rate = 525000000}, + {.prate = 0x00002400, .rate = 550000000}, + {.prate = 0x00105000, .rate = 550000000}, + {.prate = 0x00105400, .rate = 575000000}, + {.prate = 0x00002800, .rate = 600000000}, + {.prate = 0x00105800, .rate = 600000000}, + {.prate = 0x00105C00, .rate = 625000000}, + {.prate = 0x00002C00, .rate = 650000000}, + {.prate = 0x00106000, .rate = 650000000}, + {.prate = 0x00106400, .rate = 675000000}, + {.prate = 0x00003000, .rate = 700000000}, + {.prate = 0x00106800, .rate = 700000000}, + {.prate = 0x00106C00, .rate = 725000000}, + {.prate = 0x00003400, .rate = 750000000}, + {.prate = 0x00107000, .rate = 750000000}, + {.prate = 0x00107400, .rate = 775000000}, + {.prate = 0x00003800, .rate = 800000000}, + {.prate = 0x00107800, .rate = 800000000}, + {.prate = 0x00107C00, .rate = 825000000}, + {.prate = 0x00003C00, .rate = 850000000}, + {.prate = 0x00108000, .rate = 850000000}, + {.prate = 0x00108400, .rate = 875000000}, + {.prate = 0x00004000, .rate = 900000000}, + {.prate = 0x00108800, .rate = 900000000}, + {.prate = 0x00108C00, .rate = 925000000}, + {.prate = 0x00004400, .rate = 950000000}, + {.prate = 0x00109000, .rate = 950000000}, + {.prate = 0x00109400, .rate = 975000000}, + {.prate = 0x00004800, .rate = 1000000000}, + {.prate = 0x00109800, .rate = 1000000000}, +}; + +struct { + unsigned long prate; + unsigned long drate; +} pddr_table[] = { + {.prate = 0x00100800, .drate = 44236800}, + {.prate = 0x00100C00, .drate = 66355200}, + {.prate = 0x00101000, .drate = 88473600}, + {.prate = 0x00101400, .drate = 110592000}, + {.prate = 0x00101800, .drate = 132710400}, + {.prate = 0x00101C01, .drate = 154828800}, + {.prate = 0x00102001, .drate = 176947200}, + {.prate = 0x00102401, .drate = 199065600}, + {.prate = 0x00102801, .drate = 221184000}, + {.prate = 0x00102C01, .drate = 243302400}, + {.prate = 0x00103001, .drate = 265420800}, + {.prate = 0x00103401, .drate = 287539200}, + {.prate = 0x00103801, .drate = 309657600}, + {.prate = 0x00103C01, .drate = 331776000}, + {.prate = 0x00104001, .drate = 353894400}, +}; + +static int __init clk_init(void) +{ +#ifdef CONFIG_PUV3_PM + u32 pllrate, divstatus = readl(PM_DIVSTATUS); + u32 pcgr_val = readl(PM_PCGR); + int i; + + pcgr_val |= PM_PCGR_BCLKMME | PM_PCGR_BCLKH264E | PM_PCGR_BCLKH264D + | PM_PCGR_HECLK | PM_PCGR_HDCLK; + writel(pcgr_val, PM_PCGR); + + pllrate = readl(PM_PLLSYSSTATUS); + + /* lookup pmclk_table */ + clk_mclk_clk.rate = 0; + for (i = 0; i < ARRAY_SIZE(pllrate_table); i++) { + if (pllrate == pllrate_table[i].prate) { + clk_mclk_clk.rate = pllrate_table[i].rate; + break; + } + } + + if (clk_mclk_clk.rate) + clk_bclk32_clk.rate = clk_mclk_clk.rate / + (((divstatus & 0x0000f000) >> 12) + 1); + + pllrate = readl(PM_PLLDDRSTATUS); + + /* lookup pddr_table */ + clk_ddr_clk.rate = 0; + for (i = 0; i < ARRAY_SIZE(pddr_table); i++) { + if (pllrate == pddr_table[i].prate) { + clk_ddr_clk.rate = pddr_table[i].drate; + break; + } + } + + pllrate = readl(PM_PLLVGASTATUS); + + /* lookup pvga_table */ + clk_vga_clk.rate = 0; + for (i = 0; i < ARRAY_SIZE(pllrate_table); i++) { + if (pllrate == pllrate_table[i].prate) { + clk_vga_clk.rate = pllrate_table[i].rate; + break; + } + } + + if (clk_vga_clk.rate) + clk_vga_clk.rate = clk_vga_clk.rate / + (((divstatus & 0x00f00000) >> 20) + 1); + + clk_register(&clk_vga_clk); +#endif +#ifdef CONFIG_ARCH_FPGA + clk_ddr_clk.rate = 33000000; + clk_mclk_clk.rate = 33000000; + clk_bclk32_clk.rate = 33000000; +#endif + clk_register(&clk_ddr_clk); + clk_register(&clk_mclk_clk); + clk_register(&clk_bclk32_clk); + clk_register(&clk_ost_clk); + return 0; +} +core_initcall(clk_init); diff --git a/arch/unicore32/kernel/cpu-ucv2.c b/arch/unicore32/kernel/cpu-ucv2.c new file mode 100644 index 000000000000..4a99f62584c7 --- /dev/null +++ b/arch/unicore32/kernel/cpu-ucv2.c @@ -0,0 +1,93 @@ +/* + * linux/arch/unicore32/kernel/cpu-ucv2.c: clock scaling for the UniCore-II + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn> + * Copyright (C) 2001-2010 Guan Xuetao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/cpufreq.h> + +#include <mach/hardware.h> + +static struct cpufreq_driver ucv2_driver; + +/* make sure that only the "userspace" governor is run + * -- anything else wouldn't make sense on this platform, anyway. + */ +int ucv2_verify_speed(struct cpufreq_policy *policy) +{ + if (policy->cpu) + return -EINVAL; + + cpufreq_verify_within_limits(policy, + policy->cpuinfo.min_freq, policy->cpuinfo.max_freq); + + return 0; +} + +static unsigned int ucv2_getspeed(unsigned int cpu) +{ + struct clk *mclk = clk_get(NULL, "MAIN_CLK"); + + if (cpu) + return 0; + return clk_get_rate(mclk)/1000; +} + +static int ucv2_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + unsigned int cur = ucv2_getspeed(0); + struct cpufreq_freqs freqs; + struct clk *mclk = clk_get(NULL, "MAIN_CLK"); + + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + + if (!clk_set_rate(mclk, target_freq * 1000)) { + freqs.old = cur; + freqs.new = target_freq; + freqs.cpu = 0; + } + + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + + return 0; +} + +static int __init ucv2_cpu_init(struct cpufreq_policy *policy) +{ + if (policy->cpu != 0) + return -EINVAL; + policy->cur = ucv2_getspeed(0); + policy->min = policy->cpuinfo.min_freq = 250000; + policy->max = policy->cpuinfo.max_freq = 1000000; + policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; + return 0; +} + +static struct cpufreq_driver ucv2_driver = { + .flags = CPUFREQ_STICKY, + .verify = ucv2_verify_speed, + .target = ucv2_target, + .get = ucv2_getspeed, + .init = ucv2_cpu_init, + .name = "UniCore-II", +}; + +static int __init ucv2_cpufreq_init(void) +{ + return cpufreq_register_driver(&ucv2_driver); +} + +arch_initcall(ucv2_cpufreq_init); diff --git a/arch/unicore32/kernel/debug-macro.S b/arch/unicore32/kernel/debug-macro.S new file mode 100644 index 000000000000..2711d6d87d8e --- /dev/null +++ b/arch/unicore32/kernel/debug-macro.S @@ -0,0 +1,89 @@ +/* + * linux/arch/unicore32/kernel/debug-macro.S + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Debugging macro include header + */ +#include <generated/asm-offsets.h> +#include <mach/hardware.h> + + .macro put_word_ocd, rd, rx=r16 +1001: movc \rx, p1.c0, #0 + cand.a \rx, #2 + bne 1001b + movc p1.c1, \rd, #1 + .endm + +#ifdef CONFIG_DEBUG_OCD + /* debug using UniCore On-Chip-Debugger */ + .macro addruart, rx + .endm + + .macro senduart, rd, rx + put_word_ocd \rd, \rx + .endm + + .macro busyuart, rd, rx + .endm + + .macro waituart, rd, rx + .endm +#else +#define UART_CLK_DEFAULT 3686400 * 20 + /* Uartclk = MCLK/ 2, The MCLK on my board is 3686400 * 40 */ +#define BAUD_RATE_DEFAULT 115200 + /* The baud rate of the serial port */ + +#define UART_DIVISOR_DEFAULT (UART_CLK_DEFAULT \ + / (16 * BAUD_RATE_DEFAULT) - 1) + + .macro addruart,rx + mrc p0, #0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + moveq \rx, #0xee000000 @ physical base address + movne \rx, #0x6e000000 @ virtual address + + @ We probe for the active serial port here + @ However, now we assume UART0 is active: epip4d + @ We assume r1 and r2 can be clobbered. + + movl r2, #UART_DIVISOR_DEFAULT + mov r1, #0x80 + str r1, [\rx, #UART_LCR_OFFSET] + and r1, r2, #0xff00 + mov r1, r1, lsr #8 + str r1, [\rx, #UART_DLH_OFFSET] + and r1, r2, #0xff + str r1, [\rx, #UART_DLL_OFFSET] + mov r1, #0x7 + str r1, [\rx, #UART_FCR_OFFSET] + mov r1, #0x3 + str r1, [\rx, #UART_LCR_OFFSET] + mov r1, #0x0 + str r1, [\rx, #UART_IER_OFFSET] + .endm + + .macro senduart,rd,rx + str \rd, [\rx, #UART_THR_OFFSET] + .endm + + .macro waituart,rd,rx +1001: ldr \rd, [\rx, #UART_LSR_OFFSET] + tst \rd, #UART_LSR_THRE + beq 1001b + .endm + + .macro busyuart,rd,rx +1001: ldr \rd, [\rx, #UART_LSR_OFFSET] + tst \rd, #UART_LSR_TEMT + bne 1001b + .endm +#endif + diff --git a/arch/unicore32/kernel/debug.S b/arch/unicore32/kernel/debug.S new file mode 100644 index 000000000000..029fd12f6ab0 --- /dev/null +++ b/arch/unicore32/kernel/debug.S @@ -0,0 +1,85 @@ +/* + * linux/arch/unicore32/kernel/debug.S + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * 32-bit debugging code + */ +#include <linux/linkage.h> +#include <asm/assembler.h> + + .text + +/* + * Some debugging routines (useful if you've got MM problems and + * printk isn't working). For DEBUGGING ONLY!!! Do not leave + * references to these in a production kernel! + */ +#include "debug-macro.S" + +/* + * Useful debugging routines + */ +ENTRY(printhex8) + mov r1, #8 + b printhex +ENDPROC(printhex8) + +ENTRY(printhex4) + mov r1, #4 + b printhex +ENDPROC(printhex4) + +ENTRY(printhex2) + mov r1, #2 +printhex: adr r2, hexbuf + add r3, r2, r1 + mov r1, #0 + stb r1, [r3] +1: and r1, r0, #15 + mov r0, r0 >> #4 + csub.a r1, #10 + beg 2f + add r1, r1, #'0' - 'a' + 10 +2: add r1, r1, #'a' - 10 + stb.w r1, [r3+], #-1 + cxor.a r3, r2 + bne 1b + mov r0, r2 + b printascii +ENDPROC(printhex2) + + .ltorg + +ENTRY(printascii) + addruart r3 + b 2f +1: waituart r2, r3 + senduart r1, r3 + busyuart r2, r3 + cxor.a r1, #'\n' + cmoveq r1, #'\r' + beq 1b +2: cxor.a r0, #0 + beq 3f + ldb.w r1, [r0]+, #1 + cxor.a r1, #0 + bne 1b +3: mov pc, lr +ENDPROC(printascii) + +ENTRY(printch) + addruart r3 + mov r1, r0 + mov r0, #0 + b 1b +ENDPROC(printch) + +hexbuf: .space 16 + diff --git a/arch/unicore32/kernel/dma.c b/arch/unicore32/kernel/dma.c new file mode 100644 index 000000000000..ae441bc3122c --- /dev/null +++ b/arch/unicore32/kernel/dma.c @@ -0,0 +1,183 @@ +/* + * linux/arch/unicore32/kernel/dma.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn> + * Copyright (C) 2001-2010 Guan Xuetao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/interrupt.h> +#include <linux/errno.h> +#include <linux/io.h> + +#include <asm/system.h> +#include <asm/irq.h> +#include <mach/hardware.h> +#include <mach/dma.h> + +struct dma_channel { + char *name; + puv3_dma_prio prio; + void (*irq_handler)(int, void *); + void (*err_handler)(int, void *); + void *data; +}; + +static struct dma_channel dma_channels[MAX_DMA_CHANNELS]; + +int puv3_request_dma(char *name, puv3_dma_prio prio, + void (*irq_handler)(int, void *), + void (*err_handler)(int, void *), + void *data) +{ + unsigned long flags; + int i, found = 0; + + /* basic sanity checks */ + if (!name) + return -EINVAL; + + local_irq_save(flags); + + do { + /* try grabbing a DMA channel with the requested priority */ + for (i = 0; i < MAX_DMA_CHANNELS; i++) { + if ((dma_channels[i].prio == prio) && + !dma_channels[i].name) { + found = 1; + break; + } + } + /* if requested prio group is full, try a hier priority */ + } while (!found && prio--); + + if (found) { + dma_channels[i].name = name; + dma_channels[i].irq_handler = irq_handler; + dma_channels[i].err_handler = err_handler; + dma_channels[i].data = data; + } else { + printk(KERN_WARNING "No more available DMA channels for %s\n", + name); + i = -ENODEV; + } + + local_irq_restore(flags); + return i; +} +EXPORT_SYMBOL(puv3_request_dma); + +void puv3_free_dma(int dma_ch) +{ + unsigned long flags; + + if (!dma_channels[dma_ch].name) { + printk(KERN_CRIT + "%s: trying to free channel %d which is already freed\n", + __func__, dma_ch); + return; + } + + local_irq_save(flags); + dma_channels[dma_ch].name = NULL; + dma_channels[dma_ch].err_handler = NULL; + local_irq_restore(flags); +} +EXPORT_SYMBOL(puv3_free_dma); + +static irqreturn_t dma_irq_handler(int irq, void *dev_id) +{ + int i, dint; + + dint = readl(DMAC_ITCSR); + for (i = 0; i < MAX_DMA_CHANNELS; i++) { + if (dint & DMAC_CHANNEL(i)) { + struct dma_channel *channel = &dma_channels[i]; + + /* Clear TC interrupt of channel i */ + writel(DMAC_CHANNEL(i), DMAC_ITCCR); + writel(0, DMAC_ITCCR); + + if (channel->name && channel->irq_handler) { + channel->irq_handler(i, channel->data); + } else { + /* + * IRQ for an unregistered DMA channel: + * let's clear the interrupts and disable it. + */ + printk(KERN_WARNING "spurious IRQ for" + " DMA channel %d\n", i); + } + } + } + return IRQ_HANDLED; +} + +static irqreturn_t dma_err_handler(int irq, void *dev_id) +{ + int i, dint; + + dint = readl(DMAC_IESR); + for (i = 0; i < MAX_DMA_CHANNELS; i++) { + if (dint & DMAC_CHANNEL(i)) { + struct dma_channel *channel = &dma_channels[i]; + + /* Clear Err interrupt of channel i */ + writel(DMAC_CHANNEL(i), DMAC_IECR); + writel(0, DMAC_IECR); + + if (channel->name && channel->err_handler) { + channel->err_handler(i, channel->data); + } else { + /* + * IRQ for an unregistered DMA channel: + * let's clear the interrupts and disable it. + */ + printk(KERN_WARNING "spurious IRQ for" + " DMA channel %d\n", i); + } + } + } + return IRQ_HANDLED; +} + +int __init puv3_init_dma(void) +{ + int i, ret; + + /* dma channel priorities on v8 processors: + * ch 0 - 1 <--> (0) DMA_PRIO_HIGH + * ch 2 - 3 <--> (1) DMA_PRIO_MEDIUM + * ch 4 - 5 <--> (2) DMA_PRIO_LOW + */ + for (i = 0; i < MAX_DMA_CHANNELS; i++) { + puv3_stop_dma(i); + dma_channels[i].name = NULL; + dma_channels[i].prio = min((i & 0x7) >> 1, DMA_PRIO_LOW); + } + + ret = request_irq(IRQ_DMA, dma_irq_handler, 0, "DMA", NULL); + if (ret) { + printk(KERN_CRIT "Can't register IRQ for DMA\n"); + return ret; + } + + ret = request_irq(IRQ_DMAERR, dma_err_handler, 0, "DMAERR", NULL); + if (ret) { + printk(KERN_CRIT "Can't register IRQ for DMAERR\n"); + free_irq(IRQ_DMA, "DMA"); + return ret; + } + + return 0; +} + +postcore_initcall(puv3_init_dma); diff --git a/arch/unicore32/kernel/early_printk.c b/arch/unicore32/kernel/early_printk.c new file mode 100644 index 000000000000..3922255f1fa8 --- /dev/null +++ b/arch/unicore32/kernel/early_printk.c @@ -0,0 +1,59 @@ +/* + * linux/arch/unicore32/kernel/early_printk.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/console.h> +#include <linux/init.h> +#include <linux/string.h> +#include <mach/ocd.h> + +/* On-Chip-Debugger functions */ + +static void early_ocd_write(struct console *con, const char *s, unsigned n) +{ + while (*s && n-- > 0) { + if (*s == '\n') + ocd_putc((int)'\r'); + ocd_putc((int)*s); + s++; + } +} + +static struct console early_ocd_console = { + .name = "earlyocd", + .write = early_ocd_write, + .flags = CON_PRINTBUFFER, + .index = -1, +}; + +/* Direct interface for emergencies */ +static struct console *early_console = &early_ocd_console; + +static int __initdata keep_early; + +static int __init setup_early_printk(char *buf) +{ + if (!buf) + return 0; + + if (strstr(buf, "keep")) + keep_early = 1; + + if (!strncmp(buf, "ocd", 3)) + early_console = &early_ocd_console; + + if (keep_early) + early_console->flags &= ~CON_BOOT; + else + early_console->flags |= CON_BOOT; + register_console(early_console); + return 0; +} +early_param("earlyprintk", setup_early_printk); diff --git a/arch/unicore32/kernel/elf.c b/arch/unicore32/kernel/elf.c new file mode 100644 index 000000000000..0a176734fefa --- /dev/null +++ b/arch/unicore32/kernel/elf.c @@ -0,0 +1,38 @@ +/* + * linux/arch/unicore32/kernel/elf.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/module.h> +#include <linux/sched.h> +#include <linux/personality.h> +#include <linux/binfmts.h> +#include <linux/elf.h> + +int elf_check_arch(const struct elf32_hdr *x) +{ + /* Make sure it's an UniCore executable */ + if (x->e_machine != EM_UNICORE) + return 0; + + /* Make sure the entry address is reasonable */ + if (x->e_entry & 3) + return 0; + + return 1; +} +EXPORT_SYMBOL(elf_check_arch); + +void elf_set_personality(const struct elf32_hdr *x) +{ + unsigned int personality = PER_LINUX; + + set_personality(personality); +} +EXPORT_SYMBOL(elf_set_personality); diff --git a/arch/unicore32/kernel/entry.S b/arch/unicore32/kernel/entry.S new file mode 100644 index 000000000000..00a259f9819e --- /dev/null +++ b/arch/unicore32/kernel/entry.S @@ -0,0 +1,824 @@ +/* + * linux/arch/unicore32/kernel/entry.S + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Low-level vector interface routines + */ +#include <linux/init.h> +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <asm/errno.h> +#include <asm/thread_info.h> +#include <asm/memory.h> +#include <asm/unistd.h> +#include <generated/asm-offsets.h> +#include "debug-macro.S" + +@ +@ Most of the stack format comes from struct pt_regs, but with +@ the addition of 8 bytes for storing syscall args 5 and 6. +@ +#define S_OFF 8 + +/* + * The SWI code relies on the fact that R0 is at the bottom of the stack + * (due to slow/fast restore user regs). + */ +#if S_R0 != 0 +#error "Please fix" +#endif + + .macro zero_fp +#ifdef CONFIG_FRAME_POINTER + mov fp, #0 +#endif + .endm + + .macro alignment_trap, rtemp +#ifdef CONFIG_ALIGNMENT_TRAP + ldw \rtemp, .LCcralign + ldw \rtemp, [\rtemp] + movc p0.c1, \rtemp, #0 +#endif + .endm + + .macro load_user_sp_lr, rd, rtemp, offset = 0 + mov \rtemp, asr + xor \rtemp, \rtemp, #(PRIV_MODE ^ SUSR_MODE) + mov.a asr, \rtemp @ switch to the SUSR mode + + ldw sp, [\rd+], #\offset @ load sp_user + ldw lr, [\rd+], #\offset + 4 @ load lr_user + + xor \rtemp, \rtemp, #(PRIV_MODE ^ SUSR_MODE) + mov.a asr, \rtemp @ switch back to the PRIV mode + .endm + + .macro priv_exit, rpsr + mov.a bsr, \rpsr + ldm.w (r0 - r15), [sp]+ + ldm.b (r16 - pc), [sp]+ @ load r0 - pc, asr + .endm + + .macro restore_user_regs, fast = 0, offset = 0 + ldw r1, [sp+], #\offset + S_PSR @ get calling asr + ldw lr, [sp+], #\offset + S_PC @ get pc + mov.a bsr, r1 @ save in bsr_priv + .if \fast + add sp, sp, #\offset + S_R1 @ r0 is syscall return value + ldm.w (r1 - r15), [sp]+ @ get calling r1 - r15 + ldur (r16 - lr), [sp]+ @ get calling r16 - lr + .else + ldm.w (r0 - r15), [sp]+ @ get calling r0 - r15 + ldur (r16 - lr), [sp]+ @ get calling r16 - lr + .endif + nop + add sp, sp, #S_FRAME_SIZE - S_R16 + mov.a pc, lr @ return + @ and move bsr_priv into asr + .endm + + .macro get_thread_info, rd + mov \rd, sp >> #13 + mov \rd, \rd << #13 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldw \base, =(PKUNITY_INTC_BASE) + ldw \irqstat, [\base+], #0xC @ INTC_ICIP + ldw \tmp, [\base+], #0x4 @ INTC_ICMR + and.a \irqstat, \irqstat, \tmp + beq 1001f + cntlz \irqnr, \irqstat + rsub \irqnr, \irqnr, #31 +1001: /* EQ will be set if no irqs pending */ + .endm + +#ifdef CONFIG_DEBUG_LL + .macro printreg, reg, temp + adr \temp, 901f + stm (r0-r3), [\temp]+ + stw lr, [\temp+], #0x10 + mov r0, \reg + b.l printhex8 + mov r0, #':' + b.l printch + mov r0, pc + b.l printhex8 + adr r0, 902f + b.l printascii + adr \temp, 901f + ldm (r0-r3), [\temp]+ + ldw lr, [\temp+], #0x10 + b 903f +901: .word 0, 0, 0, 0, 0 @ r0-r3, lr +902: .asciz ": epip4d\n" + .align +903: + .endm +#endif + +/* + * These are the registers used in the syscall handler, and allow us to + * have in theory up to 7 arguments to a function - r0 to r6. + * + * Note that tbl == why is intentional. + * + * We must set at least "tsk" and "why" when calling ret_with_reschedule. + */ +scno .req r21 @ syscall number +tbl .req r22 @ syscall table pointer +why .req r22 @ Linux syscall (!= 0) +tsk .req r23 @ current thread_info + +/* + * Interrupt handling. Preserves r17, r18, r19 + */ + .macro intr_handler +1: get_irqnr_and_base r0, r6, r5, lr + beq 2f + mov r1, sp + @ + @ routine called with r0 = irq number, r1 = struct pt_regs * + @ + adr lr, 1b + b asm_do_IRQ +2: + .endm + +/* + * PRIV mode handlers + */ + .macro priv_entry + sub sp, sp, #(S_FRAME_SIZE - 4) + stm (r1 - r15), [sp]+ + add r5, sp, #S_R15 + stm (r16 - r28), [r5]+ + + ldm (r1 - r3), [r0]+ + add r5, sp, #S_SP - 4 @ here for interlock avoidance + mov r4, #-1 @ "" "" "" "" + add r0, sp, #(S_FRAME_SIZE - 4) + stw.w r1, [sp+], #-4 @ save the "real" r0 copied + @ from the exception stack + + mov r1, lr + + @ + @ We are now ready to fill in the remaining blanks on the stack: + @ + @ r0 - sp_priv + @ r1 - lr_priv + @ r2 - lr_<exception>, already fixed up for correct return/restart + @ r3 - bsr_<exception> + @ r4 - orig_r0 (see pt_regs definition in ptrace.h) + @ + stm (r0 - r4), [r5]+ + .endm + +/* + * User mode handlers + * + */ + .macro user_entry + sub sp, sp, #S_FRAME_SIZE + stm (r1 - r15), [sp+] + add r4, sp, #S_R16 + stm (r16 - r28), [r4]+ + + ldm (r1 - r3), [r0]+ + add r0, sp, #S_PC @ here for interlock avoidance + mov r4, #-1 @ "" "" "" "" + + stw r1, [sp] @ save the "real" r0 copied + @ from the exception stack + + @ + @ We are now ready to fill in the remaining blanks on the stack: + @ + @ r2 - lr_<exception>, already fixed up for correct return/restart + @ r3 - bsr_<exception> + @ r4 - orig_r0 (see pt_regs definition in ptrace.h) + @ + @ Also, separately save sp_user and lr_user + @ + stm (r2 - r4), [r0]+ + stur (sp, lr), [r0-] + + @ + @ Enable the alignment trap while in kernel mode + @ + alignment_trap r0 + + @ + @ Clear FP to mark the first stack frame + @ + zero_fp + .endm + + .text + +@ +@ __invalid - generic code for failed exception +@ (re-entrant version of handlers) +@ +__invalid: + sub sp, sp, #S_FRAME_SIZE + stm (r1 - r15), [sp+] + add r1, sp, #S_R16 + stm (r16 - r28, sp, lr), [r1]+ + + zero_fp + + ldm (r4 - r6), [r0]+ + add r0, sp, #S_PC @ here for interlock avoidance + mov r7, #-1 @ "" "" "" "" + stw r4, [sp] @ save preserved r0 + stm (r5 - r7), [r0]+ @ lr_<exception>, + @ asr_<exception>, "old_r0" + + mov r0, sp + mov r1, asr + b bad_mode +ENDPROC(__invalid) + + .align 5 +__dabt_priv: + priv_entry + + @ + @ get ready to re-enable interrupts if appropriate + @ + mov r17, asr + cand.a r3, #PSR_I_BIT + bne 1f + andn r17, r17, #PSR_I_BIT +1: + + @ + @ Call the processor-specific abort handler: + @ + @ r2 - aborted context pc + @ r3 - aborted context asr + @ + @ The abort handler must return the aborted address in r0, and + @ the fault status register in r1. + @ + movc r1, p0.c3, #0 @ get FSR + movc r0, p0.c4, #0 @ get FAR + + @ + @ set desired INTR state, then call main handler + @ + mov.a asr, r17 + mov r2, sp + b.l do_DataAbort + + @ + @ INTRs off again before pulling preserved data off the stack + @ + disable_irq r0 + + @ + @ restore BSR and restart the instruction + @ + ldw r2, [sp+], #S_PSR + priv_exit r2 @ return from exception +ENDPROC(__dabt_priv) + + .align 5 +__intr_priv: + priv_entry + + intr_handler + + mov r0, #0 @ epip4d + movc p0.c5, r0, #14 + nop; nop; nop; nop; nop; nop; nop; nop + + ldw r4, [sp+], #S_PSR @ irqs are already disabled + + priv_exit r4 @ return from exception +ENDPROC(__intr_priv) + + .ltorg + + .align 5 +__extn_priv: + priv_entry + + mov r0, sp @ struct pt_regs *regs + mov r1, asr + b bad_mode @ not supported +ENDPROC(__extn_priv) + + .align 5 +__pabt_priv: + priv_entry + + @ + @ re-enable interrupts if appropriate + @ + mov r17, asr + cand.a r3, #PSR_I_BIT + bne 1f + andn r17, r17, #PSR_I_BIT +1: + + @ + @ set args, then call main handler + @ + @ r0 - address of faulting instruction + @ r1 - pointer to registers on stack + @ + mov r0, r2 @ pass address of aborted instruction + mov r1, #5 + mov.a asr, r17 + mov r2, sp @ regs + b.l do_PrefetchAbort @ call abort handler + + @ + @ INTRs off again before pulling preserved data off the stack + @ + disable_irq r0 + + @ + @ restore BSR and restart the instruction + @ + ldw r2, [sp+], #S_PSR + priv_exit r2 @ return from exception +ENDPROC(__pabt_priv) + + .align 5 +.LCcralign: + .word cr_alignment + + .align 5 +__dabt_user: + user_entry + +#ifdef CONFIG_UNICORE_FPU_F64 + cff ip, s31 + cand.a ip, #0x08000000 @ FPU execption traps? + beq 209f + + ldw ip, [sp+], #S_PC + add ip, ip, #4 + stw ip, [sp+], #S_PC + @ + @ fall through to the emulation code, which returns using r19 if + @ it has emulated the instruction, or the more conventional lr + @ if we are to treat this as a real extended instruction + @ + @ r0 - instruction + @ +1: ldw.u r0, [r2] + adr r19, ret_from_exception + adr lr, 209f + @ + @ fallthrough to call do_uc_f64 + @ +/* + * Check whether the instruction is a co-processor instruction. + * If yes, we need to call the relevant co-processor handler. + * + * Note that we don't do a full check here for the co-processor + * instructions; all instructions with bit 27 set are well + * defined. The only instructions that should fault are the + * co-processor instructions. + * + * Emulators may wish to make use of the following registers: + * r0 = instruction opcode. + * r2 = PC + * r19 = normal "successful" return address + * r20 = this threads thread_info structure. + * lr = unrecognised instruction return address + */ + get_thread_info r20 @ get current thread + and r8, r0, #0x00003c00 @ mask out CP number + mov r7, #1 + stb r7, [r20+], #TI_USED_CP + 2 @ set appropriate used_cp[] + + @ F64 hardware support entry point. + @ r0 = faulted instruction + @ r19 = return address + @ r20 = fp_state + enable_irq r4 + add r20, r20, #TI_FPSTATE @ r20 = workspace + cff r1, s31 @ get fpu FPSCR + andn r2, r1, #0x08000000 + ctf r2, s31 @ clear 27 bit + mov r2, sp @ nothing stacked - regdump is at TOS + mov lr, r19 @ setup for a return to the user code + + @ Now call the C code to package up the bounce to the support code + @ r0 holds the trigger instruction + @ r1 holds the FPSCR value + @ r2 pointer to register dump + b ucf64_exchandler +209: +#endif + @ + @ Call the processor-specific abort handler: + @ + @ r2 - aborted context pc + @ r3 - aborted context asr + @ + @ The abort handler must return the aborted address in r0, and + @ the fault status register in r1. + @ + movc r1, p0.c3, #0 @ get FSR + movc r0, p0.c4, #0 @ get FAR + + @ + @ INTRs on, then call the main handler + @ + enable_irq r2 + mov r2, sp + adr lr, ret_from_exception + b do_DataAbort +ENDPROC(__dabt_user) + + .align 5 +__intr_user: + user_entry + + get_thread_info tsk + + intr_handler + + mov why, #0 + b ret_to_user +ENDPROC(__intr_user) + + .ltorg + + .align 5 +__extn_user: + user_entry + + mov r0, sp + mov r1, asr + b bad_mode +ENDPROC(__extn_user) + + .align 5 +__pabt_user: + user_entry + + mov r0, r2 @ pass address of aborted instruction. + mov r1, #5 + enable_irq r1 @ Enable interrupts + mov r2, sp @ regs + b.l do_PrefetchAbort @ call abort handler + /* fall through */ +/* + * This is the return code to user mode for abort handlers + */ +ENTRY(ret_from_exception) + get_thread_info tsk + mov why, #0 + b ret_to_user +ENDPROC(__pabt_user) +ENDPROC(ret_from_exception) + +/* + * Register switch for UniCore V2 processors + * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info + * previous and next are guaranteed not to be the same. + */ +ENTRY(__switch_to) + add ip, r1, #TI_CPU_SAVE + stm.w (r4 - r15), [ip]+ + stm.w (r16 - r27, sp, lr), [ip]+ + +#ifdef CONFIG_UNICORE_FPU_F64 + add ip, r1, #TI_FPSTATE + sfm.w (f0 - f7 ), [ip]+ + sfm.w (f8 - f15), [ip]+ + sfm.w (f16 - f23), [ip]+ + sfm.w (f24 - f31), [ip]+ + cff r4, s31 + stw r4, [ip] + + add ip, r2, #TI_FPSTATE + lfm.w (f0 - f7 ), [ip]+ + lfm.w (f8 - f15), [ip]+ + lfm.w (f16 - f23), [ip]+ + lfm.w (f24 - f31), [ip]+ + ldw r4, [ip] + ctf r4, s31 +#endif + add ip, r2, #TI_CPU_SAVE + ldm.w (r4 - r15), [ip]+ + ldm (r16 - r27, sp, pc), [ip]+ @ Load all regs saved previously +ENDPROC(__switch_to) + + .align 5 +/* + * This is the fast syscall return path. We do as little as + * possible here, and this includes saving r0 back into the PRIV + * stack. + */ +ret_fast_syscall: + disable_irq r1 @ disable interrupts + ldw r1, [tsk+], #TI_FLAGS + cand.a r1, #_TIF_WORK_MASK + bne fast_work_pending + + @ fast_restore_user_regs + restore_user_regs fast = 1, offset = S_OFF + +/* + * Ok, we need to do extra processing, enter the slow path. + */ +fast_work_pending: + stw.w r0, [sp+], #S_R0+S_OFF @ returned r0 +work_pending: + cand.a r1, #_TIF_NEED_RESCHED + bne work_resched + cand.a r1, #_TIF_SIGPENDING|_TIF_NOTIFY_RESUME + beq no_work_pending + mov r0, sp @ 'regs' + mov r2, why @ 'syscall' + cand.a r1, #_TIF_SIGPENDING @ delivering a signal? + cmovne why, #0 @ prevent further restarts + b.l do_notify_resume + b ret_slow_syscall @ Check work again + +work_resched: + b.l schedule +/* + * "slow" syscall return path. "why" tells us if this was a real syscall. + */ +ENTRY(ret_to_user) +ret_slow_syscall: + disable_irq r1 @ disable interrupts + get_thread_info tsk @ epip4d, one path error?! + ldw r1, [tsk+], #TI_FLAGS + cand.a r1, #_TIF_WORK_MASK + bne work_pending +no_work_pending: + @ slow_restore_user_regs + restore_user_regs fast = 0, offset = 0 +ENDPROC(ret_to_user) + +/* + * This is how we return from a fork. + */ +ENTRY(ret_from_fork) + b.l schedule_tail + get_thread_info tsk + ldw r1, [tsk+], #TI_FLAGS @ check for syscall tracing + mov why, #1 + cand.a r1, #_TIF_SYSCALL_TRACE @ are we tracing syscalls? + beq ret_slow_syscall + mov r1, sp + mov r0, #1 @ trace exit [IP = 1] + b.l syscall_trace + b ret_slow_syscall +ENDPROC(ret_from_fork) + +/*============================================================================= + * SWI handler + *----------------------------------------------------------------------------- + */ + .align 5 +ENTRY(vector_swi) + sub sp, sp, #S_FRAME_SIZE + stm (r0 - r15), [sp]+ @ Calling r0 - r15 + add r8, sp, #S_R16 + stm (r16 - r28), [r8]+ @ Calling r16 - r28 + add r8, sp, #S_PC + stur (sp, lr), [r8-] @ Calling sp, lr + mov r8, bsr @ called from non-REAL mode + stw lr, [sp+], #S_PC @ Save calling PC + stw r8, [sp+], #S_PSR @ Save ASR + stw r0, [sp+], #S_OLD_R0 @ Save OLD_R0 + zero_fp + + /* + * Get the system call number. + */ + sub ip, lr, #4 + ldw.u scno, [ip] @ get SWI instruction + +#ifdef CONFIG_ALIGNMENT_TRAP + ldw ip, __cr_alignment + ldw ip, [ip] + movc p0.c1, ip, #0 @ update control register +#endif + enable_irq ip + + get_thread_info tsk + ldw tbl, =sys_call_table @ load syscall table pointer + + andn scno, scno, #0xff000000 @ mask off SWI op-code + andn scno, scno, #0x00ff0000 @ mask off SWI op-code + + stm.w (r4, r5), [sp-] @ push fifth and sixth args + ldw ip, [tsk+], #TI_FLAGS @ check for syscall tracing + cand.a ip, #_TIF_SYSCALL_TRACE @ are we tracing syscalls? + bne __sys_trace + + csub.a scno, #__NR_syscalls @ check upper syscall limit + adr lr, ret_fast_syscall @ return address + bea 1f + ldw pc, [tbl+], scno << #2 @ call sys_* routine +1: + add r1, sp, #S_OFF +2: mov why, #0 @ no longer a real syscall + b sys_ni_syscall @ not private func + + /* + * This is the really slow path. We're going to be doing + * context switches, and waiting for our parent to respond. + */ +__sys_trace: + mov r2, scno + add r1, sp, #S_OFF + mov r0, #0 @ trace entry [IP = 0] + b.l syscall_trace + + adr lr, __sys_trace_return @ return address + mov scno, r0 @ syscall number (possibly new) + add r1, sp, #S_R0 + S_OFF @ pointer to regs + csub.a scno, #__NR_syscalls @ check upper syscall limit + bea 2b + ldm (r0 - r3), [r1]+ @ have to reload r0 - r3 + ldw pc, [tbl+], scno << #2 @ call sys_* routine + +__sys_trace_return: + stw.w r0, [sp+], #S_R0 + S_OFF @ save returned r0 + mov r2, scno + mov r1, sp + mov r0, #1 @ trace exit [IP = 1] + b.l syscall_trace + b ret_slow_syscall + + .align 5 +#ifdef CONFIG_ALIGNMENT_TRAP + .type __cr_alignment, #object +__cr_alignment: + .word cr_alignment +#endif + .ltorg + +ENTRY(sys_execve) + add r3, sp, #S_OFF + b __sys_execve +ENDPROC(sys_execve) + +ENTRY(sys_clone) + add ip, sp, #S_OFF + stw ip, [sp+], #4 + b __sys_clone +ENDPROC(sys_clone) + +ENTRY(sys_rt_sigreturn) + add r0, sp, #S_OFF + mov why, #0 @ prevent syscall restart handling + b __sys_rt_sigreturn +ENDPROC(sys_rt_sigreturn) + +ENTRY(sys_sigaltstack) + ldw r2, [sp+], #S_OFF + S_SP + b do_sigaltstack +ENDPROC(sys_sigaltstack) + + __INIT + +/* + * Vector stubs. + * + * This code is copied to 0xffff0200 so we can use branches in the + * vectors, rather than ldr's. Note that this code must not + * exceed 0x300 bytes. + * + * Common stub entry macro: + * Enter in INTR mode, bsr = PRIV/USER ASR, lr = PRIV/USER PC + * + * SP points to a minimal amount of processor-private memory, the address + * of which is copied into r0 for the mode specific abort handler. + */ + .macro vector_stub, name, mode + .align 5 + +vector_\name: + @ + @ Save r0, lr_<exception> (parent PC) and bsr_<exception> + @ (parent ASR) + @ + stw r0, [sp] + stw lr, [sp+], #4 @ save r0, lr + mov lr, bsr + stw lr, [sp+], #8 @ save bsr + + @ + @ Prepare for PRIV mode. INTRs remain disabled. + @ + mov r0, asr + xor r0, r0, #(\mode ^ PRIV_MODE) + mov.a bsr, r0 + + @ + @ the branch table must immediately follow this code + @ + and lr, lr, #0x03 + add lr, lr, #1 + mov r0, sp + ldw lr, [pc+], lr << #2 + mov.a pc, lr @ branch to handler in PRIV mode +ENDPROC(vector_\name) + .align 2 + @ handler addresses follow this label + .endm + + .globl __stubs_start +__stubs_start: +/* + * Interrupt dispatcher + */ + vector_stub intr, INTR_MODE + + .long __intr_user @ 0 (USER) + .long __invalid @ 1 + .long __invalid @ 2 + .long __intr_priv @ 3 (PRIV) + +/* + * Data abort dispatcher + * Enter in ABT mode, bsr = USER ASR, lr = USER PC + */ + vector_stub dabt, ABRT_MODE + + .long __dabt_user @ 0 (USER) + .long __invalid @ 1 + .long __invalid @ 2 (INTR) + .long __dabt_priv @ 3 (PRIV) + +/* + * Prefetch abort dispatcher + * Enter in ABT mode, bsr = USER ASR, lr = USER PC + */ + vector_stub pabt, ABRT_MODE + + .long __pabt_user @ 0 (USER) + .long __invalid @ 1 + .long __invalid @ 2 (INTR) + .long __pabt_priv @ 3 (PRIV) + +/* + * Undef instr entry dispatcher + * Enter in EXTN mode, bsr = PRIV/USER ASR, lr = PRIV/USER PC + */ + vector_stub extn, EXTN_MODE + + .long __extn_user @ 0 (USER) + .long __invalid @ 1 + .long __invalid @ 2 (INTR) + .long __extn_priv @ 3 (PRIV) + +/* + * We group all the following data together to optimise + * for CPUs with separate I & D caches. + */ + .align 5 + +.LCvswi: + .word vector_swi + + .globl __stubs_end +__stubs_end: + + .equ stubs_offset, __vectors_start + 0x200 - __stubs_start + + .globl __vectors_start +__vectors_start: + jepriv SYS_ERROR0 + b vector_extn + stubs_offset + ldw pc, .LCvswi + stubs_offset + b vector_pabt + stubs_offset + b vector_dabt + stubs_offset + jepriv SYS_ERROR0 + b vector_intr + stubs_offset + jepriv SYS_ERROR0 + + .globl __vectors_end +__vectors_end: + + .data + + .globl cr_alignment + .globl cr_no_alignment +cr_alignment: + .space 4 +cr_no_alignment: + .space 4 diff --git a/arch/unicore32/kernel/fpu-ucf64.c b/arch/unicore32/kernel/fpu-ucf64.c new file mode 100644 index 000000000000..282a60ac82ba --- /dev/null +++ b/arch/unicore32/kernel/fpu-ucf64.c @@ -0,0 +1,126 @@ +/* + * linux/arch/unicore32/kernel/fpu-ucf64.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/module.h> +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/signal.h> +#include <linux/sched.h> +#include <linux/init.h> + +#include <asm/fpu-ucf64.h> + +/* + * A special flag to tell the normalisation code not to normalise. + */ +#define F64_NAN_FLAG 0x100 + +/* + * A bit pattern used to indicate the initial (unset) value of the + * exception mask, in case nothing handles an instruction. This + * doesn't include the NAN flag, which get masked out before + * we check for an error. + */ +#define F64_EXCEPTION_ERROR ((u32)-1 & ~F64_NAN_FLAG) + +/* + * Since we aren't building with -mfpu=f64, we need to code + * these instructions using their MRC/MCR equivalents. + */ +#define f64reg(_f64_) #_f64_ + +#define cff(_f64_) ({ \ + u32 __v; \ + asm("cff %0, " f64reg(_f64_) "@ fmrx %0, " #_f64_ \ + : "=r" (__v) : : "cc"); \ + __v; \ + }) + +#define ctf(_f64_, _var_) \ + asm("ctf %0, " f64reg(_f64_) "@ fmxr " #_f64_ ", %0" \ + : : "r" (_var_) : "cc") + +/* + * Raise a SIGFPE for the current process. + * sicode describes the signal being raised. + */ +void ucf64_raise_sigfpe(unsigned int sicode, struct pt_regs *regs) +{ + siginfo_t info; + + memset(&info, 0, sizeof(info)); + + info.si_signo = SIGFPE; + info.si_code = sicode; + info.si_addr = (void __user *)(instruction_pointer(regs) - 4); + + /* + * This is the same as NWFPE, because it's not clear what + * this is used for + */ + current->thread.error_code = 0; + current->thread.trap_no = 6; + + send_sig_info(SIGFPE, &info, current); +} + +/* + * Handle exceptions of UniCore-F64. + */ +void ucf64_exchandler(u32 inst, u32 fpexc, struct pt_regs *regs) +{ + u32 tmp = fpexc; + u32 exc = F64_EXCEPTION_ERROR & fpexc; + + pr_debug("UniCore-F64: instruction %08x fpscr %08x\n", + inst, fpexc); + + if (exc & FPSCR_CMPINSTR_BIT) { + if (exc & FPSCR_CON) + tmp |= FPSCR_CON; + else + tmp &= ~(FPSCR_CON); + exc &= ~(FPSCR_CMPINSTR_BIT | FPSCR_CON); + } else { + pr_debug(KERN_ERR "UniCore-F64 Error: unhandled exceptions\n"); + pr_debug(KERN_ERR "UniCore-F64 FPSCR 0x%08x INST 0x%08x\n", + cff(FPSCR), inst); + + ucf64_raise_sigfpe(0, regs); + return; + } + + /* + * Update the FPSCR with the additional exception flags. + * Comparison instructions always return at least one of + * these flags set. + */ + tmp &= ~(FPSCR_TRAP | FPSCR_IOS | FPSCR_OFS | FPSCR_UFS | + FPSCR_IXS | FPSCR_HIS | FPSCR_IOC | FPSCR_OFC | + FPSCR_UFC | FPSCR_IXC | FPSCR_HIC); + + tmp |= exc; + ctf(FPSCR, tmp); +} + +/* + * F64 support code initialisation. + */ +static int __init ucf64_init(void) +{ + ctf(FPSCR, 0x0); /* FPSCR_UFE | FPSCR_NDE perhaps better */ + + printk(KERN_INFO "Enable UniCore-F64 support.\n"); + + return 0; +} + +late_initcall(ucf64_init); diff --git a/arch/unicore32/kernel/gpio.c b/arch/unicore32/kernel/gpio.c new file mode 100644 index 000000000000..cb12ec39552c --- /dev/null +++ b/arch/unicore32/kernel/gpio.c @@ -0,0 +1,122 @@ +/* + * linux/arch/unicore32/kernel/gpio.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn> + * Copyright (C) 2001-2010 Guan Xuetao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/* in FPGA, no GPIO support */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/gpio.h> +#include <mach/hardware.h> + +#ifdef CONFIG_LEDS +#include <linux/leds.h> +#include <linux/platform_device.h> + +static const struct gpio_led puv3_gpio_leds[] = { + { .name = "cpuhealth", .gpio = GPO_CPU_HEALTH, .active_low = 0, + .default_trigger = "heartbeat", }, + { .name = "hdd_led", .gpio = GPO_HDD_LED, .active_low = 1, + .default_trigger = "ide-disk", }, +}; + +static const struct gpio_led_platform_data puv3_gpio_led_data = { + .num_leds = ARRAY_SIZE(puv3_gpio_leds), + .leds = (void *) puv3_gpio_leds, +}; + +static struct platform_device puv3_gpio_gpio_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = (void *) &puv3_gpio_led_data, + } +}; + +static int __init puv3_gpio_leds_init(void) +{ + platform_device_register(&puv3_gpio_gpio_leds); + return 0; +} + +device_initcall(puv3_gpio_leds_init); +#endif + +static int puv3_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + return readl(GPIO_GPLR) & GPIO_GPIO(offset); +} + +static void puv3_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + if (value) + writel(GPIO_GPIO(offset), GPIO_GPSR); + else + writel(GPIO_GPIO(offset), GPIO_GPCR); +} + +static int puv3_direction_input(struct gpio_chip *chip, unsigned offset) +{ + unsigned long flags; + + local_irq_save(flags); + writel(readl(GPIO_GPDR) & ~GPIO_GPIO(offset), GPIO_GPDR); + local_irq_restore(flags); + return 0; +} + +static int puv3_direction_output(struct gpio_chip *chip, unsigned offset, + int value) +{ + unsigned long flags; + + local_irq_save(flags); + puv3_gpio_set(chip, offset, value); + writel(readl(GPIO_GPDR) | GPIO_GPIO(offset), GPIO_GPDR); + local_irq_restore(flags); + return 0; +} + +static struct gpio_chip puv3_gpio_chip = { + .label = "gpio", + .direction_input = puv3_direction_input, + .direction_output = puv3_direction_output, + .set = puv3_gpio_set, + .get = puv3_gpio_get, + .base = 0, + .ngpio = GPIO_MAX + 1, +}; + +void __init puv3_init_gpio(void) +{ + writel(GPIO_DIR, GPIO_GPDR); +#if defined(CONFIG_PUV3_NB0916) || defined(CONFIG_PUV3_SMW0919) \ + || defined(CONFIG_PUV3_DB0913) + gpio_set_value(GPO_WIFI_EN, 1); + gpio_set_value(GPO_HDD_LED, 1); + gpio_set_value(GPO_VGA_EN, 1); + gpio_set_value(GPO_LCD_EN, 1); + gpio_set_value(GPO_CAM_PWR_EN, 0); + gpio_set_value(GPO_LCD_VCC_EN, 1); + gpio_set_value(GPO_SOFT_OFF, 1); + gpio_set_value(GPO_BT_EN, 1); + gpio_set_value(GPO_FAN_ON, 0); + gpio_set_value(GPO_SPKR, 0); + gpio_set_value(GPO_CPU_HEALTH, 1); + gpio_set_value(GPO_LAN_SEL, 1); +/* + * DO NOT modify the GPO_SET_V1 and GPO_SET_V2 in kernel + * gpio_set_value(GPO_SET_V1, 1); + * gpio_set_value(GPO_SET_V2, 1); + */ +#endif + gpiochip_add(&puv3_gpio_chip); +} diff --git a/arch/unicore32/kernel/head.S b/arch/unicore32/kernel/head.S new file mode 100644 index 000000000000..92255f3ab6a7 --- /dev/null +++ b/arch/unicore32/kernel/head.S @@ -0,0 +1,252 @@ +/* + * linux/arch/unicore32/kernel/head.S + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/linkage.h> +#include <linux/init.h> + +#include <asm/assembler.h> +#include <asm/ptrace.h> +#include <generated/asm-offsets.h> +#include <asm/memory.h> +#include <asm/thread_info.h> +#include <asm/system.h> +#include <asm/pgtable-hwdef.h> + +#if (PHYS_OFFSET & 0x003fffff) +#error "PHYS_OFFSET must be at an even 4MiB boundary!" +#endif + +#define KERNEL_RAM_VADDR (PAGE_OFFSET + KERNEL_IMAGE_START) +#define KERNEL_RAM_PADDR (PHYS_OFFSET + KERNEL_IMAGE_START) + +#define KERNEL_PGD_PADDR (KERNEL_RAM_PADDR - 0x1000) +#define KERNEL_PGD_VADDR (KERNEL_RAM_VADDR - 0x1000) + +#define KERNEL_START KERNEL_RAM_VADDR +#define KERNEL_END _end + +/* + * swapper_pg_dir is the virtual address of the initial page table. + * We place the page tables 4K below KERNEL_RAM_VADDR. Therefore, we must + * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect + * the least significant 16 bits to be 0x8000, but we could probably + * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x1000. + */ +#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000 +#error KERNEL_RAM_VADDR must start at 0xXXXX8000 +#endif + + .globl swapper_pg_dir + .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x1000 + +/* + * Kernel startup entry point. + * --------------------------- + * + * This is normally called from the decompressor code. The requirements + * are: MMU = off, D-cache = off, I-cache = dont care + * + * This code is mostly position independent, so if you link the kernel at + * 0xc0008000, you call this at __pa(0xc0008000). + */ + __HEAD +ENTRY(stext) + @ set asr + mov r0, #PRIV_MODE @ ensure priv mode + or r0, #PSR_R_BIT | PSR_I_BIT @ disable irqs + mov.a asr, r0 + + @ process identify + movc r0, p0.c0, #0 @ cpuid + movl r1, 0xff00ffff @ mask + movl r2, 0x4d000863 @ value + and r0, r1, r0 + cxor.a r0, r2 + bne __error_p @ invalid processor id + + /* + * Clear the 4K level 1 swapper page table + */ + movl r0, #KERNEL_PGD_PADDR @ page table address + mov r1, #0 + add r2, r0, #0x1000 +101: stw.w r1, [r0]+, #4 + stw.w r1, [r0]+, #4 + stw.w r1, [r0]+, #4 + stw.w r1, [r0]+, #4 + cxor.a r0, r2 + bne 101b + + movl r4, #KERNEL_PGD_PADDR @ page table address + mov r7, #PMD_TYPE_SECT | PMD_PRESENT @ page size: section + or r7, r7, #PMD_SECT_CACHEABLE @ cacheable + or r7, r7, #PMD_SECT_READ | PMD_SECT_WRITE | PMD_SECT_EXEC + + /* + * Create identity mapping for first 4MB of kernel to + * cater for the MMU enable. This identity mapping + * will be removed by paging_init(). We use our current program + * counter to determine corresponding section base address. + */ + mov r6, pc + mov r6, r6 >> #22 @ start of kernel section + or r1, r7, r6 << #22 @ flags + kernel base + stw r1, [r4+], r6 << #2 @ identity mapping + + /* + * Now setup the pagetables for our kernel direct + * mapped region. + */ + add r0, r4, #(KERNEL_START & 0xff000000) >> 20 + stw.w r1, [r0+], #(KERNEL_START & 0x00c00000) >> 20 + movl r6, #(KERNEL_END - 1) + add r0, r0, #4 + add r6, r4, r6 >> #20 +102: csub.a r0, r6 + add r1, r1, #1 << 22 + bua 103f + stw.w r1, [r0]+, #4 + b 102b +103: + /* + * Then map first 4MB of ram in case it contains our boot params. + */ + add r0, r4, #PAGE_OFFSET >> 20 + or r6, r7, #(PHYS_OFFSET & 0xffc00000) + stw r6, [r0] + + ldw r15, __switch_data @ address to jump to after + + /* + * Initialise TLB, Caches, and MMU state ready to switch the MMU + * on. + */ + mov r0, #0 + movc p0.c5, r0, #28 @ cache invalidate all + nop8 + movc p0.c6, r0, #6 @ TLB invalidate all + nop8 + + /* + * ..V. .... ..TB IDAM + * ..1. .... ..01 1111 + */ + movl r0, #0x201f @ control register setting + + /* + * Setup common bits before finally enabling the MMU. Essentially + * this is just loading the page table pointer and domain access + * registers. + */ + #ifndef CONFIG_ALIGNMENT_TRAP + andn r0, r0, #CR_A + #endif + #ifdef CONFIG_CPU_DCACHE_DISABLE + andn r0, r0, #CR_D + #endif + #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH + andn r0, r0, #CR_B + #endif + #ifdef CONFIG_CPU_ICACHE_DISABLE + andn r0, r0, #CR_I + #endif + + movc p0.c2, r4, #0 @ set pgd + b __turn_mmu_on +ENDPROC(stext) + +/* + * Enable the MMU. This completely changes the stucture of the visible + * memory space. You will not be able to trace execution through this. + * + * r0 = cp#0 control register + * r15 = *virtual* address to jump to upon completion + */ + .align 5 +__turn_mmu_on: + mov r0, r0 + movc p0.c1, r0, #0 @ write control reg + nop @ fetch inst by phys addr + mov pc, r15 + nop8 @ fetch inst by phys addr +ENDPROC(__turn_mmu_on) + +/* + * Setup the initial page tables. We only setup the barest + * amount which are required to get the kernel running, which + * generally means mapping in the kernel code. + * + * r9 = cpuid + * r10 = procinfo + * + * Returns: + * r0, r3, r6, r7 corrupted + * r4 = physical page table address + */ + .ltorg + + .align 2 + .type __switch_data, %object +__switch_data: + .long __mmap_switched + .long __bss_start @ r6 + .long _end @ r7 + .long cr_alignment @ r8 + .long init_thread_union + THREAD_START_SP @ sp + +/* + * The following fragment of code is executed with the MMU on in MMU mode, + * and uses absolute addresses; this is not position independent. + * + * r0 = cp#0 control register + */ +__mmap_switched: + adr r3, __switch_data + 4 + + ldm.w (r6, r7, r8), [r3]+ + ldw sp, [r3] + + mov fp, #0 @ Clear BSS (and zero fp) +203: csub.a r6, r7 + bea 204f + stw.w fp, [r6]+,#4 + b 203b +204: + andn r1, r0, #CR_A @ Clear 'A' bit + stm (r0, r1), [r8]+ @ Save control register values + b start_kernel +ENDPROC(__mmap_switched) + +/* + * Exception handling. Something went wrong and we can't proceed. We + * ought to tell the user, but since we don't have any guarantee that + * we're even running on the right architecture, we do virtually nothing. + * + * If CONFIG_DEBUG_LL is set we try to print out something about the error + * and hope for the best (useful if bootloader fails to pass a proper + * machine ID for example). + */ +__error_p: +#ifdef CONFIG_DEBUG_LL + adr r0, str_p1 + b.l printascii + mov r0, r9 + b.l printhex8 + adr r0, str_p2 + b.l printascii +901: nop8 + b 901b +str_p1: .asciz "\nError: unrecognized processor variant (0x" +str_p2: .asciz ").\n" + .align +#endif +ENDPROC(__error_p) + diff --git a/arch/unicore32/kernel/hibernate.c b/arch/unicore32/kernel/hibernate.c new file mode 100644 index 000000000000..7d0f0b7983a0 --- /dev/null +++ b/arch/unicore32/kernel/hibernate.c @@ -0,0 +1,160 @@ +/* + * linux/arch/unicore32/kernel/hibernate.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn> + * Copyright (C) 2001-2010 Guan Xuetao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/gfp.h> +#include <linux/suspend.h> +#include <linux/bootmem.h> + +#include <asm/system.h> +#include <asm/page.h> +#include <asm/pgtable.h> +#include <asm/pgalloc.h> +#include <asm/suspend.h> + +#include "mach/pm.h" + +/* Pointer to the temporary resume page tables */ +pgd_t *resume_pg_dir; + +struct swsusp_arch_regs swsusp_arch_regs_cpu0; + +/* + * Create a middle page table on a resume-safe page and put a pointer to it in + * the given global directory entry. This only returns the gd entry + * in non-PAE compilation mode, since the middle layer is folded. + */ +static pmd_t *resume_one_md_table_init(pgd_t *pgd) +{ + pud_t *pud; + pmd_t *pmd_table; + + pud = pud_offset(pgd, 0); + pmd_table = pmd_offset(pud, 0); + + return pmd_table; +} + +/* + * Create a page table on a resume-safe page and place a pointer to it in + * a middle page directory entry. + */ +static pte_t *resume_one_page_table_init(pmd_t *pmd) +{ + if (pmd_none(*pmd)) { + pte_t *page_table = (pte_t *)get_safe_page(GFP_ATOMIC); + if (!page_table) + return NULL; + + set_pmd(pmd, __pmd(__pa(page_table) | _PAGE_KERNEL_TABLE)); + + BUG_ON(page_table != pte_offset_kernel(pmd, 0)); + + return page_table; + } + + return pte_offset_kernel(pmd, 0); +} + +/* + * This maps the physical memory to kernel virtual address space, a total + * of max_low_pfn pages, by creating page tables starting from address + * PAGE_OFFSET. The page tables are allocated out of resume-safe pages. + */ +static int resume_physical_mapping_init(pgd_t *pgd_base) +{ + unsigned long pfn; + pgd_t *pgd; + pmd_t *pmd; + pte_t *pte; + int pgd_idx, pmd_idx; + + pgd_idx = pgd_index(PAGE_OFFSET); + pgd = pgd_base + pgd_idx; + pfn = 0; + + for (; pgd_idx < PTRS_PER_PGD; pgd++, pgd_idx++) { + pmd = resume_one_md_table_init(pgd); + if (!pmd) + return -ENOMEM; + + if (pfn >= max_low_pfn) + continue; + + for (pmd_idx = 0; pmd_idx < PTRS_PER_PMD; pmd++, pmd_idx++) { + pte_t *max_pte; + + if (pfn >= max_low_pfn) + break; + + /* Map with normal page tables. + * NOTE: We can mark everything as executable here + */ + pte = resume_one_page_table_init(pmd); + if (!pte) + return -ENOMEM; + + max_pte = pte + PTRS_PER_PTE; + for (; pte < max_pte; pte++, pfn++) { + if (pfn >= max_low_pfn) + break; + + set_pte(pte, pfn_pte(pfn, PAGE_KERNEL_EXEC)); + } + } + } + + return 0; +} + +static inline void resume_init_first_level_page_table(pgd_t *pg_dir) +{ +} + +int swsusp_arch_resume(void) +{ + int error; + + resume_pg_dir = (pgd_t *)get_safe_page(GFP_ATOMIC); + if (!resume_pg_dir) + return -ENOMEM; + + resume_init_first_level_page_table(resume_pg_dir); + error = resume_physical_mapping_init(resume_pg_dir); + if (error) + return error; + + /* We have got enough memory and from now on we cannot recover */ + restore_image(resume_pg_dir, restore_pblist); + return 0; +} + +/* + * pfn_is_nosave - check if given pfn is in the 'nosave' section + */ + +int pfn_is_nosave(unsigned long pfn) +{ + unsigned long begin_pfn = __pa(&__nosave_begin) >> PAGE_SHIFT; + unsigned long end_pfn = PAGE_ALIGN(__pa(&__nosave_end)) >> PAGE_SHIFT; + + return (pfn >= begin_pfn) && (pfn < end_pfn); +} + +void save_processor_state(void) +{ +} + +void restore_processor_state(void) +{ + local_flush_tlb_all(); +} diff --git a/arch/unicore32/kernel/hibernate_asm.S b/arch/unicore32/kernel/hibernate_asm.S new file mode 100644 index 000000000000..cc3c65253c8c --- /dev/null +++ b/arch/unicore32/kernel/hibernate_asm.S @@ -0,0 +1,117 @@ +/* + * linux/arch/unicore32/kernel/hibernate_asm.S + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn> + * Copyright (C) 2001-2010 Guan Xuetao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/sys.h> +#include <linux/errno.h> +#include <linux/linkage.h> +#include <generated/asm-offsets.h> +#include <asm/page.h> +#include <asm/pgtable.h> +#include <asm/assembler.h> + +@ restore_image(pgd_t *resume_pg_dir, struct pbe *restore_pblist) +@ r0: resume_pg_dir +@ r1: restore_pblist +@ copy restore_pblist pages +@ restore registers from swsusp_arch_regs_cpu0 +@ +ENTRY(restore_image) + sub r0, r0, #PAGE_OFFSET + mov r5, #0 + movc p0.c6, r5, #6 @invalidate ITLB & DTLB + movc p0.c2, r0, #0 + nop + nop + nop + nop + nop + nop + nop + + .p2align 4,,7 +101: + csub.a r1, #0 + beq 109f + + ldw r6, [r1+], #PBE_ADDRESS + ldw r7, [r1+], #PBE_ORIN_ADDRESS + + movl ip, #128 +102: ldm.w (r8 - r15), [r6]+ + stm.w (r8 - r15), [r7]+ + sub.a ip, ip, #1 + bne 102b + + ldw r1, [r1+], #PBE_NEXT + b 101b + + .p2align 4,,7 +109: + /* go back to the original page tables */ + ldw r0, =swapper_pg_dir + sub r0, r0, #PAGE_OFFSET + mov r5, #0 + movc p0.c6, r5, #6 + movc p0.c2, r0, #0 + nop + nop + nop + nop + nop + nop + nop + +#ifdef CONFIG_UNICORE_FPU_F64 + ldw ip, 1f + add ip, ip, #SWSUSP_FPSTATE + lfm.w (f0 - f7 ), [ip]+ + lfm.w (f8 - f15), [ip]+ + lfm.w (f16 - f23), [ip]+ + lfm.w (f24 - f31), [ip]+ + ldw r4, [ip] + ctf r4, s31 +#endif + mov r0, #0x0 + ldw ip, 1f + add ip, ip, #SWSUSP_CPU + ldm.w (r4 - r15), [ip]+ + ldm (r16 - r27, sp, pc), [ip]+ @ Load all regs saved previously + + .align 2 +1: .long swsusp_arch_regs_cpu0 + + +@ swsusp_arch_suspend() +@ - prepare pc for resume, return from function without swsusp_save on resume +@ - save registers in swsusp_arch_regs_cpu0 +@ - call swsusp_save write suspend image + +ENTRY(swsusp_arch_suspend) + ldw ip, 1f + add ip, ip, #SWSUSP_CPU + stm.w (r4 - r15), [ip]+ + stm.w (r16 - r27, sp, lr), [ip]+ + +#ifdef CONFIG_UNICORE_FPU_F64 + ldw ip, 1f + add ip, ip, #SWSUSP_FPSTATE + sfm.w (f0 - f7 ), [ip]+ + sfm.w (f8 - f15), [ip]+ + sfm.w (f16 - f23), [ip]+ + sfm.w (f24 - f31), [ip]+ + cff r4, s31 + stw r4, [ip] +#endif + b swsusp_save @ no return + +1: .long swsusp_arch_regs_cpu0 diff --git a/arch/unicore32/kernel/init_task.c b/arch/unicore32/kernel/init_task.c new file mode 100644 index 000000000000..a35a1e50e4f4 --- /dev/null +++ b/arch/unicore32/kernel/init_task.c @@ -0,0 +1,44 @@ +/* + * linux/arch/unicore32/kernel/init_task.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/mm.h> +#include <linux/module.h> +#include <linux/fs.h> +#include <linux/sched.h> +#include <linux/init.h> +#include <linux/init_task.h> +#include <linux/mqueue.h> +#include <linux/uaccess.h> + +#include <asm/pgtable.h> + +static struct signal_struct init_signals = INIT_SIGNALS(init_signals); +static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); +/* + * Initial thread structure. + * + * We need to make sure that this is 8192-byte aligned due to the + * way process stacks are handled. This is done by making sure + * the linker maps this in the .text segment right after head.S, + * and making head.S ensure the proper alignment. + * + * The things we do for performance.. + */ +union thread_union init_thread_union __init_task_data = { + INIT_THREAD_INFO(init_task) }; + +/* + * Initial task structure. + * + * All other task structs will be allocated on slabs in fork.c + */ +struct task_struct init_task = INIT_TASK(init_task); +EXPORT_SYMBOL(init_task); diff --git a/arch/unicore32/kernel/irq.c b/arch/unicore32/kernel/irq.c new file mode 100644 index 000000000000..b23624cf3062 --- /dev/null +++ b/arch/unicore32/kernel/irq.c @@ -0,0 +1,426 @@ +/* + * linux/arch/unicore32/kernel/irq.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/kernel_stat.h> +#include <linux/module.h> +#include <linux/signal.h> +#include <linux/ioport.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/random.h> +#include <linux/smp.h> +#include <linux/init.h> +#include <linux/seq_file.h> +#include <linux/errno.h> +#include <linux/list.h> +#include <linux/kallsyms.h> +#include <linux/proc_fs.h> +#include <linux/sysdev.h> +#include <linux/gpio.h> + +#include <asm/system.h> +#include <mach/hardware.h> + +#include "setup.h" + +/* + * PKUnity GPIO edge detection for IRQs: + * IRQs are generated on Falling-Edge, Rising-Edge, or both. + * Use this instead of directly setting GRER/GFER. + */ +static int GPIO_IRQ_rising_edge; +static int GPIO_IRQ_falling_edge; +static int GPIO_IRQ_mask = 0; + +#define GPIO_MASK(irq) (1 << (irq - IRQ_GPIO0)) + +static int puv3_gpio_type(struct irq_data *d, unsigned int type) +{ + unsigned int mask; + + if (d->irq < IRQ_GPIOHIGH) + mask = 1 << d->irq; + else + mask = GPIO_MASK(d->irq); + + if (type == IRQ_TYPE_PROBE) { + if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask) + return 0; + type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; + } + + if (type & IRQ_TYPE_EDGE_RISING) + GPIO_IRQ_rising_edge |= mask; + else + GPIO_IRQ_rising_edge &= ~mask; + if (type & IRQ_TYPE_EDGE_FALLING) + GPIO_IRQ_falling_edge |= mask; + else + GPIO_IRQ_falling_edge &= ~mask; + + writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER); + writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER); + + return 0; +} + +/* + * GPIO IRQs must be acknowledged. This is for IRQs from 0 to 7. + */ +static void puv3_low_gpio_ack(struct irq_data *d) +{ + writel((1 << d->irq), GPIO_GEDR); +} + +static void puv3_low_gpio_mask(struct irq_data *d) +{ + writel(readl(INTC_ICMR) & ~(1 << d->irq), INTC_ICMR); +} + +static void puv3_low_gpio_unmask(struct irq_data *d) +{ + writel(readl(INTC_ICMR) | (1 << d->irq), INTC_ICMR); +} + +static int puv3_low_gpio_wake(struct irq_data *d, unsigned int on) +{ + if (on) + writel(readl(PM_PWER) | (1 << d->irq), PM_PWER); + else + writel(readl(PM_PWER) & ~(1 << d->irq), PM_PWER); + return 0; +} + +static struct irq_chip puv3_low_gpio_chip = { + .name = "GPIO-low", + .irq_ack = puv3_low_gpio_ack, + .irq_mask = puv3_low_gpio_mask, + .irq_unmask = puv3_low_gpio_unmask, + .irq_set_type = puv3_gpio_type, + .irq_set_wake = puv3_low_gpio_wake, +}; + +/* + * IRQ8 (GPIO0 through 27) handler. We enter here with the + * irq_controller_lock held, and IRQs disabled. Decode the IRQ + * and call the handler. + */ +static void +puv3_gpio_handler(unsigned int irq, struct irq_desc *desc) +{ + unsigned int mask; + + mask = readl(GPIO_GEDR); + do { + /* + * clear down all currently active IRQ sources. + * We will be processing them all. + */ + writel(mask, GPIO_GEDR); + + irq = IRQ_GPIO0; + do { + if (mask & 1) + generic_handle_irq(irq); + mask >>= 1; + irq++; + } while (mask); + mask = readl(GPIO_GEDR); + } while (mask); +} + +/* + * GPIO0-27 edge IRQs need to be handled specially. + * In addition, the IRQs are all collected up into one bit in the + * interrupt controller registers. + */ +static void puv3_high_gpio_ack(struct irq_data *d) +{ + unsigned int mask = GPIO_MASK(d->irq); + + writel(mask, GPIO_GEDR); +} + +static void puv3_high_gpio_mask(struct irq_data *d) +{ + unsigned int mask = GPIO_MASK(d->irq); + + GPIO_IRQ_mask &= ~mask; + + writel(readl(GPIO_GRER) & ~mask, GPIO_GRER); + writel(readl(GPIO_GFER) & ~mask, GPIO_GFER); +} + +static void puv3_high_gpio_unmask(struct irq_data *d) +{ + unsigned int mask = GPIO_MASK(d->irq); + + GPIO_IRQ_mask |= mask; + + writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER); + writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER); +} + +static int puv3_high_gpio_wake(struct irq_data *d, unsigned int on) +{ + if (on) + writel(readl(PM_PWER) | PM_PWER_GPIOHIGH, PM_PWER); + else + writel(readl(PM_PWER) & ~PM_PWER_GPIOHIGH, PM_PWER); + return 0; +} + +static struct irq_chip puv3_high_gpio_chip = { + .name = "GPIO-high", + .irq_ack = puv3_high_gpio_ack, + .irq_mask = puv3_high_gpio_mask, + .irq_unmask = puv3_high_gpio_unmask, + .irq_set_type = puv3_gpio_type, + .irq_set_wake = puv3_high_gpio_wake, +}; + +/* + * We don't need to ACK IRQs on the PKUnity unless they're GPIOs + * this is for internal IRQs i.e. from 8 to 31. + */ +static void puv3_mask_irq(struct irq_data *d) +{ + writel(readl(INTC_ICMR) & ~(1 << d->irq), INTC_ICMR); +} + +static void puv3_unmask_irq(struct irq_data *d) +{ + writel(readl(INTC_ICMR) | (1 << d->irq), INTC_ICMR); +} + +/* + * Apart form GPIOs, only the RTC alarm can be a wakeup event. + */ +static int puv3_set_wake(struct irq_data *d, unsigned int on) +{ + if (d->irq == IRQ_RTCAlarm) { + if (on) + writel(readl(PM_PWER) | PM_PWER_RTC, PM_PWER); + else + writel(readl(PM_PWER) & ~PM_PWER_RTC, PM_PWER); + return 0; + } + return -EINVAL; +} + +static struct irq_chip puv3_normal_chip = { + .name = "PKUnity-v3", + .irq_ack = puv3_mask_irq, + .irq_mask = puv3_mask_irq, + .irq_unmask = puv3_unmask_irq, + .irq_set_wake = puv3_set_wake, +}; + +static struct resource irq_resource = { + .name = "irqs", + .start = io_v2p(PKUNITY_INTC_BASE), + .end = io_v2p(PKUNITY_INTC_BASE) + 0xFFFFF, +}; + +static struct puv3_irq_state { + unsigned int saved; + unsigned int icmr; + unsigned int iclr; + unsigned int iccr; +} puv3_irq_state; + +static int puv3_irq_suspend(struct sys_device *dev, pm_message_t state) +{ + struct puv3_irq_state *st = &puv3_irq_state; + + st->saved = 1; + st->icmr = readl(INTC_ICMR); + st->iclr = readl(INTC_ICLR); + st->iccr = readl(INTC_ICCR); + + /* + * Disable all GPIO-based interrupts. + */ + writel(readl(INTC_ICMR) & ~(0x1ff), INTC_ICMR); + + /* + * Set the appropriate edges for wakeup. + */ + writel(readl(PM_PWER) & GPIO_IRQ_rising_edge, GPIO_GRER); + writel(readl(PM_PWER) & GPIO_IRQ_falling_edge, GPIO_GFER); + + /* + * Clear any pending GPIO interrupts. + */ + writel(readl(GPIO_GEDR), GPIO_GEDR); + + return 0; +} + +static int puv3_irq_resume(struct sys_device *dev) +{ + struct puv3_irq_state *st = &puv3_irq_state; + + if (st->saved) { + writel(st->iccr, INTC_ICCR); + writel(st->iclr, INTC_ICLR); + + writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER); + writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER); + + writel(st->icmr, INTC_ICMR); + } + return 0; +} + +static struct sysdev_class puv3_irq_sysclass = { + .name = "pkunity-irq", + .suspend = puv3_irq_suspend, + .resume = puv3_irq_resume, +}; + +static struct sys_device puv3_irq_device = { + .id = 0, + .cls = &puv3_irq_sysclass, +}; + +static int __init puv3_irq_init_devicefs(void) +{ + sysdev_class_register(&puv3_irq_sysclass); + return sysdev_register(&puv3_irq_device); +} + +device_initcall(puv3_irq_init_devicefs); + +void __init init_IRQ(void) +{ + unsigned int irq; + + request_resource(&iomem_resource, &irq_resource); + + /* disable all IRQs */ + writel(0, INTC_ICMR); + + /* all IRQs are IRQ, not REAL */ + writel(0, INTC_ICLR); + + /* clear all GPIO edge detects */ + writel(FMASK(8, 0) & ~FIELD(1, 1, GPI_SOFF_REQ), GPIO_GPIR); + writel(0, GPIO_GFER); + writel(0, GPIO_GRER); + writel(0x0FFFFFFF, GPIO_GEDR); + + writel(1, INTC_ICCR); + + for (irq = 0; irq < IRQ_GPIOHIGH; irq++) { + set_irq_chip(irq, &puv3_low_gpio_chip); + set_irq_handler(irq, handle_edge_irq); + irq_modify_status(irq, + IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN, + 0); + } + + for (irq = IRQ_GPIOHIGH + 1; irq < IRQ_GPIO0; irq++) { + set_irq_chip(irq, &puv3_normal_chip); + set_irq_handler(irq, handle_level_irq); + irq_modify_status(irq, + IRQ_NOREQUEST | IRQ_NOAUTOEN, + IRQ_NOPROBE); + } + + for (irq = IRQ_GPIO0; irq <= IRQ_GPIO27; irq++) { + set_irq_chip(irq, &puv3_high_gpio_chip); + set_irq_handler(irq, handle_edge_irq); + irq_modify_status(irq, + IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN, + 0); + } + + /* + * Install handler for GPIO 0-27 edge detect interrupts + */ + set_irq_chip(IRQ_GPIOHIGH, &puv3_normal_chip); + set_irq_chained_handler(IRQ_GPIOHIGH, puv3_gpio_handler); + +#ifdef CONFIG_PUV3_GPIO + puv3_init_gpio(); +#endif +} + +int show_interrupts(struct seq_file *p, void *v) +{ + int i = *(loff_t *) v, cpu; + struct irq_desc *desc; + struct irqaction *action; + unsigned long flags; + + if (i == 0) { + char cpuname[12]; + + seq_printf(p, " "); + for_each_present_cpu(cpu) { + sprintf(cpuname, "CPU%d", cpu); + seq_printf(p, " %10s", cpuname); + } + seq_putc(p, '\n'); + } + + if (i < nr_irqs) { + desc = irq_to_desc(i); + raw_spin_lock_irqsave(&desc->lock, flags); + action = desc->action; + if (!action) + goto unlock; + + seq_printf(p, "%3d: ", i); + for_each_present_cpu(cpu) + seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu)); + seq_printf(p, " %10s", desc->irq_data.chip->name ? : "-"); + seq_printf(p, " %s", action->name); + for (action = action->next; action; action = action->next) + seq_printf(p, ", %s", action->name); + + seq_putc(p, '\n'); +unlock: + raw_spin_unlock_irqrestore(&desc->lock, flags); + } else if (i == nr_irqs) { + seq_printf(p, "Error in interrupt!\n"); + } + return 0; +} + +/* + * do_IRQ handles all hardware IRQ's. Decoded IRQs should not + * come via this function. Instead, they should provide their + * own 'handler' + */ +asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) +{ + struct pt_regs *old_regs = set_irq_regs(regs); + + irq_enter(); + + /* + * Some hardware gives randomly wrong interrupts. Rather + * than crashing, do something sensible. + */ + if (unlikely(irq >= nr_irqs)) { + if (printk_ratelimit()) + printk(KERN_WARNING "Bad IRQ%u\n", irq); + ack_bad_irq(irq); + } else { + generic_handle_irq(irq); + } + + irq_exit(); + set_irq_regs(old_regs); +} + diff --git a/arch/unicore32/kernel/ksyms.c b/arch/unicore32/kernel/ksyms.c new file mode 100644 index 000000000000..a8970809428a --- /dev/null +++ b/arch/unicore32/kernel/ksyms.c @@ -0,0 +1,99 @@ +/* + * linux/arch/unicore32/kernel/ksyms.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/module.h> +#include <linux/sched.h> +#include <linux/string.h> +#include <linux/cryptohash.h> +#include <linux/delay.h> +#include <linux/in6.h> +#include <linux/syscalls.h> +#include <linux/uaccess.h> +#include <linux/io.h> + +#include <asm/checksum.h> +#include <asm/system.h> + +#include "ksyms.h" + +EXPORT_SYMBOL(__uc32_find_next_zero_bit); +EXPORT_SYMBOL(__uc32_find_next_bit); + +EXPORT_SYMBOL(__backtrace); + + /* platform dependent support */ +EXPORT_SYMBOL(__udelay); +EXPORT_SYMBOL(__const_udelay); + + /* networking */ +EXPORT_SYMBOL(csum_partial); +EXPORT_SYMBOL(csum_partial_copy_from_user); +EXPORT_SYMBOL(csum_partial_copy_nocheck); +EXPORT_SYMBOL(__csum_ipv6_magic); + + /* io */ +#ifndef __raw_readsb +EXPORT_SYMBOL(__raw_readsb); +#endif +#ifndef __raw_readsw +EXPORT_SYMBOL(__raw_readsw); +#endif +#ifndef __raw_readsl +EXPORT_SYMBOL(__raw_readsl); +#endif +#ifndef __raw_writesb +EXPORT_SYMBOL(__raw_writesb); +#endif +#ifndef __raw_writesw +EXPORT_SYMBOL(__raw_writesw); +#endif +#ifndef __raw_writesl +EXPORT_SYMBOL(__raw_writesl); +#endif + + /* string / mem functions */ +EXPORT_SYMBOL(strchr); +EXPORT_SYMBOL(strrchr); +EXPORT_SYMBOL(memset); +EXPORT_SYMBOL(memcpy); +EXPORT_SYMBOL(memmove); +EXPORT_SYMBOL(memchr); + + /* user mem (segment) */ +EXPORT_SYMBOL(__strnlen_user); +EXPORT_SYMBOL(__strncpy_from_user); + +EXPORT_SYMBOL(copy_page); + +EXPORT_SYMBOL(__copy_from_user); +EXPORT_SYMBOL(__copy_to_user); +EXPORT_SYMBOL(__clear_user); + +EXPORT_SYMBOL(__get_user_1); +EXPORT_SYMBOL(__get_user_2); +EXPORT_SYMBOL(__get_user_4); + +EXPORT_SYMBOL(__put_user_1); +EXPORT_SYMBOL(__put_user_2); +EXPORT_SYMBOL(__put_user_4); +EXPORT_SYMBOL(__put_user_8); + +EXPORT_SYMBOL(__ashldi3); +EXPORT_SYMBOL(__ashrdi3); +EXPORT_SYMBOL(__divsi3); +EXPORT_SYMBOL(__lshrdi3); +EXPORT_SYMBOL(__modsi3); +EXPORT_SYMBOL(__muldi3); +EXPORT_SYMBOL(__ucmpdi2); +EXPORT_SYMBOL(__udivsi3); +EXPORT_SYMBOL(__umodsi3); +EXPORT_SYMBOL(__bswapsi2); + diff --git a/arch/unicore32/kernel/ksyms.h b/arch/unicore32/kernel/ksyms.h new file mode 100644 index 000000000000..185cdc712d03 --- /dev/null +++ b/arch/unicore32/kernel/ksyms.h @@ -0,0 +1,15 @@ +/* + * libgcc functions - functions that are used internally by the + * compiler... (prototypes are not correct though, but that + * doesn't really matter since they're not versioned). + */ +extern void __ashldi3(void); +extern void __ashrdi3(void); +extern void __divsi3(void); +extern void __lshrdi3(void); +extern void __modsi3(void); +extern void __muldi3(void); +extern void __ucmpdi2(void); +extern void __udivsi3(void); +extern void __umodsi3(void); +extern void __bswapsi2(void); diff --git a/arch/unicore32/kernel/module.c b/arch/unicore32/kernel/module.c new file mode 100644 index 000000000000..3e5a38d71a1e --- /dev/null +++ b/arch/unicore32/kernel/module.c @@ -0,0 +1,152 @@ +/* + * linux/arch/unicore32/kernel/module.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/module.h> +#include <linux/moduleloader.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/elf.h> +#include <linux/vmalloc.h> +#include <linux/fs.h> +#include <linux/string.h> +#include <linux/gfp.h> + +#include <asm/pgtable.h> +#include <asm/sections.h> + +void *module_alloc(unsigned long size) +{ + struct vm_struct *area; + + size = PAGE_ALIGN(size); + if (!size) + return NULL; + + area = __get_vm_area(size, VM_ALLOC, MODULES_VADDR, MODULES_END); + if (!area) + return NULL; + + return __vmalloc_area(area, GFP_KERNEL, PAGE_KERNEL_EXEC); +} + +void module_free(struct module *module, void *region) +{ + vfree(region); +} + +int module_frob_arch_sections(Elf_Ehdr *hdr, + Elf_Shdr *sechdrs, + char *secstrings, + struct module *mod) +{ + return 0; +} + +int +apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, + unsigned int relindex, struct module *module) +{ + Elf32_Shdr *symsec = sechdrs + symindex; + Elf32_Shdr *relsec = sechdrs + relindex; + Elf32_Shdr *dstsec = sechdrs + relsec->sh_info; + Elf32_Rel *rel = (void *)relsec->sh_addr; + unsigned int i; + + for (i = 0; i < relsec->sh_size / sizeof(Elf32_Rel); i++, rel++) { + unsigned long loc; + Elf32_Sym *sym; + s32 offset; + + offset = ELF32_R_SYM(rel->r_info); + if (offset < 0 || offset > + (symsec->sh_size / sizeof(Elf32_Sym))) { + printk(KERN_ERR "%s: bad relocation, " + "section %d reloc %d\n", + module->name, relindex, i); + return -ENOEXEC; + } + + sym = ((Elf32_Sym *)symsec->sh_addr) + offset; + + if (rel->r_offset < 0 || rel->r_offset > + dstsec->sh_size - sizeof(u32)) { + printk(KERN_ERR "%s: out of bounds relocation, " + "section %d reloc %d offset %d size %d\n", + module->name, relindex, i, rel->r_offset, + dstsec->sh_size); + return -ENOEXEC; + } + + loc = dstsec->sh_addr + rel->r_offset; + + switch (ELF32_R_TYPE(rel->r_info)) { + case R_UNICORE_NONE: + /* ignore */ + break; + + case R_UNICORE_ABS32: + *(u32 *)loc += sym->st_value; + break; + + case R_UNICORE_PC24: + case R_UNICORE_CALL: + case R_UNICORE_JUMP24: + offset = (*(u32 *)loc & 0x00ffffff) << 2; + if (offset & 0x02000000) + offset -= 0x04000000; + + offset += sym->st_value - loc; + if (offset & 3 || + offset <= (s32)0xfe000000 || + offset >= (s32)0x02000000) { + printk(KERN_ERR + "%s: relocation out of range, section " + "%d reloc %d sym '%s'\n", module->name, + relindex, i, strtab + sym->st_name); + return -ENOEXEC; + } + + offset >>= 2; + + *(u32 *)loc &= 0xff000000; + *(u32 *)loc |= offset & 0x00ffffff; + break; + + default: + printk(KERN_ERR "%s: unknown relocation: %u\n", + module->name, ELF32_R_TYPE(rel->r_info)); + return -ENOEXEC; + } + } + return 0; +} + +int +apply_relocate_add(Elf32_Shdr *sechdrs, const char *strtab, + unsigned int symindex, unsigned int relsec, + struct module *module) +{ + printk(KERN_ERR "module %s: ADD RELOCATION unsupported\n", + module->name); + return -ENOEXEC; +} + +int +module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs, + struct module *module) +{ + return 0; +} + +void +module_arch_cleanup(struct module *mod) +{ +} diff --git a/arch/unicore32/kernel/pci.c b/arch/unicore32/kernel/pci.c new file mode 100644 index 000000000000..100eab842e66 --- /dev/null +++ b/arch/unicore32/kernel/pci.c @@ -0,0 +1,404 @@ +/* + * linux/arch/unicore32/kernel/pci.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * PCI bios-type initialisation for PCI machines + * + */ +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/interrupt.h> +#include <linux/pci.h> +#include <linux/slab.h> +#include <linux/init.h> +#include <linux/io.h> + +static int debug_pci; +static int use_firmware; + +#define CONFIG_CMD(bus, devfn, where) \ + (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3)) + +static int +puv3_read_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 *value) +{ + writel(CONFIG_CMD(bus, devfn, where), PCICFG_ADDR); + switch (size) { + case 1: + *value = (readl(PCICFG_DATA) >> ((where & 3) * 8)) & 0xFF; + break; + case 2: + *value = (readl(PCICFG_DATA) >> ((where & 2) * 8)) & 0xFFFF; + break; + case 4: + *value = readl(PCICFG_DATA); + break; + } + return PCIBIOS_SUCCESSFUL; +} + +static int +puv3_write_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 value) +{ + writel(CONFIG_CMD(bus, devfn, where), PCICFG_ADDR); + switch (size) { + case 1: + writel((readl(PCICFG_DATA) & ~FMASK(8, (where&3)*8)) + | FIELD(value, 8, (where&3)*8), PCICFG_DATA); + break; + case 2: + writel((readl(PCICFG_DATA) & ~FMASK(16, (where&2)*8)) + | FIELD(value, 16, (where&2)*8), PCICFG_DATA); + break; + case 4: + writel(value, PCICFG_DATA); + break; + } + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops pci_puv3_ops = { + .read = puv3_read_config, + .write = puv3_write_config, +}; + +void pci_puv3_preinit(void) +{ + printk(KERN_DEBUG "PCI: PKUnity PCI Controller Initializing ...\n"); + /* config PCI bridge base */ + writel(io_v2p(PKUNITY_PCIBRI_BASE), PCICFG_BRIBASE); + + writel(0, PCIBRI_AHBCTL0); + writel(io_v2p(PKUNITY_PCIBRI_BASE) | PCIBRI_BARx_MEM, PCIBRI_AHBBAR0); + writel(0xFFFF0000, PCIBRI_AHBAMR0); + writel(0, PCIBRI_AHBTAR0); + + writel(PCIBRI_CTLx_AT, PCIBRI_AHBCTL1); + writel(io_v2p(PKUNITY_PCILIO_BASE) | PCIBRI_BARx_IO, PCIBRI_AHBBAR1); + writel(0xFFFF0000, PCIBRI_AHBAMR1); + writel(0x00000000, PCIBRI_AHBTAR1); + + writel(PCIBRI_CTLx_PREF, PCIBRI_AHBCTL2); + writel(io_v2p(PKUNITY_PCIMEM_BASE) | PCIBRI_BARx_MEM, PCIBRI_AHBBAR2); + writel(0xF8000000, PCIBRI_AHBAMR2); + writel(0, PCIBRI_AHBTAR2); + + writel(io_v2p(PKUNITY_PCIAHB_BASE) | PCIBRI_BARx_MEM, PCIBRI_BAR1); + + writel(PCIBRI_CTLx_AT | PCIBRI_CTLx_PREF, PCIBRI_PCICTL0); + writel(io_v2p(PKUNITY_PCIAHB_BASE) | PCIBRI_BARx_MEM, PCIBRI_PCIBAR0); + writel(0xF8000000, PCIBRI_PCIAMR0); + writel(PKUNITY_SDRAM_BASE, PCIBRI_PCITAR0); + + writel(readl(PCIBRI_CMD) | PCIBRI_CMD_IO | PCIBRI_CMD_MEM, PCIBRI_CMD); +} + +static int __init pci_puv3_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + if (dev->bus->number == 0) { +#ifdef CONFIG_ARCH_FPGA /* 4 pci slots */ + if (dev->devfn == 0x00) + return IRQ_PCIINTA; + else if (dev->devfn == 0x08) + return IRQ_PCIINTB; + else if (dev->devfn == 0x10) + return IRQ_PCIINTC; + else if (dev->devfn == 0x18) + return IRQ_PCIINTD; +#endif +#ifdef CONFIG_PUV3_DB0913 /* 3 pci slots */ + if (dev->devfn == 0x30) + return IRQ_PCIINTB; + else if (dev->devfn == 0x60) + return IRQ_PCIINTC; + else if (dev->devfn == 0x58) + return IRQ_PCIINTD; +#endif +#if defined(CONFIG_PUV3_NB0916) || defined(CONFIG_PUV3_SMW0919) + /* only support 2 pci devices */ + if (dev->devfn == 0x00) + return IRQ_PCIINTC; /* sata */ +#endif + } + return -1; +} + +/* + * Only first 128MB of memory can be accessed via PCI. + * We use GFP_DMA to allocate safe buffers to do map/unmap. + * This is really ugly and we need a better way of specifying + * DMA-capable regions of memory. + */ +void __init puv3_pci_adjust_zones(unsigned long *zone_size, + unsigned long *zhole_size) +{ + unsigned int sz = SZ_128M >> PAGE_SHIFT; + + /* + * Only adjust if > 128M on current system + */ + if (zone_size[0] <= sz) + return; + + zone_size[1] = zone_size[0] - sz; + zone_size[0] = sz; + zhole_size[1] = zhole_size[0]; + zhole_size[0] = 0; +} + +void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) +{ + if (debug_pci) + printk(KERN_DEBUG "PCI: Assigning IRQ %02d to %s\n", + irq, pci_name(dev)); + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); +} + +/* + * If the bus contains any of these devices, then we must not turn on + * parity checking of any kind. + */ +static inline int pdev_bad_for_parity(struct pci_dev *dev) +{ + return 0; +} + +/* + * pcibios_fixup_bus - Called after each bus is probed, + * but before its children are examined. + */ +void __devinit pcibios_fixup_bus(struct pci_bus *bus) +{ + struct pci_dev *dev; + u16 features = PCI_COMMAND_SERR + | PCI_COMMAND_PARITY + | PCI_COMMAND_FAST_BACK; + + bus->resource[0] = &ioport_resource; + bus->resource[1] = &iomem_resource; + + /* + * Walk the devices on this bus, working out what we can + * and can't support. + */ + list_for_each_entry(dev, &bus->devices, bus_list) { + u16 status; + + pci_read_config_word(dev, PCI_STATUS, &status); + + /* + * If any device on this bus does not support fast back + * to back transfers, then the bus as a whole is not able + * to support them. Having fast back to back transfers + * on saves us one PCI cycle per transaction. + */ + if (!(status & PCI_STATUS_FAST_BACK)) + features &= ~PCI_COMMAND_FAST_BACK; + + if (pdev_bad_for_parity(dev)) + features &= ~(PCI_COMMAND_SERR + | PCI_COMMAND_PARITY); + + switch (dev->class >> 8) { + case PCI_CLASS_BRIDGE_PCI: + pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status); + status |= PCI_BRIDGE_CTL_PARITY + | PCI_BRIDGE_CTL_MASTER_ABORT; + status &= ~(PCI_BRIDGE_CTL_BUS_RESET + | PCI_BRIDGE_CTL_FAST_BACK); + pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status); + break; + + case PCI_CLASS_BRIDGE_CARDBUS: + pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, + &status); + status |= PCI_CB_BRIDGE_CTL_PARITY + | PCI_CB_BRIDGE_CTL_MASTER_ABORT; + pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, + status); + break; + } + } + + /* + * Now walk the devices again, this time setting them up. + */ + list_for_each_entry(dev, &bus->devices, bus_list) { + u16 cmd; + + pci_read_config_word(dev, PCI_COMMAND, &cmd); + cmd |= features; + pci_write_config_word(dev, PCI_COMMAND, cmd); + + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, + L1_CACHE_BYTES >> 2); + } + + /* + * Propagate the flags to the PCI bridge. + */ + if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) { + if (features & PCI_COMMAND_FAST_BACK) + bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK; + if (features & PCI_COMMAND_PARITY) + bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY; + } + + /* + * Report what we did for this bus + */ + printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n", + bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis"); +} +#ifdef CONFIG_HOTPLUG +EXPORT_SYMBOL(pcibios_fixup_bus); +#endif + +static int __init pci_common_init(void) +{ + struct pci_bus *puv3_bus; + + pci_puv3_preinit(); + + puv3_bus = pci_scan_bus(0, &pci_puv3_ops, NULL); + + if (!puv3_bus) + panic("PCI: unable to scan bus!"); + + pci_fixup_irqs(pci_common_swizzle, pci_puv3_map_irq); + + if (!use_firmware) { + /* + * Size the bridge windows. + */ + pci_bus_size_bridges(puv3_bus); + + /* + * Assign resources. + */ + pci_bus_assign_resources(puv3_bus); + } + + /* + * Tell drivers about devices found. + */ + pci_bus_add_devices(puv3_bus); + + return 0; +} +subsys_initcall(pci_common_init); + +char * __devinit pcibios_setup(char *str) +{ + if (!strcmp(str, "debug")) { + debug_pci = 1; + return NULL; + } else if (!strcmp(str, "firmware")) { + use_firmware = 1; + return NULL; + } + return str; +} + +/* + * From arch/i386/kernel/pci-i386.c: + * + * We need to avoid collisions with `mirrored' VGA ports + * and other strange ISA hardware, so we always want the + * addresses to be allocated in the 0x000-0x0ff region + * modulo 0x400. + * + * Why? Because some silly external IO cards only decode + * the low 10 bits of the IO address. The 0x00-0xff region + * is reserved for motherboard devices that decode all 16 + * bits, so it's ok to allocate at, say, 0x2800-0x28ff, + * but we want to try to avoid allocating at 0x2900-0x2bff + * which might be mirrored at 0x0100-0x03ff.. + */ +resource_size_t pcibios_align_resource(void *data, const struct resource *res, + resource_size_t size, resource_size_t align) +{ + resource_size_t start = res->start; + + if (res->flags & IORESOURCE_IO && start & 0x300) + start = (start + 0x3ff) & ~0x3ff; + + start = (start + align - 1) & ~(align - 1); + + return start; +} + +/** + * pcibios_enable_device - Enable I/O and memory. + * @dev: PCI device to be enabled + */ +int pcibios_enable_device(struct pci_dev *dev, int mask) +{ + u16 cmd, old_cmd; + int idx; + struct resource *r; + + pci_read_config_word(dev, PCI_COMMAND, &cmd); + old_cmd = cmd; + for (idx = 0; idx < 6; idx++) { + /* Only set up the requested stuff */ + if (!(mask & (1 << idx))) + continue; + + r = dev->resource + idx; + if (!r->start && r->end) { + printk(KERN_ERR "PCI: Device %s not available because" + " of resource collisions\n", pci_name(dev)); + return -EINVAL; + } + if (r->flags & IORESOURCE_IO) + cmd |= PCI_COMMAND_IO; + if (r->flags & IORESOURCE_MEM) + cmd |= PCI_COMMAND_MEMORY; + } + + /* + * Bridges (eg, cardbus bridges) need to be fully enabled + */ + if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) + cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY; + + if (cmd != old_cmd) { + printk("PCI: enabling device %s (%04x -> %04x)\n", + pci_name(dev), old_cmd, cmd); + pci_write_config_word(dev, PCI_COMMAND, cmd); + } + return 0; +} + +int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, + enum pci_mmap_state mmap_state, int write_combine) +{ + unsigned long phys; + + if (mmap_state == pci_mmap_io) + return -EINVAL; + + phys = vma->vm_pgoff; + + /* + * Mark this as IO + */ + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + if (remap_pfn_range(vma, vma->vm_start, phys, + vma->vm_end - vma->vm_start, + vma->vm_page_prot)) + return -EAGAIN; + + return 0; +} diff --git a/arch/unicore32/kernel/pm.c b/arch/unicore32/kernel/pm.c new file mode 100644 index 000000000000..784bc2db3b28 --- /dev/null +++ b/arch/unicore32/kernel/pm.c @@ -0,0 +1,123 @@ +/* + * linux/arch/unicore32/kernel/pm.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn> + * Copyright (C) 2001-2010 Guan Xuetao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/init.h> +#include <linux/module.h> +#include <linux/suspend.h> +#include <linux/errno.h> +#include <linux/slab.h> +#include <linux/io.h> + +#include <mach/hardware.h> +#include <mach/pm.h> + +#include "setup.h" + +struct puv3_cpu_pm_fns *puv3_cpu_pm_fns; +static unsigned long *sleep_save; + +int puv3_pm_enter(suspend_state_t state) +{ + unsigned long sleep_save_checksum = 0, checksum = 0; + int i; + + /* skip registers saving for standby */ + if (state != PM_SUSPEND_STANDBY) { + puv3_cpu_pm_fns->save(sleep_save); + /* before sleeping, calculate and save a checksum */ + for (i = 0; i < puv3_cpu_pm_fns->save_count - 1; i++) + sleep_save_checksum += sleep_save[i]; + } + + /* *** go zzz *** */ + puv3_cpu_pm_fns->enter(state); + cpu_init(); +#ifdef CONFIG_INPUT_KEYBOARD + puv3_ps2_init(); +#endif +#ifdef CONFIG_PCI + pci_puv3_preinit(); +#endif + if (state != PM_SUSPEND_STANDBY) { + /* after sleeping, validate the checksum */ + for (i = 0; i < puv3_cpu_pm_fns->save_count - 1; i++) + checksum += sleep_save[i]; + + /* if invalid, display message and wait for a hardware reset */ + if (checksum != sleep_save_checksum) { + while (1) + puv3_cpu_pm_fns->enter(state); + } + puv3_cpu_pm_fns->restore(sleep_save); + } + + pr_debug("*** made it back from resume\n"); + + return 0; +} +EXPORT_SYMBOL_GPL(puv3_pm_enter); + +unsigned long sleep_phys_sp(void *sp) +{ + return virt_to_phys(sp); +} + +static int puv3_pm_valid(suspend_state_t state) +{ + if (puv3_cpu_pm_fns) + return puv3_cpu_pm_fns->valid(state); + + return -EINVAL; +} + +static int puv3_pm_prepare(void) +{ + int ret = 0; + + if (puv3_cpu_pm_fns && puv3_cpu_pm_fns->prepare) + ret = puv3_cpu_pm_fns->prepare(); + + return ret; +} + +static void puv3_pm_finish(void) +{ + if (puv3_cpu_pm_fns && puv3_cpu_pm_fns->finish) + puv3_cpu_pm_fns->finish(); +} + +static struct platform_suspend_ops puv3_pm_ops = { + .valid = puv3_pm_valid, + .enter = puv3_pm_enter, + .prepare = puv3_pm_prepare, + .finish = puv3_pm_finish, +}; + +static int __init puv3_pm_init(void) +{ + if (!puv3_cpu_pm_fns) { + printk(KERN_ERR "no valid puv3_cpu_pm_fns defined\n"); + return -EINVAL; + } + + sleep_save = kmalloc(puv3_cpu_pm_fns->save_count + * sizeof(unsigned long), GFP_KERNEL); + if (!sleep_save) { + printk(KERN_ERR "failed to alloc memory for pm save\n"); + return -ENOMEM; + } + + suspend_set_ops(&puv3_pm_ops); + return 0; +} + +device_initcall(puv3_pm_init); diff --git a/arch/unicore32/kernel/process.c b/arch/unicore32/kernel/process.c new file mode 100644 index 000000000000..ba401df971ed --- /dev/null +++ b/arch/unicore32/kernel/process.c @@ -0,0 +1,389 @@ +/* + * linux/arch/unicore32/kernel/process.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <stdarg.h> + +#include <linux/module.h> +#include <linux/sched.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/stddef.h> +#include <linux/unistd.h> +#include <linux/delay.h> +#include <linux/reboot.h> +#include <linux/interrupt.h> +#include <linux/kallsyms.h> +#include <linux/init.h> +#include <linux/cpu.h> +#include <linux/elfcore.h> +#include <linux/pm.h> +#include <linux/tick.h> +#include <linux/utsname.h> +#include <linux/uaccess.h> +#include <linux/random.h> +#include <linux/gpio.h> +#include <linux/stacktrace.h> + +#include <asm/cacheflush.h> +#include <asm/processor.h> +#include <asm/system.h> +#include <asm/stacktrace.h> + +#include "setup.h" + +static const char * const processor_modes[] = { + "UK00", "UK01", "UK02", "UK03", "UK04", "UK05", "UK06", "UK07", + "UK08", "UK09", "UK0A", "UK0B", "UK0C", "UK0D", "UK0E", "UK0F", + "USER", "REAL", "INTR", "PRIV", "UK14", "UK15", "UK16", "ABRT", + "UK18", "UK19", "UK1A", "EXTN", "UK1C", "UK1D", "UK1E", "SUSR" +}; + +/* + * The idle thread, has rather strange semantics for calling pm_idle, + * but this is what x86 does and we need to do the same, so that + * things like cpuidle get called in the same way. + */ +void cpu_idle(void) +{ + /* endless idle loop with no priority at all */ + while (1) { + tick_nohz_stop_sched_tick(1); + while (!need_resched()) { + local_irq_disable(); + stop_critical_timings(); + cpu_do_idle(); + local_irq_enable(); + start_critical_timings(); + } + tick_nohz_restart_sched_tick(); + preempt_enable_no_resched(); + schedule(); + preempt_disable(); + } +} + +static char reboot_mode = 'h'; + +int __init reboot_setup(char *str) +{ + reboot_mode = str[0]; + return 1; +} + +__setup("reboot=", reboot_setup); + +void machine_halt(void) +{ + gpio_set_value(GPO_SOFT_OFF, 0); +} + +/* + * Function pointers to optional machine specific functions + */ +void (*pm_power_off)(void) = NULL; + +void machine_power_off(void) +{ + if (pm_power_off) + pm_power_off(); + machine_halt(); +} + +void machine_restart(char *cmd) +{ + /* Disable interrupts first */ + local_irq_disable(); + + /* + * Tell the mm system that we are going to reboot - + * we may need it to insert some 1:1 mappings so that + * soft boot works. + */ + setup_mm_for_reboot(reboot_mode); + + /* Clean and invalidate caches */ + flush_cache_all(); + + /* Turn off caching */ + cpu_proc_fin(); + + /* Push out any further dirty data, and ensure cache is empty */ + flush_cache_all(); + + /* + * Now handle reboot code. + */ + if (reboot_mode == 's') { + /* Jump into ROM at address 0xffff0000 */ + cpu_reset(VECTORS_BASE); + } else { + writel(0x00002001, PM_PLLSYSCFG); /* cpu clk = 250M */ + writel(0x00100800, PM_PLLDDRCFG); /* ddr clk = 44M */ + writel(0x00002001, PM_PLLVGACFG); /* vga clk = 250M */ + + /* Use on-chip reset capability */ + /* following instructions must be in one icache line */ + __asm__ __volatile__( + " .align 5\n\t" + " stw %1, [%0]\n\t" + "201: ldw r0, [%0]\n\t" + " cmpsub.a r0, #0\n\t" + " bne 201b\n\t" + " stw %3, [%2]\n\t" + " nop; nop; nop\n\t" + /* prefetch 3 instructions at most */ + : + : "r" (PM_PMCR), + "r" (PM_PMCR_CFBSYS | PM_PMCR_CFBDDR + | PM_PMCR_CFBVGA), + "r" (RESETC_SWRR), + "r" (RESETC_SWRR_SRB) + : "r0", "memory"); + } + + /* + * Whoops - the architecture was unable to reboot. + * Tell the user! + */ + mdelay(1000); + printk(KERN_EMERG "Reboot failed -- System halted\n"); + do { } while (1); +} + +void __show_regs(struct pt_regs *regs) +{ + unsigned long flags; + char buf[64]; + + printk(KERN_DEFAULT "CPU: %d %s (%s %.*s)\n", + raw_smp_processor_id(), print_tainted(), + init_utsname()->release, + (int)strcspn(init_utsname()->version, " "), + init_utsname()->version); + print_symbol("PC is at %s\n", instruction_pointer(regs)); + print_symbol("LR is at %s\n", regs->UCreg_lr); + printk(KERN_DEFAULT "pc : [<%08lx>] lr : [<%08lx>] psr: %08lx\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + regs->UCreg_pc, regs->UCreg_lr, regs->UCreg_asr, + regs->UCreg_sp, regs->UCreg_ip, regs->UCreg_fp); + printk(KERN_DEFAULT "r26: %08lx r25: %08lx r24: %08lx\n", + regs->UCreg_26, regs->UCreg_25, + regs->UCreg_24); + printk(KERN_DEFAULT "r23: %08lx r22: %08lx r21: %08lx r20: %08lx\n", + regs->UCreg_23, regs->UCreg_22, + regs->UCreg_21, regs->UCreg_20); + printk(KERN_DEFAULT "r19: %08lx r18: %08lx r17: %08lx r16: %08lx\n", + regs->UCreg_19, regs->UCreg_18, + regs->UCreg_17, regs->UCreg_16); + printk(KERN_DEFAULT "r15: %08lx r14: %08lx r13: %08lx r12: %08lx\n", + regs->UCreg_15, regs->UCreg_14, + regs->UCreg_13, regs->UCreg_12); + printk(KERN_DEFAULT "r11: %08lx r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->UCreg_11, regs->UCreg_10, + regs->UCreg_09, regs->UCreg_08); + printk(KERN_DEFAULT "r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->UCreg_07, regs->UCreg_06, + regs->UCreg_05, regs->UCreg_04); + printk(KERN_DEFAULT "r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->UCreg_03, regs->UCreg_02, + regs->UCreg_01, regs->UCreg_00); + + flags = regs->UCreg_asr; + buf[0] = flags & PSR_S_BIT ? 'S' : 's'; + buf[1] = flags & PSR_Z_BIT ? 'Z' : 'z'; + buf[2] = flags & PSR_C_BIT ? 'C' : 'c'; + buf[3] = flags & PSR_V_BIT ? 'V' : 'v'; + buf[4] = '\0'; + + printk(KERN_DEFAULT "Flags: %s INTR o%s REAL o%s Mode %s Segment %s\n", + buf, interrupts_enabled(regs) ? "n" : "ff", + fast_interrupts_enabled(regs) ? "n" : "ff", + processor_modes[processor_mode(regs)], + segment_eq(get_fs(), get_ds()) ? "kernel" : "user"); + { + unsigned int ctrl; + + buf[0] = '\0'; + { + unsigned int transbase; + asm("movc %0, p0.c2, #0\n" + : "=r" (transbase)); + snprintf(buf, sizeof(buf), " Table: %08x", transbase); + } + asm("movc %0, p0.c1, #0\n" : "=r" (ctrl)); + + printk(KERN_DEFAULT "Control: %08x%s\n", ctrl, buf); + } +} + +void show_regs(struct pt_regs *regs) +{ + printk(KERN_DEFAULT "\n"); + printk(KERN_DEFAULT "Pid: %d, comm: %20s\n", + task_pid_nr(current), current->comm); + __show_regs(regs); + __backtrace(); +} + +/* + * Free current thread data structures etc.. + */ +void exit_thread(void) +{ +} + +void flush_thread(void) +{ + struct thread_info *thread = current_thread_info(); + struct task_struct *tsk = current; + + memset(thread->used_cp, 0, sizeof(thread->used_cp)); + memset(&tsk->thread.debug, 0, sizeof(struct debug_info)); +#ifdef CONFIG_UNICORE_FPU_F64 + memset(&thread->fpstate, 0, sizeof(struct fp_state)); +#endif +} + +void release_thread(struct task_struct *dead_task) +{ +} + +asmlinkage void ret_from_fork(void) __asm__("ret_from_fork"); + +int +copy_thread(unsigned long clone_flags, unsigned long stack_start, + unsigned long stk_sz, struct task_struct *p, struct pt_regs *regs) +{ + struct thread_info *thread = task_thread_info(p); + struct pt_regs *childregs = task_pt_regs(p); + + *childregs = *regs; + childregs->UCreg_00 = 0; + childregs->UCreg_sp = stack_start; + + memset(&thread->cpu_context, 0, sizeof(struct cpu_context_save)); + thread->cpu_context.sp = (unsigned long)childregs; + thread->cpu_context.pc = (unsigned long)ret_from_fork; + + if (clone_flags & CLONE_SETTLS) + childregs->UCreg_16 = regs->UCreg_03; + + return 0; +} + +/* + * Fill in the task's elfregs structure for a core dump. + */ +int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs) +{ + elf_core_copy_regs(elfregs, task_pt_regs(t)); + return 1; +} + +/* + * fill in the fpe structure for a core dump... + */ +int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fp) +{ + struct thread_info *thread = current_thread_info(); + int used_math = thread->used_cp[1] | thread->used_cp[2]; + +#ifdef CONFIG_UNICORE_FPU_F64 + if (used_math) + memcpy(fp, &thread->fpstate, sizeof(*fp)); +#endif + return used_math != 0; +} +EXPORT_SYMBOL(dump_fpu); + +/* + * Shuffle the argument into the correct register before calling the + * thread function. r1 is the thread argument, r2 is the pointer to + * the thread function, and r3 points to the exit function. + */ +asm(".pushsection .text\n" +" .align\n" +" .type kernel_thread_helper, #function\n" +"kernel_thread_helper:\n" +" mov.a asr, r7\n" +" mov r0, r4\n" +" mov lr, r6\n" +" mov pc, r5\n" +" .size kernel_thread_helper, . - kernel_thread_helper\n" +" .popsection"); + +/* + * Create a kernel thread. + */ +pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags) +{ + struct pt_regs regs; + + memset(®s, 0, sizeof(regs)); + + regs.UCreg_04 = (unsigned long)arg; + regs.UCreg_05 = (unsigned long)fn; + regs.UCreg_06 = (unsigned long)do_exit; + regs.UCreg_07 = PRIV_MODE; + regs.UCreg_pc = (unsigned long)kernel_thread_helper; + regs.UCreg_asr = regs.UCreg_07 | PSR_I_BIT; + + return do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, ®s, 0, NULL, NULL); +} +EXPORT_SYMBOL(kernel_thread); + +unsigned long get_wchan(struct task_struct *p) +{ + struct stackframe frame; + int count = 0; + if (!p || p == current || p->state == TASK_RUNNING) + return 0; + + frame.fp = thread_saved_fp(p); + frame.sp = thread_saved_sp(p); + frame.lr = 0; /* recovered from the stack */ + frame.pc = thread_saved_pc(p); + do { + int ret = unwind_frame(&frame); + if (ret < 0) + return 0; + if (!in_sched_functions(frame.pc)) + return frame.pc; + } while ((count++) < 16); + return 0; +} + +unsigned long arch_randomize_brk(struct mm_struct *mm) +{ + unsigned long range_end = mm->brk + 0x02000000; + return randomize_range(mm->brk, range_end, 0) ? : mm->brk; +} + +/* + * The vectors page is always readable from user space for the + * atomic helpers and the signal restart code. Let's declare a mapping + * for it so it is visible through ptrace and /proc/<pid>/mem. + */ + +int vectors_user_mapping(void) +{ + struct mm_struct *mm = current->mm; + return install_special_mapping(mm, 0xffff0000, PAGE_SIZE, + VM_READ | VM_EXEC | + VM_MAYREAD | VM_MAYEXEC | + VM_ALWAYSDUMP | VM_RESERVED, + NULL); +} + +const char *arch_vma_name(struct vm_area_struct *vma) +{ + return (vma->vm_start == 0xffff0000) ? "[vectors]" : NULL; +} diff --git a/arch/unicore32/kernel/ptrace.c b/arch/unicore32/kernel/ptrace.c new file mode 100644 index 000000000000..9f07c08da050 --- /dev/null +++ b/arch/unicore32/kernel/ptrace.c @@ -0,0 +1,149 @@ +/* + * linux/arch/unicore32/kernel/ptrace.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * By Ross Biro 1/23/92 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/ptrace.h> +#include <linux/signal.h> +#include <linux/uaccess.h> + +/* + * this routine will get a word off of the processes privileged stack. + * the offset is how far from the base addr as stored in the THREAD. + * this routine assumes that all the privileged stacks are in our + * data space. + */ +static inline long get_user_reg(struct task_struct *task, int offset) +{ + return task_pt_regs(task)->uregs[offset]; +} + +/* + * this routine will put a word on the processes privileged stack. + * the offset is how far from the base addr as stored in the THREAD. + * this routine assumes that all the privileged stacks are in our + * data space. + */ +static inline int +put_user_reg(struct task_struct *task, int offset, long data) +{ + struct pt_regs newregs, *regs = task_pt_regs(task); + int ret = -EINVAL; + + newregs = *regs; + newregs.uregs[offset] = data; + + if (valid_user_regs(&newregs)) { + regs->uregs[offset] = data; + ret = 0; + } + + return ret; +} + +/* + * Called by kernel/ptrace.c when detaching.. + */ +void ptrace_disable(struct task_struct *child) +{ +} + +/* + * We actually access the pt_regs stored on the kernel stack. + */ +static int ptrace_read_user(struct task_struct *tsk, unsigned long off, + unsigned long __user *ret) +{ + unsigned long tmp; + + tmp = 0; + if (off < sizeof(struct pt_regs)) + tmp = get_user_reg(tsk, off >> 2); + + return put_user(tmp, ret); +} + +/* + * We actually access the pt_regs stored on the kernel stack. + */ +static int ptrace_write_user(struct task_struct *tsk, unsigned long off, + unsigned long val) +{ + if (off >= sizeof(struct pt_regs)) + return 0; + + return put_user_reg(tsk, off >> 2, val); +} + +long arch_ptrace(struct task_struct *child, long request, + unsigned long addr, unsigned long data) +{ + int ret; + unsigned long __user *datap = (unsigned long __user *) data; + + switch (request) { + case PTRACE_PEEKUSR: + ret = ptrace_read_user(child, addr, datap); + break; + + case PTRACE_POKEUSR: + ret = ptrace_write_user(child, addr, data); + break; + + case PTRACE_GET_THREAD_AREA: + ret = put_user(task_pt_regs(child)->UCreg_16, + datap); + break; + + default: + ret = ptrace_request(child, request, addr, data); + break; + } + + return ret; +} + +asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno) +{ + unsigned long ip; + + if (!test_thread_flag(TIF_SYSCALL_TRACE)) + return scno; + if (!(current->ptrace & PT_PTRACED)) + return scno; + + /* + * Save IP. IP is used to denote syscall entry/exit: + * IP = 0 -> entry, = 1 -> exit + */ + ip = regs->UCreg_ip; + regs->UCreg_ip = why; + + current_thread_info()->syscall = scno; + + /* the 0x80 provides a way for the tracing parent to distinguish + between a syscall stop and SIGTRAP delivery */ + ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) + ? 0x80 : 0)); + /* + * this isn't the same as continuing with a signal, but it will do + * for normal use. strace only continues with a signal if the + * stopping signal is not SIGTRAP. -brl + */ + if (current->exit_code) { + send_sig(current->exit_code, current, 1); + current->exit_code = 0; + } + regs->UCreg_ip = ip; + + return current_thread_info()->syscall; +} diff --git a/arch/unicore32/kernel/puv3-core.c b/arch/unicore32/kernel/puv3-core.c new file mode 100644 index 000000000000..8b1b6beb858e --- /dev/null +++ b/arch/unicore32/kernel/puv3-core.c @@ -0,0 +1,285 @@ +/* + * linux/arch/unicore32/kernel/puv3-core.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn> + * Copyright (C) 2001-2010 Guan Xuetao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/device.h> +#include <linux/sysdev.h> +#include <linux/amba/bus.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/cnt32_to_63.h> +#include <linux/usb/musb.h> + +#include <asm/irq.h> +#include <mach/hardware.h> +#include <mach/pm.h> + +/* + * This is the PKUnity sched_clock implementation. This has + * a resolution of 271ns, and a maximum value of 32025597s (370 days). + * + * The return value is guaranteed to be monotonic in that range as + * long as there is always less than 582 seconds between successive + * calls to this function. + * + * ( * 1E9 / CLOCK_TICK_RATE ) -> about 2235/32 + */ +unsigned long long sched_clock(void) +{ + unsigned long long v = cnt32_to_63(readl(OST_OSCR)); + + /* original conservative method, but overflow frequently + * v *= NSEC_PER_SEC >> 12; + * do_div(v, CLOCK_TICK_RATE >> 12); + */ + v = ((v & 0x7fffffffffffffffULL) * 2235) >> 5; + + return v; +} + +static struct resource puv3_usb_resources[] = { + /* order is significant! */ + { + .start = io_v2p(PKUNITY_USB_BASE), + .end = io_v2p(PKUNITY_USB_BASE) + 0x3ff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_USB, + .flags = IORESOURCE_IRQ, + }, { + .start = IRQ_USB, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct musb_hdrc_config puv3_usb_config[] = { + { + .num_eps = 16, + .multipoint = 1, +#ifdef CONFIG_USB_INVENTRA_DMA + .dma = 1, + .dma_channels = 8, +#endif + }, +}; + +static struct musb_hdrc_platform_data puv3_usb_plat = { + .mode = MUSB_HOST, + .min_power = 100, + .clock = 0, + .config = puv3_usb_config, +}; + +static struct resource puv3_mmc_resources[] = { + [0] = { + .start = io_v2p(PKUNITY_SDC_BASE), + .end = io_v2p(PKUNITY_SDC_BASE) + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_SDC, + .end = IRQ_SDC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource puv3_unigfx_resources[] = { + [0] = { + .start = io_v2p(PKUNITY_UNIGFX_BASE), + .end = io_v2p(PKUNITY_UNIGFX_BASE) + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = PKUNITY_UNIGFX_MMAP_BASE, + .end = PKUNITY_UNIGFX_MMAP_BASE + PKUNITY_UNIGFX_MMAP_SIZE, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource puv3_rtc_resources[] = { + [0] = { + .start = io_v2p(PKUNITY_RTC_BASE), + .end = io_v2p(PKUNITY_RTC_BASE) + 0xff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_RTCAlarm, + .end = IRQ_RTCAlarm, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_RTC, + .end = IRQ_RTC, + .flags = IORESOURCE_IRQ + } +}; + +static struct resource puv3_pwm_resources[] = { + [0] = { + .start = io_v2p(PKUNITY_OST_BASE) + 0x80, + .end = io_v2p(PKUNITY_OST_BASE) + 0xff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource puv3_uart0_resources[] = { + [0] = { + .start = io_v2p(PKUNITY_UART0_BASE), + .end = io_v2p(PKUNITY_UART0_BASE) + 0xff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_UART0, + .end = IRQ_UART0, + .flags = IORESOURCE_IRQ + } +}; + +static struct resource puv3_uart1_resources[] = { + [0] = { + .start = io_v2p(PKUNITY_UART1_BASE), + .end = io_v2p(PKUNITY_UART1_BASE) + 0xff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_UART1, + .end = IRQ_UART1, + .flags = IORESOURCE_IRQ + } +}; + +static struct resource puv3_umal_resources[] = { + [0] = { + .start = io_v2p(PKUNITY_UMAL_BASE), + .end = io_v2p(PKUNITY_UMAL_BASE) + 0x1fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_UMAL, + .end = IRQ_UMAL, + .flags = IORESOURCE_IRQ + } +}; + +#ifdef CONFIG_PUV3_PM + +#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x +#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] + +/* + * List of global PXA peripheral registers to preserve. + * More ones like CP and general purpose register values are preserved + * with the stack pointer in sleep.S. + */ +enum { + SLEEP_SAVE_PM_PLLDDRCFG, + SLEEP_SAVE_COUNT +}; + + +static void puv3_cpu_pm_save(unsigned long *sleep_save) +{ +/* SAVE(PM_PLLDDRCFG); */ +} + +static void puv3_cpu_pm_restore(unsigned long *sleep_save) +{ +/* RESTORE(PM_PLLDDRCFG); */ +} + +static int puv3_cpu_pm_prepare(void) +{ + /* set resume return address */ + writel(virt_to_phys(puv3_cpu_resume), PM_DIVCFG); + return 0; +} + +static void puv3_cpu_pm_enter(suspend_state_t state) +{ + /* Clear reset status */ + writel(RESETC_RSSR_HWR | RESETC_RSSR_WDR + | RESETC_RSSR_SMR | RESETC_RSSR_SWR, RESETC_RSSR); + + switch (state) { +/* case PM_SUSPEND_ON: + puv3_cpu_idle(); + break; */ + case PM_SUSPEND_MEM: + puv3_cpu_pm_prepare(); + puv3_cpu_suspend(PM_PMCR_SFB); + break; + } +} + +static int puv3_cpu_pm_valid(suspend_state_t state) +{ + return state == PM_SUSPEND_MEM; +} + +static void puv3_cpu_pm_finish(void) +{ + /* ensure not to come back here if it wasn't intended */ + /* PSPR = 0; */ +} + +static struct puv3_cpu_pm_fns puv3_cpu_pm_fnss = { + .save_count = SLEEP_SAVE_COUNT, + .valid = puv3_cpu_pm_valid, + .save = puv3_cpu_pm_save, + .restore = puv3_cpu_pm_restore, + .enter = puv3_cpu_pm_enter, + .prepare = puv3_cpu_pm_prepare, + .finish = puv3_cpu_pm_finish, +}; + +static void __init puv3_init_pm(void) +{ + puv3_cpu_pm_fns = &puv3_cpu_pm_fnss; +} +#else +static inline void puv3_init_pm(void) {} +#endif + +void puv3_ps2_init(void) +{ + struct clk *bclk32; + + bclk32 = clk_get(NULL, "BUS32_CLK"); + writel(clk_get_rate(bclk32) / 200000, PS2_CNT); /* should > 5us */ +} + +void __init puv3_core_init(void) +{ + puv3_init_pm(); + puv3_ps2_init(); + + platform_device_register_simple("PKUnity-v3-RTC", -1, + puv3_rtc_resources, ARRAY_SIZE(puv3_rtc_resources)); + platform_device_register_simple("PKUnity-v3-UMAL", -1, + puv3_umal_resources, ARRAY_SIZE(puv3_umal_resources)); + platform_device_register_simple("PKUnity-v3-MMC", -1, + puv3_mmc_resources, ARRAY_SIZE(puv3_mmc_resources)); + platform_device_register_simple("PKUnity-v3-UNIGFX", -1, + puv3_unigfx_resources, ARRAY_SIZE(puv3_unigfx_resources)); + platform_device_register_simple("PKUnity-v3-PWM", -1, + puv3_pwm_resources, ARRAY_SIZE(puv3_pwm_resources)); + platform_device_register_simple("PKUnity-v3-UART", 0, + puv3_uart0_resources, ARRAY_SIZE(puv3_uart0_resources)); + platform_device_register_simple("PKUnity-v3-UART", 1, + puv3_uart1_resources, ARRAY_SIZE(puv3_uart1_resources)); + platform_device_register_simple("PKUnity-v3-AC97", -1, NULL, 0); + platform_device_register_resndata(&platform_bus, "musb_hdrc", -1, + puv3_usb_resources, ARRAY_SIZE(puv3_usb_resources), + &puv3_usb_plat, sizeof(puv3_usb_plat)); +} + diff --git a/arch/unicore32/kernel/puv3-nb0916.c b/arch/unicore32/kernel/puv3-nb0916.c new file mode 100644 index 000000000000..e731c561ed4e --- /dev/null +++ b/arch/unicore32/kernel/puv3-nb0916.c @@ -0,0 +1,145 @@ +/* + * linux/arch/unicore32/kernel/puv3-nb0916.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn> + * Copyright (C) 2001-2010 Guan Xuetao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/device.h> +#include <linux/sysdev.h> +#include <linux/platform_device.h> +#include <linux/mtd/physmap.h> +#include <linux/io.h> +#include <linux/reboot.h> +#include <linux/interrupt.h> +#include <linux/i2c.h> +#include <linux/pwm_backlight.h> +#include <linux/gpio.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> + +#include <mach/hardware.h> + +static struct physmap_flash_data physmap_flash_data = { + .width = 1, +}; + +static struct resource physmap_flash_resource = { + .start = 0xFFF80000, + .end = 0xFFFFFFFF, + .flags = IORESOURCE_MEM, +}; + +static struct resource puv3_i2c_resources[] = { + [0] = { + .start = io_v2p(PKUNITY_I2C_BASE), + .end = io_v2p(PKUNITY_I2C_BASE) + 0xff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_I2C, + .end = IRQ_I2C, + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_pwm_backlight_data nb0916_backlight_data = { + .pwm_id = 0, + .max_brightness = 100, + .dft_brightness = 100, + .pwm_period_ns = 70 * 1024, +}; + +static struct gpio_keys_button nb0916_gpio_keys[] = { + { + .type = EV_KEY, + .code = KEY_POWER, + .gpio = GPI_SOFF_REQ, + .desc = "Power Button", + .wakeup = 1, + .active_low = 1, + }, + { + .type = EV_KEY, + .code = BTN_TOUCH, + .gpio = GPI_BTN_TOUCH, + .desc = "Touchpad Button", + .wakeup = 1, + .active_low = 1, + }, +}; + +static struct gpio_keys_platform_data nb0916_gpio_button_data = { + .buttons = nb0916_gpio_keys, + .nbuttons = ARRAY_SIZE(nb0916_gpio_keys), +}; + +static irqreturn_t nb0916_lcdcaseoff_handler(int irq, void *dev_id) +{ + if (gpio_get_value(GPI_LCD_CASE_OFF)) + gpio_set_value(GPO_LCD_EN, 1); + else + gpio_set_value(GPO_LCD_EN, 0); + + return IRQ_HANDLED; +} + +static irqreturn_t nb0916_overheat_handler(int irq, void *dev_id) +{ + machine_halt(); + /* SYSTEM HALT, NO RETURN */ + return IRQ_HANDLED; +} + +static struct i2c_board_info __initdata puv3_i2c_devices[] = { + { I2C_BOARD_INFO("lm75", I2C_TAR_THERMAL), }, + { I2C_BOARD_INFO("bq27200", I2C_TAR_PWIC), }, + { I2C_BOARD_INFO("24c02", I2C_TAR_EEPROM), }, +}; + +int __init mach_nb0916_init(void) +{ + i2c_register_board_info(0, puv3_i2c_devices, + ARRAY_SIZE(puv3_i2c_devices)); + + platform_device_register_simple("PKUnity-v3-I2C", -1, + puv3_i2c_resources, ARRAY_SIZE(puv3_i2c_resources)); + + platform_device_register_data(&platform_bus, "pwm-backlight", -1, + &nb0916_backlight_data, sizeof(nb0916_backlight_data)); + + platform_device_register_data(&platform_bus, "gpio-keys", -1, + &nb0916_gpio_button_data, sizeof(nb0916_gpio_button_data)); + + platform_device_register_resndata(&platform_bus, "physmap-flash", -1, + &physmap_flash_resource, 1, + &physmap_flash_data, sizeof(physmap_flash_data)); + + if (request_irq(gpio_to_irq(GPI_LCD_CASE_OFF), + &nb0916_lcdcaseoff_handler, + IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, + "NB0916 lcd case off", NULL) < 0) { + + printk(KERN_DEBUG "LCD-Case-OFF IRQ %d not available\n", + gpio_to_irq(GPI_LCD_CASE_OFF)); + } + + if (request_irq(gpio_to_irq(GPI_OTP_INT), &nb0916_overheat_handler, + IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, + "NB0916 overheating protection", NULL) < 0) { + + printk(KERN_DEBUG "Overheating Protection IRQ %d not available\n", + gpio_to_irq(GPI_OTP_INT)); + } + + return 0; +} + +subsys_initcall_sync(mach_nb0916_init); diff --git a/arch/unicore32/kernel/pwm.c b/arch/unicore32/kernel/pwm.c new file mode 100644 index 000000000000..4615d51e3ba6 --- /dev/null +++ b/arch/unicore32/kernel/pwm.c @@ -0,0 +1,263 @@ +/* + * linux/arch/unicore32/kernel/pwm.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn> + * Copyright (C) 2001-2010 Guan Xuetao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/pwm.h> + +#include <asm/div64.h> +#include <mach/hardware.h> + +struct pwm_device { + struct list_head node; + struct platform_device *pdev; + + const char *label; + struct clk *clk; + int clk_enabled; + + unsigned int use_count; + unsigned int pwm_id; +}; + +/* + * period_ns = 10^9 * (PRESCALE + 1) * (PV + 1) / PWM_CLK_RATE + * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE + */ +int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) +{ + unsigned long long c; + unsigned long period_cycles, prescale, pv, dc; + + if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) + return -EINVAL; + + c = clk_get_rate(pwm->clk); + c = c * period_ns; + do_div(c, 1000000000); + period_cycles = c; + + if (period_cycles < 1) + period_cycles = 1; + prescale = (period_cycles - 1) / 1024; + pv = period_cycles / (prescale + 1) - 1; + + if (prescale > 63) + return -EINVAL; + + if (duty_ns == period_ns) + dc = OST_PWMDCCR_FDCYCLE; + else + dc = (pv + 1) * duty_ns / period_ns; + + /* NOTE: the clock to PWM has to be enabled first + * before writing to the registers + */ + clk_enable(pwm->clk); + OST_PWMPWCR = prescale; + OST_PWMDCCR = pv - dc; + OST_PWMPCR = pv; + clk_disable(pwm->clk); + + return 0; +} +EXPORT_SYMBOL(pwm_config); + +int pwm_enable(struct pwm_device *pwm) +{ + int rc = 0; + + if (!pwm->clk_enabled) { + rc = clk_enable(pwm->clk); + if (!rc) + pwm->clk_enabled = 1; + } + return rc; +} +EXPORT_SYMBOL(pwm_enable); + +void pwm_disable(struct pwm_device *pwm) +{ + if (pwm->clk_enabled) { + clk_disable(pwm->clk); + pwm->clk_enabled = 0; + } +} +EXPORT_SYMBOL(pwm_disable); + +static DEFINE_MUTEX(pwm_lock); +static LIST_HEAD(pwm_list); + +struct pwm_device *pwm_request(int pwm_id, const char *label) +{ + struct pwm_device *pwm; + int found = 0; + + mutex_lock(&pwm_lock); + + list_for_each_entry(pwm, &pwm_list, node) { + if (pwm->pwm_id == pwm_id) { + found = 1; + break; + } + } + + if (found) { + if (pwm->use_count == 0) { + pwm->use_count++; + pwm->label = label; + } else + pwm = ERR_PTR(-EBUSY); + } else + pwm = ERR_PTR(-ENOENT); + + mutex_unlock(&pwm_lock); + return pwm; +} +EXPORT_SYMBOL(pwm_request); + +void pwm_free(struct pwm_device *pwm) +{ + mutex_lock(&pwm_lock); + + if (pwm->use_count) { + pwm->use_count--; + pwm->label = NULL; + } else + pr_warning("PWM device already freed\n"); + + mutex_unlock(&pwm_lock); +} +EXPORT_SYMBOL(pwm_free); + +static inline void __add_pwm(struct pwm_device *pwm) +{ + mutex_lock(&pwm_lock); + list_add_tail(&pwm->node, &pwm_list); + mutex_unlock(&pwm_lock); +} + +static struct pwm_device *pwm_probe(struct platform_device *pdev, + unsigned int pwm_id, struct pwm_device *parent_pwm) +{ + struct pwm_device *pwm; + struct resource *r; + int ret = 0; + + pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); + if (pwm == NULL) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + return ERR_PTR(-ENOMEM); + } + + pwm->clk = clk_get(NULL, "OST_CLK"); + if (IS_ERR(pwm->clk)) { + ret = PTR_ERR(pwm->clk); + goto err_free; + } + pwm->clk_enabled = 0; + + pwm->use_count = 0; + pwm->pwm_id = pwm_id; + pwm->pdev = pdev; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (r == NULL) { + dev_err(&pdev->dev, "no memory resource defined\n"); + ret = -ENODEV; + goto err_free_clk; + } + + r = request_mem_region(r->start, resource_size(r), pdev->name); + if (r == NULL) { + dev_err(&pdev->dev, "failed to request memory resource\n"); + ret = -EBUSY; + goto err_free_clk; + } + + __add_pwm(pwm); + platform_set_drvdata(pdev, pwm); + return pwm; + +err_free_clk: + clk_put(pwm->clk); +err_free: + kfree(pwm); + return ERR_PTR(ret); +} + +static int __devinit puv3_pwm_probe(struct platform_device *pdev) +{ + struct pwm_device *pwm = pwm_probe(pdev, pdev->id, NULL); + + if (IS_ERR(pwm)) + return PTR_ERR(pwm); + + return 0; +} + +static int __devexit pwm_remove(struct platform_device *pdev) +{ + struct pwm_device *pwm; + struct resource *r; + + pwm = platform_get_drvdata(pdev); + if (pwm == NULL) + return -ENODEV; + + mutex_lock(&pwm_lock); + list_del(&pwm->node); + mutex_unlock(&pwm_lock); + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(r->start, resource_size(r)); + + clk_put(pwm->clk); + kfree(pwm); + return 0; +} + +static struct platform_driver puv3_pwm_driver = { + .driver = { + .name = "PKUnity-v3-PWM", + }, + .probe = puv3_pwm_probe, + .remove = __devexit_p(pwm_remove), +}; + +static int __init pwm_init(void) +{ + int ret = 0; + + ret = platform_driver_register(&puv3_pwm_driver); + if (ret) { + printk(KERN_ERR "failed to register puv3_pwm_driver\n"); + return ret; + } + + return ret; +} +arch_initcall(pwm_init); + +static void __exit pwm_exit(void) +{ + platform_driver_unregister(&puv3_pwm_driver); +} +module_exit(pwm_exit); + +MODULE_LICENSE("GPL v2"); diff --git a/arch/unicore32/kernel/rtc.c b/arch/unicore32/kernel/rtc.c new file mode 100644 index 000000000000..c5f068295b51 --- /dev/null +++ b/arch/unicore32/kernel/rtc.c @@ -0,0 +1,380 @@ +/* + * linux/arch/unicore32/kernel/rtc.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn> + * Copyright (C) 2001-2010 Guan Xuetao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/fs.h> +#include <linux/string.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/rtc.h> +#include <linux/bcd.h> +#include <linux/clk.h> +#include <linux/log2.h> +#include <linux/slab.h> +#include <linux/uaccess.h> +#include <linux/io.h> + +#include <asm/irq.h> +#include <mach/hardware.h> + +static struct resource *puv3_rtc_mem; + +static int puv3_rtc_alarmno = IRQ_RTCAlarm; +static int puv3_rtc_tickno = IRQ_RTC; + +static DEFINE_SPINLOCK(puv3_rtc_pie_lock); + +/* IRQ Handlers */ + +static irqreturn_t puv3_rtc_alarmirq(int irq, void *id) +{ + struct rtc_device *rdev = id; + + writel(readl(RTC_RTSR) | RTC_RTSR_AL, RTC_RTSR); + rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF); + return IRQ_HANDLED; +} + +static irqreturn_t puv3_rtc_tickirq(int irq, void *id) +{ + struct rtc_device *rdev = id; + + writel(readl(RTC_RTSR) | RTC_RTSR_HZ, RTC_RTSR); + rtc_update_irq(rdev, 1, RTC_PF | RTC_IRQF); + return IRQ_HANDLED; +} + +/* Update control registers */ +static void puv3_rtc_setaie(int to) +{ + unsigned int tmp; + + pr_debug("%s: aie=%d\n", __func__, to); + + tmp = readl(RTC_RTSR) & ~RTC_RTSR_ALE; + + if (to) + tmp |= RTC_RTSR_ALE; + + writel(tmp, RTC_RTSR); +} + +static int puv3_rtc_setpie(struct device *dev, int enabled) +{ + unsigned int tmp; + + pr_debug("%s: pie=%d\n", __func__, enabled); + + spin_lock_irq(&puv3_rtc_pie_lock); + tmp = readl(RTC_RTSR) & ~RTC_RTSR_HZE; + + if (enabled) + tmp |= RTC_RTSR_HZE; + + writel(tmp, RTC_RTSR); + spin_unlock_irq(&puv3_rtc_pie_lock); + + return 0; +} + +static int puv3_rtc_setfreq(struct device *dev, int freq) +{ + return 0; +} + +/* Time read/write */ + +static int puv3_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) +{ + rtc_time_to_tm(readl(RTC_RCNR), rtc_tm); + + pr_debug("read time %02x.%02x.%02x %02x/%02x/%02x\n", + rtc_tm->tm_year, rtc_tm->tm_mon, rtc_tm->tm_mday, + rtc_tm->tm_hour, rtc_tm->tm_min, rtc_tm->tm_sec); + + return 0; +} + +static int puv3_rtc_settime(struct device *dev, struct rtc_time *tm) +{ + unsigned long rtc_count = 0; + + pr_debug("set time %02d.%02d.%02d %02d/%02d/%02d\n", + tm->tm_year, tm->tm_mon, tm->tm_mday, + tm->tm_hour, tm->tm_min, tm->tm_sec); + + rtc_tm_to_time(tm, &rtc_count); + writel(rtc_count, RTC_RCNR); + + return 0; +} + +static int puv3_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct rtc_time *alm_tm = &alrm->time; + + rtc_time_to_tm(readl(RTC_RTAR), alm_tm); + + alrm->enabled = readl(RTC_RTSR) & RTC_RTSR_ALE; + + pr_debug("read alarm %02x %02x.%02x.%02x %02x/%02x/%02x\n", + alrm->enabled, + alm_tm->tm_year, alm_tm->tm_mon, alm_tm->tm_mday, + alm_tm->tm_hour, alm_tm->tm_min, alm_tm->tm_sec); + + return 0; +} + +static int puv3_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct rtc_time *tm = &alrm->time; + unsigned long rtcalarm_count = 0; + + pr_debug("puv3_rtc_setalarm: %d, %02x/%02x/%02x %02x.%02x.%02x\n", + alrm->enabled, + tm->tm_mday & 0xff, tm->tm_mon & 0xff, tm->tm_year & 0xff, + tm->tm_hour & 0xff, tm->tm_min & 0xff, tm->tm_sec); + + rtc_tm_to_time(tm, &rtcalarm_count); + writel(rtcalarm_count, RTC_RTAR); + + puv3_rtc_setaie(alrm->enabled); + + if (alrm->enabled) + enable_irq_wake(puv3_rtc_alarmno); + else + disable_irq_wake(puv3_rtc_alarmno); + + return 0; +} + +static int puv3_rtc_proc(struct device *dev, struct seq_file *seq) +{ + seq_printf(seq, "periodic_IRQ\t: %s\n", + (readl(RTC_RTSR) & RTC_RTSR_HZE) ? "yes" : "no"); + return 0; +} + +static int puv3_rtc_open(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct rtc_device *rtc_dev = platform_get_drvdata(pdev); + int ret; + + ret = request_irq(puv3_rtc_alarmno, puv3_rtc_alarmirq, + IRQF_DISABLED, "pkunity-rtc alarm", rtc_dev); + + if (ret) { + dev_err(dev, "IRQ%d error %d\n", puv3_rtc_alarmno, ret); + return ret; + } + + ret = request_irq(puv3_rtc_tickno, puv3_rtc_tickirq, + IRQF_DISABLED, "pkunity-rtc tick", rtc_dev); + + if (ret) { + dev_err(dev, "IRQ%d error %d\n", puv3_rtc_tickno, ret); + goto tick_err; + } + + return ret; + + tick_err: + free_irq(puv3_rtc_alarmno, rtc_dev); + return ret; +} + +static void puv3_rtc_release(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct rtc_device *rtc_dev = platform_get_drvdata(pdev); + + /* do not clear AIE here, it may be needed for wake */ + + puv3_rtc_setpie(dev, 0); + free_irq(puv3_rtc_alarmno, rtc_dev); + free_irq(puv3_rtc_tickno, rtc_dev); +} + +static const struct rtc_class_ops puv3_rtcops = { + .open = puv3_rtc_open, + .release = puv3_rtc_release, + .read_time = puv3_rtc_gettime, + .set_time = puv3_rtc_settime, + .read_alarm = puv3_rtc_getalarm, + .set_alarm = puv3_rtc_setalarm, + .irq_set_freq = puv3_rtc_setfreq, + .irq_set_state = puv3_rtc_setpie, + .proc = puv3_rtc_proc, +}; + +static void puv3_rtc_enable(struct platform_device *pdev, int en) +{ + if (!en) { + writel(readl(RTC_RTSR) & ~RTC_RTSR_HZE, RTC_RTSR); + } else { + /* re-enable the device, and check it is ok */ + + if ((readl(RTC_RTSR) & RTC_RTSR_HZE) == 0) { + dev_info(&pdev->dev, "rtc disabled, re-enabling\n"); + writel(readl(RTC_RTSR) | RTC_RTSR_HZE, RTC_RTSR); + } + } +} + +static int puv3_rtc_remove(struct platform_device *dev) +{ + struct rtc_device *rtc = platform_get_drvdata(dev); + + platform_set_drvdata(dev, NULL); + rtc_device_unregister(rtc); + + puv3_rtc_setpie(&dev->dev, 0); + puv3_rtc_setaie(0); + + release_resource(puv3_rtc_mem); + kfree(puv3_rtc_mem); + + return 0; +} + +static int puv3_rtc_probe(struct platform_device *pdev) +{ + struct rtc_device *rtc; + struct resource *res; + int ret; + + pr_debug("%s: probe=%p\n", __func__, pdev); + + /* find the IRQs */ + + puv3_rtc_tickno = platform_get_irq(pdev, 1); + if (puv3_rtc_tickno < 0) { + dev_err(&pdev->dev, "no irq for rtc tick\n"); + return -ENOENT; + } + + puv3_rtc_alarmno = platform_get_irq(pdev, 0); + if (puv3_rtc_alarmno < 0) { + dev_err(&pdev->dev, "no irq for alarm\n"); + return -ENOENT; + } + + pr_debug("PKUnity_rtc: tick irq %d, alarm irq %d\n", + puv3_rtc_tickno, puv3_rtc_alarmno); + + /* get the memory region */ + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "failed to get memory region resource\n"); + return -ENOENT; + } + + puv3_rtc_mem = request_mem_region(res->start, + res->end-res->start+1, + pdev->name); + + if (puv3_rtc_mem == NULL) { + dev_err(&pdev->dev, "failed to reserve memory region\n"); + ret = -ENOENT; + goto err_nores; + } + + puv3_rtc_enable(pdev, 1); + + puv3_rtc_setfreq(&pdev->dev, 1); + + /* register RTC and exit */ + + rtc = rtc_device_register("pkunity", &pdev->dev, &puv3_rtcops, + THIS_MODULE); + + if (IS_ERR(rtc)) { + dev_err(&pdev->dev, "cannot attach rtc\n"); + ret = PTR_ERR(rtc); + goto err_nortc; + } + + /* platform setup code should have handled this; sigh */ + if (!device_can_wakeup(&pdev->dev)) + device_init_wakeup(&pdev->dev, 1); + + platform_set_drvdata(pdev, rtc); + return 0; + + err_nortc: + puv3_rtc_enable(pdev, 0); + release_resource(puv3_rtc_mem); + + err_nores: + return ret; +} + +#ifdef CONFIG_PM + +/* RTC Power management control */ + +static int ticnt_save; + +static int puv3_rtc_suspend(struct platform_device *pdev, pm_message_t state) +{ + /* save RTAR for anyone using periodic interrupts */ + ticnt_save = readl(RTC_RTAR); + puv3_rtc_enable(pdev, 0); + return 0; +} + +static int puv3_rtc_resume(struct platform_device *pdev) +{ + puv3_rtc_enable(pdev, 1); + writel(ticnt_save, RTC_RTAR); + return 0; +} +#else +#define puv3_rtc_suspend NULL +#define puv3_rtc_resume NULL +#endif + +static struct platform_driver puv3_rtcdrv = { + .probe = puv3_rtc_probe, + .remove = __devexit_p(puv3_rtc_remove), + .suspend = puv3_rtc_suspend, + .resume = puv3_rtc_resume, + .driver = { + .name = "PKUnity-v3-RTC", + .owner = THIS_MODULE, + } +}; + +static char __initdata banner[] = "PKUnity-v3 RTC, (c) 2009 PKUnity Co.\n"; + +static int __init puv3_rtc_init(void) +{ + printk(banner); + return platform_driver_register(&puv3_rtcdrv); +} + +static void __exit puv3_rtc_exit(void) +{ + platform_driver_unregister(&puv3_rtcdrv); +} + +module_init(puv3_rtc_init); +module_exit(puv3_rtc_exit); + +MODULE_DESCRIPTION("RTC Driver for the PKUnity v3 chip"); +MODULE_AUTHOR("Hu Dongliang"); +MODULE_LICENSE("GPL v2"); + diff --git a/arch/unicore32/kernel/setup.c b/arch/unicore32/kernel/setup.c new file mode 100644 index 000000000000..1e175a82844d --- /dev/null +++ b/arch/unicore32/kernel/setup.c @@ -0,0 +1,360 @@ +/* + * linux/arch/unicore32/kernel/setup.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/stddef.h> +#include <linux/ioport.h> +#include <linux/delay.h> +#include <linux/utsname.h> +#include <linux/initrd.h> +#include <linux/console.h> +#include <linux/bootmem.h> +#include <linux/seq_file.h> +#include <linux/screen_info.h> +#include <linux/init.h> +#include <linux/root_dev.h> +#include <linux/cpu.h> +#include <linux/interrupt.h> +#include <linux/smp.h> +#include <linux/fs.h> +#include <linux/proc_fs.h> +#include <linux/memblock.h> +#include <linux/elf.h> +#include <linux/io.h> + +#include <asm/cputype.h> +#include <asm/sections.h> +#include <asm/setup.h> +#include <asm/cacheflush.h> +#include <asm/tlbflush.h> +#include <asm/traps.h> + +#include "setup.h" + +#ifndef MEM_SIZE +#define MEM_SIZE (16*1024*1024) +#endif + +struct stack { + u32 irq[3]; + u32 abt[3]; + u32 und[3]; +} ____cacheline_aligned; + +static struct stack stacks[NR_CPUS]; + +char elf_platform[ELF_PLATFORM_SIZE]; +EXPORT_SYMBOL(elf_platform); + +static char __initdata cmd_line[COMMAND_LINE_SIZE]; + +static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE; + +/* + * Standard memory resources + */ +static struct resource mem_res[] = { + { + .name = "Video RAM", + .start = 0, + .end = 0, + .flags = IORESOURCE_MEM + }, + { + .name = "Kernel text", + .start = 0, + .end = 0, + .flags = IORESOURCE_MEM + }, + { + .name = "Kernel data", + .start = 0, + .end = 0, + .flags = IORESOURCE_MEM + } +}; + +#define video_ram mem_res[0] +#define kernel_code mem_res[1] +#define kernel_data mem_res[2] + +/* + * These functions re-use the assembly code in head.S, which + * already provide the required functionality. + */ +static void __init setup_processor(void) +{ + printk(KERN_DEFAULT "CPU: UniCore-II [%08x] revision %d, cr=%08lx\n", + uc32_cpuid, (int)(uc32_cpuid >> 16) & 15, cr_alignment); + + sprintf(init_utsname()->machine, "puv3"); + sprintf(elf_platform, "ucv2"); +} + +/* + * cpu_init - initialise one CPU. + * + * cpu_init sets up the per-CPU stacks. + */ +void cpu_init(void) +{ + unsigned int cpu = smp_processor_id(); + struct stack *stk = &stacks[cpu]; + + /* + * setup stacks for re-entrant exception handlers + */ + __asm__ ( + "mov.a asr, %1\n\t" + "add sp, %0, %2\n\t" + "mov.a asr, %3\n\t" + "add sp, %0, %4\n\t" + "mov.a asr, %5\n\t" + "add sp, %0, %6\n\t" + "mov.a asr, %7" + : + : "r" (stk), + "r" (PSR_R_BIT | PSR_I_BIT | INTR_MODE), + "I" (offsetof(struct stack, irq[0])), + "r" (PSR_R_BIT | PSR_I_BIT | ABRT_MODE), + "I" (offsetof(struct stack, abt[0])), + "r" (PSR_R_BIT | PSR_I_BIT | EXTN_MODE), + "I" (offsetof(struct stack, und[0])), + "r" (PSR_R_BIT | PSR_I_BIT | PRIV_MODE) + : "r30", "cc"); +} + +static int __init uc32_add_memory(unsigned long start, unsigned long size) +{ + struct membank *bank = &meminfo.bank[meminfo.nr_banks]; + + if (meminfo.nr_banks >= NR_BANKS) { + printk(KERN_CRIT "NR_BANKS too low, " + "ignoring memory at %#lx\n", start); + return -EINVAL; + } + + /* + * Ensure that start/size are aligned to a page boundary. + * Size is appropriately rounded down, start is rounded up. + */ + size -= start & ~PAGE_MASK; + + bank->start = PAGE_ALIGN(start); + bank->size = size & PAGE_MASK; + + /* + * Check whether this memory region has non-zero size or + * invalid node number. + */ + if (bank->size == 0) + return -EINVAL; + + meminfo.nr_banks++; + return 0; +} + +/* + * Pick out the memory size. We look for mem=size@start, + * where start and size are "size[KkMm]" + */ +static int __init early_mem(char *p) +{ + static int usermem __initdata = 1; + unsigned long size, start; + char *endp; + + /* + * If the user specifies memory size, we + * blow away any automatically generated + * size. + */ + if (usermem) { + usermem = 0; + meminfo.nr_banks = 0; + } + + start = PHYS_OFFSET; + size = memparse(p, &endp); + if (*endp == '@') + start = memparse(endp + 1, NULL); + + uc32_add_memory(start, size); + + return 0; +} +early_param("mem", early_mem); + +static void __init +request_standard_resources(struct meminfo *mi) +{ + struct resource *res; + int i; + + kernel_code.start = virt_to_phys(_stext); + kernel_code.end = virt_to_phys(_etext - 1); + kernel_data.start = virt_to_phys(_sdata); + kernel_data.end = virt_to_phys(_end - 1); + + for (i = 0; i < mi->nr_banks; i++) { + if (mi->bank[i].size == 0) + continue; + + res = alloc_bootmem_low(sizeof(*res)); + res->name = "System RAM"; + res->start = mi->bank[i].start; + res->end = mi->bank[i].start + mi->bank[i].size - 1; + res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; + + request_resource(&iomem_resource, res); + + if (kernel_code.start >= res->start && + kernel_code.end <= res->end) + request_resource(res, &kernel_code); + if (kernel_data.start >= res->start && + kernel_data.end <= res->end) + request_resource(res, &kernel_data); + } + + video_ram.start = PKUNITY_UNIGFX_MMAP_BASE; + video_ram.end = PKUNITY_UNIGFX_MMAP_BASE + PKUNITY_UNIGFX_MMAP_SIZE; + request_resource(&iomem_resource, &video_ram); +} + +static void (*init_machine)(void) __initdata; + +static int __init customize_machine(void) +{ + /* customizes platform devices, or adds new ones */ + if (init_machine) + init_machine(); + return 0; +} +arch_initcall(customize_machine); + +void __init setup_arch(char **cmdline_p) +{ + char *from = default_command_line; + + setup_processor(); + + init_mm.start_code = (unsigned long) _stext; + init_mm.end_code = (unsigned long) _etext; + init_mm.end_data = (unsigned long) _edata; + init_mm.brk = (unsigned long) _end; + + /* parse_early_param needs a boot_command_line */ + strlcpy(boot_command_line, from, COMMAND_LINE_SIZE); + + /* populate cmd_line too for later use, preserving boot_command_line */ + strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE); + *cmdline_p = cmd_line; + + parse_early_param(); + + uc32_memblock_init(&meminfo); + + paging_init(); + request_standard_resources(&meminfo); + + cpu_init(); + + /* + * Set up various architecture-specific pointers + */ + init_machine = puv3_core_init; + +#ifdef CONFIG_VT +#if defined(CONFIG_VGA_CONSOLE) + conswitchp = &vga_con; +#elif defined(CONFIG_DUMMY_CONSOLE) + conswitchp = &dummy_con; +#endif +#endif + early_trap_init(); +} + +static struct cpu cpuinfo_unicore; + +static int __init topology_init(void) +{ + int i; + + for_each_possible_cpu(i) + register_cpu(&cpuinfo_unicore, i); + + return 0; +} +subsys_initcall(topology_init); + +#ifdef CONFIG_HAVE_PROC_CPU +static int __init proc_cpu_init(void) +{ + struct proc_dir_entry *res; + + res = proc_mkdir("cpu", NULL); + if (!res) + return -ENOMEM; + return 0; +} +fs_initcall(proc_cpu_init); +#endif + +static int c_show(struct seq_file *m, void *v) +{ + seq_printf(m, "Processor\t: UniCore-II rev %d (%s)\n", + (int)(uc32_cpuid >> 16) & 15, elf_platform); + + seq_printf(m, "BogoMIPS\t: %lu.%02lu\n", + loops_per_jiffy / (500000/HZ), + (loops_per_jiffy / (5000/HZ)) % 100); + + /* dump out the processor features */ + seq_puts(m, "Features\t: CMOV UC-F64"); + + seq_printf(m, "\nCPU implementer\t: 0x%02x\n", uc32_cpuid >> 24); + seq_printf(m, "CPU architecture: 2\n"); + seq_printf(m, "CPU revision\t: %d\n", (uc32_cpuid >> 16) & 15); + + seq_printf(m, "Cache type\t: write-back\n" + "Cache clean\t: cp0 c5 ops\n" + "Cache lockdown\t: not support\n" + "Cache format\t: Harvard\n"); + + seq_puts(m, "\n"); + + seq_printf(m, "Hardware\t: PKUnity v3\n"); + + return 0; +} + +static void *c_start(struct seq_file *m, loff_t *pos) +{ + return *pos < 1 ? (void *)1 : NULL; +} + +static void *c_next(struct seq_file *m, void *v, loff_t *pos) +{ + ++*pos; + return NULL; +} + +static void c_stop(struct seq_file *m, void *v) +{ +} + +const struct seq_operations cpuinfo_op = { + .start = c_start, + .next = c_next, + .stop = c_stop, + .show = c_show +}; diff --git a/arch/unicore32/kernel/setup.h b/arch/unicore32/kernel/setup.h new file mode 100644 index 000000000000..dcd1306eb5c6 --- /dev/null +++ b/arch/unicore32/kernel/setup.h @@ -0,0 +1,30 @@ +/* + * linux/arch/unicore32/kernel/setup.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __UNICORE_KERNEL_SETUP_H__ +#define __UNICORE_KERNEL_SETUP_H__ + +extern void paging_init(void); +extern void puv3_core_init(void); + +extern void puv3_ps2_init(void); +extern void pci_puv3_preinit(void); +extern void __init puv3_init_gpio(void); + +extern void setup_mm_for_reboot(char mode); + +extern char __stubs_start[], __stubs_end[]; +extern char __vectors_start[], __vectors_end[]; + +extern void kernel_thread_helper(void); + +extern void __init early_signal_init(void); +#endif diff --git a/arch/unicore32/kernel/signal.c b/arch/unicore32/kernel/signal.c new file mode 100644 index 000000000000..b163fca56789 --- /dev/null +++ b/arch/unicore32/kernel/signal.c @@ -0,0 +1,494 @@ +/* + * linux/arch/unicore32/kernel/signal.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/errno.h> +#include <linux/signal.h> +#include <linux/personality.h> +#include <linux/freezer.h> +#include <linux/uaccess.h> +#include <linux/tracehook.h> +#include <linux/elf.h> +#include <linux/unistd.h> + +#include <asm/cacheflush.h> +#include <asm/ucontext.h> + +#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) + +/* + * For UniCore syscalls, we encode the syscall number into the instruction. + */ +#define SWI_SYS_SIGRETURN (0xff000000) /* error number for new abi */ +#define SWI_SYS_RT_SIGRETURN (0xff000000 | (__NR_rt_sigreturn)) +#define SWI_SYS_RESTART (0xff000000 | (__NR_restart_syscall)) + +#define KERN_SIGRETURN_CODE (KUSER_VECPAGE_BASE + 0x00000500) +#define KERN_RESTART_CODE (KERN_SIGRETURN_CODE + sizeof(sigreturn_codes)) + +const unsigned long sigreturn_codes[3] = { + SWI_SYS_SIGRETURN, SWI_SYS_RT_SIGRETURN, +}; + +const unsigned long syscall_restart_code[2] = { + SWI_SYS_RESTART, /* swi __NR_restart_syscall */ + 0x69efc004, /* ldr pc, [sp], #4 */ +}; + +/* + * Do a signal return; undo the signal stack. These are aligned to 64-bit. + */ +struct sigframe { + struct ucontext uc; + unsigned long retcode[2]; +}; + +struct rt_sigframe { + struct siginfo info; + struct sigframe sig; +}; + +static int restore_sigframe(struct pt_regs *regs, struct sigframe __user *sf) +{ + sigset_t set; + int err; + + err = __copy_from_user(&set, &sf->uc.uc_sigmask, sizeof(set)); + if (err == 0) { + sigdelsetmask(&set, ~_BLOCKABLE); + spin_lock_irq(¤t->sighand->siglock); + current->blocked = set; + recalc_sigpending(); + spin_unlock_irq(¤t->sighand->siglock); + } + + err |= __get_user(regs->UCreg_00, &sf->uc.uc_mcontext.regs.UCreg_00); + err |= __get_user(regs->UCreg_01, &sf->uc.uc_mcontext.regs.UCreg_01); + err |= __get_user(regs->UCreg_02, &sf->uc.uc_mcontext.regs.UCreg_02); + err |= __get_user(regs->UCreg_03, &sf->uc.uc_mcontext.regs.UCreg_03); + err |= __get_user(regs->UCreg_04, &sf->uc.uc_mcontext.regs.UCreg_04); + err |= __get_user(regs->UCreg_05, &sf->uc.uc_mcontext.regs.UCreg_05); + err |= __get_user(regs->UCreg_06, &sf->uc.uc_mcontext.regs.UCreg_06); + err |= __get_user(regs->UCreg_07, &sf->uc.uc_mcontext.regs.UCreg_07); + err |= __get_user(regs->UCreg_08, &sf->uc.uc_mcontext.regs.UCreg_08); + err |= __get_user(regs->UCreg_09, &sf->uc.uc_mcontext.regs.UCreg_09); + err |= __get_user(regs->UCreg_10, &sf->uc.uc_mcontext.regs.UCreg_10); + err |= __get_user(regs->UCreg_11, &sf->uc.uc_mcontext.regs.UCreg_11); + err |= __get_user(regs->UCreg_12, &sf->uc.uc_mcontext.regs.UCreg_12); + err |= __get_user(regs->UCreg_13, &sf->uc.uc_mcontext.regs.UCreg_13); + err |= __get_user(regs->UCreg_14, &sf->uc.uc_mcontext.regs.UCreg_14); + err |= __get_user(regs->UCreg_15, &sf->uc.uc_mcontext.regs.UCreg_15); + err |= __get_user(regs->UCreg_16, &sf->uc.uc_mcontext.regs.UCreg_16); + err |= __get_user(regs->UCreg_17, &sf->uc.uc_mcontext.regs.UCreg_17); + err |= __get_user(regs->UCreg_18, &sf->uc.uc_mcontext.regs.UCreg_18); + err |= __get_user(regs->UCreg_19, &sf->uc.uc_mcontext.regs.UCreg_19); + err |= __get_user(regs->UCreg_20, &sf->uc.uc_mcontext.regs.UCreg_20); + err |= __get_user(regs->UCreg_21, &sf->uc.uc_mcontext.regs.UCreg_21); + err |= __get_user(regs->UCreg_22, &sf->uc.uc_mcontext.regs.UCreg_22); + err |= __get_user(regs->UCreg_23, &sf->uc.uc_mcontext.regs.UCreg_23); + err |= __get_user(regs->UCreg_24, &sf->uc.uc_mcontext.regs.UCreg_24); + err |= __get_user(regs->UCreg_25, &sf->uc.uc_mcontext.regs.UCreg_25); + err |= __get_user(regs->UCreg_26, &sf->uc.uc_mcontext.regs.UCreg_26); + err |= __get_user(regs->UCreg_fp, &sf->uc.uc_mcontext.regs.UCreg_fp); + err |= __get_user(regs->UCreg_ip, &sf->uc.uc_mcontext.regs.UCreg_ip); + err |= __get_user(regs->UCreg_sp, &sf->uc.uc_mcontext.regs.UCreg_sp); + err |= __get_user(regs->UCreg_lr, &sf->uc.uc_mcontext.regs.UCreg_lr); + err |= __get_user(regs->UCreg_pc, &sf->uc.uc_mcontext.regs.UCreg_pc); + err |= __get_user(regs->UCreg_asr, &sf->uc.uc_mcontext.regs.UCreg_asr); + + err |= !valid_user_regs(regs); + + return err; +} + +asmlinkage int __sys_rt_sigreturn(struct pt_regs *regs) +{ + struct rt_sigframe __user *frame; + + /* Always make any pending restarted system calls return -EINTR */ + current_thread_info()->restart_block.fn = do_no_restart_syscall; + + /* + * Since we stacked the signal on a 64-bit boundary, + * then 'sp' should be word aligned here. If it's + * not, then the user is trying to mess with us. + */ + if (regs->UCreg_sp & 7) + goto badframe; + + frame = (struct rt_sigframe __user *)regs->UCreg_sp; + + if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) + goto badframe; + + if (restore_sigframe(regs, &frame->sig)) + goto badframe; + + if (do_sigaltstack(&frame->sig.uc.uc_stack, NULL, regs->UCreg_sp) + == -EFAULT) + goto badframe; + + return regs->UCreg_00; + +badframe: + force_sig(SIGSEGV, current); + return 0; +} + +static int setup_sigframe(struct sigframe __user *sf, struct pt_regs *regs, + sigset_t *set) +{ + int err = 0; + + err |= __put_user(regs->UCreg_00, &sf->uc.uc_mcontext.regs.UCreg_00); + err |= __put_user(regs->UCreg_01, &sf->uc.uc_mcontext.regs.UCreg_01); + err |= __put_user(regs->UCreg_02, &sf->uc.uc_mcontext.regs.UCreg_02); + err |= __put_user(regs->UCreg_03, &sf->uc.uc_mcontext.regs.UCreg_03); + err |= __put_user(regs->UCreg_04, &sf->uc.uc_mcontext.regs.UCreg_04); + err |= __put_user(regs->UCreg_05, &sf->uc.uc_mcontext.regs.UCreg_05); + err |= __put_user(regs->UCreg_06, &sf->uc.uc_mcontext.regs.UCreg_06); + err |= __put_user(regs->UCreg_07, &sf->uc.uc_mcontext.regs.UCreg_07); + err |= __put_user(regs->UCreg_08, &sf->uc.uc_mcontext.regs.UCreg_08); + err |= __put_user(regs->UCreg_09, &sf->uc.uc_mcontext.regs.UCreg_09); + err |= __put_user(regs->UCreg_10, &sf->uc.uc_mcontext.regs.UCreg_10); + err |= __put_user(regs->UCreg_11, &sf->uc.uc_mcontext.regs.UCreg_11); + err |= __put_user(regs->UCreg_12, &sf->uc.uc_mcontext.regs.UCreg_12); + err |= __put_user(regs->UCreg_13, &sf->uc.uc_mcontext.regs.UCreg_13); + err |= __put_user(regs->UCreg_14, &sf->uc.uc_mcontext.regs.UCreg_14); + err |= __put_user(regs->UCreg_15, &sf->uc.uc_mcontext.regs.UCreg_15); + err |= __put_user(regs->UCreg_16, &sf->uc.uc_mcontext.regs.UCreg_16); + err |= __put_user(regs->UCreg_17, &sf->uc.uc_mcontext.regs.UCreg_17); + err |= __put_user(regs->UCreg_18, &sf->uc.uc_mcontext.regs.UCreg_18); + err |= __put_user(regs->UCreg_19, &sf->uc.uc_mcontext.regs.UCreg_19); + err |= __put_user(regs->UCreg_20, &sf->uc.uc_mcontext.regs.UCreg_20); + err |= __put_user(regs->UCreg_21, &sf->uc.uc_mcontext.regs.UCreg_21); + err |= __put_user(regs->UCreg_22, &sf->uc.uc_mcontext.regs.UCreg_22); + err |= __put_user(regs->UCreg_23, &sf->uc.uc_mcontext.regs.UCreg_23); + err |= __put_user(regs->UCreg_24, &sf->uc.uc_mcontext.regs.UCreg_24); + err |= __put_user(regs->UCreg_25, &sf->uc.uc_mcontext.regs.UCreg_25); + err |= __put_user(regs->UCreg_26, &sf->uc.uc_mcontext.regs.UCreg_26); + err |= __put_user(regs->UCreg_fp, &sf->uc.uc_mcontext.regs.UCreg_fp); + err |= __put_user(regs->UCreg_ip, &sf->uc.uc_mcontext.regs.UCreg_ip); + err |= __put_user(regs->UCreg_sp, &sf->uc.uc_mcontext.regs.UCreg_sp); + err |= __put_user(regs->UCreg_lr, &sf->uc.uc_mcontext.regs.UCreg_lr); + err |= __put_user(regs->UCreg_pc, &sf->uc.uc_mcontext.regs.UCreg_pc); + err |= __put_user(regs->UCreg_asr, &sf->uc.uc_mcontext.regs.UCreg_asr); + + err |= __put_user(current->thread.trap_no, + &sf->uc.uc_mcontext.trap_no); + err |= __put_user(current->thread.error_code, + &sf->uc.uc_mcontext.error_code); + err |= __put_user(current->thread.address, + &sf->uc.uc_mcontext.fault_address); + err |= __put_user(set->sig[0], &sf->uc.uc_mcontext.oldmask); + + err |= __copy_to_user(&sf->uc.uc_sigmask, set, sizeof(*set)); + + return err; +} + +static inline void __user *get_sigframe(struct k_sigaction *ka, + struct pt_regs *regs, int framesize) +{ + unsigned long sp = regs->UCreg_sp; + void __user *frame; + + /* + * This is the X/Open sanctioned signal stack switching. + */ + if ((ka->sa.sa_flags & SA_ONSTACK) && !sas_ss_flags(sp)) + sp = current->sas_ss_sp + current->sas_ss_size; + + /* + * ATPCS B01 mandates 8-byte alignment + */ + frame = (void __user *)((sp - framesize) & ~7); + + /* + * Check that we can actually write to the signal frame. + */ + if (!access_ok(VERIFY_WRITE, frame, framesize)) + frame = NULL; + + return frame; +} + +static int setup_return(struct pt_regs *regs, struct k_sigaction *ka, + unsigned long __user *rc, void __user *frame, int usig) +{ + unsigned long handler = (unsigned long)ka->sa.sa_handler; + unsigned long retcode; + unsigned long asr = regs->UCreg_asr & ~PSR_f; + + unsigned int idx = 0; + + if (ka->sa.sa_flags & SA_SIGINFO) + idx += 1; + + if (__put_user(sigreturn_codes[idx], rc) || + __put_user(sigreturn_codes[idx+1], rc+1)) + return 1; + + retcode = KERN_SIGRETURN_CODE + (idx << 2); + + regs->UCreg_00 = usig; + regs->UCreg_sp = (unsigned long)frame; + regs->UCreg_lr = retcode; + regs->UCreg_pc = handler; + regs->UCreg_asr = asr; + + return 0; +} + +static int setup_frame(int usig, struct k_sigaction *ka, + sigset_t *set, struct pt_regs *regs) +{ + struct sigframe __user *frame = get_sigframe(ka, regs, sizeof(*frame)); + int err = 0; + + if (!frame) + return 1; + + /* + * Set uc.uc_flags to a value which sc.trap_no would never have. + */ + err |= __put_user(0x5ac3c35a, &frame->uc.uc_flags); + + err |= setup_sigframe(frame, regs, set); + if (err == 0) + err |= setup_return(regs, ka, frame->retcode, frame, usig); + + return err; +} + +static int setup_rt_frame(int usig, struct k_sigaction *ka, siginfo_t *info, + sigset_t *set, struct pt_regs *regs) +{ + struct rt_sigframe __user *frame = + get_sigframe(ka, regs, sizeof(*frame)); + stack_t stack; + int err = 0; + + if (!frame) + return 1; + + err |= copy_siginfo_to_user(&frame->info, info); + + err |= __put_user(0, &frame->sig.uc.uc_flags); + err |= __put_user(NULL, &frame->sig.uc.uc_link); + + memset(&stack, 0, sizeof(stack)); + stack.ss_sp = (void __user *)current->sas_ss_sp; + stack.ss_flags = sas_ss_flags(regs->UCreg_sp); + stack.ss_size = current->sas_ss_size; + err |= __copy_to_user(&frame->sig.uc.uc_stack, &stack, sizeof(stack)); + + err |= setup_sigframe(&frame->sig, regs, set); + if (err == 0) + err |= setup_return(regs, ka, frame->sig.retcode, frame, usig); + + if (err == 0) { + /* + * For realtime signals we must also set the second and third + * arguments for the signal handler. + */ + regs->UCreg_01 = (unsigned long)&frame->info; + regs->UCreg_02 = (unsigned long)&frame->sig.uc; + } + + return err; +} + +static inline void setup_syscall_restart(struct pt_regs *regs) +{ + regs->UCreg_00 = regs->UCreg_ORIG_00; + regs->UCreg_pc -= 4; +} + +/* + * OK, we're invoking a handler + */ +static int handle_signal(unsigned long sig, struct k_sigaction *ka, + siginfo_t *info, sigset_t *oldset, + struct pt_regs *regs, int syscall) +{ + struct thread_info *thread = current_thread_info(); + struct task_struct *tsk = current; + int usig = sig; + int ret; + + /* + * If we were from a system call, check for system call restarting... + */ + if (syscall) { + switch (regs->UCreg_00) { + case -ERESTART_RESTARTBLOCK: + case -ERESTARTNOHAND: + regs->UCreg_00 = -EINTR; + break; + case -ERESTARTSYS: + if (!(ka->sa.sa_flags & SA_RESTART)) { + regs->UCreg_00 = -EINTR; + break; + } + /* fallthrough */ + case -ERESTARTNOINTR: + setup_syscall_restart(regs); + } + } + + /* + * translate the signal + */ + if (usig < 32 && thread->exec_domain + && thread->exec_domain->signal_invmap) + usig = thread->exec_domain->signal_invmap[usig]; + + /* + * Set up the stack frame + */ + if (ka->sa.sa_flags & SA_SIGINFO) + ret = setup_rt_frame(usig, ka, info, oldset, regs); + else + ret = setup_frame(usig, ka, oldset, regs); + + /* + * Check that the resulting registers are actually sane. + */ + ret |= !valid_user_regs(regs); + + if (ret != 0) { + force_sigsegv(sig, tsk); + return ret; + } + + /* + * Block the signal if we were successful. + */ + spin_lock_irq(&tsk->sighand->siglock); + sigorsets(&tsk->blocked, &tsk->blocked, + &ka->sa.sa_mask); + if (!(ka->sa.sa_flags & SA_NODEFER)) + sigaddset(&tsk->blocked, sig); + recalc_sigpending(); + spin_unlock_irq(&tsk->sighand->siglock); + + return 0; +} + +/* + * Note that 'init' is a special process: it doesn't get signals it doesn't + * want to handle. Thus you cannot kill init even with a SIGKILL even by + * mistake. + * + * Note that we go through the signals twice: once to check the signals that + * the kernel can handle, and then we build all the user-level signal handling + * stack-frames in one go after that. + */ +static void do_signal(struct pt_regs *regs, int syscall) +{ + struct k_sigaction ka; + siginfo_t info; + int signr; + + /* + * We want the common case to go fast, which + * is why we may in certain cases get here from + * kernel mode. Just return without doing anything + * if so. + */ + if (!user_mode(regs)) + return; + + if (try_to_freeze()) + goto no_signal; + + signr = get_signal_to_deliver(&info, &ka, regs, NULL); + if (signr > 0) { + sigset_t *oldset; + + if (test_thread_flag(TIF_RESTORE_SIGMASK)) + oldset = ¤t->saved_sigmask; + else + oldset = ¤t->blocked; + if (handle_signal(signr, &ka, &info, oldset, regs, syscall) + == 0) { + /* + * A signal was successfully delivered; the saved + * sigmask will have been stored in the signal frame, + * and will be restored by sigreturn, so we can simply + * clear the TIF_RESTORE_SIGMASK flag. + */ + if (test_thread_flag(TIF_RESTORE_SIGMASK)) + clear_thread_flag(TIF_RESTORE_SIGMASK); + } + return; + } + + no_signal: + /* + * No signal to deliver to the process - restart the syscall. + */ + if (syscall) { + if (regs->UCreg_00 == -ERESTART_RESTARTBLOCK) { + u32 __user *usp; + + regs->UCreg_sp -= 4; + usp = (u32 __user *)regs->UCreg_sp; + + if (put_user(regs->UCreg_pc, usp) == 0) { + regs->UCreg_pc = KERN_RESTART_CODE; + } else { + regs->UCreg_sp += 4; + force_sigsegv(0, current); + } + } + if (regs->UCreg_00 == -ERESTARTNOHAND || + regs->UCreg_00 == -ERESTARTSYS || + regs->UCreg_00 == -ERESTARTNOINTR) { + setup_syscall_restart(regs); + } + + /* If there's no signal to deliver, we just put the saved + * sigmask back. + */ + if (test_thread_flag(TIF_RESTORE_SIGMASK)) { + clear_thread_flag(TIF_RESTORE_SIGMASK); + sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL); + } + } +} + +asmlinkage void do_notify_resume(struct pt_regs *regs, + unsigned int thread_flags, int syscall) +{ + if (thread_flags & _TIF_SIGPENDING) + do_signal(regs, syscall); + + if (thread_flags & _TIF_NOTIFY_RESUME) { + clear_thread_flag(TIF_NOTIFY_RESUME); + tracehook_notify_resume(regs); + if (current->replacement_session_keyring) + key_replace_session_keyring(); + } +} + +/* + * Copy signal return handlers into the vector page, and + * set sigreturn to be a pointer to these. + */ +void __init early_signal_init(void) +{ + memcpy((void *)kuser_vecpage_to_vectors(KERN_SIGRETURN_CODE), + sigreturn_codes, sizeof(sigreturn_codes)); + memcpy((void *)kuser_vecpage_to_vectors(KERN_RESTART_CODE), + syscall_restart_code, sizeof(syscall_restart_code)); + /* Need not to flush icache, since early_trap_init will do it last. */ +} diff --git a/arch/unicore32/kernel/sleep.S b/arch/unicore32/kernel/sleep.S new file mode 100644 index 000000000000..607a104aec59 --- /dev/null +++ b/arch/unicore32/kernel/sleep.S @@ -0,0 +1,202 @@ +/* + * linux/arch/unicore32/kernel/sleep.S + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn> + * Copyright (C) 2001-2010 Guan Xuetao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <mach/hardware.h> + + .text + +pkunity_cpu_save_cp: + + @ get coprocessor registers + + movc r3, p0.c7, #0 @ PID + movc r4, p0.c2, #0 @ translation table base addr + movc r5, p0.c1, #0 @ control reg + + + @ store them plus current virtual stack ptr on stack + mov r6, sp + stm.w (r3 - r6), [sp-] + + mov pc, lr + +pkunity_cpu_save_sp: + @ preserve phys address of stack + mov r0, sp + stw.w lr, [sp+], #-4 + b.l sleep_phys_sp + ldw r1, =sleep_save_sp + stw r0, [r1] + ldw.w pc, [sp]+, #4 + +/* + * puv3_cpu_suspend() + * + * Forces CPU into sleep state. + * + * r0 = value for PWRMODE M field for desired sleep state + */ + +ENTRY(puv3_cpu_suspend) + stm.w (r16 - r27, lr), [sp-] @ save registers on stack + stm.w (r4 - r15), [sp-] @ save registers on stack + +#ifdef CONFIG_UNICORE_FPU_F64 + sfm.w (f0 - f7 ), [sp-] + sfm.w (f8 - f15), [sp-] + sfm.w (f16 - f23), [sp-] + sfm.w (f24 - f31), [sp-] + cff r4, s31 + stm.w (r4), [sp-] +#endif + b.l pkunity_cpu_save_cp + + b.l pkunity_cpu_save_sp + + @ clean data cache + mov r1, #0 + movc p0.c5, r1, #14 + nop + nop + nop + nop + + + + @ DDR2 BaseAddr + ldw r0, =(PKUNITY_DDR2CTRL_BASE) + + @ PM BaseAddr + ldw r1, =(PKUNITY_PM_BASE) + + @ set PLL_SYS_CFG reg, 275 + movl r6, #0x00002401 + stw r6, [r1+], #0x18 + @ set PLL_DDR_CFG reg, 66MHz + movl r6, #0x00100c00 + stw r6, [r1+], #0x1c + + @ set wake up source + movl r8, #0x800001ff @ epip4d + stw r8, [r1+], #0xc + + @ set PGSR + movl r5, #0x40000 + stw r5, [r1+], #0x10 + + @ prepare DDR2 refresh settings + ldw r5, [r0+], #0x24 + or r5, r5, #0x00000001 + + @ prepare PMCR for PLL changing + movl r6, #0xc + + @ prepare for closing PLL + movl r7, #0x1 + + @ prepare sleep mode + mov r8, #0x1 + +@ movl r0, 0x11111111 +@ put_word_ocd r0 + b pkunity_cpu_do_suspend + + .ltorg + .align 5 +pkunity_cpu_do_suspend: + b 101f + @ put DDR2 into self-refresh +100: stw r5, [r0+], #0x24 + @ change PLL + stw r6, [r1] + b 1f + + .ltorg + .align 5 +101: b 102f + @ wait for PLL changing complete +1: ldw r6, [r1+], #0x44 + csub.a r6, #0x1 + bne 1b + b 2f + + .ltorg + .align 5 +102: b 100b + @ close PLL +2: stw r7, [r1+], #0x4 + @ enter sleep mode + stw r8, [r1] +3: b 3b + + + + +/* + * puv3_cpu_resume() + * + * entry point from bootloader into kernel during resume + * + * Note: Yes, part of the following code is located into the .data section. + * This is to allow sleep_save_sp to be accessed with a relative load + * while we can't rely on any MMU translation. We could have put + * sleep_save_sp in the .text section as well, but some setups might + * insist on it to be truly read-only. + */ + + .data + .align 5 +ENTRY(puv3_cpu_resume) +@ movl r0, 0x20202020 +@ put_word_ocd r0 + + ldw r0, sleep_save_sp @ stack phys addr + ldw r2, =resume_after_mmu @ its absolute virtual address + ldm (r3 - r6), [r0]+ @ CP regs + virt stack ptr + mov sp, r6 @ CP regs + virt stack ptr + + mov r1, #0 + movc p0.c6, r1, #6 @ invalidate I & D TLBs + movc p0.c5, r1, #28 @ invalidate I & D caches, BTB + + movc p0.c7, r3, #0 @ PID + movc p0.c2, r4, #0 @ translation table base addr + movc p0.c1, r5, #0 @ control reg, turn on mmu + nop + jump r2 + nop + nop + nop + nop + nop + +sleep_save_sp: + .word 0 @ preserve stack phys ptr here + + .text +resume_after_mmu: +@ movl r0, 0x30303030 +@ put_word_ocd r0 + +#ifdef CONFIG_UNICORE_FPU_F64 + lfm.w (f0 - f7 ), [sp]+ + lfm.w (f8 - f15), [sp]+ + lfm.w (f16 - f23), [sp]+ + lfm.w (f24 - f31), [sp]+ + ldm.w (r4), [sp]+ + ctf r4, s31 +#endif + ldm.w (r4 - r15), [sp]+ @ restore registers from stack + ldm.w (r16 - r27, pc), [sp]+ @ return to caller diff --git a/arch/unicore32/kernel/stacktrace.c b/arch/unicore32/kernel/stacktrace.c new file mode 100644 index 000000000000..b34030bdabe3 --- /dev/null +++ b/arch/unicore32/kernel/stacktrace.c @@ -0,0 +1,131 @@ +/* + * linux/arch/unicore32/kernel/stacktrace.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/module.h> +#include <linux/sched.h> +#include <linux/stacktrace.h> + +#include <asm/stacktrace.h> + +#if defined(CONFIG_FRAME_POINTER) +/* + * Unwind the current stack frame and store the new register values in the + * structure passed as argument. Unwinding is equivalent to a function return, + * hence the new PC value rather than LR should be used for backtrace. + * + * With framepointer enabled, a simple function prologue looks like this: + * mov ip, sp + * stmdb sp!, {fp, ip, lr, pc} + * sub fp, ip, #4 + * + * A simple function epilogue looks like this: + * ldm sp, {fp, sp, pc} + * + * Note that with framepointer enabled, even the leaf functions have the same + * prologue and epilogue, therefore we can ignore the LR value in this case. + */ +int notrace unwind_frame(struct stackframe *frame) +{ + unsigned long high, low; + unsigned long fp = frame->fp; + + /* only go to a higher address on the stack */ + low = frame->sp; + high = ALIGN(low, THREAD_SIZE); + + /* check current frame pointer is within bounds */ + if (fp < (low + 12) || fp + 4 >= high) + return -EINVAL; + + /* restore the registers from the stack frame */ + frame->fp = *(unsigned long *)(fp - 12); + frame->sp = *(unsigned long *)(fp - 8); + frame->pc = *(unsigned long *)(fp - 4); + + return 0; +} +#endif + +void notrace walk_stackframe(struct stackframe *frame, + int (*fn)(struct stackframe *, void *), void *data) +{ + while (1) { + int ret; + + if (fn(frame, data)) + break; + ret = unwind_frame(frame); + if (ret < 0) + break; + } +} +EXPORT_SYMBOL(walk_stackframe); + +#ifdef CONFIG_STACKTRACE +struct stack_trace_data { + struct stack_trace *trace; + unsigned int no_sched_functions; + unsigned int skip; +}; + +static int save_trace(struct stackframe *frame, void *d) +{ + struct stack_trace_data *data = d; + struct stack_trace *trace = data->trace; + unsigned long addr = frame->pc; + + if (data->no_sched_functions && in_sched_functions(addr)) + return 0; + if (data->skip) { + data->skip--; + return 0; + } + + trace->entries[trace->nr_entries++] = addr; + + return trace->nr_entries >= trace->max_entries; +} + +void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace) +{ + struct stack_trace_data data; + struct stackframe frame; + + data.trace = trace; + data.skip = trace->skip; + + if (tsk != current) { + data.no_sched_functions = 1; + frame.fp = thread_saved_fp(tsk); + frame.sp = thread_saved_sp(tsk); + frame.lr = 0; /* recovered from the stack */ + frame.pc = thread_saved_pc(tsk); + } else { + register unsigned long current_sp asm("sp"); + + data.no_sched_functions = 0; + frame.fp = (unsigned long)__builtin_frame_address(0); + frame.sp = current_sp; + frame.lr = (unsigned long)__builtin_return_address(0); + frame.pc = (unsigned long)save_stack_trace_tsk; + } + + walk_stackframe(&frame, save_trace, &data); + if (trace->nr_entries < trace->max_entries) + trace->entries[trace->nr_entries++] = ULONG_MAX; +} + +void save_stack_trace(struct stack_trace *trace) +{ + save_stack_trace_tsk(current, trace); +} +EXPORT_SYMBOL_GPL(save_stack_trace); +#endif diff --git a/arch/unicore32/kernel/sys.c b/arch/unicore32/kernel/sys.c new file mode 100644 index 000000000000..3afe60a39ac9 --- /dev/null +++ b/arch/unicore32/kernel/sys.c @@ -0,0 +1,126 @@ +/* + * linux/arch/unicore32/kernel/sys.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/module.h> +#include <linux/errno.h> +#include <linux/sched.h> +#include <linux/slab.h> +#include <linux/mm.h> +#include <linux/sem.h> +#include <linux/msg.h> +#include <linux/shm.h> +#include <linux/stat.h> +#include <linux/syscalls.h> +#include <linux/mman.h> +#include <linux/fs.h> +#include <linux/file.h> +#include <linux/ipc.h> +#include <linux/uaccess.h> + +#include <asm/syscalls.h> +#include <asm/cacheflush.h> + +/* Clone a task - this clones the calling program thread. + * This is called indirectly via a small wrapper + */ +asmlinkage long __sys_clone(unsigned long clone_flags, unsigned long newsp, + void __user *parent_tid, void __user *child_tid, + struct pt_regs *regs) +{ + if (!newsp) + newsp = regs->UCreg_sp; + + return do_fork(clone_flags, newsp, regs, 0, + parent_tid, child_tid); +} + +/* sys_execve() executes a new program. + * This is called indirectly via a small wrapper + */ +asmlinkage long __sys_execve(const char __user *filename, + const char __user *const __user *argv, + const char __user *const __user *envp, + struct pt_regs *regs) +{ + int error; + char *fn; + + fn = getname(filename); + error = PTR_ERR(fn); + if (IS_ERR(fn)) + goto out; + error = do_execve(fn, argv, envp, regs); + putname(fn); +out: + return error; +} + +int kernel_execve(const char *filename, + const char *const argv[], + const char *const envp[]) +{ + struct pt_regs regs; + int ret; + + memset(®s, 0, sizeof(struct pt_regs)); + ret = do_execve(filename, + (const char __user *const __user *)argv, + (const char __user *const __user *)envp, ®s); + if (ret < 0) + goto out; + + /* + * Save argc to the register structure for userspace. + */ + regs.UCreg_00 = ret; + + /* + * We were successful. We won't be returning to our caller, but + * instead to user space by manipulating the kernel stack. + */ + asm("add r0, %0, %1\n\t" + "mov r1, %2\n\t" + "mov r2, %3\n\t" + "mov r22, #0\n\t" /* not a syscall */ + "mov r23, %0\n\t" /* thread structure */ + "b.l memmove\n\t" /* copy regs to top of stack */ + "mov sp, r0\n\t" /* reposition stack pointer */ + "b ret_to_user" + : + : "r" (current_thread_info()), + "Ir" (THREAD_START_SP - sizeof(regs)), + "r" (®s), + "Ir" (sizeof(regs)) + : "r0", "r1", "r2", "r3", "ip", "lr", "memory"); + + out: + return ret; +} +EXPORT_SYMBOL(kernel_execve); + +/* Note: used by the compat code even in 64-bit Linux. */ +SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len, + unsigned long, prot, unsigned long, flags, + unsigned long, fd, unsigned long, off_4k) +{ + return sys_mmap_pgoff(addr, len, prot, flags, fd, + off_4k); +} + +/* Provide the actual syscall number to call mapping. */ +#undef __SYSCALL +#define __SYSCALL(nr, call) [nr] = (call), + +/* Note that we don't include <linux/unistd.h> but <asm/unistd.h> */ +void *sys_call_table[__NR_syscalls] = { + [0 ... __NR_syscalls-1] = sys_ni_syscall, +#include <asm/unistd.h> +}; diff --git a/arch/unicore32/kernel/time.c b/arch/unicore32/kernel/time.c new file mode 100644 index 000000000000..080710c09241 --- /dev/null +++ b/arch/unicore32/kernel/time.c @@ -0,0 +1,143 @@ +/* + * linux/arch/unicore32/kernel/time.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn> + * Copyright (C) 2001-2010 Guan Xuetao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/init.h> +#include <linux/errno.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/timex.h> +#include <linux/clockchips.h> + +#include <mach/hardware.h> + +#define MIN_OSCR_DELTA 2 + +static irqreturn_t puv3_ost0_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *c = dev_id; + + /* Disarm the compare/match, signal the event. */ + writel(readl(OST_OIER) & ~OST_OIER_E0, OST_OIER); + writel(readl(OST_OSSR) & ~OST_OSSR_M0, OST_OSSR); + c->event_handler(c); + + return IRQ_HANDLED; +} + +static int +puv3_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c) +{ + unsigned long next, oscr; + + writel(readl(OST_OIER) | OST_OIER_E0, OST_OIER); + next = readl(OST_OSCR) + delta; + writel(next, OST_OSMR0); + oscr = readl(OST_OSCR); + + return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0; +} + +static void +puv3_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c) +{ + switch (mode) { + case CLOCK_EVT_MODE_ONESHOT: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + writel(readl(OST_OIER) & ~OST_OIER_E0, OST_OIER); + writel(readl(OST_OSSR) & ~OST_OSSR_M0, OST_OSSR); + break; + + case CLOCK_EVT_MODE_RESUME: + case CLOCK_EVT_MODE_PERIODIC: + break; + } +} + +static struct clock_event_device ckevt_puv3_osmr0 = { + .name = "osmr0", + .features = CLOCK_EVT_FEAT_ONESHOT, + .rating = 200, + .set_next_event = puv3_osmr0_set_next_event, + .set_mode = puv3_osmr0_set_mode, +}; + +static cycle_t puv3_read_oscr(struct clocksource *cs) +{ + return readl(OST_OSCR); +} + +static struct clocksource cksrc_puv3_oscr = { + .name = "oscr", + .rating = 200, + .read = puv3_read_oscr, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static struct irqaction puv3_timer_irq = { + .name = "ost0", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = puv3_ost0_interrupt, + .dev_id = &ckevt_puv3_osmr0, +}; + +void __init time_init(void) +{ + writel(0, OST_OIER); /* disable any timer interrupts */ + writel(0, OST_OSSR); /* clear status on all timers */ + + clockevents_calc_mult_shift(&ckevt_puv3_osmr0, CLOCK_TICK_RATE, 5); + + ckevt_puv3_osmr0.max_delta_ns = + clockevent_delta2ns(0x7fffffff, &ckevt_puv3_osmr0); + ckevt_puv3_osmr0.min_delta_ns = + clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_puv3_osmr0) + 1; + ckevt_puv3_osmr0.cpumask = cpumask_of(0); + + setup_irq(IRQ_TIMER0, &puv3_timer_irq); + + clocksource_register_hz(&cksrc_puv3_oscr, CLOCK_TICK_RATE); + clockevents_register_device(&ckevt_puv3_osmr0); +} + +#ifdef CONFIG_PM +unsigned long osmr[4], oier; + +void puv3_timer_suspend(void) +{ + osmr[0] = readl(OST_OSMR0); + osmr[1] = readl(OST_OSMR1); + osmr[2] = readl(OST_OSMR2); + osmr[3] = readl(OST_OSMR3); + oier = readl(OST_OIER); +} + +void puv3_timer_resume(void) +{ + writel(0, OST_OSSR); + writel(osmr[0], OST_OSMR0); + writel(osmr[1], OST_OSMR1); + writel(osmr[2], OST_OSMR2); + writel(osmr[3], OST_OSMR3); + writel(oier, OST_OIER); + + /* + * OSMR0 is the system timer: make sure OSCR is sufficiently behind + */ + writel(readl(OST_OSMR0) - LATCH, OST_OSCR); +} +#else +void puv3_timer_suspend(void) { }; +void puv3_timer_resume(void) { }; +#endif + diff --git a/arch/unicore32/kernel/traps.c b/arch/unicore32/kernel/traps.c new file mode 100644 index 000000000000..25abbb101729 --- /dev/null +++ b/arch/unicore32/kernel/traps.c @@ -0,0 +1,333 @@ +/* + * linux/arch/unicore32/kernel/traps.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * 'traps.c' handles hardware exceptions after we have saved some state. + * Mostly a debugging aid, but will probably kill the offending process. + */ +#include <linux/module.h> +#include <linux/signal.h> +#include <linux/spinlock.h> +#include <linux/personality.h> +#include <linux/kallsyms.h> +#include <linux/kdebug.h> +#include <linux/uaccess.h> +#include <linux/delay.h> +#include <linux/hardirq.h> +#include <linux/init.h> +#include <linux/uaccess.h> +#include <linux/atomic.h> +#include <linux/unistd.h> + +#include <asm/cacheflush.h> +#include <asm/system.h> +#include <asm/traps.h> + +#include "setup.h" + +static void dump_mem(const char *, const char *, unsigned long, unsigned long); + +void dump_backtrace_entry(unsigned long where, + unsigned long from, unsigned long frame) +{ +#ifdef CONFIG_KALLSYMS + printk(KERN_DEFAULT "[<%08lx>] (%pS) from [<%08lx>] (%pS)\n", + where, (void *)where, from, (void *)from); +#else + printk(KERN_DEFAULT "Function entered at [<%08lx>] from [<%08lx>]\n", + where, from); +#endif +} + +/* + * Stack pointers should always be within the kernels view of + * physical memory. If it is not there, then we can't dump + * out any information relating to the stack. + */ +static int verify_stack(unsigned long sp) +{ + if (sp < PAGE_OFFSET || + (sp > (unsigned long)high_memory && high_memory != NULL)) + return -EFAULT; + + return 0; +} + +/* + * Dump out the contents of some memory nicely... + */ +static void dump_mem(const char *lvl, const char *str, unsigned long bottom, + unsigned long top) +{ + unsigned long first; + mm_segment_t fs; + int i; + + /* + * We need to switch to kernel mode so that we can use __get_user + * to safely read from kernel space. Note that we now dump the + * code first, just in case the backtrace kills us. + */ + fs = get_fs(); + set_fs(KERNEL_DS); + + printk(KERN_DEFAULT "%s%s(0x%08lx to 0x%08lx)\n", + lvl, str, bottom, top); + + for (first = bottom & ~31; first < top; first += 32) { + unsigned long p; + char str[sizeof(" 12345678") * 8 + 1]; + + memset(str, ' ', sizeof(str)); + str[sizeof(str) - 1] = '\0'; + + for (p = first, i = 0; i < 8 && p < top; i++, p += 4) { + if (p >= bottom && p < top) { + unsigned long val; + if (__get_user(val, (unsigned long *)p) == 0) + sprintf(str + i * 9, " %08lx", val); + else + sprintf(str + i * 9, " ????????"); + } + } + printk(KERN_DEFAULT "%s%04lx:%s\n", lvl, first & 0xffff, str); + } + + set_fs(fs); +} + +static void dump_instr(const char *lvl, struct pt_regs *regs) +{ + unsigned long addr = instruction_pointer(regs); + const int width = 8; + mm_segment_t fs; + char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str; + int i; + + /* + * We need to switch to kernel mode so that we can use __get_user + * to safely read from kernel space. Note that we now dump the + * code first, just in case the backtrace kills us. + */ + fs = get_fs(); + set_fs(KERNEL_DS); + + for (i = -4; i < 1; i++) { + unsigned int val, bad; + + bad = __get_user(val, &((u32 *)addr)[i]); + + if (!bad) + p += sprintf(p, i == 0 ? "(%0*x) " : "%0*x ", + width, val); + else { + p += sprintf(p, "bad PC value"); + break; + } + } + printk(KERN_DEFAULT "%sCode: %s\n", lvl, str); + + set_fs(fs); +} + +static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk) +{ + unsigned int fp, mode; + int ok = 1; + + printk(KERN_DEFAULT "Backtrace: "); + + if (!tsk) + tsk = current; + + if (regs) { + fp = regs->UCreg_fp; + mode = processor_mode(regs); + } else if (tsk != current) { + fp = thread_saved_fp(tsk); + mode = 0x10; + } else { + asm("mov %0, fp" : "=r" (fp) : : "cc"); + mode = 0x10; + } + + if (!fp) { + printk("no frame pointer"); + ok = 0; + } else if (verify_stack(fp)) { + printk("invalid frame pointer 0x%08x", fp); + ok = 0; + } else if (fp < (unsigned long)end_of_stack(tsk)) + printk("frame pointer underflow"); + printk("\n"); + + if (ok) + c_backtrace(fp, mode); +} + +void dump_stack(void) +{ + dump_backtrace(NULL, NULL); +} +EXPORT_SYMBOL(dump_stack); + +void show_stack(struct task_struct *tsk, unsigned long *sp) +{ + dump_backtrace(NULL, tsk); + barrier(); +} + +static int __die(const char *str, int err, struct thread_info *thread, + struct pt_regs *regs) +{ + struct task_struct *tsk = thread->task; + static int die_counter; + int ret; + + printk(KERN_EMERG "Internal error: %s: %x [#%d]\n", + str, err, ++die_counter); + sysfs_printk_last_file(); + + /* trap and error numbers are mostly meaningless on UniCore */ + ret = notify_die(DIE_OOPS, str, regs, err, tsk->thread.trap_no, \ + SIGSEGV); + if (ret == NOTIFY_STOP) + return ret; + + print_modules(); + __show_regs(regs); + printk(KERN_EMERG "Process %.*s (pid: %d, stack limit = 0x%p)\n", + TASK_COMM_LEN, tsk->comm, task_pid_nr(tsk), thread + 1); + + if (!user_mode(regs) || in_interrupt()) { + dump_mem(KERN_EMERG, "Stack: ", regs->UCreg_sp, + THREAD_SIZE + (unsigned long)task_stack_page(tsk)); + dump_backtrace(regs, tsk); + dump_instr(KERN_EMERG, regs); + } + + return ret; +} + +DEFINE_SPINLOCK(die_lock); + +/* + * This function is protected against re-entrancy. + */ +void die(const char *str, struct pt_regs *regs, int err) +{ + struct thread_info *thread = current_thread_info(); + int ret; + + oops_enter(); + + spin_lock_irq(&die_lock); + console_verbose(); + bust_spinlocks(1); + ret = __die(str, err, thread, regs); + + bust_spinlocks(0); + add_taint(TAINT_DIE); + spin_unlock_irq(&die_lock); + oops_exit(); + + if (in_interrupt()) + panic("Fatal exception in interrupt"); + if (panic_on_oops) + panic("Fatal exception"); + if (ret != NOTIFY_STOP) + do_exit(SIGSEGV); +} + +void uc32_notify_die(const char *str, struct pt_regs *regs, + struct siginfo *info, unsigned long err, unsigned long trap) +{ + if (user_mode(regs)) { + current->thread.error_code = err; + current->thread.trap_no = trap; + + force_sig_info(info->si_signo, info, current); + } else + die(str, regs, err); +} + +/* + * bad_mode handles the impossible case in the vectors. If you see one of + * these, then it's extremely serious, and could mean you have buggy hardware. + * It never returns, and never tries to sync. We hope that we can at least + * dump out some state information... + */ +asmlinkage void bad_mode(struct pt_regs *regs, unsigned int reason) +{ + console_verbose(); + + printk(KERN_CRIT "Bad mode detected with reason 0x%x\n", reason); + + die("Oops - bad mode", regs, 0); + local_irq_disable(); + panic("bad mode"); +} + +void __pte_error(const char *file, int line, unsigned long val) +{ + printk(KERN_DEFAULT "%s:%d: bad pte %08lx.\n", file, line, val); +} + +void __pmd_error(const char *file, int line, unsigned long val) +{ + printk(KERN_DEFAULT "%s:%d: bad pmd %08lx.\n", file, line, val); +} + +void __pgd_error(const char *file, int line, unsigned long val) +{ + printk(KERN_DEFAULT "%s:%d: bad pgd %08lx.\n", file, line, val); +} + +asmlinkage void __div0(void) +{ + printk(KERN_DEFAULT "Division by zero in kernel.\n"); + dump_stack(); +} +EXPORT_SYMBOL(__div0); + +void abort(void) +{ + BUG(); + + /* if that doesn't kill us, halt */ + panic("Oops failed to kill thread"); +} +EXPORT_SYMBOL(abort); + +void __init trap_init(void) +{ + return; +} + +void __init early_trap_init(void) +{ + unsigned long vectors = VECTORS_BASE; + + /* + * Copy the vectors, stubs (in entry-unicore.S) + * into the vector page, mapped at 0xffff0000, and ensure these + * are visible to the instruction stream. + */ + memcpy((void *)vectors, + __vectors_start, + __vectors_end - __vectors_start); + memcpy((void *)vectors + 0x200, + __stubs_start, + __stubs_end - __stubs_start); + + early_signal_init(); + + flush_icache_range(vectors, vectors + PAGE_SIZE); +} diff --git a/arch/unicore32/kernel/vmlinux.lds.S b/arch/unicore32/kernel/vmlinux.lds.S new file mode 100644 index 000000000000..0b4eb89729e7 --- /dev/null +++ b/arch/unicore32/kernel/vmlinux.lds.S @@ -0,0 +1,61 @@ +/* + * linux/arch/unicore32/kernel/vmlinux.lds.S + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <asm-generic/vmlinux.lds.h> +#include <asm/thread_info.h> +#include <asm/memory.h> +#include <asm/page.h> + +OUTPUT_ARCH(unicore32) +ENTRY(stext) + +jiffies = jiffies_64; + +SECTIONS +{ + . = PAGE_OFFSET + KERNEL_IMAGE_START; + + _text = .; + __init_begin = .; + HEAD_TEXT_SECTION + INIT_TEXT_SECTION(PAGE_SIZE) + INIT_DATA_SECTION(16) + PERCPU(PAGE_SIZE) + __init_end = .; + + _stext = .; + .text : { /* Real text segment */ + TEXT_TEXT + SCHED_TEXT + LOCK_TEXT + + *(.fixup) + *(.gnu.warning) + } + _etext = .; + + _sdata = .; + RO_DATA_SECTION(PAGE_SIZE) + RW_DATA_SECTION(32, PAGE_SIZE, THREAD_SIZE) + _edata = .; + + EXCEPTION_TABLE(32) + NOTES + + BSS_SECTION(0, 0, 0) + _end = .; + + STABS_DEBUG + DWARF_DEBUG + + DISCARDS /* Exit code and data */ +} diff --git a/arch/unicore32/lib/Makefile b/arch/unicore32/lib/Makefile new file mode 100644 index 000000000000..87229a558b36 --- /dev/null +++ b/arch/unicore32/lib/Makefile @@ -0,0 +1,27 @@ +# +# linux/arch/unicore32/lib/Makefile +# +# Copyright (C) 2001-2010 GUAN Xue-tao +# + +lib-y := backtrace.o delay.o findbit.o +lib-y += strncpy_from_user.o strnlen_user.o +lib-y += clear_user.o copy_page.o +lib-y += copy_from_user.o copy_to_user.o + +GNU_LIBC_A := $(shell $(CC) $(KBUILD_CFLAGS) -print-file-name=libc.a) +GNU_LIBC_A_OBJS := memchr.o memcpy.o memmove.o memset.o +GNU_LIBC_A_OBJS += strchr.o strrchr.o +GNU_LIBC_A_OBJS += rawmemchr.o # needed by strrchr.o + +GNU_LIBGCC_A := $(shell $(CC) $(KBUILD_CFLAGS) -print-file-name=libgcc.a) +GNU_LIBGCC_A_OBJS := _ashldi3.o _ashrdi3.o _lshrdi3.o +GNU_LIBGCC_A_OBJS += _divsi3.o _modsi3.o _ucmpdi2.o _umodsi3.o _udivsi3.o + +lib-y += $(GNU_LIBC_A_OBJS) $(GNU_LIBGCC_A_OBJS) + +$(addprefix $(obj)/, $(GNU_LIBC_A_OBJS)): + $(Q)$(AR) p $(GNU_LIBC_A) $(notdir $@) > $@ + +$(addprefix $(obj)/, $(GNU_LIBGCC_A_OBJS)): + $(Q)$(AR) p $(GNU_LIBGCC_A) $(notdir $@) > $@ diff --git a/arch/unicore32/lib/backtrace.S b/arch/unicore32/lib/backtrace.S new file mode 100644 index 000000000000..ef01d77f2f65 --- /dev/null +++ b/arch/unicore32/lib/backtrace.S @@ -0,0 +1,163 @@ +/* + * linux/arch/unicore32/lib/backtrace.S + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/linkage.h> +#include <asm/assembler.h> + .text + +@ fp is 0 or stack frame + +#define frame v4 +#define sv_fp v5 +#define sv_pc v6 +#define offset v8 + +ENTRY(__backtrace) + mov r0, fp + +ENTRY(c_backtrace) + +#if !defined(CONFIG_FRAME_POINTER) || !defined(CONFIG_PRINTK) + mov pc, lr +ENDPROC(__backtrace) +ENDPROC(c_backtrace) +#else + stm.w (v4 - v8, lr), [sp-] @ Save an extra register + @ so we have a location... + mov.a frame, r0 @ if frame pointer is zero + beq no_frame @ we have no stack frames + +1: stm.w (pc), [sp-] @ calculate offset of PC stored + ldw.w r0, [sp]+, #4 @ by stmfd for this CPU + adr r1, 1b + sub offset, r0, r1 + +/* + * Stack frame layout: + * optionally saved caller registers (r4 - r10) + * saved fp + * saved sp + * saved lr + * frame => saved pc + * optionally saved arguments (r0 - r3) + * saved sp => <next word> + * + * Functions start with the following code sequence: + * mov ip, sp + * stm.w (r0 - r3), [sp-] (optional) + * corrected pc => stm.w sp, (..., fp, ip, lr, pc) + */ +for_each_frame: + +1001: ldw sv_pc, [frame+], #0 @ get saved pc +1002: ldw sv_fp, [frame+], #-12 @ get saved fp + + sub sv_pc, sv_pc, offset @ Correct PC for prefetching + +1003: ldw r2, [sv_pc+], #-4 @ if stmfd sp, {args} exists, + ldw r3, .Ldsi+4 @ adjust saved 'pc' back one + cxor.a r3, r2 >> #14 @ instruction + beq 201f + sub r0, sv_pc, #4 @ allow for mov + b 202f +201: + sub r0, sv_pc, #8 @ allow for mov + stmia +202: + ldw r1, [frame+], #-4 @ get saved lr + mov r2, frame + b.l dump_backtrace_entry + + ldw r1, [sv_pc+], #-4 @ if stmfd sp, {args} exists, + ldw r3, .Ldsi+4 + cxor.a r3, r1 >> #14 + bne 1004f + ldw r0, [frame+], #-8 @ get sp + sub r0, r0, #4 @ point at the last arg + b.l .Ldumpstm @ dump saved registers + +1004: ldw r1, [sv_pc+], #0 @ if stmfd {, fp, ip, lr, pc} + ldw r3, .Ldsi @ instruction exists, + cxor.a r3, r1 >> #14 + bne 201f + sub r0, frame, #16 + b.l .Ldumpstm @ dump saved registers +201: + cxor.a sv_fp, #0 @ zero saved fp means + beq no_frame @ no further frames + + csub.a sv_fp, frame @ next frame must be + mov frame, sv_fp @ above the current frame + bua for_each_frame + +1006: adr r0, .Lbad + mov r1, frame + b.l printk +no_frame: ldm.w (v4 - v8, pc), [sp]+ +ENDPROC(__backtrace) +ENDPROC(c_backtrace) + + .pushsection __ex_table,"a" + .align 3 + .long 1001b, 1006b + .long 1002b, 1006b + .long 1003b, 1006b + .long 1004b, 1006b + .popsection + +#define instr v4 +#define reg v5 +#define stack v6 + +.Ldumpstm: stm.w (instr, reg, stack, v7, lr), [sp-] + mov stack, r0 + mov instr, r1 + mov reg, #14 + mov v7, #0 +1: mov r3, #1 + csub.a reg, #8 + bne 201f + sub reg, reg, #3 +201: + cand.a instr, r3 << reg + beq 2f + add v7, v7, #1 + cxor.a v7, #6 + cmoveq v7, #1 + cmoveq r1, #'\n' + cmovne r1, #' ' + ldw.w r3, [stack]+, #-4 + mov r2, reg + csub.a r2, #8 + bsl 201f + sub r2, r2, #3 +201: + cand.a instr, #0x40 @ if H is 1, high 16 regs + beq 201f + add r2, r2, #0x10 @ so r2 need add 16 +201: + adr r0, .Lfp + b.l printk +2: sub.a reg, reg, #1 + bns 1b + cxor.a v7, #0 + beq 201f + adr r0, .Lcr + b.l printk +201: ldm.w (instr, reg, stack, v7, pc), [sp]+ + +.Lfp: .asciz "%cr%d:%08x" +.Lcr: .asciz "\n" +.Lbad: .asciz "Backtrace aborted due to bad frame pointer <%p>\n" + .align +.Ldsi: .word 0x92eec000 >> 14 @ stm.w sp, (... fp, ip, lr, pc) + .word 0x92e10000 >> 14 @ stm.w sp, () + +#endif diff --git a/arch/unicore32/lib/clear_user.S b/arch/unicore32/lib/clear_user.S new file mode 100644 index 000000000000..20047f7224fd --- /dev/null +++ b/arch/unicore32/lib/clear_user.S @@ -0,0 +1,57 @@ +/* + * linux/arch/unicore32/lib/clear_user.S + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/linkage.h> +#include <asm/assembler.h> + + .text + +/* Prototype: int __clear_user(void *addr, size_t sz) + * Purpose : clear some user memory + * Params : addr - user memory address to clear + * : sz - number of bytes to clear + * Returns : number of bytes NOT cleared + */ +WEAK(__clear_user) + stm.w (lr), [sp-] + stm.w (r1), [sp-] + mov r2, #0 + csub.a r1, #4 + bsl 2f + and.a ip, r0, #3 + beq 1f + csub.a ip, #2 + strusr r2, r0, 1 + strusr r2, r0, 1, el + strusr r2, r0, 1, sl + rsub ip, ip, #4 + sub r1, r1, ip @ 7 6 5 4 3 2 1 +1: sub.a r1, r1, #8 @ -1 -2 -3 -4 -5 -6 -7 + strusr r2, r0, 4, ns, rept=2 + bns 1b + add.a r1, r1, #4 @ 3 2 1 0 -1 -2 -3 + strusr r2, r0, 4, ns +2: cand.a r1, #2 @ 1x 1x 0x 0x 1x 1x 0x + strusr r2, r0, 1, ne, rept=2 + cand.a r1, #1 @ x1 x0 x1 x0 x1 x0 x1 + beq 3f +USER( stb.u r2, [r0]) +3: mov r0, #0 + ldm.w (r1), [sp]+ + ldm.w (pc), [sp]+ +ENDPROC(__clear_user) + + .pushsection .fixup,"ax" + .align 0 +9001: ldm.w (r0), [sp]+ + ldm.w (pc), [sp]+ + .popsection + diff --git a/arch/unicore32/lib/copy_from_user.S b/arch/unicore32/lib/copy_from_user.S new file mode 100644 index 000000000000..ab0767ea5dbd --- /dev/null +++ b/arch/unicore32/lib/copy_from_user.S @@ -0,0 +1,108 @@ +/* + * linux/arch/unicore32/lib/copy_from_user.S + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/linkage.h> +#include <asm/assembler.h> + +/* + * Prototype: + * + * size_t __copy_from_user(void *to, const void *from, size_t n) + * + * Purpose: + * + * copy a block to kernel memory from user memory + * + * Params: + * + * to = kernel memory + * from = user memory + * n = number of bytes to copy + * + * Return value: + * + * Number of bytes NOT copied. + */ + + .macro ldr1w ptr reg abort + ldrusr \reg, \ptr, 4, abort=\abort + .endm + + .macro ldr4w ptr reg1 reg2 reg3 reg4 abort +100: ldm.w (\reg1, \reg2, \reg3, \reg4), [\ptr]+ + .pushsection __ex_table, "a" + .align 3 + .long 100b, \abort + .popsection + .endm + + .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort +100: ldm.w (\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8), [\ptr]+ + .pushsection __ex_table, "a" + .align 3 + .long 100b, \abort + .popsection + .endm + + .macro ldr1b ptr reg cond=al abort + ldrusr \reg, \ptr, 1, \cond, abort=\abort + .endm + + .macro str1w ptr reg abort + stw.w \reg, [\ptr]+, #4 + .endm + + .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort + stm.w (\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8), [\ptr]+ + .endm + + .macro str1b ptr reg cond=al abort + .ifnc \cond, al + b\cond 201f + b 202f + .endif +201: stb.w \reg, [\ptr]+, #1 +202: + .endm + + .macro enter + mov r3, #0 + stm.w (r0, r2, r3), [sp-] + .endm + + .macro exit + add sp, sp, #8 + ldm.w (r0), [sp]+ + mov pc, lr + .endm + + .text + +ENTRY(__copy_from_user) + +#include "copy_template.S" + +ENDPROC(__copy_from_user) + + .pushsection .fixup,"ax" + .align 0 + copy_abort_preamble + ldm.w (r1, r2), [sp]+ + sub r3, r0, r1 + rsub r2, r3, r2 + stw r2, [sp] + mov r1, #0 + b.l memset + ldw.w r0, [sp]+, #4 + copy_abort_end + .popsection + diff --git a/arch/unicore32/lib/copy_page.S b/arch/unicore32/lib/copy_page.S new file mode 100644 index 000000000000..3a448d755ade --- /dev/null +++ b/arch/unicore32/lib/copy_page.S @@ -0,0 +1,39 @@ +/* + * linux/arch/unicore32/lib/copy_page.S + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * ASM optimised string functions + */ +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <generated/asm-offsets.h> +#include <asm/cache.h> + +#define COPY_COUNT (PAGE_SZ/256) + + .text + .align 5 +/* + * UniCore optimised copy_page routine + */ +ENTRY(copy_page) + stm.w (r17 - r19, lr), [sp-] + mov r17, r0 + mov r18, r1 + mov r19, #COPY_COUNT +1: + .rept 4 + ldm.w (r0 - r15), [r18]+ + stm.w (r0 - r15), [r17]+ + .endr + sub.a r19, r19, #1 + bne 1b + ldm.w (r17 - r19, pc), [sp]+ +ENDPROC(copy_page) diff --git a/arch/unicore32/lib/copy_template.S b/arch/unicore32/lib/copy_template.S new file mode 100644 index 000000000000..524287fc0120 --- /dev/null +++ b/arch/unicore32/lib/copy_template.S @@ -0,0 +1,214 @@ +/* + * linux/arch/unicore32/lib/copy_template.S + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Theory of operation + * ------------------- + * + * This file provides the core code for a forward memory copy used in + * the implementation of memcopy(), copy_to_user() and copy_from_user(). + * + * The including file must define the following accessor macros + * according to the need of the given function: + * + * ldr1w ptr reg abort + * + * This loads one word from 'ptr', stores it in 'reg' and increments + * 'ptr' to the next word. The 'abort' argument is used for fixup tables. + * + * ldr4w ptr reg1 reg2 reg3 reg4 abort + * ldr8w ptr, reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort + * + * This loads four or eight words starting from 'ptr', stores them + * in provided registers and increments 'ptr' past those words. + * The'abort' argument is used for fixup tables. + * + * ldr1b ptr reg cond abort + * + * Similar to ldr1w, but it loads a byte and increments 'ptr' one byte. + * It also must apply the condition code if provided, otherwise the + * "al" condition is assumed by default. + * + * str1w ptr reg abort + * str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort + * str1b ptr reg cond abort + * + * Same as their ldr* counterparts, but data is stored to 'ptr' location + * rather than being loaded. + * + * enter + * + * Preserve the provided registers on the stack plus any additional + * data as needed by the implementation including this code. Called + * upon code entry. + * + * exit + * + * Restore registers with the values previously saved with the + * 'preserv' macro. Called upon code termination. + */ + + + enter + + sub.a r2, r2, #4 + bsl 8f + and.a ip, r0, #3 + bne 9f + and.a ip, r1, #3 + bne 10f + +1: sub.a r2, r2, #(28) + stm.w (r5 - r8), [sp-] + bsl 5f + +3: +4: ldr8w r1, r3, r4, r5, r6, r7, r8, r10, r11, abort=20f + sub.a r2, r2, #32 + str8w r0, r3, r4, r5, r6, r7, r8, r10, r11, abort=20f + beg 3b + +5: and.a ip, r2, #28 + rsub ip, ip, #32 + beq 7f + add pc, pc, ip @ C is always clear here + nop + + ldr1w r1, r3, abort=20f + ldr1w r1, r4, abort=20f + ldr1w r1, r5, abort=20f + ldr1w r1, r6, abort=20f + ldr1w r1, r7, abort=20f + ldr1w r1, r8, abort=20f + ldr1w r1, r11, abort=20f + + add pc, pc, ip + nop + + str1w r0, r3, abort=20f + str1w r0, r4, abort=20f + str1w r0, r5, abort=20f + str1w r0, r6, abort=20f + str1w r0, r7, abort=20f + str1w r0, r8, abort=20f + str1w r0, r11, abort=20f + +7: ldm.w (r5 - r8), [sp]+ + +8: mov.a r2, r2 << #31 + ldr1b r1, r3, ne, abort=21f + ldr1b r1, r4, ea, abort=21f + ldr1b r1, r10, ea, abort=21f + str1b r0, r3, ne, abort=21f + str1b r0, r4, ea, abort=21f + str1b r0, r10, ea, abort=21f + + exit + +9: rsub ip, ip, #4 + csub.a ip, #2 + ldr1b r1, r3, sg, abort=21f + ldr1b r1, r4, eg, abort=21f + ldr1b r1, r11, abort=21f + str1b r0, r3, sg, abort=21f + str1b r0, r4, eg, abort=21f + sub.a r2, r2, ip + str1b r0, r11, abort=21f + bsl 8b + and.a ip, r1, #3 + beq 1b + +10: andn r1, r1, #3 + csub.a ip, #2 + ldr1w r1, r11, abort=21f + beq 17f + bsg 18f + + + .macro forward_copy_shift a b + + sub.a r2, r2, #28 + bsl 14f + +11: stm.w (r5 - r9), [sp-] + +12: + ldr4w r1, r4, r5, r6, r7, abort=19f + mov r3, r11 pull #\a + sub.a r2, r2, #32 + ldr4w r1, r8, r9, r10, r11, abort=19f + or r3, r3, r4 push #\b + mov r4, r4 pull #\a + or r4, r4, r5 push #\b + mov r5, r5 pull #\a + or r5, r5, r6 push #\b + mov r6, r6 pull #\a + or r6, r6, r7 push #\b + mov r7, r7 pull #\a + or r7, r7, r8 push #\b + mov r8, r8 pull #\a + or r8, r8, r9 push #\b + mov r9, r9 pull #\a + or r9, r9, r10 push #\b + mov r10, r10 pull #\a + or r10, r10, r11 push #\b + str8w r0, r3, r4, r5, r6, r7, r8, r9, r10, , abort=19f + beg 12b + + ldm.w (r5 - r9), [sp]+ + +14: and.a ip, r2, #28 + beq 16f + +15: mov r3, r11 pull #\a + ldr1w r1, r11, abort=21f + sub.a ip, ip, #4 + or r3, r3, r11 push #\b + str1w r0, r3, abort=21f + bsg 15b + +16: sub r1, r1, #(\b / 8) + b 8b + + .endm + + + forward_copy_shift a=8 b=24 + +17: forward_copy_shift a=16 b=16 + +18: forward_copy_shift a=24 b=8 + + +/* + * Abort preamble and completion macros. + * If a fixup handler is required then those macros must surround it. + * It is assumed that the fixup code will handle the private part of + * the exit macro. + */ + + .macro copy_abort_preamble +19: ldm.w (r5 - r9), [sp]+ + b 21f +299: .word 0 @ store lr + @ to avoid function call in fixup +20: ldm.w (r5 - r8), [sp]+ +21: + adr r1, 299b + stw lr, [r1] + .endm + + .macro copy_abort_end + adr lr, 299b + ldw pc, [lr] + .endm + diff --git a/arch/unicore32/lib/copy_to_user.S b/arch/unicore32/lib/copy_to_user.S new file mode 100644 index 000000000000..6e22151c840d --- /dev/null +++ b/arch/unicore32/lib/copy_to_user.S @@ -0,0 +1,96 @@ +/* + * linux/arch/unicore32/lib/copy_to_user.S + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/linkage.h> +#include <asm/assembler.h> + +/* + * Prototype: + * + * size_t __copy_to_user(void *to, const void *from, size_t n) + * + * Purpose: + * + * copy a block to user memory from kernel memory + * + * Params: + * + * to = user memory + * from = kernel memory + * n = number of bytes to copy + * + * Return value: + * + * Number of bytes NOT copied. + */ + + .macro ldr1w ptr reg abort + ldw.w \reg, [\ptr]+, #4 + .endm + + .macro ldr4w ptr reg1 reg2 reg3 reg4 abort + ldm.w (\reg1, \reg2, \reg3, \reg4), [\ptr]+ + .endm + + .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort + ldm.w (\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8), [\ptr]+ + .endm + + .macro ldr1b ptr reg cond=al abort + notcond \cond, .+8 + ldb.w \reg, [\ptr]+, #1 + .endm + + .macro str1w ptr reg abort + strusr \reg, \ptr, 4, abort=\abort + .endm + + .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort +100: stm.w (\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8), [\ptr]+ + + .pushsection __ex_table, "a" + .long 100b, \abort + .popsection + .endm + + .macro str1b ptr reg cond=al abort + strusr \reg, \ptr, 1, \cond, abort=\abort + .endm + + .macro enter + mov r3, #0 + stm.w (r0, r2, r3), [sp-] + .endm + + .macro exit + add sp, sp, #8 + ldm.w (r0), [sp]+ + mov pc, lr + .endm + + .text + +WEAK(__copy_to_user) + +#include "copy_template.S" + +ENDPROC(__copy_to_user) + + .pushsection .fixup,"ax" + .align 0 + copy_abort_preamble + ldm.w (r1, r2, r3), [sp]+ + sub r0, r0, r1 + rsub r0, r0, r2 + copy_abort_end + .popsection + diff --git a/arch/unicore32/lib/delay.S b/arch/unicore32/lib/delay.S new file mode 100644 index 000000000000..24664c009e78 --- /dev/null +++ b/arch/unicore32/lib/delay.S @@ -0,0 +1,51 @@ +/* + * linux/arch/unicore32/lib/delay.S + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <asm/param.h> + .text + +.LC0: .word loops_per_jiffy +.LC1: .word (2199023*HZ)>>11 + +/* + * r0 <= 2000 + * lpj <= 0x01ffffff (max. 3355 bogomips) + * HZ <= 1000 + */ + +ENTRY(__udelay) + ldw r2, .LC1 + mul r0, r2, r0 +ENTRY(__const_udelay) @ 0 <= r0 <= 0x7fffff06 + ldw r2, .LC0 + ldw r2, [r2] @ max = 0x01ffffff + mov r0, r0 >> #14 @ max = 0x0001ffff + mov r2, r2 >> #10 @ max = 0x00007fff + mul r0, r2, r0 @ max = 2^32-1 + mov.a r0, r0 >> #6 + cmoveq pc, lr + +/* + * loops = r0 * HZ * loops_per_jiffy / 1000000 + * + * Oh, if only we had a cycle counter... + */ + +@ Delay routine +ENTRY(__delay) + sub.a r0, r0, #2 + bua __delay + mov pc, lr +ENDPROC(__udelay) +ENDPROC(__const_udelay) +ENDPROC(__delay) diff --git a/arch/unicore32/lib/findbit.S b/arch/unicore32/lib/findbit.S new file mode 100644 index 000000000000..c360ce905d8b --- /dev/null +++ b/arch/unicore32/lib/findbit.S @@ -0,0 +1,98 @@ +/* + * linux/arch/unicore32/lib/findbit.S + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/linkage.h> +#include <asm/assembler.h> + .text + +/* + * Purpose : Find a 'zero' bit + * Prototype: int find_first_zero_bit(void *addr, unsigned int maxbit); + */ +__uc32_find_first_zero_bit: + cxor.a r1, #0 + beq 3f + mov r2, #0 +1: ldb r3, [r0+], r2 >> #3 + xor.a r3, r3, #0xff @ invert bits + bne .L_found @ any now set - found zero bit + add r2, r2, #8 @ next bit pointer +2: csub.a r2, r1 @ any more? + bub 1b +3: mov r0, r1 @ no free bits + mov pc, lr + +/* + * Purpose : Find next 'zero' bit + * Prototype: int find_next_zero_bit + * (void *addr, unsigned int maxbit, int offset) + */ +ENTRY(__uc32_find_next_zero_bit) + cxor.a r1, #0 + beq 3b + and.a ip, r2, #7 + beq 1b @ If new byte, goto old routine + ldb r3, [r0+], r2 >> #3 + xor r3, r3, #0xff @ now looking for a 1 bit + mov.a r3, r3 >> ip @ shift off unused bits + bne .L_found + or r2, r2, #7 @ if zero, then no bits here + add r2, r2, #1 @ align bit pointer + b 2b @ loop for next bit +ENDPROC(__uc32_find_next_zero_bit) + +/* + * Purpose : Find a 'one' bit + * Prototype: int find_first_bit + * (const unsigned long *addr, unsigned int maxbit); + */ +__uc32_find_first_bit: + cxor.a r1, #0 + beq 3f + mov r2, #0 +1: ldb r3, [r0+], r2 >> #3 + mov.a r3, r3 + bne .L_found @ any now set - found zero bit + add r2, r2, #8 @ next bit pointer +2: csub.a r2, r1 @ any more? + bub 1b +3: mov r0, r1 @ no free bits + mov pc, lr + +/* + * Purpose : Find next 'one' bit + * Prototype: int find_next_zero_bit + * (void *addr, unsigned int maxbit, int offset) + */ +ENTRY(__uc32_find_next_bit) + cxor.a r1, #0 + beq 3b + and.a ip, r2, #7 + beq 1b @ If new byte, goto old routine + ldb r3, [r0+], r2 >> #3 + mov.a r3, r3 >> ip @ shift off unused bits + bne .L_found + or r2, r2, #7 @ if zero, then no bits here + add r2, r2, #1 @ align bit pointer + b 2b @ loop for next bit +ENDPROC(__uc32_find_next_bit) + +/* + * One or more bits in the LSB of r3 are assumed to be set. + */ +.L_found: + rsub r1, r3, #0 + and r3, r3, r1 + cntlz r3, r3 + rsub r3, r3, #31 + add r0, r2, r3 + mov pc, lr + diff --git a/arch/unicore32/lib/strncpy_from_user.S b/arch/unicore32/lib/strncpy_from_user.S new file mode 100644 index 000000000000..ff6c304d5c7e --- /dev/null +++ b/arch/unicore32/lib/strncpy_from_user.S @@ -0,0 +1,45 @@ +/* + * linux/arch/unicore32/lib/strncpy_from_user.S + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <asm/errno.h> + + .text + .align 5 + +/* + * Copy a string from user space to kernel space. + * r0 = dst, r1 = src, r2 = byte length + * returns the number of characters copied (strlen of copied string), + * -EFAULT on exception, or "len" if we fill the whole buffer + */ +ENTRY(__strncpy_from_user) + mov ip, r1 +1: sub.a r2, r2, #1 + ldrusr r3, r1, 1, ns + bfs 2f + stb.w r3, [r0]+, #1 + cxor.a r3, #0 + bne 1b + sub r1, r1, #1 @ take NUL character out of count +2: sub r0, r1, ip + mov pc, lr +ENDPROC(__strncpy_from_user) + + .pushsection .fixup,"ax" + .align 0 +9001: mov r3, #0 + stb r3, [r0+], #0 @ null terminate + mov r0, #-EFAULT + mov pc, lr + .popsection + diff --git a/arch/unicore32/lib/strnlen_user.S b/arch/unicore32/lib/strnlen_user.S new file mode 100644 index 000000000000..75863030f21d --- /dev/null +++ b/arch/unicore32/lib/strnlen_user.S @@ -0,0 +1,42 @@ +/* + * linux/arch/unicore32/lib/strnlen_user.S + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <asm/errno.h> + + .text + .align 5 + +/* Prototype: unsigned long __strnlen_user(const char *str, long n) + * Purpose : get length of a string in user memory + * Params : str - address of string in user memory + * Returns : length of string *including terminator* + * or zero on exception, or n + 1 if too long + */ +ENTRY(__strnlen_user) + mov r2, r0 +1: + ldrusr r3, r0, 1 + cxor.a r3, #0 + beq 2f + sub.a r1, r1, #1 + bne 1b + add r0, r0, #1 +2: sub r0, r0, r2 + mov pc, lr +ENDPROC(__strnlen_user) + + .pushsection .fixup,"ax" + .align 0 +9001: mov r0, #0 + mov pc, lr + .popsection diff --git a/arch/unicore32/mm/Kconfig b/arch/unicore32/mm/Kconfig new file mode 100644 index 000000000000..5f77fb3c63be --- /dev/null +++ b/arch/unicore32/mm/Kconfig @@ -0,0 +1,50 @@ +comment "Processor Type" + +# Select CPU types depending on the architecture selected. This selects +# which CPUs we support in the kernel image, and the compiler instruction +# optimiser behaviour. + +config CPU_UCV2 + def_bool y + +comment "Processor Features" + +config CPU_ICACHE_DISABLE + bool "Disable I-Cache (I-bit)" + help + Say Y here to disable the processor instruction cache. Unless + you have a reason not to or are unsure, say N. + +config CPU_DCACHE_DISABLE + bool "Disable D-Cache (D-bit)" + help + Say Y here to disable the processor data cache. Unless + you have a reason not to or are unsure, say N. + +config CPU_DCACHE_WRITETHROUGH + bool "Force write through D-cache" + help + Say Y here to use the data cache in writethrough mode. Unless you + specifically require this or are unsure, say N. + +config CPU_DCACHE_LINE_DISABLE + bool "Disable D-cache line ops" + default y + help + Say Y here to disable the data cache line operations. + +config CPU_TLB_SINGLE_ENTRY_DISABLE + bool "Disable TLB single entry ops" + default y + help + Say Y here to disable the TLB single entry operations. + +config SWIOTLB + def_bool y + +config IOMMU_HELPER + def_bool SWIOTLB + +config NEED_SG_DMA_LENGTH + def_bool SWIOTLB + diff --git a/arch/unicore32/mm/Makefile b/arch/unicore32/mm/Makefile new file mode 100644 index 000000000000..46c166699319 --- /dev/null +++ b/arch/unicore32/mm/Makefile @@ -0,0 +1,15 @@ +# +# Makefile for the linux unicore-specific parts of the memory manager. +# + +obj-y := extable.o fault.o init.o pgd.o mmu.o +obj-y += flush.o ioremap.o + +obj-$(CONFIG_SWIOTLB) += dma-swiotlb.o + +obj-$(CONFIG_MODULES) += proc-syms.o + +obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o + +obj-$(CONFIG_CPU_UCV2) += cache-ucv2.o tlb-ucv2.o proc-ucv2.o + diff --git a/arch/unicore32/mm/alignment.c b/arch/unicore32/mm/alignment.c new file mode 100644 index 000000000000..28f576d733ee --- /dev/null +++ b/arch/unicore32/mm/alignment.c @@ -0,0 +1,523 @@ +/* + * linux/arch/unicore32/mm/alignment.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/* + * TODO: + * FPU ldm/stm not handling + */ +#include <linux/compiler.h> +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/string.h> +#include <linux/init.h> +#include <linux/sched.h> +#include <linux/uaccess.h> + +#include <asm/tlbflush.h> +#include <asm/unaligned.h> + +#define CODING_BITS(i) (i & 0xe0000120) + +#define LDST_P_BIT(i) (i & (1 << 28)) /* Preindex */ +#define LDST_U_BIT(i) (i & (1 << 27)) /* Add offset */ +#define LDST_W_BIT(i) (i & (1 << 25)) /* Writeback */ +#define LDST_L_BIT(i) (i & (1 << 24)) /* Load */ + +#define LDST_P_EQ_U(i) ((((i) ^ ((i) >> 1)) & (1 << 27)) == 0) + +#define LDSTH_I_BIT(i) (i & (1 << 26)) /* half-word immed */ +#define LDM_S_BIT(i) (i & (1 << 26)) /* write ASR from BSR */ +#define LDM_H_BIT(i) (i & (1 << 6)) /* select r0-r15 or r16-r31 */ + +#define RN_BITS(i) ((i >> 19) & 31) /* Rn */ +#define RD_BITS(i) ((i >> 14) & 31) /* Rd */ +#define RM_BITS(i) (i & 31) /* Rm */ + +#define REGMASK_BITS(i) (((i & 0x7fe00) >> 3) | (i & 0x3f)) +#define OFFSET_BITS(i) (i & 0x03fff) + +#define SHIFT_BITS(i) ((i >> 9) & 0x1f) +#define SHIFT_TYPE(i) (i & 0xc0) +#define SHIFT_LSL 0x00 +#define SHIFT_LSR 0x40 +#define SHIFT_ASR 0x80 +#define SHIFT_RORRRX 0xc0 + +union offset_union { + unsigned long un; + signed long sn; +}; + +#define TYPE_ERROR 0 +#define TYPE_FAULT 1 +#define TYPE_LDST 2 +#define TYPE_DONE 3 +#define TYPE_SWAP 4 +#define TYPE_COLS 5 /* Coprocessor load/store */ + +#define get8_unaligned_check(val, addr, err) \ + __asm__( \ + "1: ldb.u %1, [%2], #1\n" \ + "2:\n" \ + " .pushsection .fixup,\"ax\"\n" \ + " .align 2\n" \ + "3: mov %0, #1\n" \ + " b 2b\n" \ + " .popsection\n" \ + " .pushsection __ex_table,\"a\"\n" \ + " .align 3\n" \ + " .long 1b, 3b\n" \ + " .popsection\n" \ + : "=r" (err), "=&r" (val), "=r" (addr) \ + : "0" (err), "2" (addr)) + +#define get8t_unaligned_check(val, addr, err) \ + __asm__( \ + "1: ldb.u %1, [%2], #1\n" \ + "2:\n" \ + " .pushsection .fixup,\"ax\"\n" \ + " .align 2\n" \ + "3: mov %0, #1\n" \ + " b 2b\n" \ + " .popsection\n" \ + " .pushsection __ex_table,\"a\"\n" \ + " .align 3\n" \ + " .long 1b, 3b\n" \ + " .popsection\n" \ + : "=r" (err), "=&r" (val), "=r" (addr) \ + : "0" (err), "2" (addr)) + +#define get16_unaligned_check(val, addr) \ + do { \ + unsigned int err = 0, v, a = addr; \ + get8_unaligned_check(val, a, err); \ + get8_unaligned_check(v, a, err); \ + val |= v << 8; \ + if (err) \ + goto fault; \ + } while (0) + +#define put16_unaligned_check(val, addr) \ + do { \ + unsigned int err = 0, v = val, a = addr; \ + __asm__( \ + "1: stb.u %1, [%2], #1\n" \ + " mov %1, %1 >> #8\n" \ + "2: stb.u %1, [%2]\n" \ + "3:\n" \ + " .pushsection .fixup,\"ax\"\n" \ + " .align 2\n" \ + "4: mov %0, #1\n" \ + " b 3b\n" \ + " .popsection\n" \ + " .pushsection __ex_table,\"a\"\n" \ + " .align 3\n" \ + " .long 1b, 4b\n" \ + " .long 2b, 4b\n" \ + " .popsection\n" \ + : "=r" (err), "=&r" (v), "=&r" (a) \ + : "0" (err), "1" (v), "2" (a)); \ + if (err) \ + goto fault; \ + } while (0) + +#define __put32_unaligned_check(ins, val, addr) \ + do { \ + unsigned int err = 0, v = val, a = addr; \ + __asm__( \ + "1: "ins" %1, [%2], #1\n" \ + " mov %1, %1 >> #8\n" \ + "2: "ins" %1, [%2], #1\n" \ + " mov %1, %1 >> #8\n" \ + "3: "ins" %1, [%2], #1\n" \ + " mov %1, %1 >> #8\n" \ + "4: "ins" %1, [%2]\n" \ + "5:\n" \ + " .pushsection .fixup,\"ax\"\n" \ + " .align 2\n" \ + "6: mov %0, #1\n" \ + " b 5b\n" \ + " .popsection\n" \ + " .pushsection __ex_table,\"a\"\n" \ + " .align 3\n" \ + " .long 1b, 6b\n" \ + " .long 2b, 6b\n" \ + " .long 3b, 6b\n" \ + " .long 4b, 6b\n" \ + " .popsection\n" \ + : "=r" (err), "=&r" (v), "=&r" (a) \ + : "0" (err), "1" (v), "2" (a)); \ + if (err) \ + goto fault; \ + } while (0) + +#define get32_unaligned_check(val, addr) \ + do { \ + unsigned int err = 0, v, a = addr; \ + get8_unaligned_check(val, a, err); \ + get8_unaligned_check(v, a, err); \ + val |= v << 8; \ + get8_unaligned_check(v, a, err); \ + val |= v << 16; \ + get8_unaligned_check(v, a, err); \ + val |= v << 24; \ + if (err) \ + goto fault; \ + } while (0) + +#define put32_unaligned_check(val, addr) \ + __put32_unaligned_check("stb.u", val, addr) + +#define get32t_unaligned_check(val, addr) \ + do { \ + unsigned int err = 0, v, a = addr; \ + get8t_unaligned_check(val, a, err); \ + get8t_unaligned_check(v, a, err); \ + val |= v << 8; \ + get8t_unaligned_check(v, a, err); \ + val |= v << 16; \ + get8t_unaligned_check(v, a, err); \ + val |= v << 24; \ + if (err) \ + goto fault; \ + } while (0) + +#define put32t_unaligned_check(val, addr) \ + __put32_unaligned_check("stb.u", val, addr) + +static void +do_alignment_finish_ldst(unsigned long addr, unsigned long instr, + struct pt_regs *regs, union offset_union offset) +{ + if (!LDST_U_BIT(instr)) + offset.un = -offset.un; + + if (!LDST_P_BIT(instr)) + addr += offset.un; + + if (!LDST_P_BIT(instr) || LDST_W_BIT(instr)) + regs->uregs[RN_BITS(instr)] = addr; +} + +static int +do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, + struct pt_regs *regs) +{ + unsigned int rd = RD_BITS(instr); + + /* old value 0x40002120, can't judge swap instr correctly */ + if ((instr & 0x4b003fe0) == 0x40000120) + goto swp; + + if (LDST_L_BIT(instr)) { + unsigned long val; + get16_unaligned_check(val, addr); + + /* signed half-word? */ + if (instr & 0x80) + val = (signed long)((signed short)val); + + regs->uregs[rd] = val; + } else + put16_unaligned_check(regs->uregs[rd], addr); + + return TYPE_LDST; + +swp: + /* only handle swap word + * for swap byte should not active this alignment exception */ + get32_unaligned_check(regs->uregs[RD_BITS(instr)], addr); + put32_unaligned_check(regs->uregs[RM_BITS(instr)], addr); + return TYPE_SWAP; + +fault: + return TYPE_FAULT; +} + +static int +do_alignment_ldrstr(unsigned long addr, unsigned long instr, + struct pt_regs *regs) +{ + unsigned int rd = RD_BITS(instr); + + if (!LDST_P_BIT(instr) && LDST_W_BIT(instr)) + goto trans; + + if (LDST_L_BIT(instr)) + get32_unaligned_check(regs->uregs[rd], addr); + else + put32_unaligned_check(regs->uregs[rd], addr); + return TYPE_LDST; + +trans: + if (LDST_L_BIT(instr)) + get32t_unaligned_check(regs->uregs[rd], addr); + else + put32t_unaligned_check(regs->uregs[rd], addr); + return TYPE_LDST; + +fault: + return TYPE_FAULT; +} + +/* + * LDM/STM alignment handler. + * + * There are 4 variants of this instruction: + * + * B = rn pointer before instruction, A = rn pointer after instruction + * ------ increasing address -----> + * | | r0 | r1 | ... | rx | | + * PU = 01 B A + * PU = 11 B A + * PU = 00 A B + * PU = 10 A B + */ +static int +do_alignment_ldmstm(unsigned long addr, unsigned long instr, + struct pt_regs *regs) +{ + unsigned int rd, rn, pc_correction, reg_correction, nr_regs, regbits; + unsigned long eaddr, newaddr; + + if (LDM_S_BIT(instr)) + goto bad; + + pc_correction = 4; /* processor implementation defined */ + + /* count the number of registers in the mask to be transferred */ + nr_regs = hweight16(REGMASK_BITS(instr)) * 4; + + rn = RN_BITS(instr); + newaddr = eaddr = regs->uregs[rn]; + + if (!LDST_U_BIT(instr)) + nr_regs = -nr_regs; + newaddr += nr_regs; + if (!LDST_U_BIT(instr)) + eaddr = newaddr; + + if (LDST_P_EQ_U(instr)) /* U = P */ + eaddr += 4; + + /* + * This is a "hint" - we already have eaddr worked out by the + * processor for us. + */ + if (addr != eaddr) { + printk(KERN_ERR "LDMSTM: PC = %08lx, instr = %08lx, " + "addr = %08lx, eaddr = %08lx\n", + instruction_pointer(regs), instr, addr, eaddr); + show_regs(regs); + } + + if (LDM_H_BIT(instr)) + reg_correction = 0x10; + else + reg_correction = 0x00; + + for (regbits = REGMASK_BITS(instr), rd = 0; regbits; + regbits >>= 1, rd += 1) + if (regbits & 1) { + if (LDST_L_BIT(instr)) + get32_unaligned_check(regs-> + uregs[rd + reg_correction], eaddr); + else + put32_unaligned_check(regs-> + uregs[rd + reg_correction], eaddr); + eaddr += 4; + } + + if (LDST_W_BIT(instr)) + regs->uregs[rn] = newaddr; + return TYPE_DONE; + +fault: + regs->UCreg_pc -= pc_correction; + return TYPE_FAULT; + +bad: + printk(KERN_ERR "Alignment trap: not handling ldm with s-bit set\n"); + return TYPE_ERROR; +} + +static int +do_alignment(unsigned long addr, unsigned int error_code, struct pt_regs *regs) +{ + union offset_union offset; + unsigned long instr, instrptr; + int (*handler) (unsigned long addr, unsigned long instr, + struct pt_regs *regs); + unsigned int type; + + instrptr = instruction_pointer(regs); + if (instrptr >= PAGE_OFFSET) + instr = *(unsigned long *)instrptr; + else { + __asm__ __volatile__( + "ldw.u %0, [%1]\n" + : "=&r"(instr) + : "r"(instrptr)); + } + + regs->UCreg_pc += 4; + + switch (CODING_BITS(instr)) { + case 0x40000120: /* ldrh or strh */ + if (LDSTH_I_BIT(instr)) + offset.un = (instr & 0x3e00) >> 4 | (instr & 31); + else + offset.un = regs->uregs[RM_BITS(instr)]; + handler = do_alignment_ldrhstrh; + break; + + case 0x60000000: /* ldr or str immediate */ + case 0x60000100: /* ldr or str immediate */ + case 0x60000020: /* ldr or str immediate */ + case 0x60000120: /* ldr or str immediate */ + offset.un = OFFSET_BITS(instr); + handler = do_alignment_ldrstr; + break; + + case 0x40000000: /* ldr or str register */ + offset.un = regs->uregs[RM_BITS(instr)]; + { + unsigned int shiftval = SHIFT_BITS(instr); + + switch (SHIFT_TYPE(instr)) { + case SHIFT_LSL: + offset.un <<= shiftval; + break; + + case SHIFT_LSR: + offset.un >>= shiftval; + break; + + case SHIFT_ASR: + offset.sn >>= shiftval; + break; + + case SHIFT_RORRRX: + if (shiftval == 0) { + offset.un >>= 1; + if (regs->UCreg_asr & PSR_C_BIT) + offset.un |= 1 << 31; + } else + offset.un = offset.un >> shiftval | + offset.un << (32 - shiftval); + break; + } + } + handler = do_alignment_ldrstr; + break; + + case 0x80000000: /* ldm or stm */ + case 0x80000020: /* ldm or stm */ + handler = do_alignment_ldmstm; + break; + + default: + goto bad; + } + + type = handler(addr, instr, regs); + + if (type == TYPE_ERROR || type == TYPE_FAULT) + goto bad_or_fault; + + if (type == TYPE_LDST) + do_alignment_finish_ldst(addr, instr, regs, offset); + + return 0; + +bad_or_fault: + if (type == TYPE_ERROR) + goto bad; + regs->UCreg_pc -= 4; + /* + * We got a fault - fix it up, or die. + */ + do_bad_area(addr, error_code, regs); + return 0; + +bad: + /* + * Oops, we didn't handle the instruction. + * However, we must handle fpu instr firstly. + */ +#ifdef CONFIG_UNICORE_FPU_F64 + /* handle co.load/store */ +#define CODING_COLS 0xc0000000 +#define COLS_OFFSET_BITS(i) (i & 0x1FF) +#define COLS_L_BITS(i) (i & (1<<24)) +#define COLS_FN_BITS(i) ((i>>14) & 31) + if ((instr & 0xe0000000) == CODING_COLS) { + unsigned int fn = COLS_FN_BITS(instr); + unsigned long val = 0; + if (COLS_L_BITS(instr)) { + get32t_unaligned_check(val, addr); + switch (fn) { +#define ASM_MTF(n) case n: \ + __asm__ __volatile__("MTF %0, F" __stringify(n) \ + : : "r"(val)); \ + break; + ASM_MTF(0); ASM_MTF(1); ASM_MTF(2); ASM_MTF(3); + ASM_MTF(4); ASM_MTF(5); ASM_MTF(6); ASM_MTF(7); + ASM_MTF(8); ASM_MTF(9); ASM_MTF(10); ASM_MTF(11); + ASM_MTF(12); ASM_MTF(13); ASM_MTF(14); ASM_MTF(15); + ASM_MTF(16); ASM_MTF(17); ASM_MTF(18); ASM_MTF(19); + ASM_MTF(20); ASM_MTF(21); ASM_MTF(22); ASM_MTF(23); + ASM_MTF(24); ASM_MTF(25); ASM_MTF(26); ASM_MTF(27); + ASM_MTF(28); ASM_MTF(29); ASM_MTF(30); ASM_MTF(31); +#undef ASM_MTF + } + } else { + switch (fn) { +#define ASM_MFF(n) case n: \ + __asm__ __volatile__("MFF %0, F" __stringify(n) \ + : : "r"(val)); \ + break; + ASM_MFF(0); ASM_MFF(1); ASM_MFF(2); ASM_MFF(3); + ASM_MFF(4); ASM_MFF(5); ASM_MFF(6); ASM_MFF(7); + ASM_MFF(8); ASM_MFF(9); ASM_MFF(10); ASM_MFF(11); + ASM_MFF(12); ASM_MFF(13); ASM_MFF(14); ASM_MFF(15); + ASM_MFF(16); ASM_MFF(17); ASM_MFF(18); ASM_MFF(19); + ASM_MFF(20); ASM_MFF(21); ASM_MFF(22); ASM_MFF(23); + ASM_MFF(24); ASM_MFF(25); ASM_MFF(26); ASM_MFF(27); + ASM_MFF(28); ASM_MFF(29); ASM_MFF(30); ASM_MFF(31); +#undef ASM_MFF + } + put32t_unaligned_check(val, addr); + } + return TYPE_COLS; + } +fault: + return TYPE_FAULT; +#endif + printk(KERN_ERR "Alignment trap: not handling instruction " + "%08lx at [<%08lx>]\n", instr, instrptr); + return 1; +} + +/* + * This needs to be done after sysctl_init, otherwise sys/ will be + * overwritten. Actually, this shouldn't be in sys/ at all since + * it isn't a sysctl, and it doesn't contain sysctl information. + */ +static int __init alignment_init(void) +{ + hook_fault_code(1, do_alignment, SIGBUS, BUS_ADRALN, + "alignment exception"); + + return 0; +} + +fs_initcall(alignment_init); diff --git a/arch/unicore32/mm/cache-ucv2.S b/arch/unicore32/mm/cache-ucv2.S new file mode 100644 index 000000000000..ecaa1727f906 --- /dev/null +++ b/arch/unicore32/mm/cache-ucv2.S @@ -0,0 +1,212 @@ +/* + * linux/arch/unicore32/mm/cache-ucv2.S + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This is the "shell" of the UniCore-v2 processor support. + */ +#include <linux/linkage.h> +#include <linux/init.h> +#include <asm/assembler.h> +#include <asm/page.h> + +#include "proc-macros.S" + +/* + * __cpuc_flush_icache_all() + * __cpuc_flush_kern_all() + * __cpuc_flush_user_all() + * + * Flush the entire cache. + */ +ENTRY(__cpuc_flush_icache_all) + /*FALLTHROUGH*/ +ENTRY(__cpuc_flush_kern_all) + /*FALLTHROUGH*/ +ENTRY(__cpuc_flush_user_all) + mov r0, #0 + movc p0.c5, r0, #14 @ Dcache flush all + nop8 + + mov r0, #0 + movc p0.c5, r0, #20 @ Icache invalidate all + nop8 + + mov pc, lr + +/* + * __cpuc_flush_user_range(start, end, flags) + * + * Flush a range of TLB entries in the specified address space. + * + * - start - start address (may not be aligned) + * - end - end address (exclusive, may not be aligned) + * - flags - vm_area_struct flags describing address space + */ +ENTRY(__cpuc_flush_user_range) + cxor.a r2, #0 + beq __cpuc_dma_flush_range + +#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE + andn r0, r0, #CACHE_LINESIZE - 1 @ Safety check + sub r1, r1, r0 + csub.a r1, #MAX_AREA_SIZE + bsg 2f + + andn r1, r1, #CACHE_LINESIZE - 1 + add r1, r1, #CACHE_LINESIZE + +101: dcacheline_flush r0, r11, r12 + + add r0, r0, #CACHE_LINESIZE + sub.a r1, r1, #CACHE_LINESIZE + bns 101b + b 3f +#endif +2: mov ip, #0 + movc p0.c5, ip, #14 @ Dcache flush all + nop8 + +3: mov ip, #0 + movc p0.c5, ip, #20 @ Icache invalidate all + nop8 + + mov pc, lr + +/* + * __cpuc_coherent_kern_range(start,end) + * __cpuc_coherent_user_range(start,end) + * + * Ensure that the I and D caches are coherent within specified + * region. This is typically used when code has been written to + * a memory region, and will be executed. + * + * - start - virtual start address of region + * - end - virtual end address of region + */ +ENTRY(__cpuc_coherent_kern_range) + /* FALLTHROUGH */ +ENTRY(__cpuc_coherent_user_range) +#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE + andn r0, r0, #CACHE_LINESIZE - 1 @ Safety check + sub r1, r1, r0 + csub.a r1, #MAX_AREA_SIZE + bsg 2f + + andn r1, r1, #CACHE_LINESIZE - 1 + add r1, r1, #CACHE_LINESIZE + + @ r0 va2pa r10 + mov r9, #PAGE_SZ + sub r9, r9, #1 @ PAGE_MASK +101: va2pa r0, r10, r11, r12, r13, 2f @ r10 is PA + b 103f +102: cand.a r0, r9 + beq 101b + +103: movc p0.c5, r10, #11 @ Dcache clean line of R10 + nop8 + + add r0, r0, #CACHE_LINESIZE + add r10, r10, #CACHE_LINESIZE + sub.a r1, r1, #CACHE_LINESIZE + bns 102b + b 3f +#endif +2: mov ip, #0 + movc p0.c5, ip, #10 @ Dcache clean all + nop8 + +3: mov ip, #0 + movc p0.c5, ip, #20 @ Icache invalidate all + nop8 + + mov pc, lr + +/* + * __cpuc_flush_kern_dcache_area(void *addr, size_t size) + * + * - addr - kernel address + * - size - region size + */ +ENTRY(__cpuc_flush_kern_dcache_area) + mov ip, #0 + movc p0.c5, ip, #14 @ Dcache flush all + nop8 + mov pc, lr + +/* + * __cpuc_dma_clean_range(start,end) + * - start - virtual start address of region + * - end - virtual end address of region + */ +ENTRY(__cpuc_dma_clean_range) +#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE + andn r0, r0, #CACHE_LINESIZE - 1 + sub r1, r1, r0 + andn r1, r1, #CACHE_LINESIZE - 1 + add r1, r1, #CACHE_LINESIZE + + csub.a r1, #MAX_AREA_SIZE + bsg 2f + + @ r0 va2pa r10 + mov r9, #PAGE_SZ + sub r9, r9, #1 @ PAGE_MASK +101: va2pa r0, r10, r11, r12, r13, 2f @ r10 is PA + b 1f +102: cand.a r0, r9 + beq 101b + +1: movc p0.c5, r10, #11 @ Dcache clean line of R10 + nop8 + add r0, r0, #CACHE_LINESIZE + add r10, r10, #CACHE_LINESIZE + sub.a r1, r1, #CACHE_LINESIZE + bns 102b + mov pc, lr +#endif +2: mov ip, #0 + movc p0.c5, ip, #10 @ Dcache clean all + nop8 + + mov pc, lr + +/* + * __cpuc_dma_inv_range(start,end) + * __cpuc_dma_flush_range(start,end) + * - start - virtual start address of region + * - end - virtual end address of region + */ +__cpuc_dma_inv_range: + /* FALLTHROUGH */ +ENTRY(__cpuc_dma_flush_range) +#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE + andn r0, r0, #CACHE_LINESIZE - 1 + sub r1, r1, r0 + andn r1, r1, #CACHE_LINESIZE - 1 + add r1, r1, #CACHE_LINESIZE + + csub.a r1, #MAX_AREA_SIZE + bsg 2f + + @ r0 va2pa r10 +101: dcacheline_flush r0, r11, r12 + + add r0, r0, #CACHE_LINESIZE + sub.a r1, r1, #CACHE_LINESIZE + bns 101b + mov pc, lr +#endif +2: mov ip, #0 + movc p0.c5, ip, #14 @ Dcache flush all + nop8 + + mov pc, lr + diff --git a/arch/unicore32/mm/dma-swiotlb.c b/arch/unicore32/mm/dma-swiotlb.c new file mode 100644 index 000000000000..bfa9fbb2bbb1 --- /dev/null +++ b/arch/unicore32/mm/dma-swiotlb.c @@ -0,0 +1,34 @@ +/* + * Contains routines needed to support swiotlb for UniCore32. + * + * Copyright (C) 2010 Guan Xuetao + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include <linux/pci.h> +#include <linux/cache.h> +#include <linux/module.h> +#include <linux/dma-mapping.h> +#include <linux/swiotlb.h> +#include <linux/bootmem.h> + +#include <asm/dma.h> + +struct dma_map_ops swiotlb_dma_map_ops = { + .alloc_coherent = swiotlb_alloc_coherent, + .free_coherent = swiotlb_free_coherent, + .map_sg = swiotlb_map_sg_attrs, + .unmap_sg = swiotlb_unmap_sg_attrs, + .dma_supported = swiotlb_dma_supported, + .map_page = swiotlb_map_page, + .unmap_page = swiotlb_unmap_page, + .sync_single_for_cpu = swiotlb_sync_single_for_cpu, + .sync_single_for_device = swiotlb_sync_single_for_device, + .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu, + .sync_sg_for_device = swiotlb_sync_sg_for_device, + .mapping_error = swiotlb_dma_mapping_error, +}; +EXPORT_SYMBOL(swiotlb_dma_map_ops); diff --git a/arch/unicore32/mm/extable.c b/arch/unicore32/mm/extable.c new file mode 100644 index 000000000000..6564180eb285 --- /dev/null +++ b/arch/unicore32/mm/extable.c @@ -0,0 +1,24 @@ +/* + * linux/arch/unicore32/mm/extable.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/module.h> +#include <linux/uaccess.h> + +int fixup_exception(struct pt_regs *regs) +{ + const struct exception_table_entry *fixup; + + fixup = search_exception_tables(instruction_pointer(regs)); + if (fixup) + regs->UCreg_pc = fixup->fixup; + + return fixup != NULL; +} diff --git a/arch/unicore32/mm/fault.c b/arch/unicore32/mm/fault.c new file mode 100644 index 000000000000..283aa4b50b7a --- /dev/null +++ b/arch/unicore32/mm/fault.c @@ -0,0 +1,479 @@ +/* + * linux/arch/unicore32/mm/fault.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/module.h> +#include <linux/signal.h> +#include <linux/mm.h> +#include <linux/hardirq.h> +#include <linux/init.h> +#include <linux/kprobes.h> +#include <linux/uaccess.h> +#include <linux/page-flags.h> +#include <linux/sched.h> +#include <linux/io.h> + +#include <asm/system.h> +#include <asm/pgtable.h> +#include <asm/tlbflush.h> + +/* + * Fault status register encodings. We steal bit 31 for our own purposes. + */ +#define FSR_LNX_PF (1 << 31) + +static inline int fsr_fs(unsigned int fsr) +{ + /* xyabcde will be abcde+xy */ + return (fsr & 31) + ((fsr & (3 << 5)) >> 5); +} + +/* + * This is useful to dump out the page tables associated with + * 'addr' in mm 'mm'. + */ +void show_pte(struct mm_struct *mm, unsigned long addr) +{ + pgd_t *pgd; + + if (!mm) + mm = &init_mm; + + printk(KERN_ALERT "pgd = %p\n", mm->pgd); + pgd = pgd_offset(mm, addr); + printk(KERN_ALERT "[%08lx] *pgd=%08lx", addr, pgd_val(*pgd)); + + do { + pmd_t *pmd; + pte_t *pte; + + if (pgd_none(*pgd)) + break; + + if (pgd_bad(*pgd)) { + printk("(bad)"); + break; + } + + pmd = pmd_offset((pud_t *) pgd, addr); + if (PTRS_PER_PMD != 1) + printk(", *pmd=%08lx", pmd_val(*pmd)); + + if (pmd_none(*pmd)) + break; + + if (pmd_bad(*pmd)) { + printk("(bad)"); + break; + } + + /* We must not map this if we have highmem enabled */ + if (PageHighMem(pfn_to_page(pmd_val(*pmd) >> PAGE_SHIFT))) + break; + + pte = pte_offset_map(pmd, addr); + printk(", *pte=%08lx", pte_val(*pte)); + pte_unmap(pte); + } while (0); + + printk("\n"); +} + +/* + * Oops. The kernel tried to access some page that wasn't present. + */ +static void __do_kernel_fault(struct mm_struct *mm, unsigned long addr, + unsigned int fsr, struct pt_regs *regs) +{ + /* + * Are we prepared to handle this kernel fault? + */ + if (fixup_exception(regs)) + return; + + /* + * No handler, we'll have to terminate things with extreme prejudice. + */ + bust_spinlocks(1); + printk(KERN_ALERT + "Unable to handle kernel %s at virtual address %08lx\n", + (addr < PAGE_SIZE) ? "NULL pointer dereference" : + "paging request", addr); + + show_pte(mm, addr); + die("Oops", regs, fsr); + bust_spinlocks(0); + do_exit(SIGKILL); +} + +/* + * Something tried to access memory that isn't in our memory map.. + * User mode accesses just cause a SIGSEGV + */ +static void __do_user_fault(struct task_struct *tsk, unsigned long addr, + unsigned int fsr, unsigned int sig, int code, + struct pt_regs *regs) +{ + struct siginfo si; + + tsk->thread.address = addr; + tsk->thread.error_code = fsr; + tsk->thread.trap_no = 14; + si.si_signo = sig; + si.si_errno = 0; + si.si_code = code; + si.si_addr = (void __user *)addr; + force_sig_info(sig, &si, tsk); +} + +void do_bad_area(unsigned long addr, unsigned int fsr, struct pt_regs *regs) +{ + struct task_struct *tsk = current; + struct mm_struct *mm = tsk->active_mm; + + /* + * If we are in kernel mode at this point, we + * have no context to handle this fault with. + */ + if (user_mode(regs)) + __do_user_fault(tsk, addr, fsr, SIGSEGV, SEGV_MAPERR, regs); + else + __do_kernel_fault(mm, addr, fsr, regs); +} + +#define VM_FAULT_BADMAP 0x010000 +#define VM_FAULT_BADACCESS 0x020000 + +/* + * Check that the permissions on the VMA allow for the fault which occurred. + * If we encountered a write fault, we must have write permission, otherwise + * we allow any permission. + */ +static inline bool access_error(unsigned int fsr, struct vm_area_struct *vma) +{ + unsigned int mask = VM_READ | VM_WRITE | VM_EXEC; + + if (!(fsr ^ 0x12)) /* write? */ + mask = VM_WRITE; + if (fsr & FSR_LNX_PF) + mask = VM_EXEC; + + return vma->vm_flags & mask ? false : true; +} + +static int __do_pf(struct mm_struct *mm, unsigned long addr, unsigned int fsr, + struct task_struct *tsk) +{ + struct vm_area_struct *vma; + int fault; + + vma = find_vma(mm, addr); + fault = VM_FAULT_BADMAP; + if (unlikely(!vma)) + goto out; + if (unlikely(vma->vm_start > addr)) + goto check_stack; + + /* + * Ok, we have a good vm_area for this + * memory access, so we can handle it. + */ +good_area: + if (access_error(fsr, vma)) { + fault = VM_FAULT_BADACCESS; + goto out; + } + + /* + * If for any reason at all we couldn't handle the fault, make + * sure we exit gracefully rather than endlessly redo the fault. + */ + fault = handle_mm_fault(mm, vma, addr & PAGE_MASK, + (!(fsr ^ 0x12)) ? FAULT_FLAG_WRITE : 0); + if (unlikely(fault & VM_FAULT_ERROR)) + return fault; + if (fault & VM_FAULT_MAJOR) + tsk->maj_flt++; + else + tsk->min_flt++; + return fault; + +check_stack: + if (vma->vm_flags & VM_GROWSDOWN && !expand_stack(vma, addr)) + goto good_area; +out: + return fault; +} + +static int do_pf(unsigned long addr, unsigned int fsr, struct pt_regs *regs) +{ + struct task_struct *tsk; + struct mm_struct *mm; + int fault, sig, code; + + tsk = current; + mm = tsk->mm; + + /* + * If we're in an interrupt or have no user + * context, we must not take the fault.. + */ + if (in_atomic() || !mm) + goto no_context; + + /* + * As per x86, we may deadlock here. However, since the kernel only + * validly references user space from well defined areas of the code, + * we can bug out early if this is from code which shouldn't. + */ + if (!down_read_trylock(&mm->mmap_sem)) { + if (!user_mode(regs) + && !search_exception_tables(regs->UCreg_pc)) + goto no_context; + down_read(&mm->mmap_sem); + } else { + /* + * The above down_read_trylock() might have succeeded in + * which case, we'll have missed the might_sleep() from + * down_read() + */ + might_sleep(); +#ifdef CONFIG_DEBUG_VM + if (!user_mode(regs) && + !search_exception_tables(regs->UCreg_pc)) + goto no_context; +#endif + } + + fault = __do_pf(mm, addr, fsr, tsk); + up_read(&mm->mmap_sem); + + /* + * Handle the "normal" case first - VM_FAULT_MAJOR / VM_FAULT_MINOR + */ + if (likely(!(fault & + (VM_FAULT_ERROR | VM_FAULT_BADMAP | VM_FAULT_BADACCESS)))) + return 0; + + if (fault & VM_FAULT_OOM) { + /* + * We ran out of memory, call the OOM killer, and return to + * userspace (which will retry the fault, or kill us if we + * got oom-killed) + */ + pagefault_out_of_memory(); + return 0; + } + + /* + * If we are in kernel mode at this point, we + * have no context to handle this fault with. + */ + if (!user_mode(regs)) + goto no_context; + + if (fault & VM_FAULT_SIGBUS) { + /* + * We had some memory, but were unable to + * successfully fix up this page fault. + */ + sig = SIGBUS; + code = BUS_ADRERR; + } else { + /* + * Something tried to access memory that + * isn't in our memory map.. + */ + sig = SIGSEGV; + code = fault == VM_FAULT_BADACCESS ? SEGV_ACCERR : SEGV_MAPERR; + } + + __do_user_fault(tsk, addr, fsr, sig, code, regs); + return 0; + +no_context: + __do_kernel_fault(mm, addr, fsr, regs); + return 0; +} + +/* + * First Level Translation Fault Handler + * + * We enter here because the first level page table doesn't contain + * a valid entry for the address. + * + * If the address is in kernel space (>= TASK_SIZE), then we are + * probably faulting in the vmalloc() area. + * + * If the init_task's first level page tables contains the relevant + * entry, we copy the it to this task. If not, we send the process + * a signal, fixup the exception, or oops the kernel. + * + * NOTE! We MUST NOT take any locks for this case. We may be in an + * interrupt or a critical region, and should only copy the information + * from the master page table, nothing more. + */ +static int do_ifault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) +{ + unsigned int index; + pgd_t *pgd, *pgd_k; + pmd_t *pmd, *pmd_k; + + if (addr < TASK_SIZE) + return do_pf(addr, fsr, regs); + + if (user_mode(regs)) + goto bad_area; + + index = pgd_index(addr); + + pgd = cpu_get_pgd() + index; + pgd_k = init_mm.pgd + index; + + if (pgd_none(*pgd_k)) + goto bad_area; + + pmd_k = pmd_offset((pud_t *) pgd_k, addr); + pmd = pmd_offset((pud_t *) pgd, addr); + + if (pmd_none(*pmd_k)) + goto bad_area; + + set_pmd(pmd, *pmd_k); + flush_pmd_entry(pmd); + return 0; + +bad_area: + do_bad_area(addr, fsr, regs); + return 0; +} + +/* + * This abort handler always returns "fault". + */ +static int do_bad(unsigned long addr, unsigned int fsr, struct pt_regs *regs) +{ + return 1; +} + +static int do_good(unsigned long addr, unsigned int fsr, struct pt_regs *regs) +{ + unsigned int res1, res2; + + printk("dabt exception but no error!\n"); + + __asm__ __volatile__( + "mff %0,f0\n" + "mff %1,f1\n" + : "=r"(res1), "=r"(res2) + : + : "memory"); + + printk(KERN_EMERG "r0 :%08x r1 :%08x\n", res1, res2); + panic("shut up\n"); + return 0; +} + +static struct fsr_info { + int (*fn) (unsigned long addr, unsigned int fsr, struct pt_regs *regs); + int sig; + int code; + const char *name; +} fsr_info[] = { + /* + * The following are the standard Unicore-I and UniCore-II aborts. + */ + { do_good, SIGBUS, 0, "no error" }, + { do_bad, SIGBUS, BUS_ADRALN, "alignment exception" }, + { do_bad, SIGBUS, BUS_OBJERR, "external exception" }, + { do_bad, SIGBUS, 0, "burst operation" }, + { do_bad, SIGBUS, 0, "unknown 00100" }, + { do_ifault, SIGSEGV, SEGV_MAPERR, "2nd level pt non-exist"}, + { do_bad, SIGBUS, 0, "2nd lvl large pt non-exist" }, + { do_bad, SIGBUS, 0, "invalid pte" }, + { do_pf, SIGSEGV, SEGV_MAPERR, "page miss" }, + { do_bad, SIGBUS, 0, "middle page miss" }, + { do_bad, SIGBUS, 0, "large page miss" }, + { do_pf, SIGSEGV, SEGV_MAPERR, "super page (section) miss" }, + { do_bad, SIGBUS, 0, "unknown 01100" }, + { do_bad, SIGBUS, 0, "unknown 01101" }, + { do_bad, SIGBUS, 0, "unknown 01110" }, + { do_bad, SIGBUS, 0, "unknown 01111" }, + { do_bad, SIGBUS, 0, "addr: up 3G or IO" }, + { do_pf, SIGSEGV, SEGV_ACCERR, "read unreadable addr" }, + { do_pf, SIGSEGV, SEGV_ACCERR, "write unwriteable addr"}, + { do_pf, SIGSEGV, SEGV_ACCERR, "exec unexecutable addr"}, + { do_bad, SIGBUS, 0, "unknown 10100" }, + { do_bad, SIGBUS, 0, "unknown 10101" }, + { do_bad, SIGBUS, 0, "unknown 10110" }, + { do_bad, SIGBUS, 0, "unknown 10111" }, + { do_bad, SIGBUS, 0, "unknown 11000" }, + { do_bad, SIGBUS, 0, "unknown 11001" }, + { do_bad, SIGBUS, 0, "unknown 11010" }, + { do_bad, SIGBUS, 0, "unknown 11011" }, + { do_bad, SIGBUS, 0, "unknown 11100" }, + { do_bad, SIGBUS, 0, "unknown 11101" }, + { do_bad, SIGBUS, 0, "unknown 11110" }, + { do_bad, SIGBUS, 0, "unknown 11111" } +}; + +void __init hook_fault_code(int nr, + int (*fn) (unsigned long, unsigned int, struct pt_regs *), + int sig, int code, const char *name) +{ + if (nr < 0 || nr >= ARRAY_SIZE(fsr_info)) + BUG(); + + fsr_info[nr].fn = fn; + fsr_info[nr].sig = sig; + fsr_info[nr].code = code; + fsr_info[nr].name = name; +} + +/* + * Dispatch a data abort to the relevant handler. + */ +asmlinkage void do_DataAbort(unsigned long addr, unsigned int fsr, + struct pt_regs *regs) +{ + const struct fsr_info *inf = fsr_info + fsr_fs(fsr); + struct siginfo info; + + if (!inf->fn(addr, fsr & ~FSR_LNX_PF, regs)) + return; + + printk(KERN_ALERT "Unhandled fault: %s (0x%03x) at 0x%08lx\n", + inf->name, fsr, addr); + + info.si_signo = inf->sig; + info.si_errno = 0; + info.si_code = inf->code; + info.si_addr = (void __user *)addr; + uc32_notify_die("", regs, &info, fsr, 0); +} + +asmlinkage void do_PrefetchAbort(unsigned long addr, + unsigned int ifsr, struct pt_regs *regs) +{ + const struct fsr_info *inf = fsr_info + fsr_fs(ifsr); + struct siginfo info; + + if (!inf->fn(addr, ifsr | FSR_LNX_PF, regs)) + return; + + printk(KERN_ALERT "Unhandled prefetch abort: %s (0x%03x) at 0x%08lx\n", + inf->name, ifsr, addr); + + info.si_signo = inf->sig; + info.si_errno = 0; + info.si_code = inf->code; + info.si_addr = (void __user *)addr; + uc32_notify_die("", regs, &info, ifsr, 0); +} diff --git a/arch/unicore32/mm/flush.c b/arch/unicore32/mm/flush.c new file mode 100644 index 000000000000..93478cc8b26d --- /dev/null +++ b/arch/unicore32/mm/flush.c @@ -0,0 +1,98 @@ +/* + * linux/arch/unicore32/mm/flush.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/module.h> +#include <linux/mm.h> +#include <linux/pagemap.h> + +#include <asm/cacheflush.h> +#include <asm/system.h> +#include <asm/tlbflush.h> + +void flush_cache_mm(struct mm_struct *mm) +{ +} + +void flush_cache_range(struct vm_area_struct *vma, unsigned long start, + unsigned long end) +{ + if (vma->vm_flags & VM_EXEC) + __flush_icache_all(); +} + +void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, + unsigned long pfn) +{ +} + +static void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, + unsigned long uaddr, void *kaddr, unsigned long len) +{ + /* VIPT non-aliasing D-cache */ + if (vma->vm_flags & VM_EXEC) { + unsigned long addr = (unsigned long)kaddr; + + __cpuc_coherent_kern_range(addr, addr + len); + } +} + +/* + * Copy user data from/to a page which is mapped into a different + * processes address space. Really, we want to allow our "user + * space" model to handle this. + * + * Note that this code needs to run on the current CPU. + */ +void copy_to_user_page(struct vm_area_struct *vma, struct page *page, + unsigned long uaddr, void *dst, const void *src, + unsigned long len) +{ + memcpy(dst, src, len); + flush_ptrace_access(vma, page, uaddr, dst, len); +} + +void __flush_dcache_page(struct address_space *mapping, struct page *page) +{ + /* + * Writeback any data associated with the kernel mapping of this + * page. This ensures that data in the physical page is mutually + * coherent with the kernels mapping. + */ + __cpuc_flush_kern_dcache_area(page_address(page), PAGE_SIZE); +} + +/* + * Ensure cache coherency between kernel mapping and userspace mapping + * of this page. + */ +void flush_dcache_page(struct page *page) +{ + struct address_space *mapping; + + /* + * The zero page is never written to, so never has any dirty + * cache lines, and therefore never needs to be flushed. + */ + if (page == ZERO_PAGE(0)) + return; + + mapping = page_mapping(page); + + if (mapping && !mapping_mapped(mapping)) + clear_bit(PG_dcache_clean, &page->flags); + else { + __flush_dcache_page(mapping, page); + if (mapping) + __flush_icache_all(); + set_bit(PG_dcache_clean, &page->flags); + } +} +EXPORT_SYMBOL(flush_dcache_page); diff --git a/arch/unicore32/mm/init.c b/arch/unicore32/mm/init.c new file mode 100644 index 000000000000..3dbe3709b69d --- /dev/null +++ b/arch/unicore32/mm/init.c @@ -0,0 +1,517 @@ +/* + * linux/arch/unicore32/mm/init.c + * + * Copyright (C) 2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/swap.h> +#include <linux/init.h> +#include <linux/bootmem.h> +#include <linux/mman.h> +#include <linux/nodemask.h> +#include <linux/initrd.h> +#include <linux/highmem.h> +#include <linux/gfp.h> +#include <linux/memblock.h> +#include <linux/sort.h> +#include <linux/dma-mapping.h> + +#include <asm/sections.h> +#include <asm/setup.h> +#include <asm/sizes.h> +#include <asm/tlb.h> +#include <mach/map.h> + +#include "mm.h" + +static unsigned long phys_initrd_start __initdata = 0x01000000; +static unsigned long phys_initrd_size __initdata = SZ_8M; + +static int __init early_initrd(char *p) +{ + unsigned long start, size; + char *endp; + + start = memparse(p, &endp); + if (*endp == ',') { + size = memparse(endp + 1, NULL); + + phys_initrd_start = start; + phys_initrd_size = size; + } + return 0; +} +early_param("initrd", early_initrd); + +/* + * This keeps memory configuration data used by a couple memory + * initialization functions, as well as show_mem() for the skipping + * of holes in the memory map. It is populated by uc32_add_memory(). + */ +struct meminfo meminfo; + +void show_mem(void) +{ + int free = 0, total = 0, reserved = 0; + int shared = 0, cached = 0, slab = 0, i; + struct meminfo *mi = &meminfo; + + printk(KERN_DEFAULT "Mem-info:\n"); + show_free_areas(); + + for_each_bank(i, mi) { + struct membank *bank = &mi->bank[i]; + unsigned int pfn1, pfn2; + struct page *page, *end; + + pfn1 = bank_pfn_start(bank); + pfn2 = bank_pfn_end(bank); + + page = pfn_to_page(pfn1); + end = pfn_to_page(pfn2 - 1) + 1; + + do { + total++; + if (PageReserved(page)) + reserved++; + else if (PageSwapCache(page)) + cached++; + else if (PageSlab(page)) + slab++; + else if (!page_count(page)) + free++; + else + shared += page_count(page) - 1; + page++; + } while (page < end); + } + + printk(KERN_DEFAULT "%d pages of RAM\n", total); + printk(KERN_DEFAULT "%d free pages\n", free); + printk(KERN_DEFAULT "%d reserved pages\n", reserved); + printk(KERN_DEFAULT "%d slab pages\n", slab); + printk(KERN_DEFAULT "%d pages shared\n", shared); + printk(KERN_DEFAULT "%d pages swap cached\n", cached); +} + +static void __init find_limits(unsigned long *min, unsigned long *max_low, + unsigned long *max_high) +{ + struct meminfo *mi = &meminfo; + int i; + + *min = -1UL; + *max_low = *max_high = 0; + + for_each_bank(i, mi) { + struct membank *bank = &mi->bank[i]; + unsigned long start, end; + + start = bank_pfn_start(bank); + end = bank_pfn_end(bank); + + if (*min > start) + *min = start; + if (*max_high < end) + *max_high = end; + if (bank->highmem) + continue; + if (*max_low < end) + *max_low = end; + } +} + +static void __init uc32_bootmem_init(unsigned long start_pfn, + unsigned long end_pfn) +{ + struct memblock_region *reg; + unsigned int boot_pages; + phys_addr_t bitmap; + pg_data_t *pgdat; + + /* + * Allocate the bootmem bitmap page. This must be in a region + * of memory which has already been mapped. + */ + boot_pages = bootmem_bootmap_pages(end_pfn - start_pfn); + bitmap = memblock_alloc_base(boot_pages << PAGE_SHIFT, L1_CACHE_BYTES, + __pfn_to_phys(end_pfn)); + + /* + * Initialise the bootmem allocator, handing the + * memory banks over to bootmem. + */ + node_set_online(0); + pgdat = NODE_DATA(0); + init_bootmem_node(pgdat, __phys_to_pfn(bitmap), start_pfn, end_pfn); + + /* Free the lowmem regions from memblock into bootmem. */ + for_each_memblock(memory, reg) { + unsigned long start = memblock_region_memory_base_pfn(reg); + unsigned long end = memblock_region_memory_end_pfn(reg); + + if (end >= end_pfn) + end = end_pfn; + if (start >= end) + break; + + free_bootmem(__pfn_to_phys(start), (end - start) << PAGE_SHIFT); + } + + /* Reserve the lowmem memblock reserved regions in bootmem. */ + for_each_memblock(reserved, reg) { + unsigned long start = memblock_region_reserved_base_pfn(reg); + unsigned long end = memblock_region_reserved_end_pfn(reg); + + if (end >= end_pfn) + end = end_pfn; + if (start >= end) + break; + + reserve_bootmem(__pfn_to_phys(start), + (end - start) << PAGE_SHIFT, BOOTMEM_DEFAULT); + } +} + +static void __init uc32_bootmem_free(unsigned long min, unsigned long max_low, + unsigned long max_high) +{ + unsigned long zone_size[MAX_NR_ZONES], zhole_size[MAX_NR_ZONES]; + struct memblock_region *reg; + + /* + * initialise the zones. + */ + memset(zone_size, 0, sizeof(zone_size)); + + /* + * The memory size has already been determined. If we need + * to do anything fancy with the allocation of this memory + * to the zones, now is the time to do it. + */ + zone_size[0] = max_low - min; + + /* + * Calculate the size of the holes. + * holes = node_size - sum(bank_sizes) + */ + memcpy(zhole_size, zone_size, sizeof(zhole_size)); + for_each_memblock(memory, reg) { + unsigned long start = memblock_region_memory_base_pfn(reg); + unsigned long end = memblock_region_memory_end_pfn(reg); + + if (start < max_low) { + unsigned long low_end = min(end, max_low); + zhole_size[0] -= low_end - start; + } + } + + /* + * Adjust the sizes according to any special requirements for + * this machine type. + */ + arch_adjust_zones(zone_size, zhole_size); + + free_area_init_node(0, zone_size, min, zhole_size); +} + +int pfn_valid(unsigned long pfn) +{ + return memblock_is_memory(pfn << PAGE_SHIFT); +} +EXPORT_SYMBOL(pfn_valid); + +static void uc32_memory_present(void) +{ +} + +static int __init meminfo_cmp(const void *_a, const void *_b) +{ + const struct membank *a = _a, *b = _b; + long cmp = bank_pfn_start(a) - bank_pfn_start(b); + return cmp < 0 ? -1 : cmp > 0 ? 1 : 0; +} + +void __init uc32_memblock_init(struct meminfo *mi) +{ + int i; + + sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), + meminfo_cmp, NULL); + + memblock_init(); + for (i = 0; i < mi->nr_banks; i++) + memblock_add(mi->bank[i].start, mi->bank[i].size); + + /* Register the kernel text, kernel data and initrd with memblock. */ + memblock_reserve(__pa(_text), _end - _text); + +#ifdef CONFIG_BLK_DEV_INITRD + if (phys_initrd_size) { + memblock_reserve(phys_initrd_start, phys_initrd_size); + + /* Now convert initrd to virtual addresses */ + initrd_start = __phys_to_virt(phys_initrd_start); + initrd_end = initrd_start + phys_initrd_size; + } +#endif + + uc32_mm_memblock_reserve(); + + memblock_analyze(); + memblock_dump_all(); +} + +void __init bootmem_init(void) +{ + unsigned long min, max_low, max_high; + + max_low = max_high = 0; + + find_limits(&min, &max_low, &max_high); + + uc32_bootmem_init(min, max_low); + +#ifdef CONFIG_SWIOTLB + swiotlb_init(1); +#endif + /* + * Sparsemem tries to allocate bootmem in memory_present(), + * so must be done after the fixed reservations + */ + uc32_memory_present(); + + /* + * sparse_init() needs the bootmem allocator up and running. + */ + sparse_init(); + + /* + * Now free the memory - free_area_init_node needs + * the sparse mem_map arrays initialized by sparse_init() + * for memmap_init_zone(), otherwise all PFNs are invalid. + */ + uc32_bootmem_free(min, max_low, max_high); + + high_memory = __va((max_low << PAGE_SHIFT) - 1) + 1; + + /* + * This doesn't seem to be used by the Linux memory manager any + * more, but is used by ll_rw_block. If we can get rid of it, we + * also get rid of some of the stuff above as well. + * + * Note: max_low_pfn and max_pfn reflect the number of _pages_ in + * the system, not the maximum PFN. + */ + max_low_pfn = max_low - PHYS_PFN_OFFSET; + max_pfn = max_high - PHYS_PFN_OFFSET; +} + +static inline int free_area(unsigned long pfn, unsigned long end, char *s) +{ + unsigned int pages = 0, size = (end - pfn) << (PAGE_SHIFT - 10); + + for (; pfn < end; pfn++) { + struct page *page = pfn_to_page(pfn); + ClearPageReserved(page); + init_page_count(page); + __free_page(page); + pages++; + } + + if (size && s) + printk(KERN_INFO "Freeing %s memory: %dK\n", s, size); + + return pages; +} + +static inline void +free_memmap(unsigned long start_pfn, unsigned long end_pfn) +{ + struct page *start_pg, *end_pg; + unsigned long pg, pgend; + + /* + * Convert start_pfn/end_pfn to a struct page pointer. + */ + start_pg = pfn_to_page(start_pfn - 1) + 1; + end_pg = pfn_to_page(end_pfn); + + /* + * Convert to physical addresses, and + * round start upwards and end downwards. + */ + pg = PAGE_ALIGN(__pa(start_pg)); + pgend = __pa(end_pg) & PAGE_MASK; + + /* + * If there are free pages between these, + * free the section of the memmap array. + */ + if (pg < pgend) + free_bootmem(pg, pgend - pg); +} + +/* + * The mem_map array can get very big. Free the unused area of the memory map. + */ +static void __init free_unused_memmap(struct meminfo *mi) +{ + unsigned long bank_start, prev_bank_end = 0; + unsigned int i; + + /* + * This relies on each bank being in address order. + * The banks are sorted previously in bootmem_init(). + */ + for_each_bank(i, mi) { + struct membank *bank = &mi->bank[i]; + + bank_start = bank_pfn_start(bank); + + /* + * If we had a previous bank, and there is a space + * between the current bank and the previous, free it. + */ + if (prev_bank_end && prev_bank_end < bank_start) + free_memmap(prev_bank_end, bank_start); + + /* + * Align up here since the VM subsystem insists that the + * memmap entries are valid from the bank end aligned to + * MAX_ORDER_NR_PAGES. + */ + prev_bank_end = ALIGN(bank_pfn_end(bank), MAX_ORDER_NR_PAGES); + } +} + +/* + * mem_init() marks the free areas in the mem_map and tells us how much + * memory is free. This is done after various parts of the system have + * claimed their memory after the kernel image. + */ +void __init mem_init(void) +{ + unsigned long reserved_pages, free_pages; + struct memblock_region *reg; + int i; + + max_mapnr = pfn_to_page(max_pfn + PHYS_PFN_OFFSET) - mem_map; + + /* this will put all unused low memory onto the freelists */ + free_unused_memmap(&meminfo); + + totalram_pages += free_all_bootmem(); + + reserved_pages = free_pages = 0; + + for_each_bank(i, &meminfo) { + struct membank *bank = &meminfo.bank[i]; + unsigned int pfn1, pfn2; + struct page *page, *end; + + pfn1 = bank_pfn_start(bank); + pfn2 = bank_pfn_end(bank); + + page = pfn_to_page(pfn1); + end = pfn_to_page(pfn2 - 1) + 1; + + do { + if (PageReserved(page)) + reserved_pages++; + else if (!page_count(page)) + free_pages++; + page++; + } while (page < end); + } + + /* + * Since our memory may not be contiguous, calculate the + * real number of pages we have in this system + */ + printk(KERN_INFO "Memory:"); + num_physpages = 0; + for_each_memblock(memory, reg) { + unsigned long pages = memblock_region_memory_end_pfn(reg) - + memblock_region_memory_base_pfn(reg); + num_physpages += pages; + printk(" %ldMB", pages >> (20 - PAGE_SHIFT)); + } + printk(" = %luMB total\n", num_physpages >> (20 - PAGE_SHIFT)); + + printk(KERN_NOTICE "Memory: %luk/%luk available, %luk reserved, %luK highmem\n", + nr_free_pages() << (PAGE_SHIFT-10), + free_pages << (PAGE_SHIFT-10), + reserved_pages << (PAGE_SHIFT-10), + totalhigh_pages << (PAGE_SHIFT-10)); + + printk(KERN_NOTICE "Virtual kernel memory layout:\n" + " vector : 0x%08lx - 0x%08lx (%4ld kB)\n" + " vmalloc : 0x%08lx - 0x%08lx (%4ld MB)\n" + " lowmem : 0x%08lx - 0x%08lx (%4ld MB)\n" + " modules : 0x%08lx - 0x%08lx (%4ld MB)\n" + " .init : 0x%p" " - 0x%p" " (%4d kB)\n" + " .text : 0x%p" " - 0x%p" " (%4d kB)\n" + " .data : 0x%p" " - 0x%p" " (%4d kB)\n", + + VECTORS_BASE, VECTORS_BASE + PAGE_SIZE, + DIV_ROUND_UP(PAGE_SIZE, SZ_1K), + VMALLOC_START, VMALLOC_END, + DIV_ROUND_UP((VMALLOC_END - VMALLOC_START), SZ_1M), + PAGE_OFFSET, (unsigned long)high_memory, + DIV_ROUND_UP(((unsigned long)high_memory - PAGE_OFFSET), SZ_1M), + MODULES_VADDR, MODULES_END, + DIV_ROUND_UP((MODULES_END - MODULES_VADDR), SZ_1M), + + __init_begin, __init_end, + DIV_ROUND_UP((__init_end - __init_begin), SZ_1K), + _stext, _etext, + DIV_ROUND_UP((_etext - _stext), SZ_1K), + _sdata, _edata, + DIV_ROUND_UP((_edata - _sdata), SZ_1K)); + + BUILD_BUG_ON(TASK_SIZE > MODULES_VADDR); + BUG_ON(TASK_SIZE > MODULES_VADDR); + + if (PAGE_SIZE >= 16384 && num_physpages <= 128) { + /* + * On a machine this small we won't get + * anywhere without overcommit, so turn + * it on by default. + */ + sysctl_overcommit_memory = OVERCOMMIT_ALWAYS; + } +} + +void free_initmem(void) +{ + totalram_pages += free_area(__phys_to_pfn(__pa(__init_begin)), + __phys_to_pfn(__pa(__init_end)), + "init"); +} + +#ifdef CONFIG_BLK_DEV_INITRD + +static int keep_initrd; + +void free_initrd_mem(unsigned long start, unsigned long end) +{ + if (!keep_initrd) + totalram_pages += free_area(__phys_to_pfn(__pa(start)), + __phys_to_pfn(__pa(end)), + "initrd"); +} + +static int __init keepinitrd_setup(char *__unused) +{ + keep_initrd = 1; + return 1; +} + +__setup("keepinitrd", keepinitrd_setup); +#endif diff --git a/arch/unicore32/mm/ioremap.c b/arch/unicore32/mm/ioremap.c new file mode 100644 index 000000000000..b7a605597b08 --- /dev/null +++ b/arch/unicore32/mm/ioremap.c @@ -0,0 +1,261 @@ +/* + * linux/arch/unicore32/mm/ioremap.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * + * Re-map IO memory to kernel address space so that we can access it. + * + * This allows a driver to remap an arbitrary region of bus memory into + * virtual space. One should *only* use readl, writel, memcpy_toio and + * so on with such remapped areas. + * + * Because UniCore only has a 32-bit address space we can't address the + * whole of the (physical) PCI space at once. PCI huge-mode addressing + * allows us to circumvent this restriction by splitting PCI space into + * two 2GB chunks and mapping only one at a time into processor memory. + * We use MMU protection domains to trap any attempt to access the bank + * that is not currently mapped. (This isn't fully implemented yet.) + */ +#include <linux/module.h> +#include <linux/errno.h> +#include <linux/mm.h> +#include <linux/vmalloc.h> +#include <linux/io.h> + +#include <asm/cputype.h> +#include <asm/cacheflush.h> +#include <asm/mmu_context.h> +#include <asm/pgalloc.h> +#include <asm/tlbflush.h> +#include <asm/sizes.h> + +#include <mach/map.h> +#include "mm.h" + +/* + * Used by ioremap() and iounmap() code to mark (super)section-mapped + * I/O regions in vm_struct->flags field. + */ +#define VM_UNICORE_SECTION_MAPPING 0x80000000 + +int ioremap_page(unsigned long virt, unsigned long phys, + const struct mem_type *mtype) +{ + return ioremap_page_range(virt, virt + PAGE_SIZE, phys, + __pgprot(mtype->prot_pte)); +} +EXPORT_SYMBOL(ioremap_page); + +/* + * Section support is unsafe on SMP - If you iounmap and ioremap a region, + * the other CPUs will not see this change until their next context switch. + * Meanwhile, (eg) if an interrupt comes in on one of those other CPUs + * which requires the new ioremap'd region to be referenced, the CPU will + * reference the _old_ region. + * + * Note that get_vm_area_caller() allocates a guard 4K page, so we need to + * mask the size back to 4MB aligned or we will overflow in the loop below. + */ +static void unmap_area_sections(unsigned long virt, unsigned long size) +{ + unsigned long addr = virt, end = virt + (size & ~(SZ_4M - 1)); + pgd_t *pgd; + + flush_cache_vunmap(addr, end); + pgd = pgd_offset_k(addr); + do { + pmd_t pmd, *pmdp = pmd_offset((pud_t *)pgd, addr); + + pmd = *pmdp; + if (!pmd_none(pmd)) { + /* + * Clear the PMD from the page table, and + * increment the kvm sequence so others + * notice this change. + * + * Note: this is still racy on SMP machines. + */ + pmd_clear(pmdp); + + /* + * Free the page table, if there was one. + */ + if ((pmd_val(pmd) & PMD_TYPE_MASK) == PMD_TYPE_TABLE) + pte_free_kernel(&init_mm, pmd_page_vaddr(pmd)); + } + + addr += PGDIR_SIZE; + pgd++; + } while (addr < end); + + flush_tlb_kernel_range(virt, end); +} + +static int +remap_area_sections(unsigned long virt, unsigned long pfn, + size_t size, const struct mem_type *type) +{ + unsigned long addr = virt, end = virt + size; + pgd_t *pgd; + + /* + * Remove and free any PTE-based mapping, and + * sync the current kernel mapping. + */ + unmap_area_sections(virt, size); + + pgd = pgd_offset_k(addr); + do { + pmd_t *pmd = pmd_offset((pud_t *)pgd, addr); + + set_pmd(pmd, __pmd(__pfn_to_phys(pfn) | type->prot_sect)); + pfn += SZ_4M >> PAGE_SHIFT; + flush_pmd_entry(pmd); + + addr += PGDIR_SIZE; + pgd++; + } while (addr < end); + + return 0; +} + +void __iomem *__uc32_ioremap_pfn_caller(unsigned long pfn, + unsigned long offset, size_t size, unsigned int mtype, void *caller) +{ + const struct mem_type *type; + int err; + unsigned long addr; + struct vm_struct *area; + + /* + * High mappings must be section aligned + */ + if (pfn >= 0x100000 && (__pfn_to_phys(pfn) & ~SECTION_MASK)) + return NULL; + + /* + * Don't allow RAM to be mapped + */ + if (pfn_valid(pfn)) { + printk(KERN_WARNING "BUG: Your driver calls ioremap() on\n" + "system memory. This leads to architecturally\n" + "unpredictable behaviour, and ioremap() will fail in\n" + "the next kernel release. Please fix your driver.\n"); + WARN_ON(1); + } + + type = get_mem_type(mtype); + if (!type) + return NULL; + + /* + * Page align the mapping size, taking account of any offset. + */ + size = PAGE_ALIGN(offset + size); + + area = get_vm_area_caller(size, VM_IOREMAP, caller); + if (!area) + return NULL; + addr = (unsigned long)area->addr; + + if (!((__pfn_to_phys(pfn) | size | addr) & ~PMD_MASK)) { + area->flags |= VM_UNICORE_SECTION_MAPPING; + err = remap_area_sections(addr, pfn, size, type); + } else + err = ioremap_page_range(addr, addr + size, __pfn_to_phys(pfn), + __pgprot(type->prot_pte)); + + if (err) { + vunmap((void *)addr); + return NULL; + } + + flush_cache_vmap(addr, addr + size); + return (void __iomem *) (offset + addr); +} + +void __iomem *__uc32_ioremap_caller(unsigned long phys_addr, size_t size, + unsigned int mtype, void *caller) +{ + unsigned long last_addr; + unsigned long offset = phys_addr & ~PAGE_MASK; + unsigned long pfn = __phys_to_pfn(phys_addr); + + /* + * Don't allow wraparound or zero size + */ + last_addr = phys_addr + size - 1; + if (!size || last_addr < phys_addr) + return NULL; + + return __uc32_ioremap_pfn_caller(pfn, offset, size, mtype, caller); +} + +/* + * Remap an arbitrary physical address space into the kernel virtual + * address space. Needed when the kernel wants to access high addresses + * directly. + * + * NOTE! We need to allow non-page-aligned mappings too: we will obviously + * have to convert them into an offset in a page-aligned mapping, but the + * caller shouldn't need to know that small detail. + */ +void __iomem * +__uc32_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size, + unsigned int mtype) +{ + return __uc32_ioremap_pfn_caller(pfn, offset, size, mtype, + __builtin_return_address(0)); +} +EXPORT_SYMBOL(__uc32_ioremap_pfn); + +void __iomem * +__uc32_ioremap(unsigned long phys_addr, size_t size) +{ + return __uc32_ioremap_caller(phys_addr, size, MT_DEVICE, + __builtin_return_address(0)); +} +EXPORT_SYMBOL(__uc32_ioremap); + +void __iomem * +__uc32_ioremap_cached(unsigned long phys_addr, size_t size) +{ + return __uc32_ioremap_caller(phys_addr, size, MT_DEVICE_CACHED, + __builtin_return_address(0)); +} +EXPORT_SYMBOL(__uc32_ioremap_cached); + +void __uc32_iounmap(volatile void __iomem *io_addr) +{ + void *addr = (void *)(PAGE_MASK & (unsigned long)io_addr); + struct vm_struct **p, *tmp; + + /* + * If this is a section based mapping we need to handle it + * specially as the VM subsystem does not know how to handle + * such a beast. We need the lock here b/c we need to clear + * all the mappings before the area can be reclaimed + * by someone else. + */ + write_lock(&vmlist_lock); + for (p = &vmlist ; (tmp = *p) ; p = &tmp->next) { + if ((tmp->flags & VM_IOREMAP) && (tmp->addr == addr)) { + if (tmp->flags & VM_UNICORE_SECTION_MAPPING) { + unmap_area_sections((unsigned long)tmp->addr, + tmp->size); + } + break; + } + } + write_unlock(&vmlist_lock); + + vunmap(addr); +} +EXPORT_SYMBOL(__uc32_iounmap); diff --git a/arch/unicore32/mm/mm.h b/arch/unicore32/mm/mm.h new file mode 100644 index 000000000000..3296bca0f1f7 --- /dev/null +++ b/arch/unicore32/mm/mm.h @@ -0,0 +1,39 @@ +/* + * linux/arch/unicore32/mm/mm.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/* the upper-most page table pointer */ +extern pmd_t *top_pmd; +extern int sysctl_overcommit_memory; + +#define TOP_PTE(x) pte_offset_kernel(top_pmd, x) + +static inline pmd_t *pmd_off(pgd_t *pgd, unsigned long virt) +{ + return pmd_offset((pud_t *)pgd, virt); +} + +static inline pmd_t *pmd_off_k(unsigned long virt) +{ + return pmd_off(pgd_offset_k(virt), virt); +} + +struct mem_type { + unsigned int prot_pte; + unsigned int prot_l1; + unsigned int prot_sect; +}; + +const struct mem_type *get_mem_type(unsigned int type); + +extern void __flush_dcache_page(struct address_space *, struct page *); + +void __init bootmem_init(void); +void uc32_mm_memblock_reserve(void); diff --git a/arch/unicore32/mm/mmu.c b/arch/unicore32/mm/mmu.c new file mode 100644 index 000000000000..7bf3d588631f --- /dev/null +++ b/arch/unicore32/mm/mmu.c @@ -0,0 +1,533 @@ +/* + * linux/arch/unicore32/mm/mmu.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/mman.h> +#include <linux/nodemask.h> +#include <linux/memblock.h> +#include <linux/fs.h> +#include <linux/bootmem.h> +#include <linux/io.h> + +#include <asm/cputype.h> +#include <asm/sections.h> +#include <asm/setup.h> +#include <asm/sizes.h> +#include <asm/tlb.h> + +#include <mach/map.h> + +#include "mm.h" + +DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); + +/* + * empty_zero_page is a special page that is used for + * zero-initialized data and COW. + */ +struct page *empty_zero_page; +EXPORT_SYMBOL(empty_zero_page); + +/* + * The pmd table for the upper-most set of pages. + */ +pmd_t *top_pmd; + +pgprot_t pgprot_user; +EXPORT_SYMBOL(pgprot_user); + +pgprot_t pgprot_kernel; +EXPORT_SYMBOL(pgprot_kernel); + +static int __init noalign_setup(char *__unused) +{ + cr_alignment &= ~CR_A; + cr_no_alignment &= ~CR_A; + set_cr(cr_alignment); + return 1; +} +__setup("noalign", noalign_setup); + +void adjust_cr(unsigned long mask, unsigned long set) +{ + unsigned long flags; + + mask &= ~CR_A; + + set &= mask; + + local_irq_save(flags); + + cr_no_alignment = (cr_no_alignment & ~mask) | set; + cr_alignment = (cr_alignment & ~mask) | set; + + set_cr((get_cr() & ~mask) | set); + + local_irq_restore(flags); +} + +struct map_desc { + unsigned long virtual; + unsigned long pfn; + unsigned long length; + unsigned int type; +}; + +#define PROT_PTE_DEVICE (PTE_PRESENT | PTE_YOUNG | \ + PTE_DIRTY | PTE_READ | PTE_WRITE) +#define PROT_SECT_DEVICE (PMD_TYPE_SECT | PMD_PRESENT | \ + PMD_SECT_READ | PMD_SECT_WRITE) + +static struct mem_type mem_types[] = { + [MT_DEVICE] = { /* Strongly ordered */ + .prot_pte = PROT_PTE_DEVICE, + .prot_l1 = PMD_TYPE_TABLE | PMD_PRESENT, + .prot_sect = PROT_SECT_DEVICE, + }, + /* + * MT_KUSER: pte for vecpage -- cacheable, + * and sect for unigfx mmap -- noncacheable + */ + [MT_KUSER] = { + .prot_pte = PTE_PRESENT | PTE_YOUNG | PTE_DIRTY | + PTE_CACHEABLE | PTE_READ | PTE_EXEC, + .prot_l1 = PMD_TYPE_TABLE | PMD_PRESENT, + .prot_sect = PROT_SECT_DEVICE, + }, + [MT_HIGH_VECTORS] = { + .prot_pte = PTE_PRESENT | PTE_YOUNG | PTE_DIRTY | + PTE_CACHEABLE | PTE_READ | PTE_WRITE | + PTE_EXEC, + .prot_l1 = PMD_TYPE_TABLE | PMD_PRESENT, + }, + [MT_MEMORY] = { + .prot_pte = PTE_PRESENT | PTE_YOUNG | PTE_DIRTY | + PTE_WRITE | PTE_EXEC, + .prot_l1 = PMD_TYPE_TABLE | PMD_PRESENT, + .prot_sect = PMD_TYPE_SECT | PMD_PRESENT | PMD_SECT_CACHEABLE | + PMD_SECT_READ | PMD_SECT_WRITE | PMD_SECT_EXEC, + }, + [MT_ROM] = { + .prot_sect = PMD_TYPE_SECT | PMD_PRESENT | PMD_SECT_CACHEABLE | + PMD_SECT_READ, + }, +}; + +const struct mem_type *get_mem_type(unsigned int type) +{ + return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; +} +EXPORT_SYMBOL(get_mem_type); + +/* + * Adjust the PMD section entries according to the CPU in use. + */ +static void __init build_mem_type_table(void) +{ + pgprot_user = __pgprot(PTE_PRESENT | PTE_YOUNG | PTE_CACHEABLE); + pgprot_kernel = __pgprot(PTE_PRESENT | PTE_YOUNG | + PTE_DIRTY | PTE_READ | PTE_WRITE | + PTE_EXEC | PTE_CACHEABLE); +} + +#define vectors_base() (vectors_high() ? 0xffff0000 : 0) + +static void __init *early_alloc(unsigned long sz) +{ + void *ptr = __va(memblock_alloc(sz, sz)); + memset(ptr, 0, sz); + return ptr; +} + +static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, + unsigned long prot) +{ + if (pmd_none(*pmd)) { + pte_t *pte = early_alloc(PTRS_PER_PTE * sizeof(pte_t)); + __pmd_populate(pmd, __pa(pte) | prot); + } + BUG_ON(pmd_bad(*pmd)); + return pte_offset_kernel(pmd, addr); +} + +static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, + unsigned long end, unsigned long pfn, + const struct mem_type *type) +{ + pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1); + do { + set_pte(pte, pfn_pte(pfn, __pgprot(type->prot_pte))); + pfn++; + } while (pte++, addr += PAGE_SIZE, addr != end); +} + +static void __init alloc_init_section(pgd_t *pgd, unsigned long addr, + unsigned long end, unsigned long phys, + const struct mem_type *type) +{ + pmd_t *pmd = pmd_offset((pud_t *)pgd, addr); + + /* + * Try a section mapping - end, addr and phys must all be aligned + * to a section boundary. + */ + if (((addr | end | phys) & ~SECTION_MASK) == 0) { + pmd_t *p = pmd; + + do { + set_pmd(pmd, __pmd(phys | type->prot_sect)); + phys += SECTION_SIZE; + } while (pmd++, addr += SECTION_SIZE, addr != end); + + flush_pmd_entry(p); + } else { + /* + * No need to loop; pte's aren't interested in the + * individual L1 entries. + */ + alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type); + } +} + +/* + * Create the page directory entries and any necessary + * page tables for the mapping specified by `md'. We + * are able to cope here with varying sizes and address + * offsets, and we take full advantage of sections. + */ +static void __init create_mapping(struct map_desc *md) +{ + unsigned long phys, addr, length, end; + const struct mem_type *type; + pgd_t *pgd; + + if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { + printk(KERN_WARNING "BUG: not creating mapping for " + "0x%08llx at 0x%08lx in user region\n", + __pfn_to_phys((u64)md->pfn), md->virtual); + return; + } + + if ((md->type == MT_DEVICE || md->type == MT_ROM) && + md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) { + printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx " + "overlaps vmalloc space\n", + __pfn_to_phys((u64)md->pfn), md->virtual); + } + + type = &mem_types[md->type]; + + addr = md->virtual & PAGE_MASK; + phys = (unsigned long)__pfn_to_phys(md->pfn); + length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); + + if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { + printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not " + "be mapped using pages, ignoring.\n", + __pfn_to_phys(md->pfn), addr); + return; + } + + pgd = pgd_offset_k(addr); + end = addr + length; + do { + unsigned long next = pgd_addr_end(addr, end); + + alloc_init_section(pgd, addr, next, phys, type); + + phys += next - addr; + addr = next; + } while (pgd++, addr != end); +} + +static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_128M); + +/* + * vmalloc=size forces the vmalloc area to be exactly 'size' + * bytes. This can be used to increase (or decrease) the vmalloc + * area - the default is 128m. + */ +static int __init early_vmalloc(char *arg) +{ + unsigned long vmalloc_reserve = memparse(arg, NULL); + + if (vmalloc_reserve < SZ_16M) { + vmalloc_reserve = SZ_16M; + printk(KERN_WARNING + "vmalloc area too small, limiting to %luMB\n", + vmalloc_reserve >> 20); + } + + if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { + vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); + printk(KERN_WARNING + "vmalloc area is too big, limiting to %luMB\n", + vmalloc_reserve >> 20); + } + + vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve); + return 0; +} +early_param("vmalloc", early_vmalloc); + +static phys_addr_t lowmem_limit __initdata = SZ_1G; + +static void __init sanity_check_meminfo(void) +{ + int i, j; + + lowmem_limit = __pa(vmalloc_min - 1) + 1; + memblock_set_current_limit(lowmem_limit); + + for (i = 0, j = 0; i < meminfo.nr_banks; i++) { + struct membank *bank = &meminfo.bank[j]; + *bank = meminfo.bank[i]; + j++; + } + meminfo.nr_banks = j; +} + +static inline void prepare_page_table(void) +{ + unsigned long addr; + phys_addr_t end; + + /* + * Clear out all the mappings below the kernel image. + */ + for (addr = 0; addr < MODULES_VADDR; addr += PGDIR_SIZE) + pmd_clear(pmd_off_k(addr)); + + for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE) + pmd_clear(pmd_off_k(addr)); + + /* + * Find the end of the first block of lowmem. + */ + end = memblock.memory.regions[0].base + memblock.memory.regions[0].size; + if (end >= lowmem_limit) + end = lowmem_limit; + + /* + * Clear out all the kernel space mappings, except for the first + * memory bank, up to the end of the vmalloc region. + */ + for (addr = __phys_to_virt(end); + addr < VMALLOC_END; addr += PGDIR_SIZE) + pmd_clear(pmd_off_k(addr)); +} + +/* + * Reserve the special regions of memory + */ +void __init uc32_mm_memblock_reserve(void) +{ + /* + * Reserve the page tables. These are already in use, + * and can only be in node 0. + */ + memblock_reserve(__pa(swapper_pg_dir), PTRS_PER_PGD * sizeof(pgd_t)); + +#ifdef CONFIG_PUV3_UNIGFX + /* + * These should likewise go elsewhere. They pre-reserve the + * screen/video memory region at the 48M~64M of main system memory. + */ + memblock_reserve(PKUNITY_UNIGFX_MMAP_BASE, PKUNITY_UNIGFX_MMAP_SIZE); + memblock_reserve(PKUNITY_UVC_MMAP_BASE, PKUNITY_UVC_MMAP_SIZE); +#endif +} + +/* + * Set up device the mappings. Since we clear out the page tables for all + * mappings above VMALLOC_END, we will remove any debug device mappings. + * This means you have to be careful how you debug this function, or any + * called function. This means you can't use any function or debugging + * method which may touch any device, otherwise the kernel _will_ crash. + */ +static void __init devicemaps_init(void) +{ + struct map_desc map; + unsigned long addr; + void *vectors; + + /* + * Allocate the vector page early. + */ + vectors = early_alloc(PAGE_SIZE); + + for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE) + pmd_clear(pmd_off_k(addr)); + + /* + * Create a mapping for UniGFX VRAM + */ +#ifdef CONFIG_PUV3_UNIGFX + map.pfn = __phys_to_pfn(PKUNITY_UNIGFX_MMAP_BASE); + map.virtual = KUSER_UNIGFX_BASE; + map.length = PKUNITY_UNIGFX_MMAP_SIZE; + map.type = MT_KUSER; + create_mapping(&map); +#endif + + /* + * Create a mapping for the machine vectors at the high-vectors + * location (0xffff0000). If we aren't using high-vectors, also + * create a mapping at the low-vectors virtual address. + */ + map.pfn = __phys_to_pfn(virt_to_phys(vectors)); + map.virtual = VECTORS_BASE; + map.length = PAGE_SIZE; + map.type = MT_HIGH_VECTORS; + create_mapping(&map); + + /* + * Create a mapping for the kuser page at the special + * location (0xbfff0000) to the same vectors location. + */ + map.pfn = __phys_to_pfn(virt_to_phys(vectors)); + map.virtual = KUSER_VECPAGE_BASE; + map.length = PAGE_SIZE; + map.type = MT_KUSER; + create_mapping(&map); + + /* + * Finally flush the caches and tlb to ensure that we're in a + * consistent state wrt the writebuffer. This also ensures that + * any write-allocated cache lines in the vector page are written + * back. After this point, we can start to touch devices again. + */ + local_flush_tlb_all(); + flush_cache_all(); +} + +static void __init map_lowmem(void) +{ + struct memblock_region *reg; + + /* Map all the lowmem memory banks. */ + for_each_memblock(memory, reg) { + phys_addr_t start = reg->base; + phys_addr_t end = start + reg->size; + struct map_desc map; + + if (end > lowmem_limit) + end = lowmem_limit; + if (start >= end) + break; + + map.pfn = __phys_to_pfn(start); + map.virtual = __phys_to_virt(start); + map.length = end - start; + map.type = MT_MEMORY; + + create_mapping(&map); + } +} + +/* + * paging_init() sets up the page tables, initialises the zone memory + * maps, and sets up the zero page, bad page and bad page tables. + */ +void __init paging_init(void) +{ + void *zero_page; + + build_mem_type_table(); + sanity_check_meminfo(); + prepare_page_table(); + map_lowmem(); + devicemaps_init(); + + top_pmd = pmd_off_k(0xffff0000); + + /* allocate the zero page. */ + zero_page = early_alloc(PAGE_SIZE); + + bootmem_init(); + + empty_zero_page = virt_to_page(zero_page); + __flush_dcache_page(NULL, empty_zero_page); +} + +/* + * In order to soft-boot, we need to insert a 1:1 mapping in place of + * the user-mode pages. This will then ensure that we have predictable + * results when turning the mmu off + */ +void setup_mm_for_reboot(char mode) +{ + unsigned long base_pmdval; + pgd_t *pgd; + int i; + + /* + * We need to access to user-mode page tables here. For kernel threads + * we don't have any user-mode mappings so we use the context that we + * "borrowed". + */ + pgd = current->active_mm->pgd; + + base_pmdval = PMD_SECT_WRITE | PMD_SECT_READ | PMD_TYPE_SECT; + + for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) { + unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval; + pmd_t *pmd; + + pmd = pmd_off(pgd, i << PGDIR_SHIFT); + set_pmd(pmd, __pmd(pmdval)); + flush_pmd_entry(pmd); + } + + local_flush_tlb_all(); +} + +/* + * Take care of architecture specific things when placing a new PTE into + * a page table, or changing an existing PTE. Basically, there are two + * things that we need to take care of: + * + * 1. If PG_dcache_clean is not set for the page, we need to ensure + * that any cache entries for the kernels virtual memory + * range are written back to the page. + * 2. If we have multiple shared mappings of the same space in + * an object, we need to deal with the cache aliasing issues. + * + * Note that the pte lock will be held. + */ +void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, + pte_t *ptep) +{ + unsigned long pfn = pte_pfn(*ptep); + struct address_space *mapping; + struct page *page; + + if (!pfn_valid(pfn)) + return; + + /* + * The zero page is never written to, so never has any dirty + * cache lines, and therefore never needs to be flushed. + */ + page = pfn_to_page(pfn); + if (page == ZERO_PAGE(0)) + return; + + mapping = page_mapping(page); + if (!test_and_set_bit(PG_dcache_clean, &page->flags)) + __flush_dcache_page(mapping, page); + if (mapping) + if (vma->vm_flags & VM_EXEC) + __flush_icache_all(); +} diff --git a/arch/unicore32/mm/pgd.c b/arch/unicore32/mm/pgd.c new file mode 100644 index 000000000000..08b8d4295e70 --- /dev/null +++ b/arch/unicore32/mm/pgd.c @@ -0,0 +1,102 @@ +/* + * linux/arch/unicore32/mm/pgd.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/mm.h> +#include <linux/gfp.h> +#include <linux/highmem.h> + +#include <asm/pgalloc.h> +#include <asm/page.h> +#include <asm/tlbflush.h> + +#include "mm.h" + +#define FIRST_KERNEL_PGD_NR (FIRST_USER_PGD_NR + USER_PTRS_PER_PGD) + +/* + * need to get a 4k page for level 1 + */ +pgd_t *get_pgd_slow(struct mm_struct *mm) +{ + pgd_t *new_pgd, *init_pgd; + pmd_t *new_pmd, *init_pmd; + pte_t *new_pte, *init_pte; + + new_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL, 0); + if (!new_pgd) + goto no_pgd; + + memset(new_pgd, 0, FIRST_KERNEL_PGD_NR * sizeof(pgd_t)); + + /* + * Copy over the kernel and IO PGD entries + */ + init_pgd = pgd_offset_k(0); + memcpy(new_pgd + FIRST_KERNEL_PGD_NR, init_pgd + FIRST_KERNEL_PGD_NR, + (PTRS_PER_PGD - FIRST_KERNEL_PGD_NR) * sizeof(pgd_t)); + + clean_dcache_area(new_pgd, PTRS_PER_PGD * sizeof(pgd_t)); + + if (!vectors_high()) { + /* + * On UniCore, first page must always be allocated since it + * contains the machine vectors. + */ + new_pmd = pmd_alloc(mm, (pud_t *)new_pgd, 0); + if (!new_pmd) + goto no_pmd; + + new_pte = pte_alloc_map(mm, NULL, new_pmd, 0); + if (!new_pte) + goto no_pte; + + init_pmd = pmd_offset((pud_t *)init_pgd, 0); + init_pte = pte_offset_map(init_pmd, 0); + set_pte(new_pte, *init_pte); + pte_unmap(init_pte); + pte_unmap(new_pte); + } + + return new_pgd; + +no_pte: + pmd_free(mm, new_pmd); +no_pmd: + free_pages((unsigned long)new_pgd, 0); +no_pgd: + return NULL; +} + +void free_pgd_slow(struct mm_struct *mm, pgd_t *pgd) +{ + pmd_t *pmd; + pgtable_t pte; + + if (!pgd) + return; + + /* pgd is always present and good */ + pmd = pmd_off(pgd, 0); + if (pmd_none(*pmd)) + goto free; + if (pmd_bad(*pmd)) { + pmd_ERROR(*pmd); + pmd_clear(pmd); + goto free; + } + + pte = pmd_pgtable(*pmd); + pmd_clear(pmd); + pte_free(mm, pte); + pmd_free(mm, pmd); +free: + free_pages((unsigned long) pgd, 0); +} diff --git a/arch/unicore32/mm/proc-macros.S b/arch/unicore32/mm/proc-macros.S new file mode 100644 index 000000000000..51560d68c894 --- /dev/null +++ b/arch/unicore32/mm/proc-macros.S @@ -0,0 +1,145 @@ +/* + * linux/arch/unicore32/mm/proc-macros.S + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * We need constants.h for: + * VMA_VM_MM + * VMA_VM_FLAGS + * VM_EXEC + */ +#include <generated/asm-offsets.h> +#include <asm/thread_info.h> +#include <asm/memory.h> + +/* + * the cache line sizes of the I and D cache are the same + */ +#define CACHE_LINESIZE 32 + +/* + * This is the maximum size of an area which will be invalidated + * using the single invalidate entry instructions. Anything larger + * than this, and we go for the whole cache. + * + * This value should be chosen such that we choose the cheapest + * alternative. + */ +#ifdef CONFIG_CPU_UCV2 +#define MAX_AREA_SIZE 0x800 /* 64 cache line */ +#endif + +/* + * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm) + */ + .macro vma_vm_mm, rd, rn + ldw \rd, [\rn+], #VMA_VM_MM + .endm + +/* + * vma_vm_flags - get vma->vm_flags + */ + .macro vma_vm_flags, rd, rn + ldw \rd, [\rn+], #VMA_VM_FLAGS + .endm + + .macro tsk_mm, rd, rn + ldw \rd, [\rn+], #TI_TASK + ldw \rd, [\rd+], #TSK_ACTIVE_MM + .endm + +/* + * act_mm - get current->active_mm + */ + .macro act_mm, rd + andn \rd, sp, #8128 + andn \rd, \rd, #63 + ldw \rd, [\rd+], #TI_TASK + ldw \rd, [\rd+], #TSK_ACTIVE_MM + .endm + +/* + * mmid - get context id from mm pointer (mm->context.id) + */ + .macro mmid, rd, rn + ldw \rd, [\rn+], #MM_CONTEXT_ID + .endm + +/* + * mask_asid - mask the ASID from the context ID + */ + .macro asid, rd, rn + and \rd, \rn, #255 + .endm + + .macro crval, clear, mmuset, ucset + .word \clear + .word \mmuset + .endm + +#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE +/* + * va2pa va, pa, tbl, msk, off, err + * This macro is used to translate virtual address to its physical address. + * + * va: virtual address + * pa: physical address, result is stored in this register + * tbl, msk, off: temp registers, will be destroyed + * err: jump to error label if the physical address not exist + * NOTE: all regs must be different + */ + .macro va2pa, va, pa, tbl, msk, off, err=990f + movc \pa, p0.c2, #0 + mov \off, \va >> #22 @ off <- index of 1st page table + adr \tbl, 910f @ tbl <- table of 1st page table +900: @ ---- handle 1, 2 page table + add \pa, \pa, #PAGE_OFFSET @ pa <- virt addr of page table + ldw \pa, [\pa+], \off << #2 @ pa <- the content of pt + cand.a \pa, #4 @ test exist bit + beq \err @ if not exist + and \off, \pa, #3 @ off <- the last 2 bits + add \tbl, \tbl, \off << #3 @ cmove table pointer + ldw \msk, [\tbl+], #0 @ get the mask + ldw pc, [\tbl+], #4 +930: @ ---- handle 2nd page table + and \pa, \pa, \msk @ pa <- phys addr of 2nd pt + mov \off, \va << #10 + cntlo \tbl, \msk @ use tbl as temp reg + mov \off, \off >> \tbl + mov \off, \off >> #2 @ off <- index of 2nd pt + adr \tbl, 920f @ tbl <- table of 2nd pt + b 900b +910: @ 1st level page table + .word 0xfffff000, 930b @ second level page table + .word 0xfffffc00, 930b @ second level large page table + .word 0x00000000, \err @ invalid + .word 0xffc00000, 980f @ super page + +920: @ 2nd level page table + .word 0xfffff000, 980f @ page + .word 0xffffc000, 980f @ middle page + .word 0xffff0000, 980f @ large page + .word 0x00000000, \err @ invalid +980: + andn \tbl, \va, \msk + and \pa, \pa, \msk + or \pa, \pa, \tbl +990: + .endm +#endif + + .macro dcacheline_flush, addr, t1, t2 + mov \t1, \addr << #20 + ldw \t2, =_stext @ _stext must ALIGN(4096) + add \t2, \t2, \t1 >> #20 + ldw \t1, [\t2+], #0x0000 + ldw \t1, [\t2+], #0x1000 + ldw \t1, [\t2+], #0x2000 + ldw \t1, [\t2+], #0x3000 + .endm diff --git a/arch/unicore32/mm/proc-syms.c b/arch/unicore32/mm/proc-syms.c new file mode 100644 index 000000000000..f30071e3665d --- /dev/null +++ b/arch/unicore32/mm/proc-syms.c @@ -0,0 +1,23 @@ +/* + * linux/arch/unicore32/mm/proc-syms.c + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/module.h> +#include <linux/mm.h> + +#include <asm/cacheflush.h> +#include <asm/tlbflush.h> +#include <asm/page.h> + +EXPORT_SYMBOL(cpu_dcache_clean_area); +EXPORT_SYMBOL(cpu_set_pte); + +EXPORT_SYMBOL(__cpuc_dma_flush_range); +EXPORT_SYMBOL(__cpuc_dma_clean_range); diff --git a/arch/unicore32/mm/proc-ucv2.S b/arch/unicore32/mm/proc-ucv2.S new file mode 100644 index 000000000000..9d296092e362 --- /dev/null +++ b/arch/unicore32/mm/proc-ucv2.S @@ -0,0 +1,134 @@ +/* + * linux/arch/unicore32/mm/proc-ucv2.S + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/init.h> +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <asm/hwcap.h> +#include <asm/pgtable-hwdef.h> +#include <asm/pgtable.h> + +#include "proc-macros.S" + +ENTRY(cpu_proc_fin) + stm.w (lr), [sp-] + mov ip, #PSR_R_BIT | PSR_I_BIT | PRIV_MODE + mov.a asr, ip + b.l __cpuc_flush_kern_all + ldm.w (pc), [sp]+ + +/* + * cpu_reset(loc) + * + * Perform a soft reset of the system. Put the CPU into the + * same state as it would be if it had been reset, and branch + * to what would be the reset vector. + * + * - loc - location to jump to for soft reset + */ + .align 5 +ENTRY(cpu_reset) + mov ip, #0 + movc p0.c5, ip, #28 @ Cache invalidate all + nop8 + + movc p0.c6, ip, #6 @ TLB invalidate all + nop8 + + movc ip, p0.c1, #0 @ ctrl register + or ip, ip, #0x2000 @ vector base address + andn ip, ip, #0x000f @ ............idam + movc p0.c1, ip, #0 @ disable caches and mmu + nop + mov pc, r0 @ jump to loc + nop8 + +/* + * cpu_do_idle() + * + * Idle the processor (eg, wait for interrupt). + * + * IRQs are already disabled. + */ +ENTRY(cpu_do_idle) + mov r0, #0 @ PCI address + .rept 8 + ldw r1, [r0] + .endr + mov pc, lr + +ENTRY(cpu_dcache_clean_area) +#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE + csub.a r1, #MAX_AREA_SIZE + bsg 101f + mov r9, #PAGE_SZ + sub r9, r9, #1 @ PAGE_MASK +1: va2pa r0, r10, r11, r12, r13 @ r10 is PA + b 3f +2: cand.a r0, r9 + beq 1b +3: movc p0.c5, r10, #11 @ clean D entry + nop8 + add r0, r0, #CACHE_LINESIZE + add r10, r10, #CACHE_LINESIZE + sub.a r1, r1, #CACHE_LINESIZE + bua 2b + mov pc, lr +#endif +101: mov ip, #0 + movc p0.c5, ip, #10 @ Dcache clean all + nop8 + + mov pc, lr + +/* + * cpu_do_switch_mm(pgd_phys) + * + * Set the translation table base pointer to be pgd_phys + * + * - pgd_phys - physical address of new pgd + * + * It is assumed that: + * - we are not using split page tables + */ + .align 5 +ENTRY(cpu_do_switch_mm) + movc p0.c2, r0, #0 @ update page table ptr + nop8 + + movc p0.c6, ip, #6 @ TLB invalidate all + nop8 + + mov pc, lr + +/* + * cpu_set_pte(ptep, pte) + * + * Set a level 2 translation table entry. + * + * - ptep - pointer to level 2 translation table entry + * - pte - PTE value to store + */ + .align 5 +ENTRY(cpu_set_pte) + stw r1, [r0] +#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE + sub r2, r0, #PAGE_OFFSET + movc p0.c5, r2, #11 @ Dcache clean line + nop8 +#else + mov ip, #0 + movc p0.c5, ip, #10 @ Dcache clean all + nop8 + @dcacheline_flush r0, r2, ip +#endif + mov pc, lr + diff --git a/arch/unicore32/mm/tlb-ucv2.S b/arch/unicore32/mm/tlb-ucv2.S new file mode 100644 index 000000000000..061d455f9a15 --- /dev/null +++ b/arch/unicore32/mm/tlb-ucv2.S @@ -0,0 +1,89 @@ +/* + * linux/arch/unicore32/mm/tlb-ucv2.S + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Copyright (C) 2001-2010 GUAN Xue-tao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/init.h> +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <asm/page.h> +#include <asm/tlbflush.h> +#include "proc-macros.S" + +/* + * __cpu_flush_user_tlb_range(start, end, vma) + * + * Invalidate a range of TLB entries in the specified address space. + * + * - start - start address (may not be aligned) + * - end - end address (exclusive, may not be aligned) + * - vma - vma_struct describing address range + */ +ENTRY(__cpu_flush_user_tlb_range) +#ifndef CONFIG_CPU_TLB_SINGLE_ENTRY_DISABLE + mov r0, r0 >> #PAGE_SHIFT @ align address + mov r0, r0 << #PAGE_SHIFT + vma_vm_flags r2, r2 @ get vma->vm_flags +1: + movc p0.c6, r0, #3 + nop8 + + cand.a r2, #VM_EXEC @ Executable area ? + beq 2f + + movc p0.c6, r0, #5 + nop8 +2: + add r0, r0, #PAGE_SZ + csub.a r0, r1 + beb 1b +#else + movc p0.c6, r0, #2 + nop8 + + cand.a r2, #VM_EXEC @ Executable area ? + beq 2f + + movc p0.c6, r0, #4 + nop8 +2: +#endif + mov pc, lr + +/* + * __cpu_flush_kern_tlb_range(start,end) + * + * Invalidate a range of kernel TLB entries + * + * - start - start address (may not be aligned) + * - end - end address (exclusive, may not be aligned) + */ +ENTRY(__cpu_flush_kern_tlb_range) +#ifndef CONFIG_CPU_TLB_SINGLE_ENTRY_DISABLE + mov r0, r0 >> #PAGE_SHIFT @ align address + mov r0, r0 << #PAGE_SHIFT +1: + movc p0.c6, r0, #3 + nop8 + + movc p0.c6, r0, #5 + nop8 + + add r0, r0, #PAGE_SZ + csub.a r0, r1 + beb 1b +#else + movc p0.c6, r0, #2 + nop8 + + movc p0.c6, r0, #4 + nop8 +#endif + mov pc, lr + diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index d5ed94d30aad..e1f65c46bc93 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -64,8 +64,12 @@ config X86 select HAVE_TEXT_POKE_SMP select HAVE_GENERIC_HARDIRQS select HAVE_SPARSE_IRQ + select GENERIC_FIND_FIRST_BIT + select GENERIC_FIND_NEXT_BIT select GENERIC_IRQ_PROBE select GENERIC_PENDING_IRQ if SMP + select GENERIC_IRQ_SHOW + select IRQ_FORCED_THREADING select USE_GENERIC_SMP_HELPERS if SMP config INSTRUCTION_DECODER @@ -217,10 +221,6 @@ config X86_HT def_bool y depends on SMP -config X86_TRAMPOLINE - def_bool y - depends on SMP || (64BIT && ACPI_SLEEP) - config X86_32_LAZY_GS def_bool y depends on X86_32 && !CC_STACKPROTECTOR @@ -382,6 +382,8 @@ config X86_INTEL_CE depends on X86_32 depends on X86_EXTENDED_PLATFORM select X86_REBOOTFIXUPS + select OF + select OF_EARLY_FLATTREE ---help--- Select for the Intel CE media processor (CE4100) SOC. This option compiles in support for the CE4100 SOC for settop @@ -811,7 +813,7 @@ config X86_LOCAL_APIC config X86_IO_APIC def_bool y - depends on X86_64 || SMP || X86_32_NON_STANDARD || X86_UP_APIC + depends on X86_64 || SMP || X86_32_NON_STANDARD || X86_UP_IOAPIC config X86_VISWS_APIC def_bool y @@ -1705,7 +1707,7 @@ config HAVE_ARCH_EARLY_PFN_TO_NID depends on NUMA config USE_PERCPU_NUMA_NODE_ID - def_bool X86_64 + def_bool y depends on NUMA menu "Power management and ACPI options" @@ -2066,9 +2068,10 @@ config SCx200HR_TIMER config OLPC bool "One Laptop Per Child support" + depends on !X86_PAE select GPIOLIB - select OLPC_OPENFIRMWARE - depends on !X86_64 && !X86_PAE + select OF + select OF_PROMTREE if PROC_DEVICETREE ---help--- Add support for detecting the unique features of the OLPC XO hardware. @@ -2079,21 +2082,6 @@ config OLPC_XO1 ---help--- Add support for non-essential features of the OLPC XO-1 laptop. -config OLPC_OPENFIRMWARE - bool "Support for OLPC's Open Firmware" - depends on !X86_64 && !X86_PAE - default n - select OF - help - This option adds support for the implementation of Open Firmware - that is used on the OLPC XO-1 Children's Machine. - If unsure, say N here. - -config OLPC_OPENFIRMWARE_DT - bool - default y if OLPC_OPENFIRMWARE && PROC_DEVICETREE - select OF_PROMTREE - endif # X86_32 config AMD_NB @@ -2138,6 +2126,11 @@ config SYSVIPC_COMPAT def_bool y depends on COMPAT && SYSVIPC +config KEYS_COMPAT + bool + depends on COMPAT && KEYS + default y + endmenu diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 283c5a6a03a6..ed47e6e1747f 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -294,11 +294,6 @@ config X86_GENERIC endif -config X86_CPU - def_bool y - select GENERIC_FIND_FIRST_BIT - select GENERIC_FIND_NEXT_BIT - # # Define implied options from the CPU selection here config X86_INTERNODE_CACHE_SHIFT diff --git a/arch/x86/crypto/aesni-intel_glue.c b/arch/x86/crypto/aesni-intel_glue.c index e1e60c7d5813..e0e6340c8dad 100644 --- a/arch/x86/crypto/aesni-intel_glue.c +++ b/arch/x86/crypto/aesni-intel_glue.c @@ -873,22 +873,18 @@ rfc4106_set_hash_subkey(u8 *hash_subkey, const u8 *key, unsigned int key_len) crypto_ablkcipher_clear_flags(ctr_tfm, ~0); ret = crypto_ablkcipher_setkey(ctr_tfm, key, key_len); - if (ret) { - crypto_free_ablkcipher(ctr_tfm); - return ret; - } + if (ret) + goto out_free_ablkcipher; + ret = -ENOMEM; req = ablkcipher_request_alloc(ctr_tfm, GFP_KERNEL); - if (!req) { - crypto_free_ablkcipher(ctr_tfm); - return -EINVAL; - } + if (!req) + goto out_free_ablkcipher; req_data = kmalloc(sizeof(*req_data), GFP_KERNEL); - if (!req_data) { - crypto_free_ablkcipher(ctr_tfm); - return -ENOMEM; - } + if (!req_data) + goto out_free_request; + memset(req_data->iv, 0, sizeof(req_data->iv)); /* Clear the data in the hash sub key container to zero.*/ @@ -913,8 +909,10 @@ rfc4106_set_hash_subkey(u8 *hash_subkey, const u8 *key, unsigned int key_len) if (!ret) ret = req_data->result.err; } - ablkcipher_request_free(req); kfree(req_data); +out_free_request: + ablkcipher_request_free(req); +out_free_ablkcipher: crypto_free_ablkcipher(ctr_tfm); return ret; } diff --git a/arch/x86/ia32/ia32entry.S b/arch/x86/ia32/ia32entry.S index 518bb99c3394..430312ba6e3f 100644 --- a/arch/x86/ia32/ia32entry.S +++ b/arch/x86/ia32/ia32entry.S @@ -25,6 +25,8 @@ #define sysretl_audit ia32_ret_from_sys_call #endif + .section .entry.text, "ax" + #define IA32_NR_syscalls ((ia32_syscall_end - ia32_sys_call_table)/8) .macro IA32_ARG_FIXUP noebp=0 @@ -126,26 +128,20 @@ ENTRY(ia32_sysenter_target) */ ENABLE_INTERRUPTS(CLBR_NONE) movl %ebp,%ebp /* zero extension */ - pushq $__USER32_DS - CFI_ADJUST_CFA_OFFSET 8 + pushq_cfi $__USER32_DS /*CFI_REL_OFFSET ss,0*/ - pushq %rbp - CFI_ADJUST_CFA_OFFSET 8 + pushq_cfi %rbp CFI_REL_OFFSET rsp,0 - pushfq - CFI_ADJUST_CFA_OFFSET 8 + pushfq_cfi /*CFI_REL_OFFSET rflags,0*/ movl 8*3-THREAD_SIZE+TI_sysenter_return(%rsp), %r10d CFI_REGISTER rip,r10 - pushq $__USER32_CS - CFI_ADJUST_CFA_OFFSET 8 + pushq_cfi $__USER32_CS /*CFI_REL_OFFSET cs,0*/ movl %eax, %eax - pushq %r10 - CFI_ADJUST_CFA_OFFSET 8 + pushq_cfi %r10 CFI_REL_OFFSET rip,0 - pushq %rax - CFI_ADJUST_CFA_OFFSET 8 + pushq_cfi %rax cld SAVE_ARGS 0,0,1 /* no need to do an access_ok check here because rbp has been @@ -182,11 +178,9 @@ sysexit_from_sys_call: xorq %r9,%r9 xorq %r10,%r10 xorq %r11,%r11 - popfq - CFI_ADJUST_CFA_OFFSET -8 + popfq_cfi /*CFI_RESTORE rflags*/ - popq %rcx /* User %esp */ - CFI_ADJUST_CFA_OFFSET -8 + popq_cfi %rcx /* User %esp */ CFI_REGISTER rsp,rcx TRACE_IRQS_ON ENABLE_INTERRUPTS_SYSEXIT32 @@ -421,8 +415,7 @@ ENTRY(ia32_syscall) */ ENABLE_INTERRUPTS(CLBR_NONE) movl %eax,%eax - pushq %rax - CFI_ADJUST_CFA_OFFSET 8 + pushq_cfi %rax cld /* note the registers are not zero extended to the sf. this could be a problem. */ @@ -851,4 +844,7 @@ ia32_sys_call_table: .quad sys_fanotify_init .quad sys32_fanotify_mark .quad sys_prlimit64 /* 340 */ + .quad sys_name_to_handle_at + .quad compat_sys_open_by_handle_at + .quad compat_sys_clock_adjtime ia32_syscall_end: diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h index 4ea15ca89b2b..448d73a371ba 100644 --- a/arch/x86/include/asm/acpi.h +++ b/arch/x86/include/asm/acpi.h @@ -29,6 +29,7 @@ #include <asm/processor.h> #include <asm/mmu.h> #include <asm/mpspec.h> +#include <asm/trampoline.h> #define COMPILER_DEPENDENT_INT64 long long #define COMPILER_DEPENDENT_UINT64 unsigned long long @@ -117,7 +118,8 @@ static inline void acpi_disable_pci(void) extern int acpi_save_state_mem(void); extern void acpi_restore_state_mem(void); -extern unsigned long acpi_wakeup_address; +extern const unsigned char acpi_wakeup_code[]; +#define acpi_wakeup_address (__pa(TRAMPOLINE_SYM(acpi_wakeup_code))) /* early initialization routine */ extern void acpi_reserve_wakeup_memory(void); @@ -186,15 +188,7 @@ struct bootnode; #ifdef CONFIG_ACPI_NUMA extern int acpi_numa; -extern void acpi_get_nodes(struct bootnode *physnodes, unsigned long start, - unsigned long end); -extern int acpi_scan_nodes(unsigned long start, unsigned long end); -#define NR_NODE_MEMBLKS (MAX_NUMNODES*2) - -#ifdef CONFIG_NUMA_EMU -extern void acpi_fake_nodes(const struct bootnode *fake_nodes, - int num_nodes); -#endif +extern int x86_acpi_numa_init(void); #endif /* CONFIG_ACPI_NUMA */ #define acpi_unlazy_tlb(x) leave_mm(x) diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h index 64dc82ee19f0..331682231bb4 100644 --- a/arch/x86/include/asm/amd_nb.h +++ b/arch/x86/include/asm/amd_nb.h @@ -9,23 +9,20 @@ struct amd_nb_bus_dev_range { u8 dev_limit; }; -extern struct pci_device_id amd_nb_misc_ids[]; +extern const struct pci_device_id amd_nb_misc_ids[]; extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[]; struct bootnode; -extern int early_is_amd_nb(u32 value); +extern bool early_is_amd_nb(u32 value); extern int amd_cache_northbridges(void); extern void amd_flush_garts(void); -extern int amd_numa_init(unsigned long start_pfn, unsigned long end_pfn); -extern int amd_scan_nodes(void); - -#ifdef CONFIG_NUMA_EMU -extern void amd_fake_nodes(const struct bootnode *nodes, int nr_nodes); -extern void amd_get_nodes(struct bootnode *nodes); -#endif +extern int amd_numa_init(void); +extern int amd_get_subcaches(int); +extern int amd_set_subcaches(int, int); struct amd_northbridge { struct pci_dev *misc; + struct pci_dev *link; }; struct amd_northbridge_info { @@ -35,17 +32,18 @@ struct amd_northbridge_info { }; extern struct amd_northbridge_info amd_northbridges; -#define AMD_NB_GART 0x1 -#define AMD_NB_L3_INDEX_DISABLE 0x2 +#define AMD_NB_GART BIT(0) +#define AMD_NB_L3_INDEX_DISABLE BIT(1) +#define AMD_NB_L3_PARTITIONING BIT(2) #ifdef CONFIG_AMD_NB -static inline int amd_nb_num(void) +static inline u16 amd_nb_num(void) { return amd_northbridges.num; } -static inline int amd_nb_has_feature(int feature) +static inline bool amd_nb_has_feature(unsigned feature) { return ((amd_northbridges.flags & feature) == feature); } diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 3c896946f4cc..a279d98ea95e 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -220,7 +220,6 @@ extern void enable_IR_x2apic(void); extern int get_physical_broadcast(void); -extern void apic_disable(void); extern int lapic_get_maxlvt(void); extern void clear_local_APIC(void); extern void connect_bsp_APIC(void); @@ -228,7 +227,6 @@ extern void disconnect_bsp_APIC(int virt_wire_setup); extern void disable_local_APIC(void); extern void lapic_shutdown(void); extern int verify_local_APIC(void); -extern void cache_APIC_registers(void); extern void sync_Arb_IDs(void); extern void init_bsp_APIC(void); extern void setup_local_APIC(void); @@ -239,8 +237,7 @@ void register_lapic_address(unsigned long address); extern void setup_boot_APIC_clock(void); extern void setup_secondary_APIC_clock(void); extern int APIC_init_uniprocessor(void); -extern void enable_NMI_through_LVT0(void); -extern int apic_force_enable(void); +extern int apic_force_enable(unsigned long addr); /* * On 32bit this is mach-xxx local @@ -261,7 +258,6 @@ static inline void lapic_shutdown(void) { } #define local_apic_timer_c2_ok 1 static inline void init_apic_mappings(void) { } static inline void disable_local_APIC(void) { } -static inline void apic_disable(void) { } # define setup_boot_APIC_clock x86_init_noop # define setup_secondary_APIC_clock x86_init_noop #endif /* !CONFIG_X86_LOCAL_APIC */ @@ -307,8 +303,6 @@ struct apic { void (*setup_apic_routing)(void); int (*multi_timer_check)(int apic, int irq); - int (*apicid_to_node)(int logical_apicid); - int (*cpu_to_logical_apicid)(int cpu); int (*cpu_present_to_apicid)(int mps_cpu); void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); void (*setup_portio_remap)(void); @@ -356,6 +350,23 @@ struct apic { void (*icr_write)(u32 low, u32 high); void (*wait_icr_idle)(void); u32 (*safe_wait_icr_idle)(void); + +#ifdef CONFIG_X86_32 + /* + * Called very early during boot from get_smp_config(). It should + * return the logical apicid. x86_[bios]_cpu_to_apicid is + * initialized before this function is called. + * + * If logical apicid can't be determined that early, the function + * may return BAD_APICID. Logical apicid will be configured after + * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity + * won't be applied properly during early boot in this case. + */ + int (*x86_32_early_logical_apicid)(int cpu); + + /* determine CPU -> NUMA node mapping */ + int (*x86_32_numa_cpu_node)(int cpu); +#endif }; /* @@ -503,6 +514,11 @@ extern struct apic apic_noop; extern struct apic apic_default; +static inline int noop_x86_32_early_logical_apicid(int cpu) +{ + return BAD_APICID; +} + /* * Set up the logical destination ID. * @@ -522,7 +538,7 @@ static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) return cpuid_apic >> index_msb; } -extern int default_apicid_to_node(int logical_apicid); +extern int default_x86_32_numa_cpu_node(int cpu); #endif @@ -558,12 +574,6 @@ static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_ma *retmap = *phys_map; } -/* Mapping from cpu number to logical apicid */ -static inline int default_cpu_to_logical_apicid(int cpu) -{ - return 1 << cpu; -} - static inline int __default_cpu_present_to_apicid(int mps_cpu) { if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) @@ -596,8 +606,4 @@ extern int default_check_phys_apicid_present(int phys_apicid); #endif /* CONFIG_X86_LOCAL_APIC */ -#ifdef CONFIG_X86_32 -extern u8 cpu_2_logical_apicid[NR_CPUS]; -#endif - #endif /* _ASM_X86_APIC_H */ diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index 47a30ff8e517..d87988bacf3e 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h @@ -426,4 +426,16 @@ struct local_apic { #else #define BAD_APICID 0xFFFFu #endif + +enum ioapic_irq_destination_types { + dest_Fixed = 0, + dest_LowestPrio = 1, + dest_SMI = 2, + dest__reserved_1 = 3, + dest_NMI = 4, + dest_INIT = 5, + dest__reserved_2 = 6, + dest_ExtINT = 7 +}; + #endif /* _ASM_X86_APICDEF_H */ diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h index c8bfe63a06de..e020d88ec02d 100644 --- a/arch/x86/include/asm/bootparam.h +++ b/arch/x86/include/asm/bootparam.h @@ -12,6 +12,7 @@ /* setup data types */ #define SETUP_NONE 0 #define SETUP_E820_EXT 1 +#define SETUP_DTB 2 /* extensible setup data list node */ struct setup_data { diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 220e2ea08e80..91f3e087cf21 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -160,6 +160,7 @@ #define X86_FEATURE_NODEID_MSR (6*32+19) /* NodeId MSR */ #define X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */ #define X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */ +#define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */ /* * Auxiliary flags: Linux defined - For features scattered in various @@ -279,6 +280,7 @@ extern const char * const x86_power_flags[32]; #define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE) #define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR) #define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ) +#define cpu_has_perfctr_core boot_cpu_has(X86_FEATURE_PERFCTR_CORE) #if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64) # define cpu_has_invlpg 1 diff --git a/arch/x86/include/asm/e820.h b/arch/x86/include/asm/e820.h index e99d55d74df5..908b96957d88 100644 --- a/arch/x86/include/asm/e820.h +++ b/arch/x86/include/asm/e820.h @@ -96,7 +96,7 @@ extern void e820_setup_gap(void); extern int e820_search_gap(unsigned long *gapstart, unsigned long *gapsize, unsigned long start_addr, unsigned long long end_addr); struct setup_data; -extern void parse_e820_ext(struct setup_data *data, unsigned long pa_data); +extern void parse_e820_ext(struct setup_data *data); #if defined(CONFIG_X86_64) || \ (defined(CONFIG_X86_32) && defined(CONFIG_HIBERNATION)) diff --git a/arch/x86/include/asm/entry_arch.h b/arch/x86/include/asm/entry_arch.h index 57650ab4a5f5..1cd6d26a0a8d 100644 --- a/arch/x86/include/asm/entry_arch.h +++ b/arch/x86/include/asm/entry_arch.h @@ -16,10 +16,13 @@ BUILD_INTERRUPT(call_function_single_interrupt,CALL_FUNCTION_SINGLE_VECTOR) BUILD_INTERRUPT(irq_move_cleanup_interrupt,IRQ_MOVE_CLEANUP_VECTOR) BUILD_INTERRUPT(reboot_interrupt,REBOOT_VECTOR) -.irpc idx, "01234567" +.irp idx,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15, \ + 16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 +.if NUM_INVALIDATE_TLB_VECTORS > \idx BUILD_INTERRUPT3(invalidate_interrupt\idx, (INVALIDATE_TLB_VECTOR_START)+\idx, smp_invalidate_interrupt) +.endif .endr #endif diff --git a/arch/x86/include/asm/frame.h b/arch/x86/include/asm/frame.h index 06850a7194e1..2c6fc9e62812 100644 --- a/arch/x86/include/asm/frame.h +++ b/arch/x86/include/asm/frame.h @@ -7,14 +7,12 @@ frame pointer later */ #ifdef CONFIG_FRAME_POINTER .macro FRAME - pushl %ebp - CFI_ADJUST_CFA_OFFSET 4 + pushl_cfi %ebp CFI_REL_OFFSET ebp,0 movl %esp,%ebp .endm .macro ENDFRAME - popl %ebp - CFI_ADJUST_CFA_OFFSET -4 + popl_cfi %ebp CFI_RESTORE ebp .endm #else diff --git a/arch/x86/include/asm/futex.h b/arch/x86/include/asm/futex.h index 1f11ce44e956..d09bb03653f0 100644 --- a/arch/x86/include/asm/futex.h +++ b/arch/x86/include/asm/futex.h @@ -37,7 +37,7 @@ "+m" (*uaddr), "=&r" (tem) \ : "r" (oparg), "i" (-EFAULT), "1" (0)) -static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr) +static inline int futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr) { int op = (encoded_op >> 28) & 7; int cmp = (encoded_op >> 24) & 15; @@ -48,7 +48,7 @@ static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr) if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) oparg = 1 << oparg; - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_BSWAP) @@ -109,9 +109,10 @@ static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr) return ret; } -static inline int futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, - int newval) +static inline int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) { + int ret = 0; #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_BSWAP) /* Real i386 machines have no cmpxchg instruction */ @@ -119,21 +120,22 @@ static inline int futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, return -ENOSYS; #endif - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; - asm volatile("1:\t" LOCK_PREFIX "cmpxchgl %3, %1\n" + asm volatile("1:\t" LOCK_PREFIX "cmpxchgl %4, %2\n" "2:\t.section .fixup, \"ax\"\n" - "3:\tmov %2, %0\n" + "3:\tmov %3, %0\n" "\tjmp 2b\n" "\t.previous\n" _ASM_EXTABLE(1b, 3b) - : "=a" (oldval), "+m" (*uaddr) - : "i" (-EFAULT), "r" (newval), "0" (oldval) + : "+r" (ret), "=a" (oldval), "+m" (*uaddr) + : "i" (-EFAULT), "r" (newval), "1" (oldval) : "memory" ); - return oldval; + *uval = oldval; + return ret; } #endif diff --git a/arch/x86/include/asm/hw_irq.h b/arch/x86/include/asm/hw_irq.h index 0274ec5a7e62..bb9efe8706e2 100644 --- a/arch/x86/include/asm/hw_irq.h +++ b/arch/x86/include/asm/hw_irq.h @@ -45,6 +45,30 @@ extern void invalidate_interrupt4(void); extern void invalidate_interrupt5(void); extern void invalidate_interrupt6(void); extern void invalidate_interrupt7(void); +extern void invalidate_interrupt8(void); +extern void invalidate_interrupt9(void); +extern void invalidate_interrupt10(void); +extern void invalidate_interrupt11(void); +extern void invalidate_interrupt12(void); +extern void invalidate_interrupt13(void); +extern void invalidate_interrupt14(void); +extern void invalidate_interrupt15(void); +extern void invalidate_interrupt16(void); +extern void invalidate_interrupt17(void); +extern void invalidate_interrupt18(void); +extern void invalidate_interrupt19(void); +extern void invalidate_interrupt20(void); +extern void invalidate_interrupt21(void); +extern void invalidate_interrupt22(void); +extern void invalidate_interrupt23(void); +extern void invalidate_interrupt24(void); +extern void invalidate_interrupt25(void); +extern void invalidate_interrupt26(void); +extern void invalidate_interrupt27(void); +extern void invalidate_interrupt28(void); +extern void invalidate_interrupt29(void); +extern void invalidate_interrupt30(void); +extern void invalidate_interrupt31(void); extern void irq_move_cleanup_interrupt(void); extern void reboot_interrupt(void); diff --git a/arch/x86/include/asm/init.h b/arch/x86/include/asm/init.h index 36fb1a6a5109..8dbe353e41e1 100644 --- a/arch/x86/include/asm/init.h +++ b/arch/x86/include/asm/init.h @@ -11,8 +11,8 @@ kernel_physical_mapping_init(unsigned long start, unsigned long page_size_mask); -extern unsigned long __initdata e820_table_start; -extern unsigned long __meminitdata e820_table_end; -extern unsigned long __meminitdata e820_table_top; +extern unsigned long __initdata pgt_buf_start; +extern unsigned long __meminitdata pgt_buf_end; +extern unsigned long __meminitdata pgt_buf_top; #endif /* _ASM_X86_INIT_32_H */ diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h index f327d386d6cc..c4bd267dfc50 100644 --- a/arch/x86/include/asm/io_apic.h +++ b/arch/x86/include/asm/io_apic.h @@ -63,17 +63,6 @@ union IO_APIC_reg_03 { } __attribute__ ((packed)) bits; }; -enum ioapic_irq_destination_types { - dest_Fixed = 0, - dest_LowestPrio = 1, - dest_SMI = 2, - dest__reserved_1 = 3, - dest_NMI = 4, - dest_INIT = 5, - dest__reserved_2 = 6, - dest_ExtINT = 7 -}; - struct IO_APIC_route_entry { __u32 vector : 8, delivery_mode : 3, /* 000: FIXED @@ -106,6 +95,10 @@ struct IR_IO_APIC_route_entry { index : 15; } __attribute__ ((packed)); +#define IOAPIC_AUTO -1 +#define IOAPIC_EDGE 0 +#define IOAPIC_LEVEL 1 + #ifdef CONFIG_X86_IO_APIC /* @@ -150,11 +143,6 @@ extern int timer_through_8259; #define io_apic_assign_pci_irqs \ (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs) -extern u8 io_apic_unique_id(u8 id); -extern int io_apic_get_unique_id(int ioapic, int apic_id); -extern int io_apic_get_version(int ioapic); -extern int io_apic_get_redir_entries(int ioapic); - struct io_apic_irq_attr; extern int io_apic_set_pci_routing(struct device *dev, int irq, struct io_apic_irq_attr *irq_attr); @@ -162,6 +150,8 @@ void setup_IO_APIC_irq_extra(u32 gsi); extern void ioapic_and_gsi_init(void); extern void ioapic_insert_resources(void); +int io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr); + extern struct IO_APIC_route_entry **alloc_ioapic_entries(void); extern void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries); extern int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries); @@ -186,6 +176,8 @@ extern void __init pre_init_apic_IRQ0(void); extern void mp_save_irq(struct mpc_intsrc *m); +extern void disable_ioapic_support(void); + #else /* !CONFIG_X86_IO_APIC */ #define io_apic_assign_pci_irqs 0 @@ -199,6 +191,26 @@ static inline int mp_find_ioapic(u32 gsi) { return 0; } struct io_apic_irq_attr; static inline int io_apic_set_pci_routing(struct device *dev, int irq, struct io_apic_irq_attr *irq_attr) { return 0; } + +static inline struct IO_APIC_route_entry **alloc_ioapic_entries(void) +{ + return NULL; +} + +static inline void free_ioapic_entries(struct IO_APIC_route_entry **ent) { } +static inline int save_IO_APIC_setup(struct IO_APIC_route_entry **ent) +{ + return -ENOMEM; +} + +static inline void mask_IO_APIC_setup(struct IO_APIC_route_entry **ent) { } +static inline int restore_IO_APIC_setup(struct IO_APIC_route_entry **ent) +{ + return -ENOMEM; +} + +static inline void mp_save_irq(struct mpc_intsrc *m) { }; +static inline void disable_ioapic_support(void) { } #endif #endif /* _ASM_X86_IO_APIC_H */ diff --git a/arch/x86/include/asm/ipi.h b/arch/x86/include/asm/ipi.h index 0b7228268a63..615fa9061b57 100644 --- a/arch/x86/include/asm/ipi.h +++ b/arch/x86/include/asm/ipi.h @@ -123,10 +123,6 @@ extern void default_send_IPI_mask_sequence_phys(const struct cpumask *mask, int vector); extern void default_send_IPI_mask_allbutself_phys(const struct cpumask *mask, int vector); -extern void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, - int vector); -extern void default_send_IPI_mask_allbutself_logical(const struct cpumask *mask, - int vector); /* Avoid include hell */ #define NMI_VECTOR 0x02 @@ -150,6 +146,10 @@ static inline void __default_local_send_IPI_all(int vector) } #ifdef CONFIG_X86_32 +extern void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, + int vector); +extern void default_send_IPI_mask_allbutself_logical(const struct cpumask *mask, + int vector); extern void default_send_IPI_mask_logical(const struct cpumask *mask, int vector); extern void default_send_IPI_allbutself(int vector); diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h index c704b38c57a2..ba870bb6dd8e 100644 --- a/arch/x86/include/asm/irq.h +++ b/arch/x86/include/asm/irq.h @@ -10,9 +10,6 @@ #include <asm/apicdef.h> #include <asm/irq_vectors.h> -/* Even though we don't support this, supply it to appease OF */ -static inline void irq_dispose_mapping(unsigned int virq) { } - static inline int irq_canonicalize(int irq) { return ((irq == 2) ? 9 : irq); diff --git a/arch/x86/include/asm/irq_controller.h b/arch/x86/include/asm/irq_controller.h new file mode 100644 index 000000000000..423bbbddf36d --- /dev/null +++ b/arch/x86/include/asm/irq_controller.h @@ -0,0 +1,12 @@ +#ifndef __IRQ_CONTROLLER__ +#define __IRQ_CONTROLLER__ + +struct irq_domain { + int (*xlate)(struct irq_domain *h, const u32 *intspec, u32 intsize, + u32 *out_hwirq, u32 *out_type); + void *priv; + struct device_node *controller; + struct list_head l; +}; + +#endif diff --git a/arch/x86/include/asm/irq_vectors.h b/arch/x86/include/asm/irq_vectors.h index 6af0894dafb4..6e976ee3b3ef 100644 --- a/arch/x86/include/asm/irq_vectors.h +++ b/arch/x86/include/asm/irq_vectors.h @@ -1,6 +1,7 @@ #ifndef _ASM_X86_IRQ_VECTORS_H #define _ASM_X86_IRQ_VECTORS_H +#include <linux/threads.h> /* * Linux IRQ vector layout. * @@ -16,8 +17,8 @@ * Vectors 0 ... 31 : system traps and exceptions - hardcoded events * Vectors 32 ... 127 : device interrupts * Vector 128 : legacy int80 syscall interface - * Vectors 129 ... 237 : device interrupts - * Vectors 238 ... 255 : special interrupts + * Vectors 129 ... INVALIDATE_TLB_VECTOR_START-1 : device interrupts + * Vectors INVALIDATE_TLB_VECTOR_START ... 255 : special interrupts * * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table. * @@ -96,37 +97,43 @@ #define THRESHOLD_APIC_VECTOR 0xf9 #define REBOOT_VECTOR 0xf8 -/* f0-f7 used for spreading out TLB flushes: */ -#define INVALIDATE_TLB_VECTOR_END 0xf7 -#define INVALIDATE_TLB_VECTOR_START 0xf0 -#define NUM_INVALIDATE_TLB_VECTORS 8 - -/* - * Local APIC timer IRQ vector is on a different priority level, - * to work around the 'lost local interrupt if more than 2 IRQ - * sources per level' errata. - */ -#define LOCAL_TIMER_VECTOR 0xef - /* * Generic system vector for platform specific use */ -#define X86_PLATFORM_IPI_VECTOR 0xed +#define X86_PLATFORM_IPI_VECTOR 0xf7 /* * IRQ work vector: */ -#define IRQ_WORK_VECTOR 0xec +#define IRQ_WORK_VECTOR 0xf6 -#define UV_BAU_MESSAGE 0xea +#define UV_BAU_MESSAGE 0xf5 /* * Self IPI vector for machine checks */ -#define MCE_SELF_VECTOR 0xeb +#define MCE_SELF_VECTOR 0xf4 /* Xen vector callback to receive events in a HVM domain */ -#define XEN_HVM_EVTCHN_CALLBACK 0xe9 +#define XEN_HVM_EVTCHN_CALLBACK 0xf3 + +/* + * Local APIC timer IRQ vector is on a different priority level, + * to work around the 'lost local interrupt if more than 2 IRQ + * sources per level' errata. + */ +#define LOCAL_TIMER_VECTOR 0xef + +/* up to 32 vectors used for spreading out TLB flushes: */ +#if NR_CPUS <= 32 +# define NUM_INVALIDATE_TLB_VECTORS (NR_CPUS) +#else +# define NUM_INVALIDATE_TLB_VECTORS (32) +#endif + +#define INVALIDATE_TLB_VECTOR_END (0xee) +#define INVALIDATE_TLB_VECTOR_START \ + (INVALIDATE_TLB_VECTOR_END-NUM_INVALIDATE_TLB_VECTORS+1) #define NR_VECTORS 256 diff --git a/arch/x86/include/asm/kdebug.h b/arch/x86/include/asm/kdebug.h index ca242d35e873..518bbbb9ee59 100644 --- a/arch/x86/include/asm/kdebug.h +++ b/arch/x86/include/asm/kdebug.h @@ -13,7 +13,6 @@ enum die_val { DIE_PANIC, DIE_NMI, DIE_DIE, - DIE_NMIWATCHDOG, DIE_KERNELDEBUG, DIE_TRAP, DIE_GPF, diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h index 0c90dd9f0505..9c7d95f6174b 100644 --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -25,7 +25,6 @@ extern int pic_mode; #define MAX_IRQ_SOURCES 256 extern unsigned int def_to_bigsmp; -extern u8 apicid_2_node[]; #ifdef CONFIG_X86_NUMAQ extern int mp_bus_id_to_node[MAX_MP_BUSSES]; @@ -33,8 +32,6 @@ extern int mp_bus_id_to_local[MAX_MP_BUSSES]; extern int quad_local_to_mp_bus_id [NR_CPUS/4][4]; #endif -#define MAX_APICID 256 - #else /* CONFIG_X86_64: */ #define MAX_MP_BUSSES 256 diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 43a18c77676d..823d48223400 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -52,6 +52,9 @@ #define MSR_IA32_MCG_STATUS 0x0000017a #define MSR_IA32_MCG_CTL 0x0000017b +#define MSR_OFFCORE_RSP_0 0x000001a6 +#define MSR_OFFCORE_RSP_1 0x000001a7 + #define MSR_IA32_PEBS_ENABLE 0x000003f1 #define MSR_IA32_DS_AREA 0x00000600 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 diff --git a/arch/x86/include/asm/nmi.h b/arch/x86/include/asm/nmi.h index c76f5b92b840..07f46016d3ff 100644 --- a/arch/x86/include/asm/nmi.h +++ b/arch/x86/include/asm/nmi.h @@ -7,7 +7,6 @@ #ifdef CONFIG_X86_LOCAL_APIC -extern void die_nmi(char *str, struct pt_regs *regs, int do_panic); extern int avail_to_resrv_perfctr_nmi_bit(unsigned int); extern int reserve_perfctr_nmi(unsigned int); extern void release_perfctr_nmi(unsigned int); diff --git a/arch/x86/include/asm/numa.h b/arch/x86/include/asm/numa.h index 27da400d3138..3d4dab43c994 100644 --- a/arch/x86/include/asm/numa.h +++ b/arch/x86/include/asm/numa.h @@ -1,5 +1,57 @@ +#ifndef _ASM_X86_NUMA_H +#define _ASM_X86_NUMA_H + +#include <asm/topology.h> +#include <asm/apicdef.h> + +#ifdef CONFIG_NUMA + +#define NR_NODE_MEMBLKS (MAX_NUMNODES*2) + +/* + * __apicid_to_node[] stores the raw mapping between physical apicid and + * node and is used to initialize cpu_to_node mapping. + * + * The mapping may be overridden by apic->numa_cpu_node() on 32bit and thus + * should be accessed by the accessors - set_apicid_to_node() and + * numa_cpu_node(). + */ +extern s16 __apicid_to_node[MAX_LOCAL_APIC]; + +static inline void set_apicid_to_node(int apicid, s16 node) +{ + __apicid_to_node[apicid] = node; +} +#else /* CONFIG_NUMA */ +static inline void set_apicid_to_node(int apicid, s16 node) +{ +} +#endif /* CONFIG_NUMA */ + #ifdef CONFIG_X86_32 # include "numa_32.h" #else # include "numa_64.h" #endif + +#ifdef CONFIG_NUMA +extern void __cpuinit numa_set_node(int cpu, int node); +extern void __cpuinit numa_clear_node(int cpu); +extern void __init numa_init_array(void); +extern void __init init_cpu_to_node(void); +extern void __cpuinit numa_add_cpu(int cpu); +extern void __cpuinit numa_remove_cpu(int cpu); +#else /* CONFIG_NUMA */ +static inline void numa_set_node(int cpu, int node) { } +static inline void numa_clear_node(int cpu) { } +static inline void numa_init_array(void) { } +static inline void init_cpu_to_node(void) { } +static inline void numa_add_cpu(int cpu) { } +static inline void numa_remove_cpu(int cpu) { } +#endif /* CONFIG_NUMA */ + +#ifdef CONFIG_DEBUG_PER_CPU_MAPS +struct cpumask __cpuinit *debug_cpumask_set_cpu(int cpu, int enable); +#endif + +#endif /* _ASM_X86_NUMA_H */ diff --git a/arch/x86/include/asm/numa_32.h b/arch/x86/include/asm/numa_32.h index b0ef2b449a9d..c6beed1ef103 100644 --- a/arch/x86/include/asm/numa_32.h +++ b/arch/x86/include/asm/numa_32.h @@ -4,7 +4,12 @@ extern int numa_off; extern int pxm_to_nid(int pxm); -extern void numa_remove_cpu(int cpu); + +#ifdef CONFIG_NUMA +extern int __cpuinit numa_cpu_node(int cpu); +#else /* CONFIG_NUMA */ +static inline int numa_cpu_node(int cpu) { return NUMA_NO_NODE; } +#endif /* CONFIG_NUMA */ #ifdef CONFIG_HIGHMEM extern void set_highmem_pages_init(void); diff --git a/arch/x86/include/asm/numa_64.h b/arch/x86/include/asm/numa_64.h index 0493be39607c..344eb1790b46 100644 --- a/arch/x86/include/asm/numa_64.h +++ b/arch/x86/include/asm/numa_64.h @@ -2,23 +2,16 @@ #define _ASM_X86_NUMA_64_H #include <linux/nodemask.h> -#include <asm/apicdef.h> struct bootnode { u64 start; u64 end; }; -extern int compute_hash_shift(struct bootnode *nodes, int numblks, - int *nodeids); - #define ZONE_ALIGN (1UL << (MAX_ORDER+PAGE_SHIFT)) -extern void numa_init_array(void); extern int numa_off; -extern s16 apicid_to_node[MAX_LOCAL_APIC]; - extern unsigned long numa_free_all_bootmem(void); extern void setup_node_bootmem(int nodeid, unsigned long start, unsigned long end); @@ -31,11 +24,11 @@ extern void setup_node_bootmem(int nodeid, unsigned long start, */ #define NODE_MIN_SIZE (4*1024*1024) -extern void __init init_cpu_to_node(void); -extern void __cpuinit numa_set_node(int cpu, int node); -extern void __cpuinit numa_clear_node(int cpu); -extern void __cpuinit numa_add_cpu(int cpu); -extern void __cpuinit numa_remove_cpu(int cpu); +extern nodemask_t numa_nodes_parsed __initdata; + +extern int __cpuinit numa_cpu_node(int cpu); +extern int __init numa_add_memblk(int nodeid, u64 start, u64 end); +extern void __init numa_set_distance(int from, int to, int distance); #ifdef CONFIG_NUMA_EMU #define FAKE_NODE_MIN_SIZE ((u64)32 << 20) @@ -43,11 +36,7 @@ extern void __cpuinit numa_remove_cpu(int cpu); void numa_emu_cmdline(char *); #endif /* CONFIG_NUMA_EMU */ #else -static inline void init_cpu_to_node(void) { } -static inline void numa_set_node(int cpu, int node) { } -static inline void numa_clear_node(int cpu) { } -static inline void numa_add_cpu(int cpu, int node) { } -static inline void numa_remove_cpu(int cpu) { } +static inline int numa_cpu_node(int cpu) { return NUMA_NO_NODE; } #endif #endif /* _ASM_X86_NUMA_64_H */ diff --git a/arch/x86/include/asm/olpc_ofw.h b/arch/x86/include/asm/olpc_ofw.h index 641988efe063..c5d3a5abbb9f 100644 --- a/arch/x86/include/asm/olpc_ofw.h +++ b/arch/x86/include/asm/olpc_ofw.h @@ -6,7 +6,7 @@ #define OLPC_OFW_SIG 0x2057464F /* aka "OFW " */ -#ifdef CONFIG_OLPC_OPENFIRMWARE +#ifdef CONFIG_OLPC extern bool olpc_ofw_is_installed(void); @@ -26,19 +26,15 @@ extern void setup_olpc_ofw_pgd(void); /* check if OFW was detected during boot */ extern bool olpc_ofw_present(void); -#else /* !CONFIG_OLPC_OPENFIRMWARE */ - -static inline bool olpc_ofw_is_installed(void) { return false; } +#else /* !CONFIG_OLPC */ static inline void olpc_ofw_detect(void) { } static inline void setup_olpc_ofw_pgd(void) { } -static inline bool olpc_ofw_present(void) { return false; } - -#endif /* !CONFIG_OLPC_OPENFIRMWARE */ +#endif /* !CONFIG_OLPC */ -#ifdef CONFIG_OLPC_OPENFIRMWARE_DT +#ifdef CONFIG_OF_PROMTREE extern void olpc_dt_build_devicetree(void); #else static inline void olpc_dt_build_devicetree(void) { } -#endif /* CONFIG_OLPC_OPENFIRMWARE_DT */ +#endif #endif /* _ASM_X86_OLPC_OFW_H */ diff --git a/arch/x86/include/asm/page_types.h b/arch/x86/include/asm/page_types.h index 1df66211fd1b..bce688d54c12 100644 --- a/arch/x86/include/asm/page_types.h +++ b/arch/x86/include/asm/page_types.h @@ -2,6 +2,7 @@ #define _ASM_X86_PAGE_DEFS_H #include <linux/const.h> +#include <linux/types.h> /* PAGE_SHIFT determines the page size */ #define PAGE_SHIFT 12 @@ -45,11 +46,15 @@ extern int devmem_is_allowed(unsigned long pagenr); extern unsigned long max_low_pfn_mapped; extern unsigned long max_pfn_mapped; +static inline phys_addr_t get_max_mapped(void) +{ + return (phys_addr_t)max_pfn_mapped << PAGE_SHIFT; +} + extern unsigned long init_memory_mapping(unsigned long start, unsigned long end); -extern void initmem_init(unsigned long start_pfn, unsigned long end_pfn, - int acpi, int k8); +extern void initmem_init(void); extern void free_initmem(void); #endif /* !__ASSEMBLY__ */ diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h index 7e172955ee57..a09e1f052d84 100644 --- a/arch/x86/include/asm/percpu.h +++ b/arch/x86/include/asm/percpu.h @@ -451,6 +451,26 @@ do { \ #define irqsafe_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) #endif /* !CONFIG_M386 */ +#ifdef CONFIG_X86_CMPXCHG64 +#define percpu_cmpxchg8b_double(pcp1, o1, o2, n1, n2) \ +({ \ + char __ret; \ + typeof(o1) __o1 = o1; \ + typeof(o1) __n1 = n1; \ + typeof(o2) __o2 = o2; \ + typeof(o2) __n2 = n2; \ + typeof(o2) __dummy = n2; \ + asm volatile("cmpxchg8b "__percpu_arg(1)"\n\tsetz %0\n\t" \ + : "=a"(__ret), "=m" (pcp1), "=d"(__dummy) \ + : "b"(__n1), "c"(__n2), "a"(__o1), "d"(__o2)); \ + __ret; \ +}) + +#define __this_cpu_cmpxchg_double_4(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg8b_double(pcp1, o1, o2, n1, n2) +#define this_cpu_cmpxchg_double_4(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg8b_double(pcp1, o1, o2, n1, n2) +#define irqsafe_cpu_cmpxchg_double_4(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg8b_double(pcp1, o1, o2, n1, n2) +#endif /* CONFIG_X86_CMPXCHG64 */ + /* * Per cpu atomic 64 bit operations are only available under 64 bit. * 32 bit must fall back to generic operations. @@ -480,6 +500,34 @@ do { \ #define irqsafe_cpu_xor_8(pcp, val) percpu_to_op("xor", (pcp), val) #define irqsafe_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval) #define irqsafe_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) + +/* + * Pretty complex macro to generate cmpxchg16 instruction. The instruction + * is not supported on early AMD64 processors so we must be able to emulate + * it in software. The address used in the cmpxchg16 instruction must be + * aligned to a 16 byte boundary. + */ +#define percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2) \ +({ \ + char __ret; \ + typeof(o1) __o1 = o1; \ + typeof(o1) __n1 = n1; \ + typeof(o2) __o2 = o2; \ + typeof(o2) __n2 = n2; \ + typeof(o2) __dummy; \ + alternative_io("call this_cpu_cmpxchg16b_emu\n\t" P6_NOP4, \ + "cmpxchg16b %%gs:(%%rsi)\n\tsetz %0\n\t", \ + X86_FEATURE_CX16, \ + ASM_OUTPUT2("=a"(__ret), "=d"(__dummy)), \ + "S" (&pcp1), "b"(__n1), "c"(__n2), \ + "a"(__o1), "d"(__o2)); \ + __ret; \ +}) + +#define __this_cpu_cmpxchg_double_8(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2) +#define this_cpu_cmpxchg_double_8(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2) +#define irqsafe_cpu_cmpxchg_double_8(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2) + #endif /* This is not atomic against other CPUs -- CPU preemption needs to be off */ diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 45636cefa186..4c25ab48257b 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -94,10 +94,6 @@ struct cpuinfo_x86 { int x86_cache_alignment; /* In bytes */ int x86_power; unsigned long loops_per_jiffy; -#ifdef CONFIG_SMP - /* cpus sharing the last level cache: */ - cpumask_var_t llc_shared_map; -#endif /* cpuid returned max cores value: */ u16 x86_max_cores; u16 apicid; diff --git a/arch/x86/include/asm/prom.h b/arch/x86/include/asm/prom.h index b4ec95f07518..971e0b46446e 100644 --- a/arch/x86/include/asm/prom.h +++ b/arch/x86/include/asm/prom.h @@ -1 +1,69 @@ -/* dummy prom.h; here to make linux/of.h's #includes happy */ +/* + * Definitions for Device tree / OpenFirmware handling on X86 + * + * based on arch/powerpc/include/asm/prom.h which is + * Copyright (C) 1996-2005 Paul Mackerras. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#ifndef _ASM_X86_PROM_H +#define _ASM_X86_PROM_H +#ifndef __ASSEMBLY__ + +#include <linux/of.h> +#include <linux/types.h> +#include <linux/pci.h> + +#include <asm/irq.h> +#include <asm/atomic.h> +#include <asm/setup.h> +#include <asm/irq_controller.h> + +#ifdef CONFIG_OF +extern int of_ioapic; +extern u64 initial_dtb; +extern void add_dtb(u64 data); +extern void x86_add_irq_domains(void); +void __cpuinit x86_of_pci_init(void); +void x86_dtb_init(void); + +static inline struct device_node *pci_device_to_OF_node(struct pci_dev *pdev) +{ + return pdev ? pdev->dev.of_node : NULL; +} + +static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) +{ + return pci_device_to_OF_node(bus->self); +} + +#else +static inline void add_dtb(u64 data) { } +static inline void x86_add_irq_domains(void) { } +static inline void x86_of_pci_init(void) { } +static inline void x86_dtb_init(void) { } +#define of_ioapic 0 +#endif + +extern char cmd_line[COMMAND_LINE_SIZE]; + +#define pci_address_to_pio pci_address_to_pio +unsigned long pci_address_to_pio(phys_addr_t addr); + +/** + * irq_dispose_mapping - Unmap an interrupt + * @virq: linux virq number of the interrupt to unmap + * + * FIXME: We really should implement proper virq handling like power, + * but that's going to be major surgery. + */ +static inline void irq_dispose_mapping(unsigned int virq) { } + +#define HAVE_ARCH_DEVTREE_FIXUPS + +#endif /* __ASSEMBLY__ */ +#endif diff --git a/arch/x86/include/asm/reboot.h b/arch/x86/include/asm/reboot.h index 562d4fd31ba8..3250e3d605d9 100644 --- a/arch/x86/include/asm/reboot.h +++ b/arch/x86/include/asm/reboot.h @@ -18,7 +18,10 @@ extern struct machine_ops machine_ops; void native_machine_crash_shutdown(struct pt_regs *regs); void native_machine_shutdown(void); -void machine_real_restart(const unsigned char *code, int length); +void machine_real_restart(unsigned int type); +/* These must match dispatch_table in reboot_32.S */ +#define MRR_BIOS 0 +#define MRR_APM 1 typedef void (*nmi_shootdown_cb)(int, struct die_args*); void nmi_shootdown_cpus(nmi_shootdown_cb callback); diff --git a/arch/x86/include/asm/rwsem.h b/arch/x86/include/asm/rwsem.h index d1e41b0f9b60..df4cd32b4cc6 100644 --- a/arch/x86/include/asm/rwsem.h +++ b/arch/x86/include/asm/rwsem.h @@ -37,26 +37,9 @@ #endif #ifdef __KERNEL__ - -#include <linux/list.h> -#include <linux/spinlock.h> -#include <linux/lockdep.h> #include <asm/asm.h> -struct rwsem_waiter; - -extern asmregparm struct rw_semaphore * - rwsem_down_read_failed(struct rw_semaphore *sem); -extern asmregparm struct rw_semaphore * - rwsem_down_write_failed(struct rw_semaphore *sem); -extern asmregparm struct rw_semaphore * - rwsem_wake(struct rw_semaphore *); -extern asmregparm struct rw_semaphore * - rwsem_downgrade_wake(struct rw_semaphore *sem); - /* - * the semaphore definition - * * The bias values and the counter type limits the number of * potential readers/writers to 32767 for 32 bits and 2147483647 * for 64 bits. @@ -74,43 +57,6 @@ extern asmregparm struct rw_semaphore * #define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS #define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS) -typedef signed long rwsem_count_t; - -struct rw_semaphore { - rwsem_count_t count; - spinlock_t wait_lock; - struct list_head wait_list; -#ifdef CONFIG_DEBUG_LOCK_ALLOC - struct lockdep_map dep_map; -#endif -}; - -#ifdef CONFIG_DEBUG_LOCK_ALLOC -# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname } -#else -# define __RWSEM_DEP_MAP_INIT(lockname) -#endif - - -#define __RWSEM_INITIALIZER(name) \ -{ \ - RWSEM_UNLOCKED_VALUE, __SPIN_LOCK_UNLOCKED((name).wait_lock), \ - LIST_HEAD_INIT((name).wait_list) __RWSEM_DEP_MAP_INIT(name) \ -} - -#define DECLARE_RWSEM(name) \ - struct rw_semaphore name = __RWSEM_INITIALIZER(name) - -extern void __init_rwsem(struct rw_semaphore *sem, const char *name, - struct lock_class_key *key); - -#define init_rwsem(sem) \ -do { \ - static struct lock_class_key __key; \ - \ - __init_rwsem((sem), #sem, &__key); \ -} while (0) - /* * lock for reading */ @@ -133,7 +79,7 @@ static inline void __down_read(struct rw_semaphore *sem) */ static inline int __down_read_trylock(struct rw_semaphore *sem) { - rwsem_count_t result, tmp; + long result, tmp; asm volatile("# beginning __down_read_trylock\n\t" " mov %0,%1\n\t" "1:\n\t" @@ -155,7 +101,7 @@ static inline int __down_read_trylock(struct rw_semaphore *sem) */ static inline void __down_write_nested(struct rw_semaphore *sem, int subclass) { - rwsem_count_t tmp; + long tmp; asm volatile("# beginning down_write\n\t" LOCK_PREFIX " xadd %1,(%2)\n\t" /* adds 0xffff0001, returns the old value */ @@ -180,9 +126,8 @@ static inline void __down_write(struct rw_semaphore *sem) */ static inline int __down_write_trylock(struct rw_semaphore *sem) { - rwsem_count_t ret = cmpxchg(&sem->count, - RWSEM_UNLOCKED_VALUE, - RWSEM_ACTIVE_WRITE_BIAS); + long ret = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE, + RWSEM_ACTIVE_WRITE_BIAS); if (ret == RWSEM_UNLOCKED_VALUE) return 1; return 0; @@ -193,7 +138,7 @@ static inline int __down_write_trylock(struct rw_semaphore *sem) */ static inline void __up_read(struct rw_semaphore *sem) { - rwsem_count_t tmp; + long tmp; asm volatile("# beginning __up_read\n\t" LOCK_PREFIX " xadd %1,(%2)\n\t" /* subtracts 1, returns the old value */ @@ -211,7 +156,7 @@ static inline void __up_read(struct rw_semaphore *sem) */ static inline void __up_write(struct rw_semaphore *sem) { - rwsem_count_t tmp; + long tmp; asm volatile("# beginning __up_write\n\t" LOCK_PREFIX " xadd %1,(%2)\n\t" /* subtracts 0xffff0001, returns the old value */ @@ -247,8 +192,7 @@ static inline void __downgrade_write(struct rw_semaphore *sem) /* * implement atomic add functionality */ -static inline void rwsem_atomic_add(rwsem_count_t delta, - struct rw_semaphore *sem) +static inline void rwsem_atomic_add(long delta, struct rw_semaphore *sem) { asm volatile(LOCK_PREFIX _ASM_ADD "%1,%0" : "+m" (sem->count) @@ -258,10 +202,9 @@ static inline void rwsem_atomic_add(rwsem_count_t delta, /* * implement exchange and add functionality */ -static inline rwsem_count_t rwsem_atomic_update(rwsem_count_t delta, - struct rw_semaphore *sem) +static inline long rwsem_atomic_update(long delta, struct rw_semaphore *sem) { - rwsem_count_t tmp = delta; + long tmp = delta; asm volatile(LOCK_PREFIX "xadd %0,%1" : "+r" (tmp), "+m" (sem->count) @@ -270,10 +213,5 @@ static inline rwsem_count_t rwsem_atomic_update(rwsem_count_t delta, return tmp + delta; } -static inline int rwsem_is_locked(struct rw_semaphore *sem) -{ - return (sem->count != 0); -} - #endif /* __KERNEL__ */ #endif /* _ASM_X86_RWSEM_H */ diff --git a/arch/x86/include/asm/segment.h b/arch/x86/include/asm/segment.h index 231f1c1d6607..cd84f7208f76 100644 --- a/arch/x86/include/asm/segment.h +++ b/arch/x86/include/asm/segment.h @@ -1,14 +1,16 @@ #ifndef _ASM_X86_SEGMENT_H #define _ASM_X86_SEGMENT_H +#include <linux/const.h> + /* Constructor for a conventional segment GDT (or LDT) entry */ /* This is a macro so it can be used in initializers */ #define GDT_ENTRY(flags, base, limit) \ - ((((base) & 0xff000000ULL) << (56-24)) | \ - (((flags) & 0x0000f0ffULL) << 40) | \ - (((limit) & 0x000f0000ULL) << (48-16)) | \ - (((base) & 0x00ffffffULL) << 16) | \ - (((limit) & 0x0000ffffULL))) + ((((base) & _AC(0xff000000,ULL)) << (56-24)) | \ + (((flags) & _AC(0x0000f0ff,ULL)) << 40) | \ + (((limit) & _AC(0x000f0000,ULL)) << (48-16)) | \ + (((base) & _AC(0x00ffffff,ULL)) << 16) | \ + (((limit) & _AC(0x0000ffff,ULL)))) /* Simple and small GDT entries for booting only */ diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h index 1f4695136776..73b11bc0ae6f 100644 --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -17,12 +17,24 @@ #endif #include <asm/thread_info.h> #include <asm/cpumask.h> +#include <asm/cpufeature.h> extern int smp_num_siblings; extern unsigned int num_processors; +static inline bool cpu_has_ht_siblings(void) +{ + bool has_siblings = false; +#ifdef CONFIG_SMP + has_siblings = cpu_has_ht && smp_num_siblings > 1; +#endif + return has_siblings; +} + DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_map); DECLARE_PER_CPU(cpumask_var_t, cpu_core_map); +/* cpus sharing the last level cache: */ +DECLARE_PER_CPU(cpumask_var_t, cpu_llc_shared_map); DECLARE_PER_CPU(u16, cpu_llc_id); DECLARE_PER_CPU(int, cpu_number); @@ -36,8 +48,16 @@ static inline struct cpumask *cpu_core_mask(int cpu) return per_cpu(cpu_core_map, cpu); } +static inline struct cpumask *cpu_llc_shared_mask(int cpu) +{ + return per_cpu(cpu_llc_shared_map, cpu); +} + DECLARE_EARLY_PER_CPU(u16, x86_cpu_to_apicid); DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid); +#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) +DECLARE_EARLY_PER_CPU(int, x86_cpu_to_logical_apicid); +#endif /* Static state in head.S used to set up a CPU */ extern unsigned long stack_start; /* Initial stack pointer address */ diff --git a/arch/x86/include/asm/system.h b/arch/x86/include/asm/system.h index 33ecc3ea8782..12569e691ce3 100644 --- a/arch/x86/include/asm/system.h +++ b/arch/x86/include/asm/system.h @@ -98,8 +98,6 @@ do { \ */ #define HAVE_DISABLE_HLT #else -#define __SAVE(reg, offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t" -#define __RESTORE(reg, offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t" /* frame pointer must be last for get_wchan */ #define SAVE_CONTEXT "pushf ; pushq %%rbp ; movq %%rsi,%%rbp\n\t" diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h index 21899cc31e52..910a7084f7f2 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -47,21 +47,6 @@ #include <asm/mpspec.h> -#ifdef CONFIG_X86_32 - -/* Mappings between logical cpu number and node number */ -extern int cpu_to_node_map[]; - -/* Returns the number of the node containing CPU 'cpu' */ -static inline int __cpu_to_node(int cpu) -{ - return cpu_to_node_map[cpu]; -} -#define early_cpu_to_node __cpu_to_node -#define cpu_to_node __cpu_to_node - -#else /* CONFIG_X86_64 */ - /* Mappings between logical cpu number and node number */ DECLARE_EARLY_PER_CPU(int, x86_cpu_to_node_map); @@ -84,8 +69,6 @@ static inline int early_cpu_to_node(int cpu) #endif /* !CONFIG_DEBUG_PER_CPU_MAPS */ -#endif /* CONFIG_X86_64 */ - /* Mappings between node number and cpus on that node. */ extern cpumask_var_t node_to_cpumask_map[MAX_NUMNODES]; @@ -155,7 +138,7 @@ extern unsigned long node_remap_size[]; .balance_interval = 1, \ } -#ifdef CONFIG_X86_64_ACPI_NUMA +#ifdef CONFIG_X86_64 extern int __node_distance(int, int); #define node_distance(a, b) __node_distance(a, b) #endif diff --git a/arch/x86/include/asm/trampoline.h b/arch/x86/include/asm/trampoline.h index f4500fb3b485..feca3118a73b 100644 --- a/arch/x86/include/asm/trampoline.h +++ b/arch/x86/include/asm/trampoline.h @@ -3,25 +3,36 @@ #ifndef __ASSEMBLY__ -#ifdef CONFIG_X86_TRAMPOLINE +#include <linux/types.h> +#include <asm/io.h> + /* - * Trampoline 80x86 program as an array. + * Trampoline 80x86 program as an array. These are in the init rodata + * segment, but that's okay, because we only care about the relative + * addresses of the symbols. */ -extern const unsigned char trampoline_data []; -extern const unsigned char trampoline_end []; -extern unsigned char *trampoline_base; +extern const unsigned char x86_trampoline_start []; +extern const unsigned char x86_trampoline_end []; +extern unsigned char *x86_trampoline_base; extern unsigned long init_rsp; extern unsigned long initial_code; extern unsigned long initial_gs; -#define TRAMPOLINE_SIZE roundup(trampoline_end - trampoline_data, PAGE_SIZE) +extern void __init setup_trampolines(void); + +extern const unsigned char trampoline_data[]; +extern const unsigned char trampoline_status[]; + +#define TRAMPOLINE_SYM(x) \ + ((void *)(x86_trampoline_base + \ + ((const unsigned char *)(x) - x86_trampoline_start))) -extern unsigned long setup_trampoline(void); -extern void __init reserve_trampoline_memory(void); -#else -static inline void reserve_trampoline_memory(void) {} -#endif /* CONFIG_X86_TRAMPOLINE */ +/* Address of the SMP trampoline */ +static inline unsigned long trampoline_address(void) +{ + return virt_to_phys(TRAMPOLINE_SYM(trampoline_data)); +} #endif /* __ASSEMBLY__ */ diff --git a/arch/x86/include/asm/unistd_32.h b/arch/x86/include/asm/unistd_32.h index b766a5e8ba0e..ffaf183c619a 100644 --- a/arch/x86/include/asm/unistd_32.h +++ b/arch/x86/include/asm/unistd_32.h @@ -346,10 +346,13 @@ #define __NR_fanotify_init 338 #define __NR_fanotify_mark 339 #define __NR_prlimit64 340 +#define __NR_name_to_handle_at 341 +#define __NR_open_by_handle_at 342 +#define __NR_clock_adjtime 343 #ifdef __KERNEL__ -#define NR_syscalls 341 +#define NR_syscalls 344 #define __ARCH_WANT_IPC_PARSE_VERSION #define __ARCH_WANT_OLD_READDIR diff --git a/arch/x86/include/asm/unistd_64.h b/arch/x86/include/asm/unistd_64.h index 363e9b8a715b..5466bea670e7 100644 --- a/arch/x86/include/asm/unistd_64.h +++ b/arch/x86/include/asm/unistd_64.h @@ -669,6 +669,12 @@ __SYSCALL(__NR_fanotify_init, sys_fanotify_init) __SYSCALL(__NR_fanotify_mark, sys_fanotify_mark) #define __NR_prlimit64 302 __SYSCALL(__NR_prlimit64, sys_prlimit64) +#define __NR_name_to_handle_at 303 +__SYSCALL(__NR_name_to_handle_at, sys_name_to_handle_at) +#define __NR_open_by_handle_at 304 +__SYSCALL(__NR_open_by_handle_at, sys_open_by_handle_at) +#define __NR_clock_adjtime 305 +__SYSCALL(__NR_clock_adjtime, sys_clock_adjtime) #ifndef __NO_STUBS #define __ARCH_WANT_OLD_READDIR diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h index 64642ad019fb..643ebf2e2ad8 100644 --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h @@ -83,11 +83,13 @@ struct x86_init_paging { * boot cpu * @tsc_pre_init: platform function called before TSC init * @timer_init: initialize the platform timer (default PIT/HPET) + * @wallclock_init: init the wallclock device */ struct x86_init_timers { void (*setup_percpu_clockev)(void); void (*tsc_pre_init)(void); void (*timer_init)(void); + void (*wallclock_init)(void); }; /** diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index 34244b2cd880..743642f1a36c 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -47,7 +47,7 @@ obj-y += tsc.o io_delay.o rtc.o obj-y += pci-iommu_table.o obj-y += resource.o -obj-$(CONFIG_X86_TRAMPOLINE) += trampoline.o +obj-y += trampoline.o trampoline_$(BITS).o obj-y += process.o obj-y += i387.o xsave.o obj-y += ptrace.o @@ -59,6 +59,7 @@ obj-$(CONFIG_STACKTRACE) += stacktrace.o obj-y += cpu/ obj-y += acpi/ obj-y += reboot.o +obj-$(CONFIG_X86_32) += reboot_32.o obj-$(CONFIG_MCA) += mca_32.o obj-$(CONFIG_X86_MSR) += msr.o obj-$(CONFIG_X86_CPUID) += cpuid.o @@ -66,10 +67,9 @@ obj-$(CONFIG_PCI) += early-quirks.o apm-y := apm_32.o obj-$(CONFIG_APM) += apm.o obj-$(CONFIG_SMP) += smp.o -obj-$(CONFIG_SMP) += smpboot.o tsc_sync.o +obj-$(CONFIG_SMP) += smpboot.o +obj-$(CONFIG_SMP) += tsc_sync.o obj-$(CONFIG_SMP) += setup_percpu.o -obj-$(CONFIG_X86_64_SMP) += tsc_sync.o -obj-$(CONFIG_X86_TRAMPOLINE) += trampoline_$(BITS).o obj-$(CONFIG_X86_MPPARSE) += mpparse.o obj-y += apic/ obj-$(CONFIG_X86_REBOOTFIXUPS) += reboot_fixups_32.o @@ -109,6 +109,7 @@ obj-$(CONFIG_MICROCODE) += microcode.o obj-$(CONFIG_X86_CHECK_BIOS_CORRUPTION) += check.o obj-$(CONFIG_SWIOTLB) += pci-swiotlb.o +obj-$(CONFIG_OF) += devicetree.o ### # 64 bit specific files diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c index 3e6e2d68f761..9a966c579af5 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -595,14 +595,8 @@ static void acpi_map_cpu2node(acpi_handle handle, int cpu, int physid) nid = acpi_get_node(handle); if (nid == -1 || !node_online(nid)) return; -#ifdef CONFIG_X86_64 - apicid_to_node[physid] = nid; + set_apicid_to_node(physid, nid); numa_set_node(cpu, nid); -#else /* CONFIG_X86_32 */ - apicid_2_node[physid] = nid; - cpu_to_node_map[cpu] = nid; -#endif - #endif } diff --git a/arch/x86/kernel/acpi/realmode/wakeup.S b/arch/x86/kernel/acpi/realmode/wakeup.S index 28595d6df47c..ead21b663117 100644 --- a/arch/x86/kernel/acpi/realmode/wakeup.S +++ b/arch/x86/kernel/acpi/realmode/wakeup.S @@ -6,11 +6,17 @@ #include <asm/page_types.h> #include <asm/pgtable_types.h> #include <asm/processor-flags.h> +#include "wakeup.h" .code16 - .section ".header", "a" + .section ".jump", "ax" + .globl _start +_start: + cli + jmp wakeup_code /* This should match the structure in wakeup.h */ + .section ".header", "a" .globl wakeup_header wakeup_header: video_mode: .short 0 /* Video mode number */ @@ -30,14 +36,11 @@ wakeup_jmp: .byte 0xea /* ljmpw */ wakeup_jmp_off: .word 3f wakeup_jmp_seg: .word 0 wakeup_gdt: .quad 0, 0, 0 -signature: .long 0x51ee1111 +signature: .long WAKEUP_HEADER_SIGNATURE .text - .globl _start .code16 wakeup_code: -_start: - cli cld /* Apparently some dimwit BIOS programmers don't know how to @@ -77,12 +80,12 @@ _start: /* Check header signature... */ movl signature, %eax - cmpl $0x51ee1111, %eax + cmpl $WAKEUP_HEADER_SIGNATURE, %eax jne bogus_real_magic /* Check we really have everything... */ movl end_signature, %eax - cmpl $0x65a22c82, %eax + cmpl $WAKEUP_END_SIGNATURE, %eax jne bogus_real_magic /* Call the C code */ @@ -147,3 +150,7 @@ wakeup_heap: wakeup_stack: .space 2048 wakeup_stack_end: + + .section ".signature","a" +end_signature: + .long WAKEUP_END_SIGNATURE diff --git a/arch/x86/kernel/acpi/realmode/wakeup.h b/arch/x86/kernel/acpi/realmode/wakeup.h index 69d38d0b2b64..e1828c07e79c 100644 --- a/arch/x86/kernel/acpi/realmode/wakeup.h +++ b/arch/x86/kernel/acpi/realmode/wakeup.h @@ -35,7 +35,8 @@ struct wakeup_header { extern struct wakeup_header wakeup_header; #endif -#define HEADER_OFFSET 0x3f00 -#define WAKEUP_SIZE 0x4000 +#define WAKEUP_HEADER_OFFSET 8 +#define WAKEUP_HEADER_SIGNATURE 0x51ee1111 +#define WAKEUP_END_SIGNATURE 0x65a22c82 #endif /* ARCH_X86_KERNEL_ACPI_RM_WAKEUP_H */ diff --git a/arch/x86/kernel/acpi/realmode/wakeup.lds.S b/arch/x86/kernel/acpi/realmode/wakeup.lds.S index 060fff8f5c5b..d4f8010a5b1b 100644 --- a/arch/x86/kernel/acpi/realmode/wakeup.lds.S +++ b/arch/x86/kernel/acpi/realmode/wakeup.lds.S @@ -13,9 +13,19 @@ ENTRY(_start) SECTIONS { . = 0; + .jump : { + *(.jump) + } = 0x90909090 + + . = WAKEUP_HEADER_OFFSET; + .header : { + *(.header) + } + + . = ALIGN(16); .text : { *(.text*) - } + } = 0x90909090 . = ALIGN(16); .rodata : { @@ -33,11 +43,6 @@ SECTIONS *(.data*) } - .signature : { - end_signature = .; - LONG(0x65a22c82) - } - . = ALIGN(16); .bss : { __bss_start = .; @@ -45,20 +50,13 @@ SECTIONS __bss_end = .; } - . = HEADER_OFFSET; - .header : { - *(.header) + .signature : { + *(.signature) } - . = ALIGN(16); _end = .; /DISCARD/ : { *(.note*) } - - /* - * The ASSERT() sink to . is intentional, for binutils 2.14 compatibility: - */ - . = ASSERT(_end <= WAKEUP_SIZE, "Wakeup too big!"); } diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c index 68d1537b8c81..4572c58e66d5 100644 --- a/arch/x86/kernel/acpi/sleep.c +++ b/arch/x86/kernel/acpi/sleep.c @@ -18,12 +18,8 @@ #include "realmode/wakeup.h" #include "sleep.h" -unsigned long acpi_wakeup_address; unsigned long acpi_realmode_flags; -/* address in low memory of the wakeup routine. */ -static unsigned long acpi_realmode; - #if defined(CONFIG_SMP) && defined(CONFIG_64BIT) static char temp_stack[4096]; #endif @@ -33,22 +29,17 @@ static char temp_stack[4096]; * * Create an identity mapped page table and copy the wakeup routine to * low memory. - * - * Note that this is too late to change acpi_wakeup_address. */ int acpi_save_state_mem(void) { struct wakeup_header *header; + /* address in low memory of the wakeup routine. */ + char *acpi_realmode; - if (!acpi_realmode) { - printk(KERN_ERR "Could not allocate memory during boot, " - "S3 disabled\n"); - return -ENOMEM; - } - memcpy((void *)acpi_realmode, &wakeup_code_start, WAKEUP_SIZE); + acpi_realmode = TRAMPOLINE_SYM(acpi_wakeup_code); - header = (struct wakeup_header *)(acpi_realmode + HEADER_OFFSET); - if (header->signature != 0x51ee1111) { + header = (struct wakeup_header *)(acpi_realmode + WAKEUP_HEADER_OFFSET); + if (header->signature != WAKEUP_HEADER_SIGNATURE) { printk(KERN_ERR "wakeup header does not match\n"); return -EINVAL; } @@ -68,9 +59,7 @@ int acpi_save_state_mem(void) /* GDT[0]: GDT self-pointer */ header->wakeup_gdt[0] = (u64)(sizeof(header->wakeup_gdt) - 1) + - ((u64)(acpi_wakeup_address + - ((char *)&header->wakeup_gdt - (char *)acpi_realmode)) - << 16); + ((u64)__pa(&header->wakeup_gdt) << 16); /* GDT[1]: big real mode-like code segment */ header->wakeup_gdt[1] = GDT_ENTRY(0x809b, acpi_wakeup_address, 0xfffff); @@ -96,7 +85,7 @@ int acpi_save_state_mem(void) header->pmode_cr3 = (u32)__pa(&initial_page_table); saved_magic = 0x12345678; #else /* CONFIG_64BIT */ - header->trampoline_segment = setup_trampoline() >> 4; + header->trampoline_segment = trampoline_address() >> 4; #ifdef CONFIG_SMP stack_start = (unsigned long)temp_stack + sizeof(temp_stack); early_gdt_descr.address = @@ -117,46 +106,6 @@ void acpi_restore_state_mem(void) { } - -/** - * acpi_reserve_wakeup_memory - do _very_ early ACPI initialisation - * - * We allocate a page from the first 1MB of memory for the wakeup - * routine for when we come back from a sleep state. The - * runtime allocator allows specification of <16MB pages, but not - * <1MB pages. - */ -void __init acpi_reserve_wakeup_memory(void) -{ - phys_addr_t mem; - - if ((&wakeup_code_end - &wakeup_code_start) > WAKEUP_SIZE) { - printk(KERN_ERR - "ACPI: Wakeup code way too big, S3 disabled.\n"); - return; - } - - mem = memblock_find_in_range(0, 1<<20, WAKEUP_SIZE, PAGE_SIZE); - - if (mem == MEMBLOCK_ERROR) { - printk(KERN_ERR "ACPI: Cannot allocate lowmem, S3 disabled.\n"); - return; - } - acpi_realmode = (unsigned long) phys_to_virt(mem); - acpi_wakeup_address = mem; - memblock_x86_reserve_range(mem, mem + WAKEUP_SIZE, "ACPI WAKEUP"); -} - -int __init acpi_configure_wakeup_memory(void) -{ - if (acpi_realmode) - set_memory_x(acpi_realmode, WAKEUP_SIZE >> PAGE_SHIFT); - - return 0; -} -arch_initcall(acpi_configure_wakeup_memory); - - static int __init acpi_sleep_setup(char *str) { while ((str != NULL) && (*str != '\0')) { diff --git a/arch/x86/kernel/acpi/sleep.h b/arch/x86/kernel/acpi/sleep.h index adbcbaa6f1df..86ba1c87165b 100644 --- a/arch/x86/kernel/acpi/sleep.h +++ b/arch/x86/kernel/acpi/sleep.h @@ -4,13 +4,10 @@ #include <asm/trampoline.h> -extern char wakeup_code_start, wakeup_code_end; - extern unsigned long saved_video_mode; extern long saved_magic; extern int wakeup_pmode_return; -extern char swsusp_pg_dir[PAGE_SIZE]; extern unsigned long acpi_copy_wakeup_routine(unsigned long); extern void wakeup_long64(void); diff --git a/arch/x86/kernel/acpi/wakeup_rm.S b/arch/x86/kernel/acpi/wakeup_rm.S index 6ff3b5730575..63b8ab524f2c 100644 --- a/arch/x86/kernel/acpi/wakeup_rm.S +++ b/arch/x86/kernel/acpi/wakeup_rm.S @@ -2,9 +2,11 @@ * Wrapper script for the realmode binary as a transport object * before copying to low memory. */ - .section ".rodata","a" - .globl wakeup_code_start, wakeup_code_end -wakeup_code_start: +#include <asm/page_types.h> + + .section ".x86_trampoline","a" + .balign PAGE_SIZE + .globl acpi_wakeup_code +acpi_wakeup_code: .incbin "arch/x86/kernel/acpi/realmode/wakeup.bin" -wakeup_code_end: - .size wakeup_code_start, .-wakeup_code_start + .size acpi_wakeup_code, .-acpi_wakeup_code diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c index 7038b95d363f..4db35544de73 100644 --- a/arch/x86/kernel/alternative.c +++ b/arch/x86/kernel/alternative.c @@ -620,7 +620,12 @@ static int __kprobes stop_machine_text_poke(void *data) flush_icache_range((unsigned long)p->addr, (unsigned long)p->addr + p->len); } - + /* + * Intel Archiecture Software Developer's Manual section 7.1.3 specifies + * that a core serializing instruction such as "cpuid" should be + * executed on _each_ core before the new instruction is made visible. + */ + sync_core(); return 0; } diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index 0a99f7198bc3..6801959a8b2a 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -12,14 +12,19 @@ static u32 *flush_words; -struct pci_device_id amd_nb_misc_ids[] = { +const struct pci_device_id amd_nb_misc_ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) }, - { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_MISC) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) }, {} }; EXPORT_SYMBOL(amd_nb_misc_ids); +static struct pci_device_id amd_nb_link_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_LINK) }, + {} +}; + const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = { { 0x00, 0x18, 0x20 }, { 0xff, 0x00, 0x20 }, @@ -31,7 +36,7 @@ struct amd_northbridge_info amd_northbridges; EXPORT_SYMBOL(amd_northbridges); static struct pci_dev *next_northbridge(struct pci_dev *dev, - struct pci_device_id *ids) + const struct pci_device_id *ids) { do { dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev); @@ -43,9 +48,9 @@ static struct pci_dev *next_northbridge(struct pci_dev *dev, int amd_cache_northbridges(void) { - int i = 0; + u16 i = 0; struct amd_northbridge *nb; - struct pci_dev *misc; + struct pci_dev *misc, *link; if (amd_nb_num()) return 0; @@ -64,10 +69,12 @@ int amd_cache_northbridges(void) amd_northbridges.nb = nb; amd_northbridges.num = i; - misc = NULL; + link = misc = NULL; for (i = 0; i != amd_nb_num(); i++) { node_to_amd_nb(i)->misc = misc = next_northbridge(misc, amd_nb_misc_ids); + node_to_amd_nb(i)->link = link = + next_northbridge(link, amd_nb_link_ids); } /* some CPU families (e.g. family 0x11) do not support GART */ @@ -85,26 +92,95 @@ int amd_cache_northbridges(void) boot_cpu_data.x86_mask >= 0x1)) amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE; + if (boot_cpu_data.x86 == 0x15) + amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE; + + /* L3 cache partitioning is supported on family 0x15 */ + if (boot_cpu_data.x86 == 0x15) + amd_northbridges.flags |= AMD_NB_L3_PARTITIONING; + return 0; } EXPORT_SYMBOL_GPL(amd_cache_northbridges); -/* Ignores subdevice/subvendor but as far as I can figure out - they're useless anyways */ -int __init early_is_amd_nb(u32 device) +/* + * Ignores subdevice/subvendor but as far as I can figure out + * they're useless anyways + */ +bool __init early_is_amd_nb(u32 device) { - struct pci_device_id *id; + const struct pci_device_id *id; u32 vendor = device & 0xffff; + device >>= 16; for (id = amd_nb_misc_ids; id->vendor; id++) if (vendor == id->vendor && device == id->device) - return 1; + return true; + return false; +} + +int amd_get_subcaches(int cpu) +{ + struct pci_dev *link = node_to_amd_nb(amd_get_nb_id(cpu))->link; + unsigned int mask; + int cuid = 0; + + if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) + return 0; + + pci_read_config_dword(link, 0x1d4, &mask); + +#ifdef CONFIG_SMP + cuid = cpu_data(cpu).compute_unit_id; +#endif + return (mask >> (4 * cuid)) & 0xf; +} + +int amd_set_subcaches(int cpu, int mask) +{ + static unsigned int reset, ban; + struct amd_northbridge *nb = node_to_amd_nb(amd_get_nb_id(cpu)); + unsigned int reg; + int cuid = 0; + + if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf) + return -EINVAL; + + /* if necessary, collect reset state of L3 partitioning and BAN mode */ + if (reset == 0) { + pci_read_config_dword(nb->link, 0x1d4, &reset); + pci_read_config_dword(nb->misc, 0x1b8, &ban); + ban &= 0x180000; + } + + /* deactivate BAN mode if any subcaches are to be disabled */ + if (mask != 0xf) { + pci_read_config_dword(nb->misc, 0x1b8, ®); + pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000); + } + +#ifdef CONFIG_SMP + cuid = cpu_data(cpu).compute_unit_id; +#endif + mask <<= 4 * cuid; + mask |= (0xf ^ (1 << cuid)) << 26; + + pci_write_config_dword(nb->link, 0x1d4, mask); + + /* reset BAN mode if L3 partitioning returned to reset state */ + pci_read_config_dword(nb->link, 0x1d4, ®); + if (reg == reset) { + pci_read_config_dword(nb->misc, 0x1b8, ®); + reg &= ~0x180000; + pci_write_config_dword(nb->misc, 0x1b8, reg | ban); + } + return 0; } -int amd_cache_gart(void) +static int amd_cache_gart(void) { - int i; + u16 i; if (!amd_nb_has_feature(AMD_NB_GART)) return 0; diff --git a/arch/x86/kernel/apb_timer.c b/arch/x86/kernel/apb_timer.c index 51d4e1663066..1293c709ee85 100644 --- a/arch/x86/kernel/apb_timer.c +++ b/arch/x86/kernel/apb_timer.c @@ -508,64 +508,12 @@ static int apbt_next_event(unsigned long delta, return 0; } -/* - * APB timer clock is not in sync with pclk on Langwell, which translates to - * unreliable read value caused by sampling error. the error does not add up - * overtime and only happens when sampling a 0 as a 1 by mistake. so the time - * would go backwards. the following code is trying to prevent time traveling - * backwards. little bit paranoid. - */ static cycle_t apbt_read_clocksource(struct clocksource *cs) { - unsigned long t0, t1, t2; - static unsigned long last_read; - -bad_count: - t1 = apbt_readl(phy_cs_timer_id, - APBTMR_N_CURRENT_VALUE); - t2 = apbt_readl(phy_cs_timer_id, - APBTMR_N_CURRENT_VALUE); - if (unlikely(t1 < t2)) { - pr_debug("APBT: read current count error %lx:%lx:%lx\n", - t1, t2, t2 - t1); - goto bad_count; - } - /* - * check against cached last read, makes sure time does not go back. - * it could be a normal rollover but we will do tripple check anyway - */ - if (unlikely(t2 > last_read)) { - /* check if we have a normal rollover */ - unsigned long raw_intr_status = - apbt_readl_reg(APBTMRS_RAW_INT_STATUS); - /* - * cs timer interrupt is masked but raw intr bit is set if - * rollover occurs. then we read EOI reg to clear it. - */ - if (raw_intr_status & (1 << phy_cs_timer_id)) { - apbt_readl(phy_cs_timer_id, APBTMR_N_EOI); - goto out; - } - pr_debug("APB CS going back %lx:%lx:%lx ", - t2, last_read, t2 - last_read); -bad_count_x3: - pr_debug("triple check enforced\n"); - t0 = apbt_readl(phy_cs_timer_id, - APBTMR_N_CURRENT_VALUE); - udelay(1); - t1 = apbt_readl(phy_cs_timer_id, - APBTMR_N_CURRENT_VALUE); - udelay(1); - t2 = apbt_readl(phy_cs_timer_id, - APBTMR_N_CURRENT_VALUE); - if ((t2 > t1) || (t1 > t0)) { - printk(KERN_ERR "Error: APB CS tripple check failed\n"); - goto bad_count_x3; - } - } -out: - last_read = t2; - return (cycle_t)~t2; + unsigned long current_count; + + current_count = apbt_readl(phy_cs_timer_id, APBTMR_N_CURRENT_VALUE); + return (cycle_t)~current_count; } static int apbt_clocksource_register(void) diff --git a/arch/x86/kernel/aperture_64.c b/arch/x86/kernel/aperture_64.c index 5955a7800a96..7b1e8e10b89c 100644 --- a/arch/x86/kernel/aperture_64.c +++ b/arch/x86/kernel/aperture_64.c @@ -13,7 +13,7 @@ #include <linux/kernel.h> #include <linux/types.h> #include <linux/init.h> -#include <linux/bootmem.h> +#include <linux/memblock.h> #include <linux/mmzone.h> #include <linux/pci_ids.h> #include <linux/pci.h> @@ -57,7 +57,7 @@ static void __init insert_aperture_resource(u32 aper_base, u32 aper_size) static u32 __init allocate_aperture(void) { u32 aper_size; - void *p; + unsigned long addr; /* aper_size should <= 1G */ if (fallback_aper_order > 5) @@ -83,27 +83,26 @@ static u32 __init allocate_aperture(void) * so don't use 512M below as gart iommu, leave the space for kernel * code for safe */ - p = __alloc_bootmem_nopanic(aper_size, aper_size, 512ULL<<20); + addr = memblock_find_in_range(0, 1ULL<<32, aper_size, 512ULL<<20); + if (addr == MEMBLOCK_ERROR || addr + aper_size > 0xffffffff) { + printk(KERN_ERR + "Cannot allocate aperture memory hole (%lx,%uK)\n", + addr, aper_size>>10); + return 0; + } + memblock_x86_reserve_range(addr, addr + aper_size, "aperture64"); /* * Kmemleak should not scan this block as it may not be mapped via the * kernel direct mapping. */ - kmemleak_ignore(p); - if (!p || __pa(p)+aper_size > 0xffffffff) { - printk(KERN_ERR - "Cannot allocate aperture memory hole (%p,%uK)\n", - p, aper_size>>10); - if (p) - free_bootmem(__pa(p), aper_size); - return 0; - } + kmemleak_ignore(phys_to_virt(addr)); printk(KERN_INFO "Mapping aperture over %d KB of RAM @ %lx\n", - aper_size >> 10, __pa(p)); - insert_aperture_resource((u32)__pa(p), aper_size); - register_nosave_region((u32)__pa(p) >> PAGE_SHIFT, - (u32)__pa(p+aper_size) >> PAGE_SHIFT); + aper_size >> 10, addr); + insert_aperture_resource((u32)addr, aper_size); + register_nosave_region(addr >> PAGE_SHIFT, + (addr+aper_size) >> PAGE_SHIFT); - return (u32)__pa(p); + return (u32)addr; } diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 76b96d74978a..966673f44141 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -43,6 +43,7 @@ #include <asm/i8259.h> #include <asm/proto.h> #include <asm/apic.h> +#include <asm/io_apic.h> #include <asm/desc.h> #include <asm/hpet.h> #include <asm/idle.h> @@ -78,12 +79,21 @@ EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); #ifdef CONFIG_X86_32 + +/* + * On x86_32, the mapping between cpu and logical apicid may vary + * depending on apic in use. The following early percpu variable is + * used for the mapping. This is where the behaviors of x86_64 and 32 + * actually diverge. Let's keep it ugly for now. + */ +DEFINE_EARLY_PER_CPU(int, x86_cpu_to_logical_apicid, BAD_APICID); + /* * Knob to control our willingness to enable the local APIC. * * +1=force-enable */ -static int force_enable_local_apic; +static int force_enable_local_apic __initdata; /* * APIC command line parameters */ @@ -153,7 +163,7 @@ early_param("nox2apic", setup_nox2apic); unsigned long mp_lapic_addr; int disable_apic; /* Disable local APIC timer from the kernel commandline or via dmi quirk */ -static int disable_apic_timer __cpuinitdata; +static int disable_apic_timer __initdata; /* Local APIC timer works in C2 */ int local_apic_timer_c2_ok; EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); @@ -177,29 +187,8 @@ static struct resource lapic_resource = { static unsigned int calibration_result; -static int lapic_next_event(unsigned long delta, - struct clock_event_device *evt); -static void lapic_timer_setup(enum clock_event_mode mode, - struct clock_event_device *evt); -static void lapic_timer_broadcast(const struct cpumask *mask); static void apic_pm_activate(void); -/* - * The local apic timer can be used for any function which is CPU local. - */ -static struct clock_event_device lapic_clockevent = { - .name = "lapic", - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT - | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, - .shift = 32, - .set_mode = lapic_timer_setup, - .set_next_event = lapic_next_event, - .broadcast = lapic_timer_broadcast, - .rating = 100, - .irq = -1, -}; -static DEFINE_PER_CPU(struct clock_event_device, lapic_events); - static unsigned long apic_phys; /* @@ -238,7 +227,7 @@ static int modern_apic(void) * right after this call apic become NOOP driven * so apic->write/read doesn't do anything */ -void apic_disable(void) +static void __init apic_disable(void) { pr_info("APIC: switched to apic NOOP\n"); apic = &apic_noop; @@ -282,23 +271,6 @@ u64 native_apic_icr_read(void) return icr1 | ((u64)icr2 << 32); } -/** - * enable_NMI_through_LVT0 - enable NMI through local vector table 0 - */ -void __cpuinit enable_NMI_through_LVT0(void) -{ - unsigned int v; - - /* unmask and set to NMI */ - v = APIC_DM_NMI; - - /* Level triggered for 82489DX (32bit mode) */ - if (!lapic_is_integrated()) - v |= APIC_LVT_LEVEL_TRIGGER; - - apic_write(APIC_LVT0, v); -} - #ifdef CONFIG_X86_32 /** * get_physical_broadcast - Get number of physical broadcast IDs @@ -508,6 +480,23 @@ static void lapic_timer_broadcast(const struct cpumask *mask) #endif } + +/* + * The local apic timer can be used for any function which is CPU local. + */ +static struct clock_event_device lapic_clockevent = { + .name = "lapic", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT + | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, + .shift = 32, + .set_mode = lapic_timer_setup, + .set_next_event = lapic_next_event, + .broadcast = lapic_timer_broadcast, + .rating = 100, + .irq = -1, +}; +static DEFINE_PER_CPU(struct clock_event_device, lapic_events); + /* * Setup the local APIC timer for this CPU. Copy the initialized values * of the boot CPU and register the clock event in the framework. @@ -1209,7 +1198,7 @@ void __cpuinit setup_local_APIC(void) rdtscll(tsc); if (disable_apic) { - arch_disable_smp_support(); + disable_ioapic_support(); return; } @@ -1237,6 +1226,19 @@ void __cpuinit setup_local_APIC(void) */ apic->init_apic_ldr(); +#ifdef CONFIG_X86_32 + /* + * APIC LDR is initialized. If logical_apicid mapping was + * initialized during get_smp_config(), make sure it matches the + * actual value. + */ + i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); + WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); + /* always use the value from LDR */ + early_per_cpu(x86_cpu_to_logical_apicid, cpu) = + logical_smp_processor_id(); +#endif + /* * Set Task Priority to 'accept all'. We never change this * later on. @@ -1448,7 +1450,7 @@ int __init enable_IR(void) void __init enable_IR_x2apic(void) { unsigned long flags; - struct IO_APIC_route_entry **ioapic_entries = NULL; + struct IO_APIC_route_entry **ioapic_entries; int ret, x2apic_enabled = 0; int dmar_table_init_ret; @@ -1537,7 +1539,7 @@ static int __init detect_init_APIC(void) } #else -static int apic_verify(void) +static int __init apic_verify(void) { u32 features, h, l; @@ -1562,7 +1564,7 @@ static int apic_verify(void) return 0; } -int apic_force_enable(void) +int __init apic_force_enable(unsigned long addr) { u32 h, l; @@ -1578,7 +1580,7 @@ int apic_force_enable(void) if (!(l & MSR_IA32_APICBASE_ENABLE)) { pr_info("Local APIC disabled by BIOS -- reenabling.\n"); l &= ~MSR_IA32_APICBASE_BASE; - l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; + l |= MSR_IA32_APICBASE_ENABLE | addr; wrmsr(MSR_IA32_APICBASE, l, h); enabled_via_apicbase = 1; } @@ -1619,7 +1621,7 @@ static int __init detect_init_APIC(void) "you can enable it with \"lapic\"\n"); return -1; } - if (apic_force_enable()) + if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) return -1; } else { if (apic_verify()) @@ -1930,17 +1932,6 @@ void __cpuinit generic_processor_info(int apicid, int version) { int cpu; - /* - * Validate version - */ - if (version == 0x0) { - pr_warning("BIOS bug, APIC version is 0 for CPU#%d! " - "fixing up to 0x10. (tell your hw vendor)\n", - version); - version = 0x10; - } - apic_version[apicid] = version; - if (num_processors >= nr_cpu_ids) { int max = nr_cpu_ids; int thiscpu = max + disabled_cpus; @@ -1954,22 +1945,34 @@ void __cpuinit generic_processor_info(int apicid, int version) } num_processors++; - cpu = cpumask_next_zero(-1, cpu_present_mask); - - if (version != apic_version[boot_cpu_physical_apicid]) - WARN_ONCE(1, - "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n", - apic_version[boot_cpu_physical_apicid], cpu, version); - - physid_set(apicid, phys_cpu_present_map); if (apicid == boot_cpu_physical_apicid) { /* * x86_bios_cpu_apicid is required to have processors listed * in same order as logical cpu numbers. Hence the first * entry is BSP, and so on. + * boot_cpu_init() already hold bit 0 in cpu_present_mask + * for BSP. */ cpu = 0; + } else + cpu = cpumask_next_zero(-1, cpu_present_mask); + + /* + * Validate version + */ + if (version == 0x0) { + pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", + cpu, apicid); + version = 0x10; } + apic_version[apicid] = version; + + if (version != apic_version[boot_cpu_physical_apicid]) { + pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", + apic_version[boot_cpu_physical_apicid], cpu, version); + } + + physid_set(apicid, phys_cpu_present_map); if (apicid > max_physical_apicid) max_physical_apicid = apicid; @@ -1977,7 +1980,10 @@ void __cpuinit generic_processor_info(int apicid, int version) early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; #endif - +#ifdef CONFIG_X86_32 + early_per_cpu(x86_cpu_to_logical_apicid, cpu) = + apic->x86_32_early_logical_apicid(cpu); +#endif set_cpu_possible(cpu, true); set_cpu_present(cpu, true); } @@ -1998,10 +2004,14 @@ void default_init_apic_ldr(void) } #ifdef CONFIG_X86_32 -int default_apicid_to_node(int logical_apicid) +int default_x86_32_numa_cpu_node(int cpu) { -#ifdef CONFIG_SMP - return apicid_2_node[hard_smp_processor_id()]; +#ifdef CONFIG_NUMA + int apicid = early_per_cpu(x86_cpu_to_apicid, cpu); + + if (apicid != BAD_APICID) + return __apicid_to_node[apicid]; + return NUMA_NO_NODE; #else return 0; #endif diff --git a/arch/x86/kernel/apic/apic_flat_64.c b/arch/x86/kernel/apic/apic_flat_64.c index 09d3b17ce0c2..5652d31fe108 100644 --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -185,8 +185,6 @@ struct apic apic_flat = { .ioapic_phys_id_map = NULL, .setup_apic_routing = NULL, .multi_timer_check = NULL, - .apicid_to_node = NULL, - .cpu_to_logical_apicid = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .apicid_to_cpu_present = NULL, .setup_portio_remap = NULL, @@ -337,8 +335,6 @@ struct apic apic_physflat = { .ioapic_phys_id_map = NULL, .setup_apic_routing = NULL, .multi_timer_check = NULL, - .apicid_to_node = NULL, - .cpu_to_logical_apicid = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .apicid_to_cpu_present = NULL, .setup_portio_remap = NULL, diff --git a/arch/x86/kernel/apic/apic_noop.c b/arch/x86/kernel/apic/apic_noop.c index e31b9ffe25f5..f1baa2dc087a 100644 --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -54,11 +54,6 @@ static u64 noop_apic_icr_read(void) return 0; } -static int noop_cpu_to_logical_apicid(int cpu) -{ - return 0; -} - static int noop_phys_pkg_id(int cpuid_apic, int index_msb) { return 0; @@ -113,12 +108,6 @@ static void noop_vector_allocation_domain(int cpu, struct cpumask *retmask) cpumask_set_cpu(cpu, retmask); } -int noop_apicid_to_node(int logical_apicid) -{ - /* we're always on node 0 */ - return 0; -} - static u32 noop_apic_read(u32 reg) { WARN_ON_ONCE((cpu_has_apic && !disable_apic)); @@ -130,6 +119,14 @@ static void noop_apic_write(u32 reg, u32 v) WARN_ON_ONCE(cpu_has_apic && !disable_apic); } +#ifdef CONFIG_X86_32 +static int noop_x86_32_numa_cpu_node(int cpu) +{ + /* we're always on node 0 */ + return 0; +} +#endif + struct apic apic_noop = { .name = "noop", .probe = noop_probe, @@ -153,9 +150,7 @@ struct apic apic_noop = { .ioapic_phys_id_map = default_ioapic_phys_id_map, .setup_apic_routing = NULL, .multi_timer_check = NULL, - .apicid_to_node = noop_apicid_to_node, - .cpu_to_logical_apicid = noop_cpu_to_logical_apicid, .cpu_present_to_apicid = default_cpu_present_to_apicid, .apicid_to_cpu_present = physid_set_mask_of_physid, @@ -197,4 +192,9 @@ struct apic apic_noop = { .icr_write = noop_apic_icr_write, .wait_icr_idle = noop_apic_wait_icr_idle, .safe_wait_icr_idle = noop_safe_apic_wait_icr_idle, + +#ifdef CONFIG_X86_32 + .x86_32_early_logical_apicid = noop_x86_32_early_logical_apicid, + .x86_32_numa_cpu_node = noop_x86_32_numa_cpu_node, +#endif }; diff --git a/arch/x86/kernel/apic/bigsmp_32.c b/arch/x86/kernel/apic/bigsmp_32.c index cb804c5091b9..541a2e431659 100644 --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -45,6 +45,12 @@ static unsigned long bigsmp_check_apicid_present(int bit) return 1; } +static int bigsmp_early_logical_apicid(int cpu) +{ + /* on bigsmp, logical apicid is the same as physical */ + return early_per_cpu(x86_cpu_to_apicid, cpu); +} + static inline unsigned long calculate_ldr(int cpu) { unsigned long val, id; @@ -80,11 +86,6 @@ static void bigsmp_setup_apic_routing(void) nr_ioapics); } -static int bigsmp_apicid_to_node(int logical_apicid) -{ - return apicid_2_node[hard_smp_processor_id()]; -} - static int bigsmp_cpu_present_to_apicid(int mps_cpu) { if (mps_cpu < nr_cpu_ids) @@ -93,14 +94,6 @@ static int bigsmp_cpu_present_to_apicid(int mps_cpu) return BAD_APICID; } -/* Mapping from cpu number to logical apicid */ -static inline int bigsmp_cpu_to_logical_apicid(int cpu) -{ - if (cpu >= nr_cpu_ids) - return BAD_APICID; - return cpu_physical_id(cpu); -} - static void bigsmp_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) { /* For clustered we don't have a good way to do this yet - hack */ @@ -115,7 +108,11 @@ static int bigsmp_check_phys_apicid_present(int phys_apicid) /* As we are using single CPU as destination, pick only one CPU here */ static unsigned int bigsmp_cpu_mask_to_apicid(const struct cpumask *cpumask) { - return bigsmp_cpu_to_logical_apicid(cpumask_first(cpumask)); + int cpu = cpumask_first(cpumask); + + if (cpu < nr_cpu_ids) + return cpu_physical_id(cpu); + return BAD_APICID; } static unsigned int bigsmp_cpu_mask_to_apicid_and(const struct cpumask *cpumask, @@ -129,9 +126,9 @@ static unsigned int bigsmp_cpu_mask_to_apicid_and(const struct cpumask *cpumask, */ for_each_cpu_and(cpu, cpumask, andmask) { if (cpumask_test_cpu(cpu, cpu_online_mask)) - break; + return cpu_physical_id(cpu); } - return bigsmp_cpu_to_logical_apicid(cpu); + return BAD_APICID; } static int bigsmp_phys_pkg_id(int cpuid_apic, int index_msb) @@ -219,8 +216,6 @@ struct apic apic_bigsmp = { .ioapic_phys_id_map = bigsmp_ioapic_phys_id_map, .setup_apic_routing = bigsmp_setup_apic_routing, .multi_timer_check = NULL, - .apicid_to_node = bigsmp_apicid_to_node, - .cpu_to_logical_apicid = bigsmp_cpu_to_logical_apicid, .cpu_present_to_apicid = bigsmp_cpu_present_to_apicid, .apicid_to_cpu_present = physid_set_mask_of_physid, .setup_portio_remap = NULL, @@ -256,4 +251,7 @@ struct apic apic_bigsmp = { .icr_write = native_apic_icr_write, .wait_icr_idle = native_apic_wait_icr_idle, .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, + + .x86_32_early_logical_apicid = bigsmp_early_logical_apicid, + .x86_32_numa_cpu_node = default_x86_32_numa_cpu_node, }; diff --git a/arch/x86/kernel/apic/es7000_32.c b/arch/x86/kernel/apic/es7000_32.c index 8593582d8022..3e9de4854c5b 100644 --- a/arch/x86/kernel/apic/es7000_32.c +++ b/arch/x86/kernel/apic/es7000_32.c @@ -460,6 +460,12 @@ static unsigned long es7000_check_apicid_present(int bit) return physid_isset(bit, phys_cpu_present_map); } +static int es7000_early_logical_apicid(int cpu) +{ + /* on es7000, logical apicid is the same as physical */ + return early_per_cpu(x86_bios_cpu_apicid, cpu); +} + static unsigned long calculate_ldr(int cpu) { unsigned long id = per_cpu(x86_bios_cpu_apicid, cpu); @@ -504,12 +510,11 @@ static void es7000_setup_apic_routing(void) nr_ioapics, cpumask_bits(es7000_target_cpus())[0]); } -static int es7000_apicid_to_node(int logical_apicid) +static int es7000_numa_cpu_node(int cpu) { return 0; } - static int es7000_cpu_present_to_apicid(int mps_cpu) { if (!mps_cpu) @@ -528,18 +533,6 @@ static void es7000_apicid_to_cpu_present(int phys_apicid, physid_mask_t *retmap) ++cpu_id; } -/* Mapping from cpu number to logical apicid */ -static int es7000_cpu_to_logical_apicid(int cpu) -{ -#ifdef CONFIG_SMP - if (cpu >= nr_cpu_ids) - return BAD_APICID; - return cpu_2_logical_apicid[cpu]; -#else - return logical_smp_processor_id(); -#endif -} - static void es7000_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) { /* For clustered we don't have a good way to do this yet - hack */ @@ -561,7 +554,7 @@ static unsigned int es7000_cpu_mask_to_apicid(const struct cpumask *cpumask) * The cpus in the mask must all be on the apic cluster. */ for_each_cpu(cpu, cpumask) { - int new_apicid = es7000_cpu_to_logical_apicid(cpu); + int new_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); if (round && APIC_CLUSTER(apicid) != APIC_CLUSTER(new_apicid)) { WARN(1, "Not a valid mask!"); @@ -578,7 +571,7 @@ static unsigned int es7000_cpu_mask_to_apicid_and(const struct cpumask *inmask, const struct cpumask *andmask) { - int apicid = es7000_cpu_to_logical_apicid(0); + int apicid = early_per_cpu(x86_cpu_to_logical_apicid, 0); cpumask_var_t cpumask; if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC)) @@ -655,8 +648,6 @@ struct apic __refdata apic_es7000_cluster = { .ioapic_phys_id_map = es7000_ioapic_phys_id_map, .setup_apic_routing = es7000_setup_apic_routing, .multi_timer_check = NULL, - .apicid_to_node = es7000_apicid_to_node, - .cpu_to_logical_apicid = es7000_cpu_to_logical_apicid, .cpu_present_to_apicid = es7000_cpu_present_to_apicid, .apicid_to_cpu_present = es7000_apicid_to_cpu_present, .setup_portio_remap = NULL, @@ -695,6 +686,9 @@ struct apic __refdata apic_es7000_cluster = { .icr_write = native_apic_icr_write, .wait_icr_idle = native_apic_wait_icr_idle, .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, + + .x86_32_early_logical_apicid = es7000_early_logical_apicid, + .x86_32_numa_cpu_node = es7000_numa_cpu_node, }; struct apic __refdata apic_es7000 = { @@ -720,8 +714,6 @@ struct apic __refdata apic_es7000 = { .ioapic_phys_id_map = es7000_ioapic_phys_id_map, .setup_apic_routing = es7000_setup_apic_routing, .multi_timer_check = NULL, - .apicid_to_node = es7000_apicid_to_node, - .cpu_to_logical_apicid = es7000_cpu_to_logical_apicid, .cpu_present_to_apicid = es7000_cpu_present_to_apicid, .apicid_to_cpu_present = es7000_apicid_to_cpu_present, .setup_portio_remap = NULL, @@ -758,4 +750,7 @@ struct apic __refdata apic_es7000 = { .icr_write = native_apic_icr_write, .wait_icr_idle = native_apic_wait_icr_idle, .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, + + .x86_32_early_logical_apicid = es7000_early_logical_apicid, + .x86_32_numa_cpu_node = es7000_numa_cpu_node, }; diff --git a/arch/x86/kernel/apic/hw_nmi.c b/arch/x86/kernel/apic/hw_nmi.c index 79fd43ca6f96..c4e557a1ebb6 100644 --- a/arch/x86/kernel/apic/hw_nmi.c +++ b/arch/x86/kernel/apic/hw_nmi.c @@ -83,7 +83,6 @@ arch_trigger_all_cpu_backtrace_handler(struct notifier_block *self, arch_spin_lock(&lock); printk(KERN_WARNING "NMI backtrace for cpu %d\n", cpu); show_regs(regs); - dump_stack(); arch_spin_unlock(&lock); cpumask_clear_cpu(cpu, to_cpumask(backtrace_mask)); return NOTIFY_STOP; diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index ca9e2a3545a9..4b5ebd26f565 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -108,7 +108,10 @@ DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); int skip_ioapic_setup; -void arch_disable_smp_support(void) +/** + * disable_ioapic_support() - disables ioapic support at runtime + */ +void disable_ioapic_support(void) { #ifdef CONFIG_PCI noioapicquirk = 1; @@ -120,11 +123,14 @@ void arch_disable_smp_support(void) static int __init parse_noapic(char *str) { /* disable IO-APIC */ - arch_disable_smp_support(); + disable_ioapic_support(); return 0; } early_param("noapic", parse_noapic); +static int io_apic_setup_irq_pin_once(unsigned int irq, int node, + struct io_apic_irq_attr *attr); + /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ void mp_save_irq(struct mpc_intsrc *m) { @@ -181,7 +187,7 @@ int __init arch_early_irq_init(void) irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs); for (i = 0; i < count; i++) { - set_irq_chip_data(i, &cfg[i]); + irq_set_chip_data(i, &cfg[i]); zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node); zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node); /* @@ -200,7 +206,7 @@ int __init arch_early_irq_init(void) #ifdef CONFIG_SPARSE_IRQ static struct irq_cfg *irq_cfg(unsigned int irq) { - return get_irq_chip_data(irq); + return irq_get_chip_data(irq); } static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) @@ -226,7 +232,7 @@ static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) { if (!cfg) return; - set_irq_chip_data(at, NULL); + irq_set_chip_data(at, NULL); free_cpumask_var(cfg->domain); free_cpumask_var(cfg->old_domain); kfree(cfg); @@ -256,14 +262,14 @@ static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node) if (res < 0) { if (res != -EEXIST) return NULL; - cfg = get_irq_chip_data(at); + cfg = irq_get_chip_data(at); if (cfg) return cfg; } cfg = alloc_irq_cfg(at, node); if (cfg) - set_irq_chip_data(at, cfg); + irq_set_chip_data(at, cfg); else irq_free_desc(at); return cfg; @@ -818,7 +824,7 @@ static int EISA_ELCR(unsigned int irq) #define default_MCA_trigger(idx) (1) #define default_MCA_polarity(idx) default_ISA_polarity(idx) -static int MPBIOS_polarity(int idx) +static int irq_polarity(int idx) { int bus = mp_irqs[idx].srcbus; int polarity; @@ -860,7 +866,7 @@ static int MPBIOS_polarity(int idx) return polarity; } -static int MPBIOS_trigger(int idx) +static int irq_trigger(int idx) { int bus = mp_irqs[idx].srcbus; int trigger; @@ -932,16 +938,6 @@ static int MPBIOS_trigger(int idx) return trigger; } -static inline int irq_polarity(int idx) -{ - return MPBIOS_polarity(idx); -} - -static inline int irq_trigger(int idx) -{ - return MPBIOS_trigger(idx); -} - static int pin_2_irq(int idx, int apic, int pin) { int irq; @@ -1189,7 +1185,7 @@ void __setup_vector_irq(int cpu) raw_spin_lock(&vector_lock); /* Mark the inuse vectors */ for_each_active_irq(irq) { - cfg = get_irq_chip_data(irq); + cfg = irq_get_chip_data(irq); if (!cfg) continue; /* @@ -1220,10 +1216,6 @@ void __setup_vector_irq(int cpu) static struct irq_chip ioapic_chip; static struct irq_chip ir_ioapic_chip; -#define IOAPIC_AUTO -1 -#define IOAPIC_EDGE 0 -#define IOAPIC_LEVEL 1 - #ifdef CONFIG_X86_32 static inline int IO_APIC_irq_trigger(int irq) { @@ -1248,35 +1240,31 @@ static inline int IO_APIC_irq_trigger(int irq) } #endif -static void ioapic_register_intr(unsigned int irq, unsigned long trigger) +static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg, + unsigned long trigger) { + struct irq_chip *chip = &ioapic_chip; + irq_flow_handler_t hdl; + bool fasteoi; if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || - trigger == IOAPIC_LEVEL) + trigger == IOAPIC_LEVEL) { irq_set_status_flags(irq, IRQ_LEVEL); - else + fasteoi = true; + } else { irq_clear_status_flags(irq, IRQ_LEVEL); + fasteoi = false; + } - if (irq_remapped(get_irq_chip_data(irq))) { + if (irq_remapped(cfg)) { irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); - if (trigger) - set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, - handle_fasteoi_irq, - "fasteoi"); - else - set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, - handle_edge_irq, "edge"); - return; + chip = &ir_ioapic_chip; + fasteoi = trigger != 0; } - if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || - trigger == IOAPIC_LEVEL) - set_irq_chip_and_handler_name(irq, &ioapic_chip, - handle_fasteoi_irq, - "fasteoi"); - else - set_irq_chip_and_handler_name(irq, &ioapic_chip, - handle_edge_irq, "edge"); + hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq; + irq_set_chip_and_handler_name(irq, chip, hdl, + fasteoi ? "fasteoi" : "edge"); } static int setup_ioapic_entry(int apic_id, int irq, @@ -1374,7 +1362,7 @@ static void setup_ioapic_irq(int apic_id, int pin, unsigned int irq, return; } - ioapic_register_intr(irq, trigger); + ioapic_register_intr(irq, cfg, trigger); if (irq < legacy_pic->nr_legacy_irqs) legacy_pic->mask(irq); @@ -1385,33 +1373,26 @@ static struct { DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); } mp_ioapic_routing[MAX_IO_APICS]; -static void __init setup_IO_APIC_irqs(void) +static bool __init io_apic_pin_not_connected(int idx, int apic_id, int pin) { - int apic_id, pin, idx, irq, notcon = 0; - int node = cpu_to_node(0); - struct irq_cfg *cfg; + if (idx != -1) + return false; - apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); + apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n", + mp_ioapics[apic_id].apicid, pin); + return true; +} + +static void __init __io_apic_setup_irqs(unsigned int apic_id) +{ + int idx, node = cpu_to_node(0); + struct io_apic_irq_attr attr; + unsigned int pin, irq; - for (apic_id = 0; apic_id < nr_ioapics; apic_id++) for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { idx = find_irq_entry(apic_id, pin, mp_INT); - if (idx == -1) { - if (!notcon) { - notcon = 1; - apic_printk(APIC_VERBOSE, - KERN_DEBUG " %d-%d", - mp_ioapics[apic_id].apicid, pin); - } else - apic_printk(APIC_VERBOSE, " %d-%d", - mp_ioapics[apic_id].apicid, pin); + if (io_apic_pin_not_connected(idx, apic_id, pin)) continue; - } - if (notcon) { - apic_printk(APIC_VERBOSE, - " (apicid-pin) not connected\n"); - notcon = 0; - } irq = pin_2_irq(idx, apic_id, pin); @@ -1423,25 +1404,24 @@ static void __init setup_IO_APIC_irqs(void) * installed and if it returns 1: */ if (apic->multi_timer_check && - apic->multi_timer_check(apic_id, irq)) + apic->multi_timer_check(apic_id, irq)) continue; - cfg = alloc_irq_and_cfg_at(irq, node); - if (!cfg) - continue; + set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx), + irq_polarity(idx)); - add_pin_to_irq_node(cfg, node, apic_id, pin); - /* - * don't mark it in pin_programmed, so later acpi could - * set it correctly when irq < 16 - */ - setup_ioapic_irq(apic_id, pin, irq, cfg, irq_trigger(idx), - irq_polarity(idx)); + io_apic_setup_irq_pin(irq, node, &attr); } +} - if (notcon) - apic_printk(APIC_VERBOSE, - " (apicid-pin) not connected\n"); +static void __init setup_IO_APIC_irqs(void) +{ + unsigned int apic_id; + + apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); + + for (apic_id = 0; apic_id < nr_ioapics; apic_id++) + __io_apic_setup_irqs(apic_id); } /* @@ -1452,7 +1432,7 @@ static void __init setup_IO_APIC_irqs(void) void setup_IO_APIC_irq_extra(u32 gsi) { int apic_id = 0, pin, idx, irq, node = cpu_to_node(0); - struct irq_cfg *cfg; + struct io_apic_irq_attr attr; /* * Convert 'gsi' to 'ioapic.pin'. @@ -1472,21 +1452,10 @@ void setup_IO_APIC_irq_extra(u32 gsi) if (apic_id == 0 || irq < NR_IRQS_LEGACY) return; - cfg = alloc_irq_and_cfg_at(irq, node); - if (!cfg) - return; - - add_pin_to_irq_node(cfg, node, apic_id, pin); - - if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) { - pr_debug("Pin %d-%d already programmed\n", - mp_ioapics[apic_id].apicid, pin); - return; - } - set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed); + set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx), + irq_polarity(idx)); - setup_ioapic_irq(apic_id, pin, irq, cfg, - irq_trigger(idx), irq_polarity(idx)); + io_apic_setup_irq_pin_once(irq, node, &attr); } /* @@ -1518,7 +1487,8 @@ static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, * The timer IRQ doesn't have to know that behind the * scene we may have a 8259A-master in AEOI mode ... */ - set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); + irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, + "edge"); /* * Add it to the IO-APIC irq-routing table: @@ -1625,7 +1595,7 @@ __apicdebuginit(void) print_IO_APIC(void) for_each_active_irq(irq) { struct irq_pin_list *entry; - cfg = get_irq_chip_data(irq); + cfg = irq_get_chip_data(irq); if (!cfg) continue; entry = cfg->irq_2_pin; @@ -2391,7 +2361,7 @@ static void irq_complete_move(struct irq_cfg *cfg) void irq_force_complete_move(int irq) { - struct irq_cfg *cfg = get_irq_chip_data(irq); + struct irq_cfg *cfg = irq_get_chip_data(irq); if (!cfg) return; @@ -2405,7 +2375,7 @@ static inline void irq_complete_move(struct irq_cfg *cfg) { } static void ack_apic_edge(struct irq_data *data) { irq_complete_move(data->chip_data); - move_native_irq(data->irq); + irq_move_irq(data); ack_APIC_irq(); } @@ -2462,7 +2432,7 @@ static void ack_apic_level(struct irq_data *data) irq_complete_move(cfg); #ifdef CONFIG_GENERIC_PENDING_IRQ /* If we are moving the irq we need to mask it */ - if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) { + if (unlikely(irqd_is_setaffinity_pending(data))) { do_unmask_irq = 1; mask_ioapic(cfg); } @@ -2551,7 +2521,7 @@ static void ack_apic_level(struct irq_data *data) * and you can go talk to the chipset vendor about it. */ if (!io_apic_level_ack_pending(cfg)) - move_masked_irq(irq); + irq_move_masked_irq(data); unmask_ioapic(cfg); } } @@ -2614,7 +2584,7 @@ static inline void init_IO_APIC_traps(void) * 0x80, because int 0x80 is hm, kind of importantish. ;) */ for_each_active_irq(irq) { - cfg = get_irq_chip_data(irq); + cfg = irq_get_chip_data(irq); if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { /* * Hmm.. We don't have an entry for this, @@ -2625,7 +2595,7 @@ static inline void init_IO_APIC_traps(void) legacy_pic->make_irq(irq); else /* Strange. Oh, well.. */ - set_irq_chip(irq, &no_irq_chip); + irq_set_chip(irq, &no_irq_chip); } } } @@ -2665,7 +2635,7 @@ static struct irq_chip lapic_chip __read_mostly = { static void lapic_register_intr(int irq) { irq_clear_status_flags(irq, IRQ_LEVEL); - set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, + irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, "edge"); } @@ -2749,7 +2719,7 @@ int timer_through_8259 __initdata; */ static inline void __init check_timer(void) { - struct irq_cfg *cfg = get_irq_chip_data(0); + struct irq_cfg *cfg = irq_get_chip_data(0); int node = cpu_to_node(0); int apic1, pin1, apic2, pin2; unsigned long flags; @@ -3060,7 +3030,7 @@ unsigned int create_irq_nr(unsigned int from, int node) raw_spin_unlock_irqrestore(&vector_lock, flags); if (ret) { - set_irq_chip_data(irq, cfg); + irq_set_chip_data(irq, cfg); irq_clear_status_flags(irq, IRQ_NOREQUEST); } else { free_irq_at(irq, cfg); @@ -3085,7 +3055,7 @@ int create_irq(void) void destroy_irq(unsigned int irq) { - struct irq_cfg *cfg = get_irq_chip_data(irq); + struct irq_cfg *cfg = irq_get_chip_data(irq); unsigned long flags; irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE); @@ -3119,7 +3089,7 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); - if (irq_remapped(get_irq_chip_data(irq))) { + if (irq_remapped(cfg)) { struct irte irte; int ir_index; u16 sub_handle; @@ -3291,6 +3261,7 @@ static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) { + struct irq_chip *chip = &msi_chip; struct msi_msg msg; int ret; @@ -3298,14 +3269,15 @@ static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) if (ret < 0) return ret; - set_irq_msi(irq, msidesc); + irq_set_msi_desc(irq, msidesc); write_msi_msg(irq, &msg); - if (irq_remapped(get_irq_chip_data(irq))) { + if (irq_remapped(irq_get_chip_data(irq))) { irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); - set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); - } else - set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); + chip = &msi_ir_chip; + } + + irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); @@ -3423,8 +3395,8 @@ int arch_setup_dmar_msi(unsigned int irq) if (ret < 0) return ret; dmar_msi_write(irq, &msg); - set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, - "edge"); + irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, + "edge"); return 0; } #endif @@ -3482,6 +3454,7 @@ static struct irq_chip hpet_msi_type = { int arch_setup_hpet_msi(unsigned int irq, unsigned int id) { + struct irq_chip *chip = &hpet_msi_type; struct msi_msg msg; int ret; @@ -3501,15 +3474,12 @@ int arch_setup_hpet_msi(unsigned int irq, unsigned int id) if (ret < 0) return ret; - hpet_msi_write(get_irq_data(irq), &msg); + hpet_msi_write(irq_get_handler_data(irq), &msg); irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); - if (irq_remapped(get_irq_chip_data(irq))) - set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type, - handle_edge_irq, "edge"); - else - set_irq_chip_and_handler_name(irq, &hpet_msi_type, - handle_edge_irq, "edge"); + if (irq_remapped(irq_get_chip_data(irq))) + chip = &ir_hpet_msi_type; + irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); return 0; } #endif @@ -3596,7 +3566,7 @@ int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) write_ht_irq_msg(irq, &msg); - set_irq_chip_and_handler_name(irq, &ht_irq_chip, + irq_set_chip_and_handler_name(irq, &ht_irq_chip, handle_edge_irq, "edge"); dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); @@ -3605,7 +3575,40 @@ int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) } #endif /* CONFIG_HT_IRQ */ -int __init io_apic_get_redir_entries (int ioapic) +int +io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr) +{ + struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node); + int ret; + + if (!cfg) + return -EINVAL; + ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin); + if (!ret) + setup_ioapic_irq(attr->ioapic, attr->ioapic_pin, irq, cfg, + attr->trigger, attr->polarity); + return ret; +} + +static int io_apic_setup_irq_pin_once(unsigned int irq, int node, + struct io_apic_irq_attr *attr) +{ + unsigned int id = attr->ioapic, pin = attr->ioapic_pin; + int ret; + + /* Avoid redundant programming */ + if (test_bit(pin, mp_ioapic_routing[id].pin_programmed)) { + pr_debug("Pin %d-%d already programmed\n", + mp_ioapics[id].apicid, pin); + return 0; + } + ret = io_apic_setup_irq_pin(irq, node, attr); + if (!ret) + set_bit(pin, mp_ioapic_routing[id].pin_programmed); + return ret; +} + +static int __init io_apic_get_redir_entries(int ioapic) { union IO_APIC_reg_01 reg_01; unsigned long flags; @@ -3659,96 +3662,24 @@ int __init arch_probe_nr_irqs(void) } #endif -static int __io_apic_set_pci_routing(struct device *dev, int irq, - struct io_apic_irq_attr *irq_attr) +int io_apic_set_pci_routing(struct device *dev, int irq, + struct io_apic_irq_attr *irq_attr) { - struct irq_cfg *cfg; int node; - int ioapic, pin; - int trigger, polarity; - ioapic = irq_attr->ioapic; if (!IO_APIC_IRQ(irq)) { apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", - ioapic); + irq_attr->ioapic); return -EINVAL; } - if (dev) - node = dev_to_node(dev); - else - node = cpu_to_node(0); - - cfg = alloc_irq_and_cfg_at(irq, node); - if (!cfg) - return 0; - - pin = irq_attr->ioapic_pin; - trigger = irq_attr->trigger; - polarity = irq_attr->polarity; + node = dev ? dev_to_node(dev) : cpu_to_node(0); - /* - * IRQs < 16 are already in the irq_2_pin[] map - */ - if (irq >= legacy_pic->nr_legacy_irqs) { - if (__add_pin_to_irq_node(cfg, node, ioapic, pin)) { - printk(KERN_INFO "can not add pin %d for irq %d\n", - pin, irq); - return 0; - } - } - - setup_ioapic_irq(ioapic, pin, irq, cfg, trigger, polarity); - - return 0; + return io_apic_setup_irq_pin_once(irq, node, irq_attr); } -int io_apic_set_pci_routing(struct device *dev, int irq, - struct io_apic_irq_attr *irq_attr) -{ - int ioapic, pin; - /* - * Avoid pin reprogramming. PRTs typically include entries - * with redundant pin->gsi mappings (but unique PCI devices); - * we only program the IOAPIC on the first. - */ - ioapic = irq_attr->ioapic; - pin = irq_attr->ioapic_pin; - if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) { - pr_debug("Pin %d-%d already programmed\n", - mp_ioapics[ioapic].apicid, pin); - return 0; - } - set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed); - - return __io_apic_set_pci_routing(dev, irq, irq_attr); -} - -u8 __init io_apic_unique_id(u8 id) -{ #ifdef CONFIG_X86_32 - if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && - !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) - return io_apic_get_unique_id(nr_ioapics, id); - else - return id; -#else - int i; - DECLARE_BITMAP(used, 256); - - bitmap_zero(used, 256); - for (i = 0; i < nr_ioapics; i++) { - struct mpc_ioapic *ia = &mp_ioapics[i]; - __set_bit(ia->apicid, used); - } - if (!test_bit(id, used)) - return id; - return find_first_zero_bit(used, 256); -#endif -} - -#ifdef CONFIG_X86_32 -int __init io_apic_get_unique_id(int ioapic, int apic_id) +static int __init io_apic_get_unique_id(int ioapic, int apic_id) { union IO_APIC_reg_00 reg_00; static physid_mask_t apic_id_map = PHYSID_MASK_NONE; @@ -3821,9 +3752,33 @@ int __init io_apic_get_unique_id(int ioapic, int apic_id) return apic_id; } + +static u8 __init io_apic_unique_id(u8 id) +{ + if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && + !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) + return io_apic_get_unique_id(nr_ioapics, id); + else + return id; +} +#else +static u8 __init io_apic_unique_id(u8 id) +{ + int i; + DECLARE_BITMAP(used, 256); + + bitmap_zero(used, 256); + for (i = 0; i < nr_ioapics; i++) { + struct mpc_ioapic *ia = &mp_ioapics[i]; + __set_bit(ia->apicid, used); + } + if (!test_bit(id, used)) + return id; + return find_first_zero_bit(used, 256); +} #endif -int __init io_apic_get_version(int ioapic) +static int __init io_apic_get_version(int ioapic) { union IO_APIC_reg_01 reg_01; unsigned long flags; @@ -3868,8 +3823,8 @@ int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) void __init setup_ioapic_dest(void) { int pin, ioapic, irq, irq_entry; - struct irq_desc *desc; const struct cpumask *mask; + struct irq_data *idata; if (skip_ioapic_setup == 1) return; @@ -3884,21 +3839,20 @@ void __init setup_ioapic_dest(void) if ((ioapic > 0) && (irq > 16)) continue; - desc = irq_to_desc(irq); + idata = irq_get_irq_data(irq); /* * Honour affinities which have been set in early boot */ - if (desc->status & - (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) - mask = desc->irq_data.affinity; + if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata)) + mask = idata->affinity; else mask = apic->target_cpus(); if (intr_remapping_enabled) - ir_ioapic_set_affinity(&desc->irq_data, mask, false); + ir_ioapic_set_affinity(idata, mask, false); else - ioapic_set_affinity(&desc->irq_data, mask, false); + ioapic_set_affinity(idata, mask, false); } } @@ -4026,7 +3980,7 @@ int mp_find_ioapic_pin(int ioapic, u32 gsi) return gsi - mp_gsi_routing[ioapic].gsi_base; } -static int bad_ioapic(unsigned long address) +static __init int bad_ioapic(unsigned long address) { if (nr_ioapics >= MAX_IO_APICS) { printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded " @@ -4086,20 +4040,16 @@ void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) /* Enable IOAPIC early just for system timer */ void __init pre_init_apic_IRQ0(void) { - struct irq_cfg *cfg; + struct io_apic_irq_attr attr = { 0, 0, 0, 0 }; printk(KERN_INFO "Early APIC setup for system timer0\n"); #ifndef CONFIG_SMP physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); #endif - /* Make sure the irq descriptor is set up */ - cfg = alloc_irq_and_cfg_at(0, 0); - setup_local_APIC(); - add_pin_to_irq_node(cfg, 0, 0, 0); - set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); - - setup_ioapic_irq(0, 0, 0, cfg, 0, 0); + io_apic_setup_irq_pin(0, 0, &attr); + irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, + "edge"); } diff --git a/arch/x86/kernel/apic/ipi.c b/arch/x86/kernel/apic/ipi.c index 08385e090a6f..cce91bf26676 100644 --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -56,6 +56,8 @@ void default_send_IPI_mask_allbutself_phys(const struct cpumask *mask, local_irq_restore(flags); } +#ifdef CONFIG_X86_32 + void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, int vector) { @@ -71,8 +73,8 @@ void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, local_irq_save(flags); for_each_cpu(query_cpu, mask) __default_send_IPI_dest_field( - apic->cpu_to_logical_apicid(query_cpu), vector, - apic->dest_logical); + early_per_cpu(x86_cpu_to_logical_apicid, query_cpu), + vector, apic->dest_logical); local_irq_restore(flags); } @@ -90,14 +92,12 @@ void default_send_IPI_mask_allbutself_logical(const struct cpumask *mask, if (query_cpu == this_cpu) continue; __default_send_IPI_dest_field( - apic->cpu_to_logical_apicid(query_cpu), vector, - apic->dest_logical); + early_per_cpu(x86_cpu_to_logical_apicid, query_cpu), + vector, apic->dest_logical); } local_irq_restore(flags); } -#ifdef CONFIG_X86_32 - /* * This is only used on smaller machines. */ diff --git a/arch/x86/kernel/apic/numaq_32.c b/arch/x86/kernel/apic/numaq_32.c index 960f26ab5c9f..6273eee5134b 100644 --- a/arch/x86/kernel/apic/numaq_32.c +++ b/arch/x86/kernel/apic/numaq_32.c @@ -373,13 +373,6 @@ static inline void numaq_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask return physids_promote(0xFUL, retmap); } -static inline int numaq_cpu_to_logical_apicid(int cpu) -{ - if (cpu >= nr_cpu_ids) - return BAD_APICID; - return cpu_2_logical_apicid[cpu]; -} - /* * Supporting over 60 cpus on NUMA-Q requires a locality-dependent * cpu to APIC ID relation to properly interact with the intelligent @@ -398,6 +391,15 @@ static inline int numaq_apicid_to_node(int logical_apicid) return logical_apicid >> 4; } +static int numaq_numa_cpu_node(int cpu) +{ + int logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); + + if (logical_apicid != BAD_APICID) + return numaq_apicid_to_node(logical_apicid); + return NUMA_NO_NODE; +} + static void numaq_apicid_to_cpu_present(int logical_apicid, physid_mask_t *retmap) { int node = numaq_apicid_to_node(logical_apicid); @@ -508,8 +510,6 @@ struct apic __refdata apic_numaq = { .ioapic_phys_id_map = numaq_ioapic_phys_id_map, .setup_apic_routing = numaq_setup_apic_routing, .multi_timer_check = numaq_multi_timer_check, - .apicid_to_node = numaq_apicid_to_node, - .cpu_to_logical_apicid = numaq_cpu_to_logical_apicid, .cpu_present_to_apicid = numaq_cpu_present_to_apicid, .apicid_to_cpu_present = numaq_apicid_to_cpu_present, .setup_portio_remap = numaq_setup_portio_remap, @@ -547,4 +547,7 @@ struct apic __refdata apic_numaq = { .icr_write = native_apic_icr_write, .wait_icr_idle = native_apic_wait_icr_idle, .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, + + .x86_32_early_logical_apicid = noop_x86_32_early_logical_apicid, + .x86_32_numa_cpu_node = numaq_numa_cpu_node, }; diff --git a/arch/x86/kernel/apic/probe_32.c b/arch/x86/kernel/apic/probe_32.c index 99d2fe016084..fc84c7b61108 100644 --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -77,6 +77,11 @@ void __init default_setup_apic_routing(void) apic->setup_apic_routing(); } +static int default_x86_32_early_logical_apicid(int cpu) +{ + return 1 << cpu; +} + static void setup_apic_flat_routing(void) { #ifdef CONFIG_X86_IO_APIC @@ -130,8 +135,6 @@ struct apic apic_default = { .ioapic_phys_id_map = default_ioapic_phys_id_map, .setup_apic_routing = setup_apic_flat_routing, .multi_timer_check = NULL, - .apicid_to_node = default_apicid_to_node, - .cpu_to_logical_apicid = default_cpu_to_logical_apicid, .cpu_present_to_apicid = default_cpu_present_to_apicid, .apicid_to_cpu_present = physid_set_mask_of_physid, .setup_portio_remap = NULL, @@ -167,6 +170,9 @@ struct apic apic_default = { .icr_write = native_apic_icr_write, .wait_icr_idle = native_apic_wait_icr_idle, .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, + + .x86_32_early_logical_apicid = default_x86_32_early_logical_apicid, + .x86_32_numa_cpu_node = default_x86_32_numa_cpu_node, }; extern struct apic apic_numaq; diff --git a/arch/x86/kernel/apic/summit_32.c b/arch/x86/kernel/apic/summit_32.c index 9b419263d90d..e4b8059b414a 100644 --- a/arch/x86/kernel/apic/summit_32.c +++ b/arch/x86/kernel/apic/summit_32.c @@ -194,11 +194,10 @@ static unsigned long summit_check_apicid_present(int bit) return 1; } -static void summit_init_apic_ldr(void) +static int summit_early_logical_apicid(int cpu) { - unsigned long val, id; int count = 0; - u8 my_id = (u8)hard_smp_processor_id(); + u8 my_id = early_per_cpu(x86_cpu_to_apicid, cpu); u8 my_cluster = APIC_CLUSTER(my_id); #ifdef CONFIG_SMP u8 lid; @@ -206,7 +205,7 @@ static void summit_init_apic_ldr(void) /* Create logical APIC IDs by counting CPUs already in cluster. */ for (count = 0, i = nr_cpu_ids; --i >= 0; ) { - lid = cpu_2_logical_apicid[i]; + lid = early_per_cpu(x86_cpu_to_logical_apicid, i); if (lid != BAD_APICID && APIC_CLUSTER(lid) == my_cluster) ++count; } @@ -214,7 +213,15 @@ static void summit_init_apic_ldr(void) /* We only have a 4 wide bitmap in cluster mode. If a deranged * BIOS puts 5 CPUs in one APIC cluster, we're hosed. */ BUG_ON(count >= XAPIC_DEST_CPUS_SHIFT); - id = my_cluster | (1UL << count); + return my_cluster | (1UL << count); +} + +static void summit_init_apic_ldr(void) +{ + int cpu = smp_processor_id(); + unsigned long id = early_per_cpu(x86_cpu_to_logical_apicid, cpu); + unsigned long val; + apic_write(APIC_DFR, SUMMIT_APIC_DFR_VALUE); val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; val |= SET_APIC_LOGICAL_ID(id); @@ -232,27 +239,6 @@ static void summit_setup_apic_routing(void) nr_ioapics); } -static int summit_apicid_to_node(int logical_apicid) -{ -#ifdef CONFIG_SMP - return apicid_2_node[hard_smp_processor_id()]; -#else - return 0; -#endif -} - -/* Mapping from cpu number to logical apicid */ -static inline int summit_cpu_to_logical_apicid(int cpu) -{ -#ifdef CONFIG_SMP - if (cpu >= nr_cpu_ids) - return BAD_APICID; - return cpu_2_logical_apicid[cpu]; -#else - return logical_smp_processor_id(); -#endif -} - static int summit_cpu_present_to_apicid(int mps_cpu) { if (mps_cpu < nr_cpu_ids) @@ -286,7 +272,7 @@ static unsigned int summit_cpu_mask_to_apicid(const struct cpumask *cpumask) * The cpus in the mask must all be on the apic cluster. */ for_each_cpu(cpu, cpumask) { - int new_apicid = summit_cpu_to_logical_apicid(cpu); + int new_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); if (round && APIC_CLUSTER(apicid) != APIC_CLUSTER(new_apicid)) { printk("%s: Not a valid mask!\n", __func__); @@ -301,7 +287,7 @@ static unsigned int summit_cpu_mask_to_apicid(const struct cpumask *cpumask) static unsigned int summit_cpu_mask_to_apicid_and(const struct cpumask *inmask, const struct cpumask *andmask) { - int apicid = summit_cpu_to_logical_apicid(0); + int apicid = early_per_cpu(x86_cpu_to_logical_apicid, 0); cpumask_var_t cpumask; if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC)) @@ -528,8 +514,6 @@ struct apic apic_summit = { .ioapic_phys_id_map = summit_ioapic_phys_id_map, .setup_apic_routing = summit_setup_apic_routing, .multi_timer_check = NULL, - .apicid_to_node = summit_apicid_to_node, - .cpu_to_logical_apicid = summit_cpu_to_logical_apicid, .cpu_present_to_apicid = summit_cpu_present_to_apicid, .apicid_to_cpu_present = summit_apicid_to_cpu_present, .setup_portio_remap = NULL, @@ -565,4 +549,7 @@ struct apic apic_summit = { .icr_write = native_apic_icr_write, .wait_icr_idle = native_apic_wait_icr_idle, .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, + + .x86_32_early_logical_apicid = summit_early_logical_apicid, + .x86_32_numa_cpu_node = default_x86_32_numa_cpu_node, }; diff --git a/arch/x86/kernel/apic/x2apic_cluster.c b/arch/x86/kernel/apic/x2apic_cluster.c index cf69c59f4910..90949bbd566d 100644 --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -206,8 +206,6 @@ struct apic apic_x2apic_cluster = { .ioapic_phys_id_map = NULL, .setup_apic_routing = NULL, .multi_timer_check = NULL, - .apicid_to_node = NULL, - .cpu_to_logical_apicid = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .apicid_to_cpu_present = NULL, .setup_portio_remap = NULL, diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c index 8972f38c5ced..c7e6d6645bf4 100644 --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -195,8 +195,6 @@ struct apic apic_x2apic_phys = { .ioapic_phys_id_map = NULL, .setup_apic_routing = NULL, .multi_timer_check = NULL, - .apicid_to_node = NULL, - .cpu_to_logical_apicid = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .apicid_to_cpu_present = NULL, .setup_portio_remap = NULL, diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c index bd16b58b8850..3c289281394c 100644 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -338,8 +338,6 @@ struct apic __refdata apic_x2apic_uv_x = { .ioapic_phys_id_map = NULL, .setup_apic_routing = NULL, .multi_timer_check = NULL, - .apicid_to_node = NULL, - .cpu_to_logical_apicid = NULL, .cpu_present_to_apicid = default_cpu_present_to_apicid, .apicid_to_cpu_present = NULL, .setup_portio_remap = NULL, diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c index 0e4f24c2a746..9079926a5b18 100644 --- a/arch/x86/kernel/apm_32.c +++ b/arch/x86/kernel/apm_32.c @@ -227,6 +227,7 @@ #include <linux/suspend.h> #include <linux/kthread.h> #include <linux/jiffies.h> +#include <linux/acpi.h> #include <asm/system.h> #include <asm/uaccess.h> @@ -975,20 +976,10 @@ recalc: static void apm_power_off(void) { - unsigned char po_bios_call[] = { - 0xb8, 0x00, 0x10, /* movw $0x1000,ax */ - 0x8e, 0xd0, /* movw ax,ss */ - 0xbc, 0x00, 0xf0, /* movw $0xf000,sp */ - 0xb8, 0x07, 0x53, /* movw $0x5307,ax */ - 0xbb, 0x01, 0x00, /* movw $0x0001,bx */ - 0xb9, 0x03, 0x00, /* movw $0x0003,cx */ - 0xcd, 0x15 /* int $0x15 */ - }; - /* Some bioses don't like being called from CPU != 0 */ if (apm_info.realmode_power_off) { set_cpus_allowed_ptr(current, cpumask_of(0)); - machine_real_restart(po_bios_call, sizeof(po_bios_call)); + machine_real_restart(MRR_APM); } else { (void)set_system_power_state(APM_STATE_OFF); } @@ -2331,12 +2322,11 @@ static int __init apm_init(void) apm_info.disabled = 1; return -ENODEV; } - if (pm_flags & PM_ACPI) { + if (!acpi_disabled) { printk(KERN_NOTICE "apm: overridden by ACPI.\n"); apm_info.disabled = 1; return -ENODEV; } - pm_flags |= PM_APM; /* * Set up the long jump entry point to the APM BIOS, which is called @@ -2428,7 +2418,6 @@ static void __exit apm_exit(void) kthread_stop(kapmd_task); kapmd_task = NULL; } - pm_flags &= ~PM_APM; } module_init(apm_init); diff --git a/arch/x86/kernel/asm-offsets.c b/arch/x86/kernel/asm-offsets.c index cfa82c899f47..4f13fafc5264 100644 --- a/arch/x86/kernel/asm-offsets.c +++ b/arch/x86/kernel/asm-offsets.c @@ -1,5 +1,70 @@ +/* + * Generate definitions needed by assembly language modules. + * This code generates raw asm output which is post-processed to extract + * and format the required data. + */ +#define COMPILE_OFFSETS + +#include <linux/crypto.h> +#include <linux/sched.h> +#include <linux/stddef.h> +#include <linux/hardirq.h> +#include <linux/suspend.h> +#include <linux/kbuild.h> +#include <asm/processor.h> +#include <asm/thread_info.h> +#include <asm/sigframe.h> +#include <asm/bootparam.h> +#include <asm/suspend.h> + +#ifdef CONFIG_XEN +#include <xen/interface/xen.h> +#endif + #ifdef CONFIG_X86_32 # include "asm-offsets_32.c" #else # include "asm-offsets_64.c" #endif + +void common(void) { + BLANK(); + OFFSET(TI_flags, thread_info, flags); + OFFSET(TI_status, thread_info, status); + OFFSET(TI_addr_limit, thread_info, addr_limit); + OFFSET(TI_preempt_count, thread_info, preempt_count); + + BLANK(); + OFFSET(crypto_tfm_ctx_offset, crypto_tfm, __crt_ctx); + + BLANK(); + OFFSET(pbe_address, pbe, address); + OFFSET(pbe_orig_address, pbe, orig_address); + OFFSET(pbe_next, pbe, next); + +#ifdef CONFIG_PARAVIRT + BLANK(); + OFFSET(PARAVIRT_enabled, pv_info, paravirt_enabled); + OFFSET(PARAVIRT_PATCH_pv_cpu_ops, paravirt_patch_template, pv_cpu_ops); + OFFSET(PARAVIRT_PATCH_pv_irq_ops, paravirt_patch_template, pv_irq_ops); + OFFSET(PV_IRQ_irq_disable, pv_irq_ops, irq_disable); + OFFSET(PV_IRQ_irq_enable, pv_irq_ops, irq_enable); + OFFSET(PV_CPU_iret, pv_cpu_ops, iret); + OFFSET(PV_CPU_irq_enable_sysexit, pv_cpu_ops, irq_enable_sysexit); + OFFSET(PV_CPU_read_cr0, pv_cpu_ops, read_cr0); + OFFSET(PV_MMU_read_cr2, pv_mmu_ops, read_cr2); +#endif + +#ifdef CONFIG_XEN + BLANK(); + OFFSET(XEN_vcpu_info_mask, vcpu_info, evtchn_upcall_mask); + OFFSET(XEN_vcpu_info_pending, vcpu_info, evtchn_upcall_pending); +#endif + + BLANK(); + OFFSET(BP_scratch, boot_params, scratch); + OFFSET(BP_loadflags, boot_params, hdr.loadflags); + OFFSET(BP_hardware_subarch, boot_params, hdr.hardware_subarch); + OFFSET(BP_version, boot_params, hdr.version); + OFFSET(BP_kernel_alignment, boot_params, hdr.kernel_alignment); +} diff --git a/arch/x86/kernel/asm-offsets_32.c b/arch/x86/kernel/asm-offsets_32.c index 1a4088dda37a..c29d631af6fc 100644 --- a/arch/x86/kernel/asm-offsets_32.c +++ b/arch/x86/kernel/asm-offsets_32.c @@ -1,26 +1,4 @@ -/* - * Generate definitions needed by assembly language modules. - * This code generates raw asm output which is post-processed - * to extract and format the required data. - */ - -#include <linux/crypto.h> -#include <linux/sched.h> -#include <linux/signal.h> -#include <linux/personality.h> -#include <linux/suspend.h> -#include <linux/kbuild.h> #include <asm/ucontext.h> -#include <asm/sigframe.h> -#include <asm/pgtable.h> -#include <asm/fixmap.h> -#include <asm/processor.h> -#include <asm/thread_info.h> -#include <asm/bootparam.h> -#include <asm/elf.h> -#include <asm/suspend.h> - -#include <xen/interface/xen.h> #include <linux/lguest.h> #include "../../../drivers/lguest/lg.h" @@ -51,21 +29,10 @@ void foo(void) OFFSET(CPUINFO_x86_vendor_id, cpuinfo_x86, x86_vendor_id); BLANK(); - OFFSET(TI_task, thread_info, task); - OFFSET(TI_exec_domain, thread_info, exec_domain); - OFFSET(TI_flags, thread_info, flags); - OFFSET(TI_status, thread_info, status); - OFFSET(TI_preempt_count, thread_info, preempt_count); - OFFSET(TI_addr_limit, thread_info, addr_limit); - OFFSET(TI_restart_block, thread_info, restart_block); OFFSET(TI_sysenter_return, thread_info, sysenter_return); OFFSET(TI_cpu, thread_info, cpu); BLANK(); - OFFSET(GDS_size, desc_ptr, size); - OFFSET(GDS_address, desc_ptr, address); - BLANK(); - OFFSET(PT_EBX, pt_regs, bx); OFFSET(PT_ECX, pt_regs, cx); OFFSET(PT_EDX, pt_regs, dx); @@ -85,42 +52,13 @@ void foo(void) OFFSET(PT_OLDSS, pt_regs, ss); BLANK(); - OFFSET(EXEC_DOMAIN_handler, exec_domain, handler); OFFSET(IA32_RT_SIGFRAME_sigcontext, rt_sigframe, uc.uc_mcontext); BLANK(); - OFFSET(pbe_address, pbe, address); - OFFSET(pbe_orig_address, pbe, orig_address); - OFFSET(pbe_next, pbe, next); - /* Offset from the sysenter stack to tss.sp0 */ DEFINE(TSS_sysenter_sp0, offsetof(struct tss_struct, x86_tss.sp0) - sizeof(struct tss_struct)); - DEFINE(PAGE_SIZE_asm, PAGE_SIZE); - DEFINE(PAGE_SHIFT_asm, PAGE_SHIFT); - DEFINE(THREAD_SIZE_asm, THREAD_SIZE); - - OFFSET(crypto_tfm_ctx_offset, crypto_tfm, __crt_ctx); - -#ifdef CONFIG_PARAVIRT - BLANK(); - OFFSET(PARAVIRT_enabled, pv_info, paravirt_enabled); - OFFSET(PARAVIRT_PATCH_pv_cpu_ops, paravirt_patch_template, pv_cpu_ops); - OFFSET(PARAVIRT_PATCH_pv_irq_ops, paravirt_patch_template, pv_irq_ops); - OFFSET(PV_IRQ_irq_disable, pv_irq_ops, irq_disable); - OFFSET(PV_IRQ_irq_enable, pv_irq_ops, irq_enable); - OFFSET(PV_CPU_iret, pv_cpu_ops, iret); - OFFSET(PV_CPU_irq_enable_sysexit, pv_cpu_ops, irq_enable_sysexit); - OFFSET(PV_CPU_read_cr0, pv_cpu_ops, read_cr0); -#endif - -#ifdef CONFIG_XEN - BLANK(); - OFFSET(XEN_vcpu_info_mask, vcpu_info, evtchn_upcall_mask); - OFFSET(XEN_vcpu_info_pending, vcpu_info, evtchn_upcall_pending); -#endif - #if defined(CONFIG_LGUEST) || defined(CONFIG_LGUEST_GUEST) || defined(CONFIG_LGUEST_MODULE) BLANK(); OFFSET(LGUEST_DATA_irq_enabled, lguest_data, irq_enabled); @@ -139,11 +77,4 @@ void foo(void) OFFSET(LGUEST_PAGES_regs_errcode, lguest_pages, regs.errcode); OFFSET(LGUEST_PAGES_regs, lguest_pages, regs); #endif - - BLANK(); - OFFSET(BP_scratch, boot_params, scratch); - OFFSET(BP_loadflags, boot_params, hdr.loadflags); - OFFSET(BP_hardware_subarch, boot_params, hdr.hardware_subarch); - OFFSET(BP_version, boot_params, hdr.version); - OFFSET(BP_kernel_alignment, boot_params, hdr.kernel_alignment); } diff --git a/arch/x86/kernel/asm-offsets_64.c b/arch/x86/kernel/asm-offsets_64.c index 4a6aeedcd965..e72a1194af22 100644 --- a/arch/x86/kernel/asm-offsets_64.c +++ b/arch/x86/kernel/asm-offsets_64.c @@ -1,27 +1,4 @@ -/* - * Generate definitions needed by assembly language modules. - * This code generates raw asm output which is post-processed to extract - * and format the required data. - */ -#define COMPILE_OFFSETS - -#include <linux/crypto.h> -#include <linux/sched.h> -#include <linux/stddef.h> -#include <linux/errno.h> -#include <linux/hardirq.h> -#include <linux/suspend.h> -#include <linux/kbuild.h> -#include <asm/processor.h> -#include <asm/segment.h> -#include <asm/thread_info.h> #include <asm/ia32.h> -#include <asm/bootparam.h> -#include <asm/suspend.h> - -#include <xen/interface/xen.h> - -#include <asm/sigframe.h> #define __NO_STUBS 1 #undef __SYSCALL @@ -33,41 +10,19 @@ static char syscalls[] = { int main(void) { -#define ENTRY(entry) DEFINE(tsk_ ## entry, offsetof(struct task_struct, entry)) - ENTRY(state); - ENTRY(flags); - ENTRY(pid); - BLANK(); -#undef ENTRY -#define ENTRY(entry) DEFINE(TI_ ## entry, offsetof(struct thread_info, entry)) - ENTRY(flags); - ENTRY(addr_limit); - ENTRY(preempt_count); - ENTRY(status); -#ifdef CONFIG_IA32_EMULATION - ENTRY(sysenter_return); -#endif - BLANK(); -#undef ENTRY #ifdef CONFIG_PARAVIRT - BLANK(); - OFFSET(PARAVIRT_enabled, pv_info, paravirt_enabled); - OFFSET(PARAVIRT_PATCH_pv_cpu_ops, paravirt_patch_template, pv_cpu_ops); - OFFSET(PARAVIRT_PATCH_pv_irq_ops, paravirt_patch_template, pv_irq_ops); - OFFSET(PV_IRQ_irq_disable, pv_irq_ops, irq_disable); - OFFSET(PV_IRQ_irq_enable, pv_irq_ops, irq_enable); OFFSET(PV_IRQ_adjust_exception_frame, pv_irq_ops, adjust_exception_frame); - OFFSET(PV_CPU_iret, pv_cpu_ops, iret); OFFSET(PV_CPU_usergs_sysret32, pv_cpu_ops, usergs_sysret32); OFFSET(PV_CPU_usergs_sysret64, pv_cpu_ops, usergs_sysret64); - OFFSET(PV_CPU_irq_enable_sysexit, pv_cpu_ops, irq_enable_sysexit); OFFSET(PV_CPU_swapgs, pv_cpu_ops, swapgs); - OFFSET(PV_MMU_read_cr2, pv_mmu_ops, read_cr2); + BLANK(); #endif - #ifdef CONFIG_IA32_EMULATION -#define ENTRY(entry) DEFINE(IA32_SIGCONTEXT_ ## entry, offsetof(struct sigcontext_ia32, entry)) + OFFSET(TI_sysenter_return, thread_info, sysenter_return); + BLANK(); + +#define ENTRY(entry) OFFSET(IA32_SIGCONTEXT_ ## entry, sigcontext_ia32, entry) ENTRY(ax); ENTRY(bx); ENTRY(cx); @@ -79,15 +34,12 @@ int main(void) ENTRY(ip); BLANK(); #undef ENTRY - DEFINE(IA32_RT_SIGFRAME_sigcontext, - offsetof (struct rt_sigframe_ia32, uc.uc_mcontext)); + + OFFSET(IA32_RT_SIGFRAME_sigcontext, rt_sigframe_ia32, uc.uc_mcontext); BLANK(); #endif - DEFINE(pbe_address, offsetof(struct pbe, address)); - DEFINE(pbe_orig_address, offsetof(struct pbe, orig_address)); - DEFINE(pbe_next, offsetof(struct pbe, next)); - BLANK(); -#define ENTRY(entry) DEFINE(pt_regs_ ## entry, offsetof(struct pt_regs, entry)) + +#define ENTRY(entry) OFFSET(pt_regs_ ## entry, pt_regs, entry) ENTRY(bx); ENTRY(bx); ENTRY(cx); @@ -107,7 +59,8 @@ int main(void) ENTRY(flags); BLANK(); #undef ENTRY -#define ENTRY(entry) DEFINE(saved_context_ ## entry, offsetof(struct saved_context, entry)) + +#define ENTRY(entry) OFFSET(saved_context_ ## entry, saved_context, entry) ENTRY(cr0); ENTRY(cr2); ENTRY(cr3); @@ -115,26 +68,11 @@ int main(void) ENTRY(cr8); BLANK(); #undef ENTRY - DEFINE(TSS_ist, offsetof(struct tss_struct, x86_tss.ist)); - BLANK(); - DEFINE(crypto_tfm_ctx_offset, offsetof(struct crypto_tfm, __crt_ctx)); - BLANK(); - DEFINE(__NR_syscall_max, sizeof(syscalls) - 1); + OFFSET(TSS_ist, tss_struct, x86_tss.ist); BLANK(); - OFFSET(BP_scratch, boot_params, scratch); - OFFSET(BP_loadflags, boot_params, hdr.loadflags); - OFFSET(BP_hardware_subarch, boot_params, hdr.hardware_subarch); - OFFSET(BP_version, boot_params, hdr.version); - OFFSET(BP_kernel_alignment, boot_params, hdr.kernel_alignment); - BLANK(); - DEFINE(PAGE_SIZE_asm, PAGE_SIZE); -#ifdef CONFIG_XEN - BLANK(); - OFFSET(XEN_vcpu_info_mask, vcpu_info, evtchn_upcall_mask); - OFFSET(XEN_vcpu_info_pending, vcpu_info, evtchn_upcall_pending); -#undef ENTRY -#endif + DEFINE(__NR_syscall_max, sizeof(syscalls) - 1); + return 0; } diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 7c7bedb83c5a..3ecece0217ef 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -233,18 +233,22 @@ static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c) } #endif -#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) +#ifdef CONFIG_NUMA +/* + * To workaround broken NUMA config. Read the comment in + * srat_detect_node(). + */ static int __cpuinit nearby_node(int apicid) { int i, node; for (i = apicid - 1; i >= 0; i--) { - node = apicid_to_node[i]; + node = __apicid_to_node[i]; if (node != NUMA_NO_NODE && node_online(node)) return node; } for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { - node = apicid_to_node[i]; + node = __apicid_to_node[i]; if (node != NUMA_NO_NODE && node_online(node)) return node; } @@ -261,7 +265,7 @@ static int __cpuinit nearby_node(int apicid) #ifdef CONFIG_X86_HT static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) { - u32 nodes; + u32 nodes, cores_per_cu = 1; u8 node_id; int cpu = smp_processor_id(); @@ -276,6 +280,7 @@ static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) /* get compute unit information */ smp_num_siblings = ((ebx >> 8) & 3) + 1; c->compute_unit_id = ebx & 0xff; + cores_per_cu += ((ebx >> 8) & 3); } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { u64 value; @@ -288,15 +293,18 @@ static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) /* fixup multi-node processor information */ if (nodes > 1) { u32 cores_per_node; + u32 cus_per_node; set_cpu_cap(c, X86_FEATURE_AMD_DCM); cores_per_node = c->x86_max_cores / nodes; + cus_per_node = cores_per_node / cores_per_cu; /* store NodeID, use llc_shared_map to store sibling info */ per_cpu(cpu_llc_id, cpu) = node_id; - /* core id to be in range from 0 to (cores_per_node - 1) */ - c->cpu_core_id = c->cpu_core_id % cores_per_node; + /* core id has to be in the [0 .. cores_per_node - 1] range */ + c->cpu_core_id %= cores_per_node; + c->compute_unit_id %= cus_per_node; } } #endif @@ -334,31 +342,40 @@ EXPORT_SYMBOL_GPL(amd_get_nb_id); static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c) { -#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) +#ifdef CONFIG_NUMA int cpu = smp_processor_id(); int node; unsigned apicid = c->apicid; - node = per_cpu(cpu_llc_id, cpu); + node = numa_cpu_node(cpu); + if (node == NUMA_NO_NODE) + node = per_cpu(cpu_llc_id, cpu); - if (apicid_to_node[apicid] != NUMA_NO_NODE) - node = apicid_to_node[apicid]; if (!node_online(node)) { - /* Two possibilities here: - - The CPU is missing memory and no node was created. - In that case try picking one from a nearby CPU - - The APIC IDs differ from the HyperTransport node IDs - which the K8 northbridge parsing fills in. - Assume they are all increased by a constant offset, - but in the same order as the HT nodeids. - If that doesn't result in a usable node fall back to the - path for the previous case. */ - + /* + * Two possibilities here: + * + * - The CPU is missing memory and no node was created. In + * that case try picking one from a nearby CPU. + * + * - The APIC IDs differ from the HyperTransport node IDs + * which the K8 northbridge parsing fills in. Assume + * they are all increased by a constant offset, but in + * the same order as the HT nodeids. If that doesn't + * result in a usable node fall back to the path for the + * previous case. + * + * This workaround operates directly on the mapping between + * APIC ID and NUMA node, assuming certain relationship + * between APIC ID, HT node ID and NUMA topology. As going + * through CPU mapping may alter the outcome, directly + * access __apicid_to_node[]. + */ int ht_nodeid = c->initial_apicid; if (ht_nodeid >= 0 && - apicid_to_node[ht_nodeid] != NUMA_NO_NODE) - node = apicid_to_node[ht_nodeid]; + __apicid_to_node[ht_nodeid] != NUMA_NO_NODE) + node = __apicid_to_node[ht_nodeid]; /* Pick a nearby node */ if (!node_online(node)) node = nearby_node(apicid); @@ -594,6 +611,10 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) } } #endif + + /* As a rule processors have APIC timer running in deep C states */ + if (c->x86 >= 0xf && !cpu_has_amd_erratum(amd_erratum_400)) + set_cpu_cap(c, X86_FEATURE_ARAT); } #ifdef CONFIG_X86_32 diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 1d59834396bd..e2ced0074a45 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -675,7 +675,7 @@ void __init early_cpu_init(void) const struct cpu_dev *const *cdev; int count = 0; -#ifdef PROCESSOR_SELECT +#ifdef CONFIG_PROCESSOR_SELECT printk(KERN_INFO "KERNEL supported cpus:\n"); #endif @@ -687,7 +687,7 @@ void __init early_cpu_init(void) cpu_devs[count] = cpudev; count++; -#ifdef PROCESSOR_SELECT +#ifdef CONFIG_PROCESSOR_SELECT { unsigned int j; @@ -869,7 +869,7 @@ static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) select_idle_routine(c); -#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) +#ifdef CONFIG_NUMA numa_add_cpu(smp_processor_id()); #endif } diff --git a/arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c b/arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c index 4a5a42b842ad..755a31e0f5b0 100644 --- a/arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c +++ b/arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c @@ -315,8 +315,6 @@ static int __init pcc_cpufreq_do_osc(acpi_handle *handle) input.count = 4; input.pointer = in_params; - input.count = 4; - input.pointer = in_params; in_params[0].type = ACPI_TYPE_BUFFER; in_params[0].buffer.length = 16; in_params[0].buffer.pointer = OSC_UUID; diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c index c567dec854f6..1ae4133e6bd6 100644 --- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c +++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c @@ -630,8 +630,7 @@ static void print_basics(struct powernow_k8_data *data) data->powernow_table[j].frequency/1000); } else { printk(KERN_INFO PFX - " %d : fid 0x%x (%d MHz), vid 0x%x\n", - j, + "fid 0x%x (%d MHz), vid 0x%x\n", data->powernow_table[j].index & 0xff, data->powernow_table[j].frequency/1000, data->powernow_table[j].index >> 8); diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index d16c2c53d6bf..df86bc8c859d 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -276,14 +276,13 @@ static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c) { -#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) +#ifdef CONFIG_NUMA unsigned node; int cpu = smp_processor_id(); - int apicid = cpu_has_apic ? hard_smp_processor_id() : c->apicid; /* Don't do the funky fallback heuristics the AMD version employs for now. */ - node = apicid_to_node[apicid]; + node = numa_cpu_node(cpu); if (node == NUMA_NO_NODE || !node_online(node)) { /* reuse the value from init_cpu_to_node() */ node = cpu_to_node(cpu); diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index ec2c19a7b8ef..1ce1af2899df 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c @@ -304,8 +304,9 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax, struct _cache_attr { struct attribute attr; - ssize_t (*show)(struct _cpuid4_info *, char *); - ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count); + ssize_t (*show)(struct _cpuid4_info *, char *, unsigned int); + ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count, + unsigned int); }; #ifdef CONFIG_AMD_NB @@ -400,7 +401,8 @@ static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf, #define SHOW_CACHE_DISABLE(slot) \ static ssize_t \ -show_cache_disable_##slot(struct _cpuid4_info *this_leaf, char *buf) \ +show_cache_disable_##slot(struct _cpuid4_info *this_leaf, char *buf, \ + unsigned int cpu) \ { \ return show_cache_disable(this_leaf, buf, slot); \ } @@ -512,7 +514,8 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf, #define STORE_CACHE_DISABLE(slot) \ static ssize_t \ store_cache_disable_##slot(struct _cpuid4_info *this_leaf, \ - const char *buf, size_t count) \ + const char *buf, size_t count, \ + unsigned int cpu) \ { \ return store_cache_disable(this_leaf, buf, count, slot); \ } @@ -524,6 +527,39 @@ static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644, static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644, show_cache_disable_1, store_cache_disable_1); +static ssize_t +show_subcaches(struct _cpuid4_info *this_leaf, char *buf, unsigned int cpu) +{ + if (!this_leaf->l3 || !amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) + return -EINVAL; + + return sprintf(buf, "%x\n", amd_get_subcaches(cpu)); +} + +static ssize_t +store_subcaches(struct _cpuid4_info *this_leaf, const char *buf, size_t count, + unsigned int cpu) +{ + unsigned long val; + + if (!capable(CAP_SYS_ADMIN)) + return -EPERM; + + if (!this_leaf->l3 || !amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) + return -EINVAL; + + if (strict_strtoul(buf, 16, &val) < 0) + return -EINVAL; + + if (amd_set_subcaches(cpu, val)) + return -EINVAL; + + return count; +} + +static struct _cache_attr subcaches = + __ATTR(subcaches, 0644, show_subcaches, store_subcaches); + #else /* CONFIG_AMD_NB */ #define amd_init_l3_cache(x, y) #endif /* CONFIG_AMD_NB */ @@ -532,9 +568,9 @@ static int __cpuinit cpuid4_cache_lookup_regs(int index, struct _cpuid4_info_regs *this_leaf) { - union _cpuid4_leaf_eax eax; - union _cpuid4_leaf_ebx ebx; - union _cpuid4_leaf_ecx ecx; + union _cpuid4_leaf_eax eax; + union _cpuid4_leaf_ebx ebx; + union _cpuid4_leaf_ecx ecx; unsigned edx; if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { @@ -732,11 +768,11 @@ static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index) struct cpuinfo_x86 *c = &cpu_data(cpu); if ((index == 3) && (c->x86_vendor == X86_VENDOR_AMD)) { - for_each_cpu(i, c->llc_shared_map) { + for_each_cpu(i, cpu_llc_shared_mask(cpu)) { if (!per_cpu(ici_cpuid4_info, i)) continue; this_leaf = CPUID4_INFO_IDX(i, index); - for_each_cpu(sibling, c->llc_shared_map) { + for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) { if (!cpu_online(sibling)) continue; set_bit(sibling, this_leaf->shared_cpu_map); @@ -870,8 +906,8 @@ static DEFINE_PER_CPU(struct _index_kobject *, ici_index_kobject); #define INDEX_KOBJECT_PTR(x, y) (&((per_cpu(ici_index_kobject, x))[y])) #define show_one_plus(file_name, object, val) \ -static ssize_t show_##file_name \ - (struct _cpuid4_info *this_leaf, char *buf) \ +static ssize_t show_##file_name(struct _cpuid4_info *this_leaf, char *buf, \ + unsigned int cpu) \ { \ return sprintf(buf, "%lu\n", (unsigned long)this_leaf->object + val); \ } @@ -882,7 +918,8 @@ show_one_plus(physical_line_partition, ebx.split.physical_line_partition, 1); show_one_plus(ways_of_associativity, ebx.split.ways_of_associativity, 1); show_one_plus(number_of_sets, ecx.split.number_of_sets, 1); -static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf) +static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf, + unsigned int cpu) { return sprintf(buf, "%luK\n", this_leaf->size / 1024); } @@ -906,17 +943,20 @@ static ssize_t show_shared_cpu_map_func(struct _cpuid4_info *this_leaf, return n; } -static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf) +static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf, + unsigned int cpu) { return show_shared_cpu_map_func(leaf, 0, buf); } -static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf) +static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf, + unsigned int cpu) { return show_shared_cpu_map_func(leaf, 1, buf); } -static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf) +static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf, + unsigned int cpu) { switch (this_leaf->eax.split.type) { case CACHE_TYPE_DATA: @@ -974,6 +1014,9 @@ static struct attribute ** __cpuinit amd_l3_attrs(void) if (amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE)) n += 2; + if (amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) + n += 1; + attrs = kzalloc(n * sizeof (struct attribute *), GFP_KERNEL); if (attrs == NULL) return attrs = default_attrs; @@ -986,6 +1029,9 @@ static struct attribute ** __cpuinit amd_l3_attrs(void) attrs[n++] = &cache_disable_1.attr; } + if (amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) + attrs[n++] = &subcaches.attr; + return attrs; } #endif @@ -998,7 +1044,7 @@ static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) ret = fattr->show ? fattr->show(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index), - buf) : + buf, this_leaf->cpu) : 0; return ret; } @@ -1012,7 +1058,7 @@ static ssize_t store(struct kobject *kobj, struct attribute *attr, ret = fattr->store ? fattr->store(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index), - buf, count) : + buf, count, this_leaf->cpu) : 0; return ret; } diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index 5bf2fac52aca..167f97b5596e 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c @@ -527,15 +527,12 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank) int i, err = 0; struct threshold_bank *b = NULL; char name[32]; -#ifdef CONFIG_SMP - struct cpuinfo_x86 *c = &cpu_data(cpu); -#endif sprintf(name, "threshold_bank%i", bank); #ifdef CONFIG_SMP if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) { /* symlink */ - i = cpumask_first(c->llc_shared_map); + i = cpumask_first(cpu_llc_shared_mask(cpu)); /* first core not up yet */ if (cpu_data(i).cpu_core_id) @@ -555,7 +552,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank) if (err) goto out; - cpumask_copy(b->cpus, c->llc_shared_map); + cpumask_copy(b->cpus, cpu_llc_shared_mask(cpu)); per_cpu(threshold_banks, cpu)[bank] = b; goto out; diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index 9d977a2ea693..26604188aa49 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c @@ -30,6 +30,7 @@ #include <asm/stacktrace.h> #include <asm/nmi.h> #include <asm/compat.h> +#include <asm/smp.h> #if 0 #undef wrmsrl @@ -93,6 +94,8 @@ struct amd_nb { struct event_constraint event_constraints[X86_PMC_IDX_MAX]; }; +struct intel_percore; + #define MAX_LBR_ENTRIES 16 struct cpu_hw_events { @@ -128,6 +131,13 @@ struct cpu_hw_events { struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; /* + * Intel percore register state. + * Coordinate shared resources between HT threads. + */ + int percore_used; /* Used by this CPU? */ + struct intel_percore *per_core; + + /* * AMD specific bits */ struct amd_nb *amd_nb; @@ -166,8 +176,10 @@ struct cpu_hw_events { /* * Constraint on the Event code + UMask */ -#define PEBS_EVENT_CONSTRAINT(c, n) \ +#define INTEL_UEVENT_CONSTRAINT(c, n) \ EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) +#define PEBS_EVENT_CONSTRAINT(c, n) \ + INTEL_UEVENT_CONSTRAINT(c, n) #define EVENT_CONSTRAINT_END \ EVENT_CONSTRAINT(0, 0, 0) @@ -175,6 +187,28 @@ struct cpu_hw_events { #define for_each_event_constraint(e, c) \ for ((e) = (c); (e)->weight; (e)++) +/* + * Extra registers for specific events. + * Some events need large masks and require external MSRs. + * Define a mapping to these extra registers. + */ +struct extra_reg { + unsigned int event; + unsigned int msr; + u64 config_mask; + u64 valid_mask; +}; + +#define EVENT_EXTRA_REG(e, ms, m, vm) { \ + .event = (e), \ + .msr = (ms), \ + .config_mask = (m), \ + .valid_mask = (vm), \ + } +#define INTEL_EVENT_EXTRA_REG(event, msr, vm) \ + EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm) +#define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0) + union perf_capabilities { struct { u64 lbr_format : 6; @@ -219,6 +253,7 @@ struct x86_pmu { void (*put_event_constraints)(struct cpu_hw_events *cpuc, struct perf_event *event); struct event_constraint *event_constraints; + struct event_constraint *percore_constraints; void (*quirks)(void); int perfctr_second_write; @@ -247,6 +282,11 @@ struct x86_pmu { */ unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ int lbr_nr; /* hardware stack size */ + + /* + * Extra registers for events + */ + struct extra_reg *extra_regs; }; static struct x86_pmu x86_pmu __read_mostly; @@ -271,6 +311,10 @@ static u64 __read_mostly hw_cache_event_ids [PERF_COUNT_HW_CACHE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_RESULT_MAX]; +static u64 __read_mostly hw_cache_extra_regs + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX]; /* * Propagate event elapsed time into the generic event. @@ -298,7 +342,7 @@ x86_perf_event_update(struct perf_event *event) */ again: prev_raw_count = local64_read(&hwc->prev_count); - rdmsrl(hwc->event_base + idx, new_raw_count); + rdmsrl(hwc->event_base, new_raw_count); if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, new_raw_count) != prev_raw_count) @@ -321,6 +365,49 @@ again: return new_raw_count; } +/* using X86_FEATURE_PERFCTR_CORE to later implement ALTERNATIVE() here */ +static inline int x86_pmu_addr_offset(int index) +{ + if (boot_cpu_has(X86_FEATURE_PERFCTR_CORE)) + return index << 1; + return index; +} + +static inline unsigned int x86_pmu_config_addr(int index) +{ + return x86_pmu.eventsel + x86_pmu_addr_offset(index); +} + +static inline unsigned int x86_pmu_event_addr(int index) +{ + return x86_pmu.perfctr + x86_pmu_addr_offset(index); +} + +/* + * Find and validate any extra registers to set up. + */ +static int x86_pmu_extra_regs(u64 config, struct perf_event *event) +{ + struct extra_reg *er; + + event->hw.extra_reg = 0; + event->hw.extra_config = 0; + + if (!x86_pmu.extra_regs) + return 0; + + for (er = x86_pmu.extra_regs; er->msr; er++) { + if (er->event != (config & er->config_mask)) + continue; + if (event->attr.config1 & ~er->valid_mask) + return -EINVAL; + event->hw.extra_reg = er->msr; + event->hw.extra_config = event->attr.config1; + break; + } + return 0; +} + static atomic_t active_events; static DEFINE_MUTEX(pmc_reserve_mutex); @@ -331,12 +418,12 @@ static bool reserve_pmc_hardware(void) int i; for (i = 0; i < x86_pmu.num_counters; i++) { - if (!reserve_perfctr_nmi(x86_pmu.perfctr + i)) + if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) goto perfctr_fail; } for (i = 0; i < x86_pmu.num_counters; i++) { - if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) + if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) goto eventsel_fail; } @@ -344,13 +431,13 @@ static bool reserve_pmc_hardware(void) eventsel_fail: for (i--; i >= 0; i--) - release_evntsel_nmi(x86_pmu.eventsel + i); + release_evntsel_nmi(x86_pmu_config_addr(i)); i = x86_pmu.num_counters; perfctr_fail: for (i--; i >= 0; i--) - release_perfctr_nmi(x86_pmu.perfctr + i); + release_perfctr_nmi(x86_pmu_event_addr(i)); return false; } @@ -360,8 +447,8 @@ static void release_pmc_hardware(void) int i; for (i = 0; i < x86_pmu.num_counters; i++) { - release_perfctr_nmi(x86_pmu.perfctr + i); - release_evntsel_nmi(x86_pmu.eventsel + i); + release_perfctr_nmi(x86_pmu_event_addr(i)); + release_evntsel_nmi(x86_pmu_config_addr(i)); } } @@ -382,7 +469,7 @@ static bool check_hw_exists(void) * complain and bail. */ for (i = 0; i < x86_pmu.num_counters; i++) { - reg = x86_pmu.eventsel + i; + reg = x86_pmu_config_addr(i); ret = rdmsrl_safe(reg, &val); if (ret) goto msr_fail; @@ -407,8 +494,8 @@ static bool check_hw_exists(void) * that don't trap on the MSR access and always return 0s. */ val = 0xabcdUL; - ret = checking_wrmsrl(x86_pmu.perfctr, val); - ret |= rdmsrl_safe(x86_pmu.perfctr, &val_new); + ret = checking_wrmsrl(x86_pmu_event_addr(0), val); + ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new); if (ret || val != val_new) goto msr_fail; @@ -442,8 +529,9 @@ static inline int x86_pmu_initialized(void) } static inline int -set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr) +set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) { + struct perf_event_attr *attr = &event->attr; unsigned int cache_type, cache_op, cache_result; u64 config, val; @@ -470,8 +558,8 @@ set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr) return -EINVAL; hwc->config |= val; - - return 0; + attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; + return x86_pmu_extra_regs(val, event); } static int x86_setup_perfctr(struct perf_event *event) @@ -496,10 +584,10 @@ static int x86_setup_perfctr(struct perf_event *event) } if (attr->type == PERF_TYPE_RAW) - return 0; + return x86_pmu_extra_regs(event->attr.config, event); if (attr->type == PERF_TYPE_HW_CACHE) - return set_ext_hw_attr(hwc, attr); + return set_ext_hw_attr(hwc, event); if (attr->config >= x86_pmu.max_events) return -EINVAL; @@ -617,11 +705,11 @@ static void x86_pmu_disable_all(void) if (!test_bit(idx, cpuc->active_mask)) continue; - rdmsrl(x86_pmu.eventsel + idx, val); + rdmsrl(x86_pmu_config_addr(idx), val); if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) continue; val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; - wrmsrl(x86_pmu.eventsel + idx, val); + wrmsrl(x86_pmu_config_addr(idx), val); } } @@ -642,21 +730,26 @@ static void x86_pmu_disable(struct pmu *pmu) x86_pmu.disable_all(); } +static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, + u64 enable_mask) +{ + if (hwc->extra_reg) + wrmsrl(hwc->extra_reg, hwc->extra_config); + wrmsrl(hwc->config_base, hwc->config | enable_mask); +} + static void x86_pmu_enable_all(int added) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); int idx; for (idx = 0; idx < x86_pmu.num_counters; idx++) { - struct perf_event *event = cpuc->events[idx]; - u64 val; + struct hw_perf_event *hwc = &cpuc->events[idx]->hw; if (!test_bit(idx, cpuc->active_mask)) continue; - val = event->hw.config; - val |= ARCH_PERFMON_EVENTSEL_ENABLE; - wrmsrl(x86_pmu.eventsel + idx, val); + __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); } } @@ -821,15 +914,10 @@ static inline void x86_assign_hw_event(struct perf_event *event, hwc->event_base = 0; } else if (hwc->idx >= X86_PMC_IDX_FIXED) { hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; - /* - * We set it so that event_base + idx in wrmsr/rdmsr maps to - * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: - */ - hwc->event_base = - MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; + hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0; } else { - hwc->config_base = x86_pmu.eventsel; - hwc->event_base = x86_pmu.perfctr; + hwc->config_base = x86_pmu_config_addr(hwc->idx); + hwc->event_base = x86_pmu_event_addr(hwc->idx); } } @@ -915,17 +1003,11 @@ static void x86_pmu_enable(struct pmu *pmu) x86_pmu.enable_all(added); } -static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, - u64 enable_mask) -{ - wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask); -} - static inline void x86_pmu_disable_event(struct perf_event *event) { struct hw_perf_event *hwc = &event->hw; - wrmsrl(hwc->config_base + hwc->idx, hwc->config); + wrmsrl(hwc->config_base, hwc->config); } static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); @@ -978,7 +1060,7 @@ x86_perf_event_set_period(struct perf_event *event) */ local64_set(&hwc->prev_count, (u64)-left); - wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask); + wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); /* * Due to erratum on certan cpu we need @@ -986,7 +1068,7 @@ x86_perf_event_set_period(struct perf_event *event) * is updated properly */ if (x86_pmu.perfctr_second_write) { - wrmsrl(hwc->event_base + idx, + wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); } @@ -1113,8 +1195,8 @@ void perf_event_print_debug(void) pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); for (idx = 0; idx < x86_pmu.num_counters; idx++) { - rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl); - rdmsrl(x86_pmu.perfctr + idx, pmc_count); + rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); + rdmsrl(x86_pmu_event_addr(idx), pmc_count); prev_left = per_cpu(pmc_prev_left[idx], cpu); @@ -1389,7 +1471,7 @@ static void __init pmu_check_apic(void) pr_info("no hardware sampling interrupt available.\n"); } -int __init init_hw_perf_events(void) +static int __init init_hw_perf_events(void) { struct event_constraint *c; int err; @@ -1608,7 +1690,7 @@ out: return ret; } -int x86_pmu_event_init(struct perf_event *event) +static int x86_pmu_event_init(struct perf_event *event) { struct pmu *tmp; int err; diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c index 67e2202a6039..461f62bbd774 100644 --- a/arch/x86/kernel/cpu/perf_event_amd.c +++ b/arch/x86/kernel/cpu/perf_event_amd.c @@ -127,6 +127,11 @@ static int amd_pmu_hw_config(struct perf_event *event) /* * AMD64 events are detected based on their event codes. */ +static inline unsigned int amd_get_event_code(struct hw_perf_event *hwc) +{ + return ((hwc->config >> 24) & 0x0f00) | (hwc->config & 0x00ff); +} + static inline int amd_is_nb_event(struct hw_perf_event *hwc) { return (hwc->config & 0xe0) == 0xe0; @@ -385,13 +390,181 @@ static __initconst const struct x86_pmu amd_pmu = { .cpu_dead = amd_pmu_cpu_dead, }; +/* AMD Family 15h */ + +#define AMD_EVENT_TYPE_MASK 0x000000F0ULL + +#define AMD_EVENT_FP 0x00000000ULL ... 0x00000010ULL +#define AMD_EVENT_LS 0x00000020ULL ... 0x00000030ULL +#define AMD_EVENT_DC 0x00000040ULL ... 0x00000050ULL +#define AMD_EVENT_CU 0x00000060ULL ... 0x00000070ULL +#define AMD_EVENT_IC_DE 0x00000080ULL ... 0x00000090ULL +#define AMD_EVENT_EX_LS 0x000000C0ULL +#define AMD_EVENT_DE 0x000000D0ULL +#define AMD_EVENT_NB 0x000000E0ULL ... 0x000000F0ULL + +/* + * AMD family 15h event code/PMC mappings: + * + * type = event_code & 0x0F0: + * + * 0x000 FP PERF_CTL[5:3] + * 0x010 FP PERF_CTL[5:3] + * 0x020 LS PERF_CTL[5:0] + * 0x030 LS PERF_CTL[5:0] + * 0x040 DC PERF_CTL[5:0] + * 0x050 DC PERF_CTL[5:0] + * 0x060 CU PERF_CTL[2:0] + * 0x070 CU PERF_CTL[2:0] + * 0x080 IC/DE PERF_CTL[2:0] + * 0x090 IC/DE PERF_CTL[2:0] + * 0x0A0 --- + * 0x0B0 --- + * 0x0C0 EX/LS PERF_CTL[5:0] + * 0x0D0 DE PERF_CTL[2:0] + * 0x0E0 NB NB_PERF_CTL[3:0] + * 0x0F0 NB NB_PERF_CTL[3:0] + * + * Exceptions: + * + * 0x003 FP PERF_CTL[3] + * 0x00B FP PERF_CTL[3] + * 0x00D FP PERF_CTL[3] + * 0x023 DE PERF_CTL[2:0] + * 0x02D LS PERF_CTL[3] + * 0x02E LS PERF_CTL[3,0] + * 0x043 CU PERF_CTL[2:0] + * 0x045 CU PERF_CTL[2:0] + * 0x046 CU PERF_CTL[2:0] + * 0x054 CU PERF_CTL[2:0] + * 0x055 CU PERF_CTL[2:0] + * 0x08F IC PERF_CTL[0] + * 0x187 DE PERF_CTL[0] + * 0x188 DE PERF_CTL[0] + * 0x0DB EX PERF_CTL[5:0] + * 0x0DC LS PERF_CTL[5:0] + * 0x0DD LS PERF_CTL[5:0] + * 0x0DE LS PERF_CTL[5:0] + * 0x0DF LS PERF_CTL[5:0] + * 0x1D6 EX PERF_CTL[5:0] + * 0x1D8 EX PERF_CTL[5:0] + */ + +static struct event_constraint amd_f15_PMC0 = EVENT_CONSTRAINT(0, 0x01, 0); +static struct event_constraint amd_f15_PMC20 = EVENT_CONSTRAINT(0, 0x07, 0); +static struct event_constraint amd_f15_PMC3 = EVENT_CONSTRAINT(0, 0x08, 0); +static struct event_constraint amd_f15_PMC30 = EVENT_CONSTRAINT(0, 0x09, 0); +static struct event_constraint amd_f15_PMC50 = EVENT_CONSTRAINT(0, 0x3F, 0); +static struct event_constraint amd_f15_PMC53 = EVENT_CONSTRAINT(0, 0x38, 0); + +static struct event_constraint * +amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *event) +{ + unsigned int event_code = amd_get_event_code(&event->hw); + + switch (event_code & AMD_EVENT_TYPE_MASK) { + case AMD_EVENT_FP: + switch (event_code) { + case 0x003: + case 0x00B: + case 0x00D: + return &amd_f15_PMC3; + default: + return &amd_f15_PMC53; + } + case AMD_EVENT_LS: + case AMD_EVENT_DC: + case AMD_EVENT_EX_LS: + switch (event_code) { + case 0x023: + case 0x043: + case 0x045: + case 0x046: + case 0x054: + case 0x055: + return &amd_f15_PMC20; + case 0x02D: + return &amd_f15_PMC3; + case 0x02E: + return &amd_f15_PMC30; + default: + return &amd_f15_PMC50; + } + case AMD_EVENT_CU: + case AMD_EVENT_IC_DE: + case AMD_EVENT_DE: + switch (event_code) { + case 0x08F: + case 0x187: + case 0x188: + return &amd_f15_PMC0; + case 0x0DB ... 0x0DF: + case 0x1D6: + case 0x1D8: + return &amd_f15_PMC50; + default: + return &amd_f15_PMC20; + } + case AMD_EVENT_NB: + /* not yet implemented */ + return &emptyconstraint; + default: + return &emptyconstraint; + } +} + +static __initconst const struct x86_pmu amd_pmu_f15h = { + .name = "AMD Family 15h", + .handle_irq = x86_pmu_handle_irq, + .disable_all = x86_pmu_disable_all, + .enable_all = x86_pmu_enable_all, + .enable = x86_pmu_enable_event, + .disable = x86_pmu_disable_event, + .hw_config = amd_pmu_hw_config, + .schedule_events = x86_schedule_events, + .eventsel = MSR_F15H_PERF_CTL, + .perfctr = MSR_F15H_PERF_CTR, + .event_map = amd_pmu_event_map, + .max_events = ARRAY_SIZE(amd_perfmon_event_map), + .num_counters = 6, + .cntval_bits = 48, + .cntval_mask = (1ULL << 48) - 1, + .apic = 1, + /* use highest bit to detect overflow */ + .max_period = (1ULL << 47) - 1, + .get_event_constraints = amd_get_event_constraints_f15h, + /* nortbridge counters not yet implemented: */ +#if 0 + .put_event_constraints = amd_put_event_constraints, + + .cpu_prepare = amd_pmu_cpu_prepare, + .cpu_starting = amd_pmu_cpu_starting, + .cpu_dead = amd_pmu_cpu_dead, +#endif +}; + static __init int amd_pmu_init(void) { /* Performance-monitoring supported from K7 and later: */ if (boot_cpu_data.x86 < 6) return -ENODEV; - x86_pmu = amd_pmu; + /* + * If core performance counter extensions exists, it must be + * family 15h, otherwise fail. See x86_pmu_addr_offset(). + */ + switch (boot_cpu_data.x86) { + case 0x15: + if (!cpu_has_perfctr_core) + return -ENODEV; + x86_pmu = amd_pmu_f15h; + break; + default: + if (cpu_has_perfctr_core) + return -ENODEV; + x86_pmu = amd_pmu; + break; + } /* Events are common for all AMDs */ memcpy(hw_cache_event_ids, amd_hw_cache_event_ids, diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 008835c1d79c..8fc2b2cee1da 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -1,5 +1,27 @@ #ifdef CONFIG_CPU_SUP_INTEL +#define MAX_EXTRA_REGS 2 + +/* + * Per register state. + */ +struct er_account { + int ref; /* reference count */ + unsigned int extra_reg; /* extra MSR number */ + u64 extra_config; /* extra MSR config */ +}; + +/* + * Per core state + * This used to coordinate shared registers for HT threads. + */ +struct intel_percore { + raw_spinlock_t lock; /* protect structure */ + struct er_account regs[MAX_EXTRA_REGS]; + int refcnt; /* number of threads */ + unsigned core_id; +}; + /* * Intel PerfMon, used on Core and later. */ @@ -64,6 +86,18 @@ static struct event_constraint intel_nehalem_event_constraints[] = EVENT_CONSTRAINT_END }; +static struct extra_reg intel_nehalem_extra_regs[] = +{ + INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff), + EVENT_EXTRA_END +}; + +static struct event_constraint intel_nehalem_percore_constraints[] = +{ + INTEL_EVENT_CONSTRAINT(0xb7, 0), + EVENT_CONSTRAINT_END +}; + static struct event_constraint intel_westmere_event_constraints[] = { FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ @@ -76,6 +110,33 @@ static struct event_constraint intel_westmere_event_constraints[] = EVENT_CONSTRAINT_END }; +static struct event_constraint intel_snb_event_constraints[] = +{ + FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ + FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ + /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */ + INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ + INTEL_EVENT_CONSTRAINT(0xb7, 0x1), /* OFF_CORE_RESPONSE_0 */ + INTEL_EVENT_CONSTRAINT(0xbb, 0x8), /* OFF_CORE_RESPONSE_1 */ + INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ + INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ + EVENT_CONSTRAINT_END +}; + +static struct extra_reg intel_westmere_extra_regs[] = +{ + INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff), + INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff), + EVENT_EXTRA_END +}; + +static struct event_constraint intel_westmere_percore_constraints[] = +{ + INTEL_EVENT_CONSTRAINT(0xb7, 0), + INTEL_EVENT_CONSTRAINT(0xbb, 0), + EVENT_CONSTRAINT_END +}; + static struct event_constraint intel_gen_event_constraints[] = { FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ @@ -89,6 +150,106 @@ static u64 intel_pmu_event_map(int hw_event) return intel_perfmon_event_map[hw_event]; } +static __initconst const u64 snb_hw_cache_event_ids + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = +{ + [ C(L1D) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ + [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ + [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = 0x0, + [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ + }, + }, + [ C(L1I ) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0x0, + [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = 0x0, + [ C(RESULT_MISS) ] = 0x0, + }, + }, + [ C(LL ) ] = { + /* + * TBD: Need Off-core Response Performance Monitoring support + */ + [ C(OP_READ) ] = { + /* OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE */ + [ C(RESULT_ACCESS) ] = 0x01b7, + /* OFFCORE_RESPONSE_1.ANY_DATA.ANY_LLC_MISS */ + [ C(RESULT_MISS) ] = 0x01bb, + }, + [ C(OP_WRITE) ] = { + /* OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE */ + [ C(RESULT_ACCESS) ] = 0x01b7, + /* OFFCORE_RESPONSE_1.ANY_RFO.ANY_LLC_MISS */ + [ C(RESULT_MISS) ] = 0x01bb, + }, + [ C(OP_PREFETCH) ] = { + /* OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE */ + [ C(RESULT_ACCESS) ] = 0x01b7, + /* OFFCORE_RESPONSE_1.PREFETCH.ANY_LLC_MISS */ + [ C(RESULT_MISS) ] = 0x01bb, + }, + }, + [ C(DTLB) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ + [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ + [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = 0x0, + [ C(RESULT_MISS) ] = 0x0, + }, + }, + [ C(ITLB) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ + [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + }, + [ C(BPU ) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ + [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + }, +}; + static __initconst const u64 westmere_hw_cache_event_ids [PERF_COUNT_HW_CACHE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] @@ -124,16 +285,26 @@ static __initconst const u64 westmere_hw_cache_event_ids }, [ C(LL ) ] = { [ C(OP_READ) ] = { - [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */ - [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */ + /* OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE */ + [ C(RESULT_ACCESS) ] = 0x01b7, + /* OFFCORE_RESPONSE_1.ANY_DATA.ANY_LLC_MISS */ + [ C(RESULT_MISS) ] = 0x01bb, }, + /* + * Use RFO, not WRITEBACK, because a write miss would typically occur + * on RFO. + */ [ C(OP_WRITE) ] = { - [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */ - [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */ + /* OFFCORE_RESPONSE_1.ANY_RFO.LOCAL_CACHE */ + [ C(RESULT_ACCESS) ] = 0x01bb, + /* OFFCORE_RESPONSE_0.ANY_RFO.ANY_LLC_MISS */ + [ C(RESULT_MISS) ] = 0x01b7, }, [ C(OP_PREFETCH) ] = { - [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */ - [ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */ + /* OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE */ + [ C(RESULT_ACCESS) ] = 0x01b7, + /* OFFCORE_RESPONSE_1.PREFETCH.ANY_LLC_MISS */ + [ C(RESULT_MISS) ] = 0x01bb, }, }, [ C(DTLB) ] = { @@ -180,6 +351,39 @@ static __initconst const u64 westmere_hw_cache_event_ids }, }; +/* + * OFFCORE_RESPONSE MSR bits (subset), See IA32 SDM Vol 3 30.6.1.3 + */ + +#define DMND_DATA_RD (1 << 0) +#define DMND_RFO (1 << 1) +#define DMND_WB (1 << 3) +#define PF_DATA_RD (1 << 4) +#define PF_DATA_RFO (1 << 5) +#define RESP_UNCORE_HIT (1 << 8) +#define RESP_MISS (0xf600) /* non uncore hit */ + +static __initconst const u64 nehalem_hw_cache_extra_regs + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = +{ + [ C(LL ) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = DMND_DATA_RD|RESP_UNCORE_HIT, + [ C(RESULT_MISS) ] = DMND_DATA_RD|RESP_MISS, + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = DMND_RFO|DMND_WB|RESP_UNCORE_HIT, + [ C(RESULT_MISS) ] = DMND_RFO|DMND_WB|RESP_MISS, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = PF_DATA_RD|PF_DATA_RFO|RESP_UNCORE_HIT, + [ C(RESULT_MISS) ] = PF_DATA_RD|PF_DATA_RFO|RESP_MISS, + }, + } +}; + static __initconst const u64 nehalem_hw_cache_event_ids [PERF_COUNT_HW_CACHE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] @@ -215,16 +419,26 @@ static __initconst const u64 nehalem_hw_cache_event_ids }, [ C(LL ) ] = { [ C(OP_READ) ] = { - [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */ - [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */ + /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ + [ C(RESULT_ACCESS) ] = 0x01b7, + /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ + [ C(RESULT_MISS) ] = 0x01b7, }, + /* + * Use RFO, not WRITEBACK, because a write miss would typically occur + * on RFO. + */ [ C(OP_WRITE) ] = { - [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */ - [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */ + /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ + [ C(RESULT_ACCESS) ] = 0x01b7, + /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ + [ C(RESULT_MISS) ] = 0x01b7, }, [ C(OP_PREFETCH) ] = { - [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */ - [ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */ + /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ + [ C(RESULT_ACCESS) ] = 0x01b7, + /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ + [ C(RESULT_MISS) ] = 0x01b7, }, }, [ C(DTLB) ] = { @@ -691,8 +905,8 @@ static void intel_pmu_reset(void) printk("clearing PMU state on CPU#%d\n", smp_processor_id()); for (idx = 0; idx < x86_pmu.num_counters; idx++) { - checking_wrmsrl(x86_pmu.eventsel + idx, 0ull); - checking_wrmsrl(x86_pmu.perfctr + idx, 0ull); + checking_wrmsrl(x86_pmu_config_addr(idx), 0ull); + checking_wrmsrl(x86_pmu_event_addr(idx), 0ull); } for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); @@ -794,6 +1008,67 @@ intel_bts_constraints(struct perf_event *event) } static struct event_constraint * +intel_percore_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) +{ + struct hw_perf_event *hwc = &event->hw; + unsigned int e = hwc->config & ARCH_PERFMON_EVENTSEL_EVENT; + struct event_constraint *c; + struct intel_percore *pc; + struct er_account *era; + int i; + int free_slot; + int found; + + if (!x86_pmu.percore_constraints || hwc->extra_alloc) + return NULL; + + for (c = x86_pmu.percore_constraints; c->cmask; c++) { + if (e != c->code) + continue; + + /* + * Allocate resource per core. + */ + pc = cpuc->per_core; + if (!pc) + break; + c = &emptyconstraint; + raw_spin_lock(&pc->lock); + free_slot = -1; + found = 0; + for (i = 0; i < MAX_EXTRA_REGS; i++) { + era = &pc->regs[i]; + if (era->ref > 0 && hwc->extra_reg == era->extra_reg) { + /* Allow sharing same config */ + if (hwc->extra_config == era->extra_config) { + era->ref++; + cpuc->percore_used = 1; + hwc->extra_alloc = 1; + c = NULL; + } + /* else conflict */ + found = 1; + break; + } else if (era->ref == 0 && free_slot == -1) + free_slot = i; + } + if (!found && free_slot != -1) { + era = &pc->regs[free_slot]; + era->ref = 1; + era->extra_reg = hwc->extra_reg; + era->extra_config = hwc->extra_config; + cpuc->percore_used = 1; + hwc->extra_alloc = 1; + c = NULL; + } + raw_spin_unlock(&pc->lock); + return c; + } + + return NULL; +} + +static struct event_constraint * intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) { struct event_constraint *c; @@ -806,9 +1081,51 @@ intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event if (c) return c; + c = intel_percore_constraints(cpuc, event); + if (c) + return c; + return x86_get_event_constraints(cpuc, event); } +static void intel_put_event_constraints(struct cpu_hw_events *cpuc, + struct perf_event *event) +{ + struct extra_reg *er; + struct intel_percore *pc; + struct er_account *era; + struct hw_perf_event *hwc = &event->hw; + int i, allref; + + if (!cpuc->percore_used) + return; + + for (er = x86_pmu.extra_regs; er->msr; er++) { + if (er->event != (hwc->config & er->config_mask)) + continue; + + pc = cpuc->per_core; + raw_spin_lock(&pc->lock); + for (i = 0; i < MAX_EXTRA_REGS; i++) { + era = &pc->regs[i]; + if (era->ref > 0 && + era->extra_config == hwc->extra_config && + era->extra_reg == er->msr) { + era->ref--; + hwc->extra_alloc = 0; + break; + } + } + allref = 0; + for (i = 0; i < MAX_EXTRA_REGS; i++) + allref += pc->regs[i].ref; + if (allref == 0) + cpuc->percore_used = 0; + raw_spin_unlock(&pc->lock); + break; + } +} + static int intel_pmu_hw_config(struct perf_event *event) { int ret = x86_pmu_hw_config(event); @@ -880,20 +1197,67 @@ static __initconst const struct x86_pmu core_pmu = { */ .max_period = (1ULL << 31) - 1, .get_event_constraints = intel_get_event_constraints, + .put_event_constraints = intel_put_event_constraints, .event_constraints = intel_core_event_constraints, }; +static int intel_pmu_cpu_prepare(int cpu) +{ + struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); + + if (!cpu_has_ht_siblings()) + return NOTIFY_OK; + + cpuc->per_core = kzalloc_node(sizeof(struct intel_percore), + GFP_KERNEL, cpu_to_node(cpu)); + if (!cpuc->per_core) + return NOTIFY_BAD; + + raw_spin_lock_init(&cpuc->per_core->lock); + cpuc->per_core->core_id = -1; + return NOTIFY_OK; +} + static void intel_pmu_cpu_starting(int cpu) { + struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); + int core_id = topology_core_id(cpu); + int i; + init_debug_store_on_cpu(cpu); /* * Deal with CPUs that don't clear their LBRs on power-up. */ intel_pmu_lbr_reset(); + + if (!cpu_has_ht_siblings()) + return; + + for_each_cpu(i, topology_thread_cpumask(cpu)) { + struct intel_percore *pc = per_cpu(cpu_hw_events, i).per_core; + + if (pc && pc->core_id == core_id) { + kfree(cpuc->per_core); + cpuc->per_core = pc; + break; + } + } + + cpuc->per_core->core_id = core_id; + cpuc->per_core->refcnt++; } static void intel_pmu_cpu_dying(int cpu) { + struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); + struct intel_percore *pc = cpuc->per_core; + + if (pc) { + if (pc->core_id == -1 || --pc->refcnt == 0) + kfree(pc); + cpuc->per_core = NULL; + } + fini_debug_store_on_cpu(cpu); } @@ -918,7 +1282,9 @@ static __initconst const struct x86_pmu intel_pmu = { */ .max_period = (1ULL << 31) - 1, .get_event_constraints = intel_get_event_constraints, + .put_event_constraints = intel_put_event_constraints, + .cpu_prepare = intel_pmu_cpu_prepare, .cpu_starting = intel_pmu_cpu_starting, .cpu_dying = intel_pmu_cpu_dying, }; @@ -1024,6 +1390,7 @@ static __init int intel_pmu_init(void) intel_pmu_lbr_init_core(); x86_pmu.event_constraints = intel_core2_event_constraints; + x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; pr_cont("Core2 events, "); break; @@ -1032,11 +1399,16 @@ static __init int intel_pmu_init(void) case 46: /* 45 nm nehalem-ex, "Beckton" */ memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, sizeof(hw_cache_event_ids)); + memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, + sizeof(hw_cache_extra_regs)); intel_pmu_lbr_init_nhm(); x86_pmu.event_constraints = intel_nehalem_event_constraints; + x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; + x86_pmu.percore_constraints = intel_nehalem_percore_constraints; x86_pmu.enable_all = intel_pmu_nhm_enable_all; + x86_pmu.extra_regs = intel_nehalem_extra_regs; pr_cont("Nehalem events, "); break; @@ -1047,6 +1419,7 @@ static __init int intel_pmu_init(void) intel_pmu_lbr_init_atom(); x86_pmu.event_constraints = intel_gen_event_constraints; + x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; pr_cont("Atom events, "); break; @@ -1054,14 +1427,30 @@ static __init int intel_pmu_init(void) case 44: /* 32 nm nehalem, "Gulftown" */ memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, sizeof(hw_cache_event_ids)); + memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, + sizeof(hw_cache_extra_regs)); intel_pmu_lbr_init_nhm(); x86_pmu.event_constraints = intel_westmere_event_constraints; + x86_pmu.percore_constraints = intel_westmere_percore_constraints; x86_pmu.enable_all = intel_pmu_nhm_enable_all; + x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; + x86_pmu.extra_regs = intel_westmere_extra_regs; pr_cont("Westmere events, "); break; + case 42: /* SandyBridge */ + memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, + sizeof(hw_cache_event_ids)); + + intel_pmu_lbr_init_nhm(); + + x86_pmu.event_constraints = intel_snb_event_constraints; + x86_pmu.pebs_constraints = intel_snb_pebs_events; + pr_cont("SandyBridge events, "); + break; + default: /* * default constraints for v2 and up diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c index b7dcd9f2b8a0..b95c66ae4a2a 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c @@ -361,30 +361,88 @@ static int intel_pmu_drain_bts_buffer(void) /* * PEBS */ - -static struct event_constraint intel_core_pebs_events[] = { - PEBS_EVENT_CONSTRAINT(0x00c0, 0x1), /* INSTR_RETIRED.ANY */ +static struct event_constraint intel_core2_pebs_event_constraints[] = { + PEBS_EVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */ PEBS_EVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */ PEBS_EVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */ PEBS_EVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */ - PEBS_EVENT_CONSTRAINT(0x01cb, 0x1), /* MEM_LOAD_RETIRED.L1D_MISS */ - PEBS_EVENT_CONSTRAINT(0x02cb, 0x1), /* MEM_LOAD_RETIRED.L1D_LINE_MISS */ - PEBS_EVENT_CONSTRAINT(0x04cb, 0x1), /* MEM_LOAD_RETIRED.L2_MISS */ - PEBS_EVENT_CONSTRAINT(0x08cb, 0x1), /* MEM_LOAD_RETIRED.L2_LINE_MISS */ - PEBS_EVENT_CONSTRAINT(0x10cb, 0x1), /* MEM_LOAD_RETIRED.DTLB_MISS */ + INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */ + EVENT_CONSTRAINT_END +}; + +static struct event_constraint intel_atom_pebs_event_constraints[] = { + PEBS_EVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */ + PEBS_EVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */ + INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */ EVENT_CONSTRAINT_END }; -static struct event_constraint intel_nehalem_pebs_events[] = { - PEBS_EVENT_CONSTRAINT(0x00c0, 0xf), /* INSTR_RETIRED.ANY */ - PEBS_EVENT_CONSTRAINT(0xfec1, 0xf), /* X87_OPS_RETIRED.ANY */ - PEBS_EVENT_CONSTRAINT(0x00c5, 0xf), /* BR_INST_RETIRED.MISPRED */ - PEBS_EVENT_CONSTRAINT(0x1fc7, 0xf), /* SIMD_INST_RETURED.ANY */ - PEBS_EVENT_CONSTRAINT(0x01cb, 0xf), /* MEM_LOAD_RETIRED.L1D_MISS */ - PEBS_EVENT_CONSTRAINT(0x02cb, 0xf), /* MEM_LOAD_RETIRED.L1D_LINE_MISS */ - PEBS_EVENT_CONSTRAINT(0x04cb, 0xf), /* MEM_LOAD_RETIRED.L2_MISS */ - PEBS_EVENT_CONSTRAINT(0x08cb, 0xf), /* MEM_LOAD_RETIRED.L2_LINE_MISS */ - PEBS_EVENT_CONSTRAINT(0x10cb, 0xf), /* MEM_LOAD_RETIRED.DTLB_MISS */ +static struct event_constraint intel_nehalem_pebs_event_constraints[] = { + INTEL_EVENT_CONSTRAINT(0x0b, 0xf), /* MEM_INST_RETIRED.* */ + INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */ + PEBS_EVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */ + INTEL_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */ + INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */ + INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */ + PEBS_EVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */ + INTEL_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */ + PEBS_EVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */ + INTEL_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */ + INTEL_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */ + EVENT_CONSTRAINT_END +}; + +static struct event_constraint intel_westmere_pebs_event_constraints[] = { + INTEL_EVENT_CONSTRAINT(0x0b, 0xf), /* MEM_INST_RETIRED.* */ + INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */ + PEBS_EVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */ + INTEL_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */ + INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */ + + INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */ + INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */ + INTEL_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */ + PEBS_EVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */ + INTEL_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */ + INTEL_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */ + EVENT_CONSTRAINT_END +}; + +static struct event_constraint intel_snb_pebs_events[] = { + PEBS_EVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ + PEBS_EVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */ + PEBS_EVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */ + PEBS_EVENT_CONSTRAINT(0x01c4, 0xf), /* BR_INST_RETIRED.CONDITIONAL */ + PEBS_EVENT_CONSTRAINT(0x02c4, 0xf), /* BR_INST_RETIRED.NEAR_CALL */ + PEBS_EVENT_CONSTRAINT(0x04c4, 0xf), /* BR_INST_RETIRED.ALL_BRANCHES */ + PEBS_EVENT_CONSTRAINT(0x08c4, 0xf), /* BR_INST_RETIRED.NEAR_RETURN */ + PEBS_EVENT_CONSTRAINT(0x10c4, 0xf), /* BR_INST_RETIRED.NOT_TAKEN */ + PEBS_EVENT_CONSTRAINT(0x20c4, 0xf), /* BR_INST_RETIRED.NEAR_TAKEN */ + PEBS_EVENT_CONSTRAINT(0x40c4, 0xf), /* BR_INST_RETIRED.FAR_BRANCH */ + PEBS_EVENT_CONSTRAINT(0x01c5, 0xf), /* BR_MISP_RETIRED.CONDITIONAL */ + PEBS_EVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */ + PEBS_EVENT_CONSTRAINT(0x04c5, 0xf), /* BR_MISP_RETIRED.ALL_BRANCHES */ + PEBS_EVENT_CONSTRAINT(0x10c5, 0xf), /* BR_MISP_RETIRED.NOT_TAKEN */ + PEBS_EVENT_CONSTRAINT(0x20c5, 0xf), /* BR_MISP_RETIRED.TAKEN */ + PEBS_EVENT_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ + PEBS_EVENT_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORE */ + PEBS_EVENT_CONSTRAINT(0x11d0, 0xf), /* MEM_UOP_RETIRED.STLB_MISS_LOADS */ + PEBS_EVENT_CONSTRAINT(0x12d0, 0xf), /* MEM_UOP_RETIRED.STLB_MISS_STORES */ + PEBS_EVENT_CONSTRAINT(0x21d0, 0xf), /* MEM_UOP_RETIRED.LOCK_LOADS */ + PEBS_EVENT_CONSTRAINT(0x22d0, 0xf), /* MEM_UOP_RETIRED.LOCK_STORES */ + PEBS_EVENT_CONSTRAINT(0x41d0, 0xf), /* MEM_UOP_RETIRED.SPLIT_LOADS */ + PEBS_EVENT_CONSTRAINT(0x42d0, 0xf), /* MEM_UOP_RETIRED.SPLIT_STORES */ + PEBS_EVENT_CONSTRAINT(0x81d0, 0xf), /* MEM_UOP_RETIRED.ANY_LOADS */ + PEBS_EVENT_CONSTRAINT(0x82d0, 0xf), /* MEM_UOP_RETIRED.ANY_STORES */ + PEBS_EVENT_CONSTRAINT(0x01d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L1_HIT */ + PEBS_EVENT_CONSTRAINT(0x02d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L2_HIT */ + PEBS_EVENT_CONSTRAINT(0x04d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.LLC_HIT */ + PEBS_EVENT_CONSTRAINT(0x40d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.HIT_LFB */ + PEBS_EVENT_CONSTRAINT(0x01d2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS */ + PEBS_EVENT_CONSTRAINT(0x02d2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT */ + PEBS_EVENT_CONSTRAINT(0x04d2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM */ + PEBS_EVENT_CONSTRAINT(0x08d2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE */ + PEBS_EVENT_CONSTRAINT(0x02d4, 0xf), /* MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS */ EVENT_CONSTRAINT_END }; @@ -695,20 +753,17 @@ static void intel_ds_init(void) printk(KERN_CONT "PEBS fmt0%c, ", pebs_type); x86_pmu.pebs_record_size = sizeof(struct pebs_record_core); x86_pmu.drain_pebs = intel_pmu_drain_pebs_core; - x86_pmu.pebs_constraints = intel_core_pebs_events; break; case 1: printk(KERN_CONT "PEBS fmt1%c, ", pebs_type); x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm); x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; - x86_pmu.pebs_constraints = intel_nehalem_pebs_events; break; default: printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type); x86_pmu.pebs = 0; - break; } } } diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c index ff751a9f182b..3769ac822f96 100644 --- a/arch/x86/kernel/cpu/perf_event_p4.c +++ b/arch/x86/kernel/cpu/perf_event_p4.c @@ -764,9 +764,9 @@ static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc) u64 v; /* an official way for overflow indication */ - rdmsrl(hwc->config_base + hwc->idx, v); + rdmsrl(hwc->config_base, v); if (v & P4_CCCR_OVF) { - wrmsrl(hwc->config_base + hwc->idx, v & ~P4_CCCR_OVF); + wrmsrl(hwc->config_base, v & ~P4_CCCR_OVF); return 1; } @@ -815,7 +815,7 @@ static inline void p4_pmu_disable_event(struct perf_event *event) * state we need to clear P4_CCCR_OVF, otherwise interrupt get * asserted again and again */ - (void)checking_wrmsrl(hwc->config_base + hwc->idx, + (void)checking_wrmsrl(hwc->config_base, (u64)(p4_config_unpack_cccr(hwc->config)) & ~P4_CCCR_ENABLE & ~P4_CCCR_OVF & ~P4_CCCR_RESERVED); } @@ -885,7 +885,7 @@ static void p4_pmu_enable_event(struct perf_event *event) p4_pmu_enable_pebs(hwc->config); (void)checking_wrmsrl(escr_addr, escr_conf); - (void)checking_wrmsrl(hwc->config_base + hwc->idx, + (void)checking_wrmsrl(hwc->config_base, (cccr & ~P4_CCCR_RESERVED) | P4_CCCR_ENABLE); } diff --git a/arch/x86/kernel/cpu/perf_event_p6.c b/arch/x86/kernel/cpu/perf_event_p6.c index 34ba07be2cda..20c097e33860 100644 --- a/arch/x86/kernel/cpu/perf_event_p6.c +++ b/arch/x86/kernel/cpu/perf_event_p6.c @@ -68,7 +68,7 @@ p6_pmu_disable_event(struct perf_event *event) if (cpuc->enabled) val |= ARCH_PERFMON_EVENTSEL_ENABLE; - (void)checking_wrmsrl(hwc->config_base + hwc->idx, val); + (void)checking_wrmsrl(hwc->config_base, val); } static void p6_pmu_enable_event(struct perf_event *event) @@ -81,7 +81,7 @@ static void p6_pmu_enable_event(struct perf_event *event) if (cpuc->enabled) val |= ARCH_PERFMON_EVENTSEL_ENABLE; - (void)checking_wrmsrl(hwc->config_base + hwc->idx, val); + (void)checking_wrmsrl(hwc->config_base, val); } static __initconst const struct x86_pmu p6_pmu = { diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c index d5a236615501..966512b2cacf 100644 --- a/arch/x86/kernel/cpu/perfctr-watchdog.c +++ b/arch/x86/kernel/cpu/perfctr-watchdog.c @@ -46,6 +46,8 @@ static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr) /* returns the bit offset of the performance counter register */ switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_AMD: + if (msr >= MSR_F15H_PERF_CTR) + return (msr - MSR_F15H_PERF_CTR) >> 1; return msr - MSR_K7_PERFCTR0; case X86_VENDOR_INTEL: if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) @@ -70,6 +72,8 @@ static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr) /* returns the bit offset of the event selection register */ switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_AMD: + if (msr >= MSR_F15H_PERF_CTL) + return (msr - MSR_F15H_PERF_CTL) >> 1; return msr - MSR_K7_EVNTSEL0; case X86_VENDOR_INTEL: if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c new file mode 100644 index 000000000000..7a8cebc9ff29 --- /dev/null +++ b/arch/x86/kernel/devicetree.c @@ -0,0 +1,441 @@ +/* + * Architecture specific OF callbacks. + */ +#include <linux/bootmem.h> +#include <linux/io.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/of.h> +#include <linux/of_fdt.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> +#include <linux/of_irq.h> +#include <linux/slab.h> +#include <linux/pci.h> +#include <linux/of_pci.h> + +#include <asm/hpet.h> +#include <asm/irq_controller.h> +#include <asm/apic.h> +#include <asm/pci_x86.h> + +__initdata u64 initial_dtb; +char __initdata cmd_line[COMMAND_LINE_SIZE]; +static LIST_HEAD(irq_domains); +static DEFINE_RAW_SPINLOCK(big_irq_lock); + +int __initdata of_ioapic; + +#ifdef CONFIG_X86_IO_APIC +static void add_interrupt_host(struct irq_domain *ih) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&big_irq_lock, flags); + list_add(&ih->l, &irq_domains); + raw_spin_unlock_irqrestore(&big_irq_lock, flags); +} +#endif + +static struct irq_domain *get_ih_from_node(struct device_node *controller) +{ + struct irq_domain *ih, *found = NULL; + unsigned long flags; + + raw_spin_lock_irqsave(&big_irq_lock, flags); + list_for_each_entry(ih, &irq_domains, l) { + if (ih->controller == controller) { + found = ih; + break; + } + } + raw_spin_unlock_irqrestore(&big_irq_lock, flags); + return found; +} + +unsigned int irq_create_of_mapping(struct device_node *controller, + const u32 *intspec, unsigned int intsize) +{ + struct irq_domain *ih; + u32 virq, type; + int ret; + + ih = get_ih_from_node(controller); + if (!ih) + return 0; + ret = ih->xlate(ih, intspec, intsize, &virq, &type); + if (ret) + return ret; + if (type == IRQ_TYPE_NONE) + return virq; + /* set the mask if it is different from current */ + if (type == (irq_to_desc(virq)->status & IRQF_TRIGGER_MASK)) + set_irq_type(virq, type); + return virq; +} +EXPORT_SYMBOL_GPL(irq_create_of_mapping); + +unsigned long pci_address_to_pio(phys_addr_t address) +{ + /* + * The ioport address can be directly used by inX / outX + */ + BUG_ON(address >= (1 << 16)); + return (unsigned long)address; +} +EXPORT_SYMBOL_GPL(pci_address_to_pio); + +void __init early_init_dt_scan_chosen_arch(unsigned long node) +{ + BUG(); +} + +void __init early_init_dt_add_memory_arch(u64 base, u64 size) +{ + BUG(); +} + +void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) +{ + return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS)); +} + +void __init add_dtb(u64 data) +{ + initial_dtb = data + offsetof(struct setup_data, data); +} + +/* + * CE4100 ids. Will be moved to machine_device_initcall() once we have it. + */ +static struct of_device_id __initdata ce4100_ids[] = { + { .compatible = "intel,ce4100-cp", }, + { .compatible = "isa", }, + { .compatible = "pci", }, + {}, +}; + +static int __init add_bus_probe(void) +{ + if (!of_have_populated_dt()) + return 0; + + return of_platform_bus_probe(NULL, ce4100_ids, NULL); +} +module_init(add_bus_probe); + +#ifdef CONFIG_PCI +static int x86_of_pci_irq_enable(struct pci_dev *dev) +{ + struct of_irq oirq; + u32 virq; + int ret; + u8 pin; + + ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); + if (ret) + return ret; + if (!pin) + return 0; + + ret = of_irq_map_pci(dev, &oirq); + if (ret) + return ret; + + virq = irq_create_of_mapping(oirq.controller, oirq.specifier, + oirq.size); + if (virq == 0) + return -EINVAL; + dev->irq = virq; + return 0; +} + +static void x86_of_pci_irq_disable(struct pci_dev *dev) +{ +} + +void __cpuinit x86_of_pci_init(void) +{ + struct device_node *np; + + pcibios_enable_irq = x86_of_pci_irq_enable; + pcibios_disable_irq = x86_of_pci_irq_disable; + + for_each_node_by_type(np, "pci") { + const void *prop; + struct pci_bus *bus; + unsigned int bus_min; + struct device_node *child; + + prop = of_get_property(np, "bus-range", NULL); + if (!prop) + continue; + bus_min = be32_to_cpup(prop); + + bus = pci_find_bus(0, bus_min); + if (!bus) { + printk(KERN_ERR "Can't find a node for bus %s.\n", + np->full_name); + continue; + } + + if (bus->self) + bus->self->dev.of_node = np; + else + bus->dev.of_node = np; + + for_each_child_of_node(np, child) { + struct pci_dev *dev; + u32 devfn; + + prop = of_get_property(child, "reg", NULL); + if (!prop) + continue; + + devfn = (be32_to_cpup(prop) >> 8) & 0xff; + dev = pci_get_slot(bus, devfn); + if (!dev) + continue; + dev->dev.of_node = child; + pci_dev_put(dev); + } + } +} +#endif + +static void __init dtb_setup_hpet(void) +{ +#ifdef CONFIG_HPET_TIMER + struct device_node *dn; + struct resource r; + int ret; + + dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet"); + if (!dn) + return; + ret = of_address_to_resource(dn, 0, &r); + if (ret) { + WARN_ON(1); + return; + } + hpet_address = r.start; +#endif +} + +static void __init dtb_lapic_setup(void) +{ +#ifdef CONFIG_X86_LOCAL_APIC + struct device_node *dn; + struct resource r; + int ret; + + dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic"); + if (!dn) + return; + + ret = of_address_to_resource(dn, 0, &r); + if (WARN_ON(ret)) + return; + + /* Did the boot loader setup the local APIC ? */ + if (!cpu_has_apic) { + if (apic_force_enable(r.start)) + return; + } + smp_found_config = 1; + pic_mode = 1; + register_lapic_address(r.start); + generic_processor_info(boot_cpu_physical_apicid, + GET_APIC_VERSION(apic_read(APIC_LVR))); +#endif +} + +#ifdef CONFIG_X86_IO_APIC +static unsigned int ioapic_id; + +static void __init dtb_add_ioapic(struct device_node *dn) +{ + struct resource r; + int ret; + + ret = of_address_to_resource(dn, 0, &r); + if (ret) { + printk(KERN_ERR "Can't obtain address from node %s.\n", + dn->full_name); + return; + } + mp_register_ioapic(++ioapic_id, r.start, gsi_top); +} + +static void __init dtb_ioapic_setup(void) +{ + struct device_node *dn; + + for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic") + dtb_add_ioapic(dn); + + if (nr_ioapics) { + of_ioapic = 1; + return; + } + printk(KERN_ERR "Error: No information about IO-APIC in OF.\n"); +} +#else +static void __init dtb_ioapic_setup(void) {} +#endif + +static void __init dtb_apic_setup(void) +{ + dtb_lapic_setup(); + dtb_ioapic_setup(); +} + +#ifdef CONFIG_OF_FLATTREE +static void __init x86_flattree_get_config(void) +{ + u32 size, map_len; + void *new_dtb; + + if (!initial_dtb) + return; + + map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), + (u64)sizeof(struct boot_param_header)); + + initial_boot_params = early_memremap(initial_dtb, map_len); + size = be32_to_cpu(initial_boot_params->totalsize); + if (map_len < size) { + early_iounmap(initial_boot_params, map_len); + initial_boot_params = early_memremap(initial_dtb, size); + map_len = size; + } + + new_dtb = alloc_bootmem(size); + memcpy(new_dtb, initial_boot_params, size); + early_iounmap(initial_boot_params, map_len); + + initial_boot_params = new_dtb; + + /* root level address cells */ + of_scan_flat_dt(early_init_dt_scan_root, NULL); + + unflatten_device_tree(); +} +#else +static inline void x86_flattree_get_config(void) { } +#endif + +void __init x86_dtb_init(void) +{ + x86_flattree_get_config(); + + if (!of_have_populated_dt()) + return; + + dtb_setup_hpet(); + dtb_apic_setup(); +} + +#ifdef CONFIG_X86_IO_APIC + +struct of_ioapic_type { + u32 out_type; + u32 trigger; + u32 polarity; +}; + +static struct of_ioapic_type of_ioapic_type[] = +{ + { + .out_type = IRQ_TYPE_EDGE_RISING, + .trigger = IOAPIC_EDGE, + .polarity = 1, + }, + { + .out_type = IRQ_TYPE_LEVEL_LOW, + .trigger = IOAPIC_LEVEL, + .polarity = 0, + }, + { + .out_type = IRQ_TYPE_LEVEL_HIGH, + .trigger = IOAPIC_LEVEL, + .polarity = 1, + }, + { + .out_type = IRQ_TYPE_EDGE_FALLING, + .trigger = IOAPIC_EDGE, + .polarity = 0, + }, +}; + +static int ioapic_xlate(struct irq_domain *id, const u32 *intspec, u32 intsize, + u32 *out_hwirq, u32 *out_type) +{ + struct io_apic_irq_attr attr; + struct of_ioapic_type *it; + u32 line, idx, type; + + if (intsize < 2) + return -EINVAL; + + line = *intspec; + idx = (u32) id->priv; + *out_hwirq = line + mp_gsi_routing[idx].gsi_base; + + intspec++; + type = *intspec; + + if (type >= ARRAY_SIZE(of_ioapic_type)) + return -EINVAL; + + it = of_ioapic_type + type; + *out_type = it->out_type; + + set_io_apic_irq_attr(&attr, idx, line, it->trigger, it->polarity); + + return io_apic_setup_irq_pin(*out_hwirq, cpu_to_node(0), &attr); +} + +static void __init ioapic_add_ofnode(struct device_node *np) +{ + struct resource r; + int i, ret; + + ret = of_address_to_resource(np, 0, &r); + if (ret) { + printk(KERN_ERR "Failed to obtain address for %s\n", + np->full_name); + return; + } + + for (i = 0; i < nr_ioapics; i++) { + if (r.start == mp_ioapics[i].apicaddr) { + struct irq_domain *id; + + id = kzalloc(sizeof(*id), GFP_KERNEL); + BUG_ON(!id); + id->controller = np; + id->xlate = ioapic_xlate; + id->priv = (void *)i; + add_interrupt_host(id); + return; + } + } + printk(KERN_ERR "IOxAPIC at %s is not registered.\n", np->full_name); +} + +void __init x86_add_irq_domains(void) +{ + struct device_node *dp; + + if (!of_have_populated_dt()) + return; + + for_each_node_with_property(dp, "interrupt-controller") { + if (of_device_is_compatible(dp, "intel,ce4100-ioapic")) + ioapic_add_ofnode(dp); + } +} +#else +void __init x86_add_irq_domains(void) { } +#endif diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c index df20723a6a1b..220a1c11cfde 100644 --- a/arch/x86/kernel/dumpstack.c +++ b/arch/x86/kernel/dumpstack.c @@ -320,31 +320,6 @@ void die(const char *str, struct pt_regs *regs, long err) oops_end(flags, regs, sig); } -void notrace __kprobes -die_nmi(char *str, struct pt_regs *regs, int do_panic) -{ - unsigned long flags; - - if (notify_die(DIE_NMIWATCHDOG, str, regs, 0, 2, SIGINT) == NOTIFY_STOP) - return; - - /* - * We are in trouble anyway, lets at least try - * to get a message out. - */ - flags = oops_begin(); - printk(KERN_EMERG "%s", str); - printk(" on CPU%d, ip %08lx, registers:\n", - smp_processor_id(), regs->ip); - show_registers(regs); - oops_end(flags, regs, 0); - if (do_panic || panic_on_oops) - panic("Non maskable interrupt"); - nmi_exit(); - local_irq_enable(); - do_exit(SIGBUS); -} - static int __init oops_setup(char *s) { if (!s) diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c index 294f26da0c0c..cdf5bfd9d4d5 100644 --- a/arch/x86/kernel/e820.c +++ b/arch/x86/kernel/e820.c @@ -667,21 +667,15 @@ __init void e820_setup_gap(void) * boot_params.e820_map, others are passed via SETUP_E820_EXT node of * linked list of struct setup_data, which is parsed here. */ -void __init parse_e820_ext(struct setup_data *sdata, unsigned long pa_data) +void __init parse_e820_ext(struct setup_data *sdata) { - u32 map_len; int entries; struct e820entry *extmap; entries = sdata->len / sizeof(struct e820entry); - map_len = sdata->len + sizeof(struct setup_data); - if (map_len > PAGE_SIZE) - sdata = early_ioremap(pa_data, map_len); extmap = (struct e820entry *)(sdata->data); __append_e820_map(extmap, entries); sanitize_e820_map(e820.map, ARRAY_SIZE(e820.map), &e820.nr_map); - if (map_len > PAGE_SIZE) - early_iounmap(sdata, map_len); printk(KERN_INFO "extended physical RAM map:\n"); e820_print_map("extended"); } @@ -847,15 +841,21 @@ static int __init parse_memopt(char *p) if (!p) return -EINVAL; -#ifdef CONFIG_X86_32 if (!strcmp(p, "nopentium")) { +#ifdef CONFIG_X86_32 setup_clear_cpu_cap(X86_FEATURE_PSE); return 0; - } +#else + printk(KERN_WARNING "mem=nopentium ignored! (only supported on x86_32)\n"); + return -EINVAL; #endif + } userdef = 1; mem_size = memparse(p, &p); + /* don't remove all of memory when handling "mem={invalid}" param */ + if (mem_size == 0) + return -EINVAL; e820_remove_range(mem_size, ULLONG_MAX - mem_size, E820_RAM, 1); return 0; diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index 9efbdcc56425..3755ef494390 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -159,7 +159,12 @@ static void __init ati_bugs_contd(int num, int slot, int func) if (rev >= 0x40) acpi_fix_pin2_polarity = 1; - if (rev > 0x13) + /* + * SB600: revisions 0x11, 0x12, 0x13, 0x14, ... + * SB700: revisions 0x39, 0x3a, ... + * SB800: revisions 0x40, 0x41, ... + */ + if (rev >= 0x39) return; if (acpi_use_timer_override) diff --git a/arch/x86/kernel/entry_32.S b/arch/x86/kernel/entry_32.S index c8b4efad7ebb..5c1a91974918 100644 --- a/arch/x86/kernel/entry_32.S +++ b/arch/x86/kernel/entry_32.S @@ -65,6 +65,8 @@ #define sysexit_audit syscall_exit_work #endif + .section .entry.text, "ax" + /* * We use macros for low-level operations which need to be overridden * for paravirtualization. The following will never clobber any registers: @@ -395,7 +397,7 @@ sysenter_past_esp: * A tiny bit of offset fixup is necessary - 4*4 means the 4 words * pushed above; +8 corresponds to copy_thread's esp0 setting. */ - pushl_cfi ((TI_sysenter_return)-THREAD_SIZE_asm+8+4*4)(%esp) + pushl_cfi ((TI_sysenter_return)-THREAD_SIZE+8+4*4)(%esp) CFI_REL_OFFSET eip, 0 pushl_cfi %eax @@ -788,7 +790,7 @@ ENDPROC(ptregs_clone) */ .section .init.rodata,"a" ENTRY(interrupt) -.text +.section .entry.text, "ax" .p2align 5 .p2align CONFIG_X86_L1_CACHE_SHIFT ENTRY(irq_entries_start) @@ -807,7 +809,7 @@ vector=FIRST_EXTERNAL_VECTOR .endif .previous .long 1b - .text + .section .entry.text, "ax" vector=vector+1 .endif .endr @@ -1409,11 +1411,10 @@ END(general_protection) #ifdef CONFIG_KVM_GUEST ENTRY(async_page_fault) RING0_EC_FRAME - pushl $do_async_page_fault - CFI_ADJUST_CFA_OFFSET 4 + pushl_cfi $do_async_page_fault jmp error_code CFI_ENDPROC -END(apf_page_fault) +END(async_page_fault) #endif /* diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S index aed1ffbeb0c9..b72b4a6466a9 100644 --- a/arch/x86/kernel/entry_64.S +++ b/arch/x86/kernel/entry_64.S @@ -61,6 +61,8 @@ #define __AUDIT_ARCH_LE 0x40000000 .code64 + .section .entry.text, "ax" + #ifdef CONFIG_FUNCTION_TRACER #ifdef CONFIG_DYNAMIC_FTRACE ENTRY(mcount) @@ -744,7 +746,7 @@ END(stub_rt_sigreturn) */ .section .init.rodata,"a" ENTRY(interrupt) - .text + .section .entry.text .p2align 5 .p2align CONFIG_X86_L1_CACHE_SHIFT ENTRY(irq_entries_start) @@ -763,7 +765,7 @@ vector=FIRST_EXTERNAL_VECTOR .endif .previous .quad 1b - .text + .section .entry.text vector=vector+1 .endif .endr @@ -975,9 +977,12 @@ apicinterrupt X86_PLATFORM_IPI_VECTOR \ x86_platform_ipi smp_x86_platform_ipi #ifdef CONFIG_SMP -.irpc idx, "01234567" +.irp idx,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15, \ + 16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 +.if NUM_INVALIDATE_TLB_VECTORS > \idx apicinterrupt (INVALIDATE_TLB_VECTOR_START)+\idx \ invalidate_interrupt\idx smp_invalidate_interrupt +.endif .endr #endif @@ -1248,7 +1253,7 @@ ENTRY(xen_do_hypervisor_callback) # do_hypervisor_callback(struct *pt_regs) decl PER_CPU_VAR(irq_count) jmp error_exit CFI_ENDPROC -END(do_hypervisor_callback) +END(xen_do_hypervisor_callback) /* * Hypervisor uses this for application faults while it executes. diff --git a/arch/x86/kernel/ftrace.c b/arch/x86/kernel/ftrace.c index 382eb2936d4d..a93742a57468 100644 --- a/arch/x86/kernel/ftrace.c +++ b/arch/x86/kernel/ftrace.c @@ -437,18 +437,19 @@ void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr, return; } - if (ftrace_push_return_trace(old, self_addr, &trace.depth, - frame_pointer) == -EBUSY) { - *parent = old; - return; - } - trace.func = self_addr; + trace.depth = current->curr_ret_stack + 1; /* Only trace if the calling function expects to */ if (!ftrace_graph_entry(&trace)) { - current->curr_ret_stack--; *parent = old; + return; + } + + if (ftrace_push_return_trace(old, self_addr, &trace.depth, + frame_pointer) == -EBUSY) { + *parent = old; + return; } } #endif /* CONFIG_FUNCTION_GRAPH_TRACER */ diff --git a/arch/x86/kernel/head32.c b/arch/x86/kernel/head32.c index 7f138b3c3c52..d6d6bb361931 100644 --- a/arch/x86/kernel/head32.c +++ b/arch/x86/kernel/head32.c @@ -34,15 +34,6 @@ void __init i386_start_kernel(void) { memblock_init(); -#ifdef CONFIG_X86_TRAMPOLINE - /* - * But first pinch a few for the stack/trampoline stuff - * FIXME: Don't need the extra page at 4K, but need to fix - * trampoline before removing it. (see the GDT stuff) - */ - memblock_x86_reserve_range(PAGE_SIZE, PAGE_SIZE + PAGE_SIZE, "EX TRAMPOLINE"); -#endif - memblock_x86_reserve_range(__pa_symbol(&_text), __pa_symbol(&__bss_stop), "TEXT DATA BSS"); #ifdef CONFIG_BLK_DEV_INITRD diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S index 767d6c43de37..ce0be7cd085e 100644 --- a/arch/x86/kernel/head_32.S +++ b/arch/x86/kernel/head_32.S @@ -73,7 +73,7 @@ MAPPING_BEYOND_END = PAGE_TABLE_SIZE(LOWMEM_PAGES) << PAGE_SHIFT */ KERNEL_PAGES = LOWMEM_PAGES -INIT_MAP_SIZE = PAGE_TABLE_SIZE(KERNEL_PAGES) * PAGE_SIZE_asm +INIT_MAP_SIZE = PAGE_TABLE_SIZE(KERNEL_PAGES) * PAGE_SIZE RESERVE_BRK(pagetables, INIT_MAP_SIZE) /* @@ -137,7 +137,7 @@ ENTRY(startup_32) movsl 1: -#ifdef CONFIG_OLPC_OPENFIRMWARE +#ifdef CONFIG_OLPC /* save OFW's pgdir table for later use when calling into OFW */ movl %cr3, %eax movl %eax, pa(olpc_ofw_pgd) @@ -623,7 +623,7 @@ ENTRY(initial_code) * BSS section */ __PAGE_ALIGNED_BSS - .align PAGE_SIZE_asm + .align PAGE_SIZE #ifdef CONFIG_X86_PAE initial_pg_pmd: .fill 1024*KPMDS,4,0 @@ -644,7 +644,7 @@ ENTRY(swapper_pg_dir) #ifdef CONFIG_X86_PAE __PAGE_ALIGNED_DATA /* Page-aligned for the benefit of paravirt? */ - .align PAGE_SIZE_asm + .align PAGE_SIZE ENTRY(initial_page_table) .long pa(initial_pg_pmd+PGD_IDENT_ATTR),0 /* low identity map */ # if KPMDS == 3 @@ -662,7 +662,7 @@ ENTRY(initial_page_table) # else # error "Kernel PMDs should be 1, 2 or 3" # endif - .align PAGE_SIZE_asm /* needs to be page-sized too */ + .align PAGE_SIZE /* needs to be page-sized too */ #endif .data diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 239046bd447f..e11e39478a49 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -136,10 +136,9 @@ ident_complete: /* Fixup phys_base */ addq %rbp, phys_base(%rip) -#ifdef CONFIG_X86_TRAMPOLINE + /* Fixup trampoline */ addq %rbp, trampoline_level4_pgt + 0(%rip) addq %rbp, trampoline_level4_pgt + (511*8)(%rip) -#endif /* Due to ENTRY(), sometimes the empty space gets filled with * zeros. Better take a jmp than relying on empty space being diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c index 4ff5968f12d2..bfe8f729e086 100644 --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c @@ -503,7 +503,7 @@ static int hpet_assign_irq(struct hpet_dev *dev) if (!irq) return -EINVAL; - set_irq_data(irq, dev); + irq_set_handler_data(irq, dev); if (hpet_setup_msi_irq(irq)) return -EINVAL; diff --git a/arch/x86/kernel/i8259.c b/arch/x86/kernel/i8259.c index 20757cb2efa3..d9ca749c123b 100644 --- a/arch/x86/kernel/i8259.c +++ b/arch/x86/kernel/i8259.c @@ -112,7 +112,7 @@ static void make_8259A_irq(unsigned int irq) { disable_irq_nosync(irq); io_apic_irqs &= ~(1<<irq); - set_irq_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq, + irq_set_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq, i8259A_chip.name); enable_irq(irq); } diff --git a/arch/x86/kernel/ioport.c b/arch/x86/kernel/ioport.c index 8eec0ec59af2..8c968974253d 100644 --- a/arch/x86/kernel/ioport.c +++ b/arch/x86/kernel/ioport.c @@ -14,22 +14,9 @@ #include <linux/slab.h> #include <linux/thread_info.h> #include <linux/syscalls.h> +#include <linux/bitmap.h> #include <asm/syscalls.h> -/* Set EXTENT bits starting at BASE in BITMAP to value TURN_ON. */ -static void set_bitmap(unsigned long *bitmap, unsigned int base, - unsigned int extent, int new_value) -{ - unsigned int i; - - for (i = base; i < base + extent; i++) { - if (new_value) - __set_bit(i, bitmap); - else - __clear_bit(i, bitmap); - } -} - /* * this changes the io permissions bitmap in the current task. */ @@ -69,7 +56,10 @@ asmlinkage long sys_ioperm(unsigned long from, unsigned long num, int turn_on) */ tss = &per_cpu(init_tss, get_cpu()); - set_bitmap(t->io_bitmap_ptr, from, num, !turn_on); + if (turn_on) + bitmap_clear(t->io_bitmap_ptr, from, num); + else + bitmap_set(t->io_bitmap_ptr, from, num); /* * Search for a (possibly new) maximum. This is simple and stupid, diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c index 387b6a0c9e81..948a31eae75f 100644 --- a/arch/x86/kernel/irq.c +++ b/arch/x86/kernel/irq.c @@ -44,9 +44,9 @@ void ack_bad_irq(unsigned int irq) #define irq_stats(x) (&per_cpu(irq_stat, x)) /* - * /proc/interrupts printing: + * /proc/interrupts printing for arch specific interrupts */ -static int show_other_interrupts(struct seq_file *p, int prec) +int arch_show_interrupts(struct seq_file *p, int prec) { int j; @@ -122,59 +122,6 @@ static int show_other_interrupts(struct seq_file *p, int prec) return 0; } -int show_interrupts(struct seq_file *p, void *v) -{ - unsigned long flags, any_count = 0; - int i = *(loff_t *) v, j, prec; - struct irqaction *action; - struct irq_desc *desc; - - if (i > nr_irqs) - return 0; - - for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec) - j *= 10; - - if (i == nr_irqs) - return show_other_interrupts(p, prec); - - /* print header */ - if (i == 0) { - seq_printf(p, "%*s", prec + 8, ""); - for_each_online_cpu(j) - seq_printf(p, "CPU%-8d", j); - seq_putc(p, '\n'); - } - - desc = irq_to_desc(i); - if (!desc) - return 0; - - raw_spin_lock_irqsave(&desc->lock, flags); - for_each_online_cpu(j) - any_count |= kstat_irqs_cpu(i, j); - action = desc->action; - if (!action && !any_count) - goto out; - - seq_printf(p, "%*d: ", prec, i); - for_each_online_cpu(j) - seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); - seq_printf(p, " %8s", desc->irq_data.chip->name); - seq_printf(p, "-%-8s", desc->name); - - if (action) { - seq_printf(p, " %s", action->name); - while ((action = action->next) != NULL) - seq_printf(p, ", %s", action->name); - } - - seq_putc(p, '\n'); -out: - raw_spin_unlock_irqrestore(&desc->lock, flags); - return 0; -} - /* * /proc/stat helpers */ @@ -276,15 +223,6 @@ void smp_x86_platform_ipi(struct pt_regs *regs) EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq); -#ifdef CONFIG_OF -unsigned int irq_create_of_mapping(struct device_node *controller, - const u32 *intspec, unsigned int intsize) -{ - return intspec[0]; -} -EXPORT_SYMBOL_GPL(irq_create_of_mapping); -#endif - #ifdef CONFIG_HOTPLUG_CPU /* A cpu has been removed from cpu_online_mask. Reset irq affinities. */ void fixup_irqs(void) @@ -293,6 +231,7 @@ void fixup_irqs(void) static int warned; struct irq_desc *desc; struct irq_data *data; + struct irq_chip *chip; for_each_irq_desc(irq, desc) { int break_affinity = 0; @@ -307,10 +246,10 @@ void fixup_irqs(void) /* interrupt's are disabled at this point */ raw_spin_lock(&desc->lock); - data = &desc->irq_data; + data = irq_desc_get_irq_data(desc); affinity = data->affinity; if (!irq_has_action(irq) || - cpumask_equal(affinity, cpu_online_mask)) { + cpumask_subset(affinity, cpu_online_mask)) { raw_spin_unlock(&desc->lock); continue; } @@ -327,16 +266,17 @@ void fixup_irqs(void) affinity = cpu_all_mask; } - if (!(desc->status & IRQ_MOVE_PCNTXT) && data->chip->irq_mask) - data->chip->irq_mask(data); + chip = irq_data_get_irq_chip(data); + if (!irqd_can_move_in_process_context(data) && chip->irq_mask) + chip->irq_mask(data); - if (data->chip->irq_set_affinity) - data->chip->irq_set_affinity(data, affinity, true); + if (chip->irq_set_affinity) + chip->irq_set_affinity(data, affinity, true); else if (!(warned++)) set_affinity = 0; - if (!(desc->status & IRQ_MOVE_PCNTXT) && data->chip->irq_unmask) - data->chip->irq_unmask(data); + if (!irqd_can_move_in_process_context(data) && chip->irq_unmask) + chip->irq_unmask(data); raw_spin_unlock(&desc->lock); @@ -368,10 +308,11 @@ void fixup_irqs(void) irq = __this_cpu_read(vector_irq[vector]); desc = irq_to_desc(irq); - data = &desc->irq_data; + data = irq_desc_get_irq_data(desc); + chip = irq_data_get_irq_chip(data); raw_spin_lock(&desc->lock); - if (data->chip->irq_retrigger) - data->chip->irq_retrigger(data); + if (chip->irq_retrigger) + chip->irq_retrigger(data); raw_spin_unlock(&desc->lock); } } diff --git a/arch/x86/kernel/irqinit.c b/arch/x86/kernel/irqinit.c index c752e973958d..f470e4ef993e 100644 --- a/arch/x86/kernel/irqinit.c +++ b/arch/x86/kernel/irqinit.c @@ -25,6 +25,7 @@ #include <asm/setup.h> #include <asm/i8259.h> #include <asm/traps.h> +#include <asm/prom.h> /* * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts: @@ -71,6 +72,7 @@ static irqreturn_t math_error_irq(int cpl, void *dev_id) static struct irqaction fpu_irq = { .handler = math_error_irq, .name = "fpu", + .flags = IRQF_NO_THREAD, }; #endif @@ -80,6 +82,7 @@ static struct irqaction fpu_irq = { static struct irqaction irq2 = { .handler = no_action, .name = "cascade", + .flags = IRQF_NO_THREAD, }; DEFINE_PER_CPU(vector_irq_t, vector_irq) = { @@ -110,7 +113,7 @@ void __init init_ISA_irqs(void) legacy_pic->init(0); for (i = 0; i < legacy_pic->nr_legacy_irqs; i++) - set_irq_chip_and_handler_name(i, chip, handle_level_irq, name); + irq_set_chip_and_handler_name(i, chip, handle_level_irq, name); } void __init init_IRQ(void) @@ -118,6 +121,12 @@ void __init init_IRQ(void) int i; /* + * We probably need a better place for this, but it works for + * now ... + */ + x86_add_irq_domains(); + + /* * On cpu 0, Assign IRQ0_VECTOR..IRQ15_VECTOR's to IRQ 0..15. * If these IRQ's are handled by legacy interrupt-controllers like PIC, * then this configuration will likely be static after the boot. If @@ -164,14 +173,77 @@ static void __init smp_intr_init(void) alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt); /* IPIs for invalidation */ - alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0); - alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1); - alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2); - alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3); - alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4); - alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5); - alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6); - alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7); +#define ALLOC_INVTLB_VEC(NR) \ + alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+NR, \ + invalidate_interrupt##NR) + + switch (NUM_INVALIDATE_TLB_VECTORS) { + default: + ALLOC_INVTLB_VEC(31); + case 31: + ALLOC_INVTLB_VEC(30); + case 30: + ALLOC_INVTLB_VEC(29); + case 29: + ALLOC_INVTLB_VEC(28); + case 28: + ALLOC_INVTLB_VEC(27); + case 27: + ALLOC_INVTLB_VEC(26); + case 26: + ALLOC_INVTLB_VEC(25); + case 25: + ALLOC_INVTLB_VEC(24); + case 24: + ALLOC_INVTLB_VEC(23); + case 23: + ALLOC_INVTLB_VEC(22); + case 22: + ALLOC_INVTLB_VEC(21); + case 21: + ALLOC_INVTLB_VEC(20); + case 20: + ALLOC_INVTLB_VEC(19); + case 19: + ALLOC_INVTLB_VEC(18); + case 18: + ALLOC_INVTLB_VEC(17); + case 17: + ALLOC_INVTLB_VEC(16); + case 16: + ALLOC_INVTLB_VEC(15); + case 15: + ALLOC_INVTLB_VEC(14); + case 14: + ALLOC_INVTLB_VEC(13); + case 13: + ALLOC_INVTLB_VEC(12); + case 12: + ALLOC_INVTLB_VEC(11); + case 11: + ALLOC_INVTLB_VEC(10); + case 10: + ALLOC_INVTLB_VEC(9); + case 9: + ALLOC_INVTLB_VEC(8); + case 8: + ALLOC_INVTLB_VEC(7); + case 7: + ALLOC_INVTLB_VEC(6); + case 6: + ALLOC_INVTLB_VEC(5); + case 5: + ALLOC_INVTLB_VEC(4); + case 4: + ALLOC_INVTLB_VEC(3); + case 3: + ALLOC_INVTLB_VEC(2); + case 2: + ALLOC_INVTLB_VEC(1); + case 1: + ALLOC_INVTLB_VEC(0); + break; + } /* IPI for generic function call */ alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt); @@ -243,7 +315,7 @@ void __init native_init_IRQ(void) set_intr_gate(i, interrupt[i-FIRST_EXTERNAL_VECTOR]); } - if (!acpi_ioapic) + if (!acpi_ioapic && !of_ioapic) setup_irq(2, &irq2); #ifdef CONFIG_X86_32 diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c index a4130005028a..7c64c420a9f6 100644 --- a/arch/x86/kernel/kgdb.c +++ b/arch/x86/kernel/kgdb.c @@ -533,15 +533,6 @@ static int __kgdb_notify(struct die_args *args, unsigned long cmd) } return NOTIFY_DONE; - case DIE_NMIWATCHDOG: - if (atomic_read(&kgdb_active) != -1) { - /* KGDB CPU roundup: */ - kgdb_nmicallback(raw_smp_processor_id(), regs); - return NOTIFY_STOP; - } - /* Enter debugger: */ - break; - case DIE_DEBUG: if (atomic_read(&kgdb_cpu_doing_single_step) != -1) { if (user_mode(regs)) diff --git a/arch/x86/kernel/kprobes.c b/arch/x86/kernel/kprobes.c index d91c477b3f62..c969fd9d1566 100644 --- a/arch/x86/kernel/kprobes.c +++ b/arch/x86/kernel/kprobes.c @@ -1276,6 +1276,14 @@ static int __kprobes can_optimize(unsigned long paddr) if (!kallsyms_lookup_size_offset(paddr, &size, &offset)) return 0; + /* + * Do not optimize in the entry code due to the unstable + * stack handling. + */ + if ((paddr >= (unsigned long )__entry_text_start) && + (paddr < (unsigned long )__entry_text_end)) + return 0; + /* Check there is enough space for a relative jump. */ if (size - offset < RELATIVEJUMP_SIZE) return 0; diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c index 0fe6d1a66c38..c5610384ab16 100644 --- a/arch/x86/kernel/microcode_amd.c +++ b/arch/x86/kernel/microcode_amd.c @@ -66,7 +66,6 @@ struct microcode_amd { unsigned int mpb[0]; }; -#define UCODE_MAX_SIZE 2048 #define UCODE_CONTAINER_SECTION_HDR 8 #define UCODE_CONTAINER_HEADER_SIZE 12 @@ -77,20 +76,20 @@ static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig) struct cpuinfo_x86 *c = &cpu_data(cpu); u32 dummy; - memset(csig, 0, sizeof(*csig)); if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) { - pr_warning("microcode: CPU%d: AMD CPU family 0x%x not " - "supported\n", cpu, c->x86); + pr_warning("CPU%d: family %d not supported\n", cpu, c->x86); return -1; } + rdmsr(MSR_AMD64_PATCH_LEVEL, csig->rev, dummy); - pr_info("CPU%d: patch_level=0x%x\n", cpu, csig->rev); + pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev); + return 0; } -static int get_matching_microcode(int cpu, void *mc, int rev) +static int get_matching_microcode(int cpu, struct microcode_header_amd *mc_hdr, + int rev) { - struct microcode_header_amd *mc_header = mc; unsigned int current_cpu_id; u16 equiv_cpu_id = 0; unsigned int i = 0; @@ -109,17 +108,17 @@ static int get_matching_microcode(int cpu, void *mc, int rev) if (!equiv_cpu_id) return 0; - if (mc_header->processor_rev_id != equiv_cpu_id) + if (mc_hdr->processor_rev_id != equiv_cpu_id) return 0; /* ucode might be chipset specific -- currently we don't support this */ - if (mc_header->nb_dev_id || mc_header->sb_dev_id) { - pr_err("CPU%d: loading of chipset specific code not yet supported\n", + if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) { + pr_err("CPU%d: chipset specific code not yet supported\n", cpu); return 0; } - if (mc_header->patch_id <= rev) + if (mc_hdr->patch_id <= rev) return 0; return 1; @@ -144,71 +143,93 @@ static int apply_microcode_amd(int cpu) /* check current patch id and patch's id for match */ if (rev != mc_amd->hdr.patch_id) { - pr_err("CPU%d: update failed (for patch_level=0x%x)\n", + pr_err("CPU%d: update failed for patch_level=0x%08x\n", cpu, mc_amd->hdr.patch_id); return -1; } - pr_info("CPU%d: updated (new patch_level=0x%x)\n", cpu, rev); + pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev); uci->cpu_sig.rev = rev; return 0; } -static void * -get_next_ucode(const u8 *buf, unsigned int size, unsigned int *mc_size) +static unsigned int verify_ucode_size(int cpu, const u8 *buf, unsigned int size) { - unsigned int total_size; - u8 section_hdr[UCODE_CONTAINER_SECTION_HDR]; - void *mc; + struct cpuinfo_x86 *c = &cpu_data(cpu); + unsigned int max_size, actual_size; + +#define F1XH_MPB_MAX_SIZE 2048 +#define F14H_MPB_MAX_SIZE 1824 +#define F15H_MPB_MAX_SIZE 4096 + + switch (c->x86) { + case 0x14: + max_size = F14H_MPB_MAX_SIZE; + break; + case 0x15: + max_size = F15H_MPB_MAX_SIZE; + break; + default: + max_size = F1XH_MPB_MAX_SIZE; + break; + } - get_ucode_data(section_hdr, buf, UCODE_CONTAINER_SECTION_HDR); + actual_size = buf[4] + (buf[5] << 8); - if (section_hdr[0] != UCODE_UCODE_TYPE) { - pr_err("error: invalid type field in container file section header\n"); - return NULL; + if (actual_size > size || actual_size > max_size) { + pr_err("section size mismatch\n"); + return 0; } - total_size = (unsigned long) (section_hdr[4] + (section_hdr[5] << 8)); + return actual_size; +} - if (total_size > size || total_size > UCODE_MAX_SIZE) { - pr_err("error: size mismatch\n"); - return NULL; +static struct microcode_header_amd * +get_next_ucode(int cpu, const u8 *buf, unsigned int size, unsigned int *mc_size) +{ + struct microcode_header_amd *mc = NULL; + unsigned int actual_size = 0; + + if (buf[0] != UCODE_UCODE_TYPE) { + pr_err("invalid type field in container file section header\n"); + goto out; } - mc = vzalloc(UCODE_MAX_SIZE); + actual_size = verify_ucode_size(cpu, buf, size); + if (!actual_size) + goto out; + + mc = vzalloc(actual_size); if (!mc) - return NULL; + goto out; - get_ucode_data(mc, buf + UCODE_CONTAINER_SECTION_HDR, total_size); - *mc_size = total_size + UCODE_CONTAINER_SECTION_HDR; + get_ucode_data(mc, buf + UCODE_CONTAINER_SECTION_HDR, actual_size); + *mc_size = actual_size + UCODE_CONTAINER_SECTION_HDR; +out: return mc; } static int install_equiv_cpu_table(const u8 *buf) { - u8 *container_hdr[UCODE_CONTAINER_HEADER_SIZE]; - unsigned int *buf_pos = (unsigned int *)container_hdr; - unsigned long size; - - get_ucode_data(&container_hdr, buf, UCODE_CONTAINER_HEADER_SIZE); - - size = buf_pos[2]; - - if (buf_pos[1] != UCODE_EQUIV_CPU_TABLE_TYPE || !size) { - pr_err("error: invalid type field in container file section header\n"); - return 0; + unsigned int *ibuf = (unsigned int *)buf; + unsigned int type = ibuf[1]; + unsigned int size = ibuf[2]; + + if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) { + pr_err("empty section/" + "invalid type field in container file section header\n"); + return -EINVAL; } equiv_cpu_table = vmalloc(size); if (!equiv_cpu_table) { pr_err("failed to allocate equivalent CPU table\n"); - return 0; + return -ENOMEM; } - buf += UCODE_CONTAINER_HEADER_SIZE; - get_ucode_data(equiv_cpu_table, buf, size); + get_ucode_data(equiv_cpu_table, buf + UCODE_CONTAINER_HEADER_SIZE, size); return size + UCODE_CONTAINER_HEADER_SIZE; /* add header length */ } @@ -223,16 +244,16 @@ static enum ucode_state generic_load_microcode(int cpu, const u8 *data, size_t size) { struct ucode_cpu_info *uci = ucode_cpu_info + cpu; + struct microcode_header_amd *mc_hdr = NULL; + unsigned int mc_size, leftover; + int offset; const u8 *ucode_ptr = data; void *new_mc = NULL; - void *mc; - int new_rev = uci->cpu_sig.rev; - unsigned int leftover; - unsigned long offset; + unsigned int new_rev = uci->cpu_sig.rev; enum ucode_state state = UCODE_OK; offset = install_equiv_cpu_table(ucode_ptr); - if (!offset) { + if (offset < 0) { pr_err("failed to create equivalent cpu table\n"); return UCODE_ERROR; } @@ -241,64 +262,65 @@ generic_load_microcode(int cpu, const u8 *data, size_t size) leftover = size - offset; while (leftover) { - unsigned int uninitialized_var(mc_size); - struct microcode_header_amd *mc_header; - - mc = get_next_ucode(ucode_ptr, leftover, &mc_size); - if (!mc) + mc_hdr = get_next_ucode(cpu, ucode_ptr, leftover, &mc_size); + if (!mc_hdr) break; - mc_header = (struct microcode_header_amd *)mc; - if (get_matching_microcode(cpu, mc, new_rev)) { + if (get_matching_microcode(cpu, mc_hdr, new_rev)) { vfree(new_mc); - new_rev = mc_header->patch_id; - new_mc = mc; + new_rev = mc_hdr->patch_id; + new_mc = mc_hdr; } else - vfree(mc); + vfree(mc_hdr); ucode_ptr += mc_size; leftover -= mc_size; } - if (new_mc) { - if (!leftover) { - vfree(uci->mc); - uci->mc = new_mc; - pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n", - cpu, new_rev, uci->cpu_sig.rev); - } else { - vfree(new_mc); - state = UCODE_ERROR; - } - } else + if (!new_mc) { state = UCODE_NFOUND; + goto free_table; + } + if (!leftover) { + vfree(uci->mc); + uci->mc = new_mc; + pr_debug("CPU%d update ucode (0x%08x -> 0x%08x)\n", + cpu, uci->cpu_sig.rev, new_rev); + } else { + vfree(new_mc); + state = UCODE_ERROR; + } + +free_table: free_equiv_cpu_table(); return state; } -static enum ucode_state request_microcode_fw(int cpu, struct device *device) +static enum ucode_state request_microcode_amd(int cpu, struct device *device) { const char *fw_name = "amd-ucode/microcode_amd.bin"; - const struct firmware *firmware; - enum ucode_state ret; + const struct firmware *fw; + enum ucode_state ret = UCODE_NFOUND; - if (request_firmware(&firmware, fw_name, device)) { - printk(KERN_ERR "microcode: failed to load file %s\n", fw_name); - return UCODE_NFOUND; + if (request_firmware(&fw, fw_name, device)) { + pr_err("failed to load file %s\n", fw_name); + goto out; } - if (*(u32 *)firmware->data != UCODE_MAGIC) { - pr_err("invalid UCODE_MAGIC (0x%08x)\n", - *(u32 *)firmware->data); - return UCODE_ERROR; + ret = UCODE_ERROR; + if (*(u32 *)fw->data != UCODE_MAGIC) { + pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data); + goto fw_release; } - ret = generic_load_microcode(cpu, firmware->data, firmware->size); + ret = generic_load_microcode(cpu, fw->data, fw->size); - release_firmware(firmware); +fw_release: + release_firmware(fw); +out: return ret; } @@ -319,7 +341,7 @@ static void microcode_fini_cpu_amd(int cpu) static struct microcode_ops microcode_amd_ops = { .request_microcode_user = request_microcode_user, - .request_microcode_fw = request_microcode_fw, + .request_microcode_fw = request_microcode_amd, .collect_cpu_info = collect_cpu_info_amd, .apply_microcode = apply_microcode_amd, .microcode_fini_cpu = microcode_fini_cpu_amd, diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c index 1cca374a2bac..87af68e0e1e1 100644 --- a/arch/x86/kernel/microcode_core.c +++ b/arch/x86/kernel/microcode_core.c @@ -417,8 +417,10 @@ static int mc_sysdev_add(struct sys_device *sys_dev) if (err) return err; - if (microcode_init_cpu(cpu) == UCODE_ERROR) - err = -EINVAL; + if (microcode_init_cpu(cpu) == UCODE_ERROR) { + sysfs_remove_group(&sys_dev->kobj, &mc_attr_group); + return -EINVAL; + } return err; } diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index ff4554198981..99fa3adf0141 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -110,12 +110,9 @@ void show_regs_common(void) init_utsname()->release, (int)strcspn(init_utsname()->version, " "), init_utsname()->version); - printk(KERN_CONT " "); - printk(KERN_CONT "%s %s", vendor, product); - if (board) { - printk(KERN_CONT "/"); - printk(KERN_CONT "%s", board); - } + printk(KERN_CONT " %s %s", vendor, product); + if (board) + printk(KERN_CONT "/%s", board); printk(KERN_CONT "\n"); } diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c index 715037caeb43..d3ce37edb54d 100644 --- a/arch/x86/kernel/reboot.c +++ b/arch/x86/kernel/reboot.c @@ -303,68 +303,16 @@ static int __init reboot_init(void) } core_initcall(reboot_init); -/* The following code and data reboots the machine by switching to real - mode and jumping to the BIOS reset entry point, as if the CPU has - really been reset. The previous version asked the keyboard - controller to pulse the CPU reset line, which is more thorough, but - doesn't work with at least one type of 486 motherboard. It is easy - to stop this code working; hence the copious comments. */ -static const unsigned long long -real_mode_gdt_entries [3] = -{ - 0x0000000000000000ULL, /* Null descriptor */ - 0x00009b000000ffffULL, /* 16-bit real-mode 64k code at 0x00000000 */ - 0x000093000100ffffULL /* 16-bit real-mode 64k data at 0x00000100 */ -}; +extern const unsigned char machine_real_restart_asm[]; +extern const u64 machine_real_restart_gdt[3]; -static const struct desc_ptr -real_mode_gdt = { sizeof (real_mode_gdt_entries) - 1, (long)real_mode_gdt_entries }, -real_mode_idt = { 0x3ff, 0 }; - -/* This is 16-bit protected mode code to disable paging and the cache, - switch to real mode and jump to the BIOS reset code. - - The instruction that switches to real mode by writing to CR0 must be - followed immediately by a far jump instruction, which set CS to a - valid value for real mode, and flushes the prefetch queue to avoid - running instructions that have already been decoded in protected - mode. - - Clears all the flags except ET, especially PG (paging), PE - (protected-mode enable) and TS (task switch for coprocessor state - save). Flushes the TLB after paging has been disabled. Sets CD and - NW, to disable the cache on a 486, and invalidates the cache. This - is more like the state of a 486 after reset. I don't know if - something else should be done for other chips. - - More could be done here to set up the registers as if a CPU reset had - occurred; hopefully real BIOSs don't assume much. */ -static const unsigned char real_mode_switch [] = -{ - 0x66, 0x0f, 0x20, 0xc0, /* movl %cr0,%eax */ - 0x66, 0x83, 0xe0, 0x11, /* andl $0x00000011,%eax */ - 0x66, 0x0d, 0x00, 0x00, 0x00, 0x60, /* orl $0x60000000,%eax */ - 0x66, 0x0f, 0x22, 0xc0, /* movl %eax,%cr0 */ - 0x66, 0x0f, 0x22, 0xd8, /* movl %eax,%cr3 */ - 0x66, 0x0f, 0x20, 0xc3, /* movl %cr0,%ebx */ - 0x66, 0x81, 0xe3, 0x00, 0x00, 0x00, 0x60, /* andl $0x60000000,%ebx */ - 0x74, 0x02, /* jz f */ - 0x0f, 0x09, /* wbinvd */ - 0x24, 0x10, /* f: andb $0x10,al */ - 0x66, 0x0f, 0x22, 0xc0 /* movl %eax,%cr0 */ -}; -static const unsigned char jump_to_bios [] = +void machine_real_restart(unsigned int type) { - 0xea, 0x00, 0x00, 0xff, 0xff /* ljmp $0xffff,$0x0000 */ -}; + void *restart_va; + unsigned long restart_pa; + void (*restart_lowmem)(unsigned int); + u64 *lowmem_gdt; -/* - * Switch to real mode and then execute the code - * specified by the code and length parameters. - * We assume that length will aways be less that 100! - */ -void machine_real_restart(const unsigned char *code, int length) -{ local_irq_disable(); /* Write zero to CMOS register number 0x0f, which the BIOS POST @@ -392,41 +340,23 @@ void machine_real_restart(const unsigned char *code, int length) too. */ *((unsigned short *)0x472) = reboot_mode; - /* For the switch to real mode, copy some code to low memory. It has - to be in the first 64k because it is running in 16-bit mode, and it - has to have the same physical and virtual address, because it turns - off paging. Copy it near the end of the first page, out of the way - of BIOS variables. */ - memcpy((void *)(0x1000 - sizeof(real_mode_switch) - 100), - real_mode_switch, sizeof (real_mode_switch)); - memcpy((void *)(0x1000 - 100), code, length); - - /* Set up the IDT for real mode. */ - load_idt(&real_mode_idt); - - /* Set up a GDT from which we can load segment descriptors for real - mode. The GDT is not used in real mode; it is just needed here to - prepare the descriptors. */ - load_gdt(&real_mode_gdt); - - /* Load the data segment registers, and thus the descriptors ready for - real mode. The base address of each segment is 0x100, 16 times the - selector value being loaded here. This is so that the segment - registers don't have to be reloaded after switching to real mode: - the values are consistent for real mode operation already. */ - __asm__ __volatile__ ("movl $0x0010,%%eax\n" - "\tmovl %%eax,%%ds\n" - "\tmovl %%eax,%%es\n" - "\tmovl %%eax,%%fs\n" - "\tmovl %%eax,%%gs\n" - "\tmovl %%eax,%%ss" : : : "eax"); - - /* Jump to the 16-bit code that we copied earlier. It disables paging - and the cache, switches to real mode, and jumps to the BIOS reset - entry point. */ - __asm__ __volatile__ ("ljmp $0x0008,%0" - : - : "i" ((void *)(0x1000 - sizeof (real_mode_switch) - 100))); + /* Patch the GDT in the low memory trampoline */ + lowmem_gdt = TRAMPOLINE_SYM(machine_real_restart_gdt); + + restart_va = TRAMPOLINE_SYM(machine_real_restart_asm); + restart_pa = virt_to_phys(restart_va); + restart_lowmem = (void (*)(unsigned int))restart_pa; + + /* GDT[0]: GDT self-pointer */ + lowmem_gdt[0] = + (u64)(sizeof(machine_real_restart_gdt) - 1) + + ((u64)virt_to_phys(lowmem_gdt) << 16); + /* GDT[1]: 64K real mode code segment */ + lowmem_gdt[1] = + GDT_ENTRY(0x009b, restart_pa, 0xffff); + + /* Jump to the identity-mapped low memory code */ + restart_lowmem(type); } #ifdef CONFIG_APM_MODULE EXPORT_SYMBOL(machine_real_restart); @@ -581,7 +511,7 @@ static void native_machine_emergency_restart(void) #ifdef CONFIG_X86_32 case BOOT_BIOS: - machine_real_restart(jump_to_bios, sizeof(jump_to_bios)); + machine_real_restart(MRR_BIOS); reboot_type = BOOT_KBD; break; diff --git a/arch/x86/kernel/reboot_32.S b/arch/x86/kernel/reboot_32.S new file mode 100644 index 000000000000..29092b38d816 --- /dev/null +++ b/arch/x86/kernel/reboot_32.S @@ -0,0 +1,135 @@ +#include <linux/linkage.h> +#include <linux/init.h> +#include <asm/segment.h> +#include <asm/page_types.h> + +/* + * The following code and data reboots the machine by switching to real + * mode and jumping to the BIOS reset entry point, as if the CPU has + * really been reset. The previous version asked the keyboard + * controller to pulse the CPU reset line, which is more thorough, but + * doesn't work with at least one type of 486 motherboard. It is easy + * to stop this code working; hence the copious comments. + * + * This code is called with the restart type (0 = BIOS, 1 = APM) in %eax. + */ + .section ".x86_trampoline","a" + .balign 16 + .code32 +ENTRY(machine_real_restart_asm) +r_base = . + /* Get our own relocated address */ + call 1f +1: popl %ebx + subl $1b, %ebx + + /* Compute the equivalent real-mode segment */ + movl %ebx, %ecx + shrl $4, %ecx + + /* Patch post-real-mode segment jump */ + movw dispatch_table(%ebx,%eax,2),%ax + movw %ax, 101f(%ebx) + movw %cx, 102f(%ebx) + + /* Set up the IDT for real mode. */ + lidtl machine_real_restart_idt(%ebx) + + /* + * Set up a GDT from which we can load segment descriptors for real + * mode. The GDT is not used in real mode; it is just needed here to + * prepare the descriptors. + */ + lgdtl machine_real_restart_gdt(%ebx) + + /* + * Load the data segment registers with 16-bit compatible values + */ + movl $16, %ecx + movl %ecx, %ds + movl %ecx, %es + movl %ecx, %fs + movl %ecx, %gs + movl %ecx, %ss + ljmpl $8, $1f - r_base + +/* + * This is 16-bit protected mode code to disable paging and the cache, + * switch to real mode and jump to the BIOS reset code. + * + * The instruction that switches to real mode by writing to CR0 must be + * followed immediately by a far jump instruction, which set CS to a + * valid value for real mode, and flushes the prefetch queue to avoid + * running instructions that have already been decoded in protected + * mode. + * + * Clears all the flags except ET, especially PG (paging), PE + * (protected-mode enable) and TS (task switch for coprocessor state + * save). Flushes the TLB after paging has been disabled. Sets CD and + * NW, to disable the cache on a 486, and invalidates the cache. This + * is more like the state of a 486 after reset. I don't know if + * something else should be done for other chips. + * + * More could be done here to set up the registers as if a CPU reset had + * occurred; hopefully real BIOSs don't assume much. This is not the + * actual BIOS entry point, anyway (that is at 0xfffffff0). + * + * Most of this work is probably excessive, but it is what is tested. + */ + .code16 +1: + xorl %ecx, %ecx + movl %cr0, %eax + andl $0x00000011, %eax + orl $0x60000000, %eax + movl %eax, %cr0 + movl %ecx, %cr3 + movl %cr0, %edx + andl $0x60000000, %edx /* If no cache bits -> no wbinvd */ + jz 2f + wbinvd +2: + andb $0x10, %al + movl %eax, %cr0 + .byte 0xea /* ljmpw */ +101: .word 0 /* Offset */ +102: .word 0 /* Segment */ + +bios: + ljmpw $0xf000, $0xfff0 + +apm: + movw $0x1000, %ax + movw %ax, %ss + movw $0xf000, %sp + movw $0x5307, %ax + movw $0x0001, %bx + movw $0x0003, %cx + int $0x15 + +END(machine_real_restart_asm) + + .balign 16 + /* These must match <asm/reboot.h */ +dispatch_table: + .word bios - r_base + .word apm - r_base +END(dispatch_table) + + .balign 16 +machine_real_restart_idt: + .word 0xffff /* Length - real mode default value */ + .long 0 /* Base - real mode default value */ +END(machine_real_restart_idt) + + .balign 16 +ENTRY(machine_real_restart_gdt) + .quad 0 /* Self-pointer, filled in by PM code */ + .quad 0 /* 16-bit code segment, filled in by PM code */ + /* + * 16-bit data segment with the selector value 16 = 0x10 and + * base value 0x100; since this is consistent with real mode + * semantics we don't have to reload the segments once CR0.PE = 0. + */ + .quad GDT_ENTRY(0x0093, 0x100, 0xffff) +END(machine_real_restart_gdt) diff --git a/arch/x86/kernel/rtc.c b/arch/x86/kernel/rtc.c index 6f39cab052d5..3f2ad2640d85 100644 --- a/arch/x86/kernel/rtc.c +++ b/arch/x86/kernel/rtc.c @@ -6,6 +6,7 @@ #include <linux/acpi.h> #include <linux/bcd.h> #include <linux/pnp.h> +#include <linux/of.h> #include <asm/vsyscall.h> #include <asm/x86_init.h> @@ -236,6 +237,8 @@ static __init int add_rtc_cmos(void) } } #endif + if (of_have_populated_dt()) + return 0; platform_device_register(&rtc_device); dev_info(&rtc_device.dev, diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index d3cfe26c0252..9d43b28e0728 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -113,6 +113,7 @@ #endif #include <asm/mce.h> #include <asm/alternative.h> +#include <asm/prom.h> /* * end_pfn only includes RAM, while max_pfn_mapped includes all e820 entries. @@ -293,10 +294,32 @@ static void __init init_gbpages(void) else direct_gbpages = 0; } + +static void __init cleanup_highmap_brk_end(void) +{ + pud_t *pud; + pmd_t *pmd; + + mmu_cr4_features = read_cr4(); + + /* + * _brk_end cannot change anymore, but it and _end may be + * located on different 2M pages. cleanup_highmap(), however, + * can only consider _end when it runs, so destroy any + * mappings beyond _brk_end here. + */ + pud = pud_offset(pgd_offset_k(_brk_end), _brk_end); + pmd = pmd_offset(pud, _brk_end - 1); + while (++pmd <= pmd_offset(pud, (unsigned long)_end - 1)) + pmd_clear(pmd); +} #else static inline void init_gbpages(void) { } +static inline void cleanup_highmap_brk_end(void) +{ +} #endif static void __init reserve_brk(void) @@ -307,6 +330,8 @@ static void __init reserve_brk(void) /* Mark brk area as locked down and no longer taking any new allocations */ _brk_start = 0; + + cleanup_highmap_brk_end(); } #ifdef CONFIG_BLK_DEV_INITRD @@ -429,16 +454,30 @@ static void __init parse_setup_data(void) return; pa_data = boot_params.hdr.setup_data; while (pa_data) { - data = early_memremap(pa_data, PAGE_SIZE); + u32 data_len, map_len; + + map_len = max(PAGE_SIZE - (pa_data & ~PAGE_MASK), + (u64)sizeof(struct setup_data)); + data = early_memremap(pa_data, map_len); + data_len = data->len + sizeof(struct setup_data); + if (data_len > map_len) { + early_iounmap(data, map_len); + data = early_memremap(pa_data, data_len); + map_len = data_len; + } + switch (data->type) { case SETUP_E820_EXT: - parse_e820_ext(data, pa_data); + parse_e820_ext(data); + break; + case SETUP_DTB: + add_dtb(pa_data); break; default: break; } pa_data = data->next; - early_iounmap(data, PAGE_SIZE); + early_iounmap(data, map_len); } } @@ -680,15 +719,6 @@ static int __init parse_reservelow(char *p) early_param("reservelow", parse_reservelow); -static u64 __init get_max_mapped(void) -{ - u64 end = max_pfn_mapped; - - end <<= PAGE_SHIFT; - - return end; -} - /* * Determine if we were loaded by an EFI loader. If so, then we have also been * passed the efi memmap, systab, etc., so we should use these data structures @@ -704,8 +734,6 @@ static u64 __init get_max_mapped(void) void __init setup_arch(char **cmdline_p) { - int acpi = 0; - int amd = 0; unsigned long flags; #ifdef CONFIG_X86_32 @@ -935,15 +963,8 @@ void __init setup_arch(char **cmdline_p) printk(KERN_DEBUG "initial memory mapped : 0 - %08lx\n", max_pfn_mapped<<PAGE_SHIFT); - reserve_trampoline_memory(); + setup_trampolines(); -#ifdef CONFIG_ACPI_SLEEP - /* - * Reserve low memory region for sleep support. - * even before init_memory_mapping - */ - acpi_reserve_wakeup_memory(); -#endif init_gbpages(); /* max_pfn_mapped is updated here */ @@ -984,19 +1005,7 @@ void __init setup_arch(char **cmdline_p) early_acpi_boot_init(); -#ifdef CONFIG_ACPI_NUMA - /* - * Parse SRAT to discover nodes. - */ - acpi = acpi_numa_init(); -#endif - -#ifdef CONFIG_AMD_NUMA - if (!acpi) - amd = !amd_numa_init(0, max_pfn); -#endif - - initmem_init(0, max_pfn, acpi, amd); + initmem_init(); memblock_find_dma_reserve(); dma32_reserve_bootmem(); @@ -1029,8 +1038,8 @@ void __init setup_arch(char **cmdline_p) * Read APIC and some other early information from ACPI tables. */ acpi_boot_init(); - sfi_init(); + x86_dtb_init(); /* * get boot-time SMP configuration: @@ -1040,9 +1049,7 @@ void __init setup_arch(char **cmdline_p) prefill_possible_map(); -#ifdef CONFIG_X86_64 init_cpu_to_node(); -#endif init_apic_mappings(); ioapic_and_gsi_init(); @@ -1066,6 +1073,8 @@ void __init setup_arch(char **cmdline_p) #endif x86_init.oem.banner(); + x86_init.timers.wallclock_init(); + mcheck_init(); local_irq_save(flags); diff --git a/arch/x86/kernel/setup_percpu.c b/arch/x86/kernel/setup_percpu.c index 002b79685f73..71f4727da373 100644 --- a/arch/x86/kernel/setup_percpu.c +++ b/arch/x86/kernel/setup_percpu.c @@ -225,10 +225,15 @@ void __init setup_per_cpu_areas(void) per_cpu(x86_bios_cpu_apicid, cpu) = early_per_cpu_map(x86_bios_cpu_apicid, cpu); #endif +#ifdef CONFIG_X86_32 + per_cpu(x86_cpu_to_logical_apicid, cpu) = + early_per_cpu_map(x86_cpu_to_logical_apicid, cpu); +#endif #ifdef CONFIG_X86_64 per_cpu(irq_stack_ptr, cpu) = per_cpu(irq_stack_union.irq_stack, cpu) + IRQ_STACK_SIZE - 64; +#endif #ifdef CONFIG_NUMA per_cpu(x86_cpu_to_node_map, cpu) = early_per_cpu_map(x86_cpu_to_node_map, cpu); @@ -242,7 +247,6 @@ void __init setup_per_cpu_areas(void) */ set_cpu_numa_node(cpu, early_cpu_to_node(cpu)); #endif -#endif /* * Up to this point, the boot CPU has been using .init.data * area. Reload any changed state for the boot CPU. @@ -256,7 +260,10 @@ void __init setup_per_cpu_areas(void) early_per_cpu_ptr(x86_cpu_to_apicid) = NULL; early_per_cpu_ptr(x86_bios_cpu_apicid) = NULL; #endif -#if defined(CONFIG_X86_64) && defined(CONFIG_NUMA) +#ifdef CONFIG_X86_32 + early_per_cpu_ptr(x86_cpu_to_logical_apicid) = NULL; +#endif +#ifdef CONFIG_NUMA early_per_cpu_ptr(x86_cpu_to_node_map) = NULL; #endif diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 08776a953487..c2871d3c71b6 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -64,6 +64,7 @@ #include <asm/mtrr.h> #include <asm/mwait.h> #include <asm/apic.h> +#include <asm/io_apic.h> #include <asm/setup.h> #include <asm/uv/uv.h> #include <linux/mc146818rtc.h> @@ -71,10 +72,6 @@ #include <asm/smpboot_hooks.h> #include <asm/i8259.h> -#ifdef CONFIG_X86_32 -u8 apicid_2_node[MAX_APICID]; -#endif - /* State of each CPU */ DEFINE_PER_CPU(int, cpu_state) = { 0 }; @@ -130,68 +127,14 @@ EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); EXPORT_PER_CPU_SYMBOL(cpu_core_map); +DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map); + /* Per CPU bogomips and other parameters */ DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); EXPORT_PER_CPU_SYMBOL(cpu_info); atomic_t init_deasserted; -#if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) -/* which node each logical CPU is on */ -int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; -EXPORT_SYMBOL(cpu_to_node_map); - -/* set up a mapping between cpu and node. */ -static void map_cpu_to_node(int cpu, int node) -{ - printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); - cpumask_set_cpu(cpu, node_to_cpumask_map[node]); - cpu_to_node_map[cpu] = node; -} - -/* undo a mapping between cpu and node. */ -static void unmap_cpu_to_node(int cpu) -{ - int node; - - printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); - for (node = 0; node < MAX_NUMNODES; node++) - cpumask_clear_cpu(cpu, node_to_cpumask_map[node]); - cpu_to_node_map[cpu] = 0; -} -#else /* !(CONFIG_NUMA && CONFIG_X86_32) */ -#define map_cpu_to_node(cpu, node) ({}) -#define unmap_cpu_to_node(cpu) ({}) -#endif - -#ifdef CONFIG_X86_32 -static int boot_cpu_logical_apicid; - -u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = - { [0 ... NR_CPUS-1] = BAD_APICID }; - -static void map_cpu_to_logical_apicid(void) -{ - int cpu = smp_processor_id(); - int apicid = logical_smp_processor_id(); - int node = apic->apicid_to_node(apicid); - - if (!node_online(node)) - node = first_online_node; - - cpu_2_logical_apicid[cpu] = apicid; - map_cpu_to_node(cpu, node); -} - -void numa_remove_cpu(int cpu) -{ - cpu_2_logical_apicid[cpu] = BAD_APICID; - unmap_cpu_to_node(cpu); -} -#else -#define map_cpu_to_logical_apicid() do {} while (0) -#endif - /* * Report back to the Boot Processor. * Running on AP. @@ -259,7 +202,6 @@ static void __cpuinit smp_callin(void) apic->smp_callin_clear_local_apic(); setup_local_APIC(); end_local_APIC_setup(); - map_cpu_to_logical_apicid(); /* * Need to setup vector mappings before we enable interrupts. @@ -355,23 +297,6 @@ notrace static void __cpuinit start_secondary(void *unused) cpu_idle(); } -#ifdef CONFIG_CPUMASK_OFFSTACK -/* In this case, llc_shared_map is a pointer to a cpumask. */ -static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, - const struct cpuinfo_x86 *src) -{ - struct cpumask *llc = dst->llc_shared_map; - *dst = *src; - dst->llc_shared_map = llc; -} -#else -static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, - const struct cpuinfo_x86 *src) -{ - *dst = *src; -} -#endif /* CONFIG_CPUMASK_OFFSTACK */ - /* * The bootstrap kernel entry code has set these up. Save them for * a given CPU @@ -381,7 +306,7 @@ void __cpuinit smp_store_cpu_info(int id) { struct cpuinfo_x86 *c = &cpu_data(id); - copy_cpuinfo_x86(c, &boot_cpu_data); + *c = boot_cpu_data; c->cpu_index = id; if (id != 0) identify_secondary_cpu(c); @@ -389,15 +314,12 @@ void __cpuinit smp_store_cpu_info(int id) static void __cpuinit link_thread_siblings(int cpu1, int cpu2) { - struct cpuinfo_x86 *c1 = &cpu_data(cpu1); - struct cpuinfo_x86 *c2 = &cpu_data(cpu2); - cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2)); cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1)); cpumask_set_cpu(cpu1, cpu_core_mask(cpu2)); cpumask_set_cpu(cpu2, cpu_core_mask(cpu1)); - cpumask_set_cpu(cpu1, c2->llc_shared_map); - cpumask_set_cpu(cpu2, c1->llc_shared_map); + cpumask_set_cpu(cpu1, cpu_llc_shared_mask(cpu2)); + cpumask_set_cpu(cpu2, cpu_llc_shared_mask(cpu1)); } @@ -414,6 +336,7 @@ void __cpuinit set_cpu_sibling_map(int cpu) if (cpu_has(c, X86_FEATURE_TOPOEXT)) { if (c->phys_proc_id == o->phys_proc_id && + per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i) && c->compute_unit_id == o->compute_unit_id) link_thread_siblings(cpu, i); } else if (c->phys_proc_id == o->phys_proc_id && @@ -425,7 +348,7 @@ void __cpuinit set_cpu_sibling_map(int cpu) cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); } - cpumask_set_cpu(cpu, c->llc_shared_map); + cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); if (__this_cpu_read(cpu_info.x86_max_cores) == 1) { cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); @@ -436,8 +359,8 @@ void __cpuinit set_cpu_sibling_map(int cpu) for_each_cpu(i, cpu_sibling_setup_mask) { if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { - cpumask_set_cpu(i, c->llc_shared_map); - cpumask_set_cpu(cpu, cpu_data(i).llc_shared_map); + cpumask_set_cpu(i, cpu_llc_shared_mask(cpu)); + cpumask_set_cpu(cpu, cpu_llc_shared_mask(i)); } if (c->phys_proc_id == cpu_data(i).phys_proc_id) { cpumask_set_cpu(i, cpu_core_mask(cpu)); @@ -476,7 +399,7 @@ const struct cpumask *cpu_coregroup_mask(int cpu) !(cpu_has(c, X86_FEATURE_AMD_DCM))) return cpu_core_mask(cpu); else - return c->llc_shared_map; + return cpu_llc_shared_mask(cpu); } static void impress_friends(void) @@ -788,7 +711,7 @@ do_rest: stack_start = c_idle.idle->thread.sp; /* start_ip had better be page-aligned! */ - start_ip = setup_trampoline(); + start_ip = trampoline_address(); /* So we see what's up */ announce_cpu(cpu, apicid); @@ -798,6 +721,8 @@ do_rest: * the targeted processor. */ + printk(KERN_DEBUG "smpboot cpu %d: start_ip = %lx\n", cpu, start_ip); + atomic_set(&init_deasserted, 0); if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { @@ -851,8 +776,8 @@ do_rest: pr_debug("CPU%d: has booted.\n", cpu); else { boot_error = 1; - if (*((volatile unsigned char *)trampoline_base) - == 0xA5) + if (*(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) + == 0xA5A5A5A5) /* trampoline started but...? */ pr_err("CPU%d: Stuck ??\n", cpu); else @@ -878,7 +803,7 @@ do_rest: } /* mark "stuck" area as not stuck */ - *((volatile unsigned long *)trampoline_base) = 0; + *(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) = 0; if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { /* @@ -945,6 +870,14 @@ int __cpuinit native_cpu_up(unsigned int cpu) return 0; } +/** + * arch_disable_smp_support() - disables SMP support for x86 at runtime + */ +void arch_disable_smp_support(void) +{ + disable_ioapic_support(); +} + /* * Fall back to non SMP mode after errors. * @@ -960,7 +893,6 @@ static __init void disable_smp(void) physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); else physid_set_mask_of_physid(0, &phys_cpu_present_map); - map_cpu_to_logical_apicid(); cpumask_set_cpu(0, cpu_sibling_mask(0)); cpumask_set_cpu(0, cpu_core_mask(0)); } @@ -1045,7 +977,7 @@ static int __init smp_sanity_check(unsigned max_cpus) "(tell your hw vendor)\n"); } smpboot_clear_io_apic(); - arch_disable_smp_support(); + disable_ioapic_support(); return -1; } @@ -1089,21 +1021,19 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus) preempt_disable(); smp_cpu_index_default(); - memcpy(__this_cpu_ptr(&cpu_info), &boot_cpu_data, sizeof(cpu_info)); - cpumask_copy(cpu_callin_mask, cpumask_of(0)); - mb(); + /* * Setup boot CPU information */ smp_store_cpu_info(0); /* Final full version of the data */ -#ifdef CONFIG_X86_32 - boot_cpu_logical_apicid = logical_smp_processor_id(); -#endif + cpumask_copy(cpu_callin_mask, cpumask_of(0)); + mb(); + current_thread_info()->cpu = 0; /* needed? */ for_each_possible_cpu(i) { zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); - zalloc_cpumask_var(&cpu_data(i).llc_shared_map, GFP_KERNEL); + zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); } set_cpu_sibling_map(0); @@ -1139,8 +1069,6 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus) bsp_end_local_APIC_setup(); - map_cpu_to_logical_apicid(); - if (apic->setup_portio_remap) apic->setup_portio_remap(); diff --git a/arch/x86/kernel/syscall_table_32.S b/arch/x86/kernel/syscall_table_32.S index b35786dc9b8f..5f181742e8f9 100644 --- a/arch/x86/kernel/syscall_table_32.S +++ b/arch/x86/kernel/syscall_table_32.S @@ -340,3 +340,6 @@ ENTRY(sys_call_table) .long sys_fanotify_init .long sys_fanotify_mark .long sys_prlimit64 /* 340 */ + .long sys_name_to_handle_at + .long sys_open_by_handle_at + .long sys_clock_adjtime diff --git a/arch/x86/kernel/trampoline.c b/arch/x86/kernel/trampoline.c index a375616d77f7..a91ae7709b49 100644 --- a/arch/x86/kernel/trampoline.c +++ b/arch/x86/kernel/trampoline.c @@ -2,39 +2,41 @@ #include <linux/memblock.h> #include <asm/trampoline.h> +#include <asm/cacheflush.h> #include <asm/pgtable.h> -#if defined(CONFIG_X86_64) && defined(CONFIG_ACPI_SLEEP) -#define __trampinit -#define __trampinitdata -#else -#define __trampinit __cpuinit -#define __trampinitdata __cpuinitdata -#endif +unsigned char *x86_trampoline_base; -/* ready for x86_64 and x86 */ -unsigned char *__trampinitdata trampoline_base; - -void __init reserve_trampoline_memory(void) +void __init setup_trampolines(void) { phys_addr_t mem; + size_t size = PAGE_ALIGN(x86_trampoline_end - x86_trampoline_start); /* Has to be in very low memory so we can execute real-mode AP code. */ - mem = memblock_find_in_range(0, 1<<20, TRAMPOLINE_SIZE, PAGE_SIZE); + mem = memblock_find_in_range(0, 1<<20, size, PAGE_SIZE); if (mem == MEMBLOCK_ERROR) panic("Cannot allocate trampoline\n"); - trampoline_base = __va(mem); - memblock_x86_reserve_range(mem, mem + TRAMPOLINE_SIZE, "TRAMPOLINE"); + x86_trampoline_base = __va(mem); + memblock_x86_reserve_range(mem, mem + size, "TRAMPOLINE"); + + printk(KERN_DEBUG "Base memory trampoline at [%p] %llx size %zu\n", + x86_trampoline_base, (unsigned long long)mem, size); + + memcpy(x86_trampoline_base, x86_trampoline_start, size); } /* - * Currently trivial. Write the real->protected mode - * bootstrap into the page concerned. The caller - * has made sure it's suitably aligned. + * setup_trampolines() gets called very early, to guarantee the + * availability of low memory. This is before the proper kernel page + * tables are set up, so we cannot set page permissions in that + * function. Thus, we use an arch_initcall instead. */ -unsigned long __trampinit setup_trampoline(void) +static int __init configure_trampolines(void) { - memcpy(trampoline_base, trampoline_data, TRAMPOLINE_SIZE); - return virt_to_phys(trampoline_base); + size_t size = PAGE_ALIGN(x86_trampoline_end - x86_trampoline_start); + + set_memory_x((unsigned long)x86_trampoline_base, size >> PAGE_SHIFT); + return 0; } +arch_initcall(configure_trampolines); diff --git a/arch/x86/kernel/trampoline_32.S b/arch/x86/kernel/trampoline_32.S index 8508237e8e43..451c0a7ef7fd 100644 --- a/arch/x86/kernel/trampoline_32.S +++ b/arch/x86/kernel/trampoline_32.S @@ -32,9 +32,11 @@ #include <asm/segment.h> #include <asm/page_types.h> -/* We can free up trampoline after bootup if cpu hotplug is not supported. */ -__CPUINITRODATA -.code16 +#ifdef CONFIG_SMP + + .section ".x86_trampoline","a" + .balign PAGE_SIZE + .code16 ENTRY(trampoline_data) r_base = . @@ -44,7 +46,7 @@ r_base = . cli # We should be safe anyway - movl $0xA5A5A5A5, trampoline_data - r_base + movl $0xA5A5A5A5, trampoline_status - r_base # write marker for master knows we're running /* GDT tables in non default location kernel can be beyond 16MB and @@ -72,5 +74,10 @@ boot_idt_descr: .word 0 # idt limit = 0 .long 0 # idt base = 0L +ENTRY(trampoline_status) + .long 0 + .globl trampoline_end trampoline_end: + +#endif /* CONFIG_SMP */ diff --git a/arch/x86/kernel/trampoline_64.S b/arch/x86/kernel/trampoline_64.S index 075d130efcf9..09ff51799e96 100644 --- a/arch/x86/kernel/trampoline_64.S +++ b/arch/x86/kernel/trampoline_64.S @@ -32,13 +32,9 @@ #include <asm/segment.h> #include <asm/processor-flags.h> -#ifdef CONFIG_ACPI_SLEEP -.section .rodata, "a", @progbits -#else -/* We can free up the trampoline after bootup if cpu hotplug is not supported. */ -__CPUINITRODATA -#endif -.code16 + .section ".x86_trampoline","a" + .balign PAGE_SIZE + .code16 ENTRY(trampoline_data) r_base = . @@ -50,7 +46,7 @@ r_base = . mov %ax, %ss - movl $0xA5A5A5A5, trampoline_data - r_base + movl $0xA5A5A5A5, trampoline_status - r_base # write marker for master knows we're running # Setup stack @@ -64,10 +60,13 @@ r_base = . movzx %ax, %esi # Find the 32bit trampoline location shll $4, %esi - # Fixup the vectors - addl %esi, startup_32_vector - r_base - addl %esi, startup_64_vector - r_base - addl %esi, tgdt + 2 - r_base # Fixup the gdt pointer + # Fixup the absolute vectors + leal (startup_32 - r_base)(%esi), %eax + movl %eax, startup_32_vector - r_base + leal (startup_64 - r_base)(%esi), %eax + movl %eax, startup_64_vector - r_base + leal (tgdt - r_base)(%esi), %eax + movl %eax, (tgdt + 2 - r_base) /* * GDT tables in non default location kernel can be beyond 16MB and @@ -129,6 +128,7 @@ no_longmode: jmp no_longmode #include "verify_cpu.S" + .balign 4 # Careful these need to be in the same 64K segment as the above; tidt: .word 0 # idt limit = 0 @@ -156,6 +156,10 @@ startup_64_vector: .long startup_64 - r_base .word __KERNEL_CS, 0 + .balign 4 +ENTRY(trampoline_status) + .long 0 + trampoline_stack: .org 0x1000 trampoline_stack_end: diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S index bf4700755184..624a2016198e 100644 --- a/arch/x86/kernel/vmlinux.lds.S +++ b/arch/x86/kernel/vmlinux.lds.S @@ -105,6 +105,7 @@ SECTIONS SCHED_TEXT LOCK_TEXT KPROBES_TEXT + ENTRY_TEXT IRQENTRY_TEXT *(.fixup) *(.gnu.warning) @@ -230,7 +231,7 @@ SECTIONS * output PHDR, so the next output section - .init.text - should * start another segment - init. */ - PERCPU_VADDR(0, :percpu) + PERCPU_VADDR(INTERNODE_CACHE_BYTES, 0, :percpu) #endif INIT_TEXT_SECTION(PAGE_SIZE) @@ -240,6 +241,18 @@ SECTIONS INIT_DATA_SECTION(16) + /* + * Code and data for a variety of lowlevel trampolines, to be + * copied into base memory (< 1 MiB) during initialization. + * Since it is copied early, the main copy can be discarded + * afterwards. + */ + .x86_trampoline : AT(ADDR(.x86_trampoline) - LOAD_OFFSET) { + x86_trampoline_start = .; + *(.x86_trampoline) + x86_trampoline_end = .; + } + .x86_cpu_dev.init : AT(ADDR(.x86_cpu_dev.init) - LOAD_OFFSET) { __x86_cpu_dev_start = .; *(.x86_cpu_dev.init) @@ -291,6 +304,7 @@ SECTIONS *(.iommu_table) __iommu_table_end = .; } + . = ALIGN(8); /* * .exit.text is discard at runtime, not link time, to deal with @@ -305,7 +319,7 @@ SECTIONS } #if !defined(CONFIG_X86_64) || !defined(CONFIG_SMP) - PERCPU(THREAD_SIZE) + PERCPU(INTERNODE_CACHE_BYTES, PAGE_SIZE) #endif . = ALIGN(PAGE_SIZE); diff --git a/arch/x86/kernel/x8664_ksyms_64.c b/arch/x86/kernel/x8664_ksyms_64.c index 1b950d151e58..9796c2f3d074 100644 --- a/arch/x86/kernel/x8664_ksyms_64.c +++ b/arch/x86/kernel/x8664_ksyms_64.c @@ -52,6 +52,7 @@ extern void *__memcpy(void *, const void *, __kernel_size_t); EXPORT_SYMBOL(memset); EXPORT_SYMBOL(memcpy); EXPORT_SYMBOL(__memcpy); +EXPORT_SYMBOL(memmove); EXPORT_SYMBOL(empty_zero_page); #ifndef CONFIG_PARAVIRT diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c index ceb2911aa439..c11514e9128b 100644 --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c @@ -70,6 +70,7 @@ struct x86_init_ops x86_init __initdata = { .setup_percpu_clockev = setup_boot_APIC_clock, .tsc_pre_init = x86_init_noop, .timer_init = hpet_time_init, + .wallclock_init = x86_init_noop, }, .iommu = { diff --git a/arch/x86/kvm/trace.h b/arch/x86/kvm/trace.h index 1357d7cf4ec8..db932760ea82 100644 --- a/arch/x86/kvm/trace.h +++ b/arch/x86/kvm/trace.h @@ -62,21 +62,21 @@ TRACE_EVENT(kvm_hv_hypercall, TP_ARGS(code, fast, rep_cnt, rep_idx, ingpa, outgpa), TP_STRUCT__entry( - __field( __u16, code ) - __field( bool, fast ) __field( __u16, rep_cnt ) __field( __u16, rep_idx ) __field( __u64, ingpa ) __field( __u64, outgpa ) + __field( __u16, code ) + __field( bool, fast ) ), TP_fast_assign( - __entry->code = code; - __entry->fast = fast; __entry->rep_cnt = rep_cnt; __entry->rep_idx = rep_idx; __entry->ingpa = ingpa; __entry->outgpa = outgpa; + __entry->code = code; + __entry->fast = fast; ), TP_printk("code 0x%x %s cnt 0x%x idx 0x%x in 0x%llx out 0x%llx", diff --git a/arch/x86/lguest/boot.c b/arch/x86/lguest/boot.c index eba687f0cc0c..b9ec1c74943c 100644 --- a/arch/x86/lguest/boot.c +++ b/arch/x86/lguest/boot.c @@ -847,7 +847,7 @@ static void __init lguest_init_IRQ(void) void lguest_setup_irq(unsigned int irq) { irq_alloc_desc_at(irq, 0); - set_irq_chip_and_handler_name(irq, &lguest_irq_controller, + irq_set_chip_and_handler_name(irq, &lguest_irq_controller, handle_level_irq, "level"); } @@ -995,7 +995,7 @@ static void lguest_time_irq(unsigned int irq, struct irq_desc *desc) static void lguest_time_init(void) { /* Set up the timer interrupt (0) to go to our simple timer routine */ - set_irq_handler(0, lguest_time_irq); + irq_set_handler(0, lguest_time_irq); clocksource_register(&lguest_clock); diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index e10cf070ede0..f2479f19ddde 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -42,4 +42,5 @@ else lib-y += memmove_64.o memset_64.o lib-y += copy_user_64.o rwlock_64.o copy_user_nocache_64.o lib-$(CONFIG_RWSEM_XCHGADD_ALGORITHM) += rwsem_64.o + lib-y += cmpxchg16b_emu.o endif diff --git a/arch/x86/lib/atomic64_386_32.S b/arch/x86/lib/atomic64_386_32.S index 2cda60a06e65..e8e7e0d06f42 100644 --- a/arch/x86/lib/atomic64_386_32.S +++ b/arch/x86/lib/atomic64_386_32.S @@ -15,14 +15,12 @@ /* if you want SMP support, implement these with real spinlocks */ .macro LOCK reg - pushfl - CFI_ADJUST_CFA_OFFSET 4 + pushfl_cfi cli .endm .macro UNLOCK reg - popfl - CFI_ADJUST_CFA_OFFSET -4 + popfl_cfi .endm #define BEGIN(op) \ diff --git a/arch/x86/lib/atomic64_cx8_32.S b/arch/x86/lib/atomic64_cx8_32.S index 71e080de3352..391a083674b4 100644 --- a/arch/x86/lib/atomic64_cx8_32.S +++ b/arch/x86/lib/atomic64_cx8_32.S @@ -14,14 +14,12 @@ #include <asm/dwarf2.h> .macro SAVE reg - pushl %\reg - CFI_ADJUST_CFA_OFFSET 4 + pushl_cfi %\reg CFI_REL_OFFSET \reg, 0 .endm .macro RESTORE reg - popl %\reg - CFI_ADJUST_CFA_OFFSET -4 + popl_cfi %\reg CFI_RESTORE \reg .endm diff --git a/arch/x86/lib/checksum_32.S b/arch/x86/lib/checksum_32.S index adbccd0bbb78..78d16a554db0 100644 --- a/arch/x86/lib/checksum_32.S +++ b/arch/x86/lib/checksum_32.S @@ -50,11 +50,9 @@ unsigned int csum_partial(const unsigned char * buff, int len, unsigned int sum) */ ENTRY(csum_partial) CFI_STARTPROC - pushl %esi - CFI_ADJUST_CFA_OFFSET 4 + pushl_cfi %esi CFI_REL_OFFSET esi, 0 - pushl %ebx - CFI_ADJUST_CFA_OFFSET 4 + pushl_cfi %ebx CFI_REL_OFFSET ebx, 0 movl 20(%esp),%eax # Function arg: unsigned int sum movl 16(%esp),%ecx # Function arg: int len @@ -132,11 +130,9 @@ ENTRY(csum_partial) jz 8f roll $8, %eax 8: - popl %ebx - CFI_ADJUST_CFA_OFFSET -4 + popl_cfi %ebx CFI_RESTORE ebx - popl %esi - CFI_ADJUST_CFA_OFFSET -4 + popl_cfi %esi CFI_RESTORE esi ret CFI_ENDPROC @@ -148,11 +144,9 @@ ENDPROC(csum_partial) ENTRY(csum_partial) CFI_STARTPROC - pushl %esi - CFI_ADJUST_CFA_OFFSET 4 + pushl_cfi %esi CFI_REL_OFFSET esi, 0 - pushl %ebx - CFI_ADJUST_CFA_OFFSET 4 + pushl_cfi %ebx CFI_REL_OFFSET ebx, 0 movl 20(%esp),%eax # Function arg: unsigned int sum movl 16(%esp),%ecx # Function arg: int len @@ -260,11 +254,9 @@ ENTRY(csum_partial) jz 90f roll $8, %eax 90: - popl %ebx - CFI_ADJUST_CFA_OFFSET -4 + popl_cfi %ebx CFI_RESTORE ebx - popl %esi - CFI_ADJUST_CFA_OFFSET -4 + popl_cfi %esi CFI_RESTORE esi ret CFI_ENDPROC @@ -309,14 +301,11 @@ ENTRY(csum_partial_copy_generic) CFI_STARTPROC subl $4,%esp CFI_ADJUST_CFA_OFFSET 4 - pushl %edi - CFI_ADJUST_CFA_OFFSET 4 + pushl_cfi %edi CFI_REL_OFFSET edi, 0 - pushl %esi - CFI_ADJUST_CFA_OFFSET 4 + pushl_cfi %esi CFI_REL_OFFSET esi, 0 - pushl %ebx - CFI_ADJUST_CFA_OFFSET 4 + pushl_cfi %ebx CFI_REL_OFFSET ebx, 0 movl ARGBASE+16(%esp),%eax # sum movl ARGBASE+12(%esp),%ecx # len @@ -426,17 +415,13 @@ DST( movb %cl, (%edi) ) .previous - popl %ebx - CFI_ADJUST_CFA_OFFSET -4 + popl_cfi %ebx CFI_RESTORE ebx - popl %esi - CFI_ADJUST_CFA_OFFSET -4 + popl_cfi %esi CFI_RESTORE esi - popl %edi - CFI_ADJUST_CFA_OFFSET -4 + popl_cfi %edi CFI_RESTORE edi - popl %ecx # equivalent to addl $4,%esp - CFI_ADJUST_CFA_OFFSET -4 + popl_cfi %ecx # equivalent to addl $4,%esp ret CFI_ENDPROC ENDPROC(csum_partial_copy_generic) @@ -459,14 +444,11 @@ ENDPROC(csum_partial_copy_generic) ENTRY(csum_partial_copy_generic) CFI_STARTPROC - pushl %ebx - CFI_ADJUST_CFA_OFFSET 4 + pushl_cfi %ebx CFI_REL_OFFSET ebx, 0 - pushl %edi - CFI_ADJUST_CFA_OFFSET 4 + pushl_cfi %edi CFI_REL_OFFSET edi, 0 - pushl %esi - CFI_ADJUST_CFA_OFFSET 4 + pushl_cfi %esi CFI_REL_OFFSET esi, 0 movl ARGBASE+4(%esp),%esi #src movl ARGBASE+8(%esp),%edi #dst @@ -527,14 +509,11 @@ DST( movb %dl, (%edi) ) jmp 7b .previous - popl %esi - CFI_ADJUST_CFA_OFFSET -4 + popl_cfi %esi CFI_RESTORE esi - popl %edi - CFI_ADJUST_CFA_OFFSET -4 + popl_cfi %edi CFI_RESTORE edi - popl %ebx - CFI_ADJUST_CFA_OFFSET -4 + popl_cfi %ebx CFI_RESTORE ebx ret CFI_ENDPROC diff --git a/arch/x86/lib/cmpxchg16b_emu.S b/arch/x86/lib/cmpxchg16b_emu.S new file mode 100644 index 000000000000..3e8b08a6de2b --- /dev/null +++ b/arch/x86/lib/cmpxchg16b_emu.S @@ -0,0 +1,59 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; version 2 + * of the License. + * + */ +#include <linux/linkage.h> +#include <asm/alternative-asm.h> +#include <asm/frame.h> +#include <asm/dwarf2.h> + +.text + +/* + * Inputs: + * %rsi : memory location to compare + * %rax : low 64 bits of old value + * %rdx : high 64 bits of old value + * %rbx : low 64 bits of new value + * %rcx : high 64 bits of new value + * %al : Operation successful + */ +ENTRY(this_cpu_cmpxchg16b_emu) +CFI_STARTPROC + +# +# Emulate 'cmpxchg16b %gs:(%rsi)' except we return the result in %al not +# via the ZF. Caller will access %al to get result. +# +# Note that this is only useful for a cpuops operation. Meaning that we +# do *not* have a fully atomic operation but just an operation that is +# *atomic* on a single cpu (as provided by the this_cpu_xx class of +# macros). +# +this_cpu_cmpxchg16b_emu: + pushf + cli + + cmpq %gs:(%rsi), %rax + jne not_same + cmpq %gs:8(%rsi), %rdx + jne not_same + + movq %rbx, %gs:(%rsi) + movq %rcx, %gs:8(%rsi) + + popf + mov $1, %al + ret + + not_same: + popf + xor %al,%al + ret + +CFI_ENDPROC + +ENDPROC(this_cpu_cmpxchg16b_emu) diff --git a/arch/x86/lib/memmove_64.S b/arch/x86/lib/memmove_64.S new file mode 100644 index 000000000000..0ecb8433e5a8 --- /dev/null +++ b/arch/x86/lib/memmove_64.S @@ -0,0 +1,197 @@ +/* + * Normally compiler builtins are used, but sometimes the compiler calls out + * of line code. Based on asm-i386/string.h. + * + * This assembly file is re-written from memmove_64.c file. + * - Copyright 2011 Fenghua Yu <fenghua.yu@intel.com> + */ +#define _STRING_C +#include <linux/linkage.h> +#include <asm/dwarf2.h> + +#undef memmove + +/* + * Implement memmove(). This can handle overlap between src and dst. + * + * Input: + * rdi: dest + * rsi: src + * rdx: count + * + * Output: + * rax: dest + */ +ENTRY(memmove) + CFI_STARTPROC + /* Handle more 32bytes in loop */ + mov %rdi, %rax + cmp $0x20, %rdx + jb 1f + + /* Decide forward/backward copy mode */ + cmp %rdi, %rsi + jb 2f + + /* + * movsq instruction have many startup latency + * so we handle small size by general register. + */ + cmp $680, %rdx + jb 3f + /* + * movsq instruction is only good for aligned case. + */ + + cmpb %dil, %sil + je 4f +3: + sub $0x20, %rdx + /* + * We gobble 32byts forward in each loop. + */ +5: + sub $0x20, %rdx + movq 0*8(%rsi), %r11 + movq 1*8(%rsi), %r10 + movq 2*8(%rsi), %r9 + movq 3*8(%rsi), %r8 + leaq 4*8(%rsi), %rsi + + movq %r11, 0*8(%rdi) + movq %r10, 1*8(%rdi) + movq %r9, 2*8(%rdi) + movq %r8, 3*8(%rdi) + leaq 4*8(%rdi), %rdi + jae 5b + addq $0x20, %rdx + jmp 1f + /* + * Handle data forward by movsq. + */ + .p2align 4 +4: + movq %rdx, %rcx + movq -8(%rsi, %rdx), %r11 + lea -8(%rdi, %rdx), %r10 + shrq $3, %rcx + rep movsq + movq %r11, (%r10) + jmp 13f + /* + * Handle data backward by movsq. + */ + .p2align 4 +7: + movq %rdx, %rcx + movq (%rsi), %r11 + movq %rdi, %r10 + leaq -8(%rsi, %rdx), %rsi + leaq -8(%rdi, %rdx), %rdi + shrq $3, %rcx + std + rep movsq + cld + movq %r11, (%r10) + jmp 13f + + /* + * Start to prepare for backward copy. + */ + .p2align 4 +2: + cmp $680, %rdx + jb 6f + cmp %dil, %sil + je 7b +6: + /* + * Calculate copy position to tail. + */ + addq %rdx, %rsi + addq %rdx, %rdi + subq $0x20, %rdx + /* + * We gobble 32byts backward in each loop. + */ +8: + subq $0x20, %rdx + movq -1*8(%rsi), %r11 + movq -2*8(%rsi), %r10 + movq -3*8(%rsi), %r9 + movq -4*8(%rsi), %r8 + leaq -4*8(%rsi), %rsi + + movq %r11, -1*8(%rdi) + movq %r10, -2*8(%rdi) + movq %r9, -3*8(%rdi) + movq %r8, -4*8(%rdi) + leaq -4*8(%rdi), %rdi + jae 8b + /* + * Calculate copy position to head. + */ + addq $0x20, %rdx + subq %rdx, %rsi + subq %rdx, %rdi +1: + cmpq $16, %rdx + jb 9f + /* + * Move data from 16 bytes to 31 bytes. + */ + movq 0*8(%rsi), %r11 + movq 1*8(%rsi), %r10 + movq -2*8(%rsi, %rdx), %r9 + movq -1*8(%rsi, %rdx), %r8 + movq %r11, 0*8(%rdi) + movq %r10, 1*8(%rdi) + movq %r9, -2*8(%rdi, %rdx) + movq %r8, -1*8(%rdi, %rdx) + jmp 13f + .p2align 4 +9: + cmpq $8, %rdx + jb 10f + /* + * Move data from 8 bytes to 15 bytes. + */ + movq 0*8(%rsi), %r11 + movq -1*8(%rsi, %rdx), %r10 + movq %r11, 0*8(%rdi) + movq %r10, -1*8(%rdi, %rdx) + jmp 13f +10: + cmpq $4, %rdx + jb 11f + /* + * Move data from 4 bytes to 7 bytes. + */ + movl (%rsi), %r11d + movl -4(%rsi, %rdx), %r10d + movl %r11d, (%rdi) + movl %r10d, -4(%rdi, %rdx) + jmp 13f +11: + cmp $2, %rdx + jb 12f + /* + * Move data from 2 bytes to 3 bytes. + */ + movw (%rsi), %r11w + movw -2(%rsi, %rdx), %r10w + movw %r11w, (%rdi) + movw %r10w, -2(%rdi, %rdx) + jmp 13f +12: + cmp $1, %rdx + jb 13f + /* + * Move data for 1 byte. + */ + movb (%rsi), %r11b + movb %r11b, (%rdi) +13: + retq + CFI_ENDPROC +ENDPROC(memmove) diff --git a/arch/x86/lib/memmove_64.c b/arch/x86/lib/memmove_64.c deleted file mode 100644 index 6d0f0ec41b34..000000000000 --- a/arch/x86/lib/memmove_64.c +++ /dev/null @@ -1,192 +0,0 @@ -/* Normally compiler builtins are used, but sometimes the compiler calls out - of line code. Based on asm-i386/string.h. - */ -#define _STRING_C -#include <linux/string.h> -#include <linux/module.h> - -#undef memmove -void *memmove(void *dest, const void *src, size_t count) -{ - unsigned long d0,d1,d2,d3,d4,d5,d6,d7; - char *ret; - - __asm__ __volatile__( - /* Handle more 32bytes in loop */ - "mov %2, %3\n\t" - "cmp $0x20, %0\n\t" - "jb 1f\n\t" - - /* Decide forward/backward copy mode */ - "cmp %2, %1\n\t" - "jb 2f\n\t" - - /* - * movsq instruction have many startup latency - * so we handle small size by general register. - */ - "cmp $680, %0\n\t" - "jb 3f\n\t" - /* - * movsq instruction is only good for aligned case. - */ - "cmpb %%dil, %%sil\n\t" - "je 4f\n\t" - "3:\n\t" - "sub $0x20, %0\n\t" - /* - * We gobble 32byts forward in each loop. - */ - "5:\n\t" - "sub $0x20, %0\n\t" - "movq 0*8(%1), %4\n\t" - "movq 1*8(%1), %5\n\t" - "movq 2*8(%1), %6\n\t" - "movq 3*8(%1), %7\n\t" - "leaq 4*8(%1), %1\n\t" - - "movq %4, 0*8(%2)\n\t" - "movq %5, 1*8(%2)\n\t" - "movq %6, 2*8(%2)\n\t" - "movq %7, 3*8(%2)\n\t" - "leaq 4*8(%2), %2\n\t" - "jae 5b\n\t" - "addq $0x20, %0\n\t" - "jmp 1f\n\t" - /* - * Handle data forward by movsq. - */ - ".p2align 4\n\t" - "4:\n\t" - "movq %0, %8\n\t" - "movq -8(%1, %0), %4\n\t" - "lea -8(%2, %0), %5\n\t" - "shrq $3, %8\n\t" - "rep movsq\n\t" - "movq %4, (%5)\n\t" - "jmp 13f\n\t" - /* - * Handle data backward by movsq. - */ - ".p2align 4\n\t" - "7:\n\t" - "movq %0, %8\n\t" - "movq (%1), %4\n\t" - "movq %2, %5\n\t" - "leaq -8(%1, %0), %1\n\t" - "leaq -8(%2, %0), %2\n\t" - "shrq $3, %8\n\t" - "std\n\t" - "rep movsq\n\t" - "cld\n\t" - "movq %4, (%5)\n\t" - "jmp 13f\n\t" - - /* - * Start to prepare for backward copy. - */ - ".p2align 4\n\t" - "2:\n\t" - "cmp $680, %0\n\t" - "jb 6f \n\t" - "cmp %%dil, %%sil\n\t" - "je 7b \n\t" - "6:\n\t" - /* - * Calculate copy position to tail. - */ - "addq %0, %1\n\t" - "addq %0, %2\n\t" - "subq $0x20, %0\n\t" - /* - * We gobble 32byts backward in each loop. - */ - "8:\n\t" - "subq $0x20, %0\n\t" - "movq -1*8(%1), %4\n\t" - "movq -2*8(%1), %5\n\t" - "movq -3*8(%1), %6\n\t" - "movq -4*8(%1), %7\n\t" - "leaq -4*8(%1), %1\n\t" - - "movq %4, -1*8(%2)\n\t" - "movq %5, -2*8(%2)\n\t" - "movq %6, -3*8(%2)\n\t" - "movq %7, -4*8(%2)\n\t" - "leaq -4*8(%2), %2\n\t" - "jae 8b\n\t" - /* - * Calculate copy position to head. - */ - "addq $0x20, %0\n\t" - "subq %0, %1\n\t" - "subq %0, %2\n\t" - "1:\n\t" - "cmpq $16, %0\n\t" - "jb 9f\n\t" - /* - * Move data from 16 bytes to 31 bytes. - */ - "movq 0*8(%1), %4\n\t" - "movq 1*8(%1), %5\n\t" - "movq -2*8(%1, %0), %6\n\t" - "movq -1*8(%1, %0), %7\n\t" - "movq %4, 0*8(%2)\n\t" - "movq %5, 1*8(%2)\n\t" - "movq %6, -2*8(%2, %0)\n\t" - "movq %7, -1*8(%2, %0)\n\t" - "jmp 13f\n\t" - ".p2align 4\n\t" - "9:\n\t" - "cmpq $8, %0\n\t" - "jb 10f\n\t" - /* - * Move data from 8 bytes to 15 bytes. - */ - "movq 0*8(%1), %4\n\t" - "movq -1*8(%1, %0), %5\n\t" - "movq %4, 0*8(%2)\n\t" - "movq %5, -1*8(%2, %0)\n\t" - "jmp 13f\n\t" - "10:\n\t" - "cmpq $4, %0\n\t" - "jb 11f\n\t" - /* - * Move data from 4 bytes to 7 bytes. - */ - "movl (%1), %4d\n\t" - "movl -4(%1, %0), %5d\n\t" - "movl %4d, (%2)\n\t" - "movl %5d, -4(%2, %0)\n\t" - "jmp 13f\n\t" - "11:\n\t" - "cmp $2, %0\n\t" - "jb 12f\n\t" - /* - * Move data from 2 bytes to 3 bytes. - */ - "movw (%1), %4w\n\t" - "movw -2(%1, %0), %5w\n\t" - "movw %4w, (%2)\n\t" - "movw %5w, -2(%2, %0)\n\t" - "jmp 13f\n\t" - "12:\n\t" - "cmp $1, %0\n\t" - "jb 13f\n\t" - /* - * Move data for 1 byte. - */ - "movb (%1), %4b\n\t" - "movb %4b, (%2)\n\t" - "13:\n\t" - : "=&d" (d0), "=&S" (d1), "=&D" (d2), "=&a" (ret) , - "=r"(d3), "=r"(d4), "=r"(d5), "=r"(d6), "=&c" (d7) - :"0" (count), - "1" (src), - "2" (dest) - :"memory"); - - return ret; - -} -EXPORT_SYMBOL(memmove); diff --git a/arch/x86/lib/rwsem_64.S b/arch/x86/lib/rwsem_64.S index 41fcf00e49df..67743977398b 100644 --- a/arch/x86/lib/rwsem_64.S +++ b/arch/x86/lib/rwsem_64.S @@ -23,43 +23,50 @@ #include <asm/dwarf2.h> #define save_common_regs \ - pushq %rdi; \ - pushq %rsi; \ - pushq %rcx; \ - pushq %r8; \ - pushq %r9; \ - pushq %r10; \ - pushq %r11 + pushq_cfi %rdi; CFI_REL_OFFSET rdi, 0; \ + pushq_cfi %rsi; CFI_REL_OFFSET rsi, 0; \ + pushq_cfi %rcx; CFI_REL_OFFSET rcx, 0; \ + pushq_cfi %r8; CFI_REL_OFFSET r8, 0; \ + pushq_cfi %r9; CFI_REL_OFFSET r9, 0; \ + pushq_cfi %r10; CFI_REL_OFFSET r10, 0; \ + pushq_cfi %r11; CFI_REL_OFFSET r11, 0 #define restore_common_regs \ - popq %r11; \ - popq %r10; \ - popq %r9; \ - popq %r8; \ - popq %rcx; \ - popq %rsi; \ - popq %rdi + popq_cfi %r11; CFI_RESTORE r11; \ + popq_cfi %r10; CFI_RESTORE r10; \ + popq_cfi %r9; CFI_RESTORE r9; \ + popq_cfi %r8; CFI_RESTORE r8; \ + popq_cfi %rcx; CFI_RESTORE rcx; \ + popq_cfi %rsi; CFI_RESTORE rsi; \ + popq_cfi %rdi; CFI_RESTORE rdi /* Fix up special calling conventions */ ENTRY(call_rwsem_down_read_failed) + CFI_STARTPROC save_common_regs - pushq %rdx + pushq_cfi %rdx + CFI_REL_OFFSET rdx, 0 movq %rax,%rdi call rwsem_down_read_failed - popq %rdx + popq_cfi %rdx + CFI_RESTORE rdx restore_common_regs ret - ENDPROC(call_rwsem_down_read_failed) + CFI_ENDPROC +ENDPROC(call_rwsem_down_read_failed) ENTRY(call_rwsem_down_write_failed) + CFI_STARTPROC save_common_regs movq %rax,%rdi call rwsem_down_write_failed restore_common_regs ret - ENDPROC(call_rwsem_down_write_failed) + CFI_ENDPROC +ENDPROC(call_rwsem_down_write_failed) ENTRY(call_rwsem_wake) + CFI_STARTPROC decl %edx /* do nothing if still outstanding active readers */ jnz 1f save_common_regs @@ -67,15 +74,20 @@ ENTRY(call_rwsem_wake) call rwsem_wake restore_common_regs 1: ret - ENDPROC(call_rwsem_wake) + CFI_ENDPROC +ENDPROC(call_rwsem_wake) /* Fix up special calling conventions */ ENTRY(call_rwsem_downgrade_wake) + CFI_STARTPROC save_common_regs - pushq %rdx + pushq_cfi %rdx + CFI_REL_OFFSET rdx, 0 movq %rax,%rdi call rwsem_downgrade_wake - popq %rdx + popq_cfi %rdx + CFI_RESTORE rdx restore_common_regs ret - ENDPROC(call_rwsem_downgrade_wake) + CFI_ENDPROC +ENDPROC(call_rwsem_downgrade_wake) diff --git a/arch/x86/lib/semaphore_32.S b/arch/x86/lib/semaphore_32.S index 648fe4741782..06691daa4108 100644 --- a/arch/x86/lib/semaphore_32.S +++ b/arch/x86/lib/semaphore_32.S @@ -36,7 +36,7 @@ */ #ifdef CONFIG_SMP ENTRY(__write_lock_failed) - CFI_STARTPROC simple + CFI_STARTPROC FRAME 2: LOCK_PREFIX addl $ RW_LOCK_BIAS,(%eax) @@ -74,29 +74,23 @@ ENTRY(__read_lock_failed) /* Fix up special calling conventions */ ENTRY(call_rwsem_down_read_failed) CFI_STARTPROC - push %ecx - CFI_ADJUST_CFA_OFFSET 4 + pushl_cfi %ecx CFI_REL_OFFSET ecx,0 - push %edx - CFI_ADJUST_CFA_OFFSET 4 + pushl_cfi %edx CFI_REL_OFFSET edx,0 call rwsem_down_read_failed - pop %edx - CFI_ADJUST_CFA_OFFSET -4 - pop %ecx - CFI_ADJUST_CFA_OFFSET -4 + popl_cfi %edx + popl_cfi %ecx ret CFI_ENDPROC ENDPROC(call_rwsem_down_read_failed) ENTRY(call_rwsem_down_write_failed) CFI_STARTPROC - push %ecx - CFI_ADJUST_CFA_OFFSET 4 + pushl_cfi %ecx CFI_REL_OFFSET ecx,0 calll rwsem_down_write_failed - pop %ecx - CFI_ADJUST_CFA_OFFSET -4 + popl_cfi %ecx ret CFI_ENDPROC ENDPROC(call_rwsem_down_write_failed) @@ -105,12 +99,10 @@ ENTRY(call_rwsem_wake) CFI_STARTPROC decw %dx /* do nothing if still outstanding active readers */ jnz 1f - push %ecx - CFI_ADJUST_CFA_OFFSET 4 + pushl_cfi %ecx CFI_REL_OFFSET ecx,0 call rwsem_wake - pop %ecx - CFI_ADJUST_CFA_OFFSET -4 + popl_cfi %ecx 1: ret CFI_ENDPROC ENDPROC(call_rwsem_wake) @@ -118,17 +110,13 @@ ENTRY(call_rwsem_wake) /* Fix up special calling conventions */ ENTRY(call_rwsem_downgrade_wake) CFI_STARTPROC - push %ecx - CFI_ADJUST_CFA_OFFSET 4 + pushl_cfi %ecx CFI_REL_OFFSET ecx,0 - push %edx - CFI_ADJUST_CFA_OFFSET 4 + pushl_cfi %edx CFI_REL_OFFSET edx,0 call rwsem_downgrade_wake - pop %edx - CFI_ADJUST_CFA_OFFSET -4 - pop %ecx - CFI_ADJUST_CFA_OFFSET -4 + popl_cfi %edx + popl_cfi %ecx ret CFI_ENDPROC ENDPROC(call_rwsem_downgrade_wake) diff --git a/arch/x86/lib/thunk_32.S b/arch/x86/lib/thunk_32.S index 650b11e00ecc..2930ae05d773 100644 --- a/arch/x86/lib/thunk_32.S +++ b/arch/x86/lib/thunk_32.S @@ -7,24 +7,6 @@ #include <linux/linkage.h> -#define ARCH_TRACE_IRQS_ON \ - pushl %eax; \ - pushl %ecx; \ - pushl %edx; \ - call trace_hardirqs_on; \ - popl %edx; \ - popl %ecx; \ - popl %eax; - -#define ARCH_TRACE_IRQS_OFF \ - pushl %eax; \ - pushl %ecx; \ - pushl %edx; \ - call trace_hardirqs_off; \ - popl %edx; \ - popl %ecx; \ - popl %eax; - #ifdef CONFIG_TRACE_IRQFLAGS /* put return address in eax (arg1) */ .macro thunk_ra name,func diff --git a/arch/x86/lib/thunk_64.S b/arch/x86/lib/thunk_64.S index bf9a7d5a5428..782b082c9ff7 100644 --- a/arch/x86/lib/thunk_64.S +++ b/arch/x86/lib/thunk_64.S @@ -22,26 +22,6 @@ CFI_ENDPROC .endm - /* rdi: arg1 ... normal C conventions. rax is passed from C. */ - .macro thunk_retrax name,func - .globl \name -\name: - CFI_STARTPROC - SAVE_ARGS - call \func - jmp restore_norax - CFI_ENDPROC - .endm - - - .section .sched.text, "ax" -#ifdef CONFIG_RWSEM_XCHGADD_ALGORITHM - thunk rwsem_down_read_failed_thunk,rwsem_down_read_failed - thunk rwsem_down_write_failed_thunk,rwsem_down_write_failed - thunk rwsem_wake_thunk,rwsem_wake - thunk rwsem_downgrade_thunk,rwsem_downgrade_wake -#endif - #ifdef CONFIG_TRACE_IRQFLAGS /* put return address in rdi (arg1) */ .macro thunk_ra name,func @@ -72,10 +52,3 @@ restore: RESTORE_ARGS ret CFI_ENDPROC - - CFI_STARTPROC - SAVE_ARGS -restore_norax: - RESTORE_ARGS 1 - ret - CFI_ENDPROC diff --git a/arch/x86/mm/Makefile b/arch/x86/mm/Makefile index 09df2f9a3d69..3e608edf9958 100644 --- a/arch/x86/mm/Makefile +++ b/arch/x86/mm/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_MMIOTRACE_TEST) += testmmiotrace.o obj-$(CONFIG_NUMA) += numa.o numa_$(BITS).o obj-$(CONFIG_AMD_NUMA) += amdtopology_64.o obj-$(CONFIG_ACPI_NUMA) += srat_$(BITS).o +obj-$(CONFIG_NUMA_EMU) += numa_emulation.o obj-$(CONFIG_HAVE_MEMBLOCK) += memblock.o diff --git a/arch/x86/mm/amdtopology_64.c b/arch/x86/mm/amdtopology_64.c index f21962c435ed..0919c26820d4 100644 --- a/arch/x86/mm/amdtopology_64.c +++ b/arch/x86/mm/amdtopology_64.c @@ -26,9 +26,7 @@ #include <asm/apic.h> #include <asm/amd_nb.h> -static struct bootnode __initdata nodes[8]; static unsigned char __initdata nodeids[8]; -static nodemask_t __initdata nodes_parsed = NODE_MASK_NONE; static __init int find_northbridge(void) { @@ -51,7 +49,7 @@ static __init int find_northbridge(void) return num; } - return -1; + return -ENOENT; } static __init void early_get_boot_cpu_id(void) @@ -69,17 +67,18 @@ static __init void early_get_boot_cpu_id(void) #endif } -int __init amd_numa_init(unsigned long start_pfn, unsigned long end_pfn) +int __init amd_numa_init(void) { - unsigned long start = PFN_PHYS(start_pfn); - unsigned long end = PFN_PHYS(end_pfn); + unsigned long start = PFN_PHYS(0); + unsigned long end = PFN_PHYS(max_pfn); unsigned numnodes; unsigned long prevbase; - int i, nb, found = 0; + int i, j, nb; u32 nodeid, reg; + unsigned int bits, cores, apicid_base; if (!early_pci_allowed()) - return -1; + return -EINVAL; nb = find_northbridge(); if (nb < 0) @@ -90,7 +89,7 @@ int __init amd_numa_init(unsigned long start_pfn, unsigned long end_pfn) reg = read_pci_config(0, nb, 0, 0x60); numnodes = ((reg >> 4) & 0xF) + 1; if (numnodes <= 1) - return -1; + return -ENOENT; pr_info("Number of physical nodes %d\n", numnodes); @@ -121,9 +120,9 @@ int __init amd_numa_init(unsigned long start_pfn, unsigned long end_pfn) if ((base >> 8) & 3 || (limit >> 8) & 3) { pr_err("Node %d using interleaving mode %lx/%lx\n", nodeid, (base >> 8) & 3, (limit >> 8) & 3); - return -1; + return -EINVAL; } - if (node_isset(nodeid, nodes_parsed)) { + if (node_isset(nodeid, numa_nodes_parsed)) { pr_info("Node %d already present, skipping\n", nodeid); continue; @@ -160,117 +159,28 @@ int __init amd_numa_init(unsigned long start_pfn, unsigned long end_pfn) if (prevbase > base) { pr_err("Node map not sorted %lx,%lx\n", prevbase, base); - return -1; + return -EINVAL; } pr_info("Node %d MemBase %016lx Limit %016lx\n", nodeid, base, limit); - found++; - - nodes[nodeid].start = base; - nodes[nodeid].end = limit; - prevbase = base; - - node_set(nodeid, nodes_parsed); - } - - if (!found) - return -1; - return 0; -} - -#ifdef CONFIG_NUMA_EMU -static s16 fake_apicid_to_node[MAX_LOCAL_APIC] __initdata = { - [0 ... MAX_LOCAL_APIC-1] = NUMA_NO_NODE -}; - -void __init amd_get_nodes(struct bootnode *physnodes) -{ - int i; - - for_each_node_mask(i, nodes_parsed) { - physnodes[i].start = nodes[i].start; - physnodes[i].end = nodes[i].end; + numa_add_memblk(nodeid, base, limit); + node_set(nodeid, numa_nodes_parsed); } -} - -static int __init find_node_by_addr(unsigned long addr) -{ - int ret = NUMA_NO_NODE; - int i; - - for (i = 0; i < 8; i++) - if (addr >= nodes[i].start && addr < nodes[i].end) { - ret = i; - break; - } - return ret; -} -/* - * For NUMA emulation, fake proximity domain (_PXM) to node id mappings must be - * setup to represent the physical topology but reflect the emulated - * environment. For each emulated node, the real node which it appears on is - * found and a fake pxm to nid mapping is created which mirrors the actual - * locality. node_distance() then represents the correct distances between - * emulated nodes by using the fake acpi mappings to pxms. - */ -void __init amd_fake_nodes(const struct bootnode *nodes, int nr_nodes) -{ - unsigned int bits; - unsigned int cores; - unsigned int apicid_base = 0; - int i; + if (!nodes_weight(numa_nodes_parsed)) + return -ENOENT; + /* + * We seem to have valid NUMA configuration. Map apicids to nodes + * using the coreid bits from early_identify_cpu. + */ bits = boot_cpu_data.x86_coreid_bits; cores = 1 << bits; - early_get_boot_cpu_id(); - if (boot_cpu_physical_apicid > 0) - apicid_base = boot_cpu_physical_apicid; - - for (i = 0; i < nr_nodes; i++) { - int index; - int nid; - int j; - - nid = find_node_by_addr(nodes[i].start); - if (nid == NUMA_NO_NODE) - continue; - - index = nodeids[nid] << bits; - if (fake_apicid_to_node[index + apicid_base] == NUMA_NO_NODE) - for (j = apicid_base; j < cores + apicid_base; j++) - fake_apicid_to_node[index + j] = i; -#ifdef CONFIG_ACPI_NUMA - __acpi_map_pxm_to_node(nid, i); -#endif - } - memcpy(apicid_to_node, fake_apicid_to_node, sizeof(apicid_to_node)); -} -#endif /* CONFIG_NUMA_EMU */ - -int __init amd_scan_nodes(void) -{ - unsigned int bits; - unsigned int cores; - unsigned int apicid_base; - int i; - - BUG_ON(nodes_empty(nodes_parsed)); - node_possible_map = nodes_parsed; - memnode_shift = compute_hash_shift(nodes, 8, NULL); - if (memnode_shift < 0) { - pr_err("No NUMA node hash function found. Contact maintainer\n"); - return -1; - } - pr_info("Using node hash shift of %d\n", memnode_shift); - - /* use the coreid bits from early_identify_cpu */ - bits = boot_cpu_data.x86_coreid_bits; - cores = (1<<bits); apicid_base = 0; + /* get the APIC ID of the BSP early for systems with apicid lifting */ early_get_boot_cpu_id(); if (boot_cpu_physical_apicid > 0) { @@ -278,17 +188,9 @@ int __init amd_scan_nodes(void) apicid_base = boot_cpu_physical_apicid; } - for_each_node_mask(i, node_possible_map) { - int j; - - memblock_x86_register_active_regions(i, - nodes[i].start >> PAGE_SHIFT, - nodes[i].end >> PAGE_SHIFT); + for_each_node_mask(i, numa_nodes_parsed) for (j = apicid_base; j < cores + apicid_base; j++) - apicid_to_node[(i << bits) + j] = i; - setup_node_bootmem(i, nodes[i].start, nodes[i].end); - } + set_apicid_to_node((i << bits) + j, i); - numa_init_array(); return 0; } diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index 947f42abe820..286d289b039b 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -18,9 +18,9 @@ DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); -unsigned long __initdata e820_table_start; -unsigned long __meminitdata e820_table_end; -unsigned long __meminitdata e820_table_top; +unsigned long __initdata pgt_buf_start; +unsigned long __meminitdata pgt_buf_end; +unsigned long __meminitdata pgt_buf_top; int after_bootmem; @@ -33,7 +33,7 @@ int direct_gbpages static void __init find_early_table_space(unsigned long end, int use_pse, int use_gbpages) { - unsigned long puds, pmds, ptes, tables, start; + unsigned long puds, pmds, ptes, tables, start = 0, good_end = end; phys_addr_t base; puds = (end + PUD_SIZE - 1) >> PUD_SHIFT; @@ -65,29 +65,20 @@ static void __init find_early_table_space(unsigned long end, int use_pse, #ifdef CONFIG_X86_32 /* for fixmap */ tables += roundup(__end_of_fixed_addresses * sizeof(pte_t), PAGE_SIZE); -#endif - /* - * RED-PEN putting page tables only on node 0 could - * cause a hotspot and fill up ZONE_DMA. The page tables - * need roughly 0.5KB per GB. - */ -#ifdef CONFIG_X86_32 - start = 0x7000; -#else - start = 0x8000; + good_end = max_pfn_mapped << PAGE_SHIFT; #endif - base = memblock_find_in_range(start, max_pfn_mapped<<PAGE_SHIFT, - tables, PAGE_SIZE); + + base = memblock_find_in_range(start, good_end, tables, PAGE_SIZE); if (base == MEMBLOCK_ERROR) panic("Cannot find space for the kernel page tables"); - e820_table_start = base >> PAGE_SHIFT; - e820_table_end = e820_table_start; - e820_table_top = e820_table_start + (tables >> PAGE_SHIFT); + pgt_buf_start = base >> PAGE_SHIFT; + pgt_buf_end = pgt_buf_start; + pgt_buf_top = pgt_buf_start + (tables >> PAGE_SHIFT); printk(KERN_DEBUG "kernel direct mapping tables up to %lx @ %lx-%lx\n", - end, e820_table_start << PAGE_SHIFT, e820_table_top << PAGE_SHIFT); + end, pgt_buf_start << PAGE_SHIFT, pgt_buf_top << PAGE_SHIFT); } struct map_range { @@ -279,30 +270,11 @@ unsigned long __init_refok init_memory_mapping(unsigned long start, load_cr3(swapper_pg_dir); #endif -#ifdef CONFIG_X86_64 - if (!after_bootmem && !start) { - pud_t *pud; - pmd_t *pmd; - - mmu_cr4_features = read_cr4(); - - /* - * _brk_end cannot change anymore, but it and _end may be - * located on different 2M pages. cleanup_highmap(), however, - * can only consider _end when it runs, so destroy any - * mappings beyond _brk_end here. - */ - pud = pud_offset(pgd_offset_k(_brk_end), _brk_end); - pmd = pmd_offset(pud, _brk_end - 1); - while (++pmd <= pmd_offset(pud, (unsigned long)_end - 1)) - pmd_clear(pmd); - } -#endif __flush_tlb_all(); - if (!after_bootmem && e820_table_end > e820_table_start) - memblock_x86_reserve_range(e820_table_start << PAGE_SHIFT, - e820_table_end << PAGE_SHIFT, "PGTABLE"); + if (!after_bootmem && pgt_buf_end > pgt_buf_start) + memblock_x86_reserve_range(pgt_buf_start << PAGE_SHIFT, + pgt_buf_end << PAGE_SHIFT, "PGTABLE"); if (!after_bootmem) early_memtest(start, end); diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c index c821074b7f0b..73ad7ebd6e9c 100644 --- a/arch/x86/mm/init_32.c +++ b/arch/x86/mm/init_32.c @@ -62,10 +62,10 @@ bool __read_mostly __vmalloc_start_set = false; static __init void *alloc_low_page(void) { - unsigned long pfn = e820_table_end++; + unsigned long pfn = pgt_buf_end++; void *adr; - if (pfn >= e820_table_top) + if (pfn >= pgt_buf_top) panic("alloc_low_page: ran out of memory"); adr = __va(pfn * PAGE_SIZE); @@ -163,8 +163,8 @@ static pte_t *__init page_table_kmap_check(pte_t *pte, pmd_t *pmd, if (pmd_idx_kmap_begin != pmd_idx_kmap_end && (vaddr >> PMD_SHIFT) >= pmd_idx_kmap_begin && (vaddr >> PMD_SHIFT) <= pmd_idx_kmap_end - && ((__pa(pte) >> PAGE_SHIFT) < e820_table_start - || (__pa(pte) >> PAGE_SHIFT) >= e820_table_end)) { + && ((__pa(pte) >> PAGE_SHIFT) < pgt_buf_start + || (__pa(pte) >> PAGE_SHIFT) >= pgt_buf_end)) { pte_t *newpte; int i; @@ -644,8 +644,7 @@ void __init find_low_pfn_range(void) } #ifndef CONFIG_NEED_MULTIPLE_NODES -void __init initmem_init(unsigned long start_pfn, unsigned long end_pfn, - int acpi, int k8) +void __init initmem_init(void) { #ifdef CONFIG_HIGHMEM highstart_pfn = highend_pfn = max_pfn; diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c index c14a5422e152..0aa34669ed3f 100644 --- a/arch/x86/mm/init_64.c +++ b/arch/x86/mm/init_64.c @@ -51,6 +51,7 @@ #include <asm/numa.h> #include <asm/cacheflush.h> #include <asm/init.h> +#include <asm/uv/uv.h> static int __init parse_direct_gbpages_off(char *arg) { @@ -314,7 +315,7 @@ void __init cleanup_highmap(void) static __ref void *alloc_low_page(unsigned long *phys) { - unsigned long pfn = e820_table_end++; + unsigned long pfn = pgt_buf_end++; void *adr; if (after_bootmem) { @@ -324,7 +325,7 @@ static __ref void *alloc_low_page(unsigned long *phys) return adr; } - if (pfn >= e820_table_top) + if (pfn >= pgt_buf_top) panic("alloc_low_page: ran out of memory"); adr = early_memremap(pfn * PAGE_SIZE, PAGE_SIZE); @@ -333,12 +334,28 @@ static __ref void *alloc_low_page(unsigned long *phys) return adr; } +static __ref void *map_low_page(void *virt) +{ + void *adr; + unsigned long phys, left; + + if (after_bootmem) + return virt; + + phys = __pa(virt); + left = phys & (PAGE_SIZE - 1); + adr = early_memremap(phys & PAGE_MASK, PAGE_SIZE); + adr = (void *)(((unsigned long)adr) | left); + + return adr; +} + static __ref void unmap_low_page(void *adr) { if (after_bootmem) return; - early_iounmap(adr, PAGE_SIZE); + early_iounmap((void *)((unsigned long)adr & PAGE_MASK), PAGE_SIZE); } static unsigned long __meminit @@ -386,15 +403,6 @@ phys_pte_init(pte_t *pte_page, unsigned long addr, unsigned long end, } static unsigned long __meminit -phys_pte_update(pmd_t *pmd, unsigned long address, unsigned long end, - pgprot_t prot) -{ - pte_t *pte = (pte_t *)pmd_page_vaddr(*pmd); - - return phys_pte_init(pte, address, end, prot); -} - -static unsigned long __meminit phys_pmd_init(pmd_t *pmd_page, unsigned long address, unsigned long end, unsigned long page_size_mask, pgprot_t prot) { @@ -420,8 +428,10 @@ phys_pmd_init(pmd_t *pmd_page, unsigned long address, unsigned long end, if (pmd_val(*pmd)) { if (!pmd_large(*pmd)) { spin_lock(&init_mm.page_table_lock); - last_map_addr = phys_pte_update(pmd, address, + pte = map_low_page((pte_t *)pmd_page_vaddr(*pmd)); + last_map_addr = phys_pte_init(pte, address, end, prot); + unmap_low_page(pte); spin_unlock(&init_mm.page_table_lock); continue; } @@ -468,18 +478,6 @@ phys_pmd_init(pmd_t *pmd_page, unsigned long address, unsigned long end, } static unsigned long __meminit -phys_pmd_update(pud_t *pud, unsigned long address, unsigned long end, - unsigned long page_size_mask, pgprot_t prot) -{ - pmd_t *pmd = pmd_offset(pud, 0); - unsigned long last_map_addr; - - last_map_addr = phys_pmd_init(pmd, address, end, page_size_mask, prot); - __flush_tlb_all(); - return last_map_addr; -} - -static unsigned long __meminit phys_pud_init(pud_t *pud_page, unsigned long addr, unsigned long end, unsigned long page_size_mask) { @@ -504,8 +502,11 @@ phys_pud_init(pud_t *pud_page, unsigned long addr, unsigned long end, if (pud_val(*pud)) { if (!pud_large(*pud)) { - last_map_addr = phys_pmd_update(pud, addr, end, + pmd = map_low_page(pmd_offset(pud, 0)); + last_map_addr = phys_pmd_init(pmd, addr, end, page_size_mask, prot); + unmap_low_page(pmd); + __flush_tlb_all(); continue; } /* @@ -553,17 +554,6 @@ phys_pud_init(pud_t *pud_page, unsigned long addr, unsigned long end, return last_map_addr; } -static unsigned long __meminit -phys_pud_update(pgd_t *pgd, unsigned long addr, unsigned long end, - unsigned long page_size_mask) -{ - pud_t *pud; - - pud = (pud_t *)pgd_page_vaddr(*pgd); - - return phys_pud_init(pud, addr, end, page_size_mask); -} - unsigned long __meminit kernel_physical_mapping_init(unsigned long start, unsigned long end, @@ -587,8 +577,10 @@ kernel_physical_mapping_init(unsigned long start, next = end; if (pgd_val(*pgd)) { - last_map_addr = phys_pud_update(pgd, __pa(start), + pud = map_low_page((pud_t *)pgd_page_vaddr(*pgd)); + last_map_addr = phys_pud_init(pud, __pa(start), __pa(end), page_size_mask); + unmap_low_page(pud); continue; } @@ -612,10 +604,9 @@ kernel_physical_mapping_init(unsigned long start, } #ifndef CONFIG_NUMA -void __init initmem_init(unsigned long start_pfn, unsigned long end_pfn, - int acpi, int k8) +void __init initmem_init(void) { - memblock_x86_register_active_regions(0, start_pfn, end_pfn); + memblock_x86_register_active_regions(0, 0, max_pfn); } #endif @@ -908,6 +899,19 @@ const char *arch_vma_name(struct vm_area_struct *vma) return NULL; } +#ifdef CONFIG_X86_UV +#define MIN_MEMORY_BLOCK_SIZE (1 << SECTION_SIZE_BITS) + +unsigned long memory_block_size_bytes(void) +{ + if (is_uv_system()) { + printk(KERN_INFO "UV: memory block size 2GB\n"); + return 2UL * 1024 * 1024 * 1024; + } + return MIN_MEMORY_BLOCK_SIZE; +} +#endif + #ifdef CONFIG_SPARSEMEM_VMEMMAP /* * Initialise the sparsemem vmemmap using huge-pages at the PMD level. diff --git a/arch/x86/mm/numa.c b/arch/x86/mm/numa.c index ebf6d7887a38..9559d360fde7 100644 --- a/arch/x86/mm/numa.c +++ b/arch/x86/mm/numa.c @@ -26,12 +26,50 @@ static __init int numa_setup(char *opt) early_param("numa", numa_setup); /* - * Which logical CPUs are on which nodes + * apicid, cpu, node mappings */ +s16 __apicid_to_node[MAX_LOCAL_APIC] __cpuinitdata = { + [0 ... MAX_LOCAL_APIC-1] = NUMA_NO_NODE +}; + cpumask_var_t node_to_cpumask_map[MAX_NUMNODES]; EXPORT_SYMBOL(node_to_cpumask_map); /* + * Map cpu index to node index + */ +DEFINE_EARLY_PER_CPU(int, x86_cpu_to_node_map, NUMA_NO_NODE); +EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_node_map); + +void __cpuinit numa_set_node(int cpu, int node) +{ + int *cpu_to_node_map = early_per_cpu_ptr(x86_cpu_to_node_map); + + /* early setting, no percpu area yet */ + if (cpu_to_node_map) { + cpu_to_node_map[cpu] = node; + return; + } + +#ifdef CONFIG_DEBUG_PER_CPU_MAPS + if (cpu >= nr_cpu_ids || !cpu_possible(cpu)) { + printk(KERN_ERR "numa_set_node: invalid cpu# (%d)\n", cpu); + dump_stack(); + return; + } +#endif + per_cpu(x86_cpu_to_node_map, cpu) = node; + + if (node != NUMA_NO_NODE) + set_cpu_numa_node(cpu, node); +} + +void __cpuinit numa_clear_node(int cpu) +{ + numa_set_node(cpu, NUMA_NO_NODE); +} + +/* * Allocate node_to_cpumask_map based on number of available nodes * Requires node_possible_map to be valid. * @@ -57,7 +95,174 @@ void __init setup_node_to_cpumask_map(void) pr_debug("Node to cpumask map for %d nodes\n", nr_node_ids); } -#ifdef CONFIG_DEBUG_PER_CPU_MAPS +/* + * There are unfortunately some poorly designed mainboards around that + * only connect memory to a single CPU. This breaks the 1:1 cpu->node + * mapping. To avoid this fill in the mapping for all possible CPUs, + * as the number of CPUs is not known yet. We round robin the existing + * nodes. + */ +void __init numa_init_array(void) +{ + int rr, i; + + rr = first_node(node_online_map); + for (i = 0; i < nr_cpu_ids; i++) { + if (early_cpu_to_node(i) != NUMA_NO_NODE) + continue; + numa_set_node(i, rr); + rr = next_node(rr, node_online_map); + if (rr == MAX_NUMNODES) + rr = first_node(node_online_map); + } +} + +static __init int find_near_online_node(int node) +{ + int n, val; + int min_val = INT_MAX; + int best_node = -1; + + for_each_online_node(n) { + val = node_distance(node, n); + + if (val < min_val) { + min_val = val; + best_node = n; + } + } + + return best_node; +} + +/* + * Setup early cpu_to_node. + * + * Populate cpu_to_node[] only if x86_cpu_to_apicid[], + * and apicid_to_node[] tables have valid entries for a CPU. + * This means we skip cpu_to_node[] initialisation for NUMA + * emulation and faking node case (when running a kernel compiled + * for NUMA on a non NUMA box), which is OK as cpu_to_node[] + * is already initialized in a round robin manner at numa_init_array, + * prior to this call, and this initialization is good enough + * for the fake NUMA cases. + * + * Called before the per_cpu areas are setup. + */ +void __init init_cpu_to_node(void) +{ + int cpu; + u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); + + BUG_ON(cpu_to_apicid == NULL); + + for_each_possible_cpu(cpu) { + int node = numa_cpu_node(cpu); + + if (node == NUMA_NO_NODE) + continue; + if (!node_online(node)) + node = find_near_online_node(node); + numa_set_node(cpu, node); + } +} + +#ifndef CONFIG_DEBUG_PER_CPU_MAPS + +# ifndef CONFIG_NUMA_EMU +void __cpuinit numa_add_cpu(int cpu) +{ + cpumask_set_cpu(cpu, node_to_cpumask_map[early_cpu_to_node(cpu)]); +} + +void __cpuinit numa_remove_cpu(int cpu) +{ + cpumask_clear_cpu(cpu, node_to_cpumask_map[early_cpu_to_node(cpu)]); +} +# endif /* !CONFIG_NUMA_EMU */ + +#else /* !CONFIG_DEBUG_PER_CPU_MAPS */ + +int __cpu_to_node(int cpu) +{ + if (early_per_cpu_ptr(x86_cpu_to_node_map)) { + printk(KERN_WARNING + "cpu_to_node(%d): usage too early!\n", cpu); + dump_stack(); + return early_per_cpu_ptr(x86_cpu_to_node_map)[cpu]; + } + return per_cpu(x86_cpu_to_node_map, cpu); +} +EXPORT_SYMBOL(__cpu_to_node); + +/* + * Same function as cpu_to_node() but used if called before the + * per_cpu areas are setup. + */ +int early_cpu_to_node(int cpu) +{ + if (early_per_cpu_ptr(x86_cpu_to_node_map)) + return early_per_cpu_ptr(x86_cpu_to_node_map)[cpu]; + + if (!cpu_possible(cpu)) { + printk(KERN_WARNING + "early_cpu_to_node(%d): no per_cpu area!\n", cpu); + dump_stack(); + return NUMA_NO_NODE; + } + return per_cpu(x86_cpu_to_node_map, cpu); +} + +struct cpumask __cpuinit *debug_cpumask_set_cpu(int cpu, int enable) +{ + int node = early_cpu_to_node(cpu); + struct cpumask *mask; + char buf[64]; + + if (node == NUMA_NO_NODE) { + /* early_cpu_to_node() already emits a warning and trace */ + return NULL; + } + mask = node_to_cpumask_map[node]; + if (!mask) { + pr_err("node_to_cpumask_map[%i] NULL\n", node); + dump_stack(); + return NULL; + } + + cpulist_scnprintf(buf, sizeof(buf), mask); + printk(KERN_DEBUG "%s cpu %d node %d: mask now %s\n", + enable ? "numa_add_cpu" : "numa_remove_cpu", + cpu, node, buf); + return mask; +} + +# ifndef CONFIG_NUMA_EMU +static void __cpuinit numa_set_cpumask(int cpu, int enable) +{ + struct cpumask *mask; + + mask = debug_cpumask_set_cpu(cpu, enable); + if (!mask) + return; + + if (enable) + cpumask_set_cpu(cpu, mask); + else + cpumask_clear_cpu(cpu, mask); +} + +void __cpuinit numa_add_cpu(int cpu) +{ + numa_set_cpumask(cpu, 1); +} + +void __cpuinit numa_remove_cpu(int cpu) +{ + numa_set_cpumask(cpu, 0); +} +# endif /* !CONFIG_NUMA_EMU */ + /* * Returns a pointer to the bitmask of CPUs on Node 'node'. */ @@ -80,4 +285,5 @@ const struct cpumask *cpumask_of_node(int node) return node_to_cpumask_map[node]; } EXPORT_SYMBOL(cpumask_of_node); -#endif + +#endif /* !CONFIG_DEBUG_PER_CPU_MAPS */ diff --git a/arch/x86/mm/numa_32.c b/arch/x86/mm/numa_32.c index 84a3e4c9f277..bde3906420df 100644 --- a/arch/x86/mm/numa_32.c +++ b/arch/x86/mm/numa_32.c @@ -110,6 +110,12 @@ void set_pmd_pfn(unsigned long vaddr, unsigned long pfn, pgprot_t flags); static unsigned long kva_start_pfn; static unsigned long kva_pages; + +int __cpuinit numa_cpu_node(int cpu) +{ + return apic->x86_32_numa_cpu_node(cpu); +} + /* * FLAT - support for basic PC memory model with discontig enabled, essentially * a single node with all available processors in it with a flat @@ -346,8 +352,7 @@ static void init_remap_allocator(int nid) (ulong) node_remap_end_vaddr[nid]); } -void __init initmem_init(unsigned long start_pfn, unsigned long end_pfn, - int acpi, int k8) +void __init initmem_init(void) { int nid; long kva_target_pfn; @@ -361,6 +366,7 @@ void __init initmem_init(unsigned long start_pfn, unsigned long end_pfn, */ get_memcfg_numa(); + numa_init_array(); kva_pages = roundup(calculate_numa_remap_pages(), PTRS_PER_PTE); diff --git a/arch/x86/mm/numa_64.c b/arch/x86/mm/numa_64.c index 1337c51b07d7..9ec0f209a6a4 100644 --- a/arch/x86/mm/numa_64.c +++ b/arch/x86/mm/numa_64.c @@ -13,31 +13,30 @@ #include <linux/module.h> #include <linux/nodemask.h> #include <linux/sched.h> +#include <linux/acpi.h> #include <asm/e820.h> #include <asm/proto.h> #include <asm/dma.h> -#include <asm/numa.h> #include <asm/acpi.h> #include <asm/amd_nb.h> +#include "numa_internal.h" + struct pglist_data *node_data[MAX_NUMNODES] __read_mostly; EXPORT_SYMBOL(node_data); -struct memnode memnode; +nodemask_t numa_nodes_parsed __initdata; -s16 apicid_to_node[MAX_LOCAL_APIC] __cpuinitdata = { - [0 ... MAX_LOCAL_APIC-1] = NUMA_NO_NODE -}; +struct memnode memnode; static unsigned long __initdata nodemap_addr; static unsigned long __initdata nodemap_size; -/* - * Map cpu index to node index - */ -DEFINE_EARLY_PER_CPU(int, x86_cpu_to_node_map, NUMA_NO_NODE); -EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_node_map); +static struct numa_meminfo numa_meminfo __initdata; + +static int numa_distance_cnt; +static u8 *numa_distance; /* * Given a shift value, try to populate memnodemap[] @@ -46,16 +45,15 @@ EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_node_map); * 0 if memnodmap[] too small (of shift too small) * -1 if node overlap or lost ram (shift too big) */ -static int __init populate_memnodemap(const struct bootnode *nodes, - int numnodes, int shift, int *nodeids) +static int __init populate_memnodemap(const struct numa_meminfo *mi, int shift) { unsigned long addr, end; int i, res = -1; memset(memnodemap, 0xff, sizeof(s16)*memnodemapsize); - for (i = 0; i < numnodes; i++) { - addr = nodes[i].start; - end = nodes[i].end; + for (i = 0; i < mi->nr_blks; i++) { + addr = mi->blk[i].start; + end = mi->blk[i].end; if (addr >= end) continue; if ((end >> shift) >= memnodemapsize) @@ -63,12 +61,7 @@ static int __init populate_memnodemap(const struct bootnode *nodes, do { if (memnodemap[addr >> shift] != NUMA_NO_NODE) return -1; - - if (!nodeids) - memnodemap[addr >> shift] = i; - else - memnodemap[addr >> shift] = nodeids[i]; - + memnodemap[addr >> shift] = mi->blk[i].nid; addr += (1UL << shift); } while (addr < end); res = 1; @@ -86,7 +79,7 @@ static int __init allocate_cachealigned_memnodemap(void) addr = 0x8000; nodemap_size = roundup(sizeof(s16) * memnodemapsize, L1_CACHE_BYTES); - nodemap_addr = memblock_find_in_range(addr, max_pfn<<PAGE_SHIFT, + nodemap_addr = memblock_find_in_range(addr, get_max_mapped(), nodemap_size, L1_CACHE_BYTES); if (nodemap_addr == MEMBLOCK_ERROR) { printk(KERN_ERR @@ -106,16 +99,15 @@ static int __init allocate_cachealigned_memnodemap(void) * The LSB of all start and end addresses in the node map is the value of the * maximum possible shift. */ -static int __init extract_lsb_from_nodes(const struct bootnode *nodes, - int numnodes) +static int __init extract_lsb_from_nodes(const struct numa_meminfo *mi) { int i, nodes_used = 0; unsigned long start, end; unsigned long bitfield = 0, memtop = 0; - for (i = 0; i < numnodes; i++) { - start = nodes[i].start; - end = nodes[i].end; + for (i = 0; i < mi->nr_blks; i++) { + start = mi->blk[i].start; + end = mi->blk[i].end; if (start >= end) continue; bitfield |= start; @@ -131,18 +123,17 @@ static int __init extract_lsb_from_nodes(const struct bootnode *nodes, return i; } -int __init compute_hash_shift(struct bootnode *nodes, int numnodes, - int *nodeids) +static int __init compute_hash_shift(const struct numa_meminfo *mi) { int shift; - shift = extract_lsb_from_nodes(nodes, numnodes); + shift = extract_lsb_from_nodes(mi); if (allocate_cachealigned_memnodemap()) return -1; printk(KERN_DEBUG "NUMA: Using %d for the hash shift.\n", shift); - if (populate_memnodemap(nodes, numnodes, shift, nodeids) != 1) { + if (populate_memnodemap(mi, shift) != 1) { printk(KERN_INFO "Your memory is not aligned you need to " "rebuild your kernel with a bigger NODEMAPSIZE " "shift=%d\n", shift); @@ -188,6 +179,63 @@ static void * __init early_node_mem(int nodeid, unsigned long start, return NULL; } +static int __init numa_add_memblk_to(int nid, u64 start, u64 end, + struct numa_meminfo *mi) +{ + /* ignore zero length blks */ + if (start == end) + return 0; + + /* whine about and ignore invalid blks */ + if (start > end || nid < 0 || nid >= MAX_NUMNODES) { + pr_warning("NUMA: Warning: invalid memblk node %d (%Lx-%Lx)\n", + nid, start, end); + return 0; + } + + if (mi->nr_blks >= NR_NODE_MEMBLKS) { + pr_err("NUMA: too many memblk ranges\n"); + return -EINVAL; + } + + mi->blk[mi->nr_blks].start = start; + mi->blk[mi->nr_blks].end = end; + mi->blk[mi->nr_blks].nid = nid; + mi->nr_blks++; + return 0; +} + +/** + * numa_remove_memblk_from - Remove one numa_memblk from a numa_meminfo + * @idx: Index of memblk to remove + * @mi: numa_meminfo to remove memblk from + * + * Remove @idx'th numa_memblk from @mi by shifting @mi->blk[] and + * decrementing @mi->nr_blks. + */ +void __init numa_remove_memblk_from(int idx, struct numa_meminfo *mi) +{ + mi->nr_blks--; + memmove(&mi->blk[idx], &mi->blk[idx + 1], + (mi->nr_blks - idx) * sizeof(mi->blk[0])); +} + +/** + * numa_add_memblk - Add one numa_memblk to numa_meminfo + * @nid: NUMA node ID of the new memblk + * @start: Start address of the new memblk + * @end: End address of the new memblk + * + * Add a new memblk to the default numa_meminfo. + * + * RETURNS: + * 0 on success, -errno on failure. + */ +int __init numa_add_memblk(int nid, u64 start, u64 end) +{ + return numa_add_memblk_to(nid, start, end, &numa_meminfo); +} + /* Initialize bootmem allocator for a node */ void __init setup_node_bootmem(int nodeid, unsigned long start, unsigned long end) @@ -234,692 +282,386 @@ setup_node_bootmem(int nodeid, unsigned long start, unsigned long end) node_set_online(nodeid); } -/* - * There are unfortunately some poorly designed mainboards around that - * only connect memory to a single CPU. This breaks the 1:1 cpu->node - * mapping. To avoid this fill in the mapping for all possible CPUs, - * as the number of CPUs is not known yet. We round robin the existing - * nodes. +/** + * numa_cleanup_meminfo - Cleanup a numa_meminfo + * @mi: numa_meminfo to clean up + * + * Sanitize @mi by merging and removing unncessary memblks. Also check for + * conflicts and clear unused memblks. + * + * RETURNS: + * 0 on success, -errno on failure. */ -void __init numa_init_array(void) +int __init numa_cleanup_meminfo(struct numa_meminfo *mi) { - int rr, i; + const u64 low = 0; + const u64 high = (u64)max_pfn << PAGE_SHIFT; + int i, j, k; - rr = first_node(node_online_map); - for (i = 0; i < nr_cpu_ids; i++) { - if (early_cpu_to_node(i) != NUMA_NO_NODE) - continue; - numa_set_node(i, rr); - rr = next_node(rr, node_online_map); - if (rr == MAX_NUMNODES) - rr = first_node(node_online_map); - } -} - -#ifdef CONFIG_NUMA_EMU -/* Numa emulation */ -static struct bootnode nodes[MAX_NUMNODES] __initdata; -static struct bootnode physnodes[MAX_NUMNODES] __cpuinitdata; -static char *cmdline __initdata; + for (i = 0; i < mi->nr_blks; i++) { + struct numa_memblk *bi = &mi->blk[i]; -void __init numa_emu_cmdline(char *str) -{ - cmdline = str; -} + /* make sure all blocks are inside the limits */ + bi->start = max(bi->start, low); + bi->end = min(bi->end, high); -static int __init setup_physnodes(unsigned long start, unsigned long end, - int acpi, int amd) -{ - int ret = 0; - int i; - - memset(physnodes, 0, sizeof(physnodes)); -#ifdef CONFIG_ACPI_NUMA - if (acpi) - acpi_get_nodes(physnodes, start, end); -#endif -#ifdef CONFIG_AMD_NUMA - if (amd) - amd_get_nodes(physnodes); -#endif - /* - * Basic sanity checking on the physical node map: there may be errors - * if the SRAT or AMD code incorrectly reported the topology or the mem= - * kernel parameter is used. - */ - for (i = 0; i < MAX_NUMNODES; i++) { - if (physnodes[i].start == physnodes[i].end) - continue; - if (physnodes[i].start > end) { - physnodes[i].end = physnodes[i].start; - continue; - } - if (physnodes[i].end < start) { - physnodes[i].start = physnodes[i].end; + /* and there's no empty block */ + if (bi->start == bi->end) { + numa_remove_memblk_from(i--, mi); continue; } - if (physnodes[i].start < start) - physnodes[i].start = start; - if (physnodes[i].end > end) - physnodes[i].end = end; - ret++; - } - /* - * If no physical topology was detected, a single node is faked to cover - * the entire address space. - */ - if (!ret) { - physnodes[ret].start = start; - physnodes[ret].end = end; - ret = 1; - } - return ret; -} - -static void __init fake_physnodes(int acpi, int amd, int nr_nodes) -{ - int i; - - BUG_ON(acpi && amd); -#ifdef CONFIG_ACPI_NUMA - if (acpi) - acpi_fake_nodes(nodes, nr_nodes); -#endif -#ifdef CONFIG_AMD_NUMA - if (amd) - amd_fake_nodes(nodes, nr_nodes); -#endif - if (!acpi && !amd) - for (i = 0; i < nr_cpu_ids; i++) - numa_set_node(i, 0); -} - -/* - * Setups up nid to range from addr to addr + size. If the end - * boundary is greater than max_addr, then max_addr is used instead. - * The return value is 0 if there is additional memory left for - * allocation past addr and -1 otherwise. addr is adjusted to be at - * the end of the node. - */ -static int __init setup_node_range(int nid, u64 *addr, u64 size, u64 max_addr) -{ - int ret = 0; - nodes[nid].start = *addr; - *addr += size; - if (*addr >= max_addr) { - *addr = max_addr; - ret = -1; - } - nodes[nid].end = *addr; - node_set(nid, node_possible_map); - printk(KERN_INFO "Faking node %d at %016Lx-%016Lx (%LuMB)\n", nid, - nodes[nid].start, nodes[nid].end, - (nodes[nid].end - nodes[nid].start) >> 20); - return ret; -} - -/* - * Sets up nr_nodes fake nodes interleaved over physical nodes ranging from addr - * to max_addr. The return value is the number of nodes allocated. - */ -static int __init split_nodes_interleave(u64 addr, u64 max_addr, int nr_nodes) -{ - nodemask_t physnode_mask = NODE_MASK_NONE; - u64 size; - int big; - int ret = 0; - int i; - - if (nr_nodes <= 0) - return -1; - if (nr_nodes > MAX_NUMNODES) { - pr_info("numa=fake=%d too large, reducing to %d\n", - nr_nodes, MAX_NUMNODES); - nr_nodes = MAX_NUMNODES; - } - - size = (max_addr - addr - memblock_x86_hole_size(addr, max_addr)) / nr_nodes; - /* - * Calculate the number of big nodes that can be allocated as a result - * of consolidating the remainder. - */ - big = ((size & ~FAKE_NODE_MIN_HASH_MASK) * nr_nodes) / - FAKE_NODE_MIN_SIZE; - - size &= FAKE_NODE_MIN_HASH_MASK; - if (!size) { - pr_err("Not enough memory for each node. " - "NUMA emulation disabled.\n"); - return -1; - } - - for (i = 0; i < MAX_NUMNODES; i++) - if (physnodes[i].start != physnodes[i].end) - node_set(i, physnode_mask); - - /* - * Continue to fill physical nodes with fake nodes until there is no - * memory left on any of them. - */ - while (nodes_weight(physnode_mask)) { - for_each_node_mask(i, physnode_mask) { - u64 end = physnodes[i].start + size; - u64 dma32_end = PFN_PHYS(MAX_DMA32_PFN); - - if (ret < big) - end += FAKE_NODE_MIN_SIZE; + for (j = i + 1; j < mi->nr_blks; j++) { + struct numa_memblk *bj = &mi->blk[j]; + unsigned long start, end; /* - * Continue to add memory to this fake node if its - * non-reserved memory is less than the per-node size. + * See whether there are overlapping blocks. Whine + * about but allow overlaps of the same nid. They + * will be merged below. */ - while (end - physnodes[i].start - - memblock_x86_hole_size(physnodes[i].start, end) < size) { - end += FAKE_NODE_MIN_SIZE; - if (end > physnodes[i].end) { - end = physnodes[i].end; - break; + if (bi->end > bj->start && bi->start < bj->end) { + if (bi->nid != bj->nid) { + pr_err("NUMA: node %d (%Lx-%Lx) overlaps with node %d (%Lx-%Lx)\n", + bi->nid, bi->start, bi->end, + bj->nid, bj->start, bj->end); + return -EINVAL; } + pr_warning("NUMA: Warning: node %d (%Lx-%Lx) overlaps with itself (%Lx-%Lx)\n", + bi->nid, bi->start, bi->end, + bj->start, bj->end); } /* - * If there won't be at least FAKE_NODE_MIN_SIZE of - * non-reserved memory in ZONE_DMA32 for the next node, - * this one must extend to the boundary. - */ - if (end < dma32_end && dma32_end - end - - memblock_x86_hole_size(end, dma32_end) < FAKE_NODE_MIN_SIZE) - end = dma32_end; - - /* - * If there won't be enough non-reserved memory for the - * next node, this one must extend to the end of the - * physical node. + * Join together blocks on the same node, holes + * between which don't overlap with memory on other + * nodes. */ - if (physnodes[i].end - end - - memblock_x86_hole_size(end, physnodes[i].end) < size) - end = physnodes[i].end; - - /* - * Avoid allocating more nodes than requested, which can - * happen as a result of rounding down each node's size - * to FAKE_NODE_MIN_SIZE. - */ - if (nodes_weight(physnode_mask) + ret >= nr_nodes) - end = physnodes[i].end; - - if (setup_node_range(ret++, &physnodes[i].start, - end - physnodes[i].start, - physnodes[i].end) < 0) - node_clear(i, physnode_mask); + if (bi->nid != bj->nid) + continue; + start = max(min(bi->start, bj->start), low); + end = min(max(bi->end, bj->end), high); + for (k = 0; k < mi->nr_blks; k++) { + struct numa_memblk *bk = &mi->blk[k]; + + if (bi->nid == bk->nid) + continue; + if (start < bk->end && end > bk->start) + break; + } + if (k < mi->nr_blks) + continue; + printk(KERN_INFO "NUMA: Node %d [%Lx,%Lx) + [%Lx,%Lx) -> [%lx,%lx)\n", + bi->nid, bi->start, bi->end, bj->start, bj->end, + start, end); + bi->start = start; + bi->end = end; + numa_remove_memblk_from(j--, mi); } } - return ret; -} - -/* - * Returns the end address of a node so that there is at least `size' amount of - * non-reserved memory or `max_addr' is reached. - */ -static u64 __init find_end_of_node(u64 start, u64 max_addr, u64 size) -{ - u64 end = start + size; - while (end - start - memblock_x86_hole_size(start, end) < size) { - end += FAKE_NODE_MIN_SIZE; - if (end > max_addr) { - end = max_addr; - break; - } + for (i = mi->nr_blks; i < ARRAY_SIZE(mi->blk); i++) { + mi->blk[i].start = mi->blk[i].end = 0; + mi->blk[i].nid = NUMA_NO_NODE; } - return end; + + return 0; } /* - * Sets up fake nodes of `size' interleaved over physical nodes ranging from - * `addr' to `max_addr'. The return value is the number of nodes allocated. + * Set nodes, which have memory in @mi, in *@nodemask. */ -static int __init split_nodes_size_interleave(u64 addr, u64 max_addr, u64 size) +static void __init numa_nodemask_from_meminfo(nodemask_t *nodemask, + const struct numa_meminfo *mi) { - nodemask_t physnode_mask = NODE_MASK_NONE; - u64 min_size; - int ret = 0; int i; - if (!size) - return -1; - /* - * The limit on emulated nodes is MAX_NUMNODES, so the size per node is - * increased accordingly if the requested size is too small. This - * creates a uniform distribution of node sizes across the entire - * machine (but not necessarily over physical nodes). - */ - min_size = (max_addr - addr - memblock_x86_hole_size(addr, max_addr)) / - MAX_NUMNODES; - min_size = max(min_size, FAKE_NODE_MIN_SIZE); - if ((min_size & FAKE_NODE_MIN_HASH_MASK) < min_size) - min_size = (min_size + FAKE_NODE_MIN_SIZE) & - FAKE_NODE_MIN_HASH_MASK; - if (size < min_size) { - pr_err("Fake node size %LuMB too small, increasing to %LuMB\n", - size >> 20, min_size >> 20); - size = min_size; - } - size &= FAKE_NODE_MIN_HASH_MASK; - - for (i = 0; i < MAX_NUMNODES; i++) - if (physnodes[i].start != physnodes[i].end) - node_set(i, physnode_mask); - /* - * Fill physical nodes with fake nodes of size until there is no memory - * left on any of them. - */ - while (nodes_weight(physnode_mask)) { - for_each_node_mask(i, physnode_mask) { - u64 dma32_end = MAX_DMA32_PFN << PAGE_SHIFT; - u64 end; - - end = find_end_of_node(physnodes[i].start, - physnodes[i].end, size); - /* - * If there won't be at least FAKE_NODE_MIN_SIZE of - * non-reserved memory in ZONE_DMA32 for the next node, - * this one must extend to the boundary. - */ - if (end < dma32_end && dma32_end - end - - memblock_x86_hole_size(end, dma32_end) < FAKE_NODE_MIN_SIZE) - end = dma32_end; + for (i = 0; i < ARRAY_SIZE(mi->blk); i++) + if (mi->blk[i].start != mi->blk[i].end && + mi->blk[i].nid != NUMA_NO_NODE) + node_set(mi->blk[i].nid, *nodemask); +} - /* - * If there won't be enough non-reserved memory for the - * next node, this one must extend to the end of the - * physical node. - */ - if (physnodes[i].end - end - - memblock_x86_hole_size(end, physnodes[i].end) < size) - end = physnodes[i].end; +/** + * numa_reset_distance - Reset NUMA distance table + * + * The current table is freed. The next numa_set_distance() call will + * create a new one. + */ +void __init numa_reset_distance(void) +{ + size_t size = numa_distance_cnt * numa_distance_cnt * sizeof(numa_distance[0]); - /* - * Setup the fake node that will be allocated as bootmem - * later. If setup_node_range() returns non-zero, there - * is no more memory available on this physical node. - */ - if (setup_node_range(ret++, &physnodes[i].start, - end - physnodes[i].start, - physnodes[i].end) < 0) - node_clear(i, physnode_mask); - } - } - return ret; + /* numa_distance could be 1LU marking allocation failure, test cnt */ + if (numa_distance_cnt) + memblock_x86_free_range(__pa(numa_distance), + __pa(numa_distance) + size); + numa_distance_cnt = 0; + numa_distance = NULL; /* enable table creation */ } -/* - * Sets up the system RAM area from start_pfn to last_pfn according to the - * numa=fake command-line option. - */ -static int __init numa_emulation(unsigned long start_pfn, - unsigned long last_pfn, int acpi, int amd) +static int __init numa_alloc_distance(void) { - u64 addr = start_pfn << PAGE_SHIFT; - u64 max_addr = last_pfn << PAGE_SHIFT; - int num_nodes; - int i; + nodemask_t nodes_parsed; + size_t size; + int i, j, cnt = 0; + u64 phys; - /* - * If the numa=fake command-line contains a 'M' or 'G', it represents - * the fixed node size. Otherwise, if it is just a single number N, - * split the system RAM into N fake nodes. - */ - if (strchr(cmdline, 'M') || strchr(cmdline, 'G')) { - u64 size; + /* size the new table and allocate it */ + nodes_parsed = numa_nodes_parsed; + numa_nodemask_from_meminfo(&nodes_parsed, &numa_meminfo); - size = memparse(cmdline, &cmdline); - num_nodes = split_nodes_size_interleave(addr, max_addr, size); - } else { - unsigned long n; + for_each_node_mask(i, nodes_parsed) + cnt = i; + cnt++; + size = cnt * cnt * sizeof(numa_distance[0]); - n = simple_strtoul(cmdline, NULL, 0); - num_nodes = split_nodes_interleave(addr, max_addr, n); + phys = memblock_find_in_range(0, (u64)max_pfn_mapped << PAGE_SHIFT, + size, PAGE_SIZE); + if (phys == MEMBLOCK_ERROR) { + pr_warning("NUMA: Warning: can't allocate distance table!\n"); + /* don't retry until explicitly reset */ + numa_distance = (void *)1LU; + return -ENOMEM; } + memblock_x86_reserve_range(phys, phys + size, "NUMA DIST"); - if (num_nodes < 0) - return num_nodes; - memnode_shift = compute_hash_shift(nodes, num_nodes, NULL); - if (memnode_shift < 0) { - memnode_shift = 0; - printk(KERN_ERR "No NUMA hash function found. NUMA emulation " - "disabled.\n"); - return -1; - } + numa_distance = __va(phys); + numa_distance_cnt = cnt; + + /* fill with the default distances */ + for (i = 0; i < cnt; i++) + for (j = 0; j < cnt; j++) + numa_distance[i * cnt + j] = i == j ? + LOCAL_DISTANCE : REMOTE_DISTANCE; + printk(KERN_DEBUG "NUMA: Initialized distance table, cnt=%d\n", cnt); - /* - * We need to vacate all active ranges that may have been registered for - * the e820 memory map. - */ - remove_all_active_ranges(); - for_each_node_mask(i, node_possible_map) { - memblock_x86_register_active_regions(i, nodes[i].start >> PAGE_SHIFT, - nodes[i].end >> PAGE_SHIFT); - setup_node_bootmem(i, nodes[i].start, nodes[i].end); - } - setup_physnodes(addr, max_addr, acpi, amd); - fake_physnodes(acpi, amd, num_nodes); - numa_init_array(); return 0; } -#endif /* CONFIG_NUMA_EMU */ -void __init initmem_init(unsigned long start_pfn, unsigned long last_pfn, - int acpi, int amd) +/** + * numa_set_distance - Set NUMA distance from one NUMA to another + * @from: the 'from' node to set distance + * @to: the 'to' node to set distance + * @distance: NUMA distance + * + * Set the distance from node @from to @to to @distance. If distance table + * doesn't exist, one which is large enough to accomodate all the currently + * known nodes will be created. + * + * If such table cannot be allocated, a warning is printed and further + * calls are ignored until the distance table is reset with + * numa_reset_distance(). + * + * If @from or @to is higher than the highest known node at the time of + * table creation or @distance doesn't make sense, the call is ignored. + * This is to allow simplification of specific NUMA config implementations. + */ +void __init numa_set_distance(int from, int to, int distance) { - int i; - - nodes_clear(node_possible_map); - nodes_clear(node_online_map); - -#ifdef CONFIG_NUMA_EMU - setup_physnodes(start_pfn << PAGE_SHIFT, last_pfn << PAGE_SHIFT, - acpi, amd); - if (cmdline && !numa_emulation(start_pfn, last_pfn, acpi, amd)) + if (!numa_distance && numa_alloc_distance() < 0) return; - setup_physnodes(start_pfn << PAGE_SHIFT, last_pfn << PAGE_SHIFT, - acpi, amd); - nodes_clear(node_possible_map); - nodes_clear(node_online_map); -#endif -#ifdef CONFIG_ACPI_NUMA - if (!numa_off && acpi && !acpi_scan_nodes(start_pfn << PAGE_SHIFT, - last_pfn << PAGE_SHIFT)) + if (from >= numa_distance_cnt || to >= numa_distance_cnt) { + printk_once(KERN_DEBUG "NUMA: Debug: distance out of bound, from=%d to=%d distance=%d\n", + from, to, distance); return; - nodes_clear(node_possible_map); - nodes_clear(node_online_map); -#endif + } -#ifdef CONFIG_AMD_NUMA - if (!numa_off && amd && !amd_scan_nodes()) + if ((u8)distance != distance || + (from == to && distance != LOCAL_DISTANCE)) { + pr_warn_once("NUMA: Warning: invalid distance parameter, from=%d to=%d distance=%d\n", + from, to, distance); return; - nodes_clear(node_possible_map); - nodes_clear(node_online_map); -#endif - printk(KERN_INFO "%s\n", - numa_off ? "NUMA turned off" : "No NUMA configuration found"); + } - printk(KERN_INFO "Faking a node at %016lx-%016lx\n", - start_pfn << PAGE_SHIFT, - last_pfn << PAGE_SHIFT); - /* setup dummy node covering all memory */ - memnode_shift = 63; - memnodemap = memnode.embedded_map; - memnodemap[0] = 0; - node_set_online(0); - node_set(0, node_possible_map); - for (i = 0; i < nr_cpu_ids; i++) - numa_set_node(i, 0); - memblock_x86_register_active_regions(0, start_pfn, last_pfn); - setup_node_bootmem(0, start_pfn << PAGE_SHIFT, last_pfn << PAGE_SHIFT); + numa_distance[from * numa_distance_cnt + to] = distance; } -unsigned long __init numa_free_all_bootmem(void) +int __node_distance(int from, int to) { - unsigned long pages = 0; - int i; + if (from >= numa_distance_cnt || to >= numa_distance_cnt) + return from == to ? LOCAL_DISTANCE : REMOTE_DISTANCE; + return numa_distance[from * numa_distance_cnt + to]; +} +EXPORT_SYMBOL(__node_distance); - for_each_online_node(i) - pages += free_all_bootmem_node(NODE_DATA(i)); +/* + * Sanity check to catch more bad NUMA configurations (they are amazingly + * common). Make sure the nodes cover all memory. + */ +static bool __init numa_meminfo_cover_memory(const struct numa_meminfo *mi) +{ + unsigned long numaram, e820ram; + int i; - pages += free_all_memory_core_early(MAX_NUMNODES); + numaram = 0; + for (i = 0; i < mi->nr_blks; i++) { + unsigned long s = mi->blk[i].start >> PAGE_SHIFT; + unsigned long e = mi->blk[i].end >> PAGE_SHIFT; + numaram += e - s; + numaram -= __absent_pages_in_range(mi->blk[i].nid, s, e); + if ((long)numaram < 0) + numaram = 0; + } - return pages; + e820ram = max_pfn - (memblock_x86_hole_size(0, + max_pfn << PAGE_SHIFT) >> PAGE_SHIFT); + /* We seem to lose 3 pages somewhere. Allow 1M of slack. */ + if ((long)(e820ram - numaram) >= (1 << (20 - PAGE_SHIFT))) { + printk(KERN_ERR "NUMA: nodes only cover %luMB of your %luMB e820 RAM. Not used.\n", + (numaram << PAGE_SHIFT) >> 20, + (e820ram << PAGE_SHIFT) >> 20); + return false; + } + return true; } -#ifdef CONFIG_NUMA - -static __init int find_near_online_node(int node) +static int __init numa_register_memblks(struct numa_meminfo *mi) { - int n, val; - int min_val = INT_MAX; - int best_node = -1; + int i, nid; - for_each_online_node(n) { - val = node_distance(node, n); + /* Account for nodes with cpus and no memory */ + node_possible_map = numa_nodes_parsed; + numa_nodemask_from_meminfo(&node_possible_map, mi); + if (WARN_ON(nodes_empty(node_possible_map))) + return -EINVAL; - if (val < min_val) { - min_val = val; - best_node = n; + memnode_shift = compute_hash_shift(mi); + if (memnode_shift < 0) { + printk(KERN_ERR "NUMA: No NUMA node hash function found. Contact maintainer\n"); + return -EINVAL; + } + + for (i = 0; i < mi->nr_blks; i++) + memblock_x86_register_active_regions(mi->blk[i].nid, + mi->blk[i].start >> PAGE_SHIFT, + mi->blk[i].end >> PAGE_SHIFT); + + /* for out of order entries */ + sort_node_map(); + if (!numa_meminfo_cover_memory(mi)) + return -EINVAL; + + /* Finally register nodes. */ + for_each_node_mask(nid, node_possible_map) { + u64 start = (u64)max_pfn << PAGE_SHIFT; + u64 end = 0; + + for (i = 0; i < mi->nr_blks; i++) { + if (nid != mi->blk[i].nid) + continue; + start = min(mi->blk[i].start, start); + end = max(mi->blk[i].end, end); } + + if (start < end) + setup_node_bootmem(nid, start, end); } - return best_node; + return 0; } -/* - * Setup early cpu_to_node. +/** + * dummy_numma_init - Fallback dummy NUMA init * - * Populate cpu_to_node[] only if x86_cpu_to_apicid[], - * and apicid_to_node[] tables have valid entries for a CPU. - * This means we skip cpu_to_node[] initialisation for NUMA - * emulation and faking node case (when running a kernel compiled - * for NUMA on a non NUMA box), which is OK as cpu_to_node[] - * is already initialized in a round robin manner at numa_init_array, - * prior to this call, and this initialization is good enough - * for the fake NUMA cases. + * Used if there's no underlying NUMA architecture, NUMA initialization + * fails, or NUMA is disabled on the command line. * - * Called before the per_cpu areas are setup. + * Must online at least one node and add memory blocks that cover all + * allowed memory. This function must not fail. */ -void __init init_cpu_to_node(void) +static int __init dummy_numa_init(void) { - int cpu; - u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); - - BUG_ON(cpu_to_apicid == NULL); + printk(KERN_INFO "%s\n", + numa_off ? "NUMA turned off" : "No NUMA configuration found"); + printk(KERN_INFO "Faking a node at %016lx-%016lx\n", + 0LU, max_pfn << PAGE_SHIFT); - for_each_possible_cpu(cpu) { - int node; - u16 apicid = cpu_to_apicid[cpu]; + node_set(0, numa_nodes_parsed); + numa_add_memblk(0, 0, (u64)max_pfn << PAGE_SHIFT); - if (apicid == BAD_APICID) - continue; - node = apicid_to_node[apicid]; - if (node == NUMA_NO_NODE) - continue; - if (!node_online(node)) - node = find_near_online_node(node); - numa_set_node(cpu, node); - } + return 0; } -#endif - -void __cpuinit numa_set_node(int cpu, int node) +static int __init numa_init(int (*init_func)(void)) { - int *cpu_to_node_map = early_per_cpu_ptr(x86_cpu_to_node_map); - - /* early setting, no percpu area yet */ - if (cpu_to_node_map) { - cpu_to_node_map[cpu] = node; - return; - } - -#ifdef CONFIG_DEBUG_PER_CPU_MAPS - if (cpu >= nr_cpu_ids || !cpu_possible(cpu)) { - printk(KERN_ERR "numa_set_node: invalid cpu# (%d)\n", cpu); - dump_stack(); - return; - } -#endif - per_cpu(x86_cpu_to_node_map, cpu) = node; + int i; + int ret; - if (node != NUMA_NO_NODE) - set_cpu_numa_node(cpu, node); -} + for (i = 0; i < MAX_LOCAL_APIC; i++) + set_apicid_to_node(i, NUMA_NO_NODE); -void __cpuinit numa_clear_node(int cpu) -{ - numa_set_node(cpu, NUMA_NO_NODE); -} - -#ifndef CONFIG_DEBUG_PER_CPU_MAPS + nodes_clear(numa_nodes_parsed); + nodes_clear(node_possible_map); + nodes_clear(node_online_map); + memset(&numa_meminfo, 0, sizeof(numa_meminfo)); + remove_all_active_ranges(); + numa_reset_distance(); -#ifndef CONFIG_NUMA_EMU -void __cpuinit numa_add_cpu(int cpu) -{ - cpumask_set_cpu(cpu, node_to_cpumask_map[early_cpu_to_node(cpu)]); -} + ret = init_func(); + if (ret < 0) + return ret; + ret = numa_cleanup_meminfo(&numa_meminfo); + if (ret < 0) + return ret; -void __cpuinit numa_remove_cpu(int cpu) -{ - cpumask_clear_cpu(cpu, node_to_cpumask_map[early_cpu_to_node(cpu)]); -} -#else -void __cpuinit numa_add_cpu(int cpu) -{ - unsigned long addr; - u16 apicid; - int physnid; - int nid = NUMA_NO_NODE; + numa_emulation(&numa_meminfo, numa_distance_cnt); - nid = early_cpu_to_node(cpu); - BUG_ON(nid == NUMA_NO_NODE || !node_online(nid)); + ret = numa_register_memblks(&numa_meminfo); + if (ret < 0) + return ret; - /* - * Use the starting address of the emulated node to find which physical - * node it is allocated on. - */ - addr = node_start_pfn(nid) << PAGE_SHIFT; - for (physnid = 0; physnid < MAX_NUMNODES; physnid++) - if (addr >= physnodes[physnid].start && - addr < physnodes[physnid].end) - break; + for (i = 0; i < nr_cpu_ids; i++) { + int nid = early_cpu_to_node(i); - /* - * Map the cpu to each emulated node that is allocated on the physical - * node of the cpu's apic id. - */ - for_each_online_node(nid) { - addr = node_start_pfn(nid) << PAGE_SHIFT; - if (addr >= physnodes[physnid].start && - addr < physnodes[physnid].end) - cpumask_set_cpu(cpu, node_to_cpumask_map[nid]); + if (nid == NUMA_NO_NODE) + continue; + if (!node_online(nid)) + numa_clear_node(i); } + numa_init_array(); + return 0; } -void __cpuinit numa_remove_cpu(int cpu) +void __init initmem_init(void) { - int i; + int ret; - for_each_online_node(i) - cpumask_clear_cpu(cpu, node_to_cpumask_map[i]); -} -#endif /* !CONFIG_NUMA_EMU */ - -#else /* CONFIG_DEBUG_PER_CPU_MAPS */ -static struct cpumask __cpuinit *debug_cpumask_set_cpu(int cpu, int enable) -{ - int node = early_cpu_to_node(cpu); - struct cpumask *mask; - char buf[64]; - - mask = node_to_cpumask_map[node]; - if (!mask) { - pr_err("node_to_cpumask_map[%i] NULL\n", node); - dump_stack(); - return NULL; + if (!numa_off) { +#ifdef CONFIG_ACPI_NUMA + ret = numa_init(x86_acpi_numa_init); + if (!ret) + return; +#endif +#ifdef CONFIG_AMD_NUMA + ret = numa_init(amd_numa_init); + if (!ret) + return; +#endif } - cpulist_scnprintf(buf, sizeof(buf), mask); - printk(KERN_DEBUG "%s cpu %d node %d: mask now %s\n", - enable ? "numa_add_cpu" : "numa_remove_cpu", - cpu, node, buf); - return mask; + numa_init(dummy_numa_init); } -/* - * --------- debug versions of the numa functions --------- - */ -#ifndef CONFIG_NUMA_EMU -static void __cpuinit numa_set_cpumask(int cpu, int enable) -{ - struct cpumask *mask; - - mask = debug_cpumask_set_cpu(cpu, enable); - if (!mask) - return; - - if (enable) - cpumask_set_cpu(cpu, mask); - else - cpumask_clear_cpu(cpu, mask); -} -#else -static void __cpuinit numa_set_cpumask(int cpu, int enable) +unsigned long __init numa_free_all_bootmem(void) { - int node = early_cpu_to_node(cpu); - struct cpumask *mask; + unsigned long pages = 0; int i; - for_each_online_node(i) { - unsigned long addr; - - addr = node_start_pfn(i) << PAGE_SHIFT; - if (addr < physnodes[node].start || - addr >= physnodes[node].end) - continue; - mask = debug_cpumask_set_cpu(cpu, enable); - if (!mask) - return; - - if (enable) - cpumask_set_cpu(cpu, mask); - else - cpumask_clear_cpu(cpu, mask); - } -} -#endif /* CONFIG_NUMA_EMU */ + for_each_online_node(i) + pages += free_all_bootmem_node(NODE_DATA(i)); -void __cpuinit numa_add_cpu(int cpu) -{ - numa_set_cpumask(cpu, 1); -} + pages += free_all_memory_core_early(MAX_NUMNODES); -void __cpuinit numa_remove_cpu(int cpu) -{ - numa_set_cpumask(cpu, 0); + return pages; } -int __cpu_to_node(int cpu) +int __cpuinit numa_cpu_node(int cpu) { - if (early_per_cpu_ptr(x86_cpu_to_node_map)) { - printk(KERN_WARNING - "cpu_to_node(%d): usage too early!\n", cpu); - dump_stack(); - return early_per_cpu_ptr(x86_cpu_to_node_map)[cpu]; - } - return per_cpu(x86_cpu_to_node_map, cpu); -} -EXPORT_SYMBOL(__cpu_to_node); + int apicid = early_per_cpu(x86_cpu_to_apicid, cpu); -/* - * Same function as cpu_to_node() but used if called before the - * per_cpu areas are setup. - */ -int early_cpu_to_node(int cpu) -{ - if (early_per_cpu_ptr(x86_cpu_to_node_map)) - return early_per_cpu_ptr(x86_cpu_to_node_map)[cpu]; - - if (!cpu_possible(cpu)) { - printk(KERN_WARNING - "early_cpu_to_node(%d): no per_cpu area!\n", cpu); - dump_stack(); - return NUMA_NO_NODE; - } - return per_cpu(x86_cpu_to_node_map, cpu); + if (apicid != BAD_APICID) + return __apicid_to_node[apicid]; + return NUMA_NO_NODE; } - -/* - * --------- end of debug versions of the numa functions --------- - */ - -#endif /* CONFIG_DEBUG_PER_CPU_MAPS */ diff --git a/arch/x86/mm/numa_emulation.c b/arch/x86/mm/numa_emulation.c new file mode 100644 index 000000000000..ad091e4cff17 --- /dev/null +++ b/arch/x86/mm/numa_emulation.c @@ -0,0 +1,494 @@ +/* + * NUMA emulation + */ +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/topology.h> +#include <linux/memblock.h> +#include <asm/dma.h> + +#include "numa_internal.h" + +static int emu_nid_to_phys[MAX_NUMNODES] __cpuinitdata; +static char *emu_cmdline __initdata; + +void __init numa_emu_cmdline(char *str) +{ + emu_cmdline = str; +} + +static int __init emu_find_memblk_by_nid(int nid, const struct numa_meminfo *mi) +{ + int i; + + for (i = 0; i < mi->nr_blks; i++) + if (mi->blk[i].nid == nid) + return i; + return -ENOENT; +} + +/* + * Sets up nid to range from @start to @end. The return value is -errno if + * something went wrong, 0 otherwise. + */ +static int __init emu_setup_memblk(struct numa_meminfo *ei, + struct numa_meminfo *pi, + int nid, int phys_blk, u64 size) +{ + struct numa_memblk *eb = &ei->blk[ei->nr_blks]; + struct numa_memblk *pb = &pi->blk[phys_blk]; + + if (ei->nr_blks >= NR_NODE_MEMBLKS) { + pr_err("NUMA: Too many emulated memblks, failing emulation\n"); + return -EINVAL; + } + + ei->nr_blks++; + eb->start = pb->start; + eb->end = pb->start + size; + eb->nid = nid; + + if (emu_nid_to_phys[nid] == NUMA_NO_NODE) + emu_nid_to_phys[nid] = pb->nid; + + pb->start += size; + if (pb->start >= pb->end) { + WARN_ON_ONCE(pb->start > pb->end); + numa_remove_memblk_from(phys_blk, pi); + } + + printk(KERN_INFO "Faking node %d at %016Lx-%016Lx (%LuMB)\n", nid, + eb->start, eb->end, (eb->end - eb->start) >> 20); + return 0; +} + +/* + * Sets up nr_nodes fake nodes interleaved over physical nodes ranging from addr + * to max_addr. The return value is the number of nodes allocated. + */ +static int __init split_nodes_interleave(struct numa_meminfo *ei, + struct numa_meminfo *pi, + u64 addr, u64 max_addr, int nr_nodes) +{ + nodemask_t physnode_mask = NODE_MASK_NONE; + u64 size; + int big; + int nid = 0; + int i, ret; + + if (nr_nodes <= 0) + return -1; + if (nr_nodes > MAX_NUMNODES) { + pr_info("numa=fake=%d too large, reducing to %d\n", + nr_nodes, MAX_NUMNODES); + nr_nodes = MAX_NUMNODES; + } + + size = (max_addr - addr - memblock_x86_hole_size(addr, max_addr)) / nr_nodes; + /* + * Calculate the number of big nodes that can be allocated as a result + * of consolidating the remainder. + */ + big = ((size & ~FAKE_NODE_MIN_HASH_MASK) * nr_nodes) / + FAKE_NODE_MIN_SIZE; + + size &= FAKE_NODE_MIN_HASH_MASK; + if (!size) { + pr_err("Not enough memory for each node. " + "NUMA emulation disabled.\n"); + return -1; + } + + for (i = 0; i < pi->nr_blks; i++) + node_set(pi->blk[i].nid, physnode_mask); + + /* + * Continue to fill physical nodes with fake nodes until there is no + * memory left on any of them. + */ + while (nodes_weight(physnode_mask)) { + for_each_node_mask(i, physnode_mask) { + u64 dma32_end = PFN_PHYS(MAX_DMA32_PFN); + u64 start, limit, end; + int phys_blk; + + phys_blk = emu_find_memblk_by_nid(i, pi); + if (phys_blk < 0) { + node_clear(i, physnode_mask); + continue; + } + start = pi->blk[phys_blk].start; + limit = pi->blk[phys_blk].end; + end = start + size; + + if (nid < big) + end += FAKE_NODE_MIN_SIZE; + + /* + * Continue to add memory to this fake node if its + * non-reserved memory is less than the per-node size. + */ + while (end - start - + memblock_x86_hole_size(start, end) < size) { + end += FAKE_NODE_MIN_SIZE; + if (end > limit) { + end = limit; + break; + } + } + + /* + * If there won't be at least FAKE_NODE_MIN_SIZE of + * non-reserved memory in ZONE_DMA32 for the next node, + * this one must extend to the boundary. + */ + if (end < dma32_end && dma32_end - end - + memblock_x86_hole_size(end, dma32_end) < FAKE_NODE_MIN_SIZE) + end = dma32_end; + + /* + * If there won't be enough non-reserved memory for the + * next node, this one must extend to the end of the + * physical node. + */ + if (limit - end - + memblock_x86_hole_size(end, limit) < size) + end = limit; + + ret = emu_setup_memblk(ei, pi, nid++ % nr_nodes, + phys_blk, + min(end, limit) - start); + if (ret < 0) + return ret; + } + } + return 0; +} + +/* + * Returns the end address of a node so that there is at least `size' amount of + * non-reserved memory or `max_addr' is reached. + */ +static u64 __init find_end_of_node(u64 start, u64 max_addr, u64 size) +{ + u64 end = start + size; + + while (end - start - memblock_x86_hole_size(start, end) < size) { + end += FAKE_NODE_MIN_SIZE; + if (end > max_addr) { + end = max_addr; + break; + } + } + return end; +} + +/* + * Sets up fake nodes of `size' interleaved over physical nodes ranging from + * `addr' to `max_addr'. The return value is the number of nodes allocated. + */ +static int __init split_nodes_size_interleave(struct numa_meminfo *ei, + struct numa_meminfo *pi, + u64 addr, u64 max_addr, u64 size) +{ + nodemask_t physnode_mask = NODE_MASK_NONE; + u64 min_size; + int nid = 0; + int i, ret; + + if (!size) + return -1; + /* + * The limit on emulated nodes is MAX_NUMNODES, so the size per node is + * increased accordingly if the requested size is too small. This + * creates a uniform distribution of node sizes across the entire + * machine (but not necessarily over physical nodes). + */ + min_size = (max_addr - addr - memblock_x86_hole_size(addr, max_addr)) / + MAX_NUMNODES; + min_size = max(min_size, FAKE_NODE_MIN_SIZE); + if ((min_size & FAKE_NODE_MIN_HASH_MASK) < min_size) + min_size = (min_size + FAKE_NODE_MIN_SIZE) & + FAKE_NODE_MIN_HASH_MASK; + if (size < min_size) { + pr_err("Fake node size %LuMB too small, increasing to %LuMB\n", + size >> 20, min_size >> 20); + size = min_size; + } + size &= FAKE_NODE_MIN_HASH_MASK; + + for (i = 0; i < pi->nr_blks; i++) + node_set(pi->blk[i].nid, physnode_mask); + + /* + * Fill physical nodes with fake nodes of size until there is no memory + * left on any of them. + */ + while (nodes_weight(physnode_mask)) { + for_each_node_mask(i, physnode_mask) { + u64 dma32_end = MAX_DMA32_PFN << PAGE_SHIFT; + u64 start, limit, end; + int phys_blk; + + phys_blk = emu_find_memblk_by_nid(i, pi); + if (phys_blk < 0) { + node_clear(i, physnode_mask); + continue; + } + start = pi->blk[phys_blk].start; + limit = pi->blk[phys_blk].end; + + end = find_end_of_node(start, limit, size); + /* + * If there won't be at least FAKE_NODE_MIN_SIZE of + * non-reserved memory in ZONE_DMA32 for the next node, + * this one must extend to the boundary. + */ + if (end < dma32_end && dma32_end - end - + memblock_x86_hole_size(end, dma32_end) < FAKE_NODE_MIN_SIZE) + end = dma32_end; + + /* + * If there won't be enough non-reserved memory for the + * next node, this one must extend to the end of the + * physical node. + */ + if (limit - end - + memblock_x86_hole_size(end, limit) < size) + end = limit; + + ret = emu_setup_memblk(ei, pi, nid++ % MAX_NUMNODES, + phys_blk, + min(end, limit) - start); + if (ret < 0) + return ret; + } + } + return 0; +} + +/** + * numa_emulation - Emulate NUMA nodes + * @numa_meminfo: NUMA configuration to massage + * @numa_dist_cnt: The size of the physical NUMA distance table + * + * Emulate NUMA nodes according to the numa=fake kernel parameter. + * @numa_meminfo contains the physical memory configuration and is modified + * to reflect the emulated configuration on success. @numa_dist_cnt is + * used to determine the size of the physical distance table. + * + * On success, the following modifications are made. + * + * - @numa_meminfo is updated to reflect the emulated nodes. + * + * - __apicid_to_node[] is updated such that APIC IDs are mapped to the + * emulated nodes. + * + * - NUMA distance table is rebuilt to represent distances between emulated + * nodes. The distances are determined considering how emulated nodes + * are mapped to physical nodes and match the actual distances. + * + * - emu_nid_to_phys[] reflects how emulated nodes are mapped to physical + * nodes. This is used by numa_add_cpu() and numa_remove_cpu(). + * + * If emulation is not enabled or fails, emu_nid_to_phys[] is filled with + * identity mapping and no other modification is made. + */ +void __init numa_emulation(struct numa_meminfo *numa_meminfo, int numa_dist_cnt) +{ + static struct numa_meminfo ei __initdata; + static struct numa_meminfo pi __initdata; + const u64 max_addr = max_pfn << PAGE_SHIFT; + u8 *phys_dist = NULL; + size_t phys_size = numa_dist_cnt * numa_dist_cnt * sizeof(phys_dist[0]); + int max_emu_nid, dfl_phys_nid; + int i, j, ret; + + if (!emu_cmdline) + goto no_emu; + + memset(&ei, 0, sizeof(ei)); + pi = *numa_meminfo; + + for (i = 0; i < MAX_NUMNODES; i++) + emu_nid_to_phys[i] = NUMA_NO_NODE; + + /* + * If the numa=fake command-line contains a 'M' or 'G', it represents + * the fixed node size. Otherwise, if it is just a single number N, + * split the system RAM into N fake nodes. + */ + if (strchr(emu_cmdline, 'M') || strchr(emu_cmdline, 'G')) { + u64 size; + + size = memparse(emu_cmdline, &emu_cmdline); + ret = split_nodes_size_interleave(&ei, &pi, 0, max_addr, size); + } else { + unsigned long n; + + n = simple_strtoul(emu_cmdline, NULL, 0); + ret = split_nodes_interleave(&ei, &pi, 0, max_addr, n); + } + + if (ret < 0) + goto no_emu; + + if (numa_cleanup_meminfo(&ei) < 0) { + pr_warning("NUMA: Warning: constructed meminfo invalid, disabling emulation\n"); + goto no_emu; + } + + /* copy the physical distance table */ + if (numa_dist_cnt) { + u64 phys; + + phys = memblock_find_in_range(0, + (u64)max_pfn_mapped << PAGE_SHIFT, + phys_size, PAGE_SIZE); + if (phys == MEMBLOCK_ERROR) { + pr_warning("NUMA: Warning: can't allocate copy of distance table, disabling emulation\n"); + goto no_emu; + } + memblock_x86_reserve_range(phys, phys + phys_size, "TMP NUMA DIST"); + phys_dist = __va(phys); + + for (i = 0; i < numa_dist_cnt; i++) + for (j = 0; j < numa_dist_cnt; j++) + phys_dist[i * numa_dist_cnt + j] = + node_distance(i, j); + } + + /* + * Determine the max emulated nid and the default phys nid to use + * for unmapped nodes. + */ + max_emu_nid = 0; + dfl_phys_nid = NUMA_NO_NODE; + for (i = 0; i < ARRAY_SIZE(emu_nid_to_phys); i++) { + if (emu_nid_to_phys[i] != NUMA_NO_NODE) { + max_emu_nid = i; + if (dfl_phys_nid == NUMA_NO_NODE) + dfl_phys_nid = emu_nid_to_phys[i]; + } + } + if (dfl_phys_nid == NUMA_NO_NODE) { + pr_warning("NUMA: Warning: can't determine default physical node, disabling emulation\n"); + goto no_emu; + } + + /* commit */ + *numa_meminfo = ei; + + /* + * Transform __apicid_to_node table to use emulated nids by + * reverse-mapping phys_nid. The maps should always exist but fall + * back to zero just in case. + */ + for (i = 0; i < ARRAY_SIZE(__apicid_to_node); i++) { + if (__apicid_to_node[i] == NUMA_NO_NODE) + continue; + for (j = 0; j < ARRAY_SIZE(emu_nid_to_phys); j++) + if (__apicid_to_node[i] == emu_nid_to_phys[j]) + break; + __apicid_to_node[i] = j < ARRAY_SIZE(emu_nid_to_phys) ? j : 0; + } + + /* make sure all emulated nodes are mapped to a physical node */ + for (i = 0; i < ARRAY_SIZE(emu_nid_to_phys); i++) + if (emu_nid_to_phys[i] == NUMA_NO_NODE) + emu_nid_to_phys[i] = dfl_phys_nid; + + /* transform distance table */ + numa_reset_distance(); + for (i = 0; i < max_emu_nid + 1; i++) { + for (j = 0; j < max_emu_nid + 1; j++) { + int physi = emu_nid_to_phys[i]; + int physj = emu_nid_to_phys[j]; + int dist; + + if (physi >= numa_dist_cnt || physj >= numa_dist_cnt) + dist = physi == physj ? + LOCAL_DISTANCE : REMOTE_DISTANCE; + else + dist = phys_dist[physi * numa_dist_cnt + physj]; + + numa_set_distance(i, j, dist); + } + } + + /* free the copied physical distance table */ + if (phys_dist) + memblock_x86_free_range(__pa(phys_dist), __pa(phys_dist) + phys_size); + return; + +no_emu: + /* No emulation. Build identity emu_nid_to_phys[] for numa_add_cpu() */ + for (i = 0; i < ARRAY_SIZE(emu_nid_to_phys); i++) + emu_nid_to_phys[i] = i; +} + +#ifndef CONFIG_DEBUG_PER_CPU_MAPS +void __cpuinit numa_add_cpu(int cpu) +{ + int physnid, nid; + + nid = early_cpu_to_node(cpu); + BUG_ON(nid == NUMA_NO_NODE || !node_online(nid)); + + physnid = emu_nid_to_phys[nid]; + + /* + * Map the cpu to each emulated node that is allocated on the physical + * node of the cpu's apic id. + */ + for_each_online_node(nid) + if (emu_nid_to_phys[nid] == physnid) + cpumask_set_cpu(cpu, node_to_cpumask_map[nid]); +} + +void __cpuinit numa_remove_cpu(int cpu) +{ + int i; + + for_each_online_node(i) + cpumask_clear_cpu(cpu, node_to_cpumask_map[i]); +} +#else /* !CONFIG_DEBUG_PER_CPU_MAPS */ +static void __cpuinit numa_set_cpumask(int cpu, int enable) +{ + struct cpumask *mask; + int nid, physnid, i; + + nid = early_cpu_to_node(cpu); + if (nid == NUMA_NO_NODE) { + /* early_cpu_to_node() already emits a warning and trace */ + return; + } + + physnid = emu_nid_to_phys[nid]; + + for_each_online_node(i) { + if (emu_nid_to_phys[nid] != physnid) + continue; + + mask = debug_cpumask_set_cpu(cpu, enable); + if (!mask) + return; + + if (enable) + cpumask_set_cpu(cpu, mask); + else + cpumask_clear_cpu(cpu, mask); + } +} + +void __cpuinit numa_add_cpu(int cpu) +{ + numa_set_cpumask(cpu, 1); +} + +void __cpuinit numa_remove_cpu(int cpu) +{ + numa_set_cpumask(cpu, 0); +} +#endif /* !CONFIG_DEBUG_PER_CPU_MAPS */ diff --git a/arch/x86/mm/numa_internal.h b/arch/x86/mm/numa_internal.h new file mode 100644 index 000000000000..ef2d97377d7c --- /dev/null +++ b/arch/x86/mm/numa_internal.h @@ -0,0 +1,31 @@ +#ifndef __X86_MM_NUMA_INTERNAL_H +#define __X86_MM_NUMA_INTERNAL_H + +#include <linux/types.h> +#include <asm/numa.h> + +struct numa_memblk { + u64 start; + u64 end; + int nid; +}; + +struct numa_meminfo { + int nr_blks; + struct numa_memblk blk[NR_NODE_MEMBLKS]; +}; + +void __init numa_remove_memblk_from(int idx, struct numa_meminfo *mi); +int __init numa_cleanup_meminfo(struct numa_meminfo *mi); +void __init numa_reset_distance(void); + +#ifdef CONFIG_NUMA_EMU +void __init numa_emulation(struct numa_meminfo *numa_meminfo, + int numa_dist_cnt); +#else +static inline void numa_emulation(struct numa_meminfo *numa_meminfo, + int numa_dist_cnt) +{ } +#endif + +#endif /* __X86_MM_NUMA_INTERNAL_H */ diff --git a/arch/x86/mm/srat_32.c b/arch/x86/mm/srat_32.c index ae96e7b8051d..48651c6f657d 100644 --- a/arch/x86/mm/srat_32.c +++ b/arch/x86/mm/srat_32.c @@ -57,7 +57,7 @@ struct node_memory_chunk_s { static struct node_memory_chunk_s __initdata node_memory_chunk[MAXCHUNKS]; static int __initdata num_memory_chunks; /* total number of memory chunks */ -static u8 __initdata apicid_to_pxm[MAX_APICID]; +static u8 __initdata apicid_to_pxm[MAX_LOCAL_APIC]; int acpi_numa __initdata; @@ -254,8 +254,8 @@ int __init get_memcfg_from_srat(void) printk(KERN_DEBUG "Number of memory chunks in system = %d\n", num_memory_chunks); - for (i = 0; i < MAX_APICID; i++) - apicid_2_node[i] = pxm_to_node(apicid_to_pxm[i]); + for (i = 0; i < MAX_LOCAL_APIC; i++) + set_apicid_to_node(i, pxm_to_node(apicid_to_pxm[i])); for (j = 0; j < num_memory_chunks; j++){ struct node_memory_chunk_s * chunk = &node_memory_chunk[j]; diff --git a/arch/x86/mm/srat_64.c b/arch/x86/mm/srat_64.c index 603d285d1daa..8e9d3394f6d4 100644 --- a/arch/x86/mm/srat_64.c +++ b/arch/x86/mm/srat_64.c @@ -26,88 +26,34 @@ int acpi_numa __initdata; -static struct acpi_table_slit *acpi_slit; - -static nodemask_t nodes_parsed __initdata; -static nodemask_t cpu_nodes_parsed __initdata; -static struct bootnode nodes[MAX_NUMNODES] __initdata; static struct bootnode nodes_add[MAX_NUMNODES]; -static int num_node_memblks __initdata; -static struct bootnode node_memblk_range[NR_NODE_MEMBLKS] __initdata; -static int memblk_nodeid[NR_NODE_MEMBLKS] __initdata; - static __init int setup_node(int pxm) { return acpi_map_pxm_to_node(pxm); } -static __init int conflicting_memblks(unsigned long start, unsigned long end) -{ - int i; - for (i = 0; i < num_node_memblks; i++) { - struct bootnode *nd = &node_memblk_range[i]; - if (nd->start == nd->end) - continue; - if (nd->end > start && nd->start < end) - return memblk_nodeid[i]; - if (nd->end == end && nd->start == start) - return memblk_nodeid[i]; - } - return -1; -} - -static __init void cutoff_node(int i, unsigned long start, unsigned long end) -{ - struct bootnode *nd = &nodes[i]; - - if (nd->start < start) { - nd->start = start; - if (nd->end < nd->start) - nd->start = nd->end; - } - if (nd->end > end) { - nd->end = end; - if (nd->start > nd->end) - nd->start = nd->end; - } -} - static __init void bad_srat(void) { - int i; printk(KERN_ERR "SRAT: SRAT not used.\n"); acpi_numa = -1; - for (i = 0; i < MAX_LOCAL_APIC; i++) - apicid_to_node[i] = NUMA_NO_NODE; - for (i = 0; i < MAX_NUMNODES; i++) { - nodes[i].start = nodes[i].end = 0; - nodes_add[i].start = nodes_add[i].end = 0; - } - remove_all_active_ranges(); + memset(nodes_add, 0, sizeof(nodes_add)); } static __init inline int srat_disabled(void) { - return numa_off || acpi_numa < 0; + return acpi_numa < 0; } /* Callback for SLIT parsing */ void __init acpi_numa_slit_init(struct acpi_table_slit *slit) { - unsigned length; - unsigned long phys; - - length = slit->header.length; - phys = memblock_find_in_range(0, max_pfn_mapped<<PAGE_SHIFT, length, - PAGE_SIZE); - - if (phys == MEMBLOCK_ERROR) - panic(" Can not save slit!\n"); + int i, j; - acpi_slit = __va(phys); - memcpy(acpi_slit, slit, length); - memblock_x86_reserve_range(phys, phys + length, "ACPI SLIT"); + for (i = 0; i < slit->locality_count; i++) + for (j = 0; j < slit->locality_count; j++) + numa_set_distance(pxm_to_node(i), pxm_to_node(j), + slit->entry[slit->locality_count * i + j]); } /* Callback for Proximity Domain -> x2APIC mapping */ @@ -138,8 +84,8 @@ acpi_numa_x2apic_affinity_init(struct acpi_srat_x2apic_cpu_affinity *pa) printk(KERN_INFO "SRAT: PXM %u -> APIC 0x%04x -> Node %u skipped apicid that is too big\n", pxm, apic_id, node); return; } - apicid_to_node[apic_id] = node; - node_set(node, cpu_nodes_parsed); + set_apicid_to_node(apic_id, node); + node_set(node, numa_nodes_parsed); acpi_numa = 1; printk(KERN_INFO "SRAT: PXM %u -> APIC 0x%04x -> Node %u\n", pxm, apic_id, node); @@ -178,8 +124,8 @@ acpi_numa_processor_affinity_init(struct acpi_srat_cpu_affinity *pa) return; } - apicid_to_node[apic_id] = node; - node_set(node, cpu_nodes_parsed); + set_apicid_to_node(apic_id, node); + node_set(node, numa_nodes_parsed); acpi_numa = 1; printk(KERN_INFO "SRAT: PXM %u -> APIC 0x%02x -> Node %u\n", pxm, apic_id, node); @@ -241,7 +187,7 @@ update_nodes_add(int node, unsigned long start, unsigned long end) } if (changed) { - node_set(node, cpu_nodes_parsed); + node_set(node, numa_nodes_parsed); printk(KERN_INFO "SRAT: hot plug zone found %Lx - %Lx\n", nd->start, nd->end); } @@ -251,10 +197,8 @@ update_nodes_add(int node, unsigned long start, unsigned long end) void __init acpi_numa_memory_affinity_init(struct acpi_srat_mem_affinity *ma) { - struct bootnode *nd, oldnode; unsigned long start, end; int node, pxm; - int i; if (srat_disabled()) return; @@ -276,300 +220,31 @@ acpi_numa_memory_affinity_init(struct acpi_srat_mem_affinity *ma) bad_srat(); return; } - i = conflicting_memblks(start, end); - if (i == node) { - printk(KERN_WARNING - "SRAT: Warning: PXM %d (%lx-%lx) overlaps with itself (%Lx-%Lx)\n", - pxm, start, end, nodes[i].start, nodes[i].end); - } else if (i >= 0) { - printk(KERN_ERR - "SRAT: PXM %d (%lx-%lx) overlaps with PXM %d (%Lx-%Lx)\n", - pxm, start, end, node_to_pxm(i), - nodes[i].start, nodes[i].end); + + if (numa_add_memblk(node, start, end) < 0) { bad_srat(); return; } - nd = &nodes[node]; - oldnode = *nd; - if (!node_test_and_set(node, nodes_parsed)) { - nd->start = start; - nd->end = end; - } else { - if (start < nd->start) - nd->start = start; - if (nd->end < end) - nd->end = end; - } printk(KERN_INFO "SRAT: Node %u PXM %u %lx-%lx\n", node, pxm, start, end); - if (ma->flags & ACPI_SRAT_MEM_HOT_PLUGGABLE) { + if (ma->flags & ACPI_SRAT_MEM_HOT_PLUGGABLE) update_nodes_add(node, start, end); - /* restore nodes[node] */ - *nd = oldnode; - if ((nd->start | nd->end) == 0) - node_clear(node, nodes_parsed); - } - - node_memblk_range[num_node_memblks].start = start; - node_memblk_range[num_node_memblks].end = end; - memblk_nodeid[num_node_memblks] = node; - num_node_memblks++; -} - -/* Sanity check to catch more bad SRATs (they are amazingly common). - Make sure the PXMs cover all memory. */ -static int __init nodes_cover_memory(const struct bootnode *nodes) -{ - int i; - unsigned long pxmram, e820ram; - - pxmram = 0; - for_each_node_mask(i, nodes_parsed) { - unsigned long s = nodes[i].start >> PAGE_SHIFT; - unsigned long e = nodes[i].end >> PAGE_SHIFT; - pxmram += e - s; - pxmram -= __absent_pages_in_range(i, s, e); - if ((long)pxmram < 0) - pxmram = 0; - } - - e820ram = max_pfn - (memblock_x86_hole_size(0, max_pfn<<PAGE_SHIFT)>>PAGE_SHIFT); - /* We seem to lose 3 pages somewhere. Allow 1M of slack. */ - if ((long)(e820ram - pxmram) >= (1<<(20 - PAGE_SHIFT))) { - printk(KERN_ERR - "SRAT: PXMs only cover %luMB of your %luMB e820 RAM. Not used.\n", - (pxmram << PAGE_SHIFT) >> 20, - (e820ram << PAGE_SHIFT) >> 20); - return 0; - } - return 1; } void __init acpi_numa_arch_fixup(void) {} -#ifdef CONFIG_NUMA_EMU -void __init acpi_get_nodes(struct bootnode *physnodes, unsigned long start, - unsigned long end) -{ - int i; - - for_each_node_mask(i, nodes_parsed) { - cutoff_node(i, start, end); - physnodes[i].start = nodes[i].start; - physnodes[i].end = nodes[i].end; - } -} -#endif /* CONFIG_NUMA_EMU */ - -/* Use the information discovered above to actually set up the nodes. */ -int __init acpi_scan_nodes(unsigned long start, unsigned long end) +int __init x86_acpi_numa_init(void) { - int i; - - if (acpi_numa <= 0) - return -1; - - /* First clean up the node list */ - for (i = 0; i < MAX_NUMNODES; i++) - cutoff_node(i, start, end); - - /* - * Join together blocks on the same node, holes between - * which don't overlap with memory on other nodes. - */ - for (i = 0; i < num_node_memblks; ++i) { - int j, k; - - for (j = i + 1; j < num_node_memblks; ++j) { - unsigned long start, end; - - if (memblk_nodeid[i] != memblk_nodeid[j]) - continue; - start = min(node_memblk_range[i].end, - node_memblk_range[j].end); - end = max(node_memblk_range[i].start, - node_memblk_range[j].start); - for (k = 0; k < num_node_memblks; ++k) { - if (memblk_nodeid[i] == memblk_nodeid[k]) - continue; - if (start < node_memblk_range[k].end && - end > node_memblk_range[k].start) - break; - } - if (k < num_node_memblks) - continue; - start = min(node_memblk_range[i].start, - node_memblk_range[j].start); - end = max(node_memblk_range[i].end, - node_memblk_range[j].end); - printk(KERN_INFO "SRAT: Node %d " - "[%Lx,%Lx) + [%Lx,%Lx) -> [%lx,%lx)\n", - memblk_nodeid[i], - node_memblk_range[i].start, - node_memblk_range[i].end, - node_memblk_range[j].start, - node_memblk_range[j].end, - start, end); - node_memblk_range[i].start = start; - node_memblk_range[i].end = end; - k = --num_node_memblks - j; - memmove(memblk_nodeid + j, memblk_nodeid + j+1, - k * sizeof(*memblk_nodeid)); - memmove(node_memblk_range + j, node_memblk_range + j+1, - k * sizeof(*node_memblk_range)); - --j; - } - } - - memnode_shift = compute_hash_shift(node_memblk_range, num_node_memblks, - memblk_nodeid); - if (memnode_shift < 0) { - printk(KERN_ERR - "SRAT: No NUMA node hash function found. Contact maintainer\n"); - bad_srat(); - return -1; - } - - for (i = 0; i < num_node_memblks; i++) - memblock_x86_register_active_regions(memblk_nodeid[i], - node_memblk_range[i].start >> PAGE_SHIFT, - node_memblk_range[i].end >> PAGE_SHIFT); - - /* for out of order entries in SRAT */ - sort_node_map(); - if (!nodes_cover_memory(nodes)) { - bad_srat(); - return -1; - } + int ret; - /* Account for nodes with cpus and no memory */ - nodes_or(node_possible_map, nodes_parsed, cpu_nodes_parsed); - - /* Finally register nodes */ - for_each_node_mask(i, node_possible_map) - setup_node_bootmem(i, nodes[i].start, nodes[i].end); - /* Try again in case setup_node_bootmem missed one due - to missing bootmem */ - for_each_node_mask(i, node_possible_map) - if (!node_online(i)) - setup_node_bootmem(i, nodes[i].start, nodes[i].end); - - for (i = 0; i < nr_cpu_ids; i++) { - int node = early_cpu_to_node(i); - - if (node == NUMA_NO_NODE) - continue; - if (!node_online(node)) - numa_clear_node(i); - } - numa_init_array(); - return 0; -} - -#ifdef CONFIG_NUMA_EMU -static int fake_node_to_pxm_map[MAX_NUMNODES] __initdata = { - [0 ... MAX_NUMNODES-1] = PXM_INVAL -}; -static s16 fake_apicid_to_node[MAX_LOCAL_APIC] __initdata = { - [0 ... MAX_LOCAL_APIC-1] = NUMA_NO_NODE -}; -static int __init find_node_by_addr(unsigned long addr) -{ - int ret = NUMA_NO_NODE; - int i; - - for_each_node_mask(i, nodes_parsed) { - /* - * Find the real node that this emulated node appears on. For - * the sake of simplicity, we only use a real node's starting - * address to determine which emulated node it appears on. - */ - if (addr >= nodes[i].start && addr < nodes[i].end) { - ret = i; - break; - } - } - return ret; + ret = acpi_numa_init(); + if (ret < 0) + return ret; + return srat_disabled() ? -EINVAL : 0; } -/* - * In NUMA emulation, we need to setup proximity domain (_PXM) to node ID - * mappings that respect the real ACPI topology but reflect our emulated - * environment. For each emulated node, we find which real node it appears on - * and create PXM to NID mappings for those fake nodes which mirror that - * locality. SLIT will now represent the correct distances between emulated - * nodes as a result of the real topology. - */ -void __init acpi_fake_nodes(const struct bootnode *fake_nodes, int num_nodes) -{ - int i, j; - - for (i = 0; i < num_nodes; i++) { - int nid, pxm; - - nid = find_node_by_addr(fake_nodes[i].start); - if (nid == NUMA_NO_NODE) - continue; - pxm = node_to_pxm(nid); - if (pxm == PXM_INVAL) - continue; - fake_node_to_pxm_map[i] = pxm; - /* - * For each apicid_to_node mapping that exists for this real - * node, it must now point to the fake node ID. - */ - for (j = 0; j < MAX_LOCAL_APIC; j++) - if (apicid_to_node[j] == nid && - fake_apicid_to_node[j] == NUMA_NO_NODE) - fake_apicid_to_node[j] = i; - } - - /* - * If there are apicid-to-node mappings for physical nodes that do not - * have a corresponding emulated node, it should default to a guaranteed - * value. - */ - for (i = 0; i < MAX_LOCAL_APIC; i++) - if (apicid_to_node[i] != NUMA_NO_NODE && - fake_apicid_to_node[i] == NUMA_NO_NODE) - fake_apicid_to_node[i] = 0; - - for (i = 0; i < num_nodes; i++) - __acpi_map_pxm_to_node(fake_node_to_pxm_map[i], i); - memcpy(apicid_to_node, fake_apicid_to_node, sizeof(apicid_to_node)); - - nodes_clear(nodes_parsed); - for (i = 0; i < num_nodes; i++) - if (fake_nodes[i].start != fake_nodes[i].end) - node_set(i, nodes_parsed); -} - -static int null_slit_node_compare(int a, int b) -{ - return node_to_pxm(a) == node_to_pxm(b); -} -#else -static int null_slit_node_compare(int a, int b) -{ - return a == b; -} -#endif /* CONFIG_NUMA_EMU */ - -int __node_distance(int a, int b) -{ - int index; - - if (!acpi_slit) - return null_slit_node_compare(a, b) ? LOCAL_DISTANCE : - REMOTE_DISTANCE; - index = acpi_slit->locality_count * node_to_pxm(a); - return acpi_slit->entry[index + node_to_pxm(b)]; -} - -EXPORT_SYMBOL(__node_distance); - #if defined(CONFIG_MEMORY_HOTPLUG_SPARSE) || defined(CONFIG_ACPI_HOTPLUG_MEMORY) int memory_add_physaddr_to_nid(u64 start) { diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 6acc724d5d8f..d6c0418c3e47 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -179,12 +179,8 @@ static void flush_tlb_others_ipi(const struct cpumask *cpumask, sender = this_cpu_read(tlb_vector_offset); f = &flush_state[sender]; - /* - * Could avoid this lock when - * num_online_cpus() <= NUM_INVALIDATE_TLB_VECTORS, but it is - * probably not worth checking this for a cache-hot lock. - */ - raw_spin_lock(&f->tlbstate_lock); + if (nr_cpu_ids > NUM_INVALIDATE_TLB_VECTORS) + raw_spin_lock(&f->tlbstate_lock); f->flush_mm = mm; f->flush_va = va; @@ -202,7 +198,8 @@ static void flush_tlb_others_ipi(const struct cpumask *cpumask, f->flush_mm = NULL; f->flush_va = 0; - raw_spin_unlock(&f->tlbstate_lock); + if (nr_cpu_ids > NUM_INVALIDATE_TLB_VECTORS) + raw_spin_unlock(&f->tlbstate_lock); } void native_flush_tlb_others(const struct cpumask *cpumask, @@ -211,11 +208,10 @@ void native_flush_tlb_others(const struct cpumask *cpumask, if (is_uv_system()) { unsigned int cpu; - cpu = get_cpu(); + cpu = smp_processor_id(); cpumask = uv_flush_tlb_others(cpumask, mm, va, cpu); if (cpumask) flush_tlb_others_ipi(cpumask, mm, va); - put_cpu(); return; } flush_tlb_others_ipi(cpumask, mm, va); diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c index e27dffbbb1a7..026e4931d162 100644 --- a/arch/x86/pci/amd_bus.c +++ b/arch/x86/pci/amd_bus.c @@ -350,7 +350,7 @@ static int __init early_fill_mp_bus_info(void) #define ENABLE_CF8_EXT_CFG (1ULL << 46) -static void enable_pci_io_ecs(void *unused) +static void __cpuinit enable_pci_io_ecs(void *unused) { u64 reg; rdmsrl(MSR_AMD64_NB_CFG, reg); diff --git a/arch/x86/pci/ce4100.c b/arch/x86/pci/ce4100.c index 9260b3eb18d4..67858be4b52b 100644 --- a/arch/x86/pci/ce4100.c +++ b/arch/x86/pci/ce4100.c @@ -255,7 +255,7 @@ int bridge_read(unsigned int devfn, int reg, int len, u32 *value) static int ce4100_conf_read(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 *value) { - int i, retval = 1; + int i; if (bus == 1) { for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) { diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c index 8c4085a95ef1..e37b407a0ee8 100644 --- a/arch/x86/pci/xen.c +++ b/arch/x86/pci/xen.c @@ -50,7 +50,7 @@ static int acpi_register_gsi_xen_hvm(struct device *dev, u32 gsi, name = "ioapic-level"; } - irq = xen_map_pirq_gsi(map_irq.pirq, gsi, shareable, name); + irq = xen_bind_pirq_gsi_to_irq(gsi, map_irq.pirq, shareable, name); printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq); @@ -237,6 +237,7 @@ static int xen_pcifront_enable_irq(struct pci_dev *dev) { int rc; int share = 1; + int pirq; u8 gsi; rc = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi); @@ -246,13 +247,21 @@ static int xen_pcifront_enable_irq(struct pci_dev *dev) return rc; } + rc = xen_allocate_pirq_gsi(gsi); + if (rc < 0) { + dev_warn(&dev->dev, "Xen PCI: failed to allocate a PIRQ for GSI%d: %d\n", + gsi, rc); + return rc; + } + pirq = rc; + if (gsi < NR_IRQS_LEGACY) share = 0; - rc = xen_allocate_pirq(gsi, share, "pcifront"); + rc = xen_bind_pirq_gsi_to_irq(gsi, pirq, share, "pcifront"); if (rc < 0) { - dev_warn(&dev->dev, "Xen PCI: failed to register GSI%d: %d\n", - gsi, rc); + dev_warn(&dev->dev, "Xen PCI: failed to bind GSI%d (PIRQ%d) to IRQ: %d\n", + gsi, pirq, rc); return rc; } @@ -309,7 +318,7 @@ int __init pci_xen_hvm_init(void) #ifdef CONFIG_XEN_DOM0 static int xen_register_pirq(u32 gsi, int triggering) { - int rc, irq; + int rc, pirq, irq = -1; struct physdev_map_pirq map_irq; int shareable = 0; char *name; @@ -325,17 +334,20 @@ static int xen_register_pirq(u32 gsi, int triggering) name = "ioapic-level"; } - irq = xen_allocate_pirq(gsi, shareable, name); - - printk(KERN_DEBUG "xen: --> irq=%d\n", irq); + pirq = xen_allocate_pirq_gsi(gsi); + if (pirq < 0) + goto out; + irq = xen_bind_pirq_gsi_to_irq(gsi, pirq, shareable, name); if (irq < 0) goto out; + printk(KERN_DEBUG "xen: --> pirq=%d -> irq=%d\n", pirq, irq); + map_irq.domid = DOMID_SELF; map_irq.type = MAP_PIRQ_TYPE_GSI; map_irq.index = gsi; - map_irq.pirq = irq; + map_irq.pirq = pirq; rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq); if (rc) { @@ -422,13 +434,18 @@ static int __init pci_xen_initial_domain(void) void __init xen_setup_pirqs(void) { - int irq; + int pirq, irq; pci_xen_initial_domain(); if (0 == nr_ioapics) { - for (irq = 0; irq < NR_IRQS_LEGACY; irq++) - xen_allocate_pirq(irq, 0, "xt-pic"); + for (irq = 0; irq < NR_IRQS_LEGACY; irq++) { + pirq = xen_allocate_pirq_gsi(irq); + if (WARN(pirq < 0, + "Could not allocate PIRQ for legacy interrupt\n")) + break; + irq = xen_bind_pirq_gsi_to_irq(irq, pirq, 0, "xt-pic"); + } return; } diff --git a/arch/x86/platform/ce4100/ce4100.c b/arch/x86/platform/ce4100/ce4100.c index cd6f184c3b3f..28071bb31db7 100644 --- a/arch/x86/platform/ce4100/ce4100.c +++ b/arch/x86/platform/ce4100/ce4100.c @@ -16,21 +16,19 @@ #include <linux/serial_8250.h> #include <asm/ce4100.h> +#include <asm/prom.h> #include <asm/setup.h> +#include <asm/i8259.h> #include <asm/io.h> +#include <asm/io_apic.h> static int ce4100_i8042_detect(void) { return 0; } -static void __init sdv_find_smp_config(void) -{ -} - #ifdef CONFIG_SERIAL_8250 - static unsigned int mem_serial_in(struct uart_port *p, int offset) { offset = offset << p->regshift; @@ -119,6 +117,15 @@ static void __init sdv_arch_setup(void) sdv_serial_fixup(); } +#ifdef CONFIG_X86_IO_APIC +static void __cpuinit sdv_pci_init(void) +{ + x86_of_pci_init(); + /* We can't set this earlier, because we need to calibrate the timer */ + legacy_pic = &null_legacy_pic; +} +#endif + /* * CE4100 specific x86_init function overrides and early setup * calls. @@ -129,6 +136,11 @@ void __init x86_ce4100_early_setup(void) x86_platform.i8042_detect = ce4100_i8042_detect; x86_init.resources.probe_roms = x86_init_noop; x86_init.mpparse.get_smp_config = x86_init_uint_noop; - x86_init.mpparse.find_smp_config = sdv_find_smp_config; + x86_init.mpparse.find_smp_config = x86_init_noop; x86_init.pci.init = ce4100_pci_init; + +#ifdef CONFIG_X86_IO_APIC + x86_init.pci.init_irq = sdv_pci_init; + x86_init.mpparse.setup_ioapic_ids = setup_ioapic_ids_from_mpc_nocheck; +#endif } diff --git a/arch/x86/platform/ce4100/falconfalls.dts b/arch/x86/platform/ce4100/falconfalls.dts new file mode 100644 index 000000000000..dc701ea58546 --- /dev/null +++ b/arch/x86/platform/ce4100/falconfalls.dts @@ -0,0 +1,428 @@ +/* + * CE4100 on Falcon Falls + * + * (c) Copyright 2010 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; version 2 of the License. + */ +/dts-v1/; +/ { + model = "intel,falconfalls"; + compatible = "intel,falconfalls"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "intel,ce4100"; + reg = <0>; + lapic = <&lapic0>; + }; + }; + + soc@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "intel,ce4100-cp"; + ranges; + + ioapic1: interrupt-controller@fec00000 { + #interrupt-cells = <2>; + compatible = "intel,ce4100-ioapic"; + interrupt-controller; + reg = <0xfec00000 0x1000>; + }; + + timer@fed00000 { + compatible = "intel,ce4100-hpet"; + reg = <0xfed00000 0x200>; + }; + + lapic0: interrupt-controller@fee00000 { + compatible = "intel,ce4100-lapic"; + reg = <0xfee00000 0x1000>; + }; + + pci@3fc { + #address-cells = <3>; + #size-cells = <2>; + compatible = "intel,ce4100-pci", "pci"; + device_type = "pci"; + bus-range = <0 0>; + ranges = <0x2000000 0 0xbffff000 0xbffff000 0 0x1000 + 0x2000000 0 0xdffe0000 0xdffe0000 0 0x1000 + 0x0000000 0 0x0 0x0 0 0x100>; + + /* Secondary IO-APIC */ + ioapic2: interrupt-controller@0,1 { + #interrupt-cells = <2>; + compatible = "intel,ce4100-ioapic"; + interrupt-controller; + reg = <0x100 0x0 0x0 0x0 0x0>; + assigned-addresses = <0x02000000 0x0 0xbffff000 0x0 0x1000>; + }; + + pci@1,0 { + #address-cells = <3>; + #size-cells = <2>; + compatible = "intel,ce4100-pci", "pci"; + device_type = "pci"; + bus-range = <1 1>; + ranges = <0x2000000 0 0xdffe0000 0x2000000 0 0xdffe0000 0 0x1000>; + + interrupt-parent = <&ioapic2>; + + display@2,0 { + compatible = "pci8086,2e5b.2", + "pci8086,2e5b", + "pciclass038000", + "pciclass0380"; + + reg = <0x11000 0x0 0x0 0x0 0x0>; + interrupts = <0 1>; + }; + + multimedia@3,0 { + compatible = "pci8086,2e5c.2", + "pci8086,2e5c", + "pciclass048000", + "pciclass0480"; + + reg = <0x11800 0x0 0x0 0x0 0x0>; + interrupts = <2 1>; + }; + + multimedia@4,0 { + compatible = "pci8086,2e5d.2", + "pci8086,2e5d", + "pciclass048000", + "pciclass0480"; + + reg = <0x12000 0x0 0x0 0x0 0x0>; + interrupts = <4 1>; + }; + + multimedia@4,1 { + compatible = "pci8086,2e5e.2", + "pci8086,2e5e", + "pciclass048000", + "pciclass0480"; + + reg = <0x12100 0x0 0x0 0x0 0x0>; + interrupts = <5 1>; + }; + + sound@6,0 { + compatible = "pci8086,2e5f.2", + "pci8086,2e5f", + "pciclass040100", + "pciclass0401"; + + reg = <0x13000 0x0 0x0 0x0 0x0>; + interrupts = <6 1>; + }; + + sound@6,1 { + compatible = "pci8086,2e5f.2", + "pci8086,2e5f", + "pciclass040100", + "pciclass0401"; + + reg = <0x13100 0x0 0x0 0x0 0x0>; + interrupts = <7 1>; + }; + + sound@6,2 { + compatible = "pci8086,2e60.2", + "pci8086,2e60", + "pciclass040100", + "pciclass0401"; + + reg = <0x13200 0x0 0x0 0x0 0x0>; + interrupts = <8 1>; + }; + + display@8,0 { + compatible = "pci8086,2e61.2", + "pci8086,2e61", + "pciclass038000", + "pciclass0380"; + + reg = <0x14000 0x0 0x0 0x0 0x0>; + interrupts = <9 1>; + }; + + display@8,1 { + compatible = "pci8086,2e62.2", + "pci8086,2e62", + "pciclass038000", + "pciclass0380"; + + reg = <0x14100 0x0 0x0 0x0 0x0>; + interrupts = <10 1>; + }; + + multimedia@8,2 { + compatible = "pci8086,2e63.2", + "pci8086,2e63", + "pciclass048000", + "pciclass0480"; + + reg = <0x14200 0x0 0x0 0x0 0x0>; + interrupts = <11 1>; + }; + + entertainment-encryption@9,0 { + compatible = "pci8086,2e64.2", + "pci8086,2e64", + "pciclass101000", + "pciclass1010"; + + reg = <0x14800 0x0 0x0 0x0 0x0>; + interrupts = <12 1>; + }; + + localbus@a,0 { + compatible = "pci8086,2e65.2", + "pci8086,2e65", + "pciclassff0000", + "pciclassff00"; + + reg = <0x15000 0x0 0x0 0x0 0x0>; + }; + + serial@b,0 { + compatible = "pci8086,2e66.2", + "pci8086,2e66", + "pciclass070003", + "pciclass0700"; + + reg = <0x15800 0x0 0x0 0x0 0x0>; + interrupts = <14 1>; + }; + + gpio@b,1 { + compatible = "pci8086,2e67.2", + "pci8086,2e67", + "pciclassff0000", + "pciclassff00"; + + #gpio-cells = <2>; + reg = <0x15900 0x0 0x0 0x0 0x0>; + interrupts = <15 1>; + gpio-controller; + }; + + i2c-controller@b,2 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "pci8086,2e68.2", + "pci8086,2e68", + "pciclass,ff0000", + "pciclass,ff00"; + + reg = <0x15a00 0x0 0x0 0x0 0x0>; + interrupts = <16 1>; + ranges = <0 0 0x02000000 0 0xdffe0500 0x100 + 1 0 0x02000000 0 0xdffe0600 0x100 + 2 0 0x02000000 0 0xdffe0700 0x100>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ce4100-i2c-controller"; + reg = <0 0 0x100>; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ce4100-i2c-controller"; + reg = <1 0 0x100>; + + gpio@26 { + #gpio-cells = <2>; + compatible = "ti,pcf8575"; + reg = <0x26>; + gpio-controller; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ce4100-i2c-controller"; + reg = <2 0 0x100>; + + gpio@26 { + #gpio-cells = <2>; + compatible = "ti,pcf8575"; + reg = <0x26>; + gpio-controller; + }; + }; + }; + + smard-card@b,3 { + compatible = "pci8086,2e69.2", + "pci8086,2e69", + "pciclass070500", + "pciclass0705"; + + reg = <0x15b00 0x0 0x0 0x0 0x0>; + interrupts = <15 1>; + }; + + spi-controller@b,4 { + #address-cells = <1>; + #size-cells = <0>; + compatible = + "pci8086,2e6a.2", + "pci8086,2e6a", + "pciclass,ff0000", + "pciclass,ff00"; + + reg = <0x15c00 0x0 0x0 0x0 0x0>; + interrupts = <15 1>; + + dac@0 { + compatible = "ti,pcm1755"; + reg = <0>; + spi-max-frequency = <115200>; + }; + + dac@1 { + compatible = "ti,pcm1609a"; + reg = <1>; + spi-max-frequency = <115200>; + }; + + eeprom@2 { + compatible = "atmel,at93c46"; + reg = <2>; + spi-max-frequency = <115200>; + }; + }; + + multimedia@b,7 { + compatible = "pci8086,2e6d.2", + "pci8086,2e6d", + "pciclassff0000", + "pciclassff00"; + + reg = <0x15f00 0x0 0x0 0x0 0x0>; + }; + + ethernet@c,0 { + compatible = "pci8086,2e6e.2", + "pci8086,2e6e", + "pciclass020000", + "pciclass0200"; + + reg = <0x16000 0x0 0x0 0x0 0x0>; + interrupts = <21 1>; + }; + + clock@c,1 { + compatible = "pci8086,2e6f.2", + "pci8086,2e6f", + "pciclassff0000", + "pciclassff00"; + + reg = <0x16100 0x0 0x0 0x0 0x0>; + interrupts = <3 1>; + }; + + usb@d,0 { + compatible = "pci8086,2e70.2", + "pci8086,2e70", + "pciclass0c0320", + "pciclass0c03"; + + reg = <0x16800 0x0 0x0 0x0 0x0>; + interrupts = <22 3>; + }; + + usb@d,1 { + compatible = "pci8086,2e70.2", + "pci8086,2e70", + "pciclass0c0320", + "pciclass0c03"; + + reg = <0x16900 0x0 0x0 0x0 0x0>; + interrupts = <22 3>; + }; + + sata@e,0 { + compatible = "pci8086,2e71.0", + "pci8086,2e71", + "pciclass010601", + "pciclass0106"; + + reg = <0x17000 0x0 0x0 0x0 0x0>; + interrupts = <23 3>; + }; + + flash@f,0 { + compatible = "pci8086,701.1", + "pci8086,701", + "pciclass050100", + "pciclass0501"; + + reg = <0x17800 0x0 0x0 0x0 0x0>; + interrupts = <13 1>; + }; + + entertainment-encryption@10,0 { + compatible = "pci8086,702.1", + "pci8086,702", + "pciclass101000", + "pciclass1010"; + + reg = <0x18000 0x0 0x0 0x0 0x0>; + }; + + co-processor@11,0 { + compatible = "pci8086,703.1", + "pci8086,703", + "pciclass0b4000", + "pciclass0b40"; + + reg = <0x18800 0x0 0x0 0x0 0x0>; + interrupts = <1 1>; + }; + + multimedia@12,0 { + compatible = "pci8086,704.0", + "pci8086,704", + "pciclass048000", + "pciclass0480"; + + reg = <0x19000 0x0 0x0 0x0 0x0>; + }; + }; + + isa@1f,0 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "isa"; + ranges = <1 0 0 0 0 0x100>; + + rtc@70 { + compatible = "intel,ce4100-rtc", "motorola,mc146818"; + interrupts = <8 3>; + interrupt-parent = <&ioapic1>; + ctrl-reg = <2>; + freq-reg = <0x26>; + reg = <1 0x70 2>; + }; + }; + }; + }; +}; diff --git a/arch/x86/platform/mrst/mrst.c b/arch/x86/platform/mrst/mrst.c index ea6529e93c6f..5c0207bf959b 100644 --- a/arch/x86/platform/mrst/mrst.c +++ b/arch/x86/platform/mrst/mrst.c @@ -31,6 +31,7 @@ #include <asm/apic.h> #include <asm/io_apic.h> #include <asm/mrst.h> +#include <asm/mrst-vrtc.h> #include <asm/io.h> #include <asm/i8259.h> #include <asm/intel_scu_ipc.h> @@ -268,6 +269,7 @@ void __init x86_mrst_early_setup(void) x86_platform.calibrate_tsc = mrst_calibrate_tsc; x86_platform.i8042_detect = mrst_i8042_detect; + x86_init.timers.wallclock_init = mrst_rtc_init; x86_init.pci.init = pci_mrst_init; x86_init.pci.fixup_irqs = x86_init_noop; diff --git a/arch/x86/platform/mrst/vrtc.c b/arch/x86/platform/mrst/vrtc.c index 32cd7edd71a0..04cf645feb92 100644 --- a/arch/x86/platform/mrst/vrtc.c +++ b/arch/x86/platform/mrst/vrtc.c @@ -100,22 +100,14 @@ int vrtc_set_mmss(unsigned long nowtime) void __init mrst_rtc_init(void) { - unsigned long rtc_paddr; - void __iomem *virt_base; + unsigned long vrtc_paddr = sfi_mrtc_array[0].phys_addr; sfi_table_parse(SFI_SIG_MRTC, NULL, NULL, sfi_parse_mrtc); - if (!sfi_mrtc_num) + if (!sfi_mrtc_num || !vrtc_paddr) return; - rtc_paddr = sfi_mrtc_array[0].phys_addr; - - /* vRTC's register address may not be page aligned */ - set_fixmap_nocache(FIX_LNW_VRTC, rtc_paddr); - - virt_base = (void __iomem *)__fix_to_virt(FIX_LNW_VRTC); - virt_base += rtc_paddr & ~PAGE_MASK; - vrtc_virt_base = virt_base; - + vrtc_virt_base = (void __iomem *)set_fixmap_offset_nocache(FIX_LNW_VRTC, + vrtc_paddr); x86_platform.get_wallclock = vrtc_get_time; x86_platform.set_wallclock = vrtc_set_mmss; } diff --git a/arch/x86/platform/olpc/Makefile b/arch/x86/platform/olpc/Makefile index e797428b163b..c2a8cab65e5d 100644 --- a/arch/x86/platform/olpc/Makefile +++ b/arch/x86/platform/olpc/Makefile @@ -1,4 +1,4 @@ obj-$(CONFIG_OLPC) += olpc.o obj-$(CONFIG_OLPC_XO1) += olpc-xo1.o -obj-$(CONFIG_OLPC_OPENFIRMWARE) += olpc_ofw.o -obj-$(CONFIG_OLPC_OPENFIRMWARE_DT) += olpc_dt.o +obj-$(CONFIG_OLPC) += olpc_ofw.o +obj-$(CONFIG_OF_PROMTREE) += olpc_dt.o diff --git a/arch/x86/platform/uv/uv_irq.c b/arch/x86/platform/uv/uv_irq.c index 7b24460917d5..374a05d8ad22 100644 --- a/arch/x86/platform/uv/uv_irq.c +++ b/arch/x86/platform/uv/uv_irq.c @@ -131,7 +131,7 @@ arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, unsigned long mmr_offset, int limit) { const struct cpumask *eligible_cpu = cpumask_of(cpu); - struct irq_cfg *cfg = get_irq_chip_data(irq); + struct irq_cfg *cfg = irq_get_chip_data(irq); unsigned long mmr_value; struct uv_IO_APIC_route_entry *entry; int mmr_pnode, err; @@ -148,7 +148,7 @@ arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, else irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); - set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq, + irq_set_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq, irq_name); mmr_value = 0; diff --git a/arch/x86/platform/visws/visws_quirks.c b/arch/x86/platform/visws/visws_quirks.c index 632037671746..fe4cf8294878 100644 --- a/arch/x86/platform/visws/visws_quirks.c +++ b/arch/x86/platform/visws/visws_quirks.c @@ -569,11 +569,13 @@ out_unlock: static struct irqaction master_action = { .handler = piix4_master_intr, .name = "PIIX4-8259", + .flags = IRQF_NO_THREAD, }; static struct irqaction cascade_action = { .handler = no_action, .name = "cascade", + .flags = IRQF_NO_THREAD, }; static inline void set_piix4_virtual_irq_type(void) @@ -606,7 +608,7 @@ static void __init visws_pre_intr_init(void) chip = &cobalt_irq_type; if (chip) - set_irq_chip(i, chip); + irq_set_chip(i, chip); } setup_irq(CO_IRQ_8259, &master_action); diff --git a/arch/x86/xen/Kconfig b/arch/x86/xen/Kconfig index e4343fe488ed..1c7121ba18ff 100644 --- a/arch/x86/xen/Kconfig +++ b/arch/x86/xen/Kconfig @@ -38,7 +38,7 @@ config XEN_MAX_DOMAIN_MEMORY config XEN_SAVE_RESTORE bool - depends on XEN && PM + depends on XEN default y config XEN_DEBUG_FS diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c index 832765c0fb8c..5695fa66d565 100644 --- a/arch/x86/xen/mmu.c +++ b/arch/x86/xen/mmu.c @@ -79,8 +79,7 @@ /* * Protects atomic reservation decrease/increase against concurrent increases. - * Also protects non-atomic updates of current_pages and driver_pages, and - * balloon lists. + * Also protects non-atomic updates of current_pages and balloon lists. */ DEFINE_SPINLOCK(xen_reservation_lock); @@ -1491,7 +1490,7 @@ static __init pte_t mask_rw_pte(pte_t *ptep, pte_t pte) * early_ioremap fixmap slot, make sure it is RO. */ if (!is_early_ioremap_ptep(ptep) && - pfn >= e820_table_start && pfn < e820_table_end) + pfn >= pgt_buf_start && pfn < pgt_buf_end) pte = pte_wrprotect(pte); return pte; diff --git a/arch/x86/xen/xen-head.S b/arch/x86/xen/xen-head.S index 1a5ff24e29c0..aaa7291c9259 100644 --- a/arch/x86/xen/xen-head.S +++ b/arch/x86/xen/xen-head.S @@ -28,9 +28,9 @@ ENTRY(startup_xen) __FINIT .pushsection .text - .align PAGE_SIZE_asm + .align PAGE_SIZE ENTRY(hypercall_page) - .skip PAGE_SIZE_asm + .skip PAGE_SIZE .popsection ELFNOTE(Xen, XEN_ELFNOTE_GUEST_OS, .asciz "linux") diff --git a/arch/xtensa/include/asm/ioctls.h b/arch/xtensa/include/asm/ioctls.h index ccf1800f0b0c..fd1d1369a407 100644 --- a/arch/xtensa/include/asm/ioctls.h +++ b/arch/xtensa/include/asm/ioctls.h @@ -100,6 +100,7 @@ #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ #define TIOCGDEV _IOR('T',0x32, unsigned int) /* Get primary device node of /dev/console */ #define TIOCSIG _IOW('T',0x36, int) /* Generate signal on Pty slave */ +#define TIOCVHANGUP _IO('T', 0x37) #define TIOCSERCONFIG _IO('T', 83) #define TIOCSERGWILD _IOR('T', 84, int) diff --git a/arch/xtensa/include/asm/rwsem.h b/arch/xtensa/include/asm/rwsem.h index e39edf5c86f2..249619e7e7f2 100644 --- a/arch/xtensa/include/asm/rwsem.h +++ b/arch/xtensa/include/asm/rwsem.h @@ -17,44 +17,12 @@ #error "Please don't include <asm/rwsem.h> directly, use <linux/rwsem.h> instead." #endif -#include <linux/list.h> -#include <linux/spinlock.h> -#include <asm/atomic.h> -#include <asm/system.h> - -/* - * the semaphore definition - */ -struct rw_semaphore { - signed long count; #define RWSEM_UNLOCKED_VALUE 0x00000000 #define RWSEM_ACTIVE_BIAS 0x00000001 #define RWSEM_ACTIVE_MASK 0x0000ffff #define RWSEM_WAITING_BIAS (-0x00010000) #define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS #define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS) - spinlock_t wait_lock; - struct list_head wait_list; -}; - -#define __RWSEM_INITIALIZER(name) \ - { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \ - LIST_HEAD_INIT((name).wait_list) } - -#define DECLARE_RWSEM(name) \ - struct rw_semaphore name = __RWSEM_INITIALIZER(name) - -extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem); -extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem); -extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem); -extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem); - -static inline void init_rwsem(struct rw_semaphore *sem) -{ - sem->count = RWSEM_UNLOCKED_VALUE; - spin_lock_init(&sem->wait_lock); - INIT_LIST_HEAD(&sem->wait_list); -} /* * lock for reading @@ -160,9 +128,4 @@ static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem) return atomic_add_return(delta, (atomic_t *)(&sem->count)); } -static inline int rwsem_is_locked(struct rw_semaphore *sem) -{ - return (sem->count != 0); -} - #endif /* _XTENSA_RWSEM_H */ diff --git a/arch/xtensa/kernel/time.c b/arch/xtensa/kernel/time.c index 19df764f6399..f3e5eb43f71c 100644 --- a/arch/xtensa/kernel/time.c +++ b/arch/xtensa/kernel/time.c @@ -96,16 +96,12 @@ again: update_process_times(user_mode(get_irq_regs())); #endif - write_seqlock(&xtime_lock); - - do_timer(1); /* Linux handler in kernel/timer.c */ + xtime_update(1); /* Linux handler in kernel/time/timekeeping */ /* Note that writing CCOMPARE clears the interrupt. */ next += CCOUNT_PER_JIFFY; set_linux_timer(next); - - write_sequnlock(&xtime_lock); } /* Allow platform to do something useful (Wdog). */ diff --git a/arch/xtensa/kernel/vmlinux.lds.S b/arch/xtensa/kernel/vmlinux.lds.S index 9b526154c9ba..a2820065927e 100644 --- a/arch/xtensa/kernel/vmlinux.lds.S +++ b/arch/xtensa/kernel/vmlinux.lds.S @@ -155,7 +155,7 @@ SECTIONS INIT_RAM_FS } - PERCPU(PAGE_SIZE) + PERCPU(XCHAL_ICACHE_LINESIZE, PAGE_SIZE) /* We need this dummy segment here */ |