diff options
Diffstat (limited to 'arch/tile/include/asm/cache.h')
| -rw-r--r-- | arch/tile/include/asm/cache.h | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h index 4810e48dbbbf..7d6aaa128e8b 100644 --- a/arch/tile/include/asm/cache.h +++ b/arch/tile/include/asm/cache.h @@ -50,18 +50,15 @@ /* * Originally we used small TLB pages for kernel data and grouped some - * things together as "write once", enforcing the property at the end + * things together as ro-after-init, enforcing the property at the end * of initialization by making those pages read-only and non-coherent. * This allowed better cache utilization since cache inclusion did not * need to be maintained. However, to do this requires an extra TLB * entry, which on balance is more of a performance hit than the * non-coherence is a performance gain, so we now just make "read - * mostly" and "write once" be synonyms. We keep the attribute + * mostly" and "ro-after-init" be synonyms. We keep the attribute * separate in case we change our minds at a future date. */ -#define __write_once __read_mostly - -/* __ro_after_init is the generic name for the tile arch __write_once. */ #define __ro_after_init __read_mostly #endif /* _ASM_TILE_CACHE_H */ |