diff options
Diffstat (limited to 'arch/sh/kernel/cpu/sh4/probe.c')
| -rw-r--r-- | arch/sh/kernel/cpu/sh4/probe.c | 130 |
1 files changed, 55 insertions, 75 deletions
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c index 91e3677ae09d..6c78d0a9c857 100644 --- a/arch/sh/kernel/cpu/sh4/probe.c +++ b/arch/sh/kernel/cpu/sh4/probe.c @@ -60,12 +60,18 @@ int __init detect_cpu_and_cache_system(void) if ((cvr & 0x10000000) == 0) boot_cpu_data.flags |= CPU_HAS_DSP; - boot_cpu_data.flags |= CPU_HAS_LLSC; + boot_cpu_data.flags |= CPU_HAS_LLSC | CPU_HAS_PERF_COUNTER; boot_cpu_data.cut_major = pvr & 0x7f; + + boot_cpu_data.icache.ways = 4; + boot_cpu_data.dcache.ways = 4; + } else { + /* And some SH-4 defaults.. */ + boot_cpu_data.flags |= CPU_HAS_PTEA; } /* FPU detection works for everyone */ - if ((cvr & 0x20000000) == 1) + if ((cvr & 0x20000000)) boot_cpu_data.flags |= CPU_HAS_FPU; /* Mask off the upper chip ID */ @@ -78,25 +84,20 @@ int __init detect_cpu_and_cache_system(void) switch (pvr) { case 0x205: boot_cpu_data.type = CPU_SH7750; - boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | - CPU_HAS_PERF_COUNTER; + boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | + CPU_HAS_PERF_COUNTER; break; case 0x206: boot_cpu_data.type = CPU_SH7750S; - boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | - CPU_HAS_PERF_COUNTER; + boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | + CPU_HAS_PERF_COUNTER; break; case 0x1100: boot_cpu_data.type = CPU_SH7751; - boot_cpu_data.flags |= CPU_HAS_FPU; break; case 0x2001: case 0x2004: boot_cpu_data.type = CPU_SH7770; - boot_cpu_data.icache.ways = 4; - boot_cpu_data.dcache.ways = 4; - - boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC; break; case 0x2006: case 0x200A: @@ -107,45 +108,26 @@ int __init detect_cpu_and_cache_system(void) else boot_cpu_data.type = CPU_SH7780; - boot_cpu_data.icache.ways = 4; - boot_cpu_data.dcache.ways = 4; - - boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | - CPU_HAS_LLSC; break; case 0x3000: case 0x3003: case 0x3009: boot_cpu_data.type = CPU_SH7343; - boot_cpu_data.icache.ways = 4; - boot_cpu_data.dcache.ways = 4; - boot_cpu_data.flags |= CPU_HAS_LLSC; break; case 0x3004: case 0x3007: boot_cpu_data.type = CPU_SH7785; - boot_cpu_data.icache.ways = 4; - boot_cpu_data.dcache.ways = 4; - boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | - CPU_HAS_LLSC; break; case 0x4004: boot_cpu_data.type = CPU_SH7786; - boot_cpu_data.icache.ways = 4; - boot_cpu_data.dcache.ways = 4; - boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | - CPU_HAS_LLSC | CPU_HAS_PTEAEX; + boot_cpu_data.flags |= CPU_HAS_PTEAEX | CPU_HAS_L2_CACHE; break; case 0x3008: - boot_cpu_data.icache.ways = 4; - boot_cpu_data.dcache.ways = 4; - boot_cpu_data.flags |= CPU_HAS_LLSC; - switch (prr) { case 0x50: case 0x51: boot_cpu_data.type = CPU_SH7723; - boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_L2_CACHE; + boot_cpu_data.flags |= CPU_HAS_L2_CACHE; break; case 0x70: boot_cpu_data.type = CPU_SH7366; @@ -156,13 +138,13 @@ int __init detect_cpu_and_cache_system(void) break; } break; + case 0x300b: + boot_cpu_data.type = CPU_SH7724; + boot_cpu_data.flags |= CPU_HAS_L2_CACHE; + break; case 0x4000: /* 1st cut */ case 0x4001: /* 2nd cut */ boot_cpu_data.type = CPU_SHX3; - boot_cpu_data.icache.ways = 4; - boot_cpu_data.dcache.ways = 4; - boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | - CPU_HAS_LLSC; break; case 0x700: boot_cpu_data.type = CPU_SH4_501; @@ -173,7 +155,6 @@ int __init detect_cpu_and_cache_system(void) boot_cpu_data.type = CPU_SH4_202; boot_cpu_data.icache.ways = 2; boot_cpu_data.dcache.ways = 2; - boot_cpu_data.flags |= CPU_HAS_FPU; break; case 0x500 ... 0x501: switch (prr) { @@ -191,18 +172,12 @@ int __init detect_cpu_and_cache_system(void) boot_cpu_data.icache.ways = 2; boot_cpu_data.dcache.ways = 2; - boot_cpu_data.flags |= CPU_HAS_FPU; - break; default: boot_cpu_data.type = CPU_SH_NONE; break; } -#ifdef CONFIG_CPU_HAS_PTEA - boot_cpu_data.flags |= CPU_HAS_PTEA; -#endif - /* * On anything that's not a direct-mapped cache, look to the CVR * for I/D-cache specifics. @@ -222,43 +197,48 @@ int __init detect_cpu_and_cache_system(void) } /* - * Setup the L2 cache desc - * * SH-4A's have an optional PIPT L2. */ if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) { - /* Bug if we can't decode the L2 info */ - BUG_ON(!(cvr & 0xf)); - - /* Silicon and specifications have clearly never met.. */ - cvr ^= 0xf; - /* - * Size calculation is much more sensible - * than it is for the L1. - * - * Sizes are 128KB, 258KB, 512KB, and 1MB. + * Verify that it really has something hooked up, this + * is the safety net for CPUs that have optional L2 + * support yet do not implement it. */ - size = (cvr & 0xf) << 17; - - BUG_ON(!size); - - boot_cpu_data.scache.way_incr = (1 << 16); - boot_cpu_data.scache.entry_shift = 5; - boot_cpu_data.scache.ways = 4; - boot_cpu_data.scache.linesz = L1_CACHE_BYTES; - - boot_cpu_data.scache.entry_mask = - (boot_cpu_data.scache.way_incr - - boot_cpu_data.scache.linesz); - - boot_cpu_data.scache.sets = size / - (boot_cpu_data.scache.linesz * - boot_cpu_data.scache.ways); - - boot_cpu_data.scache.way_size = - (boot_cpu_data.scache.sets * - boot_cpu_data.scache.linesz); + if ((cvr & 0xf) == 0) + boot_cpu_data.flags &= ~CPU_HAS_L2_CACHE; + else { + /* + * Silicon and specifications have clearly never + * met.. + */ + cvr ^= 0xf; + + /* + * Size calculation is much more sensible + * than it is for the L1. + * + * Sizes are 128KB, 258KB, 512KB, and 1MB. + */ + size = (cvr & 0xf) << 17; + + boot_cpu_data.scache.way_incr = (1 << 16); + boot_cpu_data.scache.entry_shift = 5; + boot_cpu_data.scache.ways = 4; + boot_cpu_data.scache.linesz = L1_CACHE_BYTES; + + boot_cpu_data.scache.entry_mask = + (boot_cpu_data.scache.way_incr - + boot_cpu_data.scache.linesz); + + boot_cpu_data.scache.sets = size / + (boot_cpu_data.scache.linesz * + boot_cpu_data.scache.ways); + + boot_cpu_data.scache.way_size = + (boot_cpu_data.scache.sets * + boot_cpu_data.scache.linesz); + } } return 0; |