diff options
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/mpic.h | 12 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/reg.h | 30 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/reg_booke.h | 30 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/sfp-machine.h | 6 |
4 files changed, 45 insertions, 33 deletions
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h index c2ccca53b991..a002682f3a6d 100644 --- a/arch/powerpc/include/asm/mpic.h +++ b/arch/powerpc/include/asm/mpic.h @@ -22,6 +22,14 @@ #define MPIC_GREG_FEATURE_1 0x00010 #define MPIC_GREG_GLOBAL_CONF_0 0x00020 #define MPIC_GREG_GCONF_RESET 0x80000000 +/* On the FSL mpic implementations the Mode field is expand to be + * 2 bits wide: + * 0b00 = pass through (interrupts routed to IRQ0) + * 0b01 = Mixed mode + * 0b10 = reserved + * 0b11 = External proxy / coreint + */ +#define MPIC_GREG_GCONF_COREINT 0x60000000 #define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000 #define MPIC_GREG_GCONF_NO_BIAS 0x10000000 #define MPIC_GREG_GCONF_BASE_MASK 0x000fffff @@ -357,6 +365,8 @@ struct mpic #define MPIC_BROKEN_FRR_NIRQS 0x00000800 /* Destination only supports a single CPU at a time */ #define MPIC_SINGLE_DEST_CPU 0x00001000 +/* Enable CoreInt delivery of interrupts */ +#define MPIC_ENABLE_COREINT 0x00002000 /* MPIC HW modification ID */ #define MPIC_REGSET_MASK 0xf0000000 @@ -470,6 +480,8 @@ extern void mpic_end_irq(unsigned int irq); extern unsigned int mpic_get_one_irq(struct mpic *mpic); /* This one gets from the primary mpic */ extern unsigned int mpic_get_irq(void); +/* This one gets from the primary mpic via CoreInt*/ +extern unsigned int mpic_get_coreint_irq(void); /* Fetch Machine Check interrupt from primary mpic */ extern unsigned int mpic_get_mcirq(void); diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index c9ff1ec97479..e8018d540e87 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -143,6 +143,36 @@ #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ #define FPSCR_RN 0x00000003 /* FPU rounding control */ +/* Bit definitions for SPEFSCR. */ +#define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */ +#define SPEFSCR_OVH 0x40000000 /* Integer overflow high */ +#define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */ +#define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */ +#define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */ +#define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */ +#define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */ +#define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */ +#define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */ +#define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */ +#define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */ +#define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */ +#define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */ +#define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */ +#define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */ +#define SPEFSCR_OV 0x00004000 /* Integer overflow */ +#define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */ +#define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */ +#define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */ +#define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */ +#define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */ +#define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */ +#define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */ +#define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */ +#define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */ +#define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */ +#define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */ +#define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */ + /* Special Purpose Registers (SPRNs)*/ #define SPRN_CTR 0x009 /* Count Register */ #define SPRN_DSCR 0x11 diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index a56f4d61aa72..601ddbc46002 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -423,36 +423,6 @@ #define SGR_NORMAL 0 /* Speculative fetching allowed. */ #define SGR_GUARDED 1 /* Speculative fetching disallowed. */ -/* Bit definitions for SPEFSCR. */ -#define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */ -#define SPEFSCR_OVH 0x40000000 /* Integer overflow high */ -#define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */ -#define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */ -#define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */ -#define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */ -#define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */ -#define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */ -#define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */ -#define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */ -#define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */ -#define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */ -#define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */ -#define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */ -#define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */ -#define SPEFSCR_OV 0x00004000 /* Integer overflow */ -#define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */ -#define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */ -#define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */ -#define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */ -#define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */ -#define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */ -#define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */ -#define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */ -#define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */ -#define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */ -#define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */ -#define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */ - /* * The IBM-403 is an even more odd special case, as it is much * older than the IBM-405 series. We put these down here incase someone diff --git a/arch/powerpc/include/asm/sfp-machine.h b/arch/powerpc/include/asm/sfp-machine.h index 3d9f831c3c55..3a7a67a0d006 100644 --- a/arch/powerpc/include/asm/sfp-machine.h +++ b/arch/powerpc/include/asm/sfp-machine.h @@ -29,9 +29,9 @@ /* basic word size definitions */ #define _FP_W_TYPE_SIZE 32 -#define _FP_W_TYPE unsigned long -#define _FP_WS_TYPE signed long -#define _FP_I_TYPE long +#define _FP_W_TYPE unsigned int +#define _FP_WS_TYPE signed int +#define _FP_I_TYPE int #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2)) #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1)) |