diff options
Diffstat (limited to 'arch/mips')
259 files changed, 5224 insertions, 7791 deletions
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index d9d81c219253..6e239123d6fe 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -20,7 +20,6 @@ platforms += mti-sead3 platforms += netlogic platforms += pmcs-msp71xx platforms += pnx833x -platforms += powertv platforms += ralink platforms += rb532 platforms += sgi-ip22 diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index dccd7cec442d..650de3976e7a 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1,6 +1,7 @@ config MIPS bool default y + select ARCH_MIGHT_HAVE_PC_PARPORT select HAVE_CONTEXT_TRACKING select HAVE_GENERIC_DMA_COHERENT select HAVE_IDE @@ -8,6 +9,7 @@ config MIPS select HAVE_PERF_EVENTS select PERF_USE_VMALLOC select HAVE_ARCH_KGDB + select HAVE_ARCH_TRACEHOOK select ARCH_HAVE_CUSTOM_GPIO_H select HAVE_FUNCTION_TRACER select HAVE_FUNCTION_TRACE_MCOUNT_TEST @@ -18,6 +20,7 @@ config MIPS select HAVE_KPROBES select HAVE_KRETPROBES select HAVE_DEBUG_KMEMLEAK + select HAVE_SYSCALL_TRACEPOINTS select ARCH_BINFMT_ELF_RANDOMIZE_PIE select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT select RTC_LIB if !MACH_LOONGSON @@ -25,7 +28,6 @@ config MIPS select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE select HAVE_DMA_ATTRS select HAVE_DMA_API_DEBUG - select HAVE_GENERIC_HARDIRQS select GENERIC_IRQ_PROBE select GENERIC_IRQ_SHOW select GENERIC_PCI_IOMAP @@ -95,6 +97,7 @@ config ATH79 select CSRC_R4K select DMA_NONCOHERENT select HAVE_CLK + select CLKDEV_LOOKUP select IRQ_CPU select MIPS_MACHINE select SYS_HAS_CPU_MIPS32_R2 @@ -131,7 +134,6 @@ config BCM63XX select IRQ_CPU select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_BMIPS4350 if !BCM63XX_CPU_6338 && !BCM63XX_CPU_6345 && !BCM63XX_CPU_6348 - select NR_CPUS_DEFAULT_2 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN select SYS_HAS_EARLY_PRINTK @@ -147,6 +149,7 @@ config MIPS_COBALT select CSRC_R4K select CEVT_GT641XX select DMA_NONCOHERENT + select EARLY_PRINTK_8250 if EARLY_PRINTK select HW_HAS_PCI select I8253 select I8259 @@ -413,23 +416,6 @@ config PMC_MSP of integrated peripherals, interfaces and DSPs in addition to a variety of MIPS cores. -config POWERTV - bool "Cisco PowerTV" - select BOOT_ELF32 - select CEVT_R4K - select CPU_MIPSR2_IRQ_VI - select CPU_MIPSR2_IRQ_EI - select CSRC_POWERTV - select DMA_NONCOHERENT - select HW_HAS_PCI - select SYS_HAS_CPU_MIPS32_R2 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_HIGHMEM - select USB_OHCI_LITTLE_ENDIAN - help - This enables support for the Cisco PowerTV Platform. - config RALINK bool "Ralink based machines" select CEVT_R4K @@ -445,6 +431,8 @@ config RALINK select SYS_HAS_EARLY_PRINTK select HAVE_MACH_CLKDEV select CLKDEV_LOOKUP + select ARCH_HAS_RESET_CONTROLLER + select RESET_CONTROLLER config SGI_IP22 bool "SGI IP22 (Indy/Indigo2)" @@ -609,7 +597,6 @@ config SIBYTE_SWARM select BOOT_ELF32 select DMA_COHERENT select HAVE_PATA_PLATFORM - select NR_CPUS_DEFAULT_2 select SIBYTE_SB1250 select SWAP_IO_SPACE select SYS_HAS_CPU_SB1 @@ -623,7 +610,6 @@ config SIBYTE_LITTLESUR select BOOT_ELF32 select DMA_COHERENT select HAVE_PATA_PLATFORM - select NR_CPUS_DEFAULT_2 select SIBYTE_SB1250 select SWAP_IO_SPACE select SYS_HAS_CPU_SB1 @@ -635,7 +621,6 @@ config SIBYTE_SENTOSA bool "Sibyte BCM91250E-Sentosa" select BOOT_ELF32 select DMA_COHERENT - select NR_CPUS_DEFAULT_2 select SIBYTE_SB1250 select SWAP_IO_SPACE select SYS_HAS_CPU_SB1 @@ -727,11 +712,11 @@ config CAVIUM_OCTEON_SOC select SYS_HAS_CPU_CAVIUM_OCTEON select SWAP_IO_SPACE select HW_HAS_PCI - select ARCH_SUPPORTS_MSI select ZONE_DMA32 select USB_ARCH_HAS_OHCI select USB_ARCH_HAS_EHCI select HOLES_IN_ZONE + select ARCH_REQUIRE_GPIOLIB help This option supports all of the Octeon reference boards from Cavium Networks. It builds a kernel that dynamically determines the Octeon @@ -763,7 +748,6 @@ config NLM_XLR_BOARD select CEVT_R4K select CSRC_R4K select IRQ_CPU - select ARCH_SUPPORTS_MSI select ZONE_DMA32 if 64BIT select SYNC_R4K select SYS_HAS_EARLY_PRINTK @@ -814,7 +798,6 @@ source "arch/mips/jz4740/Kconfig" source "arch/mips/lantiq/Kconfig" source "arch/mips/lasat/Kconfig" source "arch/mips/pmcs-msp71xx/Kconfig" -source "arch/mips/powertv/Kconfig" source "arch/mips/ralink/Kconfig" source "arch/mips/sgi-ip27/Kconfig" source "arch/mips/sibyte/Kconfig" @@ -893,9 +876,6 @@ config CSRC_BCM1480 config CSRC_IOASIC bool -config CSRC_POWERTV - bool - config CSRC_R4K bool @@ -1492,8 +1472,10 @@ config SYS_SUPPORTS_ZBOOT bool select HAVE_KERNEL_GZIP select HAVE_KERNEL_BZIP2 + select HAVE_KERNEL_LZ4 select HAVE_KERNEL_LZMA select HAVE_KERNEL_LZO + select HAVE_KERNEL_XZ config SYS_SUPPORTS_ZBOOT_UART16550 bool @@ -1862,7 +1844,6 @@ config MIPS_MT_SMP select CPU_MIPSR2_IRQ_VI select CPU_MIPSR2_IRQ_EI select MIPS_MT - select NR_CPUS_DEFAULT_2 select SMP select SYS_SUPPORTS_SCHED_SMT if SMP select SYS_SUPPORTS_SMP @@ -1981,6 +1962,7 @@ config MIPS_VPE_APSP_API config MIPS_CMP bool "MIPS CMP framework support" depends on SYS_SUPPORTS_MIPS_CMP + select SMP select SYNC_R4K select SYS_SUPPORTS_SMP select SYS_SUPPORTS_SCHED_SMT if SMP @@ -2144,7 +2126,6 @@ source "mm/Kconfig" config SMP bool "Multi-Processing support" depends on SYS_SUPPORTS_SMP - select USE_GENERIC_SMP_HELPERS help This enables support for systems with more than one CPU. If you have a system with only one CPU, like most personal computers, say N. If @@ -2173,12 +2154,6 @@ config SYS_SUPPORTS_MIPS_CMP config SYS_SUPPORTS_SMP bool -config NR_CPUS_DEFAULT_1 - bool - -config NR_CPUS_DEFAULT_2 - bool - config NR_CPUS_DEFAULT_4 bool @@ -2196,10 +2171,8 @@ config NR_CPUS_DEFAULT_64 config NR_CPUS int "Maximum number of CPUs (2-64)" - range 1 64 if NR_CPUS_DEFAULT_1 + range 2 64 depends on SMP - default "1" if NR_CPUS_DEFAULT_1 - default "2" if NR_CPUS_DEFAULT_2 default "4" if NR_CPUS_DEFAULT_4 default "8" if NR_CPUS_DEFAULT_8 default "16" if NR_CPUS_DEFAULT_16 diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug index 37871f0de15e..b147e7038ff0 100644 --- a/arch/mips/Kconfig.debug +++ b/arch/mips/Kconfig.debug @@ -20,6 +20,14 @@ config EARLY_PRINTK doesn't cooperate with an X server. You should normally say N here, unless you want to debug such a crash. +config EARLY_PRINTK_8250 + bool "8250/16550 and compatible serial early printk driver" + depends on EARLY_PRINTK + default n + help + If you say Y here, it will be possible to use a 8250/16550 serial + port as the boot console. + config CMDLINE_BOOL bool "Built-in kernel command line" default n diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 37f9ef324f2f..de300b993607 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -194,6 +194,8 @@ include $(srctree)/arch/mips/Kbuild.platforms ifdef CONFIG_PHYSICAL_START load-y = $(CONFIG_PHYSICAL_START) endif +entry-y = 0x$(shell $(NM) vmlinux 2>/dev/null \ + | grep "\bkernel_entry\b" | cut -f1 -d \ ) cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic drivers-$(CONFIG_PCI) += arch/mips/pci/ @@ -225,6 +227,9 @@ KBUILD_CFLAGS += $(cflags-y) KBUILD_CPPFLAGS += -DVMLINUX_LOAD_ADDRESS=$(load-y) KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0) +bootvars-y = VMLINUX_LOAD_ADDRESS=$(load-y) \ + VMLINUX_ENTRY_ADDRESS=$(entry-y) + LDFLAGS += -m $(ld-emul) ifdef CONFIG_CC_STACKPROTECTOR @@ -254,9 +259,25 @@ drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/ # suspend and hibernation support drivers-$(CONFIG_PM) += arch/mips/power/ +# boot image targets (arch/mips/boot/) +boot-y := vmlinux.bin +boot-y += vmlinux.ecoff +boot-y += vmlinux.srec +ifeq ($(shell expr $(load-y) \< 0xffffffff80000000 2> /dev/null), 0) +boot-y += uImage +boot-y += uImage.gz +endif + +# compressed boot image targets (arch/mips/boot/compressed/) +bootz-y := vmlinuz +bootz-y += vmlinuz.bin +bootz-y += vmlinuz.ecoff +bootz-y += vmlinuz.srec + ifdef CONFIG_LASAT rom.bin rom.sw: vmlinux - $(Q)$(MAKE) $(build)=arch/mips/lasat/image $@ + $(Q)$(MAKE) $(build)=arch/mips/lasat/image \ + $(bootvars-y) $@ endif # @@ -264,29 +285,37 @@ endif # Other need ECOFF, so we build a 32-bit ELF binary for them which we then # convert to ECOFF using elf2ecoff. # +quiet_cmd_32 = OBJCOPY $@ + cmd_32 = $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@ vmlinux.32: vmlinux - $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@ - - -#obj-$(CONFIG_KPROBES) += kprobes.o + $(call cmd,32) # # The 64-bit ELF tools are pretty broken so at this time we generate 64-bit # ELF files from 32-bit files by conversion. # +quiet_cmd_64 = OBJCOPY $@ + cmd_64 = $(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@ vmlinux.64: vmlinux - $(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@ + $(call cmd,64) all: $(all-y) # boot -vmlinux.bin vmlinux.ecoff vmlinux.srec: $(vmlinux-32) FORCE - $(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) arch/mips/boot/$@ +$(boot-y): $(vmlinux-32) FORCE + $(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) \ + $(bootvars-y) arch/mips/boot/$@ +ifdef CONFIG_SYS_SUPPORTS_ZBOOT # boot/compressed -vmlinuz vmlinuz.bin vmlinuz.ecoff vmlinuz.srec: $(vmlinux-32) FORCE +$(bootz-y): $(vmlinux-32) FORCE $(Q)$(MAKE) $(build)=arch/mips/boot/compressed \ - VMLINUX_LOAD_ADDRESS=$(load-y) 32bit-bfd=$(32bit-bfd) $@ + $(bootvars-y) 32bit-bfd=$(32bit-bfd) $@ +else +vmlinuz: FORCE + @echo ' CONFIG_SYS_SUPPORTS_ZBOOT is not enabled' + /bin/false +endif CLEAN_FILES += vmlinux.32 vmlinux.64 @@ -323,6 +352,8 @@ define archhelp echo ' vmlinuz.ecoff - ECOFF zboot image' echo ' vmlinuz.bin - Raw binary zboot image' echo ' vmlinuz.srec - SREC zboot image' + echo ' uImage - U-Boot image' + echo ' uImage.gz - U-Boot image (gzip)' echo echo ' These will be default as appropriate for a configured platform.' endef diff --git a/arch/mips/alchemy/board-mtx1.c b/arch/mips/alchemy/board-mtx1.c index 4a9baa9f6330..9969dbab19e3 100644 --- a/arch/mips/alchemy/board-mtx1.c +++ b/arch/mips/alchemy/board-mtx1.c @@ -276,7 +276,7 @@ static struct platform_device mtx1_pci_host = { .resource = alchemy_pci_host_res, }; -static struct __initdata platform_device * mtx1_devs[] = { +static struct platform_device *mtx1_devs[] __initdata = { &mtx1_pci_host, &mtx1_gpio_leds, &mtx1_wdt, diff --git a/arch/mips/alchemy/common/usb.c b/arch/mips/alchemy/common/usb.c index fcc695626117..2adc7edda49c 100644 --- a/arch/mips/alchemy/common/usb.c +++ b/arch/mips/alchemy/common/usb.c @@ -14,6 +14,7 @@ #include <linux/module.h> #include <linux/spinlock.h> #include <linux/syscore_ops.h> +#include <asm/cpu.h> #include <asm/mach-au1x00/au1000.h> /* control register offsets */ @@ -358,7 +359,7 @@ static inline int au1200_coherency_bug(void) { #if defined(CONFIG_DMA_COHERENT) /* Au1200 AB USB does not support coherent memory */ - if (!(read_c0_prid() & 0xff)) { + if (!(read_c0_prid() & PRID_REV_MASK)) { printk(KERN_INFO "Au1200 USB: this is chip revision AB !!\n"); printk(KERN_INFO "Au1200 USB: update your board or re-configure" " the kernel\n"); diff --git a/arch/mips/alchemy/devboards/db1235.c b/arch/mips/alchemy/devboards/db1235.c index c76a90f78664..bac19dc43d1d 100644 --- a/arch/mips/alchemy/devboards/db1235.c +++ b/arch/mips/alchemy/devboards/db1235.c @@ -59,7 +59,7 @@ void __init board_setup(void) ret = -ENODEV; } if (ret) - panic("cannot initialize board support\n"); + panic("cannot initialize board support"); } int __init db1235_arch_init(void) diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c index 765ef30e3e1c..26479f437675 100644 --- a/arch/mips/ath79/clock.c +++ b/arch/mips/ath79/clock.c @@ -16,6 +16,7 @@ #include <linux/init.h> #include <linux/err.h> #include <linux/clk.h> +#include <linux/clkdev.h> #include <asm/div64.h> @@ -31,92 +32,132 @@ struct clk { unsigned long rate; }; -static struct clk ath79_ref_clk; -static struct clk ath79_cpu_clk; -static struct clk ath79_ddr_clk; -static struct clk ath79_ahb_clk; -static struct clk ath79_wdt_clk; -static struct clk ath79_uart_clk; +static void __init ath79_add_sys_clkdev(const char *id, unsigned long rate) +{ + struct clk *clk; + int err; + + clk = kzalloc(sizeof(*clk), GFP_KERNEL); + if (!clk) + panic("failed to allocate %s clock structure", id); + + clk->rate = rate; + + err = clk_register_clkdev(clk, id, NULL); + if (err) + panic("unable to register %s clock device", id); +} static void __init ar71xx_clocks_init(void) { + unsigned long ref_rate; + unsigned long cpu_rate; + unsigned long ddr_rate; + unsigned long ahb_rate; u32 pll; u32 freq; u32 div; - ath79_ref_clk.rate = AR71XX_BASE_FREQ; + ref_rate = AR71XX_BASE_FREQ; pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; - freq = div * ath79_ref_clk.rate; + freq = div * ref_rate; div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; - ath79_cpu_clk.rate = freq / div; + cpu_rate = freq / div; div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; - ath79_ddr_clk.rate = freq / div; + ddr_rate = freq / div; div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; - ath79_ahb_clk.rate = ath79_cpu_clk.rate / div; + ahb_rate = cpu_rate / div; + + ath79_add_sys_clkdev("ref", ref_rate); + ath79_add_sys_clkdev("cpu", cpu_rate); + ath79_add_sys_clkdev("ddr", ddr_rate); + ath79_add_sys_clkdev("ahb", ahb_rate); - ath79_wdt_clk.rate = ath79_ahb_clk.rate; - ath79_uart_clk.rate = ath79_ahb_clk.rate; + clk_add_alias("wdt", NULL, "ahb", NULL); + clk_add_alias("uart", NULL, "ahb", NULL); } static void __init ar724x_clocks_init(void) { + unsigned long ref_rate; + unsigned long cpu_rate; + unsigned long ddr_rate; + unsigned long ahb_rate; u32 pll; u32 freq; u32 div; - ath79_ref_clk.rate = AR724X_BASE_FREQ; + ref_rate = AR724X_BASE_FREQ; pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG); div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); - freq = div * ath79_ref_clk.rate; + freq = div * ref_rate; div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); freq *= div; - ath79_cpu_clk.rate = freq; + cpu_rate = freq; div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; - ath79_ddr_clk.rate = freq / div; + ddr_rate = freq / div; div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; - ath79_ahb_clk.rate = ath79_cpu_clk.rate / div; + ahb_rate = cpu_rate / div; + + ath79_add_sys_clkdev("ref", ref_rate); + ath79_add_sys_clkdev("cpu", cpu_rate); + ath79_add_sys_clkdev("ddr", ddr_rate); + ath79_add_sys_clkdev("ahb", ahb_rate); - ath79_wdt_clk.rate = ath79_ahb_clk.rate; - ath79_uart_clk.rate = ath79_ahb_clk.rate; + clk_add_alias("wdt", NULL, "ahb", NULL); + clk_add_alias("uart", NULL, "ahb", NULL); } static void __init ar913x_clocks_init(void) { + unsigned long ref_rate; + unsigned long cpu_rate; + unsigned long ddr_rate; + unsigned long ahb_rate; u32 pll; u32 freq; u32 div; - ath79_ref_clk.rate = AR913X_BASE_FREQ; + ref_rate = AR913X_BASE_FREQ; pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG); div = ((pll >> AR913X_PLL_DIV_SHIFT) & AR913X_PLL_DIV_MASK); - freq = div * ath79_ref_clk.rate; + freq = div * ref_rate; - ath79_cpu_clk.rate = freq; + cpu_rate = freq; div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1; - ath79_ddr_clk.rate = freq / div; + ddr_rate = freq / div; div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2; - ath79_ahb_clk.rate = ath79_cpu_clk.rate / div; + ahb_rate = cpu_rate / div; - ath79_wdt_clk.rate = ath79_ahb_clk.rate; - ath79_uart_clk.rate = ath79_ahb_clk.rate; + ath79_add_sys_clkdev("ref", ref_rate); + ath79_add_sys_clkdev("cpu", cpu_rate); + ath79_add_sys_clkdev("ddr", ddr_rate); + ath79_add_sys_clkdev("ahb", ahb_rate); + + clk_add_alias("wdt", NULL, "ahb", NULL); + clk_add_alias("uart", NULL, "ahb", NULL); } static void __init ar933x_clocks_init(void) { + unsigned long ref_rate; + unsigned long cpu_rate; + unsigned long ddr_rate; + unsigned long ahb_rate; u32 clock_ctrl; u32 cpu_config; u32 freq; @@ -124,21 +165,21 @@ static void __init ar933x_clocks_init(void) t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); if (t & AR933X_BOOTSTRAP_REF_CLK_40) - ath79_ref_clk.rate = (40 * 1000 * 1000); + ref_rate = (40 * 1000 * 1000); else - ath79_ref_clk.rate = (25 * 1000 * 1000); + ref_rate = (25 * 1000 * 1000); clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG); if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) { - ath79_cpu_clk.rate = ath79_ref_clk.rate; - ath79_ahb_clk.rate = ath79_ref_clk.rate; - ath79_ddr_clk.rate = ath79_ref_clk.rate; + cpu_rate = ref_rate; + ahb_rate = ref_rate; + ddr_rate = ref_rate; } else { cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG); t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) & AR933X_PLL_CPU_CONFIG_REFDIV_MASK; - freq = ath79_ref_clk.rate / t; + freq = ref_rate / t; t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) & AR933X_PLL_CPU_CONFIG_NINT_MASK; @@ -153,19 +194,24 @@ static void __init ar933x_clocks_init(void) t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) & AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1; - ath79_cpu_clk.rate = freq / t; + cpu_rate = freq / t; t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) & AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1; - ath79_ddr_clk.rate = freq / t; + ddr_rate = freq / t; t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) & AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1; - ath79_ahb_clk.rate = freq / t; + ahb_rate = freq / t; } - ath79_wdt_clk.rate = ath79_ref_clk.rate; - ath79_uart_clk.rate = ath79_ref_clk.rate; + ath79_add_sys_clkdev("ref", ref_rate); + ath79_add_sys_clkdev("cpu", cpu_rate); + ath79_add_sys_clkdev("ddr", ddr_rate); + ath79_add_sys_clkdev("ahb", ahb_rate); + + clk_add_alias("wdt", NULL, "ahb", NULL); + clk_add_alias("uart", NULL, "ref", NULL); } static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, @@ -174,12 +220,12 @@ static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, u64 t; u32 ret; - t = ath79_ref_clk.rate; + t = ref; t *= nint; do_div(t, ref_div); ret = t; - t = ath79_ref_clk.rate; + t = ref; t *= nfrac; do_div(t, ref_div * frac); ret += t; @@ -190,6 +236,10 @@ static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, static void __init ar934x_clocks_init(void) { + unsigned long ref_rate; + unsigned long cpu_rate; + unsigned long ddr_rate; + unsigned long ahb_rate; u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; u32 cpu_pll, ddr_pll; u32 bootstrap; @@ -199,9 +249,9 @@ static void __init ar934x_clocks_init(void) bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40) - ath79_ref_clk.rate = 40 * 1000 * 1000; + ref_rate = 40 * 1000 * 1000; else - ath79_ref_clk.rate = 25 * 1000 * 1000; + ref_rate = 25 * 1000 * 1000; pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG); if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { @@ -227,7 +277,7 @@ static void __init ar934x_clocks_init(void) frac = 1 << 6; } - cpu_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint, + cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint, nfrac, frac, out_div); pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG); @@ -254,7 +304,7 @@ static void __init ar934x_clocks_init(void) frac = 1 << 10; } - ddr_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint, + ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint, nfrac, frac, out_div); clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); @@ -263,49 +313,58 @@ static void __init ar934x_clocks_init(void) AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK; if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS) - ath79_cpu_clk.rate = ath79_ref_clk.rate; + cpu_rate = ref_rate; else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL) - ath79_cpu_clk.rate = cpu_pll / (postdiv + 1); + cpu_rate = cpu_pll / (postdiv + 1); else - ath79_cpu_clk.rate = ddr_pll / (postdiv + 1); + cpu_rate = ddr_pll / (postdiv + 1); postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK; if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS) - ath79_ddr_clk.rate = ath79_ref_clk.rate; + ddr_rate = ref_rate; else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL) - ath79_ddr_clk.rate = ddr_pll / (postdiv + 1); + ddr_rate = ddr_pll / (postdiv + 1); else - ath79_ddr_clk.rate = cpu_pll / (postdiv + 1); + ddr_rate = cpu_pll / (postdiv + 1); postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK; if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS) - ath79_ahb_clk.rate = ath79_ref_clk.rate; + ahb_rate = ref_rate; else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL) - ath79_ahb_clk.rate = ddr_pll / (postdiv + 1); + ahb_rate = ddr_pll / (postdiv + 1); else - ath79_ahb_clk.rate = cpu_pll / (postdiv + 1); + ahb_rate = cpu_pll / (postdiv + 1); + + ath79_add_sys_clkdev("ref", ref_rate); + ath79_add_sys_clkdev("cpu", cpu_rate); + ath79_add_sys_clkdev("ddr", ddr_rate); + ath79_add_sys_clkdev("ahb", ahb_rate); - ath79_wdt_clk.rate = ath79_ref_clk.rate; - ath79_uart_clk.rate = ath79_ref_clk.rate; + clk_add_alias("wdt", NULL, "ref", NULL); + clk_add_alias("uart", NULL, "ref", NULL); iounmap(dpll_base); } static void __init qca955x_clocks_init(void) { + unsigned long ref_rate; + unsigned long cpu_rate; + unsigned long ddr_rate; + unsigned long ahb_rate; u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; u32 cpu_pll, ddr_pll; u32 bootstrap; bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP); if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40) - ath79_ref_clk.rate = 40 * 1000 * 1000; + ref_rate = 40 * 1000 * 1000; else - ath79_ref_clk.rate = 25 * 1000 * 1000; + ref_rate = 25 * 1000 * 1000; pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG); out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & @@ -317,8 +376,8 @@ static void __init qca955x_clocks_init(void) frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) & QCA955X_PLL_CPU_CONFIG_NFRAC_MASK; - cpu_pll = nint * ath79_ref_clk.rate / ref_div; - cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6)); + cpu_pll = nint * ref_rate / ref_div; + cpu_pll += frac * ref_rate / (ref_div * (1 << 6)); cpu_pll /= (1 << out_div); pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG); @@ -331,8 +390,8 @@ static void __init qca955x_clocks_init(void) frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) & QCA955X_PLL_DDR_CONFIG_NFRAC_MASK; - ddr_pll = nint * ath79_ref_clk.rate / ref_div; - ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10)); + ddr_pll = nint * ref_rate / ref_div; + ddr_pll += frac * ref_rate / (ref_div * (1 << 10)); ddr_pll /= (1 << out_div); clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG); @@ -341,34 +400,39 @@ static void __init qca955x_clocks_init(void) QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS) - ath79_cpu_clk.rate = ath79_ref_clk.rate; + cpu_rate = ref_rate; else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) - ath79_cpu_clk.rate = ddr_pll / (postdiv + 1); + cpu_rate = ddr_pll / (postdiv + 1); else - ath79_cpu_clk.rate = cpu_pll / (postdiv + 1); + cpu_rate = cpu_pll / (postdiv + 1); postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS) - ath79_ddr_clk.rate = ath79_ref_clk.rate; + ddr_rate = ref_rate; else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) - ath79_ddr_clk.rate = cpu_pll / (postdiv + 1); + ddr_rate = cpu_pll / (postdiv + 1); else - ath79_ddr_clk.rate = ddr_pll / (postdiv + 1); + ddr_rate = ddr_pll / (postdiv + 1); postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS) - ath79_ahb_clk.rate = ath79_ref_clk.rate; + ahb_rate = ref_rate; else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) - ath79_ahb_clk.rate = ddr_pll / (postdiv + 1); + ahb_rate = ddr_pll / (postdiv + 1); else - ath79_ahb_clk.rate = cpu_pll / (postdiv + 1); + ahb_rate = cpu_pll / (postdiv + 1); - ath79_wdt_clk.rate = ath79_ref_clk.rate; - ath79_uart_clk.rate = ath79_ref_clk.rate; + ath79_add_sys_clkdev("ref", ref_rate); + ath79_add_sys_clkdev("cpu", cpu_rate); + ath79_add_sys_clkdev("ddr", ddr_rate); + ath79_add_sys_clkdev("ahb", ahb_rate); + + clk_add_alias("wdt", NULL, "ref", NULL); + clk_add_alias("uart", NULL, "ref", NULL); } void __init ath79_clocks_init(void) @@ -387,46 +451,27 @@ void __init ath79_clocks_init(void) qca955x_clocks_init(); else BUG(); - - pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, " - "Ref:%lu.%03luMHz", - ath79_cpu_clk.rate / 1000000, - (ath79_cpu_clk.rate / 1000) % 1000, - ath79_ddr_clk.rate / 1000000, - (ath79_ddr_clk.rate / 1000) % 1000, - ath79_ahb_clk.rate / 1000000, - (ath79_ahb_clk.rate / 1000) % 1000, - ath79_ref_clk.rate / 1000000, - (ath79_ref_clk.rate / 1000) % 1000); } -/* - * Linux clock API - */ -struct clk *clk_get(struct device *dev, const char *id) +unsigned long __init +ath79_get_sys_clk_rate(const char *id) { - if (!strcmp(id, "ref")) - return &ath79_ref_clk; - - if (!strcmp(id, "cpu")) - return &ath79_cpu_clk; - - if (!strcmp(id, "ddr")) - return &ath79_ddr_clk; - - if (!strcmp(id, "ahb")) - return &ath79_ahb_clk; + struct clk *clk; + unsigned long rate; - if (!strcmp(id, "wdt")) - return &ath79_wdt_clk; + clk = clk_get(NULL, id); + if (IS_ERR(clk)) + panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk)); - if (!strcmp(id, "uart")) - return &ath79_uart_clk; + rate = clk_get_rate(clk); + clk_put(clk); - return ERR_PTR(-ENOENT); + return rate; } -EXPORT_SYMBOL(clk_get); +/* + * Linux clock API + */ int clk_enable(struct clk *clk) { return 0; @@ -443,8 +488,3 @@ unsigned long clk_get_rate(struct clk *clk) return clk->rate; } EXPORT_SYMBOL(clk_get_rate); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); diff --git a/arch/mips/ath79/common.h b/arch/mips/ath79/common.h index 561906c2345e..648d2dafbc56 100644 --- a/arch/mips/ath79/common.h +++ b/arch/mips/ath79/common.h @@ -21,6 +21,8 @@ #define ATH79_MEM_SIZE_MAX (128 * 1024 * 1024) void ath79_clocks_init(void); +unsigned long ath79_get_sys_clk_rate(const char *id); + void ath79_ddr_wb_flush(unsigned int reg); void ath79_gpio_function_enable(u32 mask); diff --git a/arch/mips/ath79/dev-common.c b/arch/mips/ath79/dev-common.c index a3a2741d0688..516225d207ee 100644 --- a/arch/mips/ath79/dev-common.c +++ b/arch/mips/ath79/dev-common.c @@ -20,7 +20,6 @@ #include <asm/mach-ath79/ath79.h> #include <asm/mach-ath79/ar71xx_regs.h> -#include <asm/mach-ath79/ar933x_uart_platform.h> #include "common.h" #include "dev-common.h" @@ -68,34 +67,27 @@ static struct resource ar933x_uart_resources[] = { }, }; -static struct ar933x_uart_platform_data ar933x_uart_data; static struct platform_device ar933x_uart_device = { .name = "ar933x-uart", .id = -1, .resource = ar933x_uart_resources, .num_resources = ARRAY_SIZE(ar933x_uart_resources), - .dev = { - .platform_data = &ar933x_uart_data, - }, }; void __init ath79_register_uart(void) { - struct clk *clk; + unsigned long uart_clk_rate; - clk = clk_get(NULL, "uart"); - if (IS_ERR(clk)) - panic("unable to get UART clock, err=%ld", PTR_ERR(clk)); + uart_clk_rate = ath79_get_sys_clk_rate("uart"); if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x() || soc_is_ar934x() || soc_is_qca955x()) { - ath79_uart_data[0].uartclk = clk_get_rate(clk); + ath79_uart_data[0].uartclk = uart_clk_rate; platform_device_register(&ath79_uart_device); } else if (soc_is_ar933x()) { - ar933x_uart_data.uartclk = clk_get_rate(clk); platform_device_register(&ar933x_uart_device); } else { BUG(); diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index 80f4ecd42b0d..64807a4809d0 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c @@ -200,7 +200,6 @@ void __init plat_mem_setup(void) ath79_detect_sys_type(); detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX); - ath79_clocks_init(); _machine_restart = ath79_restart; _machine_halt = ath79_halt; @@ -209,13 +208,25 @@ void __init plat_mem_setup(void) void __init plat_time_init(void) { - struct clk *clk; + unsigned long cpu_clk_rate; + unsigned long ahb_clk_rate; + unsigned long ddr_clk_rate; + unsigned long ref_clk_rate; + + ath79_clocks_init(); + + cpu_clk_rate = ath79_get_sys_clk_rate("cpu"); + ahb_clk_rate = ath79_get_sys_clk_rate("ahb"); + ddr_clk_rate = ath79_get_sys_clk_rate("ddr"); + ref_clk_rate = ath79_get_sys_clk_rate("ref"); - clk = clk_get(NULL, "cpu"); - if (IS_ERR(clk)) - panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); + pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, Ref:%lu.%03luMHz", + cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000, + ddr_clk_rate / 1000000, (ddr_clk_rate / 1000) % 1000, + ahb_clk_rate / 1000000, (ahb_clk_rate / 1000) % 1000, + ref_clk_rate / 1000000, (ref_clk_rate / 1000) % 1000); - mips_hpt_frequency = clk_get_rate(clk) / 2; + mips_hpt_frequency = cpu_clk_rate / 2; } static int __init ath79_setup(void) diff --git a/arch/mips/bcm47xx/Makefile b/arch/mips/bcm47xx/Makefile index f3bf6d5bfb9d..c52daf9b05c6 100644 --- a/arch/mips/bcm47xx/Makefile +++ b/arch/mips/bcm47xx/Makefile @@ -4,4 +4,5 @@ # obj-y += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o +obj-y += board.o obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o diff --git a/arch/mips/bcm47xx/board.c b/arch/mips/bcm47xx/board.c new file mode 100644 index 000000000000..f3f6bfe68a2a --- /dev/null +++ b/arch/mips/bcm47xx/board.c @@ -0,0 +1,309 @@ +#include <linux/export.h> +#include <linux/string.h> +#include <bcm47xx_board.h> +#include <bcm47xx_nvram.h> + +struct bcm47xx_board_type { + const enum bcm47xx_board board; + const char *name; +}; + +struct bcm47xx_board_type_list1 { + struct bcm47xx_board_type board; + const char *value1; +}; + +struct bcm47xx_board_type_list2 { + struct bcm47xx_board_type board; + const char *value1; + const char *value2; +}; + +struct bcm47xx_board_type_list3 { + struct bcm47xx_board_type board; + const char *value1; + const char *value2; + const char *value3; +}; + +struct bcm47xx_board_store { + enum bcm47xx_board board; + char name[BCM47XX_BOARD_MAX_NAME]; +}; + +/* model_name */ +static const +struct bcm47xx_board_type_list1 bcm47xx_board_list_model_name[] __initconst = { + {{BCM47XX_BOARD_DLINK_DIR130, "D-Link DIR-130"}, "DIR-130"}, + {{BCM47XX_BOARD_DLINK_DIR330, "D-Link DIR-330"}, "DIR-330"}, + { {0}, 0}, +}; + +/* model_no */ +static const +struct bcm47xx_board_type_list1 bcm47xx_board_list_model_no[] __initconst = { + {{BCM47XX_BOARD_ASUS_WL700GE, "Asus WL700"}, "WL700"}, + { {0}, 0}, +}; + +/* machine_name */ +static const +struct bcm47xx_board_type_list1 bcm47xx_board_list_machine_name[] __initconst = { + {{BCM47XX_BOARD_LINKSYS_WRTSL54GS, "Linksys WRTSL54GS"}, "WRTSL54GS"}, + { {0}, 0}, +}; + +/* hardware_version */ +static const +struct bcm47xx_board_type_list1 bcm47xx_board_list_hardware_version[] __initconst = { + {{BCM47XX_BOARD_ASUS_RTN16, "Asus RT-N16"}, "RT-N16-"}, + {{BCM47XX_BOARD_ASUS_WL320GE, "Asus WL320GE"}, "WL320G-"}, + {{BCM47XX_BOARD_ASUS_WL330GE, "Asus WL330GE"}, "WL330GE-"}, + {{BCM47XX_BOARD_ASUS_WL500GD, "Asus WL500GD"}, "WL500gd-"}, + {{BCM47XX_BOARD_ASUS_WL500GPV1, "Asus WL500GP V1"}, "WL500gp-"}, + {{BCM47XX_BOARD_ASUS_WL500GPV2, "Asus WL500GP V2"}, "WL500GPV2-"}, + {{BCM47XX_BOARD_ASUS_WL500W, "Asus WL500W"}, "WL500gW-"}, + {{BCM47XX_BOARD_ASUS_WL520GC, "Asus WL520GC"}, "WL520GC-"}, + {{BCM47XX_BOARD_ASUS_WL520GU, "Asus WL520GU"}, "WL520GU-"}, + {{BCM47XX_BOARD_BELKIN_F7D4301, "Belkin F7D4301"}, "F7D4301"}, + { {0}, 0}, +}; + +/* productid */ +static const +struct bcm47xx_board_type_list1 bcm47xx_board_list_productid[] __initconst = { + {{BCM47XX_BOARD_ASUS_RTAC66U, "Asus RT-AC66U"}, "RT-AC66U"}, + {{BCM47XX_BOARD_ASUS_RTN10, "Asus RT-N10"}, "RT-N10"}, + {{BCM47XX_BOARD_ASUS_RTN10D, "Asus RT-N10D"}, "RT-N10D"}, + {{BCM47XX_BOARD_ASUS_RTN10U, "Asus RT-N10U"}, "RT-N10U"}, + {{BCM47XX_BOARD_ASUS_RTN12, "Asus RT-N12"}, "RT-N12"}, + {{BCM47XX_BOARD_ASUS_RTN12B1, "Asus RT-N12B1"}, "RT-N12B1"}, + {{BCM47XX_BOARD_ASUS_RTN12C1, "Asus RT-N12C1"}, "RT-N12C1"}, + {{BCM47XX_BOARD_ASUS_RTN12D1, "Asus RT-N12D1"}, "RT-N12D1"}, + {{BCM47XX_BOARD_ASUS_RTN12HP, "Asus RT-N12HP"}, "RT-N12HP"}, + {{BCM47XX_BOARD_ASUS_RTN15U, "Asus RT-N15U"}, "RT-N15U"}, + {{BCM47XX_BOARD_ASUS_RTN16, "Asus RT-N16"}, "RT-N16"}, + {{BCM47XX_BOARD_ASUS_RTN53, "Asus RT-N53"}, "RT-N53"}, + {{BCM47XX_BOARD_ASUS_RTN66U, "Asus RT-N66U"}, "RT-N66U"}, + {{BCM47XX_BOARD_ASUS_WL300G, "Asus WL300G"}, "WL300g"}, + {{BCM47XX_BOARD_ASUS_WLHDD, "Asus WLHDD"}, "WLHDD"}, + { {0}, 0}, +}; + +/* ModelId */ +static const +struct bcm47xx_board_type_list1 bcm47xx_board_list_ModelId[] __initconst = { + {{BCM47XX_BOARD_DELL_TM2300, "Dell WX-5565"}, "WX-5565"}, + {{BCM47XX_BOARD_MOTOROLA_WE800G, "Motorola WE800G"}, "WE800G"}, + {{BCM47XX_BOARD_MOTOROLA_WR850GP, "Motorola WR850GP"}, "WR850GP"}, + {{BCM47XX_BOARD_MOTOROLA_WR850GV2V3, "Motorola WR850G"}, "WR850G"}, + { {0}, 0}, +}; + +/* melco_id or buf1falo_id */ +static const +struct bcm47xx_board_type_list1 bcm47xx_board_list_melco_id[] __initconst = { + {{BCM47XX_BOARD_BUFFALO_WBR2_G54, "Buffalo WBR2-G54"}, "29bb0332"}, + {{BCM47XX_BOARD_BUFFALO_WHR2_A54G54, "Buffalo WHR2-A54G54"}, "290441dd"}, + {{BCM47XX_BOARD_BUFFALO_WHR_G125, "Buffalo WHR-G125"}, "32093"}, + {{BCM47XX_BOARD_BUFFALO_WHR_G54S, "Buffalo WHR-G54S"}, "30182"}, + {{BCM47XX_BOARD_BUFFALO_WHR_HP_G54, "Buffalo WHR-HP-G54"}, "30189"}, + {{BCM47XX_BOARD_BUFFALO_WLA2_G54L, "Buffalo WLA2-G54L"}, "29129"}, + {{BCM47XX_BOARD_BUFFALO_WZR_G300N, "Buffalo WZR-G300N"}, "31120"}, + {{BCM47XX_BOARD_BUFFALO_WZR_RS_G54, "Buffalo WZR-RS-G54"}, "30083"}, + {{BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP, "Buffalo WZR-RS-G54HP"}, "30103"}, + { {0}, 0}, +}; + +/* boot_hw_model, boot_hw_ver */ +static const +struct bcm47xx_board_type_list2 bcm47xx_board_list_boot_hw[] __initconst = { + /* like WRT160N v3.0 */ + {{BCM47XX_BOARD_CISCO_M10V1, "Cisco M10"}, "M10", "1.0"}, + /* like WRT310N v2.0 */ + {{BCM47XX_BOARD_CISCO_M20V1, "Cisco M20"}, "M20", "1.0"}, + {{BCM47XX_BOARD_LINKSYS_E900V1, "Linksys E900 V1"}, "E900", "1.0"}, + /* like WRT160N v3.0 */ + {{BCM47XX_BOARD_LINKSYS_E1000V1, "Linksys E1000 V1"}, "E100", "1.0"}, + {{BCM47XX_BOARD_LINKSYS_E1000V2, "Linksys E1000 V2"}, "E1000", "2.0"}, + {{BCM47XX_BOARD_LINKSYS_E1000V21, "Linksys E1000 V2.1"}, "E1000", "2.1"}, + {{BCM47XX_BOARD_LINKSYS_E1200V2, "Linksys E1200 V2"}, "E1200", "2.0"}, + {{BCM47XX_BOARD_LINKSYS_E2000V1, "Linksys E2000 V1"}, "Linksys E2000", "1.0"}, + /* like WRT610N v2.0 */ + {{BCM47XX_BOARD_LINKSYS_E3000V1, "Linksys E3000 V1"}, "E300", "1.0"}, + {{BCM47XX_BOARD_LINKSYS_E3200V1, "Linksys E3200 V1"}, "E3200", "1.0"}, + {{BCM47XX_BOARD_LINKSYS_E4200V1, "Linksys E4200 V1"}, "E4200", "1.0"}, + {{BCM47XX_BOARD_LINKSYS_WRT150NV11, "Linksys WRT150N V1.1"}, "WRT150N", "1.1"}, + {{BCM47XX_BOARD_LINKSYS_WRT150NV1, "Linksys WRT150N V1"}, "WRT150N", "1"}, + {{BCM47XX_BOARD_LINKSYS_WRT160NV1, "Linksys WRT160N V1"}, "WRT160N", "1.0"}, + {{BCM47XX_BOARD_LINKSYS_WRT160NV3, "Linksys WRT160N V3"}, "WRT160N", "3.0"}, + {{BCM47XX_BOARD_LINKSYS_WRT300NV11, "Linksys WRT300N V1.1"}, "WRT300N", "1.1"}, + {{BCM47XX_BOARD_LINKSYS_WRT310NV1, "Linksys WRT310N V1"}, "WRT310N", "1.0"}, + {{BCM47XX_BOARD_LINKSYS_WRT310NV2, "Linksys WRT310N V2"}, "WRT310N", "2.0"}, + {{BCM47XX_BOARD_LINKSYS_WRT54G3GV2, "Linksys WRT54G3GV2-VF"}, "WRT54G3GV2-VF", "1.0"}, + {{BCM47XX_BOARD_LINKSYS_WRT610NV1, "Linksys WRT610N V1"}, "WRT610N", "1.0"}, + {{BCM47XX_BOARD_LINKSYS_WRT610NV2, "Linksys WRT610N V2"}, "WRT610N", "2.0"}, + { {0}, 0}, +}; + +/* board_id */ +static const +struct bcm47xx_board_type_list1 bcm47xx_board_list_board_id[] __initconst = { + {{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNDR3300, "Netgear WNDR3300"}, "U12H093T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNDR3400V1, "Netgear WNDR3400 V1"}, "U12H155T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNDR3400V2, "Netgear WNDR3400 V2"}, "U12H187T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNDR3400VCNA, "Netgear WNDR3400 Vcna"}, "U12H155T01_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNDR3700V3, "Netgear WNDR3700 V3"}, "U12H194T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNDR4000, "Netgear WNDR4000"}, "U12H181T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNDR4500V1, "Netgear WNDR4500 V1"}, "U12H189T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNDR4500V2, "Netgear WNDR4500 V2"}, "U12H224T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNR2000, "Netgear WNR2000"}, "U12H114T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNR3500L, "Netgear WNR3500L"}, "U12H136T99_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNR3500U, "Netgear WNR3500U"}, "U12H136T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNR3500V2, "Netgear WNR3500 V2"}, "U12H127T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNR3500V2VC, "Netgear WNR3500 V2vc"}, "U12H127T70_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNR834BV2, "Netgear WNR834B V2"}, "U12H081T00_NETGEAR"}, + { {0}, 0}, +}; + +/* boardtype, boardnum, boardrev */ +static const +struct bcm47xx_board_type_list3 bcm47xx_board_list_board[] __initconst = { + {{BCM47XX_BOARD_HUAWEI_E970, "Huawei E970"}, "0x048e", "0x5347", "0x11"}, + {{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"}, + {{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"}, + { {0}, 0}, +}; + +static const +struct bcm47xx_board_type bcm47xx_board_unknown[] __initconst = { + {BCM47XX_BOARD_UNKNOWN, "Unknown Board"}, +}; + +static struct bcm47xx_board_store bcm47xx_board = {BCM47XX_BOARD_NO, "Unknown Board"}; + +static __init const struct bcm47xx_board_type *bcm47xx_board_get_nvram(void) +{ + char buf1[30]; + char buf2[30]; + char buf3[30]; + const struct bcm47xx_board_type_list1 *e1; + const struct bcm47xx_board_type_list2 *e2; + const struct bcm47xx_board_type_list3 *e3; + + if (bcm47xx_nvram_getenv("model_name", buf1, sizeof(buf1)) >= 0) { + for (e1 = bcm47xx_board_list_model_name; e1->value1; e1++) { + if (!strcmp(buf1, e1->value1)) + return &e1->board; + } + } + + if (bcm47xx_nvram_getenv("model_no", buf1, sizeof(buf1)) >= 0) { + for (e1 = bcm47xx_board_list_model_no; e1->value1; e1++) { + if (strstarts(buf1, e1->value1)) + return &e1->board; + } + } + + if (bcm47xx_nvram_getenv("machine_name", buf1, sizeof(buf1)) >= 0) { + for (e1 = bcm47xx_board_list_machine_name; e1->value1; e1++) { + if (strstarts(buf1, e1->value1)) + return &e1->board; + } + } + + if (bcm47xx_nvram_getenv("hardware_version", buf1, sizeof(buf1)) >= 0) { + for (e1 = bcm47xx_board_list_hardware_version; e1->value1; e1++) { + if (strstarts(buf1, e1->value1)) + return &e1->board; + } + } + + if (bcm47xx_nvram_getenv("productid", buf1, sizeof(buf1)) >= 0) { + for (e1 = bcm47xx_board_list_productid; e1->value1; e1++) { + if (!strcmp(buf1, e1->value1)) + return &e1->board; + } + } + + if (bcm47xx_nvram_getenv("ModelId", buf1, sizeof(buf1)) >= 0) { + for (e1 = bcm47xx_board_list_ModelId; e1->value1; e1++) { + if (!strcmp(buf1, e1->value1)) + return &e1->board; + } + } + + if (bcm47xx_nvram_getenv("melco_id", buf1, sizeof(buf1)) >= 0 || + bcm47xx_nvram_getenv("buf1falo_id", buf1, sizeof(buf1)) >= 0) { + /* buffalo hardware, check id for specific hardware matches */ + for (e1 = bcm47xx_board_list_melco_id; e1->value1; e1++) { + if (!strcmp(buf1, e1->value1)) + return &e1->board; + } + } + + if (bcm47xx_nvram_getenv("boot_hw_model", buf1, sizeof(buf1)) >= 0 && + bcm47xx_nvram_getenv("boot_hw_ver", buf2, sizeof(buf2)) >= 0) { + for (e2 = bcm47xx_board_list_boot_hw; e2->value1; e2++) { + if (!strcmp(buf1, e2->value1) && + !strcmp(buf2, e2->value2)) + return &e2->board; + } + } + + if (bcm47xx_nvram_getenv("board_id", buf1, sizeof(buf1)) >= 0) { + for (e1 = bcm47xx_board_list_board_id; e1->value1; e1++) { + if (!strcmp(buf1, e1->value1)) + return &e1->board; + } + } + + if (bcm47xx_nvram_getenv("boardtype", buf1, sizeof(buf1)) >= 0 && + bcm47xx_nvram_getenv("boardnum", buf2, sizeof(buf2)) >= 0 && + bcm47xx_nvram_getenv("boardrev", buf3, sizeof(buf3)) >= 0) { + for (e3 = bcm47xx_board_list_board; e3->value1; e3++) { + if (!strcmp(buf1, e3->value1) && + !strcmp(buf2, e3->value2) && + !strcmp(buf3, e3->value3)) + return &e3->board; + } + } + return bcm47xx_board_unknown; +} + +void __init bcm47xx_board_detect(void) +{ + int err; + char buf[10]; + const struct bcm47xx_board_type *board_detected; + + if (bcm47xx_board.board != BCM47XX_BOARD_NO) + return; + + /* check if the nvram is available */ + err = bcm47xx_nvram_getenv("boardtype", buf, sizeof(buf)); + + /* init of nvram failed, probably too early now */ + if (err == -ENXIO) { + return; + } + + board_detected = bcm47xx_board_get_nvram(); + bcm47xx_board.board = board_detected->board; + strlcpy(bcm47xx_board.name, board_detected->name, + BCM47XX_BOARD_MAX_NAME); +} + +enum bcm47xx_board bcm47xx_board_get(void) +{ + return bcm47xx_board.board; +} +EXPORT_SYMBOL(bcm47xx_board_get); + +const char *bcm47xx_board_get_name(void) +{ + return bcm47xx_board.name; +} +EXPORT_SYMBOL(bcm47xx_board_get_name); diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c index cc40b74940f5..b4c585b1c62e 100644 --- a/arch/mips/bcm47xx/nvram.c +++ b/arch/mips/bcm47xx/nvram.c @@ -190,3 +190,23 @@ int bcm47xx_nvram_getenv(char *name, char *val, size_t val_len) return -ENOENT; } EXPORT_SYMBOL(bcm47xx_nvram_getenv); + +int bcm47xx_nvram_gpio_pin(const char *name) +{ + int i, err; + char nvram_var[10]; + char buf[30]; + + for (i = 0; i < 16; i++) { + err = snprintf(nvram_var, sizeof(nvram_var), "gpio%i", i); + if (err <= 0) + continue; + err = bcm47xx_nvram_getenv(nvram_var, buf, sizeof(buf)); + if (err <= 0) + continue; + if (!strcmp(name, buf)) + return i; + } + return -ENOENT; +} +EXPORT_SYMBOL(bcm47xx_nvram_gpio_pin); diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c index 8c155afb1299..5cba318bc1cd 100644 --- a/arch/mips/bcm47xx/prom.c +++ b/arch/mips/bcm47xx/prom.c @@ -32,12 +32,37 @@ #include <asm/bootinfo.h> #include <asm/fw/cfe/cfe_api.h> #include <asm/fw/cfe/cfe_error.h> +#include <bcm47xx.h> +#include <bcm47xx_board.h> static int cfe_cons_handle; +static u16 get_chip_id(void) +{ + switch (bcm47xx_bus_type) { +#ifdef CONFIG_BCM47XX_SSB + case BCM47XX_BUS_TYPE_SSB: + return bcm47xx_bus.ssb.chip_id; +#endif +#ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + return bcm47xx_bus.bcma.bus.chipinfo.id; +#endif + } + return 0; +} + const char *get_system_type(void) { - return "Broadcom BCM47XX"; + static char buf[50]; + u16 chip_id = get_chip_id(); + + snprintf(buf, sizeof(buf), + (chip_id > 0x9999) ? "Broadcom BCM%d (%s)" : + "Broadcom BCM%04X (%s)", + chip_id, bcm47xx_board_get_name()); + + return buf; } void prom_putchar(char c) diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index b2246cd9ca12..1f30571968e7 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -36,6 +36,7 @@ #include <asm/time.h> #include <bcm47xx.h> #include <bcm47xx_nvram.h> +#include <bcm47xx_board.h> union bcm47xx_bus bcm47xx_bus; EXPORT_SYMBOL(bcm47xx_bus); @@ -221,6 +222,7 @@ void __init plat_mem_setup(void) _machine_restart = bcm47xx_machine_restart; _machine_halt = bcm47xx_machine_halt; pm_power_off = bcm47xx_machine_halt; + bcm47xx_board_detect(); } static int __init bcm47xx_register_bus_complete(void) diff --git a/arch/mips/bcm47xx/time.c b/arch/mips/bcm47xx/time.c index 536374dcba78..2c85d9254b5e 100644 --- a/arch/mips/bcm47xx/time.c +++ b/arch/mips/bcm47xx/time.c @@ -27,10 +27,16 @@ #include <linux/ssb/ssb.h> #include <asm/time.h> #include <bcm47xx.h> +#include <bcm47xx_nvram.h> +#include <bcm47xx_board.h> void __init plat_time_init(void) { unsigned long hz = 0; + u16 chip_id = 0; + char buf[10]; + int len; + enum bcm47xx_board board = bcm47xx_board_get(); /* * Use deterministic values for initial counter interrupt @@ -43,15 +49,32 @@ void __init plat_time_init(void) #ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2; + chip_id = bcm47xx_bus.ssb.chip_id; break; #endif #ifdef CONFIG_BCM47XX_BCMA case BCM47XX_BUS_TYPE_BCMA: hz = bcma_cpu_clock(&bcm47xx_bus.bcma.bus.drv_mips) / 2; + chip_id = bcm47xx_bus.bcma.bus.chipinfo.id; break; #endif } + if (chip_id == 0x5354) { + len = bcm47xx_nvram_getenv("clkfreq", buf, sizeof(buf)); + if (len >= 0 && !strncmp(buf, "200", 4)) + hz = 100000000; + } + + switch (board) { + case BCM47XX_BOARD_ASUS_WL520GC: + case BCM47XX_BOARD_ASUS_WL520GU: + hz = 100000000; + break; + default: + break; + } + if (!hz) hz = 100000000; diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c index 7e17374a9ae8..b713cd64b087 100644 --- a/arch/mips/bcm63xx/cpu.c +++ b/arch/mips/bcm63xx/cpu.c @@ -306,14 +306,14 @@ void __init bcm63xx_cpu_init(void) switch (c->cputype) { case CPU_BMIPS3300: - if ((read_c0_prid() & 0xff00) != PRID_IMP_BMIPS3300_ALT) + if ((read_c0_prid() & PRID_IMP_MASK) != PRID_IMP_BMIPS3300_ALT) __cpu_name[cpu] = "Broadcom BCM6338"; /* fall-through */ case CPU_BMIPS32: chipid_reg = BCM_6345_PERF_BASE; break; case CPU_BMIPS4350: - switch ((read_c0_prid() & 0xff)) { + switch ((read_c0_prid() & PRID_REV_MASK)) { case 0x04: chipid_reg = BCM_3368_PERF_BASE; break; diff --git a/arch/mips/bcm63xx/nvram.c b/arch/mips/bcm63xx/nvram.c index e652e578a679..4b50d40f7451 100644 --- a/arch/mips/bcm63xx/nvram.c +++ b/arch/mips/bcm63xx/nvram.c @@ -35,6 +35,8 @@ struct bcm963xx_nvram { u32 checksum_high; }; +#define BCM63XX_DEFAULT_PSI_SIZE 64 + static struct bcm963xx_nvram nvram; static int mac_addr_used; @@ -114,3 +116,12 @@ int bcm63xx_nvram_get_mac_address(u8 *mac) return 0; } EXPORT_SYMBOL(bcm63xx_nvram_get_mac_address); + +int bcm63xx_nvram_get_psi_size(void) +{ + if (nvram.psi_size > 0) + return nvram.psi_size; + + return BCM63XX_DEFAULT_PSI_SIZE; +} +EXPORT_SYMBOL(bcm63xx_nvram_get_psi_size); diff --git a/arch/mips/boot/.gitignore b/arch/mips/boot/.gitignore index f210b09ececc..a73d6e2c4f64 100644 --- a/arch/mips/boot/.gitignore +++ b/arch/mips/boot/.gitignore @@ -4,3 +4,4 @@ vmlinux.* zImage zImage.tmp calc_vmlinuz_load_addr +uImage diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile index 851261e9fdc0..1466c0026093 100644 --- a/arch/mips/boot/Makefile +++ b/arch/mips/boot/Makefile @@ -40,3 +40,18 @@ quiet_cmd_srec = OBJCOPY $@ cmd_srec = $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $@ $(obj)/vmlinux.srec: $(VMLINUX) FORCE $(call if_changed,srec) + +UIMAGE_LOADADDR = $(VMLINUX_LOAD_ADDRESS) +UIMAGE_ENTRYADDR = $(VMLINUX_ENTRY_ADDRESS) + +$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE + $(call if_changed,gzip) + +targets += uImage.gz +$(obj)/uImage.gz: $(obj)/vmlinux.bin.gz FORCE + $(call if_changed,uimage,gzip) + +targets += uImage +$(obj)/uImage: $(obj)/uImage.gz FORCE + @ln -sf $(notdir $<) $@ + @echo ' Image $@ is ready' diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile index bb1dbf4abb9d..ca0c343c9ea5 100644 --- a/arch/mips/boot/compressed/Makefile +++ b/arch/mips/boot/compressed/Makefile @@ -25,7 +25,7 @@ KBUILD_CFLAGS := $(LINUXINCLUDE) $(KBUILD_CFLAGS) -D__KERNEL__ \ KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \ -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \ - -DKERNEL_ENTRY=0x$(shell $(NM) $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | grep " kernel_entry" | cut -f1 -d \ ) + -DKERNEL_ENTRY=$(VMLINUX_ENTRY_ADDRESS) targets := head.o decompress.o dbg.o uart-16550.o uart-alchemy.o @@ -37,6 +37,10 @@ vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY) += $(obj)/uart-alchemy.o endif +ifdef CONFIG_KERNEL_XZ +vmlinuzobjs-y += $(obj)/../../lib/ashldi3.o +endif + targets += vmlinux.bin OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S $(obj)/vmlinux.bin: $(KBUILD_IMAGE) FORCE @@ -44,8 +48,10 @@ $(obj)/vmlinux.bin: $(KBUILD_IMAGE) FORCE tool_$(CONFIG_KERNEL_GZIP) = gzip tool_$(CONFIG_KERNEL_BZIP2) = bzip2 +tool_$(CONFIG_KERNEL_LZ4) = lz4 tool_$(CONFIG_KERNEL_LZMA) = lzma tool_$(CONFIG_KERNEL_LZO) = lzo +tool_$(CONFIG_KERNEL_XZ) = xzkern targets += vmlinux.bin.z $(obj)/vmlinux.bin.z: $(obj)/vmlinux.bin FORCE diff --git a/arch/mips/boot/compressed/decompress.c b/arch/mips/boot/compressed/decompress.c index 2c9573098c0d..a8c6fd6a4406 100644 --- a/arch/mips/boot/compressed/decompress.c +++ b/arch/mips/boot/compressed/decompress.c @@ -43,7 +43,8 @@ void error(char *x) /* activate the code for pre-boot environment */ #define STATIC static -#ifdef CONFIG_KERNEL_GZIP +#if defined(CONFIG_KERNEL_GZIP) || defined(CONFIG_KERNEL_XZ) || \ + defined(CONFIG_KERNEL_LZ4) void *memcpy(void *dest, const void *src, size_t n) { int i; @@ -54,6 +55,8 @@ void *memcpy(void *dest, const void *src, size_t n) d[i] = s[i]; return dest; } +#endif +#ifdef CONFIG_KERNEL_GZIP #include "../../../../lib/decompress_inflate.c" #endif @@ -70,6 +73,10 @@ void *memset(void *s, int c, size_t n) #include "../../../../lib/decompress_bunzip2.c" #endif +#ifdef CONFIG_KERNEL_LZ4 +#include "../../../../lib/decompress_unlz4.c" +#endif + #ifdef CONFIG_KERNEL_LZMA #include "../../../../lib/decompress_unlzma.c" #endif @@ -78,6 +85,10 @@ void *memset(void *s, int c, size_t n) #include "../../../../lib/decompress_unlzo.c" #endif +#ifdef CONFIG_KERNEL_XZ +#include "../../../../lib/decompress_unxz.c" +#endif + void decompress_kernel(unsigned long boot_heap_start) { unsigned long zimage_start, zimage_size; diff --git a/arch/mips/boot/compressed/ld.script b/arch/mips/boot/compressed/ld.script index 8e6b07ca2f5e..5a33409c7f63 100644 --- a/arch/mips/boot/compressed/ld.script +++ b/arch/mips/boot/compressed/ld.script @@ -8,6 +8,9 @@ OUTPUT_ARCH(mips) ENTRY(start) +PHDRS { + text PT_LOAD FLAGS(7); /* RWX */ +} SECTIONS { /* Text and read-only data */ @@ -15,7 +18,7 @@ SECTIONS .text : { *(.text) *(.rodata) - } + }: text /* End of text section */ /* Writable data */ diff --git a/arch/mips/boot/dts/include/dt-bindings b/arch/mips/boot/dts/include/dt-bindings new file mode 120000 index 000000000000..08c00e4972fa --- /dev/null +++ b/arch/mips/boot/dts/include/dt-bindings @@ -0,0 +1 @@ +../../../../../include/dt-bindings
\ No newline at end of file diff --git a/arch/mips/boot/ecoff.h b/arch/mips/boot/ecoff.h index 83e5c3813d67..7a75ce2c1bcd 100644 --- a/arch/mips/boot/ecoff.h +++ b/arch/mips/boot/ecoff.h @@ -12,7 +12,6 @@ typedef struct filehdr { } FILHDR; #define FILHSZ sizeof(FILHDR) -#define OMAGIC 0407 #define MIPSEBMAGIC 0x160 #define MIPSELMAGIC 0x162 diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c index 02193953eb9e..b752c4ed0b79 100644 --- a/arch/mips/cavium-octeon/csrc-octeon.c +++ b/arch/mips/cavium-octeon/csrc-octeon.c @@ -12,6 +12,7 @@ #include <linux/smp.h> #include <asm/cpu-info.h> +#include <asm/cpu-type.h> #include <asm/time.h> #include <asm/octeon/octeon.h> diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index 9d36774bded1..25fbfae06c1f 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -1776,7 +1776,7 @@ asmlinkage void plat_irq_dispatch(void) #ifdef CONFIG_HOTPLUG_CPU -void fixup_irqs(void) +void octeon_fixup_irqs(void) { irq_cpu_offline(); } diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 48b08eb9d9e4..331b837cec57 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -8,6 +8,7 @@ * written by Ralf Baechle <ralf@linux-mips.org> */ #include <linux/compiler.h> +#include <linux/vmalloc.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/console.h> @@ -998,7 +999,7 @@ void __init plat_mem_setup(void) if (total == 0) panic("Unable to allocate memory from " - "cvmx_bootmem_phy_alloc\n"); + "cvmx_bootmem_phy_alloc"); } /* @@ -1080,7 +1081,7 @@ void __init device_tree_init(void) /* Copy the default tree from init memory. */ initial_boot_params = early_init_dt_alloc_memory_arch(dt_size, 8); if (initial_boot_params == NULL) - panic("Could not allocate initial_boot_params\n"); + panic("Could not allocate initial_boot_params"); memcpy(initial_boot_params, fdt, dt_size); if (do_prune) { @@ -1139,3 +1140,30 @@ static int __init edac_devinit(void) return err; } device_initcall(edac_devinit); + +static void __initdata *octeon_dummy_iospace; + +static int __init octeon_no_pci_init(void) +{ + /* + * Initially assume there is no PCI. The PCI/PCIe platform code will + * later re-initialize these to correct values if they are present. + */ + octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT); + set_io_port_base((unsigned long)octeon_dummy_iospace); + ioport_resource.start = MAX_RESOURCE; + ioport_resource.end = 0; + return 0; +} +core_initcall(octeon_no_pci_init); + +static int __init octeon_no_pci_release(void) +{ + /* + * Release the allocated memory if a real IO space is there. + */ + if ((unsigned long)octeon_dummy_iospace != mips_io_port_base) + vfree(octeon_dummy_iospace); + return 0; +} +late_initcall(octeon_no_pci_release); diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index 138cc80c5928..24a2167db778 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -255,8 +255,6 @@ static void octeon_cpus_done(void) /* State of each CPU. */ DEFINE_PER_CPU(int, cpu_state); -extern void fixup_irqs(void); - static int octeon_cpu_disable(void) { unsigned int cpu = smp_processor_id(); @@ -267,7 +265,7 @@ static int octeon_cpu_disable(void) set_cpu_online(cpu, false); cpu_clear(cpu, cpu_callin_map); local_irq_disable(); - fixup_irqs(); + octeon_fixup_irqs(); local_irq_enable(); flush_cache_all(); diff --git a/arch/mips/cobalt/Makefile b/arch/mips/cobalt/Makefile index 61a334ac43ac..558e94977942 100644 --- a/arch/mips/cobalt/Makefile +++ b/arch/mips/cobalt/Makefile @@ -5,5 +5,4 @@ obj-y := buttons.o irq.o lcd.o led.o reset.o rtc.o serial.o setup.o time.o obj-$(CONFIG_PCI) += pci.o -obj-$(CONFIG_EARLY_PRINTK) += console.o obj-$(CONFIG_MTD_PHYSMAP) += mtd.o diff --git a/arch/mips/cobalt/console.c b/arch/mips/cobalt/console.c deleted file mode 100644 index d1ba701c9dd1..000000000000 --- a/arch/mips/cobalt/console.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * (C) P. Horton 2006 - */ -#include <linux/io.h> -#include <linux/serial_reg.h> - -#include <cobalt.h> - -#define UART_BASE ((void __iomem *)CKSEG1ADDR(0x1c800000)) - -void prom_putchar(char c) -{ - if (cobalt_board_id <= COBALT_BRD_ID_QUBE1) - return; - - while (!(readb(UART_BASE + UART_LSR) & UART_LSR_THRE)) - ; - - writeb(c, UART_BASE + UART_TX); -} diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c index ec3b2c417f7c..9a8c2fe8d334 100644 --- a/arch/mips/cobalt/setup.c +++ b/arch/mips/cobalt/setup.c @@ -17,6 +17,7 @@ #include <asm/bootinfo.h> #include <asm/reboot.h> +#include <asm/setup.h> #include <asm/gt64120.h> #include <cobalt.h> @@ -112,6 +113,8 @@ void __init prom_init(void) } add_memory_region(0x0, memsz, BOOT_MEM_RAM); + + setup_8250_early_printk_port(CKSEG1ADDR(0x1c800000), 0, 0); } void __init prom_free_prom_memory(void) diff --git a/arch/mips/configs/powertv_defconfig b/arch/mips/configs/powertv_defconfig deleted file mode 100644 index 7fda0ce5f692..000000000000 --- a/arch/mips/configs/powertv_defconfig +++ /dev/null @@ -1,136 +0,0 @@ -CONFIG_POWERTV=y -CONFIG_BOOTLOADER_FAMILY="R2" -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_HZ_1000=y -CONFIG_PREEMPT=y -# CONFIG_SECCOMP is not set -CONFIG_EXPERIMENTAL=y -CONFIG_CROSS_COMPILE="" -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=16 -CONFIG_RELAY=y -CONFIG_BLK_DEV_INITRD=y -# CONFIG_RD_GZIP is not set -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS_ALL=y -# CONFIG_PCSPKR_PLATFORM is not set -# CONFIG_EPOLL is not set -# CONFIG_SIGNALFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_SLUB_DEBUG is not set -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PCI=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_PNP=y -CONFIG_SYN_COOKIES=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -CONFIG_IPV6=y -CONFIG_IPV6_PRIVACY=y -CONFIG_INET6_AH=y -CONFIG_INET6_ESP=y -CONFIG_INET6_IPCOMP=y -# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET6_XFRM_MODE_TUNNEL is not set -# CONFIG_INET6_XFRM_MODE_BEET is not set -# CONFIG_IPV6_SIT is not set -CONFIG_IPV6_TUNNEL=y -CONFIG_NETFILTER=y -# CONFIG_BRIDGE_NETFILTER is not set -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y -CONFIG_IP_NF_IPTABLES=y -CONFIG_IP_NF_FILTER=y -CONFIG_IP_NF_ARPTABLES=y -CONFIG_IP_NF_ARPFILTER=y -CONFIG_IP6_NF_IPTABLES=y -CONFIG_IP6_NF_FILTER=y -CONFIG_BRIDGE=y -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_TBF=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_NAND=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=32768 -# CONFIG_MISC_DEVICES is not set -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=y -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_ATA=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -# CONFIG_WLAN is not set -CONFIG_USB_RTL8150=y -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -# CONFIG_DEVKMEM is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_MFD_SUPPORT is not set -# CONFIG_VGA_ARB is not set -CONFIG_USB_HIDDEV=y -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_TT_NEWSCHED is not set -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SERIAL=y -CONFIG_USB_SERIAL_CONSOLE=y -CONFIG_USB_SERIAL_CP210X=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -# CONFIG_EXT3_FS_XATTR is not set -# CONFIG_DNOTIFY is not set -CONFIG_FUSE_FS=y -CONFIG_PROC_KCORE=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_CRAMFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_DEBUG_PREEMPT is not set -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_EARLY_PRINTK is not set -CONFIG_CMDLINE_BOOL=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -# CONFIG_CRYPTO_HW is not set diff --git a/arch/mips/configs/xway_defconfig b/arch/mips/configs/xway_defconfig new file mode 100644 index 000000000000..8987846240f7 --- /dev/null +++ b/arch/mips/configs/xway_defconfig @@ -0,0 +1,159 @@ +CONFIG_LANTIQ=y +CONFIG_XRX200_PHY_FW=y +CONFIG_CPU_MIPS32_R2=y +# CONFIG_COMPACTION is not set +# CONFIG_CROSS_MEMORY_ATTACH is not set +CONFIG_HZ_100=y +# CONFIG_SECCOMP is not set +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_GZIP is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_AIO is not set +CONFIG_EMBEDDED=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_COREDUMP is not set +# CONFIG_SUSPEND is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_ARPD=y +CONFIG_SYN_COOKIES=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +CONFIG_TCP_CONG_ADVANCED=y +# CONFIG_TCP_CONG_BIC is not set +# CONFIG_TCP_CONG_WESTWOOD is not set +# CONFIG_TCP_CONG_HTCP is not set +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +# CONFIG_BRIDGE_NETFILTER is not set +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NF_CONNTRACK_IPV4=m +# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_RAW=m +CONFIG_BRIDGE=y +# CONFIG_BRIDGE_IGMP_SNOOPING is not set +CONFIG_VLAN_8021Q=y +CONFIG_NET_SCHED=y +CONFIG_HAMRADIO=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_LANTIQ=y +CONFIG_EEPROM_93CX6=m +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_NETDEVICES=y +CONFIG_LANTIQ_ETOP=y +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_PHYLIB=y +CONFIG_PPP=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOE=m +CONFIG_PPP_ASYNC=m +CONFIG_ISDN=y +CONFIG_INPUT=m +CONFIG_INPUT_POLLDEV=m +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_MISC=y +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SPI=y +CONFIG_GPIO_MM_LANTIQ=y +CONFIG_GPIO_STP_XWAY=y +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_HID is not set +# CONFIG_USB_HID is not set +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DEBUG=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_STAGING=y +# CONFIG_IOMMU_SUPPORT is not set +# CONFIG_DNOTIFY is not set +# CONFIG_PROC_PAGE_MONITOR is not set +CONFIG_TMPFS=y +CONFIG_TMPFS_XATTR=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +# CONFIG_JFFS2_FS_POSIX_ACL is not set +# CONFIG_JFFS2_FS_SECURITY is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +# CONFIG_JFFS2_ZLIB is not set +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_ZLIB is not set +CONFIG_SQUASHFS_XZ=y +CONFIG_PRINTK_TIME=y +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_STRIP_ASM_SYMS=y +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_FTRACE is not set +CONFIG_CMDLINE_BOOL=y +CONFIG_CRYPTO_MANAGER=m +CONFIG_CRYPTO_ARC4=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32_SARWATE=y +CONFIG_AVERAGE=y diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S index 22afed16ccde..41a2fa1fa12e 100644 --- a/arch/mips/dec/int-handler.S +++ b/arch/mips/dec/int-handler.S @@ -118,7 +118,7 @@ * 7 FPU/R4k timer * * We handle the IRQ according to _our_ priority (see setup.c), - * then we just return. If multiple IRQs are pending then we will + * then we just return. If multiple IRQs are pending then we will * just take another exception, big deal. */ .align 5 @@ -146,7 +146,7 @@ /* * Find irq with highest priority */ - PTR_LA t1,cpu_mask_nr_tbl + PTR_LA t1,cpu_mask_nr_tbl 1: lw t2,(t1) nop and t2,t0 @@ -195,7 +195,7 @@ /* * Find irq with highest priority */ - PTR_LA t1,asic_mask_nr_tbl + PTR_LA t1,asic_mask_nr_tbl 2: lw t2,(t1) nop and t2,t0 @@ -221,7 +221,7 @@ FEXPORT(cpu_all_int) # HALT, timers, software junk li a0,DEC_CPU_IRQ_BASE srl t0,CAUSEB_IP - li t1,CAUSEF_IP>>CAUSEB_IP # mask + li t1,CAUSEF_IP>>CAUSEB_IP # mask b 1f li t2,4 # nr of bits / 2 diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c index 824e08c73798..e04d973ce5aa 100644 --- a/arch/mips/dec/ioasic-irq.c +++ b/arch/mips/dec/ioasic-irq.c @@ -1,7 +1,7 @@ /* * DEC I/O ASIC interrupts. * - * Copyright (c) 2002, 2003 Maciej W. Rozycki + * Copyright (c) 2002, 2003, 2013 Maciej W. Rozycki * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -51,14 +51,51 @@ static struct irq_chip ioasic_irq_type = { .irq_unmask = unmask_ioasic_irq, }; +static void clear_ioasic_dma_irq(struct irq_data *d) +{ + u32 sir; + + sir = ~(1 << (d->irq - ioasic_irq_base)); + ioasic_write(IO_REG_SIR, sir); + fast_iob(); +} + static struct irq_chip ioasic_dma_irq_type = { .name = "IO-ASIC-DMA", - .irq_ack = ack_ioasic_irq, + .irq_ack = clear_ioasic_dma_irq, .irq_mask = mask_ioasic_irq, - .irq_mask_ack = ack_ioasic_irq, .irq_unmask = unmask_ioasic_irq, + .irq_eoi = clear_ioasic_dma_irq, }; +/* + * I/O ASIC implements two kinds of DMA interrupts, informational and + * error interrupts. + * + * The formers do not stop DMA and should be cleared as soon as possible + * so that if they retrigger before the handler has completed, usually as + * a side effect of actions taken by the handler, then they are reissued. + * These use the `handle_edge_irq' handler that clears the request right + * away. + * + * The latters stop DMA and do not resume it until the interrupt has been + * cleared. This cannot be done until after a corrective action has been + * taken and this also means they will not retrigger. Therefore they use + * the `handle_fasteoi_irq' handler that only clears the request on the + * way out. Because MIPS processor interrupt inputs, one of which the I/O + * ASIC is cascaded to, are level-triggered it is recommended that error + * DMA interrupt action handlers are registered with the IRQF_ONESHOT flag + * set so that they are run with the interrupt line masked. + * + * This mask has `1' bits in the positions of informational interrupts. + */ +#define IO_IRQ_DMA_INFO \ + (IO_IRQ_MASK(IO_INR_SCC0A_RXDMA) | \ + IO_IRQ_MASK(IO_INR_SCC1A_RXDMA) | \ + IO_IRQ_MASK(IO_INR_ISDN_TXDMA) | \ + IO_IRQ_MASK(IO_INR_ISDN_RXDMA) | \ + IO_IRQ_MASK(IO_INR_ASC_DMA)) + void __init init_ioasic_irqs(int base) { int i; @@ -71,7 +108,9 @@ void __init init_ioasic_irqs(int base) irq_set_chip_and_handler(i, &ioasic_irq_type, handle_level_irq); for (; i < base + IO_IRQ_LINES; i++) - irq_set_chip(i, &ioasic_dma_irq_type); + irq_set_chip_and_handler(i, &ioasic_dma_irq_type, + 1 << (i - base) & IO_IRQ_DMA_INFO ? + handle_edge_irq : handle_fasteoi_irq); ioasic_irq_base = base; } diff --git a/arch/mips/dec/prom/call_o32.S b/arch/mips/dec/prom/call_o32.S index c0d1522d448f..8c8498159e43 100644 --- a/arch/mips/dec/prom/call_o32.S +++ b/arch/mips/dec/prom/call_o32.S @@ -14,7 +14,7 @@ /* Maximum number of arguments supported. Must be even! */ #define O32_ARGC 32 -/* Number of static registers we save. */ +/* Number of static registers we save. */ #define O32_STATC 11 /* Frame size for both of the above. */ #define O32_FRAMESZ (4 * O32_ARGC + SZREG * O32_STATC) diff --git a/arch/mips/dec/prom/init.c b/arch/mips/dec/prom/init.c index ab169046e442..4e1761e0a09a 100644 --- a/arch/mips/dec/prom/init.c +++ b/arch/mips/dec/prom/init.c @@ -13,6 +13,7 @@ #include <asm/bootinfo.h> #include <asm/cpu.h> +#include <asm/cpu-type.h> #include <asm/processor.h> #include <asm/dec/prom.h> @@ -103,7 +104,7 @@ void __init prom_init(void) if (prom_is_rex(magic)) rex_clear_cache(); - /* Register the early console. */ + /* Register the early console. */ register_prom_console(); /* Were we compiled with the right CPU option? */ diff --git a/arch/mips/dec/prom/memory.c b/arch/mips/dec/prom/memory.c index 0aadac742900..8c62316f22f4 100644 --- a/arch/mips/dec/prom/memory.c +++ b/arch/mips/dec/prom/memory.c @@ -22,7 +22,7 @@ volatile unsigned long mem_err; /* So we know an error occurred */ /* * Probe memory in 4MB chunks, waiting for an error to tell us we've fallen - * off the end of real memory. Only suitable for the 2100/3100's (PMAX). + * off the end of real memory. Only suitable for the 2100/3100's (PMAX). */ #define CHUNK_SIZE 0x400000 diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c index 741cb4235bde..56e6e2c23683 100644 --- a/arch/mips/dec/setup.c +++ b/arch/mips/dec/setup.c @@ -65,7 +65,7 @@ EXPORT_SYMBOL(ioasic_base); /* * IRQ routing and priority tables. Priorites are set as follows: * - * KN01 KN230 KN02 KN02-BA KN02-CA KN03 + * KN01 KN230 KN02 KN02-BA KN02-CA KN03 * * MEMORY CPU CPU CPU ASIC CPU CPU * RTC CPU CPU CPU ASIC CPU CPU @@ -413,7 +413,7 @@ static void __init dec_init_kn02(void) /* * Machine-specific initialisation for KN02-BA, aka DS5000/1xx - * (xx = 20, 25, 33), aka 3min. Also applies to KN04(-BA), aka + * (xx = 20, 25, 33), aka 3min. Also applies to KN04(-BA), aka * DS5000/150, aka 4min. */ static int kn02ba_interrupt[DEC_NR_INTS] __initdata = { diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c index ea57f39e6736..1914e56f0d96 100644 --- a/arch/mips/dec/time.c +++ b/arch/mips/dec/time.c @@ -125,13 +125,18 @@ int rtc_mips_set_mmss(unsigned long nowtime) void __init plat_time_init(void) { + int ioasic_clock = 0; u32 start, end; - int i = HZ / 10; + int i = HZ / 8; /* Set up the rate of periodic DS1287 interrupts. */ ds1287_set_base_clock(HZ); + /* On some I/O ASIC systems we have the I/O ASIC's counter. */ + if (IOASIC) + ioasic_clock = dec_ioasic_clocksource_init() == 0; if (cpu_has_counter) { + ds1287_timer_state(); while (!ds1287_timer_state()) ; @@ -143,12 +148,24 @@ void __init plat_time_init(void) end = read_c0_count(); - mips_hpt_frequency = (end - start) * 10; + mips_hpt_frequency = (end - start) * 8; printk(KERN_INFO "MIPS counter frequency %dHz\n", mips_hpt_frequency); - } else if (IOASIC) - /* For pre-R4k systems we use the I/O ASIC's counter. */ - dec_ioasic_clocksource_init(); + + /* + * All R4k DECstations suffer from the CP0 Count erratum, + * so we can't use the timer as a clock source, and a clock + * event both at a time. An accurate wall clock is more + * important than a high-precision interval timer so only + * use the timer as a clock source, and not a clock event + * if there's no I/O ASIC counter available to serve as a + * clock source. + */ + if (!ioasic_clock) { + init_r4k_clocksource(); + mips_hpt_frequency = 0; + } + } ds1287_clockevent_init(dec_interrupt[DEC_IRQ_RTC]); } diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild index 9b54b7a403d4..1acbb8b77a71 100644 --- a/arch/mips/include/asm/Kbuild +++ b/arch/mips/include/asm/Kbuild @@ -1,2 +1,16 @@ # MIPS headers +generic-y += cputime.h +generic-y += current.h +generic-y += emergency-restart.h +generic-y += local64.h +generic-y += mutex.h +generic-y += parport.h +generic-y += percpu.h +generic-y += scatterlist.h +generic-y += sections.h +generic-y += segment.h +generic-y += serial.h generic-y += trace_clock.h +generic-y += preempt.h +generic-y += ucontext.h +generic-y += xor.h diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index 13d61c002e4f..3f745459fdb5 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -58,7 +58,7 @@ /* * Memory segments (64bit kernel mode addresses) - * The compatibility segments use the full 64-bit sign extended value. Note + * The compatibility segments use the full 64-bit sign extended value. Note * the R8000 doesn't have them so don't reference these in generic MIPS code. */ #define XKUSEG _CONST64_(0x0000000000000000) @@ -131,7 +131,7 @@ /* * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting - * the region, 3 bits for the CCA mode. This leaves 59 bits of which the + * the region, 3 bits for the CCA mode. This leaves 59 bits of which the * R8000 implements most with its 48-bit physical address space. */ #define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h index 08b607969a16..7eed2f261710 100644 --- a/arch/mips/include/asm/atomic.h +++ b/arch/mips/include/asm/atomic.h @@ -1,5 +1,5 @@ /* - * Atomic operations that C can't guarantee us. Useful for + * Atomic operations that C can't guarantee us. Useful for * resource counting etc.. * * But use these as seldom as possible since they are much more slower diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h index 314ab5532019..f26d8e1bf3c3 100644 --- a/arch/mips/include/asm/barrier.h +++ b/arch/mips/include/asm/barrier.h @@ -18,7 +18,7 @@ * over this barrier. All reads preceding this primitive are guaranteed * to access memory (but not necessarily other CPUs' caches) before any * reads following this primitive that depend on the data return by - * any of the preceding reads. This primitive is much lighter weight than + * any of the preceding reads. This primitive is much lighter weight than * rmb() on most CPUs, and is never heavier weight than is * rmb(). * @@ -43,7 +43,7 @@ * </programlisting> * * because the read of "*q" depends on the read of "p" and these - * two reads are separated by a read_barrier_depends(). However, + * two reads are separated by a read_barrier_depends(). However, * the following code, with the same initial values for "a" and "b": * * <programlisting> @@ -57,7 +57,7 @@ * </programlisting> * * does not enforce ordering, since there is no data dependency between - * the read of "a" and the read of "b". Therefore, on some CPUs, such + * the read of "a" and the read of "b". Therefore, on some CPUs, such * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb() * in cases like this where there are no data dependencies. */ diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h index 552a65a0cf2b..27bd060d716e 100644 --- a/arch/mips/include/asm/bmips.h +++ b/arch/mips/include/asm/bmips.h @@ -65,44 +65,33 @@ static inline unsigned long bmips_read_zscm_reg(unsigned int offset) { unsigned long ret; - __asm__ __volatile__( - ".set push\n" - ".set noreorder\n" - "cache %1, 0(%2)\n" - "sync\n" - "_ssnop\n" - "_ssnop\n" - "_ssnop\n" - "_ssnop\n" - "_ssnop\n" - "_ssnop\n" - "_ssnop\n" - "mfc0 %0, $28, 3\n" - "_ssnop\n" - ".set pop\n" - : "=&r" (ret) - : "i" (Index_Load_Tag_S), "r" (ZSCM_REG_BASE + offset) - : "memory"); + barrier(); + cache_op(Index_Load_Tag_S, ZSCM_REG_BASE + offset); + __sync(); + _ssnop(); + _ssnop(); + _ssnop(); + _ssnop(); + _ssnop(); + _ssnop(); + _ssnop(); + ret = read_c0_ddatalo(); + _ssnop(); + return ret; } static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data) { - __asm__ __volatile__( - ".set push\n" - ".set noreorder\n" - "mtc0 %0, $28, 3\n" - "_ssnop\n" - "_ssnop\n" - "_ssnop\n" - "cache %1, 0(%2)\n" - "_ssnop\n" - "_ssnop\n" - "_ssnop\n" - : /* no outputs */ - : "r" (data), - "i" (Index_Store_Tag_S), "r" (ZSCM_REG_BASE + offset) - : "memory"); + write_c0_ddatalo(data); + _ssnop(); + _ssnop(); + _ssnop(); + cache_op(Index_Store_Tag_S, ZSCM_REG_BASE + offset); + _ssnop(); + _ssnop(); + _ssnop(); + barrier(); } #endif /* !defined(__ASSEMBLY__) */ diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h index 68f37e3eccc7..c75025f27c20 100644 --- a/arch/mips/include/asm/cacheops.h +++ b/arch/mips/include/asm/cacheops.h @@ -14,56 +14,52 @@ /* * Cache Operations available on all MIPS processors with R4000-style caches */ -#define Index_Invalidate_I 0x00 -#define Index_Writeback_Inv_D 0x01 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 -#if defined(CONFIG_CPU_LOONGSON2) -#define Hit_Invalidate_I 0x00 -#else -#define Hit_Invalidate_I 0x10 -#endif -#define Hit_Invalidate_D 0x11 -#define Hit_Writeback_Inv_D 0x15 +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#define Hit_Invalidate_I 0x10 +#define Hit_Invalidate_D 0x11 +#define Hit_Writeback_Inv_D 0x15 /* * R4000-specific cacheops */ -#define Create_Dirty_Excl_D 0x0d -#define Fill 0x14 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 +#define Create_Dirty_Excl_D 0x0d +#define Fill 0x14 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 /* * R4000SC and R4400SC-specific cacheops */ -#define Index_Invalidate_SI 0x02 -#define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_SD 0x1b -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f +#define Index_Invalidate_SI 0x02 +#define Index_Writeback_Inv_SD 0x03 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_SD 0x1b +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f /* * R5000-specific cacheops */ -#define R5K_Page_Invalidate_S 0x17 +#define R5K_Page_Invalidate_S 0x17 /* * RM7000-specific cacheops */ -#define Page_Invalidate_T 0x16 -#define Index_Store_Tag_T 0x0a -#define Index_Load_Tag_T 0x06 +#define Page_Invalidate_T 0x16 +#define Index_Store_Tag_T 0x0a +#define Index_Load_Tag_T 0x06 /* * R10000-specific cacheops @@ -71,17 +67,22 @@ * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. * Most of the _S cacheops are identical to the R4000SC _SD cacheops. */ -#define Index_Writeback_Inv_S 0x03 -#define Index_Load_Tag_S 0x07 -#define Index_Store_Tag_S 0x0B -#define Hit_Invalidate_S 0x13 -#define Cache_Barrier 0x14 -#define Hit_Writeback_Inv_S 0x17 -#define Index_Load_Data_I 0x18 -#define Index_Load_Data_D 0x19 -#define Index_Load_Data_S 0x1b -#define Index_Store_Data_I 0x1c -#define Index_Store_Data_D 0x1d -#define Index_Store_Data_S 0x1f +#define Index_Writeback_Inv_S 0x03 +#define Index_Load_Tag_S 0x07 +#define Index_Store_Tag_S 0x0B +#define Hit_Invalidate_S 0x13 +#define Cache_Barrier 0x14 +#define Hit_Writeback_Inv_S 0x17 +#define Index_Load_Data_I 0x18 +#define Index_Load_Data_D 0x19 +#define Index_Load_Data_S 0x1b +#define Index_Store_Data_I 0x1c +#define Index_Store_Data_D 0x1d +#define Index_Store_Data_S 0x1f + +/* + * Loongson2-specific cacheops + */ +#define Hit_Invalidate_I_Loongson23 0x00 #endif /* __ASM_CACHEOPS_H */ diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index fa44f3ec5302..d445d060e346 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -13,12 +13,6 @@ #include <asm/cpu-info.h> #include <cpu-feature-overrides.h> -#ifndef current_cpu_type -#define current_cpu_type() current_cpu_data.cputype -#endif - -#define boot_cpu_type() cpu_data[0].cputype - /* * SMP assumption: Options of CPU 0 are a superset of all processors. * This is true for all known MIPS systems. @@ -193,7 +187,7 @@ /* * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other - * pre-MIPS32/MIPS53 processors have CLO, CLZ. The IDT RC64574 is 64-bit and + * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. */ diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h index 41401d8eb7d1..21c8e29c8f91 100644 --- a/arch/mips/include/asm/cpu-info.h +++ b/arch/mips/include/asm/cpu-info.h @@ -84,6 +84,7 @@ struct cpuinfo_mips { extern struct cpuinfo_mips cpu_data[]; #define current_cpu_data cpu_data[smp_processor_id()] #define raw_current_cpu_data cpu_data[raw_smp_processor_id()] +#define boot_cpu_data cpu_data[0] extern void cpu_probe(void); extern void cpu_report(void); diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h new file mode 100644 index 000000000000..4a402cc60c03 --- /dev/null +++ b/arch/mips/include/asm/cpu-type.h @@ -0,0 +1,203 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + */ +#ifndef __ASM_CPU_TYPE_H +#define __ASM_CPU_TYPE_H + +#include <linux/smp.h> +#include <linux/compiler.h> + +static inline int __pure __get_cpu_type(const int cpu_type) +{ + switch (cpu_type) { +#if defined(CONFIG_SYS_HAS_CPU_LOONGSON2E) || \ + defined(CONFIG_SYS_HAS_CPU_LOONGSON2F) + case CPU_LOONGSON2: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_LOONGSON1B + case CPU_LOONGSON1: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R1 + case CPU_4KC: + case CPU_ALCHEMY: + case CPU_BMIPS3300: + case CPU_BMIPS4350: + case CPU_PR4450: + case CPU_BMIPS32: + case CPU_JZRISC: +#endif + +#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R1) || \ + defined(CONFIG_SYS_HAS_CPU_MIPS32_R2) + case CPU_4KEC: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R2 + case CPU_4KSC: + case CPU_24K: + case CPU_34K: + case CPU_1004K: + case CPU_74K: + case CPU_M14KC: + case CPU_M14KEC: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1 + case CPU_5KC: + case CPU_5KE: + case CPU_20KC: + case CPU_25KF: + case CPU_SB1: + case CPU_SB1A: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R2 + /* + * All MIPS64 R2 processors have their own special symbols. That is, + * there currently is no pure R2 core + */ +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R3000 + case CPU_R2000: + case CPU_R3000: + case CPU_R3000A: + case CPU_R3041: + case CPU_R3051: + case CPU_R3052: + case CPU_R3081: + case CPU_R3081E: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_TX39XX + case CPU_TX3912: + case CPU_TX3922: + case CPU_TX3927: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_VR41XX + case CPU_VR41XX: + case CPU_VR4111: + case CPU_VR4121: + case CPU_VR4122: + case CPU_VR4131: + case CPU_VR4133: + case CPU_VR4181: + case CPU_VR4181A: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R4300 + case CPU_R4300: + case CPU_R4310: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R4X00 + case CPU_R4000PC: + case CPU_R4000SC: + case CPU_R4000MC: + case CPU_R4200: + case CPU_R4400PC: + case CPU_R4400SC: + case CPU_R4400MC: + case CPU_R4600: + case CPU_R4700: + case CPU_R4640: + case CPU_R4650: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_TX49XX + case CPU_TX49XX: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R5000 + case CPU_R5000: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R5432 + case CPU_R5432: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R5500 + case CPU_R5500: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R6000 + case CPU_R6000: + case CPU_R6000A: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_NEVADA + case CPU_NEVADA: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R8000 + case CPU_R8000: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R10000 + case CPU_R10000: + case CPU_R12000: + case CPU_R14000: +#endif +#ifdef CONFIG_SYS_HAS_CPU_RM7000 + case CPU_RM7000: + case CPU_SR71000: +#endif +#ifdef CONFIG_SYS_HAS_CPU_RM9000 + case CPU_RM9000: +#endif +#ifdef CONFIG_SYS_HAS_CPU_SB1 + case CPU_SB1: + case CPU_SB1A: +#endif +#ifdef CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON + case CPU_CAVIUM_OCTEON: + case CPU_CAVIUM_OCTEON_PLUS: + case CPU_CAVIUM_OCTEON2: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_BMIPS4380 + case CPU_BMIPS4380: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_BMIPS5000 + case CPU_BMIPS5000: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_XLP + case CPU_XLP: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_XLR + case CPU_XLR: +#endif + break; + default: + unreachable(); + } + + return cpu_type; +} + +static inline int __pure current_cpu_type(void) +{ + const int cpu_type = current_cpu_data.cputype; + + return __get_cpu_type(cpu_type); +} + +static inline int __pure boot_cpu_type(void) +{ + const int cpu_type = cpu_data[0].cputype; + + return __get_cpu_type(cpu_type); +} + +#endif /* __ASM_CPU_TYPE_H */ diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 632bbe5a79ea..d2035e16502a 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -3,15 +3,14 @@ * various MIPS cpu types. * * Copyright (C) 1996 David S. Miller (davem@davemloft.net) - * Copyright (C) 2004 Maciej W. Rozycki + * Copyright (C) 2004, 2013 Maciej W. Rozycki */ #ifndef _ASM_CPU_H #define _ASM_CPU_H -/* Assigned Company values for bits 23:16 of the PRId Register - (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from - MTI, the PRId register is defined in this (backwards compatible) - way: +/* + As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0 + register 15, select 0) is defined in this (backwards compatible) way: +----------------+----------------+----------------+----------------+ | Company Options| Company ID | Processor ID | Revision | @@ -23,6 +22,14 @@ spec. */ +#define PRID_OPT_MASK 0xff000000 + +/* + * Assigned Company values for bits 23:16 of the PRId register. + */ + +#define PRID_COMP_MASK 0xff0000 + #define PRID_COMP_LEGACY 0x000000 #define PRID_COMP_MIPS 0x010000 #define PRID_COMP_BROADCOM 0x020000 @@ -38,10 +45,17 @@ #define PRID_COMP_INGENIC 0xd00000 /* - * Assigned values for the product ID register. In order to detect a - * certain CPU type exactly eventually additional registers may need to - * be examined. These are valid when 23:16 == PRID_COMP_LEGACY + * Assigned Processor ID (implementation) values for bits 15:8 of the PRId + * register. In order to detect a certain CPU type exactly eventually + * additional registers may need to be examined. */ + +#define PRID_IMP_MASK 0xff00 + +/* + * These are valid when 23:16 == PRID_COMP_LEGACY + */ + #define PRID_IMP_R2000 0x0100 #define PRID_IMP_AU1_REV1 0x0100 #define PRID_IMP_AU1_REV2 0x0200 @@ -141,6 +155,9 @@ #define PRID_IMP_CAVIUM_CN68XX 0x9100 #define PRID_IMP_CAVIUM_CN66XX 0x9200 #define PRID_IMP_CAVIUM_CN61XX 0x9300 +#define PRID_IMP_CAVIUM_CNF71XX 0x9400 +#define PRID_IMP_CAVIUM_CN78XX 0x9500 +#define PRID_IMP_CAVIUM_CN70XX 0x9600 /* * These are the PRID's for when 23:16 == PRID_COMP_INGENIC @@ -176,13 +193,18 @@ #define PRID_IMP_NETLOGIC_XLP8XX 0x1000 #define PRID_IMP_NETLOGIC_XLP3XX 0x1100 +#define PRID_IMP_NETLOGIC_XLP2XX 0x1200 /* - * Definitions for 7:0 on legacy processors + * Particular Revision values for bits 7:0 of the PRId register. */ #define PRID_REV_MASK 0x00ff +/* + * Definitions for 7:0 on legacy processors + */ + #define PRID_REV_TX4927 0x0022 #define PRID_REV_TX4937 0x0030 #define PRID_REV_R4400 0x0040 @@ -223,6 +245,8 @@ * 31 16 15 8 7 0 */ +#define FPIR_IMP_MASK 0xff00 + #define FPIR_IMP_NONE 0x0000 enum cpu_type_enum { @@ -272,7 +296,7 @@ enum cpu_type_enum { */ CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, - CPU_XLR, CPU_XLP, + CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, CPU_LAST }; diff --git a/arch/mips/include/asm/cputime.h b/arch/mips/include/asm/cputime.h deleted file mode 100644 index c00eacbdd979..000000000000 --- a/arch/mips/include/asm/cputime.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __MIPS_CPUTIME_H -#define __MIPS_CPUTIME_H - -#include <asm-generic/cputime.h> - -#endif /* __MIPS_CPUTIME_H */ diff --git a/arch/mips/include/asm/current.h b/arch/mips/include/asm/current.h deleted file mode 100644 index 4c51401b5537..000000000000 --- a/arch/mips/include/asm/current.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/current.h> diff --git a/arch/mips/include/asm/dec/ioasic.h b/arch/mips/include/asm/dec/ioasic.h index 98badd6bf22d..be4d62a5a10e 100644 --- a/arch/mips/include/asm/dec/ioasic.h +++ b/arch/mips/include/asm/dec/ioasic.h @@ -33,6 +33,6 @@ static inline u32 ioasic_read(unsigned int reg) extern void init_ioasic_irqs(int base); -extern void dec_ioasic_clocksource_init(void); +extern int dec_ioasic_clocksource_init(void); #endif /* __ASM_DEC_IOASIC_H */ diff --git a/arch/mips/include/asm/dec/ioasic_addrs.h b/arch/mips/include/asm/dec/ioasic_addrs.h index a8665a7611c2..8bd95971fe2d 100644 --- a/arch/mips/include/asm/dec/ioasic_addrs.h +++ b/arch/mips/include/asm/dec/ioasic_addrs.h @@ -40,7 +40,7 @@ #define IOASIC_FLOPPY (11*IOASIC_SLOT_SIZE) /* FDC (maxine) */ #define IOASIC_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */ #define IOASIC_FDC_DMA (13*IOASIC_SLOT_SIZE) /* FDC DMA (maxine) */ -#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE) /* ??? */ +#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE) /* ??? */ #define IOASIC_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */ diff --git a/arch/mips/include/asm/dec/kn01.h b/arch/mips/include/asm/dec/kn01.h index 0eb3241de706..88d9ffd74258 100644 --- a/arch/mips/include/asm/dec/kn01.h +++ b/arch/mips/include/asm/dec/kn01.h @@ -57,12 +57,12 @@ /* * System Control & Status Register bits. */ -#define KN01_CSR_MNFMOD (1<<15) /* MNFMOD manufacturing jumper */ -#define KN01_CSR_STATUS (1<<14) /* self-test result status output */ -#define KN01_CSR_PARDIS (1<<13) /* parity error disable */ -#define KN01_CSR_CRSRTST (1<<12) /* PCC test output */ -#define KN01_CSR_MONO (1<<11) /* mono/color fb SIMM installed */ -#define KN01_CSR_MEMERR (1<<10) /* write timeout error status & ack*/ +#define KN01_CSR_MNFMOD (1<<15) /* MNFMOD manufacturing jumper */ +#define KN01_CSR_STATUS (1<<14) /* self-test result status output */ +#define KN01_CSR_PARDIS (1<<13) /* parity error disable */ +#define KN01_CSR_CRSRTST (1<<12) /* PCC test output */ +#define KN01_CSR_MONO (1<<11) /* mono/color fb SIMM installed */ +#define KN01_CSR_MEMERR (1<<10) /* write timeout error status & ack*/ #define KN01_CSR_VINT (1<<9) /* PCC area detect #2 status & ack */ #define KN01_CSR_TXDIS (1<<8) /* DZ11 transmit disable */ #define KN01_CSR_VBGTRG (1<<2) /* blue DAC voltage over green (r/o) */ diff --git a/arch/mips/include/asm/dec/kn02ca.h b/arch/mips/include/asm/dec/kn02ca.h index 69dc2a9a2d0f..92c0fe256099 100644 --- a/arch/mips/include/asm/dec/kn02ca.h +++ b/arch/mips/include/asm/dec/kn02ca.h @@ -68,7 +68,7 @@ #define KN03CA_IO_SSR_ISDN_RST (1<<12) /* ~ISDN (Am79C30A) reset */ #define KN03CA_IO_SSR_FLOPPY_RST (1<<7) /* ~FDC (82077) reset */ -#define KN03CA_IO_SSR_VIDEO_RST (1<<6) /* ~framebuffer reset */ +#define KN03CA_IO_SSR_VIDEO_RST (1<<6) /* ~framebuffer reset */ #define KN03CA_IO_SSR_AB_RST (1<<5) /* ACCESS.bus reset */ #define KN03CA_IO_SSR_RES_4 (1<<4) /* unused */ #define KN03CA_IO_SSR_RES_3 (1<<4) /* unused */ diff --git a/arch/mips/include/asm/dec/prom.h b/arch/mips/include/asm/dec/prom.h index 446577712bee..c0ead6313845 100644 --- a/arch/mips/include/asm/dec/prom.h +++ b/arch/mips/include/asm/dec/prom.h @@ -49,7 +49,7 @@ #ifdef CONFIG_64BIT -#define prom_is_rex(magic) 1 /* KN04 and KN05 are REX PROMs. */ +#define prom_is_rex(magic) 1 /* KN04 and KN05 are REX PROMs. */ #else /* !CONFIG_64BIT */ diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h index cf3ae2480b1d..a66359ef4ece 100644 --- a/arch/mips/include/asm/elf.h +++ b/arch/mips/include/asm/elf.h @@ -331,6 +331,7 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); #define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \ dump_task_fpu(tsk, elf_fpregs) +#define CORE_DUMP_USE_REGSET #define ELF_EXEC_PAGESIZE PAGE_SIZE /* This yields a mask that user programs can use to figure out what diff --git a/arch/mips/include/asm/emergency-restart.h b/arch/mips/include/asm/emergency-restart.h deleted file mode 100644 index 108d8c48e42e..000000000000 --- a/arch/mips/include/asm/emergency-restart.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_EMERGENCY_RESTART_H -#define _ASM_EMERGENCY_RESTART_H - -#include <asm-generic/emergency-restart.h> - -#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/arch/mips/include/asm/jump_label.h b/arch/mips/include/asm/jump_label.h index 4d6d77ed9b9d..e194f957ca8c 100644 --- a/arch/mips/include/asm/jump_label.h +++ b/arch/mips/include/asm/jump_label.h @@ -22,7 +22,7 @@ static __always_inline bool arch_static_branch(struct static_key *key) { - asm goto("1:\tnop\n\t" + asm_volatile_goto("1:\tnop\n\t" "nop\n\t" ".pushsection __jump_table, \"aw\"\n\t" WORD_INSN " 1b, %l[l_yes], %0\n\t" diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h index 4d6fa0bf1305..32966969f2f9 100644 --- a/arch/mips/include/asm/kvm_host.h +++ b/arch/mips/include/asm/kvm_host.h @@ -27,13 +27,6 @@ #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 -/* Don't support huge pages */ -#define KVM_HPAGE_GFN_SHIFT(x) 0 - -/* We don't currently support large pages. */ -#define KVM_NR_PAGE_SIZES 1 -#define KVM_PAGES_PER_HPAGE(x) 1 - /* Special address that contains the comm page, used for reducing # of traps */ diff --git a/arch/mips/include/asm/local64.h b/arch/mips/include/asm/local64.h deleted file mode 100644 index 36c93b5cc239..000000000000 --- a/arch/mips/include/asm/local64.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/local64.h> diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h deleted file mode 100644 index 6cb30f2b7198..000000000000 --- a/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Platform data definition for Atheros AR933X UART - * - * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _AR933X_UART_PLATFORM_H -#define _AR933X_UART_PLATFORM_H - -struct ar933x_uart_platform_data { - unsigned uartclk; -}; - -#endif /* _AR933X_UART_PLATFORM_H */ diff --git a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h index ddb947e9221f..0089a740e5ae 100644 --- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h @@ -42,8 +42,6 @@ #define cpu_has_mips64r1 0 #define cpu_has_mips64r2 0 -#define cpu_has_dsp 0 -#define cpu_has_dsp2 0 #define cpu_has_mipsmt 0 #define cpu_has_64bits 0 diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 3e11a468cdf8..54f9e84db8ac 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -43,6 +43,8 @@ #include <linux/io.h> #include <linux/irq.h> +#include <asm/cpu.h> + /* cpu pipeline flush */ void static inline au_sync(void) { @@ -140,7 +142,7 @@ static inline int au1xxx_cpu_needs_config_od(void) static inline int alchemy_get_cputype(void) { - switch (read_c0_prid() & 0xffff0000) { + switch (read_c0_prid() & (PRID_OPT_MASK | PRID_COMP_MASK)) { case 0x00030000: return ALCHEMY_CPU_AU1000; break; diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h new file mode 100644 index 000000000000..00867dd05a69 --- /dev/null +++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h @@ -0,0 +1,110 @@ +#ifndef __BCM47XX_BOARD_H +#define __BCM47XX_BOARD_H + +enum bcm47xx_board { + BCM47XX_BOARD_ASUS_RTAC66U, + BCM47XX_BOARD_ASUS_RTN10, + BCM47XX_BOARD_ASUS_RTN10D, + BCM47XX_BOARD_ASUS_RTN10U, + BCM47XX_BOARD_ASUS_RTN12, + BCM47XX_BOARD_ASUS_RTN12B1, + BCM47XX_BOARD_ASUS_RTN12C1, + BCM47XX_BOARD_ASUS_RTN12D1, + BCM47XX_BOARD_ASUS_RTN12HP, + BCM47XX_BOARD_ASUS_RTN15U, + BCM47XX_BOARD_ASUS_RTN16, + BCM47XX_BOARD_ASUS_RTN53, + BCM47XX_BOARD_ASUS_RTN66U, + BCM47XX_BOARD_ASUS_WL300G, + BCM47XX_BOARD_ASUS_WL320GE, + BCM47XX_BOARD_ASUS_WL330GE, + BCM47XX_BOARD_ASUS_WL500GD, + BCM47XX_BOARD_ASUS_WL500GPV1, + BCM47XX_BOARD_ASUS_WL500GPV2, + BCM47XX_BOARD_ASUS_WL500W, + BCM47XX_BOARD_ASUS_WL520GC, + BCM47XX_BOARD_ASUS_WL520GU, + BCM47XX_BOARD_ASUS_WL700GE, + BCM47XX_BOARD_ASUS_WLHDD, + + BCM47XX_BOARD_BELKIN_F7D4301, + + BCM47XX_BOARD_BUFFALO_WBR2_G54, + BCM47XX_BOARD_BUFFALO_WHR2_A54G54, + BCM47XX_BOARD_BUFFALO_WHR_G125, + BCM47XX_BOARD_BUFFALO_WHR_G54S, + BCM47XX_BOARD_BUFFALO_WHR_HP_G54, + BCM47XX_BOARD_BUFFALO_WLA2_G54L, + BCM47XX_BOARD_BUFFALO_WZR_G300N, + BCM47XX_BOARD_BUFFALO_WZR_RS_G54, + BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP, + + BCM47XX_BOARD_CISCO_M10V1, + BCM47XX_BOARD_CISCO_M20V1, + + BCM47XX_BOARD_DELL_TM2300, + + BCM47XX_BOARD_DLINK_DIR130, + BCM47XX_BOARD_DLINK_DIR330, + + BCM47XX_BOARD_HUAWEI_E970, + + BCM47XX_BOARD_LINKSYS_E900V1, + BCM47XX_BOARD_LINKSYS_E1000V1, + BCM47XX_BOARD_LINKSYS_E1000V2, + BCM47XX_BOARD_LINKSYS_E1000V21, + BCM47XX_BOARD_LINKSYS_E1200V2, + BCM47XX_BOARD_LINKSYS_E2000V1, + BCM47XX_BOARD_LINKSYS_E3000V1, + BCM47XX_BOARD_LINKSYS_E3200V1, + BCM47XX_BOARD_LINKSYS_E4200V1, + BCM47XX_BOARD_LINKSYS_WRT150NV1, + BCM47XX_BOARD_LINKSYS_WRT150NV11, + BCM47XX_BOARD_LINKSYS_WRT160NV1, + BCM47XX_BOARD_LINKSYS_WRT160NV3, + BCM47XX_BOARD_LINKSYS_WRT300NV11, + BCM47XX_BOARD_LINKSYS_WRT310NV1, + BCM47XX_BOARD_LINKSYS_WRT310NV2, + BCM47XX_BOARD_LINKSYS_WRT54G3GV2, + BCM47XX_BOARD_LINKSYS_WRT610NV1, + BCM47XX_BOARD_LINKSYS_WRT610NV2, + BCM47XX_BOARD_LINKSYS_WRTSL54GS, + + BCM47XX_BOARD_MOTOROLA_WE800G, + BCM47XX_BOARD_MOTOROLA_WR850GP, + BCM47XX_BOARD_MOTOROLA_WR850GV2V3, + + BCM47XX_BOARD_NETGEAR_WGR614V8, + BCM47XX_BOARD_NETGEAR_WGR614V9, + BCM47XX_BOARD_NETGEAR_WNDR3300, + BCM47XX_BOARD_NETGEAR_WNDR3400V1, + BCM47XX_BOARD_NETGEAR_WNDR3400V2, + BCM47XX_BOARD_NETGEAR_WNDR3400VCNA, + BCM47XX_BOARD_NETGEAR_WNDR3700V3, + BCM47XX_BOARD_NETGEAR_WNDR4000, + BCM47XX_BOARD_NETGEAR_WNDR4500V1, + BCM47XX_BOARD_NETGEAR_WNDR4500V2, + BCM47XX_BOARD_NETGEAR_WNR2000, + BCM47XX_BOARD_NETGEAR_WNR3500L, + BCM47XX_BOARD_NETGEAR_WNR3500U, + BCM47XX_BOARD_NETGEAR_WNR3500V2, + BCM47XX_BOARD_NETGEAR_WNR3500V2VC, + BCM47XX_BOARD_NETGEAR_WNR834BV2, + + BCM47XX_BOARD_PHICOMM_M1, + + BCM47XX_BOARD_SIMPLETECH_SIMPLESHARE, + + BCM47XX_BOARD_ZTE_H218N, + + BCM47XX_BOARD_UNKNOWN, + BCM47XX_BOARD_NO, +}; + +#define BCM47XX_BOARD_MAX_NAME 30 + +void bcm47xx_board_detect(void); +enum bcm47xx_board bcm47xx_board_get(void); +const char *bcm47xx_board_get_name(void); + +#endif /* __BCM47XX_BOARD_H */ diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h index b8e7be8f34dd..36a3fc1aa3ae 100644 --- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h +++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h @@ -48,4 +48,6 @@ static inline void bcm47xx_nvram_parse_macaddr(char *buf, u8 macaddr[6]) printk(KERN_WARNING "Can not parse mac address: %s\n", buf); } +int bcm47xx_nvram_gpio_pin(const char *name); + #endif /* __BCM47XX_NVRAM_H */ diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h index 4e0b6bc1165e..348df49dcc9f 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h @@ -30,4 +30,6 @@ u8 *bcm63xx_nvram_get_name(void); */ int bcm63xx_nvram_get_mac_address(u8 *mac); +int bcm63xx_nvram_get_psi_size(void); + #endif /* BCM63XX_NVRAM_H */ diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h index 47fb247f9663..f9f448650505 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h +++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h @@ -52,23 +52,11 @@ static inline int plat_dma_supported(struct device *dev, u64 mask) return 0; } -static inline void plat_extra_sync_for_device(struct device *dev) -{ - BUG(); -} - static inline int plat_device_is_coherent(struct device *dev) { return 1; } -static inline int plat_dma_mapping_error(struct device *dev, - dma_addr_t dma_addr) -{ - BUG(); - return 0; -} - dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr); phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr); diff --git a/arch/mips/include/asm/mach-cavium-octeon/gpio.h b/arch/mips/include/asm/mach-cavium-octeon/gpio.h new file mode 100644 index 000000000000..34e9f7aabab4 --- /dev/null +++ b/arch/mips/include/asm/mach-cavium-octeon/gpio.h @@ -0,0 +1,21 @@ +#ifndef __ASM_MACH_CAVIUM_OCTEON_GPIO_H +#define __ASM_MACH_CAVIUM_OCTEON_GPIO_H + +#ifdef CONFIG_GPIOLIB +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#else +int gpio_request(unsigned gpio, const char *label); +void gpio_free(unsigned gpio); +int gpio_direction_input(unsigned gpio); +int gpio_direction_output(unsigned gpio, int value); +int gpio_get_value(unsigned gpio); +void gpio_set_value(unsigned gpio, int value); +#endif + +#include <asm-generic/gpio.h> + +#define gpio_to_irq __gpio_to_irq + +#endif /* __ASM_MACH_GENERIC_GPIO_H */ diff --git a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h new file mode 100644 index 000000000000..acce27fd2bb8 --- /dev/null +++ b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h @@ -0,0 +1,87 @@ +/* + * CPU feature overrides for DECstation systems. Two variations + * are generally applicable. + * + * Copyright (C) 2013 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#ifndef __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H + +/* Generic ones first. */ +#define cpu_has_tlb 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_fpu 1 +#define cpu_has_divec 0 +#define cpu_has_prefetch 0 +#define cpu_has_mcheck 0 +#define cpu_has_ejtag 0 +#define cpu_has_mips16 0 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 +#define cpu_has_rixi 0 +#define cpu_has_vtag_icache 0 +#define cpu_has_ic_fills_f_dc 0 +#define cpu_has_pindexed_dcache 0 +#define cpu_has_local_ebase 0 +#define cpu_icache_snoops_remote_store 1 +#define cpu_has_mips_4 0 +#define cpu_has_mips_5 0 +#define cpu_has_mips32r1 0 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 + +/* R3k-specific ones. */ +#ifdef CONFIG_CPU_R3000 +#define cpu_has_4kex 0 +#define cpu_has_3k_cache 1 +#define cpu_has_4k_cache 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 0 +#define cpu_has_watch 0 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_llsc 0 +#define cpu_has_dc_aliases 0 +#define cpu_has_mips_2 0 +#define cpu_has_mips_3 0 +#define cpu_has_nofpuex 1 +#define cpu_has_inclusive_pcaches 0 +#define cpu_dcache_line_size() 4 +#define cpu_icache_line_size() 4 +#define cpu_scache_line_size() 0 +#endif /* CONFIG_CPU_R3000 */ + +/* R4k-specific ones. */ +#ifdef CONFIG_CPU_R4X00 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_32fpr 1 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_vce 1 +#define cpu_has_cache_cdex_p 1 +#define cpu_has_cache_cdex_s 1 +#define cpu_has_llsc 1 +#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) +#define cpu_has_mips_2 1 +#define cpu_has_mips_3 1 +#define cpu_has_nofpuex 0 +#define cpu_has_inclusive_pcaches 1 +#define cpu_dcache_line_size() 16 +#define cpu_icache_line_size() 16 +#define cpu_scache_line_size() 32 +#endif /* CONFIG_CPU_R4X00 */ + +#endif /* __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h index 74cb99257d5b..a9e8f6b62b0b 100644 --- a/arch/mips/include/asm/mach-generic/dma-coherence.h +++ b/arch/mips/include/asm/mach-generic/dma-coherence.h @@ -47,16 +47,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask) return 1; } -static inline void plat_extra_sync_for_device(struct device *dev) -{ -} - -static inline int plat_dma_mapping_error(struct device *dev, - dma_addr_t dma_addr) -{ - return 0; -} - static inline int plat_device_is_coherent(struct device *dev) { #ifdef CONFIG_DMA_COHERENT diff --git a/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h index f4caacd25552..1bcb6421205e 100644 --- a/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h @@ -8,6 +8,8 @@ #ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H +#include <asm/cpu.h> + /* * IP22 with a variety of processors so we can't use defaults for everything. */ diff --git a/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h index 1d2b6ff60d33..d6111aa2e886 100644 --- a/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h @@ -8,6 +8,8 @@ #ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H +#include <asm/cpu.h> + /* * IP27 only comes with R10000 family processors all using the same config */ diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h index 06c441968e6e..4ffddfdb5062 100644 --- a/arch/mips/include/asm/mach-ip27/dma-coherence.h +++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h @@ -58,16 +58,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask) return 1; } -static inline void plat_extra_sync_for_device(struct device *dev) -{ -} - -static inline int plat_dma_mapping_error(struct device *dev, - dma_addr_t dma_addr) -{ - return 0; -} - static inline int plat_device_is_coherent(struct device *dev) { return 1; /* IP27 non-cohernet mode is unsupported */ diff --git a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h index 65e9c856390d..4cec06d133db 100644 --- a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h @@ -9,6 +9,8 @@ #ifndef __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H +#include <asm/cpu.h> + /* * IP28 only comes with R10000 family processors all using the same config */ diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h index 073f0c4760ba..104cfbc3ed63 100644 --- a/arch/mips/include/asm/mach-ip32/dma-coherence.h +++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h @@ -80,17 +80,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask) return 1; } -static inline void plat_extra_sync_for_device(struct device *dev) -{ - return; -} - -static inline int plat_dma_mapping_error(struct device *dev, - dma_addr_t dma_addr) -{ - return 0; -} - static inline int plat_device_is_coherent(struct device *dev) { return 0; /* IP32 is non-cohernet */ diff --git a/arch/mips/include/asm/mach-jazz/dma-coherence.h b/arch/mips/include/asm/mach-jazz/dma-coherence.h index 9fc1e9ad7038..949003ef97b3 100644 --- a/arch/mips/include/asm/mach-jazz/dma-coherence.h +++ b/arch/mips/include/asm/mach-jazz/dma-coherence.h @@ -48,16 +48,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask) return 1; } -static inline void plat_extra_sync_for_device(struct device *dev) -{ -} - -static inline int plat_dma_mapping_error(struct device *dev, - dma_addr_t dma_addr) -{ - return 0; -} - static inline int plat_device_is_coherent(struct device *dev) { return 0; diff --git a/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h new file mode 100644 index 000000000000..096a10072430 --- /dev/null +++ b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h @@ -0,0 +1,58 @@ +/* + * Lantiq FALCON specific CPU feature overrides + * + * Copyright (C) 2013 Thomas Langer, Lantiq Deutschland + * + * This file was derived from: include/asm-mips/cpu-features.h + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 + +#define cpu_has_prefetch 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 + +#define cpu_has_mips16 1 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#define cpu_has_dsp 1 +#define cpu_has_mipsmt 1 + +#define cpu_has_vint 1 +#define cpu_has_veic 1 + +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_64bit_gp_regs 0 +#define cpu_has_64bit_addresses 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 + +#endif /* __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h index e1433055fe98..aeb2c05d6145 100644 --- a/arch/mips/include/asm/mach-loongson/dma-coherence.h +++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h @@ -53,16 +53,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask) return 1; } -static inline void plat_extra_sync_for_device(struct device *dev) -{ -} - -static inline int plat_dma_mapping_error(struct device *dev, - dma_addr_t dma_addr) -{ - return 0; -} - static inline int plat_device_is_coherent(struct device *dev) { return 0; diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h deleted file mode 100644 index b341108d12f1..000000000000 --- a/arch/mips/include/asm/mach-powertv/asic.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _ASM_MACH_POWERTV_ASIC_H -#define _ASM_MACH_POWERTV_ASIC_H - -#include <linux/ioport.h> -#include <linux/platform_device.h> -#include <asm/mach-powertv/asic_regs.h> - -#define DVR_CAPABLE (1<<0) -#define PCIE_CAPABLE (1<<1) -#define FFS_CAPABLE (1<<2) -#define DISPLAY_CAPABLE (1<<3) - -/* Platform Family types - * For compitability, the new value must be added in the end */ -enum family_type { - FAMILY_8500, - FAMILY_8500RNG, - FAMILY_4500, - FAMILY_1500, - FAMILY_8600, - FAMILY_4600, - FAMILY_4600VZA, - FAMILY_8600VZB, - FAMILY_1500VZE, - FAMILY_1500VZF, - FAMILY_8700, - FAMILIES -}; - -/* Register maps for each ASIC */ -extern const struct register_map calliope_register_map; -extern const struct register_map cronus_register_map; -extern const struct register_map gaia_register_map; -extern const struct register_map zeus_register_map; - -extern struct resource dvr_cronus_resources[]; -extern struct resource dvr_gaia_resources[]; -extern struct resource dvr_zeus_resources[]; -extern struct resource non_dvr_calliope_resources[]; -extern struct resource non_dvr_cronus_resources[]; -extern struct resource non_dvr_cronuslite_resources[]; -extern struct resource non_dvr_gaia_resources[]; -extern struct resource non_dvr_vz_calliope_resources[]; -extern struct resource non_dvr_vze_calliope_resources[]; -extern struct resource non_dvr_vzf_calliope_resources[]; -extern struct resource non_dvr_zeus_resources[]; - -extern void powertv_platform_init(void); -extern void platform_alloc_bootmem(void); -extern enum asic_type platform_get_asic(void); -extern enum family_type platform_get_family(void); -extern int platform_supports_dvr(void); -extern int platform_supports_ffs(void); -extern int platform_supports_pcie(void); -extern int platform_supports_display(void); -extern void configure_platform(void); - -/* Platform Resources */ -#define ASIC_RESOURCE_GET_EXISTS 1 -extern struct resource *asic_resource_get(const char *name); -extern void platform_release_memory(void *baddr, int size); - -/* USB configuration */ -struct usb_hcd; /* Forward reference */ -extern void platform_configure_usb_ehci(void); -extern void platform_unconfigure_usb_ehci(void); -extern void platform_configure_usb_ohci(void); -extern void platform_unconfigure_usb_ohci(void); - -/* Resource for ASIC registers */ -extern struct resource asic_resource; -extern int platform_usb_devices_init(struct platform_device **echi_dev, - struct platform_device **ohci_dev); - -/* Reboot Cause */ -extern void set_reboot_cause(char code, unsigned int data, unsigned int data2); -extern void set_locked_reboot_cause(char code, unsigned int data, - unsigned int data2); - -enum sys_reboot_type { - sys_unknown_reboot = 0x00, /* Unknown reboot cause */ - sys_davic_change = 0x01, /* Reboot due to change in DAVIC - * mode */ - sys_user_reboot = 0x02, /* Reboot initiated by user */ - sys_system_reboot = 0x03, /* Reboot initiated by OS */ - sys_trap_reboot = 0x04, /* Reboot due to a CPU trap */ - sys_silent_reboot = 0x05, /* Silent reboot */ - sys_boot_ldr_reboot = 0x06, /* Bootloader reboot */ - sys_power_up_reboot = 0x07, /* Power on bootup. Older - * drivers may report as - * userReboot. */ - sys_code_change = 0x08, /* Reboot to take code change. - * Older drivers may report as - * userReboot. */ - sys_hardware_reset = 0x09, /* HW watchdog or front-panel - * reset button reset. Older - * drivers may report as - * userReboot. */ - sys_watchdogInterrupt = 0x0A /* Pre-watchdog interrupt */ -}; - -#endif /* _ASM_MACH_POWERTV_ASIC_H */ diff --git a/arch/mips/include/asm/mach-powertv/asic_reg_map.h b/arch/mips/include/asm/mach-powertv/asic_reg_map.h deleted file mode 100644 index 20348e817b09..000000000000 --- a/arch/mips/include/asm/mach-powertv/asic_reg_map.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * asic_reg_map.h - * - * A macro-enclosed list of the elements for the register_map structure for - * use in defining and manipulating the structure. - * - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -REGISTER_MAP_ELEMENT(eic_slow0_strt_add) -REGISTER_MAP_ELEMENT(eic_cfg_bits) -REGISTER_MAP_ELEMENT(eic_ready_status) -REGISTER_MAP_ELEMENT(chipver3) -REGISTER_MAP_ELEMENT(chipver2) -REGISTER_MAP_ELEMENT(chipver1) -REGISTER_MAP_ELEMENT(chipver0) -REGISTER_MAP_ELEMENT(uart1_intstat) -REGISTER_MAP_ELEMENT(uart1_inten) -REGISTER_MAP_ELEMENT(uart1_config1) -REGISTER_MAP_ELEMENT(uart1_config2) -REGISTER_MAP_ELEMENT(uart1_divisorhi) -REGISTER_MAP_ELEMENT(uart1_divisorlo) -REGISTER_MAP_ELEMENT(uart1_data) -REGISTER_MAP_ELEMENT(uart1_status) -REGISTER_MAP_ELEMENT(int_stat_3) -REGISTER_MAP_ELEMENT(int_stat_2) -REGISTER_MAP_ELEMENT(int_stat_1) -REGISTER_MAP_ELEMENT(int_stat_0) -REGISTER_MAP_ELEMENT(int_config) -REGISTER_MAP_ELEMENT(int_int_scan) -REGISTER_MAP_ELEMENT(ien_int_3) -REGISTER_MAP_ELEMENT(ien_int_2) -REGISTER_MAP_ELEMENT(ien_int_1) -REGISTER_MAP_ELEMENT(ien_int_0) -REGISTER_MAP_ELEMENT(int_level_3_3) -REGISTER_MAP_ELEMENT(int_level_3_2) -REGISTER_MAP_ELEMENT(int_level_3_1) -REGISTER_MAP_ELEMENT(int_level_3_0) -REGISTER_MAP_ELEMENT(int_level_2_3) -REGISTER_MAP_ELEMENT(int_level_2_2) -REGISTER_MAP_ELEMENT(int_level_2_1) -REGISTER_MAP_ELEMENT(int_level_2_0) -REGISTER_MAP_ELEMENT(int_level_1_3) -REGISTER_MAP_ELEMENT(int_level_1_2) -REGISTER_MAP_ELEMENT(int_level_1_1) -REGISTER_MAP_ELEMENT(int_level_1_0) -REGISTER_MAP_ELEMENT(int_level_0_3) -REGISTER_MAP_ELEMENT(int_level_0_2) -REGISTER_MAP_ELEMENT(int_level_0_1) -REGISTER_MAP_ELEMENT(int_level_0_0) -REGISTER_MAP_ELEMENT(int_docsis_en) -REGISTER_MAP_ELEMENT(mips_pll_setup) -REGISTER_MAP_ELEMENT(fs432x4b4_usb_ctl) -REGISTER_MAP_ELEMENT(test_bus) -REGISTER_MAP_ELEMENT(crt_spare) -REGISTER_MAP_ELEMENT(usb2_ohci_int_mask) -REGISTER_MAP_ELEMENT(usb2_strap) -REGISTER_MAP_ELEMENT(ehci_hcapbase) -REGISTER_MAP_ELEMENT(ohci_hc_revision) -REGISTER_MAP_ELEMENT(bcm1_bs_lmi_steer) -REGISTER_MAP_ELEMENT(usb2_control) -REGISTER_MAP_ELEMENT(usb2_stbus_obc) -REGISTER_MAP_ELEMENT(usb2_stbus_mess_size) -REGISTER_MAP_ELEMENT(usb2_stbus_chunk_size) -REGISTER_MAP_ELEMENT(pcie_regs) -REGISTER_MAP_ELEMENT(tim_ch) -REGISTER_MAP_ELEMENT(tim_cl) -REGISTER_MAP_ELEMENT(gpio_dout) -REGISTER_MAP_ELEMENT(gpio_din) -REGISTER_MAP_ELEMENT(gpio_dir) -REGISTER_MAP_ELEMENT(watchdog) -REGISTER_MAP_ELEMENT(front_panel) -REGISTER_MAP_ELEMENT(misc_clk_ctl1) -REGISTER_MAP_ELEMENT(misc_clk_ctl2) -REGISTER_MAP_ELEMENT(crt_ext_ctl) -REGISTER_MAP_ELEMENT(register_maps) diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h deleted file mode 100644 index 06712abb3e55..000000000000 --- a/arch/mips/include/asm/mach-powertv/asic_regs.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __ASM_MACH_POWERTV_ASIC_H_ -#define __ASM_MACH_POWERTV_ASIC_H_ -#include <linux/io.h> - -/* ASIC types */ -enum asic_type { - ASIC_UNKNOWN, - ASIC_ZEUS, - ASIC_CALLIOPE, - ASIC_CRONUS, - ASIC_CRONUSLITE, - ASIC_GAIA, - ASICS /* Number of supported ASICs */ -}; - -/* hardcoded values read from Chip Version registers */ -#define CRONUS_10 0x0B4C1C20 -#define CRONUS_11 0x0B4C1C21 -#define CRONUSLITE_10 0x0B4C1C40 - -#define NAND_FLASH_BASE 0x03000000 -#define CALLIOPE_IO_BASE 0x08000000 -#define GAIA_IO_BASE 0x09000000 -#define CRONUS_IO_BASE 0x09000000 -#define ZEUS_IO_BASE 0x09000000 - -#define ASIC_IO_SIZE 0x01000000 - -/* Definitions for backward compatibility */ -#define UART1_INTSTAT uart1_intstat -#define UART1_INTEN uart1_inten -#define UART1_CONFIG1 uart1_config1 -#define UART1_CONFIG2 uart1_config2 -#define UART1_DIVISORHI uart1_divisorhi -#define UART1_DIVISORLO uart1_divisorlo -#define UART1_DATA uart1_data -#define UART1_STATUS uart1_status - -/* ASIC register enumeration */ -union register_map_entry { - unsigned long phys; - u32 *virt; -}; - -#define REGISTER_MAP_ELEMENT(x) union register_map_entry x; -struct register_map { -#include <asm/mach-powertv/asic_reg_map.h> -}; -#undef REGISTER_MAP_ELEMENT - -/** - * register_map_offset_phys - add an offset to the physical address - * @map: Pointer to the &struct register_map - * @offset: Value to add - * - * Only adds the base to non-zero physical addresses - */ -static inline void register_map_offset_phys(struct register_map *map, - unsigned long offset) -{ -#define REGISTER_MAP_ELEMENT(x) do { \ - if (map->x.phys != 0) \ - map->x.phys += offset; \ - } while (false); - -#include <asm/mach-powertv/asic_reg_map.h> -#undef REGISTER_MAP_ELEMENT -} - -/** - * register_map_virtualize - Convert ®ister_map to virtual addresses - * @map: Pointer to ®ister_map to virtualize - */ -static inline void register_map_virtualize(struct register_map *map) -{ -#define REGISTER_MAP_ELEMENT(x) do { \ - map->x.virt = (!map->x.phys) ? NULL : \ - UNCAC_ADDR(phys_to_virt(map->x.phys)); \ - } while (false); - -#include <asm/mach-powertv/asic_reg_map.h> -#undef REGISTER_MAP_ELEMENT -} - -extern struct register_map _asic_register_map; -extern unsigned long asic_phy_base; - -/* - * Macros to interface to registers through their ioremapped address - * asic_reg_phys_addr Returns the physical address of the given register - * asic_reg_addr Returns the iomapped virtual address of the given - * register. - */ -#define asic_reg_addr(x) (_asic_register_map.x.virt) -#define asic_reg_phys_addr(x) (virt_to_phys((void *) CAC_ADDR( \ - (unsigned long) asic_reg_addr(x)))) - -/* - * The asic_reg macro is gone. It should be replaced by either asic_read or - * asic_write, as appropriate. - */ - -#define asic_read(x) readl(asic_reg_addr(x)) -#define asic_write(v, x) writel(v, asic_reg_addr(x)) - -extern void asic_irq_init(void); -#endif diff --git a/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h b/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h deleted file mode 100644 index 58c76ec32a19..000000000000 --- a/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2010 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _ASM_MACH_POWERTV_CPU_FEATURE_OVERRIDES_H_ -#define _ASM_MACH_POWERTV_CPU_FEATURE_OVERRIDES_H_ -#define cpu_has_tlb 1 -#define cpu_has_4kex 1 -#define cpu_has_3k_cache 0 -#define cpu_has_4k_cache 1 -#define cpu_has_tx39_cache 0 -#define cpu_has_fpu 0 -#define cpu_has_counter 1 -#define cpu_has_watch 1 -#define cpu_has_divec 1 -#define cpu_has_vce 0 -#define cpu_has_cache_cdex_p 0 -#define cpu_has_cache_cdex_s 0 -#define cpu_has_mcheck 1 -#define cpu_has_ejtag 1 -#define cpu_has_llsc 1 -#define cpu_has_mips16 0 -#define cpu_has_mdmx 0 -#define cpu_has_mips3d 0 -#define cpu_has_smartmips 0 -#define cpu_has_vtag_icache 0 -#define cpu_has_dc_aliases 0 -#define cpu_has_ic_fills_f_dc 0 -#define cpu_has_mips32r1 0 -#define cpu_has_mips32r2 1 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 0 -#define cpu_has_dsp 0 -#define cpu_has_dsp2 0 -#define cpu_has_mipsmt 0 -#define cpu_has_userlocal 0 -#define cpu_has_nofpuex 0 -#define cpu_has_64bits 0 -#define cpu_has_64bit_zero_reg 0 -#define cpu_has_vint 1 -#define cpu_has_veic 1 -#define cpu_has_inclusive_pcaches 0 - -#define cpu_dcache_line_size() 32 -#define cpu_icache_line_size() 32 -#endif diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h deleted file mode 100644 index f8316720a218..000000000000 --- a/arch/mips/include/asm/mach-powertv/dma-coherence.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Version from mach-generic modified to support PowerTV port - * Portions Copyright (C) 2009 Cisco Systems, Inc. - * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org> - * - */ - -#ifndef __ASM_MACH_POWERTV_DMA_COHERENCE_H -#define __ASM_MACH_POWERTV_DMA_COHERENCE_H - -#include <linux/sched.h> -#include <linux/device.h> -#include <asm/mach-powertv/asic.h> - -static inline bool is_kseg2(void *addr) -{ - return (unsigned long)addr >= KSEG2; -} - -static inline unsigned long virt_to_phys_from_pte(void *addr) -{ - pgd_t *pgd; - pud_t *pud; - pmd_t *pmd; - pte_t *ptep, pte; - - unsigned long virt_addr = (unsigned long)addr; - unsigned long phys_addr = 0UL; - - /* get the page global directory. */ - pgd = pgd_offset_k(virt_addr); - - if (!pgd_none(*pgd)) { - /* get the page upper directory */ - pud = pud_offset(pgd, virt_addr); - if (!pud_none(*pud)) { - /* get the page middle directory */ - pmd = pmd_offset(pud, virt_addr); - if (!pmd_none(*pmd)) { - /* get a pointer to the page table entry */ - ptep = pte_offset(pmd, virt_addr); - pte = *ptep; - /* check for a valid page */ - if (pte_present(pte)) { - /* get the physical address the page is - * referring to */ - phys_addr = (unsigned long) - page_to_phys(pte_page(pte)); - /* add the offset within the page */ - phys_addr |= (virt_addr & ~PAGE_MASK); - } - } - } - } - - return phys_addr; -} - -static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, - size_t size) -{ - if (is_kseg2(addr)) - return phys_to_dma(virt_to_phys_from_pte(addr)); - else - return phys_to_dma(virt_to_phys(addr)); -} - -static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, - struct page *page) -{ - return phys_to_dma(page_to_phys(page)); -} - -static inline unsigned long plat_dma_addr_to_phys(struct device *dev, - dma_addr_t dma_addr) -{ - return dma_to_phys(dma_addr); -} - -static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, - size_t size, enum dma_data_direction direction) -{ -} - -static inline int plat_dma_supported(struct device *dev, u64 mask) -{ - /* - * we fall back to GFP_DMA when the mask isn't all 1s, - * so we can't guarantee allocations that must be - * within a tighter range than GFP_DMA.. - */ - if (mask < DMA_BIT_MASK(24)) - return 0; - - return 1; -} - -static inline void plat_extra_sync_for_device(struct device *dev) -{ -} - -static inline int plat_dma_mapping_error(struct device *dev, - dma_addr_t dma_addr) -{ - return 0; -} - -static inline int plat_device_is_coherent(struct device *dev) -{ - return 0; -} - -#endif /* __ASM_MACH_POWERTV_DMA_COHERENCE_H */ diff --git a/arch/mips/include/asm/mach-powertv/interrupts.h b/arch/mips/include/asm/mach-powertv/interrupts.h deleted file mode 100644 index 6c463be62156..000000000000 --- a/arch/mips/include/asm/mach-powertv/interrupts.h +++ /dev/null @@ -1,253 +0,0 @@ -/* - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_ -#define _ASM_MACH_POWERTV_INTERRUPTS_H_ - -/* - * Defines for all of the interrupt lines - */ - -/* Definitions for backward compatibility */ -#define kIrq_Uart1 irq_uart1 - -#define ibase 0 - -/*------------- Register: int_stat_3 */ -/* 126 unused (bit 31) */ -#define irq_asc2video (ibase+126) /* ASC 2 Video Interrupt */ -#define irq_asc1video (ibase+125) /* ASC 1 Video Interrupt */ -#define irq_comms_block_wd (ibase+124) /* ASC 1 Video Interrupt */ -#define irq_fdma_mailbox (ibase+123) /* FDMA Mailbox Output */ -#define irq_fdma_gp (ibase+122) /* FDMA GP Output */ -#define irq_mips_pic (ibase+121) /* MIPS Performance Counter - * Interrupt */ -#define irq_mips_timer (ibase+120) /* MIPS Timer Interrupt */ -#define irq_memory_protect (ibase+119) /* Memory Protection Interrupt - * -- Ored by glue logic inside - * SPARC ILC (see - * INT_MEM_PROT_STAT, below, - * for individual interrupts) - */ -/* 118 unused (bit 22) */ -#define irq_sbag (ibase+117) /* SBAG Interrupt -- Ored by - * glue logic inside SPARC ILC - * (see INT_SBAG_STAT, below, - * for individual interrupts) */ -#define irq_qam_b_fec (ibase+116) /* QAM B FEC Interrupt */ -#define irq_qam_a_fec (ibase+115) /* QAM A FEC Interrupt */ -/* 114 unused (bit 18) */ -#define irq_mailbox (ibase+113) /* Mailbox Debug Interrupt -- - * Ored by glue logic inside - * SPARC ILC (see - * INT_MAILBOX_STAT, below, for - * individual interrupts) */ -#define irq_fuse_stat1 (ibase+112) /* Fuse Status 1 */ -#define irq_fuse_stat2 (ibase+111) /* Fuse Status 2 */ -#define irq_fuse_stat3 (ibase+110) /* Blitter Interrupt / Fuse - * Status 3 */ -#define irq_blitter (ibase+110) /* Blitter Interrupt / Fuse - * Status 3 */ -#define irq_avc1_pp0 (ibase+109) /* AVC Decoder #1 PP0 - * Interrupt */ -#define irq_avc1_pp1 (ibase+108) /* AVC Decoder #1 PP1 - * Interrupt */ -#define irq_avc1_mbe (ibase+107) /* AVC Decoder #1 MBE - * Interrupt */ -#define irq_avc2_pp0 (ibase+106) /* AVC Decoder #2 PP0 - * Interrupt */ -#define irq_avc2_pp1 (ibase+105) /* AVC Decoder #2 PP1 - * Interrupt */ -#define irq_avc2_mbe (ibase+104) /* AVC Decoder #2 MBE - * Interrupt */ -#define irq_zbug_spi (ibase+103) /* Zbug SPI Slave Interrupt */ -#define irq_qam_mod2 (ibase+102) /* QAM Modulator 2 DMA - * Interrupt */ -#define irq_ir_rx (ibase+101) /* IR RX 2 Interrupt */ -#define irq_aud_dsp2 (ibase+100) /* Audio DSP #2 Interrupt */ -#define irq_aud_dsp1 (ibase+99) /* Audio DSP #1 Interrupt */ -#define irq_docsis (ibase+98) /* DOCSIS Debug Interrupt */ -#define irq_sd_dvp1 (ibase+97) /* SD DVP #1 Interrupt */ -#define irq_sd_dvp2 (ibase+96) /* SD DVP #2 Interrupt */ -/*------------- Register: int_stat_2 */ -#define irq_hd_dvp (ibase+95) /* HD DVP Interrupt */ -#define kIrq_Prewatchdog (ibase+94) /* watchdog Pre-Interrupt */ -#define irq_timer2 (ibase+93) /* Programmable Timer - * Interrupt 2 */ -#define irq_1394 (ibase+92) /* 1394 Firewire Interrupt */ -#define irq_usbohci (ibase+91) /* USB 2.0 OHCI Interrupt */ -#define irq_usbehci (ibase+90) /* USB 2.0 EHCI Interrupt */ -#define irq_pciexp (ibase+89) /* PCI Express 0 Interrupt */ -#define irq_pciexp0 (ibase+89) /* PCI Express 0 Interrupt */ -#define irq_afe1 (ibase+88) /* AFE 1 Interrupt */ -#define irq_sata (ibase+87) /* SATA 1 Interrupt */ -#define irq_sata1 (ibase+87) /* SATA 1 Interrupt */ -#define irq_dtcp (ibase+86) /* DTCP Interrupt */ -#define irq_pciexp1 (ibase+85) /* PCI Express 1 Interrupt */ -/* 84 unused (bit 20) */ -/* 83 unused (bit 19) */ -/* 82 unused (bit 18) */ -#define irq_sata2 (ibase+81) /* SATA2 Interrupt */ -#define irq_uart2 (ibase+80) /* UART2 Interrupt */ -#define irq_legacy_usb (ibase+79) /* Legacy USB Host ISR (1.1 - * Host module) */ -#define irq_pod (ibase+78) /* POD Interrupt */ -#define irq_slave_usb (ibase+77) /* Slave USB */ -#define irq_denc1 (ibase+76) /* DENC #1 VTG Interrupt */ -#define irq_vbi_vtg (ibase+75) /* VBI VTG Interrupt */ -#define irq_afe2 (ibase+74) /* AFE 2 Interrupt */ -#define irq_denc2 (ibase+73) /* DENC #2 VTG Interrupt */ -#define irq_asc2 (ibase+72) /* ASC #2 Interrupt */ -#define irq_asc1 (ibase+71) /* ASC #1 Interrupt */ -#define irq_mod_dma (ibase+70) /* Modulator DMA Interrupt */ -#define irq_byte_eng1 (ibase+69) /* Byte Engine Interrupt [1] */ -#define irq_byte_eng0 (ibase+68) /* Byte Engine Interrupt [0] */ -/* 67 unused (bit 03) */ -/* 66 unused (bit 02) */ -/* 65 unused (bit 01) */ -/* 64 unused (bit 00) */ -/*------------- Register: int_stat_1 */ -/* 63 unused (bit 31) */ -/* 62 unused (bit 30) */ -/* 61 unused (bit 29) */ -/* 60 unused (bit 28) */ -/* 59 unused (bit 27) */ -/* 58 unused (bit 26) */ -/* 57 unused (bit 25) */ -/* 56 unused (bit 24) */ -#define irq_buf_dma_mem2mem (ibase+55) /* BufDMA Memory to Memory - * Interrupt */ -#define irq_buf_dma_usbtransmit (ibase+54) /* BufDMA USB Transmit - * Interrupt */ -#define irq_buf_dma_qpskpodtransmit (ibase+53) /* BufDMA QPSK/POD Tramsit - * Interrupt */ -#define irq_buf_dma_transmit_error (ibase+52) /* BufDMA Transmit Error - * Interrupt */ -#define irq_buf_dma_usbrecv (ibase+51) /* BufDMA USB Receive - * Interrupt */ -#define irq_buf_dma_qpskpodrecv (ibase+50) /* BufDMA QPSK/POD Receive - * Interrupt */ -#define irq_buf_dma_recv_error (ibase+49) /* BufDMA Receive Error - * Interrupt */ -#define irq_qamdma_transmit_play (ibase+48) /* QAMDMA Transmit/Play - * Interrupt */ -#define irq_qamdma_transmit_error (ibase+47) /* QAMDMA Transmit Error - * Interrupt */ -#define irq_qamdma_recv2high (ibase+46) /* QAMDMA Receive 2 High - * (Chans 63-32) */ -#define irq_qamdma_recv2low (ibase+45) /* QAMDMA Receive 2 Low - * (Chans 31-0) */ -#define irq_qamdma_recv1high (ibase+44) /* QAMDMA Receive 1 High - * (Chans 63-32) */ -#define irq_qamdma_recv1low (ibase+43) /* QAMDMA Receive 1 Low - * (Chans 31-0) */ -#define irq_qamdma_recv_error (ibase+42) /* QAMDMA Receive Error - * Interrupt */ -#define irq_mpegsplice (ibase+41) /* MPEG Splice Interrupt */ -#define irq_deinterlace_rdy (ibase+40) /* Deinterlacer Frame Ready - * Interrupt */ -#define irq_ext_in0 (ibase+39) /* External Interrupt irq_in0 */ -#define irq_gpio3 (ibase+38) /* GP I/O IRQ 3 - From GP I/O - * Module */ -#define irq_gpio2 (ibase+37) /* GP I/O IRQ 2 - From GP I/O - * Module (ABE_intN) */ -#define irq_pcrcmplt1 (ibase+36) /* PCR Capture Complete or - * Discontinuity 1 */ -#define irq_pcrcmplt2 (ibase+35) /* PCR Capture Complete or - * Discontinuity 2 */ -#define irq_parse_peierr (ibase+34) /* PID Parser Error Detect - * (PEI) */ -#define irq_parse_cont_err (ibase+33) /* PID Parser continuity error - * detect */ -#define irq_ds1framer (ibase+32) /* DS1 Framer Interrupt */ -/*------------- Register: int_stat_0 */ -#define irq_gpio1 (ibase+31) /* GP I/O IRQ 1 - From GP I/O - * Module */ -#define irq_gpio0 (ibase+30) /* GP I/O IRQ 0 - From GP I/O - * Module */ -#define irq_qpsk_out_aloha (ibase+29) /* QPSK Output Slotted Aloha - * (chan 3) Transmission - * Completed OK */ -#define irq_qpsk_out_tdma (ibase+28) /* QPSK Output TDMA (chan 2) - * Transmission Completed OK */ -#define irq_qpsk_out_reserve (ibase+27) /* QPSK Output Reservation - * (chan 1) Transmission - * Completed OK */ -#define irq_qpsk_out_aloha_err (ibase+26) /* QPSK Output Slotted Aloha - * (chan 3)Transmission - * completed with Errors. */ -#define irq_qpsk_out_tdma_err (ibase+25) /* QPSK Output TDMA (chan 2) - * Transmission completed with - * Errors. */ -#define irq_qpsk_out_rsrv_err (ibase+24) /* QPSK Output Reservation - * (chan 1) Transmission - * completed with Errors */ -#define irq_aloha_fail (ibase+23) /* Unsuccessful Resend of Aloha - * for N times. Aloha retry - * timeout for channel 3. */ -#define irq_timer1 (ibase+22) /* Programmable Timer - * Interrupt */ -#define irq_keyboard (ibase+21) /* Keyboard Module Interrupt */ -#define irq_i2c (ibase+20) /* I2C Module Interrupt */ -#define irq_spi (ibase+19) /* SPI Module Interrupt */ -#define irq_irblaster (ibase+18) /* IR Blaster Interrupt */ -#define irq_splice_detect (ibase+17) /* PID Key Change Interrupt or - * Splice Detect Interrupt */ -#define irq_se_micro (ibase+16) /* Secure Micro I/F Module - * Interrupt */ -#define irq_uart1 (ibase+15) /* UART Interrupt */ -#define irq_irrecv (ibase+14) /* IR Receiver Interrupt */ -#define irq_host_int1 (ibase+13) /* Host-to-Host Interrupt 1 */ -#define irq_host_int0 (ibase+12) /* Host-to-Host Interrupt 0 */ -#define irq_qpsk_hecerr (ibase+11) /* QPSK HEC Error Interrupt */ -#define irq_qpsk_crcerr (ibase+10) /* QPSK AAL-5 CRC Error - * Interrupt */ -/* 9 unused (bit 09) */ -/* 8 unused (bit 08) */ -#define irq_psicrcerr (ibase+7) /* QAM PSI CRC Error - * Interrupt */ -#define irq_psilength_err (ibase+6) /* QAM PSI Length Error - * Interrupt */ -#define irq_esfforward (ibase+5) /* ESF Interrupt Mark From - * Forward Path Reference - - * every 3ms when forward Mbits - * and forward slot control - * bytes are updated. */ -#define irq_esfreverse (ibase+4) /* ESF Interrupt Mark from - * Reverse Path Reference - - * delayed from forward mark by - * the ranging delay plus a - * fixed amount. When reverse - * Mbits and reverse slot - * control bytes are updated. - * Occurs every 3ms for 3.0M and - * 1.554 M upstream rates and - * every 6 ms for 256K upstream - * rate. */ -#define irq_aloha_timeout (ibase+3) /* Slotted-Aloha timeout on - * Channel 1. */ -#define irq_reservation (ibase+2) /* Partial (or Incremental) - * Reservation Message Completed - * or Slotted aloha verify for - * channel 1. */ -#define irq_aloha3 (ibase+1) /* Slotted-Aloha Message Verify - * Interrupt or Reservation - * increment completed for - * channel 3. */ -#define irq_mpeg_d (ibase+0) /* MPEG Decoder Interrupt */ -#endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */ diff --git a/arch/mips/include/asm/mach-powertv/ioremap.h b/arch/mips/include/asm/mach-powertv/ioremap.h deleted file mode 100644 index c86ef094ec37..000000000000 --- a/arch/mips/include/asm/mach-powertv/ioremap.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * Portions Copyright (C) Cisco Systems, Inc. - */ -#ifndef __ASM_MACH_POWERTV_IOREMAP_H -#define __ASM_MACH_POWERTV_IOREMAP_H - -#include <linux/types.h> -#include <linux/log2.h> -#include <linux/compiler.h> - -#include <asm/pgtable-bits.h> -#include <asm/addrspace.h> - -/* We're going to mess with bits, so get sizes */ -#define IOR_BPC 8 /* Bits per char */ -#define IOR_PHYS_BITS (IOR_BPC * sizeof(phys_addr_t)) -#define IOR_DMA_BITS (IOR_BPC * sizeof(dma_addr_t)) - -/* - * Define the granularity of physical/DMA mapping in terms of the number - * of bits that defines the offset within a grain. These will be the - * least significant bits of the address. The rest of a physical or DMA - * address will be used to index into an appropriate table to find the - * offset to add to the address to yield the corresponding DMA or physical - * address, respectively. - */ -#define IOR_LSBITS 22 /* Bits in a grain */ - -/* - * Compute the number of most significant address bits after removing those - * used for the offset within a grain and then compute the number of table - * entries for the conversion. - */ -#define IOR_PHYS_MSBITS (IOR_PHYS_BITS - IOR_LSBITS) -#define IOR_NUM_PHYS_TO_DMA ((phys_addr_t) 1 << IOR_PHYS_MSBITS) - -#define IOR_DMA_MSBITS (IOR_DMA_BITS - IOR_LSBITS) -#define IOR_NUM_DMA_TO_PHYS ((dma_addr_t) 1 << IOR_DMA_MSBITS) - -/* - * Define data structures used as elements in the arrays for the conversion - * between physical and DMA addresses. We do some slightly fancy math to - * compute the width of the offset element of the conversion tables so - * that we can have the smallest conversion tables. Next, round up the - * sizes to the next higher power of two, i.e. the offset element will have - * 8, 16, 32, 64, etc. bits. This eliminates the need to mask off any - * bits. Finally, we compute a shift value that puts the most significant - * bits of the offset into the most significant bits of the offset element. - * This makes it more efficient on processors without barrel shifters and - * easier to see the values if the conversion table is dumped in binary. - */ -#define _IOR_OFFSET_WIDTH(n) (1 << order_base_2(n)) -#define IOR_OFFSET_WIDTH(n) \ - (_IOR_OFFSET_WIDTH(n) < 8 ? 8 : _IOR_OFFSET_WIDTH(n)) - -#define IOR_PHYS_OFFSET_BITS IOR_OFFSET_WIDTH(IOR_PHYS_MSBITS) -#define IOR_PHYS_SHIFT (IOR_PHYS_BITS - IOR_PHYS_OFFSET_BITS) - -#define IOR_DMA_OFFSET_BITS IOR_OFFSET_WIDTH(IOR_DMA_MSBITS) -#define IOR_DMA_SHIFT (IOR_DMA_BITS - IOR_DMA_OFFSET_BITS) - -struct ior_phys_to_dma { - dma_addr_t offset:IOR_DMA_OFFSET_BITS __packed - __aligned((IOR_DMA_OFFSET_BITS / IOR_BPC)); -}; - -struct ior_dma_to_phys { - dma_addr_t offset:IOR_PHYS_OFFSET_BITS __packed - __aligned((IOR_PHYS_OFFSET_BITS / IOR_BPC)); -}; - -extern struct ior_phys_to_dma _ior_phys_to_dma[IOR_NUM_PHYS_TO_DMA]; -extern struct ior_dma_to_phys _ior_dma_to_phys[IOR_NUM_DMA_TO_PHYS]; - -static inline dma_addr_t _phys_to_dma_offset_raw(phys_addr_t phys) -{ - return (dma_addr_t)_ior_phys_to_dma[phys >> IOR_LSBITS].offset; -} - -static inline dma_addr_t _dma_to_phys_offset_raw(dma_addr_t dma) -{ - return (dma_addr_t)_ior_dma_to_phys[dma >> IOR_LSBITS].offset; -} - -/* These are not portable and should not be used in drivers. Drivers should - * be using ioremap() and friends to map physical addresses to virtual - * addresses and dma_map*() and friends to map virtual addresses into DMA - * addresses and back. - */ -static inline dma_addr_t phys_to_dma(phys_addr_t phys) -{ - return phys + (_phys_to_dma_offset_raw(phys) << IOR_PHYS_SHIFT); -} - -static inline phys_addr_t dma_to_phys(dma_addr_t dma) -{ - return dma + (_dma_to_phys_offset_raw(dma) << IOR_DMA_SHIFT); -} - -extern void ioremap_add_map(dma_addr_t phys, phys_addr_t alias, - dma_addr_t size); - -/* - * Allow physical addresses to be fixed up to help peripherals located - * outside the low 32-bit range -- generic pass-through version. - */ -static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) -{ - return phys_addr; -} - -/* - * Handle the special case of addresses the area aliased into the first - * 512 MiB of the processor's physical address space. These turn into either - * kseg0 or kseg1 addresses, depending on flags. - */ -static inline void __iomem *plat_ioremap(phys_t start, unsigned long size, - unsigned long flags) -{ - phys_addr_t start_offset; - void __iomem *result = NULL; - - /* Start by checking to see whether this is an aliased address */ - start_offset = _dma_to_phys_offset_raw(start); - - /* - * If: - * o the memory is aliased into the first 512 MiB, and - * o the start and end are in the same RAM bank, and - * o we don't have a zero size or wrap around, and - * o we are supposed to create an uncached mapping, - * handle this is a kseg0 or kseg1 address - */ - if (start_offset != 0) { - phys_addr_t last; - dma_addr_t dma_to_phys_offset; - - last = start + size - 1; - dma_to_phys_offset = - _dma_to_phys_offset_raw(last) << IOR_DMA_SHIFT; - - if (dma_to_phys_offset == start_offset && - size != 0 && start <= last) { - phys_t adjusted_start; - adjusted_start = start + start_offset; - if (flags == _CACHE_UNCACHED) - result = (void __iomem *) (unsigned long) - CKSEG1ADDR(adjusted_start); - else - result = (void __iomem *) (unsigned long) - CKSEG0ADDR(adjusted_start); - } - } - - return result; -} - -static inline int plat_iounmap(const volatile void __iomem *addr) -{ - return 0; -} -#endif /* __ASM_MACH_POWERTV_IOREMAP_H */ diff --git a/arch/mips/include/asm/mach-powertv/irq.h b/arch/mips/include/asm/mach-powertv/irq.h deleted file mode 100644 index 4bd5d0c61a91..000000000000 --- a/arch/mips/include/asm/mach-powertv/irq.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _ASM_MACH_POWERTV_IRQ_H -#define _ASM_MACH_POWERTV_IRQ_H -#include <asm/mach-powertv/interrupts.h> - -#define MIPS_CPU_IRQ_BASE ibase -#define NR_IRQS 127 -#endif diff --git a/arch/mips/include/asm/mach-powertv/powertv-clock.h b/arch/mips/include/asm/mach-powertv/powertv-clock.h deleted file mode 100644 index 6f3e9a0fcf8c..000000000000 --- a/arch/mips/include/asm/mach-powertv/powertv-clock.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -/* - * Local definitions for the powertv PCI code - */ - -#ifndef _POWERTV_PCI_POWERTV_PCI_H_ -#define _POWERTV_PCI_POWERTV_PCI_H_ -extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); -extern int asic_pcie_init(void); -extern int asic_pcie_init(void); - -extern int log_level; -#endif diff --git a/arch/mips/include/asm/mach-powertv/war.h b/arch/mips/include/asm/mach-powertv/war.h deleted file mode 100644 index c5651c8e58d1..000000000000 --- a/arch/mips/include/asm/mach-powertv/war.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * This version for the PowerTV platform copied from the Malta version. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - * Portions copyright (C) 2009 Cisco Systems, Inc. - */ -#ifndef __ASM_MACH_POWERTV_WAR_H -#define __ASM_MACH_POWERTV_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 1 -#define MIPS_CACHE_SYNC_WAR 1 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 1 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MACH_POWERTV_WAR_H */ diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h index 9809972ea882..6f9b24f51157 100644 --- a/arch/mips/include/asm/mach-ralink/mt7620.h +++ b/arch/mips/include/asm/mach-ralink/mt7620.h @@ -20,6 +20,8 @@ #define SYSC_REG_CHIP_REV 0x0c #define SYSC_REG_SYSTEM_CONFIG0 0x10 #define SYSC_REG_SYSTEM_CONFIG1 0x14 +#define SYSC_REG_CLKCFG0 0x2c +#define SYSC_REG_CPU_SYS_CLKCFG 0x3c #define SYSC_REG_CPLL_CONFIG0 0x54 #define SYSC_REG_CPLL_CONFIG1 0x58 @@ -29,20 +31,42 @@ #define MT7620A_CHIP_NAME0 0x3637544d #define MT7620A_CHIP_NAME1 0x20203032 +#define SYSCFG0_XTAL_FREQ_SEL BIT(6) + #define CHIP_REV_PKG_MASK 0x1 #define CHIP_REV_PKG_SHIFT 16 #define CHIP_REV_VER_MASK 0xf #define CHIP_REV_VER_SHIFT 8 #define CHIP_REV_ECO_MASK 0xf -#define CPLL_SW_CONFIG_SHIFT 31 -#define CPLL_SW_CONFIG_MASK 0x1 -#define CPLL_CPU_CLK_SHIFT 24 -#define CPLL_CPU_CLK_MASK 0x1 -#define CPLL_MULT_RATIO_SHIFT 16 -#define CPLL_MULT_RATIO 0x7 -#define CPLL_DIV_RATIO_SHIFT 10 -#define CPLL_DIV_RATIO 0x3 +#define CLKCFG0_PERI_CLK_SEL BIT(4) + +#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16 +#define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf +#define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */ +#define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */ +#define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */ +#define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */ +#define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */ +#define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */ +#define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */ +#define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */ +#define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */ +#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8 +#define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f +#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0 +#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f + +#define CPLL_CFG0_SW_CFG BIT(31) +#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16 +#define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7 +#define CPLL_CFG0_LC_CURFCK BIT(15) +#define CPLL_CFG0_BYPASS_REF_CLK BIT(14) +#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10 +#define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3 + +#define CPLL_CFG1_CPU_AUX1 BIT(25) +#define CPLL_CFG1_CPU_AUX0 BIT(24) #define SYSCFG0_DRAM_TYPE_MASK 0x3 #define SYSCFG0_DRAM_TYPE_SHIFT 4 diff --git a/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h new file mode 100644 index 000000000000..f7bb8cfc5eb1 --- /dev/null +++ b/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h @@ -0,0 +1,57 @@ +/* + * Ralink MT7620 specific CPU feature overrides + * + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This file was derived from: include/asm-mips/cpu-features.h + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef _MT7620_CPU_FEATURE_OVERRIDES_H +#define _MT7620_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 + +#define cpu_has_prefetch 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 + +#define cpu_has_mips16 1 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#define cpu_has_dsp 1 +#define cpu_has_dsp2 0 +#define cpu_has_mipsmt 0 + +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_64bit_gp_regs 0 +#define cpu_has_64bit_addresses 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 + +#endif /* _MT7620_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mips-boards/piix4.h b/arch/mips/include/asm/mips-boards/piix4.h index a02596cf1abd..e33227998713 100644 --- a/arch/mips/include/asm/mips-boards/piix4.h +++ b/arch/mips/include/asm/mips-boards/piix4.h @@ -1,6 +1,7 @@ /* * Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2013 Imagination Technologies Ltd. * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as @@ -20,61 +21,26 @@ #ifndef __ASM_MIPS_BOARDS_PIIX4_H #define __ASM_MIPS_BOARDS_PIIX4_H -/************************************************************************ - * IO register offsets - ************************************************************************/ -#define PIIX4_ICTLR1_ICW1 0x20 -#define PIIX4_ICTLR1_ICW2 0x21 -#define PIIX4_ICTLR1_ICW3 0x21 -#define PIIX4_ICTLR1_ICW4 0x21 -#define PIIX4_ICTLR2_ICW1 0xa0 -#define PIIX4_ICTLR2_ICW2 0xa1 -#define PIIX4_ICTLR2_ICW3 0xa1 -#define PIIX4_ICTLR2_ICW4 0xa1 -#define PIIX4_ICTLR1_OCW1 0x21 -#define PIIX4_ICTLR1_OCW2 0x20 -#define PIIX4_ICTLR1_OCW3 0x20 -#define PIIX4_ICTLR1_OCW4 0x20 -#define PIIX4_ICTLR2_OCW1 0xa1 -#define PIIX4_ICTLR2_OCW2 0xa0 -#define PIIX4_ICTLR2_OCW3 0xa0 -#define PIIX4_ICTLR2_OCW4 0xa0 - - -/************************************************************************ - * Register encodings. - ************************************************************************/ -#define PIIX4_OCW2_NSEOI (0x1 << 5) -#define PIIX4_OCW2_SEOI (0x3 << 5) -#define PIIX4_OCW2_RNSEOI (0x5 << 5) -#define PIIX4_OCW2_RAEOIS (0x4 << 5) -#define PIIX4_OCW2_RAEOIC (0x0 << 5) -#define PIIX4_OCW2_RSEOI (0x7 << 5) -#define PIIX4_OCW2_SP (0x6 << 5) -#define PIIX4_OCW2_NOP (0x2 << 5) - -#define PIIX4_OCW2_SEL (0x0 << 3) - -#define PIIX4_OCW2_ILS_0 0 -#define PIIX4_OCW2_ILS_1 1 -#define PIIX4_OCW2_ILS_2 2 -#define PIIX4_OCW2_ILS_3 3 -#define PIIX4_OCW2_ILS_4 4 -#define PIIX4_OCW2_ILS_5 5 -#define PIIX4_OCW2_ILS_6 6 -#define PIIX4_OCW2_ILS_7 7 -#define PIIX4_OCW2_ILS_8 0 -#define PIIX4_OCW2_ILS_9 1 -#define PIIX4_OCW2_ILS_10 2 -#define PIIX4_OCW2_ILS_11 3 -#define PIIX4_OCW2_ILS_12 4 -#define PIIX4_OCW2_ILS_13 5 -#define PIIX4_OCW2_ILS_14 6 -#define PIIX4_OCW2_ILS_15 7 - -#define PIIX4_OCW3_SEL (0x1 << 3) - -#define PIIX4_OCW3_IRR 0x2 -#define PIIX4_OCW3_ISR 0x3 +/* PIRQX Route Control */ +#define PIIX4_FUNC0_PIRQRC 0x60 +#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE (1 << 7) +#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK 0xf +#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX 16 +/* Top Of Memory */ +#define PIIX4_FUNC0_TOM 0x69 +#define PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK 0xf0 +/* Deterministic Latency Control */ +#define PIIX4_FUNC0_DLC 0x82 +#define PIIX4_FUNC0_DLC_USBPR_EN (1 << 2) +#define PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN (1 << 1) +#define PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN (1 << 0) + +/* IDE Timing */ +#define PIIX4_FUNC1_IDETIM_PRIMARY_LO 0x40 +#define PIIX4_FUNC1_IDETIM_PRIMARY_HI 0x41 +#define PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN (1 << 7) +#define PIIX4_FUNC1_IDETIM_SECONDARY_LO 0x42 +#define PIIX4_FUNC1_IDETIM_SECONDARY_HI 0x43 +#define PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN (1 << 7) #endif /* __ASM_MIPS_BOARDS_PIIX4_H */ diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index fed1c3e9b486..e0331414c7d6 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -603,6 +603,13 @@ #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) +#define MIPS_CONF5_NF (_ULCAST_(1) << 0) +#define MIPS_CONF5_UFR (_ULCAST_(1) << 2) +#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27) +#define MIPS_CONF5_EVA (_ULCAST_(1) << 28) +#define MIPS_CONF5_CV (_ULCAST_(1) << 29) +#define MIPS_CONF5_K (_ULCAST_(1) << 30) + #define MIPS_CONF6_SYND (_ULCAST_(1) << 13) #define MIPS_CONF7_WII (_ULCAST_(1) << 31) diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index 3b29079b5424..e277bbad2871 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -24,21 +24,21 @@ #endif /* SMTC */ #include <asm-generic/mm_hooks.h> -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT - #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ do { \ extern void tlbmiss_handler_setup_pgd(unsigned long); \ tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \ } while (0) +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT #define TLBMISS_HANDLER_SETUP() \ do { \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ - write_c0_xcontext((unsigned long) smp_processor_id() << 51); \ + write_c0_xcontext((unsigned long) smp_processor_id() << \ + SMP_CPUID_REGSHIFT); \ } while (0) -#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ +#else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ /* * For the fast tlb miss handlers, we keep a per cpu array of pointers @@ -47,21 +47,11 @@ do { \ */ extern unsigned long pgd_current[]; -#define TLBMISS_HANDLER_SETUP_PGD(pgd) \ - pgd_current[smp_processor_id()] = (unsigned long)(pgd) - -#ifdef CONFIG_32BIT #define TLBMISS_HANDLER_SETUP() \ - write_c0_context((unsigned long) smp_processor_id() << 25); \ + write_c0_context((unsigned long) smp_processor_id() << \ + SMP_CPUID_REGSHIFT); \ back_to_back_c0_hazard(); \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) -#endif -#ifdef CONFIG_64BIT -#define TLBMISS_HANDLER_SETUP() \ - write_c0_context((unsigned long) smp_processor_id() << 26); \ - back_to_back_c0_hazard(); \ - TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) -#endif #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) diff --git a/arch/mips/include/asm/mutex.h b/arch/mips/include/asm/mutex.h deleted file mode 100644 index 458c1f7fbc18..000000000000 --- a/arch/mips/include/asm/mutex.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Pull in the generic implementation for the mutex fastpath. - * - * TODO: implement optimized primitives instead, or leave the generic - * implementation in place, or pick the atomic_xchg() based generic - * implementation. (see asm-generic/mutex-xchg.h for details) - */ - -#include <asm-generic/mutex-dec.h> diff --git a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h index 790f0f1e55c6..4e8eacb9588a 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h @@ -88,6 +88,7 @@ #define BRIDGE_DRAM_LIMIT6 0x22 #define BRIDGE_DRAM_LIMIT7 0x23 +#define BRIDGE_DRAM_NODE_TRANSLN(i) (0x24 + (i)) #define BRIDGE_DRAM_NODE_TRANSLN0 0x24 #define BRIDGE_DRAM_NODE_TRANSLN1 0x25 #define BRIDGE_DRAM_NODE_TRANSLN2 0x26 @@ -96,6 +97,8 @@ #define BRIDGE_DRAM_NODE_TRANSLN5 0x29 #define BRIDGE_DRAM_NODE_TRANSLN6 0x2a #define BRIDGE_DRAM_NODE_TRANSLN7 0x2b + +#define BRIDGE_DRAM_CHNL_TRANSLN(i) (0x2c + (i)) #define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c #define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d #define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e @@ -104,6 +107,7 @@ #define BRIDGE_DRAM_CHNL_TRANSLN5 0x31 #define BRIDGE_DRAM_CHNL_TRANSLN6 0x32 #define BRIDGE_DRAM_CHNL_TRANSLN7 0x33 + #define BRIDGE_PCIEMEM_BASE0 0x34 #define BRIDGE_PCIEMEM_BASE1 0x35 #define BRIDGE_PCIEMEM_BASE2 0x36 diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h index 9fac46fb7913..55eee77adaca 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h @@ -72,6 +72,12 @@ #define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4) #define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5) +/* XLP2xx has an updated USB block */ +#define XLP2XX_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 4, i) +#define XLP2XX_IO_USB_XHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 1) +#define XLP2XX_IO_USB_XHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 2) +#define XLP2XX_IO_USB_XHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 3) + #define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0) #define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1) @@ -88,6 +94,9 @@ #define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2) #define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3) #define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4) +/* on 2XX, all I2C busses are on the same block */ +#define XLP2XX_IO_I2C_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 7) + /* system management */ #define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5) #define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6) @@ -145,6 +154,7 @@ #define PCI_DEVICE_ID_NLM_NOR 0x1015 #define PCI_DEVICE_ID_NLM_NAND 0x1016 #define PCI_DEVICE_ID_NLM_MMC 0x1018 +#define PCI_DEVICE_ID_NLM_XHCI 0x101d #ifndef __ASSEMBLY__ diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h index 4b5108dfaa16..105389b79f09 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h @@ -208,13 +208,14 @@ #define PIC_LOCAL_SCHEDULING 1 #define PIC_GLOBAL_SCHEDULING 0 -#define PIC_CLK_HZ 133333333 - #define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r) #define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v) #define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node)) #define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ) +/* We use PIC on node 0 as a timer */ +#define pic_timer_freq() nlm_get_pic_frequency(0) + /* IRT and h/w interrupt routines */ static inline int nlm_pic_read_irt(uint64_t base, int irt_index) diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h index 470e52bfc061..fcf2833c16ca 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/sys.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h @@ -117,6 +117,36 @@ #define SYS_SCRTCH2 0x4b #define SYS_SCRTCH3 0x4c +/* PLL registers XLP2XX */ +#define SYS_PLL_CTRL0 0x240 +#define SYS_PLL_CTRL1 0x241 +#define SYS_PLL_CTRL2 0x242 +#define SYS_PLL_CTRL3 0x243 +#define SYS_DMC_PLL_CTRL0 0x244 +#define SYS_DMC_PLL_CTRL1 0x245 +#define SYS_DMC_PLL_CTRL2 0x246 +#define SYS_DMC_PLL_CTRL3 0x247 + +#define SYS_PLL_CTRL0_DEVX(x) (0x248 + (x) * 4) +#define SYS_PLL_CTRL1_DEVX(x) (0x249 + (x) * 4) +#define SYS_PLL_CTRL2_DEVX(x) (0x24a + (x) * 4) +#define SYS_PLL_CTRL3_DEVX(x) (0x24b + (x) * 4) + +#define SYS_CPU_PLL_CHG_CTRL 0x288 +#define SYS_PLL_CHG_CTRL 0x289 +#define SYS_CLK_DEV_DIS 0x28a +#define SYS_CLK_DEV_SEL 0x28b +#define SYS_CLK_DEV_DIV 0x28c +#define SYS_CLK_DEV_CHG 0x28d +#define SYS_CLK_DEV_SEL_REG 0x28e +#define SYS_CLK_DEV_DIV_REG 0x28f +#define SYS_CPU_PLL_LOCK 0x29f +#define SYS_SYS_PLL_LOCK 0x2a0 +#define SYS_PLL_MEM_CMD 0x2a1 +#define SYS_CPU_PLL_MEM_REQ 0x2a2 +#define SYS_SYS_PLL_MEM_REQ 0x2a3 +#define SYS_PLL_MEM_STAT 0x2a4 + #ifndef __ASSEMBLY__ #define nlm_read_sys_reg(b, r) nlm_read_reg(b, r) @@ -124,5 +154,6 @@ #define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node)) #define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ) +unsigned int nlm_get_pic_frequency(int node); #endif #endif diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h index f4ea0f7f3965..470f2095b346 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h @@ -41,15 +41,22 @@ #define PIC_PCIE_LINK_1_IRQ 20 #define PIC_PCIE_LINK_2_IRQ 21 #define PIC_PCIE_LINK_3_IRQ 22 + #define PIC_EHCI_0_IRQ 23 #define PIC_EHCI_1_IRQ 24 #define PIC_OHCI_0_IRQ 25 #define PIC_OHCI_1_IRQ 26 #define PIC_OHCI_2_IRQ 27 #define PIC_OHCI_3_IRQ 28 +#define PIC_2XX_XHCI_0_IRQ 23 +#define PIC_2XX_XHCI_1_IRQ 24 +#define PIC_2XX_XHCI_2_IRQ 25 + #define PIC_MMC_IRQ 29 #define PIC_I2C_0_IRQ 30 #define PIC_I2C_1_IRQ 31 +#define PIC_I2C_2_IRQ 32 +#define PIC_I2C_3_IRQ 33 #ifndef __ASSEMBLY__ @@ -59,7 +66,18 @@ void xlp_wakeup_secondary_cpus(void); void xlp_mmu_init(void); void nlm_hal_init(void); +int xlp_get_dram_map(int n, uint64_t *dram_map); + +/* Device tree related */ +void xlp_early_init_devtree(void); void *xlp_dt_init(void *fdtp); +static inline int cpu_is_xlpii(void) +{ + int chip = read_c0_prid() & 0xff00; + + return chip == PRID_IMP_NETLOGIC_XLP2XX; +} + #endif /* !__ASSEMBLY__ */ #endif /* _ASM_NLM_XLP_H */ diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h index 63c99176dffe..3c80a75233bd 100644 --- a/arch/mips/include/asm/netlogic/xlr/pic.h +++ b/arch/mips/include/asm/netlogic/xlr/pic.h @@ -36,6 +36,8 @@ #define _ASM_NLM_XLR_PIC_H #define PIC_CLK_HZ 66666666 +#define pic_timer_freq() PIC_CLK_HZ + /* PIC hardware interrupt numbers */ #define PIC_IRT_WD_INDEX 0 #define PIC_IRT_TIMER_0_INDEX 1 diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h index a2eed23c49a9..f5d77b91537f 100644 --- a/arch/mips/include/asm/octeon/octeon.h +++ b/arch/mips/include/asm/octeon/octeon.h @@ -251,4 +251,6 @@ extern void (*octeon_irq_setup_secondary)(void); typedef void (*octeon_irq_ip4_handler_t)(void); void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t); +extern void octeon_fixup_irqs(void); + #endif /* __ASM_OCTEON_OCTEON_H */ diff --git a/arch/mips/include/asm/parport.h b/arch/mips/include/asm/parport.h deleted file mode 100644 index cf252af64590..000000000000 --- a/arch/mips/include/asm/parport.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/parport.h> diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index fa8e0aa250ca..12d6842962be 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h @@ -83,6 +83,18 @@ static inline void pcibios_penalize_isa_irq(int irq, int active) extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, enum pci_mmap_state mmap_state, int write_combine); +#define HAVE_ARCH_PCI_RESOURCE_TO_USER + +static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, + const struct resource *rsrc, resource_size_t *start, + resource_size_t *end) +{ + phys_t size = resource_size(rsrc); + + *start = fixup_bigphys_addr(rsrc->start, size); + *end = rsrc->start + size; +} + /* * Dynamic DMA mapping stuff. * MIPS has everything mapped statically. @@ -136,11 +148,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) return channel ? 15 : 14; } -#ifdef CONFIG_CPU_CAVIUM_OCTEON -/* MSI arch hook for OCTEON */ -#define arch_setup_msi_irqs arch_setup_msi_irqs -#endif - extern char * (*pcibios_plat_setup)(char *str); #ifdef CONFIG_OF diff --git a/arch/mips/include/asm/percpu.h b/arch/mips/include/asm/percpu.h deleted file mode 100644 index 844e763e9332..000000000000 --- a/arch/mips/include/asm/percpu.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_PERCPU_H -#define __ASM_PERCPU_H - -#include <asm-generic/percpu.h> - -#endif /* __ASM_PERCPU_H */ diff --git a/arch/mips/include/asm/pgalloc.h b/arch/mips/include/asm/pgalloc.h index 881d18b4e298..b336037e8768 100644 --- a/arch/mips/include/asm/pgalloc.h +++ b/arch/mips/include/asm/pgalloc.h @@ -80,9 +80,12 @@ static inline struct page *pte_alloc_one(struct mm_struct *mm, struct page *pte; pte = alloc_pages(GFP_KERNEL | __GFP_REPEAT, PTE_ORDER); - if (pte) { - clear_highpage(pte); - pgtable_page_ctor(pte); + if (!pte) + return NULL; + clear_highpage(pte); + if (!pgtable_page_ctor(pte)) { + __free_page(pte); + return NULL; } return pte; } diff --git a/arch/mips/include/asm/prom.h b/arch/mips/include/asm/prom.h index 1e7e0961064b..ccd2b75f152c 100644 --- a/arch/mips/include/asm/prom.h +++ b/arch/mips/include/asm/prom.h @@ -17,22 +17,8 @@ #include <linux/types.h> #include <asm/bootinfo.h> -extern int early_init_dt_scan_memory_arch(unsigned long node, - const char *uname, int depth, void *data); - extern void device_tree_init(void); -static inline unsigned long pci_address_to_pio(phys_addr_t address) -{ - /* - * The ioport address can be directly used by inX() / outX() - */ - BUG_ON(address > IO_SPACE_LIMIT); - - return (unsigned long) address; -} -#define pci_address_to_pio pci_address_to_pio - struct boot_param_header; extern void __dt_setup_arch(struct boot_param_header *bph); diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h index 5e6cd0947393..7bba9da110af 100644 --- a/arch/mips/include/asm/ptrace.h +++ b/arch/mips/include/asm/ptrace.h @@ -81,7 +81,6 @@ static inline long regs_return_value(struct pt_regs *regs) #define instruction_pointer(regs) ((regs)->cp0_epc) #define profile_pc(regs) instruction_pointer(regs) -#define user_stack_pointer(r) ((r)->regs[29]) extern asmlinkage void syscall_trace_enter(struct pt_regs *regs); extern asmlinkage void syscall_trace_leave(struct pt_regs *regs); @@ -100,4 +99,17 @@ static inline void die_if_kernel(const char *str, struct pt_regs *regs) (struct pt_regs *)((sp | (THREAD_SIZE - 1)) + 1 - 32) - 1; \ }) +/* Helpers for working with the user stack pointer */ + +static inline unsigned long user_stack_pointer(struct pt_regs *regs) +{ + return regs->regs[29]; +} + +static inline void user_stack_pointer_set(struct pt_regs *regs, + unsigned long val) +{ + regs->regs[29] = val; +} + #endif /* _ASM_PTRACE_H */ diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h index a0b2650516ac..34d1a1917125 100644 --- a/arch/mips/include/asm/r4kcache.h +++ b/arch/mips/include/asm/r4kcache.h @@ -15,6 +15,7 @@ #include <asm/asm.h> #include <asm/cacheops.h> #include <asm/cpu-features.h> +#include <asm/cpu-type.h> #include <asm/mipsmtregs.h> /* @@ -162,7 +163,15 @@ static inline void flush_scache_line_indexed(unsigned long addr) static inline void flush_icache_line(unsigned long addr) { __iflush_prologue - cache_op(Hit_Invalidate_I, addr); + switch (boot_cpu_type()) { + case CPU_LOONGSON2: + cache_op(Hit_Invalidate_I_Loongson23, addr); + break; + + default: + cache_op(Hit_Invalidate_I, addr); + break; + } __iflush_epilogue } @@ -208,7 +217,15 @@ static inline void flush_scache_line(unsigned long addr) */ static inline void protected_flush_icache_line(unsigned long addr) { - protected_cache_op(Hit_Invalidate_I, addr); + switch (boot_cpu_type()) { + case CPU_LOONGSON2: + protected_cache_op(Hit_Invalidate_I_Loongson23, addr); + break; + + default: + protected_cache_op(Hit_Invalidate_I, addr); + break; + } } /* @@ -412,8 +429,8 @@ __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64 __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128) /* build blast_xxx_range, protected_blast_xxx_range */ -#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \ -static inline void prot##blast_##pfx##cache##_range(unsigned long start, \ +#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \ +static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \ unsigned long end) \ { \ unsigned long lsize = cpu_##desc##_line_size(); \ @@ -432,13 +449,15 @@ static inline void prot##blast_##pfx##cache##_range(unsigned long start, \ __##pfx##flush_epilogue \ } -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_) -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_) -__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_) -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, ) -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, ) +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, ) +__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, ) +__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, ) +__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson23, \ + protected_, loongson23_) +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , ) +__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , ) /* blast_inv_dcache_range */ -__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, ) -__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, ) +__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , ) +__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , ) #endif /* _ASM_R4KCACHE_H */ diff --git a/arch/mips/include/asm/scatterlist.h b/arch/mips/include/asm/scatterlist.h deleted file mode 100644 index 7ee0e646d82c..000000000000 --- a/arch/mips/include/asm/scatterlist.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_SCATTERLIST_H -#define __ASM_SCATTERLIST_H - -#include <asm-generic/scatterlist.h> - -#endif /* __ASM_SCATTERLIST_H */ diff --git a/arch/mips/include/asm/sections.h b/arch/mips/include/asm/sections.h deleted file mode 100644 index b7e37262c246..000000000000 --- a/arch/mips/include/asm/sections.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_SECTIONS_H -#define _ASM_SECTIONS_H - -#include <asm-generic/sections.h> - -#endif /* _ASM_SECTIONS_H */ diff --git a/arch/mips/include/asm/segment.h b/arch/mips/include/asm/segment.h deleted file mode 100644 index 92ac001fc483..000000000000 --- a/arch/mips/include/asm/segment.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_SEGMENT_H -#define _ASM_SEGMENT_H - -/* Only here because we have some old header files that expect it.. */ - -#endif /* _ASM_SEGMENT_H */ diff --git a/arch/mips/include/asm/serial.h b/arch/mips/include/asm/serial.h deleted file mode 100644 index a0cb0caff152..000000000000 --- a/arch/mips/include/asm/serial.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/serial.h> diff --git a/arch/mips/include/asm/setup.h b/arch/mips/include/asm/setup.h index e26589ef36ee..d7bfdeba9e84 100644 --- a/arch/mips/include/asm/setup.h +++ b/arch/mips/include/asm/setup.h @@ -5,6 +5,14 @@ extern void setup_early_printk(void); +#ifdef CONFIG_EARLY_PRINTK_8250 +extern void setup_8250_early_printk_port(unsigned long base, + unsigned int reg_shift, unsigned int timeout); +#else +static inline void setup_8250_early_printk_port(unsigned long base, + unsigned int reg_shift, unsigned int timeout) {} +#endif + extern void set_handler(unsigned long offset, void *addr, unsigned long len); extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len); diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index 23fc95e65673..4857e2c8df5a 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -17,6 +17,7 @@ #include <asm/asmmacro.h> #include <asm/mipsregs.h> #include <asm/asm-offsets.h> +#include <asm/thread_info.h> /* * For SMTC kernel, global IE should be left set, and interrupts @@ -93,21 +94,8 @@ .endm #ifdef CONFIG_SMP -#ifdef CONFIG_MIPS_MT_SMTC -#define PTEBASE_SHIFT 19 /* TCBIND */ -#define CPU_ID_REG CP0_TCBIND -#define CPU_ID_MFC0 mfc0 -#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT) -#define PTEBASE_SHIFT 48 /* XCONTEXT */ -#define CPU_ID_REG CP0_XCONTEXT -#define CPU_ID_MFC0 MFC0 -#else -#define PTEBASE_SHIFT 23 /* CONTEXT */ -#define CPU_ID_REG CP0_CONTEXT -#define CPU_ID_MFC0 MFC0 -#endif .macro get_saved_sp /* SMP variation */ - CPU_ID_MFC0 k0, CPU_ID_REG + ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) lui k1, %hi(kernelsp) #else @@ -117,17 +105,17 @@ daddiu k1, %hi(kernelsp) dsll k1, 16 #endif - LONG_SRL k0, PTEBASE_SHIFT + LONG_SRL k0, SMP_CPUID_PTRSHIFT LONG_ADDU k1, k0 LONG_L k1, %lo(kernelsp)(k1) .endm .macro set_saved_sp stackp temp temp2 - CPU_ID_MFC0 \temp, CPU_ID_REG - LONG_SRL \temp, PTEBASE_SHIFT + ASM_CPUID_MFC0 \temp, ASM_SMP_CPUID_REG + LONG_SRL \temp, SMP_CPUID_PTRSHIFT LONG_S \stackp, kernelsp(\temp) .endm -#else +#else /* !CONFIG_SMP */ .macro get_saved_sp /* Uniprocessor variation */ #ifdef CONFIG_CPU_JUMP_WORKAROUNDS /* diff --git a/arch/mips/include/asm/syscall.h b/arch/mips/include/asm/syscall.h new file mode 100644 index 000000000000..81c89132c59d --- /dev/null +++ b/arch/mips/include/asm/syscall.h @@ -0,0 +1,116 @@ +/* + * Access to user system call parameters and results + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * See asm-generic/syscall.h for descriptions of what we must do here. + * + * Copyright (C) 2012 Ralf Baechle <ralf@linux-mips.org> + */ + +#ifndef __ASM_MIPS_SYSCALL_H +#define __ASM_MIPS_SYSCALL_H + +#include <linux/audit.h> +#include <linux/elf-em.h> +#include <linux/kernel.h> +#include <linux/sched.h> +#include <linux/uaccess.h> +#include <asm/ptrace.h> + +static inline long syscall_get_nr(struct task_struct *task, + struct pt_regs *regs) +{ + return regs->regs[2]; +} + +static inline unsigned long mips_get_syscall_arg(unsigned long *arg, + struct task_struct *task, struct pt_regs *regs, unsigned int n) +{ + unsigned long usp = regs->regs[29]; + + switch (n) { + case 0: case 1: case 2: case 3: + *arg = regs->regs[4 + n]; + + return 0; + +#ifdef CONFIG_32BIT + case 4: case 5: case 6: case 7: + return get_user(*arg, (int *)usp + 4 * n); +#endif + +#ifdef CONFIG_64BIT + case 4: case 5: case 6: case 7: +#ifdef CONFIG_MIPS32_O32 + if (test_thread_flag(TIF_32BIT_REGS)) + return get_user(*arg, (int *)usp + 4 * n); + else +#endif + *arg = regs->regs[4 + n]; + + return 0; +#endif + + default: + BUG(); + } +} + +static inline long syscall_get_return_value(struct task_struct *task, + struct pt_regs *regs) +{ + return regs->regs[2]; +} + +static inline void syscall_set_return_value(struct task_struct *task, + struct pt_regs *regs, + int error, long val) +{ + if (error) { + regs->regs[2] = -error; + regs->regs[7] = -1; + } else { + regs->regs[2] = val; + regs->regs[7] = 0; + } +} + +static inline void syscall_get_arguments(struct task_struct *task, + struct pt_regs *regs, + unsigned int i, unsigned int n, + unsigned long *args) +{ + unsigned long arg; + int ret; + + while (n--) + ret |= mips_get_syscall_arg(&arg, task, regs, i++); + + /* + * No way to communicate an error because this is a void function. + */ +#if 0 + return ret; +#endif +} + +extern const unsigned long sys_call_table[]; +extern const unsigned long sys32_call_table[]; +extern const unsigned long sysn32_call_table[]; + +static inline int __syscall_get_arch(void) +{ + int arch = EM_MIPS; +#ifdef CONFIG_64BIT + arch |= __AUDIT_ARCH_64BIT; +#endif +#if defined(__LITTLE_ENDIAN) + arch |= __AUDIT_ARCH_LE; +#endif + return arch; +} + +#endif /* __ASM_MIPS_SYSCALL_H */ diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h index 61215a34acc6..f9b24bfbdbae 100644 --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h @@ -116,6 +116,7 @@ static inline struct thread_info *current_thread_info(void) #define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */ #define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */ #define TIF_LOAD_WATCH 25 /* If set, load watch registers */ +#define TIF_SYSCALL_TRACEPOINT 26 /* syscall tracepoint instrumentation */ #define TIF_SYSCALL_TRACE 31 /* syscall trace active */ #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) @@ -132,21 +133,54 @@ static inline struct thread_info *current_thread_info(void) #define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR) #define _TIF_FPUBOUND (1<<TIF_FPUBOUND) #define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH) +#define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT) #define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \ - _TIF_SYSCALL_AUDIT) + _TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT) /* work to do in syscall_trace_leave() */ #define _TIF_WORK_SYSCALL_EXIT (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \ - _TIF_SYSCALL_AUDIT) + _TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT) /* work to do on interrupt/exception return */ #define _TIF_WORK_MASK \ (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME) /* work to do on any return to u-space */ #define _TIF_ALLWORK_MASK (_TIF_NOHZ | _TIF_WORK_MASK | \ - _TIF_WORK_SYSCALL_EXIT) + _TIF_WORK_SYSCALL_EXIT | \ + _TIF_SYSCALL_TRACEPOINT) -#endif /* __KERNEL__ */ +/* + * We stash processor id into a COP0 register to retrieve it fast + * at kernel exception entry. + */ +#if defined(CONFIG_MIPS_MT_SMTC) +#define SMP_CPUID_REG 2, 2 /* TCBIND */ +#define ASM_SMP_CPUID_REG $2, 2 +#define SMP_CPUID_PTRSHIFT 19 +#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT) +#define SMP_CPUID_REG 20, 0 /* XCONTEXT */ +#define ASM_SMP_CPUID_REG $20 +#define SMP_CPUID_PTRSHIFT 48 +#else +#define SMP_CPUID_REG 4, 0 /* CONTEXT */ +#define ASM_SMP_CPUID_REG $4 +#define SMP_CPUID_PTRSHIFT 23 +#endif +#ifdef CONFIG_64BIT +#define SMP_CPUID_REGSHIFT (SMP_CPUID_PTRSHIFT + 3) +#else +#define SMP_CPUID_REGSHIFT (SMP_CPUID_PTRSHIFT + 2) +#endif + +#ifdef CONFIG_MIPS_MT_SMTC +#define ASM_CPUID_MFC0 mfc0 +#define UASM_i_CPUID_MFC0 uasm_i_mfc0 +#else +#define ASM_CPUID_MFC0 MFC0 +#define UASM_i_CPUID_MFC0 UASM_i_MFC0 +#endif + +#endif /* __KERNEL__ */ #endif /* _ASM_THREAD_INFO_H */ diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h index 2d7b9df4542d..24f534a7fbc3 100644 --- a/arch/mips/include/asm/time.h +++ b/arch/mips/include/asm/time.h @@ -75,7 +75,7 @@ extern int init_r4k_clocksource(void); static inline int init_mips_clocksource(void) { -#if defined(CONFIG_CSRC_R4K) && !defined(CONFIG_CSRC_GIC) +#ifdef CONFIG_CSRC_R4K return init_r4k_clocksource(); #else return 0; diff --git a/arch/mips/include/asm/timex.h b/arch/mips/include/asm/timex.h index 6529704aa73a..c5424757da65 100644 --- a/arch/mips/include/asm/timex.h +++ b/arch/mips/include/asm/timex.h @@ -10,7 +10,9 @@ #ifdef __KERNEL__ +#include <asm/cpu-features.h> #include <asm/mipsregs.h> +#include <asm/cpu-type.h> /* * This is the clock rate of the i8253 PIT. A MIPS system may not have @@ -33,9 +35,38 @@ typedef unsigned int cycles_t; +/* + * On R4000/R4400 before version 5.0 an erratum exists such that if the + * cycle counter is read in the exact moment that it is matching the + * compare register, no interrupt will be generated. + * + * There is a suggested workaround and also the erratum can't strike if + * the compare interrupt isn't being used as the clock source device. + * However for now the implementaton of this function doesn't get these + * fine details right. + */ static inline cycles_t get_cycles(void) { - return 0; + switch (boot_cpu_type()) { + case CPU_R4400PC: + case CPU_R4400SC: + case CPU_R4400MC: + if ((read_c0_prid() & 0xff) >= 0x0050) + return read_c0_count(); + break; + + case CPU_R4000PC: + case CPU_R4000SC: + case CPU_R4000MC: + break; + + default: + if (cpu_has_counter) + return read_c0_count(); + break; + } + + return 0; /* no usable counter */ } #endif /* __KERNEL__ */ diff --git a/arch/mips/include/asm/ucontext.h b/arch/mips/include/asm/ucontext.h deleted file mode 100644 index 9bc07b9f30fb..000000000000 --- a/arch/mips/include/asm/ucontext.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/ucontext.h> diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h index 63c9c886173a..4d3b92886665 100644 --- a/arch/mips/include/asm/unistd.h +++ b/arch/mips/include/asm/unistd.h @@ -14,6 +14,13 @@ #include <uapi/asm/unistd.h> +#ifdef CONFIG_MIPS32_N32 +#define NR_syscalls (__NR_N32_Linux + __NR_N32_Linux_syscalls) +#elif defined(CONFIG_64BIT) +#define NR_syscalls (__NR_64_Linux + __NR_64_Linux_syscalls) +#else +#define NR_syscalls (__NR_O32_Linux + __NR_O32_Linux_syscalls) +#endif #ifndef __ASSEMBLY__ diff --git a/arch/mips/include/asm/vga.h b/arch/mips/include/asm/vga.h index f4cff7e4fa8a..f82c83749a08 100644 --- a/arch/mips/include/asm/vga.h +++ b/arch/mips/include/asm/vga.h @@ -6,6 +6,7 @@ #ifndef _ASM_VGA_H #define _ASM_VGA_H +#include <asm/addrspace.h> #include <asm/byteorder.h> /* @@ -13,7 +14,7 @@ * access the videoram directly without any black magic. */ -#define VGA_MAP_MEM(x, s) (0xb0000000L + (unsigned long)(x)) +#define VGA_MAP_MEM(x, s) CKSEG1ADDR(0x10000000L + (unsigned long)(x)) #define vga_readb(x) (*(x)) #define vga_writeb(x, y) (*(y) = (x)) diff --git a/arch/mips/include/asm/xor.h b/arch/mips/include/asm/xor.h deleted file mode 100644 index c82eb12a5b18..000000000000 --- a/arch/mips/include/asm/xor.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/xor.h> diff --git a/arch/mips/include/uapi/asm/Kbuild b/arch/mips/include/uapi/asm/Kbuild index 350ccccadcb9..be7196eacb88 100644 --- a/arch/mips/include/uapi/asm/Kbuild +++ b/arch/mips/include/uapi/asm/Kbuild @@ -1,7 +1,9 @@ # UAPI Header export list include include/uapi/asm-generic/Kbuild.asm -header-y += auxvec.h +generic-y += auxvec.h +generic-y += ipcbuf.h + header-y += bitsperlong.h header-y += break.h header-y += byteorder.h @@ -11,7 +13,6 @@ header-y += fcntl.h header-y += inst.h header-y += ioctl.h header-y += ioctls.h -header-y += ipcbuf.h header-y += kvm_para.h header-y += mman.h header-y += msgbuf.h diff --git a/arch/mips/include/uapi/asm/auxvec.h b/arch/mips/include/uapi/asm/auxvec.h deleted file mode 100644 index 7cf7f2d21943..000000000000 --- a/arch/mips/include/uapi/asm/auxvec.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef _ASM_AUXVEC_H -#define _ASM_AUXVEC_H - -#endif /* _ASM_AUXVEC_H */ diff --git a/arch/mips/include/uapi/asm/errno.h b/arch/mips/include/uapi/asm/errno.h index 31575e2fd1bd..02d645d7aa9a 100644 --- a/arch/mips/include/uapi/asm/errno.h +++ b/arch/mips/include/uapi/asm/errno.h @@ -102,7 +102,7 @@ #define EWOULDBLOCK EAGAIN /* Operation would block */ #define EALREADY 149 /* Operation already in progress */ #define EINPROGRESS 150 /* Operation now in progress */ -#define ESTALE 151 /* Stale NFS file handle */ +#define ESTALE 151 /* Stale file handle */ #define ECANCELED 158 /* AIO operation canceled */ /* diff --git a/arch/mips/include/uapi/asm/ipcbuf.h b/arch/mips/include/uapi/asm/ipcbuf.h deleted file mode 100644 index 84c7e51cb6d0..000000000000 --- a/arch/mips/include/uapi/asm/ipcbuf.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/ipcbuf.h> diff --git a/arch/mips/include/uapi/asm/siginfo.h b/arch/mips/include/uapi/asm/siginfo.h index 88e292b7719e..e81174432bab 100644 --- a/arch/mips/include/uapi/asm/siginfo.h +++ b/arch/mips/include/uapi/asm/siginfo.h @@ -33,6 +33,8 @@ struct siginfo; #error _MIPS_SZLONG neither 32 nor 64 #endif +#define __ARCH_SIGSYS + #include <asm-generic/siginfo.h> typedef struct siginfo { @@ -97,6 +99,13 @@ typedef struct siginfo { __ARCH_SI_BAND_T _band; /* POLL_IN, POLL_OUT, POLL_MSG */ int _fd; } _sigpoll; + + /* SIGSYS */ + struct { + void __user *_call_addr; /* calling user insn */ + int _syscall; /* triggering system call number */ + unsigned int _arch; /* AUDIT_ARCH_* of syscall */ + } _sigsys; } _sifields; } siginfo_t; diff --git a/arch/mips/include/uapi/asm/socket.h b/arch/mips/include/uapi/asm/socket.h index 61c01f054d1b..0df9787cd84d 100644 --- a/arch/mips/include/uapi/asm/socket.h +++ b/arch/mips/include/uapi/asm/socket.h @@ -94,4 +94,6 @@ #define SO_BUSY_POLL 46 +#define SO_MAX_PACING_RATE 47 + #endif /* _UAPI_ASM_SOCKET_H */ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 423d871a946b..1c1b71752c84 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -26,7 +26,6 @@ obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o obj-$(CONFIG_CSRC_GIC) += csrc-gic.o obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o -obj-$(CONFIG_CSRC_POWERTV) += csrc-powertv.o obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o obj-$(CONFIG_SYNC_R4K) += sync-r4k.o @@ -35,6 +34,7 @@ obj-$(CONFIG_STACKTRACE) += stacktrace.o obj-$(CONFIG_MODULES) += mips_ksyms.o module.o obj-$(CONFIG_MODULES_USE_ELF_RELA) += module-rela.o +obj-$(CONFIG_FTRACE_SYSCALLS) += ftrace.o obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o obj-$(CONFIG_CPU_R4K_FPU) += r4k_fpu.o r4k_switch.o @@ -84,6 +84,7 @@ obj-$(CONFIG_GPIO_TXX9) += gpio_txx9.o obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o crash.o obj-$(CONFIG_CRASH_DUMP) += crash_dump.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o +obj-$(CONFIG_EARLY_PRINTK_8250) += early_printk_8250.o obj-$(CONFIG_SPINLOCK_TEST) += spinlock_test.o obj-$(CONFIG_MIPS_MACHINE) += mips_machine.o diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 4c6167a17875..c814287bdf5d 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -20,6 +20,7 @@ #include <asm/bugs.h> #include <asm/cpu.h> +#include <asm/cpu-type.h> #include <asm/fpu.h> #include <asm/mipsregs.h> #include <asm/watch.h> @@ -55,7 +56,7 @@ static inline void check_errata(void) { struct cpuinfo_mips *c = ¤t_cpu_data; - switch (c->cputype) { + switch (current_cpu_type()) { case CPU_34K: /* * Erratum "RPS May Cause Incorrect Instruction Execution" @@ -122,7 +123,7 @@ static inline unsigned long cpu_get_fpu_id(void) */ static inline int __cpu_has_fpu(void) { - return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); + return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE); } static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) @@ -290,6 +291,17 @@ static inline unsigned int decode_config4(struct cpuinfo_mips *c) return config4 & MIPS_CONF_M; } +static inline unsigned int decode_config5(struct cpuinfo_mips *c) +{ + unsigned int config5; + + config5 = read_c0_config5(); + config5 &= ~MIPS_CONF5_UFR; + write_c0_config5(config5); + + return config5 & MIPS_CONF_M; +} + static void decode_configs(struct cpuinfo_mips *c) { int ok; @@ -310,6 +322,8 @@ static void decode_configs(struct cpuinfo_mips *c) ok = decode_config3(c); if (ok) ok = decode_config4(c); + if (ok) + ok = decode_config5(c); mips_probe_watch_registers(c); @@ -322,7 +336,7 @@ static void decode_configs(struct cpuinfo_mips *c) static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) { - switch (c->processor_id & 0xff00) { + switch (c->processor_id & PRID_IMP_MASK) { case PRID_IMP_R2000: c->cputype = CPU_R2000; __cpu_name[cpu] = "R2000"; @@ -333,7 +347,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) c->tlbsize = 64; break; case PRID_IMP_R3000: - if ((c->processor_id & 0xff) == PRID_REV_R3000A) { + if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { if (cpu_has_confreg()) { c->cputype = CPU_R3081E; __cpu_name[cpu] = "R3081"; @@ -353,7 +367,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) break; case PRID_IMP_R4000: if (read_c0_config() & CONF_SC) { - if ((c->processor_id & 0xff) >= PRID_REV_R4400) { + if ((c->processor_id & PRID_REV_MASK) >= + PRID_REV_R4400) { c->cputype = CPU_R4400PC; __cpu_name[cpu] = "R4400PC"; } else { @@ -361,12 +376,33 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "R4000PC"; } } else { - if ((c->processor_id & 0xff) >= PRID_REV_R4400) { - c->cputype = CPU_R4400SC; - __cpu_name[cpu] = "R4400SC"; + int cca = read_c0_config() & CONF_CM_CMASK; + int mc; + + /* + * SC and MC versions can't be reliably told apart, + * but only the latter support coherent caching + * modes so assume the firmware has set the KSEG0 + * coherency attribute reasonably (if uncached, we + * assume SC). + */ + switch (cca) { + case CONF_CM_CACHABLE_CE: + case CONF_CM_CACHABLE_COW: + case CONF_CM_CACHABLE_CUW: + mc = 1; + break; + default: + mc = 0; + break; + } + if ((c->processor_id & PRID_REV_MASK) >= + PRID_REV_R4400) { + c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; + __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; } else { - c->cputype = CPU_R4000SC; - __cpu_name[cpu] = "R4000SC"; + c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; + __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; } } @@ -454,7 +490,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "TX3927"; c->tlbsize = 64; } else { - switch (c->processor_id & 0xff) { + switch (c->processor_id & PRID_REV_MASK) { case PRID_REV_TX3912: c->cputype = CPU_TX3912; __cpu_name[cpu] = "TX3912"; @@ -640,7 +676,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); - switch (c->processor_id & 0xff00) { + switch (c->processor_id & PRID_IMP_MASK) { case PRID_IMP_4KC: c->cputype = CPU_4KC; __cpu_name[cpu] = "MIPS 4Kc"; @@ -711,7 +747,7 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); - switch (c->processor_id & 0xff00) { + switch (c->processor_id & PRID_IMP_MASK) { case PRID_IMP_AU1_REV1: case PRID_IMP_AU1_REV2: c->cputype = CPU_ALCHEMY; @@ -730,7 +766,7 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) break; case 4: __cpu_name[cpu] = "Au1200"; - if ((c->processor_id & 0xff) == 2) + if ((c->processor_id & PRID_REV_MASK) == 2) __cpu_name[cpu] = "Au1250"; break; case 5: @@ -748,12 +784,12 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); - switch (c->processor_id & 0xff00) { + switch (c->processor_id & PRID_IMP_MASK) { case PRID_IMP_SB1: c->cputype = CPU_SB1; __cpu_name[cpu] = "SiByte SB1"; /* FPU in pass1 is known to have issues. */ - if ((c->processor_id & 0xff) < 0x02) + if ((c->processor_id & PRID_REV_MASK) < 0x02) c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); break; case PRID_IMP_SB1A: @@ -766,7 +802,7 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); - switch (c->processor_id & 0xff00) { + switch (c->processor_id & PRID_IMP_MASK) { case PRID_IMP_SR71000: c->cputype = CPU_SR71000; __cpu_name[cpu] = "Sandcraft SR71000"; @@ -779,7 +815,7 @@ static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); - switch (c->processor_id & 0xff00) { + switch (c->processor_id & PRID_IMP_MASK) { case PRID_IMP_PR4450: c->cputype = CPU_PR4450; __cpu_name[cpu] = "Philips PR4450"; @@ -791,7 +827,7 @@ static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); - switch (c->processor_id & 0xff00) { + switch (c->processor_id & PRID_IMP_MASK) { case PRID_IMP_BMIPS32_REV4: case PRID_IMP_BMIPS32_REV8: c->cputype = CPU_BMIPS32; @@ -806,7 +842,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) set_elf_platform(cpu, "bmips3300"); break; case PRID_IMP_BMIPS43XX: { - int rev = c->processor_id & 0xff; + int rev = c->processor_id & PRID_REV_MASK; if (rev >= PRID_REV_BMIPS4380_LO && rev <= PRID_REV_BMIPS4380_HI) { @@ -832,7 +868,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); - switch (c->processor_id & 0xff00) { + switch (c->processor_id & PRID_IMP_MASK) { case PRID_IMP_CAVIUM_CN38XX: case PRID_IMP_CAVIUM_CN31XX: case PRID_IMP_CAVIUM_CN30XX: @@ -852,10 +888,17 @@ platform: case PRID_IMP_CAVIUM_CN63XX: case PRID_IMP_CAVIUM_CN66XX: case PRID_IMP_CAVIUM_CN68XX: + case PRID_IMP_CAVIUM_CNF71XX: c->cputype = CPU_CAVIUM_OCTEON2; __cpu_name[cpu] = "Cavium Octeon II"; set_elf_platform(cpu, "octeon2"); break; + case PRID_IMP_CAVIUM_CN70XX: + case PRID_IMP_CAVIUM_CN78XX: + c->cputype = CPU_CAVIUM_OCTEON3; + __cpu_name[cpu] = "Cavium Octeon III"; + set_elf_platform(cpu, "octeon3"); + break; default: printk(KERN_INFO "Unknown Octeon chip!\n"); c->cputype = CPU_UNKNOWN; @@ -868,7 +911,7 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) decode_configs(c); /* JZRISC does not implement the CP0 counter. */ c->options &= ~MIPS_CPU_COUNTER; - switch (c->processor_id & 0xff00) { + switch (c->processor_id & PRID_IMP_MASK) { case PRID_IMP_JZRISC: c->cputype = CPU_JZRISC; __cpu_name[cpu] = "Ingenic JZRISC"; @@ -883,7 +926,7 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) { decode_configs(c); - if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) { + if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { c->cputype = CPU_ALCHEMY; __cpu_name[cpu] = "Au1300"; /* following stuff is not for Alchemy */ @@ -898,7 +941,12 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) MIPS_CPU_EJTAG | MIPS_CPU_LLSC); - switch (c->processor_id & 0xff00) { + switch (c->processor_id & PRID_IMP_MASK) { + case PRID_IMP_NETLOGIC_XLP2XX: + c->cputype = CPU_XLP; + __cpu_name[cpu] = "Broadcom XLPII"; + break; + case PRID_IMP_NETLOGIC_XLP8XX: case PRID_IMP_NETLOGIC_XLP3XX: c->cputype = CPU_XLP; @@ -972,7 +1020,7 @@ void cpu_probe(void) c->cputype = CPU_UNKNOWN; c->processor_id = read_c0_prid(); - switch (c->processor_id & 0xff0000) { + switch (c->processor_id & PRID_COMP_MASK) { case PRID_COMP_LEGACY: cpu_probe_legacy(c, cpu); break; @@ -1051,8 +1099,8 @@ void cpu_report(void) { struct cpuinfo_mips *c = ¤t_cpu_data; - printk(KERN_INFO "CPU revision is: %08x (%s)\n", - c->processor_id, cpu_name_string()); + pr_info("CPU%d revision is: %08x (%s)\n", + smp_processor_id(), c->processor_id, cpu_name_string()); if (c->options & MIPS_CPU_FPU) printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); } diff --git a/arch/mips/kernel/csrc-ioasic.c b/arch/mips/kernel/csrc-ioasic.c index 0654bff9b69c..6cbbf6e106b9 100644 --- a/arch/mips/kernel/csrc-ioasic.c +++ b/arch/mips/kernel/csrc-ioasic.c @@ -37,13 +37,13 @@ static struct clocksource clocksource_dec = { .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; -void __init dec_ioasic_clocksource_init(void) +int __init dec_ioasic_clocksource_init(void) { unsigned int freq; u32 start, end; - int i = HZ / 10; - + int i = HZ / 8; + ds1287_timer_state(); while (!ds1287_timer_state()) ; @@ -55,9 +55,15 @@ void __init dec_ioasic_clocksource_init(void) end = dec_ioasic_hpt_read(&clocksource_dec); - freq = (end - start) * 10; + freq = (end - start) * 8; + + /* An early revision of the I/O ASIC didn't have the counter. */ + if (!freq) + return -ENXIO; + printk(KERN_INFO "I/O ASIC clock frequency %dHz\n", freq); clocksource_dec.rating = 200 + freq / 10000000; clocksource_register_hz(&clocksource_dec, freq); + return 0; } diff --git a/arch/mips/kernel/csrc-powertv.c b/arch/mips/kernel/csrc-powertv.c deleted file mode 100644 index abd99ea911ae..000000000000 --- a/arch/mips/kernel/csrc-powertv.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright (C) 2008 Scientific-Atlanta, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ -/* - * The file comes from kernel/csrc-r4k.c - */ -#include <linux/clocksource.h> -#include <linux/init.h> - -#include <asm/time.h> /* Not included in linux/time.h */ - -#include <asm/mach-powertv/asic_regs.h> -#include "powertv-clock.h" - -/* MIPS PLL Register Definitions */ -#define PLL_GET_M(x) (((x) >> 8) & 0x000000FF) -#define PLL_GET_N(x) (((x) >> 16) & 0x000000FF) -#define PLL_GET_P(x) (((x) >> 24) & 0x00000007) - -/* - * returns: Clock frequency in kHz - */ -unsigned int __init mips_get_pll_freq(void) -{ - unsigned int pll_reg, m, n, p; - unsigned int fin = 54000; /* Base frequency in kHz */ - unsigned int fout; - - /* Read PLL register setting */ - pll_reg = asic_read(mips_pll_setup); - m = PLL_GET_M(pll_reg); - n = PLL_GET_N(pll_reg); - p = PLL_GET_P(pll_reg); - pr_info("MIPS PLL Register:0x%x M=%d N=%d P=%d\n", pll_reg, m, n, p); - - /* Calculate clock frequency = (2 * N * 54MHz) / (M * (2**P)) */ - fout = ((2 * n * fin) / (m * (0x01 << p))); - - pr_info("MIPS Clock Freq=%d kHz\n", fout); - - return fout; -} - -static cycle_t c0_hpt_read(struct clocksource *cs) -{ - return read_c0_count(); -} - -static struct clocksource clocksource_mips = { - .name = "powertv-counter", - .read = c0_hpt_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static void __init powertv_c0_hpt_clocksource_init(void) -{ - unsigned int pll_freq = mips_get_pll_freq(); - - pr_info("CPU frequency %d.%02d MHz\n", pll_freq / 1000, - (pll_freq % 1000) * 100 / 1000); - - mips_hpt_frequency = pll_freq / 2 * 1000; - - clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; - - clocksource_register_hz(&clocksource_mips, mips_hpt_frequency); -} - -/** - * struct tim_c - free running counter - * @hi: High 16 bits of the counter - * @lo: Low 32 bits of the counter - * - * Lays out the structure of the free running counter in memory. This counter - * increments at a rate of 27 MHz/8 on all platforms. - */ -struct tim_c { - unsigned int hi; - unsigned int lo; -}; - -static struct tim_c *tim_c; - -static cycle_t tim_c_read(struct clocksource *cs) -{ - unsigned int hi; - unsigned int next_hi; - unsigned int lo; - - hi = readl(&tim_c->hi); - - for (;;) { - lo = readl(&tim_c->lo); - next_hi = readl(&tim_c->hi); - if (next_hi == hi) - break; - hi = next_hi; - } - -pr_crit("%s: read %llx\n", __func__, ((u64) hi << 32) | lo); - return ((u64) hi << 32) | lo; -} - -#define TIM_C_SIZE 48 /* # bits in the timer */ - -static struct clocksource clocksource_tim_c = { - .name = "powertv-tim_c", - .read = tim_c_read, - .mask = CLOCKSOURCE_MASK(TIM_C_SIZE), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -/** - * powertv_tim_c_clocksource_init - set up a clock source for the TIM_C clock - * - * We know that TIM_C counts at 27 MHz/8, so each cycle corresponds to - * 1 / (27,000,000/8) seconds. - */ -static void __init powertv_tim_c_clocksource_init(void) -{ - const unsigned long counts_per_second = 27000000 / 8; - - clocksource_tim_c.rating = 200; - - clocksource_register_hz(&clocksource_tim_c, counts_per_second); - tim_c = (struct tim_c *) asic_reg_addr(tim_ch); -} - -/** - powertv_clocksource_init - initialize all clocksources - */ -void __init powertv_clocksource_init(void) -{ - powertv_c0_hpt_clocksource_init(); - powertv_tim_c_clocksource_init(); -} diff --git a/arch/mips/kernel/early_printk_8250.c b/arch/mips/kernel/early_printk_8250.c new file mode 100644 index 000000000000..83cea3767556 --- /dev/null +++ b/arch/mips/kernel/early_printk_8250.c @@ -0,0 +1,66 @@ +/* + * 8250/16550-type serial ports prom_putchar() + * + * Copyright (C) 2010 Yoichi Yuasa <yuasa@linux-mips.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <linux/io.h> +#include <linux/serial_core.h> +#include <linux/serial_reg.h> + +static void __iomem *serial8250_base; +static unsigned int serial8250_reg_shift; +static unsigned int serial8250_tx_timeout; + +void setup_8250_early_printk_port(unsigned long base, unsigned int reg_shift, + unsigned int timeout) +{ + serial8250_base = (void __iomem *)base; + serial8250_reg_shift = reg_shift; + serial8250_tx_timeout = timeout; +} + +static inline u8 serial_in(int offset) +{ + return readb(serial8250_base + (offset << serial8250_reg_shift)); +} + +static inline void serial_out(int offset, char value) +{ + writeb(value, serial8250_base + (offset << serial8250_reg_shift)); +} + +void prom_putchar(char c) +{ + unsigned int timeout; + int status, bits; + + if (!serial8250_base) + return; + + timeout = serial8250_tx_timeout; + bits = UART_LSR_TEMT | UART_LSR_THRE; + + do { + status = serial_in(UART_LSR); + + if (--timeout == 0) + break; + } while ((status & bits) != bits); + + if (timeout) + serial_out(UART_TX, c); +} diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c index dba90ec0dc38..185ba258361b 100644 --- a/arch/mips/kernel/ftrace.c +++ b/arch/mips/kernel/ftrace.c @@ -11,11 +11,14 @@ #include <linux/uaccess.h> #include <linux/init.h> #include <linux/ftrace.h> +#include <linux/syscalls.h> #include <asm/asm.h> #include <asm/asm-offsets.h> #include <asm/cacheflush.h> +#include <asm/syscall.h> #include <asm/uasm.h> +#include <asm/unistd.h> #include <asm-generic/sections.h> @@ -364,3 +367,33 @@ out: WARN_ON(1); } #endif /* CONFIG_FUNCTION_GRAPH_TRACER */ + +#ifdef CONFIG_FTRACE_SYSCALLS + +#ifdef CONFIG_32BIT +unsigned long __init arch_syscall_addr(int nr) +{ + return (unsigned long)sys_call_table[nr - __NR_O32_Linux]; +} +#endif + +#ifdef CONFIG_64BIT + +unsigned long __init arch_syscall_addr(int nr) +{ +#ifdef CONFIG_MIPS32_N32 + if (nr >= __NR_N32_Linux && nr <= __NR_N32_Linux + __NR_N32_Linux_syscalls) + return (unsigned long)sysn32_call_table[nr - __NR_N32_Linux]; +#endif + if (nr >= __NR_64_Linux && nr <= __NR_64_Linux + __NR_64_Linux_syscalls) + return (unsigned long)sys_call_table[nr - __NR_64_Linux]; +#ifdef CONFIG_MIPS32_O32 + if (nr >= __NR_O32_Linux && nr <= __NR_O32_Linux + __NR_O32_Linux_syscalls) + return (unsigned long)sys32_call_table[nr - __NR_O32_Linux]; +#endif + + return (unsigned long) &sys_ni_syscall; +} +#endif + +#endif /* CONFIG_FTRACE_SYSCALLS */ diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index 31fa856829cb..47d7583cd67f 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -374,12 +374,20 @@ NESTED(except_vec_nmi, 0, sp) NESTED(nmi_handler, PT_SIZE, sp) .set push .set noat + /* + * Clear ERL - restore segment mapping + * Clear BEV - required for page fault exception handler to work + */ + mfc0 k0, CP0_STATUS + ori k0, k0, ST0_EXL + li k1, ~(ST0_BEV | ST0_ERL) + and k0, k0, k1 + mtc0 k0, CP0_STATUS + _ehb SAVE_ALL move a0, sp jal nmi_exception_handler - RESTORE_ALL - .set mips3 - eret + /* nmi_exception_handler never returns */ .set pop END(nmi_handler) diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c index 0c655deeea4a..f7991d95bff9 100644 --- a/arch/mips/kernel/idle.c +++ b/arch/mips/kernel/idle.c @@ -18,6 +18,7 @@ #include <linux/sched.h> #include <asm/cpu.h> #include <asm/cpu-info.h> +#include <asm/cpu-type.h> #include <asm/idle.h> #include <asm/mipsregs.h> @@ -136,7 +137,7 @@ void __init check_wait(void) return; } - switch (c->cputype) { + switch (current_cpu_type()) { case CPU_R3081: case CPU_R3081E: cpu_wait = r3081_wait; @@ -166,6 +167,7 @@ void __init check_wait(void) case CPU_CAVIUM_OCTEON: case CPU_CAVIUM_OCTEON_PLUS: case CPU_CAVIUM_OCTEON2: + case CPU_CAVIUM_OCTEON3: case CPU_JZRISC: case CPU_LOONGSON1: case CPU_XLR: diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index 72ef2d25cbf2..e498f2b3646a 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c @@ -150,7 +150,7 @@ int __init mips_cpu_intc_init(struct device_node *of_node, domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0, &mips_cpu_intc_irq_domain_ops, NULL); if (!domain) - panic("Failed to add irqdomain for MIPS CPU\n"); + panic("Failed to add irqdomain for MIPS CPU"); return 0; } diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S index a03e93c4a946..539b6294b613 100644 --- a/arch/mips/kernel/mcount.S +++ b/arch/mips/kernel/mcount.S @@ -83,7 +83,7 @@ _mcount: PTR_S MCOUNT_RA_ADDRESS_REG, PT_R12(sp) #endif - move a0, ra /* arg1: self return address */ + PTR_SUBU a0, ra, 8 /* arg1: self address */ .globl ftrace_call ftrace_call: nop /* a placeholder for the call to a real tracing function */ diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c index 977a623d9253..2a52568dbcd6 100644 --- a/arch/mips/kernel/module.c +++ b/arch/mips/kernel/module.c @@ -23,6 +23,7 @@ #include <linux/moduleloader.h> #include <linux/elf.h> #include <linux/mm.h> +#include <linux/numa.h> #include <linux/vmalloc.h> #include <linux/slab.h> #include <linux/fs.h> @@ -46,7 +47,7 @@ static DEFINE_SPINLOCK(dbe_lock); void *module_alloc(unsigned long size) { return __vmalloc_node_range(size, 1, MODULE_START, MODULE_END, - GFP_KERNEL, PAGE_KERNEL, -1, + GFP_KERNEL, PAGE_KERNEL, NUMA_NO_NODE, __builtin_return_address(0)); } #endif diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S index 4204d76af854..029e002a4ea0 100644 --- a/arch/mips/kernel/octeon_switch.S +++ b/arch/mips/kernel/octeon_switch.S @@ -73,7 +73,7 @@ 3: #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) - PTR_L t8, __stack_chk_guard + PTR_LA t8, __stack_chk_guard LONG_L t9, TASK_STACK_CANARY(a1) LONG_S t9, 0(t8) #endif diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 45f1ffcf1a4b..24cdf64789c3 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -971,11 +971,11 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map [C(LL)] = { [C(OP_READ)] = { [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, - [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P }, + [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P }, }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, - [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P }, + [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P }, }, }, [C(ITLB)] = { diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c index 7e954042f252..3c3b0df8f48d 100644 --- a/arch/mips/kernel/prom.c +++ b/arch/mips/kernel/prom.c @@ -13,12 +13,9 @@ #include <linux/errno.h> #include <linux/types.h> #include <linux/bootmem.h> -#include <linux/initrd.h> #include <linux/debugfs.h> #include <linux/of.h> #include <linux/of_fdt.h> -#include <linux/of_irq.h> -#include <linux/of_platform.h> #include <asm/page.h> #include <asm/prom.h> @@ -40,13 +37,6 @@ char *mips_get_machine_name(void) } #ifdef CONFIG_OF -int __init early_init_dt_scan_memory_arch(unsigned long node, - const char *uname, int depth, - void *data) -{ - return early_init_dt_scan_memory(node, uname, depth, data); -} - void __init early_init_dt_add_memory_arch(u64 base, u64 size) { return add_memory_region(base, size, BOOT_MEM_RAM); @@ -57,58 +47,11 @@ void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS)); } -#ifdef CONFIG_BLK_DEV_INITRD -void __init early_init_dt_setup_initrd_arch(unsigned long start, - unsigned long end) -{ - initrd_start = (unsigned long)__va(start); - initrd_end = (unsigned long)__va(end); - initrd_below_start_ok = 1; -} -#endif - -int __init early_init_dt_scan_model(unsigned long node, const char *uname, - int depth, void *data) -{ - if (!depth) { - char *model = of_get_flat_dt_prop(node, "model", NULL); - - if (model) - mips_set_machine_name(model); - } - return 0; -} - -void __init early_init_devtree(void *params) -{ - /* Setup flat device-tree pointer */ - initial_boot_params = params; - - /* Retrieve various informations from the /chosen node of the - * device-tree, including the platform type, initrd location and - * size, and more ... - */ - of_scan_flat_dt(early_init_dt_scan_chosen, arcs_cmdline); - - - /* Scan memory nodes */ - of_scan_flat_dt(early_init_dt_scan_root, NULL); - of_scan_flat_dt(early_init_dt_scan_memory_arch, NULL); - - /* try to load the mips machine name */ - of_scan_flat_dt(early_init_dt_scan_model, NULL); -} - void __init __dt_setup_arch(struct boot_param_header *bph) { - if (be32_to_cpu(bph->magic) != OF_DT_HEADER) { - pr_err("DTB has bad magic, ignoring builtin OF DTB\n"); - + if (!early_init_dt_scan(bph)) return; - } - - initial_boot_params = bph; - early_init_devtree(initial_boot_params); + mips_set_machine_name(of_flat_dt_get_machine_name()); } #endif diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 8ae1ebef8b71..b52e1d2b33e0 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -16,16 +16,20 @@ */ #include <linux/compiler.h> #include <linux/context_tracking.h> +#include <linux/elf.h> #include <linux/kernel.h> #include <linux/sched.h> #include <linux/mm.h> #include <linux/errno.h> #include <linux/ptrace.h> +#include <linux/regset.h> #include <linux/smp.h> #include <linux/user.h> #include <linux/security.h> +#include <linux/tracehook.h> #include <linux/audit.h> #include <linux/seccomp.h> +#include <linux/ftrace.h> #include <asm/byteorder.h> #include <asm/cpu.h> @@ -35,10 +39,14 @@ #include <asm/mipsmtregs.h> #include <asm/pgtable.h> #include <asm/page.h> +#include <asm/syscall.h> #include <asm/uaccess.h> #include <asm/bootinfo.h> #include <asm/reg.h> +#define CREATE_TRACE_POINTS +#include <trace/events/syscalls.h> + /* * Called by kernel/ptrace.c when detaching.. * @@ -255,6 +263,133 @@ int ptrace_set_watch_regs(struct task_struct *child, return 0; } +/* regset get/set implementations */ + +static int gpr_get(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + void *kbuf, void __user *ubuf) +{ + struct pt_regs *regs = task_pt_regs(target); + + return user_regset_copyout(&pos, &count, &kbuf, &ubuf, + regs, 0, sizeof(*regs)); +} + +static int gpr_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + struct pt_regs newregs; + int ret; + + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, + &newregs, + 0, sizeof(newregs)); + if (ret) + return ret; + + *task_pt_regs(target) = newregs; + + return 0; +} + +static int fpr_get(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + void *kbuf, void __user *ubuf) +{ + return user_regset_copyout(&pos, &count, &kbuf, &ubuf, + &target->thread.fpu, + 0, sizeof(elf_fpregset_t)); + /* XXX fcr31 */ +} + +static int fpr_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + return user_regset_copyin(&pos, &count, &kbuf, &ubuf, + &target->thread.fpu, + 0, sizeof(elf_fpregset_t)); + /* XXX fcr31 */ +} + +enum mips_regset { + REGSET_GPR, + REGSET_FPR, +}; + +static const struct user_regset mips_regsets[] = { + [REGSET_GPR] = { + .core_note_type = NT_PRSTATUS, + .n = ELF_NGREG, + .size = sizeof(unsigned int), + .align = sizeof(unsigned int), + .get = gpr_get, + .set = gpr_set, + }, + [REGSET_FPR] = { + .core_note_type = NT_PRFPREG, + .n = ELF_NFPREG, + .size = sizeof(elf_fpreg_t), + .align = sizeof(elf_fpreg_t), + .get = fpr_get, + .set = fpr_set, + }, +}; + +static const struct user_regset_view user_mips_view = { + .name = "mips", + .e_machine = ELF_ARCH, + .ei_osabi = ELF_OSABI, + .regsets = mips_regsets, + .n = ARRAY_SIZE(mips_regsets), +}; + +static const struct user_regset mips64_regsets[] = { + [REGSET_GPR] = { + .core_note_type = NT_PRSTATUS, + .n = ELF_NGREG, + .size = sizeof(unsigned long), + .align = sizeof(unsigned long), + .get = gpr_get, + .set = gpr_set, + }, + [REGSET_FPR] = { + .core_note_type = NT_PRFPREG, + .n = ELF_NFPREG, + .size = sizeof(elf_fpreg_t), + .align = sizeof(elf_fpreg_t), + .get = fpr_get, + .set = fpr_set, + }, +}; + +static const struct user_regset_view user_mips64_view = { + .name = "mips", + .e_machine = ELF_ARCH, + .ei_osabi = ELF_OSABI, + .regsets = mips64_regsets, + .n = ARRAY_SIZE(mips_regsets), +}; + +const struct user_regset_view *task_user_regset_view(struct task_struct *task) +{ +#ifdef CONFIG_32BIT + return &user_mips_view; +#endif + +#ifdef CONFIG_MIPS32_O32 + if (test_thread_flag(TIF_32BIT_REGS)) + return &user_mips_view; +#endif + + return &user_mips64_view; +} + long arch_ptrace(struct task_struct *child, long request, unsigned long addr, unsigned long data) { @@ -517,52 +652,27 @@ long arch_ptrace(struct task_struct *child, long request, return ret; } -static inline int audit_arch(void) -{ - int arch = EM_MIPS; -#ifdef CONFIG_64BIT - arch |= __AUDIT_ARCH_64BIT; -#endif -#if defined(__LITTLE_ENDIAN) - arch |= __AUDIT_ARCH_LE; -#endif - return arch; -} - /* * Notification of system call entry/exit * - triggered by current->work.syscall_trace */ asmlinkage void syscall_trace_enter(struct pt_regs *regs) { + long ret = 0; user_exit(); /* do the secure computing check first */ secure_computing_strict(regs->regs[2]); - if (!(current->ptrace & PT_PTRACED)) - goto out; - - if (!test_thread_flag(TIF_SYSCALL_TRACE)) - goto out; + if (test_thread_flag(TIF_SYSCALL_TRACE) && + tracehook_report_syscall_entry(regs)) + ret = -1; - /* The 0x80 provides a way for the tracing parent to distinguish - between a syscall stop and SIGTRAP delivery */ - ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ? - 0x80 : 0)); - - /* - * this isn't the same as continuing with a signal, but it will do - * for normal use. strace only continues with a signal if the - * stopping signal is not SIGTRAP. -brl - */ - if (current->exit_code) { - send_sig(current->exit_code, current, 1); - current->exit_code = 0; - } + if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) + trace_sys_enter(regs, regs->regs[2]); -out: - audit_syscall_entry(audit_arch(), regs->regs[2], + audit_syscall_entry(__syscall_get_arch(), + regs->regs[2], regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]); } @@ -582,26 +692,11 @@ asmlinkage void syscall_trace_leave(struct pt_regs *regs) audit_syscall_exit(regs); - if (!(current->ptrace & PT_PTRACED)) - return; - - if (!test_thread_flag(TIF_SYSCALL_TRACE)) - return; - - /* The 0x80 provides a way for the tracing parent to distinguish - between a syscall stop and SIGTRAP delivery */ - ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ? - 0x80 : 0)); + if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) + trace_sys_exit(regs, regs->regs[2]); - /* - * this isn't the same as continuing with a signal, but it will do - * for normal use. strace only continues with a signal if the - * stopping signal is not SIGTRAP. -brl - */ - if (current->exit_code) { - send_sig(current->exit_code, current, 1); - current->exit_code = 0; - } + if (test_thread_flag(TIF_SYSCALL_TRACE)) + tracehook_report_syscall_exit(regs, 0); user_enter(); } diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S index 38af83f84c4a..20b7b040e76f 100644 --- a/arch/mips/kernel/r2300_switch.S +++ b/arch/mips/kernel/r2300_switch.S @@ -67,7 +67,7 @@ LEAF(resume) 1: #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) - PTR_L t8, __stack_chk_guard + PTR_LA t8, __stack_chk_guard LONG_L t9, TASK_STACK_CANARY(a1) LONG_S t9, 0(t8) #endif diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S index 921238a6bd26..078de5eaca8f 100644 --- a/arch/mips/kernel/r4k_switch.S +++ b/arch/mips/kernel/r4k_switch.S @@ -69,7 +69,7 @@ 1: #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) - PTR_L t8, __stack_chk_guard + PTR_LA t8, __stack_chk_guard LONG_L t9, TASK_STACK_CANARY(a1) LONG_S t9, 0(t8) #endif diff --git a/arch/mips/kernel/relocate_kernel.S b/arch/mips/kernel/relocate_kernel.S index 43d2d78d3287..74bab9ddd0e1 100644 --- a/arch/mips/kernel/relocate_kernel.S +++ b/arch/mips/kernel/relocate_kernel.S @@ -26,6 +26,12 @@ process_entry: PTR_L s2, (s0) PTR_ADD s0, s0, SZREG + /* + * In case of a kdump/crash kernel, the indirection page is not + * populated as the kernel is directly copied to a reserved location + */ + beqz s2, done + /* destination page */ and s3, s2, 0x1 beq s3, zero, 1f diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c index d763f11e35e2..2c12ea1668d1 100644 --- a/arch/mips/kernel/rtlx.c +++ b/arch/mips/kernel/rtlx.c @@ -172,8 +172,9 @@ int rtlx_open(int index, int can_sleep) if (rtlx == NULL) { if( (p = vpe_get_shared(tclimit)) == NULL) { if (can_sleep) { - __wait_event_interruptible(channel_wqs[index].lx_queue, - (p = vpe_get_shared(tclimit)), ret); + ret = __wait_event_interruptible( + channel_wqs[index].lx_queue, + (p = vpe_get_shared(tclimit))); if (ret) goto out_fail; } else { @@ -263,11 +264,10 @@ unsigned int rtlx_read_poll(int index, int can_sleep) /* data available to read? */ if (chan->lx_read == chan->lx_write) { if (can_sleep) { - int ret = 0; - - __wait_event_interruptible(channel_wqs[index].lx_queue, + int ret = __wait_event_interruptible( + channel_wqs[index].lx_queue, (chan->lx_read != chan->lx_write) || - sp_stopping, ret); + sp_stopping); if (ret) return ret; @@ -440,14 +440,13 @@ static ssize_t file_write(struct file *file, const char __user * buffer, /* any space left... */ if (!rtlx_write_poll(minor)) { - int ret = 0; + int ret; if (file->f_flags & O_NONBLOCK) return -EAGAIN; - __wait_event_interruptible(channel_wqs[minor].rt_queue, - rtlx_write_poll(minor), - ret); + ret = __wait_event_interruptible(channel_wqs[minor].rt_queue, + rtlx_write_poll(minor)); if (ret) return ret; } diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index e774bb1088b5..e8e541b40d86 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -40,17 +40,58 @@ NESTED(handle_sys, PT_SIZE, sp) sw t1, PT_EPC(sp) beqz t0, illegal_syscall - sll t0, v0, 3 + sll t0, v0, 2 la t1, sys_call_table addu t1, t0 lw t2, (t1) # syscall routine - lw t3, 4(t1) # >= 0 if we need stack arguments beqz t2, illegal_syscall sw a3, PT_R26(sp) # save a3 for syscall restarting - bgez t3, stackargs -stack_done: + /* + * More than four arguments. Try to deal with it by copying the + * stack arguments from the user stack to the kernel stack. + * This Sucks (TM). + */ + lw t0, PT_R29(sp) # get old user stack pointer + + /* + * We intentionally keep the kernel stack a little below the top of + * userspace so we don't have to do a slower byte accurate check here. + */ + lw t5, TI_ADDR_LIMIT($28) + addu t4, t0, 32 + and t5, t4 + bltz t5, bad_stack # -> sp is bad + + /* + * Ok, copy the args from the luser stack to the kernel stack. + * t3 is the precomputed number of instruction bytes needed to + * load or store arguments 6-8. + */ + + .set push + .set noreorder + .set nomacro + +1: lw t5, 16(t0) # argument #5 from usp +4: lw t6, 20(t0) # argument #6 from usp +3: lw t7, 24(t0) # argument #7 from usp +2: lw t8, 28(t0) # argument #8 from usp + + sw t5, 16(sp) # argument #5 to ksp + sw t6, 20(sp) # argument #6 to ksp + sw t7, 24(sp) # argument #7 to ksp + sw t8, 28(sp) # argument #8 to ksp + .set pop + + .section __ex_table,"a" + PTR 1b,bad_stack + PTR 2b,bad_stack + PTR 3b,bad_stack + PTR 4b,bad_stack + .previous + lw t0, TI_FLAGS($28) # syscall tracing enabled? li t1, _TIF_WORK_SYSCALL_ENTRY and t0, t1 @@ -102,66 +143,6 @@ syscall_trace_entry: /* ------------------------------------------------------------------------ */ /* - * More than four arguments. Try to deal with it by copying the - * stack arguments from the user stack to the kernel stack. - * This Sucks (TM). - */ -stackargs: - lw t0, PT_R29(sp) # get old user stack pointer - - /* - * We intentionally keep the kernel stack a little below the top of - * userspace so we don't have to do a slower byte accurate check here. - */ - lw t5, TI_ADDR_LIMIT($28) - addu t4, t0, 32 - and t5, t4 - bltz t5, bad_stack # -> sp is bad - - /* Ok, copy the args from the luser stack to the kernel stack. - * t3 is the precomputed number of instruction bytes needed to - * load or store arguments 6-8. - */ - - la t1, 5f # load up to 3 arguments - subu t1, t3 -1: lw t5, 16(t0) # argument #5 from usp - .set push - .set noreorder - .set nomacro - jr t1 - addiu t1, 6f - 5f - -2: lw t8, 28(t0) # argument #8 from usp -3: lw t7, 24(t0) # argument #7 from usp -4: lw t6, 20(t0) # argument #6 from usp -5: jr t1 - sw t5, 16(sp) # argument #5 to ksp - -#ifdef CONFIG_CPU_MICROMIPS - sw t8, 28(sp) # argument #8 to ksp - nop - sw t7, 24(sp) # argument #7 to ksp - nop - sw t6, 20(sp) # argument #6 to ksp - nop -#else - sw t8, 28(sp) # argument #8 to ksp - sw t7, 24(sp) # argument #7 to ksp - sw t6, 20(sp) # argument #6 to ksp -#endif -6: j stack_done # go back - nop - .set pop - - .section __ex_table,"a" - PTR 1b,bad_stack - PTR 2b,bad_stack - PTR 3b,bad_stack - PTR 4b,bad_stack - .previous - - /* * The stackpointer for a call with more than 4 arguments is bad. * We probably should handle this case a bit more drastic. */ @@ -187,7 +168,7 @@ illegal_syscall: subu t0, a0, __NR_O32_Linux # check syscall number sltiu v0, t0, __NR_O32_Linux_syscalls + 1 beqz t0, einval # do not recurse - sll t1, t0, 3 + sll t1, t0, 2 beqz v0, einval lw t2, sys_call_table(t1) # syscall routine @@ -218,260 +199,248 @@ einval: li v0, -ENOSYS jr ra END(sys_syscall) - .macro fifty ptr, nargs, from=1, to=50 - sys \ptr \nargs - .if \to-\from - fifty \ptr,\nargs,"(\from+1)",\to - .endif - .endm - - .macro mille ptr, nargs, from=1, to=20 - fifty \ptr,\nargs - .if \to-\from - mille \ptr,\nargs,"(\from+1)",\to - .endif - .endm - - .macro syscalltable - sys sys_syscall 8 /* 4000 */ - sys sys_exit 1 - sys __sys_fork 0 - sys sys_read 3 - sys sys_write 3 - sys sys_open 3 /* 4005 */ - sys sys_close 1 - sys sys_waitpid 3 - sys sys_creat 2 - sys sys_link 2 - sys sys_unlink 1 /* 4010 */ - sys sys_execve 0 - sys sys_chdir 1 - sys sys_time 1 - sys sys_mknod 3 - sys sys_chmod 2 /* 4015 */ - sys sys_lchown 3 - sys sys_ni_syscall 0 - sys sys_ni_syscall 0 /* was sys_stat */ - sys sys_lseek 3 - sys sys_getpid 0 /* 4020 */ - sys sys_mount 5 - sys sys_oldumount 1 - sys sys_setuid 1 - sys sys_getuid 0 - sys sys_stime 1 /* 4025 */ - sys sys_ptrace 4 - sys sys_alarm 1 - sys sys_ni_syscall 0 /* was sys_fstat */ - sys sys_pause 0 - sys sys_utime 2 /* 4030 */ - sys sys_ni_syscall 0 - sys sys_ni_syscall 0 - sys sys_access 2 - sys sys_nice 1 - sys sys_ni_syscall 0 /* 4035 */ - sys sys_sync 0 - sys sys_kill 2 - sys sys_rename 2 - sys sys_mkdir 2 - sys sys_rmdir 1 /* 4040 */ - sys sys_dup 1 - sys sysm_pipe 0 - sys sys_times 1 - sys sys_ni_syscall 0 - sys sys_brk 1 /* 4045 */ - sys sys_setgid 1 - sys sys_getgid 0 - sys sys_ni_syscall 0 /* was signal(2) */ - sys sys_geteuid 0 - sys sys_getegid 0 /* 4050 */ - sys sys_acct 1 - sys sys_umount 2 - sys sys_ni_syscall 0 - sys sys_ioctl 3 - sys sys_fcntl 3 /* 4055 */ - sys sys_ni_syscall 2 - sys sys_setpgid 2 - sys sys_ni_syscall 0 - sys sys_olduname 1 - sys sys_umask 1 /* 4060 */ - sys sys_chroot 1 - sys sys_ustat 2 - sys sys_dup2 2 - sys sys_getppid 0 - sys sys_getpgrp 0 /* 4065 */ - sys sys_setsid 0 - sys sys_sigaction 3 - sys sys_sgetmask 0 - sys sys_ssetmask 1 - sys sys_setreuid 2 /* 4070 */ - sys sys_setregid 2 - sys sys_sigsuspend 0 - sys sys_sigpending 1 - sys sys_sethostname 2 - sys sys_setrlimit 2 /* 4075 */ - sys sys_getrlimit 2 - sys sys_getrusage 2 - sys sys_gettimeofday 2 - sys sys_settimeofday 2 - sys sys_getgroups 2 /* 4080 */ - sys sys_setgroups 2 - sys sys_ni_syscall 0 /* old_select */ - sys sys_symlink 2 - sys sys_ni_syscall 0 /* was sys_lstat */ - sys sys_readlink 3 /* 4085 */ - sys sys_uselib 1 - sys sys_swapon 2 - sys sys_reboot 3 - sys sys_old_readdir 3 - sys sys_mips_mmap 6 /* 4090 */ - sys sys_munmap 2 - sys sys_truncate 2 - sys sys_ftruncate 2 - sys sys_fchmod 2 - sys sys_fchown 3 /* 4095 */ - sys sys_getpriority 2 - sys sys_setpriority 3 - sys sys_ni_syscall 0 - sys sys_statfs 2 - sys sys_fstatfs 2 /* 4100 */ - sys sys_ni_syscall 0 /* was ioperm(2) */ - sys sys_socketcall 2 - sys sys_syslog 3 - sys sys_setitimer 3 - sys sys_getitimer 2 /* 4105 */ - sys sys_newstat 2 - sys sys_newlstat 2 - sys sys_newfstat 2 - sys sys_uname 1 - sys sys_ni_syscall 0 /* 4110 was iopl(2) */ - sys sys_vhangup 0 - sys sys_ni_syscall 0 /* was sys_idle() */ - sys sys_ni_syscall 0 /* was sys_vm86 */ - sys sys_wait4 4 - sys sys_swapoff 1 /* 4115 */ - sys sys_sysinfo 1 - sys sys_ipc 6 - sys sys_fsync 1 - sys sys_sigreturn 0 - sys __sys_clone 6 /* 4120 */ - sys sys_setdomainname 2 - sys sys_newuname 1 - sys sys_ni_syscall 0 /* sys_modify_ldt */ - sys sys_adjtimex 1 - sys sys_mprotect 3 /* 4125 */ - sys sys_sigprocmask 3 - sys sys_ni_syscall 0 /* was create_module */ - sys sys_init_module 5 - sys sys_delete_module 1 - sys sys_ni_syscall 0 /* 4130 was get_kernel_syms */ - sys sys_quotactl 4 - sys sys_getpgid 1 - sys sys_fchdir 1 - sys sys_bdflush 2 - sys sys_sysfs 3 /* 4135 */ - sys sys_personality 1 - sys sys_ni_syscall 0 /* for afs_syscall */ - sys sys_setfsuid 1 - sys sys_setfsgid 1 - sys sys_llseek 5 /* 4140 */ - sys sys_getdents 3 - sys sys_select 5 - sys sys_flock 2 - sys sys_msync 3 - sys sys_readv 3 /* 4145 */ - sys sys_writev 3 - sys sys_cacheflush 3 - sys sys_cachectl 3 - sys sys_sysmips 4 - sys sys_ni_syscall 0 /* 4150 */ - sys sys_getsid 1 - sys sys_fdatasync 1 - sys sys_sysctl 1 - sys sys_mlock 2 - sys sys_munlock 2 /* 4155 */ - sys sys_mlockall 1 - sys sys_munlockall 0 - sys sys_sched_setparam 2 - sys sys_sched_getparam 2 - sys sys_sched_setscheduler 3 /* 4160 */ - sys sys_sched_getscheduler 1 - sys sys_sched_yield 0 - sys sys_sched_get_priority_max 1 - sys sys_sched_get_priority_min 1 - sys sys_sched_rr_get_interval 2 /* 4165 */ - sys sys_nanosleep, 2 - sys sys_mremap, 5 - sys sys_accept 3 - sys sys_bind 3 - sys sys_connect 3 /* 4170 */ - sys sys_getpeername 3 - sys sys_getsockname 3 - sys sys_getsockopt 5 - sys sys_listen 2 - sys sys_recv 4 /* 4175 */ - sys sys_recvfrom 6 - sys sys_recvmsg 3 - sys sys_send 4 - sys sys_sendmsg 3 - sys sys_sendto 6 /* 4180 */ - sys sys_setsockopt 5 - sys sys_shutdown 2 - sys sys_socket 3 - sys sys_socketpair 4 - sys sys_setresuid 3 /* 4185 */ - sys sys_getresuid 3 - sys sys_ni_syscall 0 /* was sys_query_module */ - sys sys_poll 3 - sys sys_ni_syscall 0 /* was nfsservctl */ - sys sys_setresgid 3 /* 4190 */ - sys sys_getresgid 3 - sys sys_prctl 5 - sys sys_rt_sigreturn 0 - sys sys_rt_sigaction 4 - sys sys_rt_sigprocmask 4 /* 4195 */ - sys sys_rt_sigpending 2 - sys sys_rt_sigtimedwait 4 - sys sys_rt_sigqueueinfo 3 - sys sys_rt_sigsuspend 0 - sys sys_pread64 6 /* 4200 */ - sys sys_pwrite64 6 - sys sys_chown 3 - sys sys_getcwd 2 - sys sys_capget 2 - sys sys_capset 2 /* 4205 */ - sys sys_sigaltstack 0 - sys sys_sendfile 4 - sys sys_ni_syscall 0 - sys sys_ni_syscall 0 - sys sys_mips_mmap2 6 /* 4210 */ - sys sys_truncate64 4 - sys sys_ftruncate64 4 - sys sys_stat64 2 - sys sys_lstat64 2 - sys sys_fstat64 2 /* 4215 */ - sys sys_pivot_root 2 - sys sys_mincore 3 - sys sys_madvise 3 - sys sys_getdents64 3 - sys sys_fcntl64 3 /* 4220 */ - sys sys_ni_syscall 0 - sys sys_gettid 0 - sys sys_readahead 5 - sys sys_setxattr 5 - sys sys_lsetxattr 5 /* 4225 */ - sys sys_fsetxattr 5 - sys sys_getxattr 4 - sys sys_lgetxattr 4 - sys sys_fgetxattr 4 - sys sys_listxattr 3 /* 4230 */ - sys sys_llistxattr 3 - sys sys_flistxattr 3 - sys sys_removexattr 2 - sys sys_lremovexattr 2 - sys sys_fremovexattr 2 /* 4235 */ - sys sys_tkill 2 - sys sys_sendfile64 5 - sys sys_futex 6 + .align 2 + .type sys_call_table, @object +EXPORT(sys_call_table) + PTR sys_syscall /* 4000 */ + PTR sys_exit + PTR __sys_fork + PTR sys_read + PTR sys_write + PTR sys_open /* 4005 */ + PTR sys_close + PTR sys_waitpid + PTR sys_creat + PTR sys_link + PTR sys_unlink /* 4010 */ + PTR sys_execve + PTR sys_chdir + PTR sys_time + PTR sys_mknod + PTR sys_chmod /* 4015 */ + PTR sys_lchown + PTR sys_ni_syscall + PTR sys_ni_syscall /* was sys_stat */ + PTR sys_lseek + PTR sys_getpid /* 4020 */ + PTR sys_mount + PTR sys_oldumount + PTR sys_setuid + PTR sys_getuid + PTR sys_stime /* 4025 */ + PTR sys_ptrace + PTR sys_alarm + PTR sys_ni_syscall /* was sys_fstat */ + PTR sys_pause + PTR sys_utime /* 4030 */ + PTR sys_ni_syscall + PTR sys_ni_syscall + PTR sys_access + PTR sys_nice + PTR sys_ni_syscall /* 4035 */ + PTR sys_sync + PTR sys_kill + PTR sys_rename + PTR sys_mkdir + PTR sys_rmdir /* 4040 */ + PTR sys_dup + PTR sysm_pipe + PTR sys_times + PTR sys_ni_syscall + PTR sys_brk /* 4045 */ + PTR sys_setgid + PTR sys_getgid + PTR sys_ni_syscall /* was signal(2) */ + PTR sys_geteuid + PTR sys_getegid /* 4050 */ + PTR sys_acct + PTR sys_umount + PTR sys_ni_syscall + PTR sys_ioctl + PTR sys_fcntl /* 4055 */ + PTR sys_ni_syscall + PTR sys_setpgid + PTR sys_ni_syscall + PTR sys_olduname + PTR sys_umask /* 4060 */ + PTR sys_chroot + PTR sys_ustat + PTR sys_dup2 + PTR sys_getppid + PTR sys_getpgrp /* 4065 */ + PTR sys_setsid + PTR sys_sigaction + PTR sys_sgetmask + PTR sys_ssetmask + PTR sys_setreuid /* 4070 */ + PTR sys_setregid + PTR sys_sigsuspend + PTR sys_sigpending + PTR sys_sethostname + PTR sys_setrlimit /* 4075 */ + PTR sys_getrlimit + PTR sys_getrusage + PTR sys_gettimeofday + PTR sys_settimeofday + PTR sys_getgroups /* 4080 */ + PTR sys_setgroups + PTR sys_ni_syscall /* old_select */ + PTR sys_symlink + PTR sys_ni_syscall /* was sys_lstat */ + PTR sys_readlink /* 4085 */ + PTR sys_uselib + PTR sys_swapon + PTR sys_reboot + PTR sys_old_readdir + PTR sys_mips_mmap /* 4090 */ + PTR sys_munmap + PTR sys_truncate + PTR sys_ftruncate + PTR sys_fchmod + PTR sys_fchown /* 4095 */ + PTR sys_getpriority + PTR sys_setpriority + PTR sys_ni_syscall + PTR sys_statfs + PTR sys_fstatfs /* 4100 */ + PTR sys_ni_syscall /* was ioperm(2) */ + PTR sys_socketcall + PTR sys_syslog + PTR sys_setitimer + PTR sys_getitimer /* 4105 */ + PTR sys_newstat + PTR sys_newlstat + PTR sys_newfstat + PTR sys_uname + PTR sys_ni_syscall /* 4110 was iopl(2) */ + PTR sys_vhangup + PTR sys_ni_syscall /* was sys_idle() */ + PTR sys_ni_syscall /* was sys_vm86 */ + PTR sys_wait4 + PTR sys_swapoff /* 4115 */ + PTR sys_sysinfo + PTR sys_ipc + PTR sys_fsync + PTR sys_sigreturn + PTR __sys_clone /* 4120 */ + PTR sys_setdomainname + PTR sys_newuname + PTR sys_ni_syscall /* sys_modify_ldt */ + PTR sys_adjtimex + PTR sys_mprotect /* 4125 */ + PTR sys_sigprocmask + PTR sys_ni_syscall /* was create_module */ + PTR sys_init_module + PTR sys_delete_module + PTR sys_ni_syscall /* 4130 was get_kernel_syms */ + PTR sys_quotactl + PTR sys_getpgid + PTR sys_fchdir + PTR sys_bdflush + PTR sys_sysfs /* 4135 */ + PTR sys_personality + PTR sys_ni_syscall /* for afs_syscall */ + PTR sys_setfsuid + PTR sys_setfsgid + PTR sys_llseek /* 4140 */ + PTR sys_getdents + PTR sys_select + PTR sys_flock + PTR sys_msync + PTR sys_readv /* 4145 */ + PTR sys_writev + PTR sys_cacheflush + PTR sys_cachectl + PTR sys_sysmips + PTR sys_ni_syscall /* 4150 */ + PTR sys_getsid + PTR sys_fdatasync + PTR sys_sysctl + PTR sys_mlock + PTR sys_munlock /* 4155 */ + PTR sys_mlockall + PTR sys_munlockall + PTR sys_sched_setparam + PTR sys_sched_getparam + PTR sys_sched_setscheduler /* 4160 */ + PTR sys_sched_getscheduler + PTR sys_sched_yield + PTR sys_sched_get_priority_max + PTR sys_sched_get_priority_min + PTR sys_sched_rr_get_interval /* 4165 */ + PTR sys_nanosleep + PTR sys_mremap + PTR sys_accept + PTR sys_bind + PTR sys_connect /* 4170 */ + PTR sys_getpeername + PTR sys_getsockname + PTR sys_getsockopt + PTR sys_listen + PTR sys_recv /* 4175 */ + PTR sys_recvfrom + PTR sys_recvmsg + PTR sys_send + PTR sys_sendmsg + PTR sys_sendto /* 4180 */ + PTR sys_setsockopt + PTR sys_shutdown + PTR sys_socket + PTR sys_socketpair + PTR sys_setresuid /* 4185 */ + PTR sys_getresuid + PTR sys_ni_syscall /* was sys_query_module */ + PTR sys_poll + PTR sys_ni_syscall /* was nfsservctl */ + PTR sys_setresgid /* 4190 */ + PTR sys_getresgid + PTR sys_prctl + PTR sys_rt_sigreturn + PTR sys_rt_sigaction + PTR sys_rt_sigprocmask /* 4195 */ + PTR sys_rt_sigpending + PTR sys_rt_sigtimedwait + PTR sys_rt_sigqueueinfo + PTR sys_rt_sigsuspend + PTR sys_pread64 /* 4200 */ + PTR sys_pwrite64 + PTR sys_chown + PTR sys_getcwd + PTR sys_capget + PTR sys_capset /* 4205 */ + PTR sys_sigaltstack + PTR sys_sendfile + PTR sys_ni_syscall + PTR sys_ni_syscall + PTR sys_mips_mmap2 /* 4210 */ + PTR sys_truncate64 + PTR sys_ftruncate64 + PTR sys_stat64 + PTR sys_lstat64 + PTR sys_fstat64 /* 4215 */ + PTR sys_pivot_root + PTR sys_mincore + PTR sys_madvise + PTR sys_getdents64 + PTR sys_fcntl64 /* 4220 */ + PTR sys_ni_syscall + PTR sys_gettid + PTR sys_readahead + PTR sys_setxattr + PTR sys_lsetxattr /* 4225 */ + PTR sys_fsetxattr + PTR sys_getxattr + PTR sys_lgetxattr + PTR sys_fgetxattr + PTR sys_listxattr /* 4230 */ + PTR sys_llistxattr + PTR sys_flistxattr + PTR sys_removexattr + PTR sys_lremovexattr + PTR sys_fremovexattr /* 4235 */ + PTR sys_tkill + PTR sys_sendfile64 + PTR sys_futex #ifdef CONFIG_MIPS_MT_FPAFF /* * For FPU affinity scheduling on MIPS MT processors, we need to @@ -480,132 +449,117 @@ einval: li v0, -ENOSYS * these hooks for the 32-bit kernel - there is no MIPS64 MT processor * atm. */ - sys mipsmt_sys_sched_setaffinity 3 - sys mipsmt_sys_sched_getaffinity 3 + PTR mipsmt_sys_sched_setaffinity + PTR mipsmt_sys_sched_getaffinity #else - sys sys_sched_setaffinity 3 - sys sys_sched_getaffinity 3 /* 4240 */ + PTR sys_sched_setaffinity + PTR sys_sched_getaffinity /* 4240 */ #endif /* CONFIG_MIPS_MT_FPAFF */ - sys sys_io_setup 2 - sys sys_io_destroy 1 - sys sys_io_getevents 5 - sys sys_io_submit 3 - sys sys_io_cancel 3 /* 4245 */ - sys sys_exit_group 1 - sys sys_lookup_dcookie 4 - sys sys_epoll_create 1 - sys sys_epoll_ctl 4 - sys sys_epoll_wait 4 /* 4250 */ - sys sys_remap_file_pages 5 - sys sys_set_tid_address 1 - sys sys_restart_syscall 0 - sys sys_fadvise64_64 7 - sys sys_statfs64 3 /* 4255 */ - sys sys_fstatfs64 2 - sys sys_timer_create 3 - sys sys_timer_settime 4 - sys sys_timer_gettime 2 - sys sys_timer_getoverrun 1 /* 4260 */ - sys sys_timer_delete 1 - sys sys_clock_settime 2 - sys sys_clock_gettime 2 - sys sys_clock_getres 2 - sys sys_clock_nanosleep 4 /* 4265 */ - sys sys_tgkill 3 - sys sys_utimes 2 - sys sys_mbind 4 - sys sys_ni_syscall 0 /* sys_get_mempolicy */ - sys sys_ni_syscall 0 /* 4270 sys_set_mempolicy */ - sys sys_mq_open 4 - sys sys_mq_unlink 1 - sys sys_mq_timedsend 5 - sys sys_mq_timedreceive 5 - sys sys_mq_notify 2 /* 4275 */ - sys sys_mq_getsetattr 3 - sys sys_ni_syscall 0 /* sys_vserver */ - sys sys_waitid 5 - sys sys_ni_syscall 0 /* available, was setaltroot */ - sys sys_add_key 5 /* 4280 */ - sys sys_request_key 4 - sys sys_keyctl 5 - sys sys_set_thread_area 1 - sys sys_inotify_init 0 - sys sys_inotify_add_watch 3 /* 4285 */ - sys sys_inotify_rm_watch 2 - sys sys_migrate_pages 4 - sys sys_openat 4 - sys sys_mkdirat 3 - sys sys_mknodat 4 /* 4290 */ - sys sys_fchownat 5 - sys sys_futimesat 3 - sys sys_fstatat64 4 - sys sys_unlinkat 3 - sys sys_renameat 4 /* 4295 */ - sys sys_linkat 5 - sys sys_symlinkat 3 - sys sys_readlinkat 4 - sys sys_fchmodat 3 - sys sys_faccessat 3 /* 4300 */ - sys sys_pselect6 6 - sys sys_ppoll 5 - sys sys_unshare 1 - sys sys_splice 6 - sys sys_sync_file_range 7 /* 4305 */ - sys sys_tee 4 - sys sys_vmsplice 4 - sys sys_move_pages 6 - sys sys_set_robust_list 2 - sys sys_get_robust_list 3 /* 4310 */ - sys sys_kexec_load 4 - sys sys_getcpu 3 - sys sys_epoll_pwait 6 - sys sys_ioprio_set 3 - sys sys_ioprio_get 2 /* 4315 */ - sys sys_utimensat 4 - sys sys_signalfd 3 - sys sys_ni_syscall 0 /* was timerfd */ - sys sys_eventfd 1 - sys sys_fallocate 6 /* 4320 */ - sys sys_timerfd_create 2 - sys sys_timerfd_gettime 2 - sys sys_timerfd_settime 4 - sys sys_signalfd4 4 - sys sys_eventfd2 2 /* 4325 */ - sys sys_epoll_create1 1 - sys sys_dup3 3 - sys sys_pipe2 2 - sys sys_inotify_init1 1 - sys sys_preadv 6 /* 4330 */ - sys sys_pwritev 6 - sys sys_rt_tgsigqueueinfo 4 - sys sys_perf_event_open 5 - sys sys_accept4 4 - sys sys_recvmmsg 5 /* 4335 */ - sys sys_fanotify_init 2 - sys sys_fanotify_mark 6 - sys sys_prlimit64 4 - sys sys_name_to_handle_at 5 - sys sys_open_by_handle_at 3 /* 4340 */ - sys sys_clock_adjtime 2 - sys sys_syncfs 1 - sys sys_sendmmsg 4 - sys sys_setns 2 - sys sys_process_vm_readv 6 /* 4345 */ - sys sys_process_vm_writev 6 - sys sys_kcmp 5 - sys sys_finit_module 3 - .endm - - /* We pre-compute the number of _instruction_ bytes needed to - load or store the arguments 6-8. Negative values are ignored. */ - - .macro sys function, nargs - PTR \function - LONG (\nargs << 2) - (5 << 2) - .endm - - .align 3 - .type sys_call_table,@object -EXPORT(sys_call_table) - syscalltable - .size sys_call_table, . - sys_call_table + PTR sys_io_setup + PTR sys_io_destroy + PTR sys_io_getevents + PTR sys_io_submit + PTR sys_io_cancel /* 4245 */ + PTR sys_exit_group + PTR sys_lookup_dcookie + PTR sys_epoll_create + PTR sys_epoll_ctl + PTR sys_epoll_wait /* 4250 */ + PTR sys_remap_file_pages + PTR sys_set_tid_address + PTR sys_restart_syscall + PTR sys_fadvise64_64 + PTR sys_statfs64 /* 4255 */ + PTR sys_fstatfs64 + PTR sys_timer_create + PTR sys_timer_settime + PTR sys_timer_gettime + PTR sys_timer_getoverrun /* 4260 */ + PTR sys_timer_delete + PTR sys_clock_settime + PTR sys_clock_gettime + PTR sys_clock_getres + PTR sys_clock_nanosleep /* 4265 */ + PTR sys_tgkill + PTR sys_utimes + PTR sys_mbind + PTR sys_ni_syscall /* sys_get_mempolicy */ + PTR sys_ni_syscall /* 4270 sys_set_mempolicy */ + PTR sys_mq_open + PTR sys_mq_unlink + PTR sys_mq_timedsend + PTR sys_mq_timedreceive + PTR sys_mq_notify /* 4275 */ + PTR sys_mq_getsetattr + PTR sys_ni_syscall /* sys_vserver */ + PTR sys_waitid + PTR sys_ni_syscall /* available, was setaltroot */ + PTR sys_add_key /* 4280 */ + PTR sys_request_key + PTR sys_keyctl + PTR sys_set_thread_area + PTR sys_inotify_init + PTR sys_inotify_add_watch /* 4285 */ + PTR sys_inotify_rm_watch + PTR sys_migrate_pages + PTR sys_openat + PTR sys_mkdirat + PTR sys_mknodat /* 4290 */ + PTR sys_fchownat + PTR sys_futimesat + PTR sys_fstatat64 + PTR sys_unlinkat + PTR sys_renameat /* 4295 */ + PTR sys_linkat + PTR sys_symlinkat + PTR sys_readlinkat + PTR sys_fchmodat + PTR sys_faccessat /* 4300 */ + PTR sys_pselect6 + PTR sys_ppoll + PTR sys_unshare + PTR sys_splice + PTR sys_sync_file_range /* 4305 */ + PTR sys_tee + PTR sys_vmsplice + PTR sys_move_pages + PTR sys_set_robust_list + PTR sys_get_robust_list /* 4310 */ + PTR sys_kexec_load + PTR sys_getcpu + PTR sys_epoll_pwait + PTR sys_ioprio_set + PTR sys_ioprio_get /* 4315 */ + PTR sys_utimensat + PTR sys_signalfd + PTR sys_ni_syscall /* was timerfd */ + PTR sys_eventfd + PTR sys_fallocate /* 4320 */ + PTR sys_timerfd_create + PTR sys_timerfd_gettime + PTR sys_timerfd_settime + PTR sys_signalfd4 + PTR sys_eventfd2 /* 4325 */ + PTR sys_epoll_create1 + PTR sys_dup3 + PTR sys_pipe2 + PTR sys_inotify_init1 + PTR sys_preadv /* 4330 */ + PTR sys_pwritev + PTR sys_rt_tgsigqueueinfo + PTR sys_perf_event_open + PTR sys_accept4 + PTR sys_recvmmsg /* 4335 */ + PTR sys_fanotify_init + PTR sys_fanotify_mark + PTR sys_prlimit64 + PTR sys_name_to_handle_at + PTR sys_open_by_handle_at /* 4340 */ + PTR sys_clock_adjtime + PTR sys_syncfs + PTR sys_sendmmsg + PTR sys_setns + PTR sys_process_vm_readv /* 4345 */ + PTR sys_process_vm_writev + PTR sys_kcmp + PTR sys_finit_module diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S index be6627ead619..57e3742fec59 100644 --- a/arch/mips/kernel/scall64-64.S +++ b/arch/mips/kernel/scall64-64.S @@ -114,7 +114,8 @@ illegal_syscall: END(handle_sys64) .align 3 -sys_call_table: + .type sys_call_table, @object +EXPORT(sys_call_table) PTR sys_read /* 5000 */ PTR sys_write PTR sys_open diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index cab150789c8d..2f48f5934399 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S @@ -103,6 +103,7 @@ not_n32_scall: END(handle_sysn32) + .type sysn32_call_table, @object EXPORT(sysn32_call_table) PTR sys_read /* 6000 */ PTR sys_write diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index 37605dc8eef7..f1acdb429f4f 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S @@ -53,7 +53,7 @@ NESTED(handle_sys, PT_SIZE, sp) sll a3, a3, 0 dsll t0, v0, 3 # offset into table - ld t2, (sys_call_table - (__NR_O32_Linux * 8))(t0) + ld t2, (sys32_call_table - (__NR_O32_Linux * 8))(t0) sd a3, PT_R26(sp) # save a3 for syscall restarting @@ -168,7 +168,7 @@ LEAF(sys32_syscall) beqz t0, einval # do not recurse dsll t1, t0, 3 beqz v0, einval - ld t2, sys_call_table(t1) # syscall routine + ld t2, sys32_call_table(t1) # syscall routine move a0, a1 # shift argument registers move a1, a2 @@ -190,8 +190,8 @@ einval: li v0, -ENOSYS END(sys32_syscall) .align 3 - .type sys_call_table,@object -sys_call_table: + .type sys32_call_table,@object +EXPORT(sys32_call_table) PTR sys32_syscall /* 4000 */ PTR sys_exit PTR __sys_fork @@ -541,4 +541,4 @@ sys_call_table: PTR compat_sys_process_vm_writev PTR sys_kcmp PTR sys_finit_module - .size sys_call_table,.-sys_call_table + .size sys32_call_table,.-sys32_call_table diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index c7f90519e58c..a842154d57dc 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -300,12 +300,13 @@ static void __init bootmem_init(void) int i; /* - * Init any data related to initrd. It's a nop if INITRD is - * not selected. Once that done we can determine the low bound - * of usable memory. + * Sanity check any INITRD first. We don't take it into account + * for bootmem setup initially, rely on the end-of-kernel-code + * as our memory range starting point. Once bootmem is inited we + * will reserve the area used for the initrd. */ - reserved_end = max(init_initrd(), - (unsigned long) PFN_UP(__pa_symbol(&_end))); + init_initrd(); + reserved_end = (unsigned long) PFN_UP(__pa_symbol(&_end)); /* * max_low_pfn is not a number of pages. The number of pages @@ -362,6 +363,14 @@ static void __init bootmem_init(void) max_low_pfn = PFN_DOWN(HIGHMEM_START); } +#ifdef CONFIG_BLK_DEV_INITRD + /* + * mapstart should be after initrd_end + */ + if (initrd_end) + mapstart = max(mapstart, (unsigned long)PFN_UP(__pa(initrd_end))); +#endif + /* * Initialize the boot-time allocator with low memory only. */ @@ -552,6 +561,52 @@ static void __init arch_mem_addpart(phys_t mem, phys_t end, int type) add_memory_region(mem, size, type); } +#ifdef CONFIG_KEXEC +static inline unsigned long long get_total_mem(void) +{ + unsigned long long total; + + total = max_pfn - min_low_pfn; + return total << PAGE_SHIFT; +} + +static void __init mips_parse_crashkernel(void) +{ + unsigned long long total_mem; + unsigned long long crash_size, crash_base; + int ret; + + total_mem = get_total_mem(); + ret = parse_crashkernel(boot_command_line, total_mem, + &crash_size, &crash_base); + if (ret != 0 || crash_size <= 0) + return; + + crashk_res.start = crash_base; + crashk_res.end = crash_base + crash_size - 1; +} + +static void __init request_crashkernel(struct resource *res) +{ + int ret; + + ret = request_resource(res, &crashk_res); + if (!ret) + pr_info("Reserving %ldMB of memory at %ldMB for crashkernel\n", + (unsigned long)((crashk_res.end - + crashk_res.start + 1) >> 20), + (unsigned long)(crashk_res.start >> 20)); +} +#else /* !defined(CONFIG_KEXEC) */ +static void __init mips_parse_crashkernel(void) +{ +} + +static void __init request_crashkernel(struct resource *res) +{ +} +#endif /* !defined(CONFIG_KEXEC) */ + static void __init arch_mem_init(char **cmdline_p) { extern void plat_mem_setup(void); @@ -608,6 +663,8 @@ static void __init arch_mem_init(char **cmdline_p) BOOTMEM_DEFAULT); } #endif + + mips_parse_crashkernel(); #ifdef CONFIG_KEXEC if (crashk_res.start != crashk_res.end) reserve_bootmem(crashk_res.start, @@ -620,52 +677,6 @@ static void __init arch_mem_init(char **cmdline_p) paging_init(); } -#ifdef CONFIG_KEXEC -static inline unsigned long long get_total_mem(void) -{ - unsigned long long total; - - total = max_pfn - min_low_pfn; - return total << PAGE_SHIFT; -} - -static void __init mips_parse_crashkernel(void) -{ - unsigned long long total_mem; - unsigned long long crash_size, crash_base; - int ret; - - total_mem = get_total_mem(); - ret = parse_crashkernel(boot_command_line, total_mem, - &crash_size, &crash_base); - if (ret != 0 || crash_size <= 0) - return; - - crashk_res.start = crash_base; - crashk_res.end = crash_base + crash_size - 1; -} - -static void __init request_crashkernel(struct resource *res) -{ - int ret; - - ret = request_resource(res, &crashk_res); - if (!ret) - pr_info("Reserving %ldMB of memory at %ldMB for crashkernel\n", - (unsigned long)((crashk_res.end - - crashk_res.start + 1) >> 20), - (unsigned long)(crashk_res.start >> 20)); -} -#else /* !defined(CONFIG_KEXEC) */ -static void __init mips_parse_crashkernel(void) -{ -} - -static void __init request_crashkernel(struct resource *res) -{ -} -#endif /* !defined(CONFIG_KEXEC) */ - static void __init resource_init(void) { int i; @@ -678,11 +689,6 @@ static void __init resource_init(void) data_resource.start = __pa_symbol(&_etext); data_resource.end = __pa_symbol(&_edata) - 1; - /* - * Request address space for all standard RAM. - */ - mips_parse_crashkernel(); - for (i = 0; i < boot_mem_map.nr_map; i++) { struct resource *res; unsigned long start, end; diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index 57de8b751627..1905a419aa46 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -314,7 +314,7 @@ SYSCALL_DEFINE3(32_sigaction, long, sig, const struct compat_sigaction __user *, return ret; } -int copy_siginfo_to_user32(compat_siginfo_t __user *to, siginfo_t *from) +int copy_siginfo_to_user32(compat_siginfo_t __user *to, const siginfo_t *from) { int err; diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index 126da74d4c55..2362665ba496 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -136,10 +136,10 @@ static void bmips_prepare_cpus(unsigned int max_cpus) { if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU, "smp_ipi0", NULL)) - panic("Can't request IPI0 interrupt\n"); + panic("Can't request IPI0 interrupt"); if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU, "smp_ipi1", NULL)) - panic("Can't request IPI1 interrupt\n"); + panic("Can't request IPI1 interrupt"); } /* diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c index c2e5d74739b4..5969f1e9b62a 100644 --- a/arch/mips/kernel/smp-cmp.c +++ b/arch/mips/kernel/smp-cmp.c @@ -99,7 +99,9 @@ static void cmp_init_secondary(void) c->core = (read_c0_ebase() >> 1) & 0x1ff; #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) - c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE; + if (cpu_has_mipsmt) + c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & + TCBIND_CURVPE; #endif #ifdef CONFIG_MIPS_MT_SMTC c->tc_id = (read_c0_tcbind() & TCBIND_CURTC) >> TCBIND_CURTC_SHIFT; @@ -177,9 +179,16 @@ void __init cmp_smp_setup(void) } if (cpu_has_mipsmt) { - unsigned int nvpe, mvpconf0 = read_c0_mvpconf0(); + unsigned int nvpe = 1; +#ifdef CONFIG_MIPS_MT_SMP + unsigned int mvpconf0 = read_c0_mvpconf0(); + + nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; +#elif defined(CONFIG_MIPS_MT_SMTC) + unsigned int mvpconf0 = read_c0_mvpconf0(); nvpe = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1; +#endif smp_num_siblings = nvpe; } pr_info("Detected %i available secondary CPU(s)\n", ncpu); diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 5c208ed8f856..0a022ee33b2a 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -150,7 +150,6 @@ asmlinkage void start_secondary(void) void __irq_entry smp_call_function_interrupt(void) { irq_enter(); - generic_smp_call_function_single_interrupt(); generic_smp_call_function_interrupt(); irq_exit(); } diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index 9d686bf97b0e..dcb8e5d3bb8a 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -24,6 +24,7 @@ #include <linux/export.h> #include <asm/cpu-features.h> +#include <asm/cpu-type.h> #include <asm/div64.h> #include <asm/smtc_ipi.h> #include <asm/time.h> @@ -121,6 +122,14 @@ void __init time_init(void) { plat_time_init(); - if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug()) + /* + * The use of the R4k timer as a clock event takes precedence; + * if reading the Count register might interfere with the timer + * interrupt, then we don't use the timer as a clock source. + * We may still use the timer as a clock source though if the + * timer interrupt isn't reliable; the interference doesn't + * matter then, because we don't use the interrupt. + */ + if (mips_clockevent_init() != 0 || !cpu_has_mfc0_count_bug()) init_mips_clocksource(); } diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index aec3408edd4b..f9c8746be8d6 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -39,6 +39,7 @@ #include <asm/break.h> #include <asm/cop2.h> #include <asm/cpu.h> +#include <asm/cpu-type.h> #include <asm/dsp.h> #include <asm/fpu.h> #include <asm/fpu_emulator.h> @@ -329,6 +330,7 @@ void show_regs(struct pt_regs *regs) void show_registers(struct pt_regs *regs) { const int field = 2 * sizeof(unsigned long); + mm_segment_t old_fs = get_fs(); __show_regs(regs); print_modules(); @@ -343,9 +345,13 @@ void show_registers(struct pt_regs *regs) printk("*HwTLS: %0*lx\n", field, tls); } + if (!user_mode(regs)) + /* Necessary for getting the correct stack content */ + set_fs(KERNEL_DS); show_stacktrace(current, regs); show_code((unsigned int __user *) regs->cp0_epc); printk("\n"); + set_fs(old_fs); } static int regs_to_trapnr(struct pt_regs *regs) @@ -365,7 +371,8 @@ void __noreturn die(const char *str, struct pt_regs *regs) oops_enter(); - if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP) + if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), + SIGSEGV) == NOTIFY_STOP) sig = 0; console_verbose(); @@ -456,8 +463,8 @@ asmlinkage void do_be(struct pt_regs *regs) printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", data ? "Data" : "Instruction", field, regs->cp0_epc, field, regs->regs[31]); - if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS) - == NOTIFY_STOP) + if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), + SIGBUS) == NOTIFY_STOP) goto out; die_if_kernel("Oops", regs); @@ -622,7 +629,7 @@ static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt) regs->regs[rt] = read_c0_count(); return 0; case 3: /* Count register resolution */ - switch (current_cpu_data.cputype) { + switch (current_cpu_type()) { case CPU_20KC: case CPU_25KF: regs->regs[rt] = 1; @@ -726,8 +733,8 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) siginfo_t info = {0}; prev_state = exception_enter(); - if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE) - == NOTIFY_STOP) + if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), + SIGFPE) == NOTIFY_STOP) goto out; die_if_kernel("FP exception in kernel code", regs); @@ -797,7 +804,8 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, return; #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ - if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) + if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), + SIGTRAP) == NOTIFY_STOP) return; /* @@ -891,12 +899,14 @@ asmlinkage void do_bp(struct pt_regs *regs) */ switch (bcode) { case BRK_KPROBE_BP: - if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) + if (notify_die(DIE_BREAK, "debug", regs, bcode, + regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) goto out; else break; case BRK_KPROBE_SSTEPBP: - if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) + if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, + regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) goto out; else break; @@ -960,8 +970,8 @@ asmlinkage void do_ri(struct pt_regs *regs) int status = -1; prev_state = exception_enter(); - if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL) - == NOTIFY_STOP) + if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), + SIGILL) == NOTIFY_STOP) goto out; die_if_kernel("Reserved instruction in kernel code", regs); @@ -1487,10 +1497,14 @@ int register_nmi_notifier(struct notifier_block *nb) void __noreturn nmi_exception_handler(struct pt_regs *regs) { + char str[100]; + raw_notifier_call_chain(&nmi_chain, 0, regs); bust_spinlocks(1); - printk("NMI taken!!!!\n"); - die("NMI", regs); + snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n", + smp_processor_id(), regs->cp0_epc); + regs->cp0_epc = read_c0_errorepc(); + die(str, regs); } #define VECTORSPACING 0x100 /* for EI/VI mode */ @@ -1553,7 +1567,6 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) unsigned char *b; BUG_ON(!cpu_has_veic && !cpu_has_vint); - BUG_ON((n < 0) && (n > 9)); if (addr == NULL) { handler = (unsigned long) do_default_vi; diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index 05826d20a792..3b46f7ce9ca7 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -179,5 +179,6 @@ SECTIONS *(.options) *(.pdr) *(.reginfo) + *(.eh_frame) } } diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index faf84c5f2629..59b2b3cd7885 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -1368,7 +1368,7 @@ out_einval: } static DEVICE_ATTR_RW(ntcs); -static struct attribute vpe_attrs[] = { +static struct attribute *vpe_attrs[] = { &dev_attr_kill.attr, &dev_attr_ntcs.attr, NULL, diff --git a/arch/mips/kvm/kvm_mips.c b/arch/mips/kvm/kvm_mips.c index a7b044536de4..73b34827826c 100644 --- a/arch/mips/kvm/kvm_mips.c +++ b/arch/mips/kvm/kvm_mips.c @@ -198,12 +198,13 @@ kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) return -ENOIOCTLCMD; } -void kvm_arch_free_memslot(struct kvm_memory_slot *free, +void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, struct kvm_memory_slot *dont) { } -int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages) +int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, + unsigned long npages) { return 0; } diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c index ff4894a833ee..8f1866d8124d 100644 --- a/arch/mips/lantiq/falcon/sysctrl.c +++ b/arch/mips/lantiq/falcon/sysctrl.c @@ -48,6 +48,7 @@ #define CPU0CC_CPUDIV 0x0001 /* Activation Status Register */ +#define ACTS_ASC0_ACT 0x00001000 #define ACTS_ASC1_ACT 0x00000800 #define ACTS_I2C_ACT 0x00004000 #define ACTS_P0 0x00010000 @@ -108,6 +109,7 @@ static void sysctl_deactivate(struct clk *clk) static int sysctl_clken(struct clk *clk) { sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN); + sysctl_w32(clk->module, clk->bits, SYSCTL_ACT); sysctl_wait(clk, clk->bits, SYSCTL_CLKS); return 0; } @@ -256,6 +258,7 @@ void __init ltq_soc_init(void) clkdev_add_sys("1e800400.pad", SYSCTL_SYS1, ACTS_PADCTRL1); clkdev_add_sys("1e800500.pad", SYSCTL_SYS1, ACTS_PADCTRL3); clkdev_add_sys("1e800600.pad", SYSCTL_SYS1, ACTS_PADCTRL4); - clkdev_add_sys("1e100C00.serial", SYSCTL_SYS1, ACTS_ASC1_ACT); + clkdev_add_sys("1e100b00.serial", SYSCTL_SYS1, ACTS_ASC1_ACT); + clkdev_add_sys("1e100c00.serial", SYSCTL_SYS1, ACTS_ASC0_ACT); clkdev_add_sys("1e200000.i2c", SYSCTL_SYS1, ACTS_I2C_ACT); } diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index eb3e18659630..85685e1cdb89 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -390,7 +390,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent) ret = of_irq_to_resource_table(eiu_node, ltq_eiu_irq, exin_avail); if (ret != exin_avail) - panic("failed to load external irq resources\n"); + panic("failed to load external irq resources"); if (request_mem_region(res.start, resource_size(&res), res.name) < 0) diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c index 49c460370285..19686c5bc5ed 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -14,6 +14,7 @@ #include <asm/bootinfo.h> #include <asm/time.h> +#include <asm/prom.h> #include <lantiq.h> diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile index 7a13660d630d..087497d97357 100644 --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -1,3 +1,3 @@ -obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o +obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o diff --git a/arch/mips/lantiq/xway/dcdc.c b/arch/mips/lantiq/xway/dcdc.c new file mode 100644 index 000000000000..7688ac0f06d0 --- /dev/null +++ b/arch/mips/lantiq/xway/dcdc.c @@ -0,0 +1,63 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2012 John Crispin <blogic@openwrt.org> + * Copyright (C) 2010 Sameer Ahmad, Lantiq GmbH + */ + +#include <linux/ioport.h> +#include <linux/of_platform.h> + +#include <lantiq_soc.h> + +/* Bias and regulator Setup Register */ +#define DCDC_BIAS_VREG0 0xa +/* Bias and regulator Setup Register */ +#define DCDC_BIAS_VREG1 0xb + +#define dcdc_w8(x, y) ltq_w8((x), dcdc_membase + (y)) +#define dcdc_r8(x) ltq_r8(dcdc_membase + (x)) + +static void __iomem *dcdc_membase; + +static int dcdc_probe(struct platform_device *pdev) +{ + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dcdc_membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(dcdc_membase)) + return PTR_ERR(dcdc_membase); + + dev_info(&pdev->dev, "Core Voltage : %d mV\n", + dcdc_r8(DCDC_BIAS_VREG1) * 8); + + return 0; +} + +static const struct of_device_id dcdc_match[] = { + { .compatible = "lantiq,dcdc-xrx200" }, + {}, +}; + +static struct platform_driver dcdc_driver = { + .probe = dcdc_probe, + .driver = { + .name = "dcdc-xrx200", + .owner = THIS_MODULE, + .of_match_table = dcdc_match, + }, +}; + +int __init dcdc_init(void) +{ + int ret = platform_driver_register(&dcdc_driver); + + if (ret) + pr_info("dcdc: Error registering platform driver\n"); + return ret; +} + +arch_initcall(dcdc_init); diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c index c24924fe087d..51804b10a036 100644 --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -128,7 +128,7 @@ static int pmu_enable(struct clk *clk) do {} while (--retry && (pmu_r32(PWDSR(clk->module)) & clk->bits)); if (!retry) - panic("activating PMU module failed!\n"); + panic("activating PMU module failed!"); return 0; } diff --git a/arch/mips/lasat/image/Makefile b/arch/mips/lasat/image/Makefile index dfb509d21d8e..fd32075679c6 100644 --- a/arch/mips/lasat/image/Makefile +++ b/arch/mips/lasat/image/Makefile @@ -13,13 +13,11 @@ endif MKLASATIMG = mklasatimg MKLASATIMG_ARCH = mq2,mqpro,sp100,sp200 KERNEL_IMAGE = vmlinux -KERNEL_START = $(shell $(NM) $(KERNEL_IMAGE) | grep " _text" | cut -f1 -d\ ) -KERNEL_ENTRY = $(shell $(NM) $(KERNEL_IMAGE) | grep kernel_entry | cut -f1 -d\ ) LDSCRIPT= -L$(srctree)/$(src) -Tromscript.normal -HEAD_DEFINES := -D_kernel_start=0x$(KERNEL_START) \ - -D_kernel_entry=0x$(KERNEL_ENTRY) \ +HEAD_DEFINES := -D_kernel_start=$(VMLINUX_LOAD_ADDRESS) \ + -D_kernel_entry=$(VMLINUX_ENTRY_ADDRESS) \ -D VERSION="\"$(Version)\"" \ -D TIMESTAMP=$(shell date +%s) diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile index 4c57b3e5743f..9e4484ccbb03 100644 --- a/arch/mips/loongson/common/Makefile +++ b/arch/mips/loongson/common/Makefile @@ -3,8 +3,9 @@ # obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \ - pci.o bonito-irq.o mem.o machtype.o platform.o + bonito-irq.o mem.o machtype.o platform.o obj-$(CONFIG_GPIOLIB) += gpio.o +obj-$(CONFIG_PCI) += pci.o # # Serial port support diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 46048d24328c..efe008846ed0 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -436,7 +436,6 @@ static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) break; default: return SIGILL; - break; } break; case mm_32f_74_op: /* c.cond.fmt */ @@ -451,12 +450,10 @@ static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) break; default: return SIGILL; - break; } break; default: return SIGILL; - break; } *insn_ptr = mips32_insn; @@ -491,7 +488,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, dec_insn.next_pc_inc; *contpc = regs->regs[insn.mm_i_format.rs]; return 1; - break; } } break; @@ -513,7 +509,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, dec_insn.pc_inc + dec_insn.next_pc_inc; return 1; - break; case mm_bgezals_op: case mm_bgezal_op: regs->regs[31] = regs->cp0_epc + @@ -530,7 +525,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, dec_insn.pc_inc + dec_insn.next_pc_inc; return 1; - break; case mm_blez_op: if ((long)regs->regs[insn.mm_i_format.rs] <= 0) *contpc = regs->cp0_epc + @@ -541,7 +535,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, dec_insn.pc_inc + dec_insn.next_pc_inc; return 1; - break; case mm_bgtz_op: if ((long)regs->regs[insn.mm_i_format.rs] <= 0) *contpc = regs->cp0_epc + @@ -552,7 +545,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, dec_insn.pc_inc + dec_insn.next_pc_inc; return 1; - break; case mm_bc2f_op: case mm_bc1f_op: bc_false = 1; @@ -580,7 +572,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; return 1; - break; } break; case mm_pool16c_op: @@ -593,7 +584,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, case mm_jr16_op: *contpc = regs->regs[insn.mm_i_format.rs]; return 1; - break; } break; case mm_beqz16_op: @@ -605,7 +595,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; return 1; - break; case mm_bnez16_op: if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0) *contpc = regs->cp0_epc + @@ -615,12 +604,10 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; return 1; - break; case mm_b16_op: *contpc = regs->cp0_epc + dec_insn.pc_inc + (insn.mm_b0_format.simmediate << 1); return 1; - break; case mm_beq32_op: if (regs->regs[insn.mm_i_format.rs] == regs->regs[insn.mm_i_format.rt]) @@ -632,7 +619,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, dec_insn.pc_inc + dec_insn.next_pc_inc; return 1; - break; case mm_bne32_op: if (regs->regs[insn.mm_i_format.rs] != regs->regs[insn.mm_i_format.rt]) @@ -643,7 +629,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, *contpc = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; return 1; - break; case mm_jalx32_op: regs->regs[31] = regs->cp0_epc + dec_insn.pc_inc + dec_insn.next_pc_inc; @@ -652,7 +637,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, *contpc <<= 28; *contpc |= (insn.j_format.target << 2); return 1; - break; case mm_jals32_op: case mm_jal32_op: regs->regs[31] = regs->cp0_epc + @@ -665,7 +649,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, *contpc |= (insn.j_format.target << 1); set_isa16_mode(*contpc); return 1; - break; } return 0; } @@ -694,7 +677,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, case jr_op: *contpc = regs->regs[insn.r_format.rs]; return 1; - break; } break; case bcond_op: @@ -716,7 +698,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, dec_insn.pc_inc + dec_insn.next_pc_inc; return 1; - break; case bgezal_op: case bgezall_op: regs->regs[31] = regs->cp0_epc + @@ -734,7 +715,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, dec_insn.pc_inc + dec_insn.next_pc_inc; return 1; - break; } break; case jalx_op: @@ -752,7 +732,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, /* Set microMIPS mode bit: XOR for jalx. */ *contpc ^= bit; return 1; - break; case beq_op: case beql_op: if (regs->regs[insn.i_format.rs] == @@ -765,7 +744,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, dec_insn.pc_inc + dec_insn.next_pc_inc; return 1; - break; case bne_op: case bnel_op: if (regs->regs[insn.i_format.rs] != @@ -778,7 +756,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, dec_insn.pc_inc + dec_insn.next_pc_inc; return 1; - break; case blez_op: case blezl_op: if ((long)regs->regs[insn.i_format.rs] <= 0) @@ -790,7 +767,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, dec_insn.pc_inc + dec_insn.next_pc_inc; return 1; - break; case bgtz_op: case bgtzl_op: if ((long)regs->regs[insn.i_format.rs] > 0) @@ -802,7 +778,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, dec_insn.pc_inc + dec_insn.next_pc_inc; return 1; - break; #ifdef CONFIG_CPU_CAVIUM_OCTEON case lwc2_op: /* This is bbit0 on Octeon */ if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) @@ -856,7 +831,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, dec_insn.pc_inc + dec_insn.next_pc_inc; return 1; - break; case 1: /* bc1t */ case 3: /* bc1tl */ if (fcr31 & (1 << bit)) @@ -868,7 +842,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, dec_insn.pc_inc + dec_insn.next_pc_inc; return 1; - break; } } break; diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c index a0bcdbb81d41..c8efdb5b6ee0 100644 --- a/arch/mips/mm/c-octeon.c +++ b/arch/mips/mm/c-octeon.c @@ -19,6 +19,7 @@ #include <asm/bootinfo.h> #include <asm/cacheops.h> #include <asm/cpu-features.h> +#include <asm/cpu-type.h> #include <asm/page.h> #include <asm/pgtable.h> #include <asm/r4kcache.h> @@ -186,9 +187,10 @@ static void probe_octeon(void) unsigned long dcache_size; unsigned int config1; struct cpuinfo_mips *c = ¤t_cpu_data; + int cputype = current_cpu_type(); config1 = read_c0_config1(); - switch (c->cputype) { + switch (cputype) { case CPU_CAVIUM_OCTEON: case CPU_CAVIUM_OCTEON_PLUS: c->icache.linesz = 2 << ((config1 >> 19) & 7); @@ -199,7 +201,7 @@ static void probe_octeon(void) c->icache.sets * c->icache.ways * c->icache.linesz; c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; c->dcache.linesz = 128; - if (c->cputype == CPU_CAVIUM_OCTEON_PLUS) + if (cputype == CPU_CAVIUM_OCTEON_PLUS) c->dcache.sets = 2; /* CN5XXX has two Dcache sets */ else c->dcache.sets = 1; /* CN3XXX has one Dcache set */ @@ -224,6 +226,20 @@ static void probe_octeon(void) c->options |= MIPS_CPU_PREFETCH; break; + case CPU_CAVIUM_OCTEON3: + c->icache.linesz = 128; + c->icache.sets = 16; + c->icache.ways = 39; + c->icache.flags |= MIPS_CACHE_VTAG; + icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; + + c->dcache.linesz = 128; + c->dcache.ways = 32; + c->dcache.sets = 8; + dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; + c->options |= MIPS_CPU_PREFETCH; + break; + default: panic("Unsupported Cavium Networks CPU type"); break; diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index f749f687ee87..62ffd20ea869 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -12,6 +12,7 @@ #include <linux/highmem.h> #include <linux/kernel.h> #include <linux/linkage.h> +#include <linux/preempt.h> #include <linux/sched.h> #include <linux/smp.h> #include <linux/mm.h> @@ -24,6 +25,7 @@ #include <asm/cacheops.h> #include <asm/cpu.h> #include <asm/cpu-features.h> +#include <asm/cpu-type.h> #include <asm/io.h> #include <asm/page.h> #include <asm/pgtable.h> @@ -344,14 +346,8 @@ static void r4k_blast_scache_setup(void) static inline void local_r4k___flush_cache_all(void * args) { -#if defined(CONFIG_CPU_LOONGSON2) - r4k_blast_scache(); - return; -#endif - r4k_blast_dcache(); - r4k_blast_icache(); - switch (current_cpu_type()) { + case CPU_LOONGSON2: case CPU_R4000SC: case CPU_R4000MC: case CPU_R4400SC: @@ -359,7 +355,18 @@ static inline void local_r4k___flush_cache_all(void * args) case CPU_R10000: case CPU_R12000: case CPU_R14000: + /* + * These caches are inclusive caches, that is, if something + * is not cached in the S-cache, we know it also won't be + * in one of the primary caches. + */ r4k_blast_scache(); + break; + + default: + r4k_blast_dcache(); + r4k_blast_icache(); + break; } } @@ -570,8 +577,17 @@ static inline void local_r4k_flush_icache_range(unsigned long start, unsigned lo if (end - start > icache_size) r4k_blast_icache(); - else - protected_blast_icache_range(start, end); + else { + switch (boot_cpu_type()) { + case CPU_LOONGSON2: + protected_blast_icache_range(start, end); + break; + + default: + protected_loongson23_blast_icache_range(start, end); + break; + } + } } static inline void local_r4k_flush_icache_range_ipi(void *args) @@ -601,11 +617,13 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) /* Catch bad driver code */ BUG_ON(size == 0); + preempt_disable(); if (cpu_has_inclusive_pcaches) { if (size >= scache_size) r4k_blast_scache(); else blast_scache_range(addr, addr + size); + preempt_enable(); __sync(); return; } @@ -621,6 +639,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) R4600_HIT_CACHEOP_WAR_IMPL; blast_dcache_range(addr, addr + size); } + preempt_enable(); bc_wback_inv(addr, size); __sync(); @@ -631,6 +650,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) /* Catch bad driver code */ BUG_ON(size == 0); + preempt_disable(); if (cpu_has_inclusive_pcaches) { if (size >= scache_size) r4k_blast_scache(); @@ -645,6 +665,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) */ blast_inv_scache_range(addr, addr + size); } + preempt_enable(); __sync(); return; } @@ -655,6 +676,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) R4600_HIT_CACHEOP_WAR_IMPL; blast_inv_dcache_range(addr, addr + size); } + preempt_enable(); bc_inv(addr, size); __sync(); @@ -780,20 +802,30 @@ static inline void rm7k_erratum31(void) static inline void alias_74k_erratum(struct cpuinfo_mips *c) { + unsigned int imp = c->processor_id & PRID_IMP_MASK; + unsigned int rev = c->processor_id & PRID_REV_MASK; + /* * Early versions of the 74K do not update the cache tags on a * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG * aliases. In this case it is better to treat the cache as always * having aliases. */ - if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0)) - c->dcache.flags |= MIPS_CACHE_VTAG; - if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0)) - write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); - if (((c->processor_id & 0xff00) == PRID_IMP_1074K) && - ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) { - c->dcache.flags |= MIPS_CACHE_VTAG; - write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); + switch (imp) { + case PRID_IMP_74K: + if (rev <= PRID_REV_ENCODE_332(2, 4, 0)) + c->dcache.flags |= MIPS_CACHE_VTAG; + if (rev == PRID_REV_ENCODE_332(2, 4, 0)) + write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); + break; + case PRID_IMP_1074K: + if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) { + c->dcache.flags |= MIPS_CACHE_VTAG; + write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); + } + break; + default: + BUG(); } } @@ -809,7 +841,7 @@ static void probe_pcache(void) unsigned long config1; unsigned int lsize; - switch (c->cputype) { + switch (current_cpu_type()) { case CPU_R4600: /* QED style two way caches? */ case CPU_R4700: case CPU_R5000: @@ -1025,7 +1057,8 @@ static void probe_pcache(void) * presumably no vendor is shipping his hardware in the "bad" * configuration. */ - if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 && + if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 && + (prid & PRID_REV_MASK) < PRID_REV_R4400 && !(config & CONF_SC) && c->icache.linesz != 16 && PAGE_SIZE <= 0x8000) panic("Improper R4000SC processor configuration detected"); @@ -1045,7 +1078,7 @@ static void probe_pcache(void) * normally they'd suffer from aliases but magic in the hardware deals * with that for us so we don't need to take care ourselves. */ - switch (c->cputype) { + switch (current_cpu_type()) { case CPU_20KC: case CPU_25KF: case CPU_SB1: @@ -1065,7 +1098,7 @@ static void probe_pcache(void) case CPU_34K: case CPU_74K: case CPU_1004K: - if (c->cputype == CPU_74K) + if (current_cpu_type() == CPU_74K) alias_74k_erratum(c); if ((read_c0_config7() & (1 << 16))) { /* effectively physically indexed dcache, @@ -1078,7 +1111,7 @@ static void probe_pcache(void) c->dcache.flags |= MIPS_CACHE_ALIASES; } - switch (c->cputype) { + switch (current_cpu_type()) { case CPU_20KC: /* * Some older 20Kc chips doesn't have the 'VI' bit in @@ -1090,15 +1123,14 @@ static void probe_pcache(void) case CPU_ALCHEMY: c->icache.flags |= MIPS_CACHE_IC_F_DC; break; - } -#ifdef CONFIG_CPU_LOONGSON2 - /* - * LOONGSON2 has 4 way icache, but when using indexed cache op, - * one op will act on all 4 ways - */ - c->icache.ways = 1; -#endif + case CPU_LOONGSON2: + /* + * LOONGSON2 has 4 way icache, but when using indexed cache op, + * one op will act on all 4 ways + */ + c->icache.ways = 1; + } printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", icache_size >> 10, @@ -1174,7 +1206,6 @@ static int probe_scache(void) return 1; } -#if defined(CONFIG_CPU_LOONGSON2) static void __init loongson2_sc_init(void) { struct cpuinfo_mips *c = ¤t_cpu_data; @@ -1190,7 +1221,6 @@ static void __init loongson2_sc_init(void) c->options |= MIPS_CPU_INCLUSIVE_CACHES; } -#endif extern int r5k_sc_init(void); extern int rm7k_sc_init(void); @@ -1207,7 +1237,7 @@ static void setup_scache(void) * processors don't have a S-cache that would be relevant to the * Linux memory management. */ - switch (c->cputype) { + switch (current_cpu_type()) { case CPU_R4000SC: case CPU_R4000MC: case CPU_R4400SC: @@ -1240,11 +1270,10 @@ static void setup_scache(void) #endif return; -#if defined(CONFIG_CPU_LOONGSON2) case CPU_LOONGSON2: loongson2_sc_init(); return; -#endif + case CPU_XLP: /* don't need to worry about L2, fully coherent */ return; @@ -1384,9 +1413,8 @@ static void r4k_cache_error_setup(void) { extern char __weak except_vec2_generic; extern char __weak except_vec2_sb1; - struct cpuinfo_mips *c = ¤t_cpu_data; - switch (c->cputype) { + switch (current_cpu_type()) { case CPU_SB1: case CPU_SB1A: set_uncached_handler(0x100, &except_vec2_sb1, 0x80); diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index aaccf1c10699..2e9418562258 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -18,6 +18,7 @@ #include <linux/highmem.h> #include <asm/cache.h> +#include <asm/cpu-type.h> #include <asm/io.h> #include <dma-coherence.h> @@ -50,16 +51,20 @@ static inline struct page *dma_addr_to_page(struct device *dev, } /* + * The affected CPUs below in 'cpu_needs_post_dma_flush()' can + * speculatively fill random cachelines with stale data at any time, + * requiring an extra flush post-DMA. + * * Warning on the terminology - Linux calls an uncached area coherent; * MIPS terminology calls memory areas with hardware maintained coherency * coherent. */ - -static inline int cpu_is_noncoherent_r10000(struct device *dev) +static inline int cpu_needs_post_dma_flush(struct device *dev) { return !plat_device_is_coherent(dev) && - (current_cpu_type() == CPU_R10000 || - current_cpu_type() == CPU_R12000); + (boot_cpu_type() == CPU_R10000 || + boot_cpu_type() == CPU_R12000 || + boot_cpu_type() == CPU_BMIPS5000); } static gfp_t massage_gfp_flags(const struct device *dev, gfp_t gfp) @@ -230,7 +235,7 @@ static inline void __dma_sync(struct page *page, static void mips_dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, enum dma_data_direction direction, struct dma_attrs *attrs) { - if (cpu_is_noncoherent_r10000(dev)) + if (cpu_needs_post_dma_flush(dev)) __dma_sync(dma_addr_to_page(dev, dma_addr), dma_addr & ~PAGE_MASK, size, direction); @@ -284,7 +289,7 @@ static void mips_dma_unmap_sg(struct device *dev, struct scatterlist *sg, static void mips_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) { - if (cpu_is_noncoherent_r10000(dev)) + if (cpu_needs_post_dma_flush(dev)) __dma_sync(dma_addr_to_page(dev, dma_handle), dma_handle & ~PAGE_MASK, size, direction); } @@ -292,7 +297,6 @@ static void mips_dma_sync_single_for_cpu(struct device *dev, static void mips_dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) { - plat_extra_sync_for_device(dev); if (!plat_device_is_coherent(dev)) __dma_sync(dma_addr_to_page(dev, dma_handle), dma_handle & ~PAGE_MASK, size, direction); @@ -303,12 +307,10 @@ static void mips_dma_sync_sg_for_cpu(struct device *dev, { int i; - /* Make sure that gcc doesn't leave the empty loop body. */ - for (i = 0; i < nelems; i++, sg++) { - if (cpu_is_noncoherent_r10000(dev)) + if (cpu_needs_post_dma_flush(dev)) + for (i = 0; i < nelems; i++, sg++) __dma_sync(sg_page(sg), sg->offset, sg->length, direction); - } } static void mips_dma_sync_sg_for_device(struct device *dev, @@ -316,17 +318,15 @@ static void mips_dma_sync_sg_for_device(struct device *dev, { int i; - /* Make sure that gcc doesn't leave the empty loop body. */ - for (i = 0; i < nelems; i++, sg++) { - if (!plat_device_is_coherent(dev)) + if (!plat_device_is_coherent(dev)) + for (i = 0; i < nelems; i++, sg++) __dma_sync(sg_page(sg), sg->offset, sg->length, direction); - } } int mips_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) { - return plat_dma_mapping_error(dev, dma_addr); + return 0; } int mips_dma_supported(struct device *dev, u64 mask) @@ -339,7 +339,6 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size, { BUG_ON(direction == DMA_NONE); - plat_extra_sync_for_device(dev); if (!plat_device_is_coherent(dev)) __dma_sync_virtual(vaddr, size, direction); } diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c index 85df1cd8d446..becc42bb1849 100644 --- a/arch/mips/mm/fault.c +++ b/arch/mips/mm/fault.c @@ -42,8 +42,7 @@ static void __kprobes __do_page_fault(struct pt_regs *regs, unsigned long write, const int field = sizeof(unsigned long) * 2; siginfo_t info; int fault; - unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE | - (write ? FAULT_FLAG_WRITE : 0); + unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE; #if 0 printk("Cpu%d[%s:%d:%0*lx:%ld:%0*lx]\n", raw_smp_processor_id(), @@ -93,6 +92,8 @@ static void __kprobes __do_page_fault(struct pt_regs *regs, unsigned long write, if (in_atomic() || !mm) goto bad_area_nosemaphore; + if (user_mode(regs)) + flags |= FAULT_FLAG_USER; retry: down_read(&mm->mmap_sem); vma = find_vma(mm, address); @@ -114,6 +115,7 @@ good_area: if (write) { if (!(vma->vm_flags & VM_WRITE)) goto bad_area; + flags |= FAULT_FLAG_WRITE; } else { if (cpu_has_rixi) { if (address == regs->cp0_epc && !(vma->vm_flags & VM_EXEC)) { @@ -241,6 +243,8 @@ out_of_memory: * (which will retry the fault, or kill us if we got oom-killed). */ up_read(&mm->mmap_sem); + if (!user_mode(regs)) + goto no_context; pagefault_out_of_memory(); return; diff --git a/arch/mips/mm/gup.c b/arch/mips/mm/gup.c index d4ea5c9c4a93..06ce17c2a905 100644 --- a/arch/mips/mm/gup.c +++ b/arch/mips/mm/gup.c @@ -12,6 +12,7 @@ #include <linux/swap.h> #include <linux/hugetlb.h> +#include <asm/cpu-features.h> #include <asm/pgtable.h> static inline pte_t gup_get_pte(pte_t *ptep) @@ -273,7 +274,7 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write, len = (unsigned long) nr_pages << PAGE_SHIFT; end = start + len; - if (end < start) + if (end < start || cpu_has_dc_aliases) goto slow_irqon; /* XXX: batch / limit 'nr' */ diff --git a/arch/mips/mm/hugetlbpage.c b/arch/mips/mm/hugetlbpage.c index a7fee0dfb7a9..01fda4419ed0 100644 --- a/arch/mips/mm/hugetlbpage.c +++ b/arch/mips/mm/hugetlbpage.c @@ -85,6 +85,11 @@ int pud_huge(pud_t pud) return (pud_val(pud) & _PAGE_HUGE) != 0; } +int pmd_huge_support(void) +{ + return 1; +} + struct page * follow_huge_pmd(struct mm_struct *mm, unsigned long address, pmd_t *pmd, int write) diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 4e73f10a7519..12156176c7ca 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -124,7 +124,7 @@ void *kmap_coherent(struct page *page, unsigned long addr) BUG_ON(Page_dcache_dirty(page)); - inc_preempt_count(); + pagefault_disable(); idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1); #ifdef CONFIG_MIPS_MT_SMTC idx += FIX_N_COLOURS * smp_processor_id() + @@ -193,8 +193,7 @@ void kunmap_coherent(void) write_c0_entryhi(old_ctx); EXIT_CRITICAL(flags); #endif - dec_preempt_count(); - preempt_check_resched(); + pagefault_enable(); } void copy_user_highpage(struct page *to, struct page *from, @@ -254,6 +253,7 @@ void copy_from_user_page(struct vm_area_struct *vma, SetPageDcacheDirty(page); } } +EXPORT_SYMBOL_GPL(copy_from_user_page); void __init fixrange_init(unsigned long start, unsigned long end, pgd_t *pgd_base) diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c index 218c2109a55d..cbd81d17793a 100644 --- a/arch/mips/mm/page.c +++ b/arch/mips/mm/page.c @@ -18,6 +18,7 @@ #include <asm/bugs.h> #include <asm/cacheops.h> +#include <asm/cpu-type.h> #include <asm/inst.h> #include <asm/io.h> #include <asm/page.h> diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index 5d01392e3518..08d05aee8788 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -6,6 +6,7 @@ #include <linux/sched.h> #include <linux/mm.h> +#include <asm/cpu-type.h> #include <asm/mipsregs.h> #include <asm/bcache.h> #include <asm/cacheops.h> @@ -71,7 +72,7 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c) unsigned int tmp; /* Check the bypass bit (L2B) */ - switch (c->cputype) { + switch (current_cpu_type()) { case CPU_34K: case CPU_74K: case CPU_1004K: diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 00b26a67a06d..da3b0b9c9eae 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -16,6 +16,7 @@ #include <linux/module.h> #include <asm/cpu.h> +#include <asm/cpu-type.h> #include <asm/bootinfo.h> #include <asm/mmu_context.h> #include <asm/pgtable.h> @@ -51,21 +52,26 @@ extern void build_tlb_refill_handler(void); #endif /* CONFIG_MIPS_MT_SMTC */ -#if defined(CONFIG_CPU_LOONGSON2) /* * LOONGSON2 has a 4 entry itlb which is a subset of dtlb, * unfortrunately, itlb is not totally transparent to software. */ -#define FLUSH_ITLB write_c0_diag(4); - -#define FLUSH_ITLB_VM(vma) { if ((vma)->vm_flags & VM_EXEC) write_c0_diag(4); } - -#else - -#define FLUSH_ITLB -#define FLUSH_ITLB_VM(vma) +static inline void flush_itlb(void) +{ + switch (current_cpu_type()) { + case CPU_LOONGSON2: + write_c0_diag(4); + break; + default: + break; + } +} -#endif +static inline void flush_itlb_vm(struct vm_area_struct *vma) +{ + if (vma->vm_flags & VM_EXEC) + flush_itlb(); +} void local_flush_tlb_all(void) { @@ -92,7 +98,7 @@ void local_flush_tlb_all(void) } tlbw_use_hazard(); write_c0_entryhi(old_ctx); - FLUSH_ITLB; + flush_itlb(); EXIT_CRITICAL(flags); } EXPORT_SYMBOL(local_flush_tlb_all); @@ -154,7 +160,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, } else { drop_mmu_context(mm, cpu); } - FLUSH_ITLB; + flush_itlb(); EXIT_CRITICAL(flags); } } @@ -196,7 +202,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) } else { local_flush_tlb_all(); } - FLUSH_ITLB; + flush_itlb(); EXIT_CRITICAL(flags); } @@ -229,7 +235,7 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) finish: write_c0_entryhi(oldpid); - FLUSH_ITLB_VM(vma); + flush_itlb_vm(vma); EXIT_CRITICAL(flags); } } @@ -261,7 +267,7 @@ void local_flush_tlb_one(unsigned long page) tlbw_use_hazard(); } write_c0_entryhi(oldpid); - FLUSH_ITLB; + flush_itlb(); EXIT_CRITICAL(flags); } @@ -334,7 +340,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) tlb_write_indexed(); } tlbw_use_hazard(); - FLUSH_ITLB_VM(vma); + flush_itlb_vm(vma); EXIT_CRITICAL(flags); } diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 556cb4815770..183f2b583e4d 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -30,6 +30,7 @@ #include <linux/cache.h> #include <asm/cacheflush.h> +#include <asm/cpu-type.h> #include <asm/pgtable.h> #include <asm/war.h> #include <asm/uasm.h> @@ -85,6 +86,7 @@ static int use_bbit_insns(void) case CPU_CAVIUM_OCTEON: case CPU_CAVIUM_OCTEON_PLUS: case CPU_CAVIUM_OCTEON2: + case CPU_CAVIUM_OCTEON3: return 1; default: return 0; @@ -95,6 +97,7 @@ static int use_lwx_insns(void) { switch (current_cpu_type()) { case CPU_CAVIUM_OCTEON2: + case CPU_CAVIUM_OCTEON3: return 1; default: return 0; @@ -337,10 +340,6 @@ static struct work_registers build_get_work_registers(u32 **p) { struct work_registers r; - int smp_processor_id_reg; - int smp_processor_id_sel; - int smp_processor_id_shift; - if (scratch_reg >= 0) { /* Save in CPU local C0_KScratch? */ UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg); @@ -351,25 +350,9 @@ static struct work_registers build_get_work_registers(u32 **p) } if (num_possible_cpus() > 1) { -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT - smp_processor_id_shift = 51; - smp_processor_id_reg = 20; /* XContext */ - smp_processor_id_sel = 0; -#else -# ifdef CONFIG_32BIT - smp_processor_id_shift = 25; - smp_processor_id_reg = 4; /* Context */ - smp_processor_id_sel = 0; -# endif -# ifdef CONFIG_64BIT - smp_processor_id_shift = 26; - smp_processor_id_reg = 4; /* Context */ - smp_processor_id_sel = 0; -# endif -#endif /* Get smp_processor_id */ - UASM_i_MFC0(p, K0, smp_processor_id_reg, smp_processor_id_sel); - UASM_i_SRL_SAFE(p, K0, K0, smp_processor_id_shift); + UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG); + UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT); /* handler_reg_save index in K0 */ UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save))); @@ -816,11 +799,11 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, } /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT if (pgd_reg != -1) { /* pgd is in pgd_reg */ UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); } else { +#if defined(CONFIG_MIPS_PGD_C0_CONTEXT) /* * &pgd << 11 stored in CONTEXT [23..63]. */ @@ -832,30 +815,18 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, /* 1 0 1 0 1 << 6 xkphys cached */ uasm_i_ori(p, ptr, ptr, 0x540); uasm_i_drotr(p, ptr, ptr, 11); - } #elif defined(CONFIG_SMP) -# ifdef CONFIG_MIPS_MT_SMTC - /* - * SMTC uses TCBind value as "CPU" index - */ - uasm_i_mfc0(p, ptr, C0_TCBIND); - uasm_i_dsrl_safe(p, ptr, ptr, 19); -# else - /* - * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 - * stored in CONTEXT. - */ - uasm_i_dmfc0(p, ptr, C0_CONTEXT); - uasm_i_dsrl_safe(p, ptr, ptr, 23); -# endif - UASM_i_LA_mostly(p, tmp, pgdc); - uasm_i_daddu(p, ptr, ptr, tmp); - uasm_i_dmfc0(p, tmp, C0_BADVADDR); - uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); + UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG); + uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT); + UASM_i_LA_mostly(p, tmp, pgdc); + uasm_i_daddu(p, ptr, ptr, tmp); + uasm_i_dmfc0(p, tmp, C0_BADVADDR); + uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); #else - UASM_i_LA_mostly(p, ptr, pgdc); - uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); + UASM_i_LA_mostly(p, ptr, pgdc); + uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); #endif + } uasm_l_vmalloc_done(l, *p); @@ -950,31 +921,25 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, static void __maybe_unused build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) { - long pgdc = (long)pgd_current; + if (pgd_reg != -1) { + /* pgd is in pgd_reg */ + uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg); + uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ + } else { + long pgdc = (long)pgd_current; - /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ + /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ #ifdef CONFIG_SMP -#ifdef CONFIG_MIPS_MT_SMTC - /* - * SMTC uses TCBind value as "CPU" index - */ - uasm_i_mfc0(p, ptr, C0_TCBIND); - UASM_i_LA_mostly(p, tmp, pgdc); - uasm_i_srl(p, ptr, ptr, 19); -#else - /* - * smp_processor_id() << 2 is stored in CONTEXT. - */ - uasm_i_mfc0(p, ptr, C0_CONTEXT); - UASM_i_LA_mostly(p, tmp, pgdc); - uasm_i_srl(p, ptr, ptr, 23); -#endif - uasm_i_addu(p, ptr, tmp, ptr); + uasm_i_mfc0(p, ptr, SMP_CPUID_REG); + UASM_i_LA_mostly(p, tmp, pgdc); + uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT); + uasm_i_addu(p, ptr, tmp, ptr); #else - UASM_i_LA_mostly(p, ptr, pgdc); + UASM_i_LA_mostly(p, ptr, pgdc); #endif - uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ - uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); + uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ + uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); + } uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ @@ -1346,95 +1311,100 @@ static void build_r4000_tlb_refill_handler(void) * need three, with the second nop'ed and the third being * unused. */ - /* Loongson2 ebase is different than r4k, we have more space */ -#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) - if ((p - tlb_handler) > 64) - panic("TLB refill handler space exceeded"); -#else - if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) - || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) - && uasm_insn_has_bdelay(relocs, - tlb_handler + MIPS64_REFILL_INSNS - 3))) - panic("TLB refill handler space exceeded"); -#endif - - /* - * Now fold the handler in the TLB refill handler space. - */ -#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) - f = final_handler; - /* Simplest case, just copy the handler. */ - uasm_copy_handler(relocs, labels, tlb_handler, p, f); - final_len = p - tlb_handler; -#else /* CONFIG_64BIT */ - f = final_handler + MIPS64_REFILL_INSNS; - if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { - /* Just copy the handler. */ - uasm_copy_handler(relocs, labels, tlb_handler, p, f); - final_len = p - tlb_handler; - } else { -#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT - const enum label_id ls = label_tlb_huge_update; -#else - const enum label_id ls = label_vmalloc; -#endif - u32 *split; - int ov = 0; - int i; - - for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) - ; - BUG_ON(i == ARRAY_SIZE(labels)); - split = labels[i].addr; - - /* - * See if we have overflown one way or the other. - */ - if (split > tlb_handler + MIPS64_REFILL_INSNS || - split < p - MIPS64_REFILL_INSNS) - ov = 1; - - if (ov) { + switch (boot_cpu_type()) { + default: + if (sizeof(long) == 4) { + case CPU_LOONGSON2: + /* Loongson2 ebase is different than r4k, we have more space */ + if ((p - tlb_handler) > 64) + panic("TLB refill handler space exceeded"); /* - * Split two instructions before the end. One - * for the branch and one for the instruction - * in the delay slot. + * Now fold the handler in the TLB refill handler space. */ - split = tlb_handler + MIPS64_REFILL_INSNS - 2; - + f = final_handler; + /* Simplest case, just copy the handler. */ + uasm_copy_handler(relocs, labels, tlb_handler, p, f); + final_len = p - tlb_handler; + break; + } else { + if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) + || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) + && uasm_insn_has_bdelay(relocs, + tlb_handler + MIPS64_REFILL_INSNS - 3))) + panic("TLB refill handler space exceeded"); /* - * If the branch would fall in a delay slot, - * we must back up an additional instruction - * so that it is no longer in a delay slot. + * Now fold the handler in the TLB refill handler space. */ - if (uasm_insn_has_bdelay(relocs, split - 1)) - split--; - } - /* Copy first part of the handler. */ - uasm_copy_handler(relocs, labels, tlb_handler, split, f); - f += split - tlb_handler; - - if (ov) { - /* Insert branch. */ - uasm_l_split(&l, final_handler); - uasm_il_b(&f, &r, label_split); - if (uasm_insn_has_bdelay(relocs, split)) - uasm_i_nop(&f); - else { - uasm_copy_handler(relocs, labels, - split, split + 1, f); - uasm_move_labels(labels, f, f + 1, -1); - f++; - split++; + f = final_handler + MIPS64_REFILL_INSNS; + if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { + /* Just copy the handler. */ + uasm_copy_handler(relocs, labels, tlb_handler, p, f); + final_len = p - tlb_handler; + } else { +#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT + const enum label_id ls = label_tlb_huge_update; +#else + const enum label_id ls = label_vmalloc; +#endif + u32 *split; + int ov = 0; + int i; + + for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) + ; + BUG_ON(i == ARRAY_SIZE(labels)); + split = labels[i].addr; + + /* + * See if we have overflown one way or the other. + */ + if (split > tlb_handler + MIPS64_REFILL_INSNS || + split < p - MIPS64_REFILL_INSNS) + ov = 1; + + if (ov) { + /* + * Split two instructions before the end. One + * for the branch and one for the instruction + * in the delay slot. + */ + split = tlb_handler + MIPS64_REFILL_INSNS - 2; + + /* + * If the branch would fall in a delay slot, + * we must back up an additional instruction + * so that it is no longer in a delay slot. + */ + if (uasm_insn_has_bdelay(relocs, split - 1)) + split--; + } + /* Copy first part of the handler. */ + uasm_copy_handler(relocs, labels, tlb_handler, split, f); + f += split - tlb_handler; + + if (ov) { + /* Insert branch. */ + uasm_l_split(&l, final_handler); + uasm_il_b(&f, &r, label_split); + if (uasm_insn_has_bdelay(relocs, split)) + uasm_i_nop(&f); + else { + uasm_copy_handler(relocs, labels, + split, split + 1, f); + uasm_move_labels(labels, f, f + 1, -1); + f++; + split++; + } + } + + /* Copy the rest of the handler. */ + uasm_copy_handler(relocs, labels, split, p, final_handler); + final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + + (p - split); } } - - /* Copy the rest of the handler. */ - uasm_copy_handler(relocs, labels, split, p, final_handler); - final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + - (p - split); + break; } -#endif /* CONFIG_64BIT */ uasm_resolve_relocs(relocs, labels); pr_debug("Wrote TLB refill handler (%u instructions).\n", @@ -1448,28 +1418,30 @@ static void build_r4000_tlb_refill_handler(void) extern u32 handle_tlbl[], handle_tlbl_end[]; extern u32 handle_tlbs[], handle_tlbs_end[]; extern u32 handle_tlbm[], handle_tlbm_end[]; - -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT extern u32 tlbmiss_handler_setup_pgd[], tlbmiss_handler_setup_pgd_end[]; -static void build_r4000_setup_pgd(void) +static void build_setup_pgd(void) { const int a0 = 4; - const int a1 = 5; + const int __maybe_unused a1 = 5; + const int __maybe_unused a2 = 6; u32 *p = tlbmiss_handler_setup_pgd; const int tlbmiss_handler_setup_pgd_size = tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd; - struct uasm_label *l = labels; - struct uasm_reloc *r = relocs; +#ifndef CONFIG_MIPS_PGD_C0_CONTEXT + long pgdc = (long)pgd_current; +#endif memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size * sizeof(tlbmiss_handler_setup_pgd[0])); memset(labels, 0, sizeof(labels)); memset(relocs, 0, sizeof(relocs)); - pgd_reg = allocate_kscratch(); - +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT if (pgd_reg == -1) { + struct uasm_label *l = labels; + struct uasm_reloc *r = relocs; + /* PGD << 11 in c0_Context */ /* * If it is a ckseg0 address, convert to a physical @@ -1491,6 +1463,26 @@ static void build_r4000_setup_pgd(void) uasm_i_jr(&p, 31); UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); } +#else +#ifdef CONFIG_SMP + /* Save PGD to pgd_current[smp_processor_id()] */ + UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG); + UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT); + UASM_i_LA_mostly(&p, a2, pgdc); + UASM_i_ADDU(&p, a2, a2, a1); + UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); +#else + UASM_i_LA_mostly(&p, a2, pgdc); + UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); +#endif /* SMP */ + uasm_i_jr(&p, 31); + + /* if pgd_reg is allocated, save PGD also to scratch register */ + if (pgd_reg != -1) + UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); + else + uasm_i_nop(&p); +#endif if (p >= tlbmiss_handler_setup_pgd_end) panic("tlbmiss_handler_setup_pgd space exceeded"); @@ -1501,7 +1493,6 @@ static void build_r4000_setup_pgd(void) dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd, tlbmiss_handler_setup_pgd_size); } -#endif static void iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) @@ -2194,10 +2185,8 @@ static void flush_tlb_handlers(void) (unsigned long)handle_tlbs_end); local_flush_icache_range((unsigned long)handle_tlbm, (unsigned long)handle_tlbm_end); -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, (unsigned long)tlbmiss_handler_setup_pgd_end); -#endif } void build_tlb_refill_handler(void) @@ -2229,6 +2218,7 @@ void build_tlb_refill_handler(void) if (!run_once) { if (!cpu_has_local_ebase) build_r3000_tlb_refill_handler(); + build_setup_pgd(); build_r3000_tlb_load_handler(); build_r3000_tlb_store_handler(); build_r3000_tlb_modify_handler(); @@ -2252,9 +2242,7 @@ void build_tlb_refill_handler(void) default: if (!run_once) { scratch_reg = allocate_kscratch(); -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT - build_r4000_setup_pgd(); -#endif + build_setup_pgd(); build_r4000_tlb_load_handler(); build_r4000_tlb_store_handler(); build_r4000_tlb_modify_handler(); diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index c69da3734699..0892575f829d 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -37,7 +37,6 @@ #include <asm/irq_regs.h> #include <asm/mips-boards/malta.h> #include <asm/mips-boards/maltaint.h> -#include <asm/mips-boards/piix4.h> #include <asm/gt64120.h> #include <asm/mips-boards/generic.h> #include <asm/mips-boards/msc01_pci.h> @@ -473,7 +472,7 @@ static void __init fill_ipi_map(void) { int cpu; - for (cpu = 0; cpu < NR_CPUS; cpu++) { + for (cpu = 0; cpu < nr_cpu_ids; cpu++) { fill_ipi_map1(gic_resched_int_base, cpu, GIC_CPU_INT1); fill_ipi_map1(gic_call_int_base, cpu, GIC_CPU_INT2); } @@ -574,8 +573,9 @@ void __init arch_init_irq(void) /* FIXME */ int i; #if defined(CONFIG_MIPS_MT_SMP) - gic_call_int_base = GIC_NUM_INTRS - NR_CPUS; - gic_resched_int_base = gic_call_int_base - NR_CPUS; + gic_call_int_base = GIC_NUM_INTRS - + (NR_CPUS - nr_cpu_ids) * 2 - nr_cpu_ids; + gic_resched_int_base = gic_call_int_base - nr_cpu_ids; fill_ipi_map(); #endif gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, @@ -599,7 +599,7 @@ void __init arch_init_irq(void) printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status()); write_c0_status(0x1100dc00); printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status()); - for (i = 0; i < NR_CPUS; i++) { + for (i = 0; i < nr_cpu_ids; i++) { arch_init_ipiirq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched); arch_init_ipiirq(MIPS_GIC_IRQ_BASE + diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c index 53aad4a35375..a18af5fce67e 100644 --- a/arch/mips/mti-malta/malta-time.c +++ b/arch/mips/mti-malta/malta-time.c @@ -27,6 +27,7 @@ #include <linux/timex.h> #include <linux/mc146818rtc.h> +#include <asm/cpu.h> #include <asm/mipsregs.h> #include <asm/mipsmtregs.h> #include <asm/hardirq.h> @@ -76,7 +77,7 @@ static void __init estimate_frequencies(void) #endif #if defined (CONFIG_KVM_GUEST) && defined (CONFIG_KVM_HOST_FREQ) - unsigned int prid = read_c0_prid() & 0xffff00; + unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK); /* * XXXKYMA: hardwire the CPU frequency to Host Freq/4 @@ -169,7 +170,7 @@ unsigned int get_c0_compare_int(void) void __init plat_time_init(void) { - unsigned int prid = read_c0_prid() & 0xffff00; + unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK); unsigned int freq; estimate_frequencies(); diff --git a/arch/mips/mti-sead3/sead3-setup.c b/arch/mips/mti-sead3/sead3-setup.c index b5059dc899f4..928ba84c8a78 100644 --- a/arch/mips/mti-sead3/sead3-setup.c +++ b/arch/mips/mti-sead3/sead3-setup.c @@ -10,6 +10,8 @@ #include <linux/of_fdt.h> #include <linux/bootmem.h> +#include <asm/prom.h> + #include <asm/mips-boards/generic.h> const char *get_system_type(void) diff --git a/arch/mips/mti-sead3/sead3-time.c b/arch/mips/mti-sead3/sead3-time.c index a43ea3cc0a3b..552d26c34386 100644 --- a/arch/mips/mti-sead3/sead3-time.c +++ b/arch/mips/mti-sead3/sead3-time.c @@ -7,6 +7,7 @@ */ #include <linux/init.h> +#include <asm/cpu.h> #include <asm/setup.h> #include <asm/time.h> #include <asm/irq.h> @@ -34,7 +35,7 @@ static void __iomem *status_reg = (void __iomem *)0xbf000410; */ static unsigned int __init estimate_cpu_frequency(void) { - unsigned int prid = read_c0_prid() & 0xffff00; + unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK); unsigned int tick = 0; unsigned int freq; unsigned int orig; diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig index 2447bf97d35a..852a4ee09954 100644 --- a/arch/mips/netlogic/Kconfig +++ b/arch/mips/netlogic/Kconfig @@ -19,6 +19,15 @@ config DT_XLP_SVP pointer to the kernel. The corresponding DTS file is at arch/mips/netlogic/dts/xlp_svp.dts +config DT_XLP_FVP + bool "Built-in device tree for XLP FVP boards" + default y + help + Add an FDT blob for XLP FVP board into the kernel. + This DTB will be used if the firmware does not pass in a DTB + pointer to the kernel. The corresponding DTS file is at + arch/mips/netlogic/dts/xlp_fvp.dts + config NLM_MULTINODE bool "Support for multi-chip boards" depends on NLM_XLP_BOARD diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c index 4e35d9c453e2..c0eded01fde9 100644 --- a/arch/mips/netlogic/common/smp.c +++ b/arch/mips/netlogic/common/smp.c @@ -106,9 +106,7 @@ void nlm_early_init_secondary(int cpu) { change_c0_config(CONF_CM_CMASK, 0x3); #ifdef CONFIG_CPU_XLP - /* mmu init, once per core */ - if (cpu % NLM_THREADS_PER_CORE == 0) - xlp_mmu_init(); + xlp_mmu_init(); #endif write_c0_ebase(nlm_current_node()->ebase); } @@ -247,7 +245,7 @@ static int nlm_parse_cpumask(cpumask_t *wakeup_mask) return threadmode; unsupp: - panic("Unsupported CPU mask %lx\n", + panic("Unsupported CPU mask %lx", (unsigned long)cpumask_bits(wakeup_mask)[0]); return 0; } diff --git a/arch/mips/netlogic/common/time.c b/arch/mips/netlogic/common/time.c index 045a396c57ce..13391b8a6031 100644 --- a/arch/mips/netlogic/common/time.c +++ b/arch/mips/netlogic/common/time.c @@ -45,6 +45,7 @@ #if defined(CONFIG_CPU_XLP) #include <asm/netlogic/xlp-hal/iomap.h> #include <asm/netlogic/xlp-hal/xlp.h> +#include <asm/netlogic/xlp-hal/sys.h> #include <asm/netlogic/xlp-hal/pic.h> #elif defined(CONFIG_CPU_XLR) #include <asm/netlogic/xlr/iomap.h> @@ -91,7 +92,7 @@ static void nlm_init_pic_timer(void) csrc_pic.read = nlm_get_pic_timer; } csrc_pic.rating = 1000; - clocksource_register_hz(&csrc_pic, PIC_CLK_HZ); + clocksource_register_hz(&csrc_pic, pic_timer_freq()); } void __init plat_time_init(void) diff --git a/arch/mips/netlogic/dts/Makefile b/arch/mips/netlogic/dts/Makefile index aecb6fa9a9c3..0b9be5fd2e46 100644 --- a/arch/mips/netlogic/dts/Makefile +++ b/arch/mips/netlogic/dts/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_DT_XLP_EVP) := xlp_evp.dtb.o obj-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb.o +obj-$(CONFIG_DT_XLP_FVP) += xlp_fvp.dtb.o diff --git a/arch/mips/netlogic/dts/xlp_evp.dts b/arch/mips/netlogic/dts/xlp_evp.dts index 06407033678e..89ad04808c02 100644 --- a/arch/mips/netlogic/dts/xlp_evp.dts +++ b/arch/mips/netlogic/dts/xlp_evp.dts @@ -9,19 +9,12 @@ #address-cells = <2>; #size-cells = <2>; - memory { - device_type = "memory"; - reg = <0 0x00100000 0 0x0FF00000 // 255M at 1M - 0 0x20000000 0 0xa0000000 // 2560M at 512M - 0 0xe0000000 1 0x00000000>; - }; - soc { #address-cells = <2>; #size-cells = <1>; compatible = "simple-bus"; ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG - 1 0 0 0x16000000 0x01000000>; // GBU chipselects + 1 0 0 0x16000000 0x02000000>; // GBU chipselects serial0: serial@30000 { device_type = "serial"; diff --git a/arch/mips/netlogic/dts/xlp_fvp.dts b/arch/mips/netlogic/dts/xlp_fvp.dts new file mode 100644 index 000000000000..63e62b7bd758 --- /dev/null +++ b/arch/mips/netlogic/dts/xlp_fvp.dts @@ -0,0 +1,118 @@ +/* + * XLP2XX Device Tree Source for FVP boards + */ + +/dts-v1/; +/ { + model = "netlogic,XLP-FVP"; + compatible = "netlogic,xlp"; + #address-cells = <2>; + #size-cells = <2>; + + soc { + #address-cells = <2>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG + 1 0 0 0x16000000 0x02000000>; // GBU chipselects + + serial0: serial@30000 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0 0x30100 0xa00>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <133333333>; + interrupt-parent = <&pic>; + interrupts = <17>; + }; + serial1: serial@31000 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0 0x31100 0xa00>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <133333333>; + interrupt-parent = <&pic>; + interrupts = <18>; + }; + i2c0: ocores@37100 { + compatible = "opencores,i2c-ocores"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x37100 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <32000000>; + interrupt-parent = <&pic>; + interrupts = <30>; + }; + i2c1: ocores@37120 { + compatible = "opencores,i2c-ocores"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x37120 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <32000000>; + interrupt-parent = <&pic>; + interrupts = <31>; + + rtc@68 { + compatible = "dallas,ds1374"; + reg = <0x68>; + }; + + dtt@4c { + compatible = "national,lm90"; + reg = <0x4c>; + }; + }; + pic: pic@4000 { + compatible = "netlogic,xlp-pic"; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0 0x4000 0x200>; + interrupt-controller; + }; + + nor_flash@1,0 { + compatible = "cfi-flash"; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + reg = <1 0 0x1000000>; + + partition@0 { + label = "x-loader"; + reg = <0x0 0x100000>; /* 1M */ + read-only; + }; + + partition@100000 { + label = "u-boot"; + reg = <0x100000 0x100000>; /* 1M */ + }; + + partition@200000 { + label = "kernel"; + reg = <0x200000 0x500000>; /* 5M */ + }; + + partition@700000 { + label = "rootfs"; + reg = <0x700000 0x800000>; /* 8M */ + }; + + partition@f00000 { + label = "env"; + reg = <0xf00000 0x100000>; /* 1M */ + read-only; + }; + }; + }; + + chosen { + bootargs = "console=ttyS0,115200 rdinit=/sbin/init"; + }; +}; diff --git a/arch/mips/netlogic/dts/xlp_svp.dts b/arch/mips/netlogic/dts/xlp_svp.dts index 9c5db102df53..1ebd00edaacc 100644 --- a/arch/mips/netlogic/dts/xlp_svp.dts +++ b/arch/mips/netlogic/dts/xlp_svp.dts @@ -9,19 +9,12 @@ #address-cells = <2>; #size-cells = <2>; - memory { - device_type = "memory"; - reg = <0 0x00100000 0 0x0FF00000 // 255M at 1M - 0 0x20000000 0 0xa0000000 // 2560M at 512M - 0 0xe0000000 0 0x40000000>; - }; - soc { #address-cells = <2>; #size-cells = <1>; compatible = "simple-bus"; ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG - 1 0 0 0x16000000 0x01000000>; // GBU chipselects + 1 0 0 0x16000000 0x02000000>; // GBU chipselects serial0: serial@30000 { device_type = "serial"; diff --git a/arch/mips/netlogic/xlp/Makefile b/arch/mips/netlogic/xlp/Makefile index 85ac4a892ced..ed9a93c04650 100644 --- a/arch/mips/netlogic/xlp/Makefile +++ b/arch/mips/netlogic/xlp/Makefile @@ -1,3 +1,4 @@ obj-y += setup.o nlm_hal.o cop2-ex.o dt.o obj-$(CONFIG_SMP) += wakeup.o obj-$(CONFIG_USB) += usb-init.o +obj-$(CONFIG_USB) += usb-init-xlp2.o diff --git a/arch/mips/netlogic/xlp/dt.c b/arch/mips/netlogic/xlp/dt.c index a15cdbb8d0bd..8316d5454b17 100644 --- a/arch/mips/netlogic/xlp/dt.c +++ b/arch/mips/netlogic/xlp/dt.c @@ -39,12 +39,21 @@ #include <linux/of_platform.h> #include <linux/of_device.h> -extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[], __dtb_start[]; +#include <asm/prom.h> + +extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[], + __dtb_xlp_fvp_begin[], __dtb_start[]; +static void *xlp_fdt_blob; void __init *xlp_dt_init(void *fdtp) { if (!fdtp) { switch (current_cpu_data.processor_id & 0xff00) { +#ifdef CONFIG_DT_XLP_FVP + case PRID_IMP_NETLOGIC_XLP2XX: + fdtp = __dtb_xlp_fvp_begin; + break; +#endif #ifdef CONFIG_DT_XLP_SVP case PRID_IMP_NETLOGIC_XLP3XX: fdtp = __dtb_xlp_svp_begin; @@ -61,19 +70,26 @@ void __init *xlp_dt_init(void *fdtp) break; } } - initial_boot_params = fdtp; + xlp_fdt_blob = fdtp; return fdtp; } +void __init xlp_early_init_devtree(void) +{ + __dt_setup_arch(xlp_fdt_blob); + strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE); +} + void __init device_tree_init(void) { unsigned long base, size; + struct boot_param_header *fdtp = xlp_fdt_blob; - if (!initial_boot_params) + if (!fdtp) return; - base = virt_to_phys((void *)initial_boot_params); - size = be32_to_cpu(initial_boot_params->totalsize); + base = virt_to_phys(fdtp); + size = be32_to_cpu(fdtp->totalsize); /* Before we do anything, lets reserve the dt blob */ reserve_bootmem(base, size, BOOTMEM_DEFAULT); diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c index 87560e4db35f..56c50ba43c9b 100644 --- a/arch/mips/netlogic/xlp/nlm_hal.c +++ b/arch/mips/netlogic/xlp/nlm_hal.c @@ -44,6 +44,7 @@ #include <asm/netlogic/haldefs.h> #include <asm/netlogic/xlp-hal/iomap.h> #include <asm/netlogic/xlp-hal/xlp.h> +#include <asm/netlogic/xlp-hal/bridge.h> #include <asm/netlogic/xlp-hal/pic.h> #include <asm/netlogic/xlp-hal/sys.h> @@ -64,6 +65,7 @@ int nlm_irq_to_irt(int irq) uint64_t pcibase; int devoff, irt; + devoff = 0; switch (irq) { case PIC_UART_0_IRQ: devoff = XLP_IO_UART0_OFFSET(0); @@ -71,44 +73,68 @@ int nlm_irq_to_irt(int irq) case PIC_UART_1_IRQ: devoff = XLP_IO_UART1_OFFSET(0); break; - case PIC_EHCI_0_IRQ: - devoff = XLP_IO_USB_EHCI0_OFFSET(0); - break; - case PIC_EHCI_1_IRQ: - devoff = XLP_IO_USB_EHCI1_OFFSET(0); - break; - case PIC_OHCI_0_IRQ: - devoff = XLP_IO_USB_OHCI0_OFFSET(0); - break; - case PIC_OHCI_1_IRQ: - devoff = XLP_IO_USB_OHCI1_OFFSET(0); - break; - case PIC_OHCI_2_IRQ: - devoff = XLP_IO_USB_OHCI2_OFFSET(0); - break; - case PIC_OHCI_3_IRQ: - devoff = XLP_IO_USB_OHCI3_OFFSET(0); - break; case PIC_MMC_IRQ: devoff = XLP_IO_SD_OFFSET(0); break; - case PIC_I2C_0_IRQ: - devoff = XLP_IO_I2C0_OFFSET(0); - break; + case PIC_I2C_0_IRQ: /* I2C will be fixed up */ case PIC_I2C_1_IRQ: - devoff = XLP_IO_I2C1_OFFSET(0); + case PIC_I2C_2_IRQ: + case PIC_I2C_3_IRQ: + if (cpu_is_xlpii()) + devoff = XLP2XX_IO_I2C_OFFSET(0); + else + devoff = XLP_IO_I2C0_OFFSET(0); break; default: - devoff = 0; - break; + if (cpu_is_xlpii()) { + switch (irq) { + /* XLP2XX has three XHCI USB controller */ + case PIC_2XX_XHCI_0_IRQ: + devoff = XLP2XX_IO_USB_XHCI0_OFFSET(0); + break; + case PIC_2XX_XHCI_1_IRQ: + devoff = XLP2XX_IO_USB_XHCI1_OFFSET(0); + break; + case PIC_2XX_XHCI_2_IRQ: + devoff = XLP2XX_IO_USB_XHCI2_OFFSET(0); + break; + } + } else { + switch (irq) { + case PIC_EHCI_0_IRQ: + devoff = XLP_IO_USB_EHCI0_OFFSET(0); + break; + case PIC_EHCI_1_IRQ: + devoff = XLP_IO_USB_EHCI1_OFFSET(0); + break; + case PIC_OHCI_0_IRQ: + devoff = XLP_IO_USB_OHCI0_OFFSET(0); + break; + case PIC_OHCI_1_IRQ: + devoff = XLP_IO_USB_OHCI1_OFFSET(0); + break; + case PIC_OHCI_2_IRQ: + devoff = XLP_IO_USB_OHCI2_OFFSET(0); + break; + case PIC_OHCI_3_IRQ: + devoff = XLP_IO_USB_OHCI3_OFFSET(0); + break; + } + } } if (devoff != 0) { pcibase = nlm_pcicfg_base(devoff); irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff; - /* HW bug, I2C 1 irt entry is off by one */ - if (irq == PIC_I2C_1_IRQ) - irt = irt + 1; + /* HW weirdness, I2C IRT entry has to be fixed up */ + switch (irq) { + case PIC_I2C_1_IRQ: + irt = irt + 1; break; + case PIC_I2C_2_IRQ: + irt = irt + 2; break; + case PIC_I2C_3_IRQ: + irt = irt + 3; break; + } } else if (irq >= PIC_PCIE_LINK_0_IRQ && irq <= PIC_PCIE_LINK_3_IRQ) { /* HW bug, PCI IRT entries are bad on early silicon, fix */ irt = PIC_IRT_PCIE_LINK_INDEX(irq - PIC_PCIE_LINK_0_IRQ); @@ -126,19 +152,160 @@ unsigned int nlm_get_core_frequency(int node, int core) sysbase = nlm_get_node(node)->sysbase; rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG); - dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE); - pll_divf = ((rstval >> 10) & 0x7f) + 1; - pll_divr = ((rstval >> 8) & 0x3) + 1; - ext_div = ((rstval >> 30) & 0x3) + 1; - dfs_div = ((dfsval >> (core * 4)) & 0xf) + 1; - - num = 800000000ULL * pll_divf; - denom = 3 * pll_divr * ext_div * dfs_div; + if (cpu_is_xlpii()) { + num = 1000000ULL * (400 * 3 + 100 * (rstval >> 26)); + denom = 3; + } else { + dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE); + pll_divf = ((rstval >> 10) & 0x7f) + 1; + pll_divr = ((rstval >> 8) & 0x3) + 1; + ext_div = ((rstval >> 30) & 0x3) + 1; + dfs_div = ((dfsval >> (core * 4)) & 0xf) + 1; + + num = 800000000ULL * pll_divf; + denom = 3 * pll_divr * ext_div * dfs_div; + } do_div(num, denom); return (unsigned int)num; } +/* Calculate Frequency to the PIC from PLL. + * freq_out = ( ref_freq/2 * (6 + ctrl2[7:0]) + ctrl2[20:8]/2^13 ) / + * ((2^ctrl0[7:5]) * Table(ctrl0[26:24])) + */ +static unsigned int nlm_2xx_get_pic_frequency(int node) +{ + u32 ctrl_val0, ctrl_val2, vco_post_div, pll_post_div; + u32 mdiv, fdiv, pll_out_freq_den, reg_select, ref_div, pic_div; + u64 ref_clk, sysbase, pll_out_freq_num, ref_clk_select; + + sysbase = nlm_get_node(node)->sysbase; + + /* Find ref_clk_base */ + ref_clk_select = + (nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG) >> 18) & 0x3; + switch (ref_clk_select) { + case 0: + ref_clk = 200000000ULL; + ref_div = 3; + break; + case 1: + ref_clk = 100000000ULL; + ref_div = 1; + break; + case 2: + ref_clk = 125000000ULL; + ref_div = 1; + break; + case 3: + ref_clk = 400000000ULL; + ref_div = 3; + break; + } + + /* Find the clock source PLL device for PIC */ + reg_select = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_SEL) >> 22) & 0x3; + switch (reg_select) { + case 0: + ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0); + ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2); + break; + case 1: + ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(0)); + ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(0)); + break; + case 2: + ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(1)); + ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(1)); + break; + case 3: + ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(2)); + ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(2)); + break; + } + + vco_post_div = (ctrl_val0 >> 5) & 0x7; + pll_post_div = (ctrl_val0 >> 24) & 0x7; + mdiv = ctrl_val2 & 0xff; + fdiv = (ctrl_val2 >> 8) & 0xfff; + + /* Find PLL post divider value */ + switch (pll_post_div) { + case 1: + pll_post_div = 2; + break; + case 3: + pll_post_div = 4; + break; + case 7: + pll_post_div = 8; + break; + case 6: + pll_post_div = 16; + break; + case 0: + default: + pll_post_div = 1; + break; + } + + fdiv = fdiv/(1 << 13); + pll_out_freq_num = ((ref_clk >> 1) * (6 + mdiv)) + fdiv; + pll_out_freq_den = (1 << vco_post_div) * pll_post_div * 3; + + if (pll_out_freq_den > 0) + do_div(pll_out_freq_num, pll_out_freq_den); + + /* PIC post divider, which happens after PLL */ + pic_div = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_DIV) >> 22) & 0x3; + do_div(pll_out_freq_num, 1 << pic_div); + + return pll_out_freq_num; +} + +unsigned int nlm_get_pic_frequency(int node) +{ + if (cpu_is_xlpii()) + return nlm_2xx_get_pic_frequency(node); + else + return 133333333; +} + unsigned int nlm_get_cpu_frequency(void) { return nlm_get_core_frequency(0, 0); } + +/* + * Fills upto 8 pairs of entries containing the DRAM map of a node + * if n < 0, get dram map for all nodes + */ +int xlp_get_dram_map(int n, uint64_t *dram_map) +{ + uint64_t bridgebase, base, lim; + uint32_t val; + int i, node, rv; + + /* Look only at mapping on Node 0, we don't handle crazy configs */ + bridgebase = nlm_get_bridge_regbase(0); + rv = 0; + for (i = 0; i < 8; i++) { + val = nlm_read_bridge_reg(bridgebase, + BRIDGE_DRAM_NODE_TRANSLN(i)); + node = (val >> 1) & 0x3; + if (n >= 0 && n != node) + continue; + val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_BAR(i)); + val = (val >> 12) & 0xfffff; + base = (uint64_t) val << 20; + val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_LIMIT(i)); + val = (val >> 12) & 0xfffff; + if (val == 0) /* BAR not used */ + continue; + lim = ((uint64_t)val + 1) << 20; + dram_map[rv] = base; + dram_map[rv + 1] = lim; + rv += 2; + } + return rv; +} diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c index 7b638f7be491..6d981bb337ec 100644 --- a/arch/mips/netlogic/xlp/setup.c +++ b/arch/mips/netlogic/xlp/setup.c @@ -73,6 +73,23 @@ static void nlm_fixup_mem(void) } } +static void __init xlp_init_mem_from_bars(void) +{ + uint64_t map[16]; + int i, n; + + n = xlp_get_dram_map(-1, map); /* -1: info for all nodes */ + for (i = 0; i < n; i += 2) { + /* exclude 0x1000_0000-0x2000_0000, u-boot device */ + if (map[i] <= 0x10000000 && map[i+1] > 0x10000000) + map[i+1] = 0x10000000; + if (map[i] > 0x10000000 && map[i] < 0x20000000) + map[i] = 0x20000000; + + add_memory_region(map[i], map[i+1] - map[i], BOOT_MEM_RAM); + } +} + void __init plat_mem_setup(void) { panic_timeout = 5; @@ -81,13 +98,24 @@ void __init plat_mem_setup(void) pm_power_off = nlm_linux_exit; /* memory and bootargs from DT */ - early_init_devtree(initial_boot_params); + xlp_early_init_devtree(); + + if (boot_mem_map.nr_map == 0) { + pr_info("Using DRAM BARs for memory map.\n"); + xlp_init_mem_from_bars(); + } + /* Calculate and setup wired entries for mapped kernel */ nlm_fixup_mem(); } const char *get_system_type(void) { - return "Netlogic XLP Series"; + switch (read_c0_prid() & 0xff00) { + case PRID_IMP_NETLOGIC_XLP2XX: + return "Broadcom XLPII Series"; + default: + return "Netlogic XLP Series"; + } } void __init prom_free_prom_memory(void) @@ -97,12 +125,20 @@ void __init prom_free_prom_memory(void) void xlp_mmu_init(void) { - /* enable extended TLB and Large Fixed TLB */ - write_c0_config6(read_c0_config6() | 0x24); - - /* set page mask of Fixed TLB in config7 */ - write_c0_config7(PM_DEFAULT_MASK >> - (13 + (ffz(PM_DEFAULT_MASK >> 13) / 2))); + u32 conf4; + + if (cpu_is_xlpii()) { + /* XLPII series has extended pagesize in config 4 */ + conf4 = read_c0_config4() & ~0x1f00u; + write_c0_config4(conf4 | ((PAGE_SHIFT - 10) / 2 << 8)); + } else { + /* enable extended TLB and Large Fixed TLB */ + write_c0_config6(read_c0_config6() | 0x24); + + /* set page mask of extended Fixed TLB in config7 */ + write_c0_config7(PM_DEFAULT_MASK >> + (13 + (ffz(PM_DEFAULT_MASK >> 13) / 2))); + } } void nlm_percpu_init(int hwcpuid) diff --git a/arch/mips/netlogic/xlp/usb-init-xlp2.c b/arch/mips/netlogic/xlp/usb-init-xlp2.c new file mode 100644 index 000000000000..36e9c22afc46 --- /dev/null +++ b/arch/mips/netlogic/xlp/usb-init-xlp2.c @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2003-2013 Broadcom Corporation + * All Rights Reserved + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the Broadcom + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <linux/dma-mapping.h> +#include <linux/kernel.h> +#include <linux/delay.h> +#include <linux/init.h> +#include <linux/pci.h> +#include <linux/platform_device.h> +#include <linux/irq.h> + +#include <asm/netlogic/common.h> +#include <asm/netlogic/haldefs.h> +#include <asm/netlogic/xlp-hal/iomap.h> +#include <asm/netlogic/xlp-hal/xlp.h> + +#define XLPII_USB3_CTL_0 0xc0 +#define XLPII_VAUXRST BIT(0) +#define XLPII_VCCRST BIT(1) +#define XLPII_NUM2PORT 9 +#define XLPII_NUM3PORT 13 +#define XLPII_RTUNEREQ BIT(20) +#define XLPII_MS_CSYSREQ BIT(21) +#define XLPII_XS_CSYSREQ BIT(22) +#define XLPII_RETENABLEN BIT(23) +#define XLPII_TX2RX BIT(24) +#define XLPII_XHCIREV BIT(25) +#define XLPII_ECCDIS BIT(26) + +#define XLPII_USB3_INT_REG 0xc2 +#define XLPII_USB3_INT_MASK 0xc3 + +#define XLPII_USB_PHY_TEST 0xc6 +#define XLPII_PRESET BIT(0) +#define XLPII_ATERESET BIT(1) +#define XLPII_LOOPEN BIT(2) +#define XLPII_TESTPDHSP BIT(3) +#define XLPII_TESTPDSSP BIT(4) +#define XLPII_TESTBURNIN BIT(5) + +#define XLPII_USB_PHY_LOS_LV 0xc9 +#define XLPII_LOSLEV 0 +#define XLPII_LOSBIAS 5 +#define XLPII_SQRXTX 8 +#define XLPII_TXBOOST 11 +#define XLPII_RSLKSEL 16 +#define XLPII_FSEL 20 + +#define XLPII_USB_RFCLK_REG 0xcc +#define XLPII_VVLD 30 + +#define nlm_read_usb_reg(b, r) nlm_read_reg(b, r) +#define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v) + +#define nlm_xlpii_get_usb_pcibase(node, inst) \ + nlm_pcicfg_base(XLP2XX_IO_USB_OFFSET(node, inst)) +#define nlm_xlpii_get_usb_regbase(node, inst) \ + (nlm_xlpii_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ) + +static void xlpii_usb_ack(struct irq_data *data) +{ + u64 port_addr; + + switch (data->irq) { + case PIC_2XX_XHCI_0_IRQ: + port_addr = nlm_xlpii_get_usb_regbase(0, 1); + break; + case PIC_2XX_XHCI_1_IRQ: + port_addr = nlm_xlpii_get_usb_regbase(0, 2); + break; + case PIC_2XX_XHCI_2_IRQ: + port_addr = nlm_xlpii_get_usb_regbase(0, 3); + break; + default: + pr_err("No matching USB irq!\n"); + return; + } + nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff); +} + +static void nlm_xlpii_usb_hw_reset(int node, int port) +{ + u64 port_addr, xhci_base, pci_base; + void __iomem *corebase; + u32 val; + + port_addr = nlm_xlpii_get_usb_regbase(node, port); + + /* Set frequency */ + val = nlm_read_usb_reg(port_addr, XLPII_USB_PHY_LOS_LV); + val &= ~(0x3f << XLPII_FSEL); + val |= (0x27 << XLPII_FSEL); + nlm_write_usb_reg(port_addr, XLPII_USB_PHY_LOS_LV, val); + + val = nlm_read_usb_reg(port_addr, XLPII_USB_RFCLK_REG); + val |= (1 << XLPII_VVLD); + nlm_write_usb_reg(port_addr, XLPII_USB_RFCLK_REG, val); + + /* PHY reset */ + val = nlm_read_usb_reg(port_addr, XLPII_USB_PHY_TEST); + val &= (XLPII_ATERESET | XLPII_LOOPEN | XLPII_TESTPDHSP + | XLPII_TESTPDSSP | XLPII_TESTBURNIN); + nlm_write_usb_reg(port_addr, XLPII_USB_PHY_TEST, val); + + /* Setup control register */ + val = XLPII_VAUXRST | XLPII_VCCRST | (1 << XLPII_NUM2PORT) + | (1 << XLPII_NUM3PORT) | XLPII_MS_CSYSREQ | XLPII_XS_CSYSREQ + | XLPII_RETENABLEN | XLPII_XHCIREV; + nlm_write_usb_reg(port_addr, XLPII_USB3_CTL_0, val); + + /* Enable interrupts */ + nlm_write_usb_reg(port_addr, XLPII_USB3_INT_MASK, 0x00000001); + + /* Clear all interrupts */ + nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff); + + udelay(2000); + + /* XHCI configuration at PCI mem */ + pci_base = nlm_xlpii_get_usb_pcibase(node, port); + xhci_base = nlm_read_usb_reg(pci_base, 0x4) & ~0xf; + corebase = ioremap(xhci_base, 0x10000); + if (!corebase) + return; + + writel(0x240002, corebase + 0xc2c0); + /* GCTL 0xc110 */ + val = readl(corebase + 0xc110); + val &= ~(0x3 << 12); + val |= (1 << 12); + writel(val, corebase + 0xc110); + udelay(100); + + /* PHYCFG 0xc200 */ + val = readl(corebase + 0xc200); + val &= ~(1 << 6); + writel(val, corebase + 0xc200); + udelay(100); + + /* PIPECTL 0xc2c0 */ + val = readl(corebase + 0xc2c0); + val &= ~(1 << 17); + writel(val, corebase + 0xc2c0); + + iounmap(corebase); +} + +static int __init nlm_platform_xlpii_usb_init(void) +{ + if (!cpu_is_xlpii()) + return 0; + + pr_info("Initializing 2XX USB Interface\n"); + nlm_xlpii_usb_hw_reset(0, 1); + nlm_xlpii_usb_hw_reset(0, 2); + nlm_xlpii_usb_hw_reset(0, 3); + nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_0_IRQ, xlpii_usb_ack); + nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_1_IRQ, xlpii_usb_ack); + nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_2_IRQ, xlpii_usb_ack); + + return 0; +} + +arch_initcall(nlm_platform_xlpii_usb_init); + +static u64 xlp_usb_dmamask = ~(u32)0; + +/* Fixup IRQ for USB devices on XLP the SoC PCIe bus */ +static void nlm_usb_fixup_final(struct pci_dev *dev) +{ + dev->dev.dma_mask = &xlp_usb_dmamask; + dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); + switch (dev->devfn) { + case 0x21: + dev->irq = PIC_2XX_XHCI_0_IRQ; + break; + case 0x22: + dev->irq = PIC_2XX_XHCI_1_IRQ; + break; + case 0x23: + dev->irq = PIC_2XX_XHCI_2_IRQ; + break; + } +} + +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_XHCI, + nlm_usb_fixup_final); diff --git a/arch/mips/netlogic/xlp/usb-init.c b/arch/mips/netlogic/xlp/usb-init.c index ef3897ef0dc7..f8117985f0f8 100644 --- a/arch/mips/netlogic/xlp/usb-init.c +++ b/arch/mips/netlogic/xlp/usb-init.c @@ -75,8 +75,7 @@ static void nlm_usb_intr_en(int node, int port) port_addr = nlm_get_usb_regbase(node, port); val = nlm_read_usb_reg(port_addr, USB_INT_EN); val = USB_CTRL_INTERRUPT_EN | USB_OHCI_INTERRUPT_EN | - USB_OHCI_INTERRUPT1_EN | USB_CTRL_INTERRUPT_EN | - USB_OHCI_INTERRUPT_EN | USB_OHCI_INTERRUPT2_EN; + USB_OHCI_INTERRUPT1_EN | USB_OHCI_INTERRUPT2_EN; nlm_write_usb_reg(port_addr, USB_INT_EN, val); } @@ -100,6 +99,9 @@ static void nlm_usb_hw_reset(int node, int port) static int __init nlm_platform_usb_init(void) { + if (cpu_is_xlpii()) + return 0; + pr_info("Initializing USB Interface\n"); nlm_usb_hw_reset(0, 0); nlm_usb_hw_reset(0, 3); diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c index 0cce37cbffef..682d5638dc01 100644 --- a/arch/mips/netlogic/xlp/wakeup.c +++ b/arch/mips/netlogic/xlp/wakeup.c @@ -58,10 +58,12 @@ static int xlp_wakeup_core(uint64_t sysbase, int node, int core) coremask = (1 << core); - /* Enable CPU clock */ - value = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL); - value &= ~coremask; - nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value); + /* Enable CPU clock in case of 8xx/3xx */ + if (!cpu_is_xlpii()) { + value = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL); + value &= ~coremask; + nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value); + } /* Remove CPU Reset */ value = nlm_read_sys_reg(sysbase, SYS_CPU_RESET); diff --git a/arch/mips/netlogic/xlr/fmn-config.c b/arch/mips/netlogic/xlr/fmn-config.c index ed3bf0e3f309..c7622c6e5f67 100644 --- a/arch/mips/netlogic/xlr/fmn-config.c +++ b/arch/mips/netlogic/xlr/fmn-config.c @@ -36,6 +36,7 @@ #include <linux/irq.h> #include <linux/interrupt.h> +#include <asm/cpu.h> #include <asm/mipsregs.h> #include <asm/netlogic/xlr/fmn.h> #include <asm/netlogic/xlr/xlr.h> @@ -187,7 +188,7 @@ void xlr_board_info_setup(void) int processor_id, num_core; num_core = hweight32(nlm_current_node()->coremask); - processor_id = read_c0_prid() & 0xff00; + processor_id = read_c0_prid() & PRID_IMP_MASK; setup_cpu_fmninfo(cpu, num_core); switch (processor_id) { diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c index 5e5424753b56..4d1736fc1955 100644 --- a/arch/mips/oprofile/common.c +++ b/arch/mips/oprofile/common.c @@ -12,6 +12,7 @@ #include <linux/oprofile.h> #include <linux/smp.h> #include <asm/cpu-info.h> +#include <asm/cpu-type.h> #include "op_impl.h" diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index c382042911dd..719e4557e22e 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o obj-$(CONFIG_LANTIQ) += fixup-lantiq.o obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o +obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o diff --git a/arch/mips/pci/fixup-lantiq.c b/arch/mips/pci/fixup-lantiq.c index 6c829df28dc7..c2ce41ea61d7 100644 --- a/arch/mips/pci/fixup-lantiq.c +++ b/arch/mips/pci/fixup-lantiq.c @@ -25,16 +25,5 @@ int pcibios_plat_dev_init(struct pci_dev *dev) int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { - struct of_irq dev_irq; - int irq; - - if (of_irq_map_pci(dev, &dev_irq)) { - dev_err(&dev->dev, "trying to map irq for unknown slot:%d pin:%d\n", - slot, pin); - return 0; - } - irq = irq_create_of_mapping(dev_irq.controller, dev_irq.specifier, - dev_irq.size); - dev_info(&dev->dev, "SLOT:%d PIN:%d IRQ:%d\n", slot, pin, irq); - return irq; + return of_irq_parse_and_map_pci(dev, slot, pin); } diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c index 07ada7f8441e..df36e2327c54 100644 --- a/arch/mips/pci/fixup-malta.c +++ b/arch/mips/pci/fixup-malta.c @@ -1,5 +1,6 @@ #include <linux/init.h> #include <linux/pci.h> +#include <asm/mips-boards/piix4.h> /* PCI interrupt pins */ #define PCIA 1 @@ -53,7 +54,8 @@ int pcibios_plat_dev_init(struct pci_dev *dev) static void malta_piix_func0_fixup(struct pci_dev *pdev) { unsigned char reg_val; - static int piixirqmap[16] = { /* PIIX PIRQC[A:D] irq mappings */ + /* PIIX PIRQC[A:D] irq mappings */ + static int piixirqmap[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX] = { 0, 0, 0, 3, 4, 5, 6, 7, 0, 9, 10, 11, @@ -63,11 +65,12 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev) /* Interrogate PIIX4 to get PCI IRQ mapping */ for (i = 0; i <= 3; i++) { - pci_read_config_byte(pdev, 0x60+i, ®_val); - if (reg_val & 0x80) + pci_read_config_byte(pdev, PIIX4_FUNC0_PIRQRC+i, ®_val); + if (reg_val & PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE) pci_irq[PCIA+i] = 0; /* Disabled */ else - pci_irq[PCIA+i] = piixirqmap[reg_val & 15]; + pci_irq[PCIA+i] = piixirqmap[reg_val & + PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK]; } /* Done by YAMON 2.00 onwards */ @@ -76,8 +79,9 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev) * Set top of main memory accessible by ISA or DMA * devices to 16 Mb. */ - pci_read_config_byte(pdev, 0x69, ®_val); - pci_write_config_byte(pdev, 0x69, reg_val | 0xf0); + pci_read_config_byte(pdev, PIIX4_FUNC0_TOM, ®_val); + pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val | + PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK); } } @@ -93,10 +97,14 @@ static void malta_piix_func1_fixup(struct pci_dev *pdev) /* * IDE Decode enable. */ - pci_read_config_byte(pdev, 0x41, ®_val); - pci_write_config_byte(pdev, 0x41, reg_val|0x80); - pci_read_config_byte(pdev, 0x43, ®_val); - pci_write_config_byte(pdev, 0x43, reg_val|0x80); + pci_read_config_byte(pdev, PIIX4_FUNC1_IDETIM_PRIMARY_HI, + ®_val); + pci_write_config_byte(pdev, PIIX4_FUNC1_IDETIM_PRIMARY_HI, + reg_val|PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN); + pci_read_config_byte(pdev, PIIX4_FUNC1_IDETIM_SECONDARY_HI, + ®_val); + pci_write_config_byte(pdev, PIIX4_FUNC1_IDETIM_SECONDARY_HI, + reg_val|PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN); } } @@ -108,10 +116,12 @@ static void quirk_dlcsetup(struct pci_dev *dev) { u8 odlc, ndlc; - (void) pci_read_config_byte(dev, 0x82, &odlc); + (void) pci_read_config_byte(dev, PIIX4_FUNC0_DLC, &odlc); /* Enable passive releases and delayed transaction */ - ndlc = odlc | 7; - (void) pci_write_config_byte(dev, 0x82, ndlc); + ndlc = odlc | PIIX4_FUNC0_DLC_USBPR_EN | + PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN | + PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN; + (void) pci_write_config_byte(dev, PIIX4_FUNC0_DLC, ndlc); } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, diff --git a/arch/mips/pci/pci-ar71xx.c b/arch/mips/pci/pci-ar71xx.c index 18517dd0f709..d471a26dd5f8 100644 --- a/arch/mips/pci/pci-ar71xx.c +++ b/arch/mips/pci/pci-ar71xx.c @@ -363,9 +363,6 @@ static int ar71xx_pci_probe(struct platform_device *pdev) spin_lock_init(&apc->lock); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base"); - if (!res) - return -EINVAL; - apc->cfg_base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(apc->cfg_base)) return PTR_ERR(apc->cfg_base); diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c index 65ec032fa0b4..785b2659b519 100644 --- a/arch/mips/pci/pci-ar724x.c +++ b/arch/mips/pci/pci-ar724x.c @@ -362,25 +362,16 @@ static int ar724x_pci_probe(struct platform_device *pdev) return -ENOMEM; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base"); - if (!res) - return -EINVAL; - apc->ctrl_base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(apc->ctrl_base)) return PTR_ERR(apc->ctrl_base); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base"); - if (!res) - return -EINVAL; - apc->devcfg_base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(apc->devcfg_base)) return PTR_ERR(apc->devcfg_base); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "crp_base"); - if (!res) - return -EINVAL; - apc->crp_base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(apc->crp_base)) return PTR_ERR(apc->crp_base); diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c index 44dd5aa2e36f..5ec2a7bae02c 100644 --- a/arch/mips/pci/pci-bcm1480.c +++ b/arch/mips/pci/pci-bcm1480.c @@ -39,6 +39,7 @@ #include <linux/mm.h> #include <linux/console.h> #include <linux/tty.h> +#include <linux/vt.h> #include <asm/sibyte/bcm1480_regs.h> #include <asm/sibyte/bcm1480_scd.h> diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c index 95c2ea815cac..59cccd95688b 100644 --- a/arch/mips/pci/pci-octeon.c +++ b/arch/mips/pci/pci-octeon.c @@ -586,15 +586,16 @@ static int __init octeon_pci_setup(void) else octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG; - /* PCI I/O and PCI MEM values */ - set_io_port_base(OCTEON_PCI_IOSPACE_BASE); - ioport_resource.start = 0; - ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1; if (!octeon_is_pci_host()) { pr_notice("Not in host mode, PCI Controller not initialized\n"); return 0; } + /* PCI I/O and PCI MEM values */ + set_io_port_base(OCTEON_PCI_IOSPACE_BASE); + ioport_resource.start = 0; + ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1; + pr_notice("%s Octeon big bar support\n", (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling"); diff --git a/arch/mips/pci/pci-rt3883.c b/arch/mips/pci/pci-rt3883.c new file mode 100644 index 000000000000..adeff2bfe4cd --- /dev/null +++ b/arch/mips/pci/pci-rt3883.c @@ -0,0 +1,614 @@ +/* + * Ralink RT3662/RT3883 SoC PCI support + * + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org> + * + * Parts of this file are based on Ralink's 2.6.21 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/types.h> +#include <linux/pci.h> +#include <linux/io.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/of_pci.h> +#include <linux/platform_device.h> + +#include <asm/mach-ralink/rt3883.h> +#include <asm/mach-ralink/ralink_regs.h> + +#define RT3883_MEMORY_BASE 0x00000000 +#define RT3883_MEMORY_SIZE 0x02000000 + +#define RT3883_PCI_REG_PCICFG 0x00 +#define RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf +#define RT3883_PCICFG_P2P_BR_DEVNUM_S 16 +#define RT3883_PCICFG_PCIRST BIT(1) +#define RT3883_PCI_REG_PCIRAW 0x04 +#define RT3883_PCI_REG_PCIINT 0x08 +#define RT3883_PCI_REG_PCIENA 0x0c + +#define RT3883_PCI_REG_CFGADDR 0x20 +#define RT3883_PCI_REG_CFGDATA 0x24 +#define RT3883_PCI_REG_MEMBASE 0x28 +#define RT3883_PCI_REG_IOBASE 0x2c +#define RT3883_PCI_REG_ARBCTL 0x80 + +#define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000) +#define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10) +#define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18) +#define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30) +#define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34) +#define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38) +#define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50) + +#define RT3883_PCI_MODE_NONE 0 +#define RT3883_PCI_MODE_PCI BIT(0) +#define RT3883_PCI_MODE_PCIE BIT(1) +#define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE) + +#define RT3883_PCI_IRQ_COUNT 32 + +#define RT3883_P2P_BR_DEVNUM 1 + +struct rt3883_pci_controller { + void __iomem *base; + spinlock_t lock; + + struct device_node *intc_of_node; + struct irq_domain *irq_domain; + + struct pci_controller pci_controller; + struct resource io_res; + struct resource mem_res; + + bool pcie_ready; +}; + +static inline struct rt3883_pci_controller * +pci_bus_to_rt3883_controller(struct pci_bus *bus) +{ + struct pci_controller *hose; + + hose = (struct pci_controller *) bus->sysdata; + return container_of(hose, struct rt3883_pci_controller, pci_controller); +} + +static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc, + unsigned reg) +{ + return ioread32(rpc->base + reg); +} + +static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc, + u32 val, unsigned reg) +{ + iowrite32(val, rpc->base + reg); +} + +static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot, + unsigned int func, unsigned int where) +{ + return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | + 0x80000000; +} + +static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc, + unsigned bus, unsigned slot, + unsigned func, unsigned reg) +{ + unsigned long flags; + u32 address; + u32 ret; + + address = rt3883_pci_get_cfgaddr(bus, slot, func, reg); + + spin_lock_irqsave(&rpc->lock, flags); + rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); + ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA); + spin_unlock_irqrestore(&rpc->lock, flags); + + return ret; +} + +static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc, + unsigned bus, unsigned slot, + unsigned func, unsigned reg, u32 val) +{ + unsigned long flags; + u32 address; + + address = rt3883_pci_get_cfgaddr(bus, slot, func, reg); + + spin_lock_irqsave(&rpc->lock, flags); + rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); + rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA); + spin_unlock_irqrestore(&rpc->lock, flags); +} + +static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + struct rt3883_pci_controller *rpc; + u32 pending; + + rpc = irq_get_handler_data(irq); + + pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) & + rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); + + if (!pending) { + spurious_interrupt(); + return; + } + + while (pending) { + unsigned bit = __ffs(pending); + + irq = irq_find_mapping(rpc->irq_domain, bit); + generic_handle_irq(irq); + + pending &= ~BIT(bit); + } +} + +static void rt3883_pci_irq_unmask(struct irq_data *d) +{ + struct rt3883_pci_controller *rpc; + u32 t; + + rpc = irq_data_get_irq_chip_data(d); + + t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); + rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA); + /* flush write */ + rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); +} + +static void rt3883_pci_irq_mask(struct irq_data *d) +{ + struct rt3883_pci_controller *rpc; + u32 t; + + rpc = irq_data_get_irq_chip_data(d); + + t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); + rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA); + /* flush write */ + rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); +} + +static struct irq_chip rt3883_pci_irq_chip = { + .name = "RT3883 PCI", + .irq_mask = rt3883_pci_irq_mask, + .irq_unmask = rt3883_pci_irq_unmask, + .irq_mask_ack = rt3883_pci_irq_mask, +}; + +static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hw) +{ + irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq); + irq_set_chip_data(irq, d->host_data); + + return 0; +} + +static const struct irq_domain_ops rt3883_pci_irq_domain_ops = { + .map = rt3883_pci_irq_map, + .xlate = irq_domain_xlate_onecell, +}; + +static int rt3883_pci_irq_init(struct device *dev, + struct rt3883_pci_controller *rpc) +{ + int irq; + + irq = irq_of_parse_and_map(rpc->intc_of_node, 0); + if (irq == 0) { + dev_err(dev, "%s has no IRQ", + of_node_full_name(rpc->intc_of_node)); + return -EINVAL; + } + + /* disable all interrupts */ + rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA); + + rpc->irq_domain = + irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT, + &rt3883_pci_irq_domain_ops, + rpc); + if (!rpc->irq_domain) { + dev_err(dev, "unable to add IRQ domain\n"); + return -ENODEV; + } + + irq_set_handler_data(irq, rpc); + irq_set_chained_handler(irq, rt3883_pci_irq_handler); + + return 0; +} + +static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + struct rt3883_pci_controller *rpc; + unsigned long flags; + u32 address; + u32 data; + + rpc = pci_bus_to_rt3883_controller(bus); + + if (!rpc->pcie_ready && bus->number == 1) + return PCIBIOS_DEVICE_NOT_FOUND; + + address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), + PCI_FUNC(devfn), where); + + spin_lock_irqsave(&rpc->lock, flags); + rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); + data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA); + spin_unlock_irqrestore(&rpc->lock, flags); + + switch (size) { + case 1: + *val = (data >> ((where & 3) << 3)) & 0xff; + break; + case 2: + *val = (data >> ((where & 3) << 3)) & 0xffff; + break; + case 4: + *val = data; + break; + } + + return PCIBIOS_SUCCESSFUL; +} + +static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + struct rt3883_pci_controller *rpc; + unsigned long flags; + u32 address; + u32 data; + + rpc = pci_bus_to_rt3883_controller(bus); + + if (!rpc->pcie_ready && bus->number == 1) + return PCIBIOS_DEVICE_NOT_FOUND; + + address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), + PCI_FUNC(devfn), where); + + spin_lock_irqsave(&rpc->lock, flags); + rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); + data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA); + + switch (size) { + case 1: + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + break; + case 2: + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + break; + case 4: + data = val; + break; + } + + rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA); + spin_unlock_irqrestore(&rpc->lock, flags); + + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops rt3883_pci_ops = { + .read = rt3883_pci_config_read, + .write = rt3883_pci_config_write, +}; + +static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode) +{ + u32 syscfg1; + u32 rstctrl; + u32 clkcfg1; + u32 t; + + rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); + syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1); + clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); + + if (mode & RT3883_PCI_MODE_PCIE) { + rstctrl |= RT3883_RSTCTRL_PCIE; + rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL); + + /* setup PCI PAD drive mode */ + syscfg1 &= ~(0x30); + syscfg1 |= (2 << 4); + rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1); + + t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); + t &= ~BIT(31); + rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0); + + t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); + t &= 0x80ffffff; + rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1); + + t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); + t |= 0xa << 24; + rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1); + + t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); + t |= BIT(31); + rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0); + + msleep(50); + + rstctrl &= ~RT3883_RSTCTRL_PCIE; + rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL); + } + + syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE); + + clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN); + + if (mode & RT3883_PCI_MODE_PCI) { + clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN; + rstctrl &= ~RT3883_RSTCTRL_PCI; + } + + if (mode & RT3883_PCI_MODE_PCIE) { + clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN; + rstctrl &= ~RT3883_RSTCTRL_PCIE; + } + + rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1); + rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL); + rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1); + + msleep(500); + + /* + * setup the device number of the P2P bridge + * and de-assert the reset line + */ + t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S); + rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG); + + /* flush write */ + rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG); + msleep(500); + + if (mode & RT3883_PCI_MODE_PCIE) { + msleep(500); + + t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1)); + + rpc->pcie_ready = t & BIT(0); + + if (!rpc->pcie_ready) { + /* reset the PCIe block */ + t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); + t |= RT3883_RSTCTRL_PCIE; + rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL); + t &= ~RT3883_RSTCTRL_PCIE; + rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL); + + /* turn off PCIe clock */ + t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); + t &= ~RT3883_CLKCFG1_PCIE_CLK_EN; + rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1); + + t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); + t &= ~0xf000c080; + rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0); + } + } + + /* enable PCI arbiter */ + rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL); +} + +static int rt3883_pci_probe(struct platform_device *pdev) +{ + struct rt3883_pci_controller *rpc; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct resource *res; + struct device_node *child; + u32 val; + int err; + int mode; + + rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL); + if (!rpc) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -EINVAL; + + rpc->base = devm_ioremap_resource(dev, res); + if (IS_ERR(rpc->base)) + return PTR_ERR(rpc->base); + + /* find the interrupt controller child node */ + for_each_child_of_node(np, child) { + if (of_get_property(child, "interrupt-controller", NULL) && + of_node_get(child)) { + rpc->intc_of_node = child; + break; + } + } + + if (!rpc->intc_of_node) { + dev_err(dev, "%s has no %s child node", + of_node_full_name(rpc->intc_of_node), + "interrupt controller"); + return -EINVAL; + } + + /* find the PCI host bridge child node */ + for_each_child_of_node(np, child) { + if (child->type && + of_node_cmp(child->type, "pci") == 0 && + of_node_get(child)) { + rpc->pci_controller.of_node = child; + break; + } + } + + if (!rpc->pci_controller.of_node) { + dev_err(dev, "%s has no %s child node", + of_node_full_name(rpc->intc_of_node), + "PCI host bridge"); + err = -EINVAL; + goto err_put_intc_node; + } + + mode = RT3883_PCI_MODE_NONE; + for_each_available_child_of_node(rpc->pci_controller.of_node, child) { + int devfn; + + if (!child->type || + of_node_cmp(child->type, "pci") != 0) + continue; + + devfn = of_pci_get_devfn(child); + if (devfn < 0) + continue; + + switch (PCI_SLOT(devfn)) { + case 1: + mode |= RT3883_PCI_MODE_PCIE; + break; + + case 17: + case 18: + mode |= RT3883_PCI_MODE_PCI; + break; + } + } + + if (mode == RT3883_PCI_MODE_NONE) { + dev_err(dev, "unable to determine PCI mode\n"); + err = -EINVAL; + goto err_put_hb_node; + } + + dev_info(dev, "mode:%s%s\n", + (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "", + (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : ""); + + rt3883_pci_preinit(rpc, mode); + + rpc->pci_controller.pci_ops = &rt3883_pci_ops; + rpc->pci_controller.io_resource = &rpc->io_res; + rpc->pci_controller.mem_resource = &rpc->mem_res; + + /* Load PCI I/O and memory resources from DT */ + pci_load_of_ranges(&rpc->pci_controller, + rpc->pci_controller.of_node); + + rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE); + rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE); + + ioport_resource.start = rpc->io_res.start; + ioport_resource.end = rpc->io_res.end; + + /* PCI */ + rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0)); + rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0)); + rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0)); + rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0)); + rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0)); + + /* PCIe */ + rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1)); + rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1)); + rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1)); + rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1)); + rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1)); + + err = rt3883_pci_irq_init(dev, rpc); + if (err) + goto err_put_hb_node; + + /* PCIe */ + val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND); + val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val); + + /* PCI */ + val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND); + val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val); + + if (mode == RT3883_PCI_MODE_PCIE) { + rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0)); + rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1)); + + rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0, + PCI_BASE_ADDRESS_0, + RT3883_MEMORY_BASE); + /* flush write */ + rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0, + PCI_BASE_ADDRESS_0); + } else { + rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0, + PCI_IO_BASE, 0x00000101); + } + + register_pci_controller(&rpc->pci_controller); + + return 0; + +err_put_hb_node: + of_node_put(rpc->pci_controller.of_node); +err_put_intc_node: + of_node_put(rpc->intc_of_node); + return err; +} + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + return of_irq_parse_and_map_pci(dev, slot, pin); +} + +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + +static const struct of_device_id rt3883_pci_ids[] = { + { .compatible = "ralink,rt3883-pci" }, + {}, +}; +MODULE_DEVICE_TABLE(of, rt3883_pci_ids); + +static struct platform_driver rt3883_pci_driver = { + .probe = rt3883_pci_probe, + .driver = { + .name = "rt3883-pci", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(rt3883_pci_ids), + }, +}; + +static int __init rt3883_pci_init(void) +{ + return platform_driver_register(&rt3883_pci_driver); +} + +postcore_initcall(rt3883_pci_init); diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 33e7aa52d9c4..1bf60b127377 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -120,51 +120,37 @@ static void pcibios_scanbus(struct pci_controller *hose) #ifdef CONFIG_OF void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node) { - const __be32 *ranges; - int rlen; - int pna = of_n_addr_cells(node); - int np = pna + 5; + struct of_pci_range range; + struct of_pci_range_parser parser; pr_info("PCI host bridge %s ranges:\n", node->full_name); - ranges = of_get_property(node, "ranges", &rlen); - if (ranges == NULL) - return; hose->of_node = node; - while ((rlen -= np * 4) >= 0) { - u32 pci_space; + if (of_pci_range_parser_init(&parser, node)) + return; + + for_each_of_pci_range(&parser, &range) { struct resource *res = NULL; - u64 addr, size; - - pci_space = be32_to_cpup(&ranges[0]); - addr = of_translate_address(node, ranges + 3); - size = of_read_number(ranges + pna + 3, 2); - ranges += np; - switch ((pci_space >> 24) & 0x3) { - case 1: /* PCI IO space */ + + switch (range.flags & IORESOURCE_TYPE_BITS) { + case IORESOURCE_IO: pr_info(" IO 0x%016llx..0x%016llx\n", - addr, addr + size - 1); + range.cpu_addr, + range.cpu_addr + range.size - 1); hose->io_map_base = - (unsigned long)ioremap(addr, size); + (unsigned long)ioremap(range.cpu_addr, + range.size); res = hose->io_resource; - res->flags = IORESOURCE_IO; break; - case 2: /* PCI Memory space */ - case 3: /* PCI 64 bits Memory space */ + case IORESOURCE_MEM: pr_info(" MEM 0x%016llx..0x%016llx\n", - addr, addr + size - 1); + range.cpu_addr, + range.cpu_addr + range.size - 1); res = hose->mem_resource; - res->flags = IORESOURCE_MEM; break; } - if (res != NULL) { - res->start = addr; - res->name = node->full_name; - res->end = res->start + size - 1; - res->parent = NULL; - res->sibling = NULL; - res->child = NULL; - } + if (res != NULL) + of_pci_range_to_resource(&range, node, res); } } diff --git a/arch/mips/powertv/Kconfig b/arch/mips/powertv/Kconfig deleted file mode 100644 index 1a1b03ea6398..000000000000 --- a/arch/mips/powertv/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -config BOOTLOADER_DRIVER - bool "PowerTV Bootloader Driver Support" - default n - depends on POWERTV - help - Use this option if you want to load bootloader driver. - -config BOOTLOADER_FAMILY - string "POWERTV Bootloader Family string" - default "85" - depends on POWERTV && !BOOTLOADER_DRIVER - help - This value should be specified when the bootloader driver is disabled - and must be exactly two characters long. Families supported are: - R1 - RNG-100 R2 - RNG-200 - A1 - Class A B1 - Class B - E1 - Class E F1 - Class F - 44 - 45xx 46 - 46xx - 85 - 85xx 86 - 86xx diff --git a/arch/mips/powertv/Makefile b/arch/mips/powertv/Makefile deleted file mode 100644 index 39ca9f8d63ae..000000000000 --- a/arch/mips/powertv/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -# -# Carsten Langgaard, carstenl@mips.com -# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. -# -# Carsten Langgaard, carstenl@mips.com -# Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. -# Portions copyright (C) 2009 Cisco Systems, Inc. -# -# This program is free software; you can distribute it and/or modify it -# under the terms of the GNU General Public License (Version 2) as -# published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -# -# Makefile for the Cisco PowerTV-specific kernel interface routines -# under Linux. -# - -obj-y += init.o ioremap.o memory.o powertv_setup.o reset.o time.o \ - asic/ pci/ - -obj-$(CONFIG_USB) += powertv-usb.o diff --git a/arch/mips/powertv/Platform b/arch/mips/powertv/Platform deleted file mode 100644 index 4eb5af1d8eea..000000000000 --- a/arch/mips/powertv/Platform +++ /dev/null @@ -1,7 +0,0 @@ -# -# Cisco PowerTV Platform -# -platform-$(CONFIG_POWERTV) += powertv/ -cflags-$(CONFIG_POWERTV) += \ - -I$(srctree)/arch/mips/include/asm/mach-powertv -load-$(CONFIG_POWERTV) += 0xffffffff90800000 diff --git a/arch/mips/powertv/asic/Makefile b/arch/mips/powertv/asic/Makefile deleted file mode 100644 index 35dcc53eb25f..000000000000 --- a/arch/mips/powertv/asic/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (C) 2009 Scientific-Atlanta, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -# - -obj-y += asic-calliope.o asic-cronus.o asic-gaia.o asic-zeus.o \ - asic_devices.o asic_int.o irq_asic.o prealloc-calliope.o \ - prealloc-cronus.o prealloc-cronuslite.o prealloc-gaia.o prealloc-zeus.o diff --git a/arch/mips/powertv/asic/asic-calliope.c b/arch/mips/powertv/asic/asic-calliope.c deleted file mode 100644 index 2f539b43f56b..000000000000 --- a/arch/mips/powertv/asic/asic-calliope.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Locations of devices in the Calliope ASIC. - * - * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: Ken Eppinett - * David Schleef <ds@schleef.org> - * - * Description: Defines the platform resources for the SA settop. - */ - -#include <linux/init.h> -#include <asm/mach-powertv/asic.h> - -#define CALLIOPE_ADDR(x) (CALLIOPE_IO_BASE + (x)) - -const struct register_map calliope_register_map __initconst = { - .eic_slow0_strt_add = {.phys = CALLIOPE_ADDR(0x800000)}, - .eic_cfg_bits = {.phys = CALLIOPE_ADDR(0x800038)}, - .eic_ready_status = {.phys = CALLIOPE_ADDR(0x80004c)}, - - .chipver3 = {.phys = CALLIOPE_ADDR(0xA00800)}, - .chipver2 = {.phys = CALLIOPE_ADDR(0xA00804)}, - .chipver1 = {.phys = CALLIOPE_ADDR(0xA00808)}, - .chipver0 = {.phys = CALLIOPE_ADDR(0xA0080c)}, - - /* The registers of IRBlaster */ - .uart1_intstat = {.phys = CALLIOPE_ADDR(0xA01800)}, - .uart1_inten = {.phys = CALLIOPE_ADDR(0xA01804)}, - .uart1_config1 = {.phys = CALLIOPE_ADDR(0xA01808)}, - .uart1_config2 = {.phys = CALLIOPE_ADDR(0xA0180C)}, - .uart1_divisorhi = {.phys = CALLIOPE_ADDR(0xA01810)}, - .uart1_divisorlo = {.phys = CALLIOPE_ADDR(0xA01814)}, - .uart1_data = {.phys = CALLIOPE_ADDR(0xA01818)}, - .uart1_status = {.phys = CALLIOPE_ADDR(0xA0181C)}, - - .int_stat_3 = {.phys = CALLIOPE_ADDR(0xA02800)}, - .int_stat_2 = {.phys = CALLIOPE_ADDR(0xA02804)}, - .int_stat_1 = {.phys = CALLIOPE_ADDR(0xA02808)}, - .int_stat_0 = {.phys = CALLIOPE_ADDR(0xA0280c)}, - .int_config = {.phys = CALLIOPE_ADDR(0xA02810)}, - .int_int_scan = {.phys = CALLIOPE_ADDR(0xA02818)}, - .ien_int_3 = {.phys = CALLIOPE_ADDR(0xA02830)}, - .ien_int_2 = {.phys = CALLIOPE_ADDR(0xA02834)}, - .ien_int_1 = {.phys = CALLIOPE_ADDR(0xA02838)}, - .ien_int_0 = {.phys = CALLIOPE_ADDR(0xA0283c)}, - .int_level_3_3 = {.phys = CALLIOPE_ADDR(0xA02880)}, - .int_level_3_2 = {.phys = CALLIOPE_ADDR(0xA02884)}, - .int_level_3_1 = {.phys = CALLIOPE_ADDR(0xA02888)}, - .int_level_3_0 = {.phys = CALLIOPE_ADDR(0xA0288c)}, - .int_level_2_3 = {.phys = CALLIOPE_ADDR(0xA02890)}, - .int_level_2_2 = {.phys = CALLIOPE_ADDR(0xA02894)}, - .int_level_2_1 = {.phys = CALLIOPE_ADDR(0xA02898)}, - .int_level_2_0 = {.phys = CALLIOPE_ADDR(0xA0289c)}, - .int_level_1_3 = {.phys = CALLIOPE_ADDR(0xA028a0)}, - .int_level_1_2 = {.phys = CALLIOPE_ADDR(0xA028a4)}, - .int_level_1_1 = {.phys = CALLIOPE_ADDR(0xA028a8)}, - .int_level_1_0 = {.phys = CALLIOPE_ADDR(0xA028ac)}, - .int_level_0_3 = {.phys = CALLIOPE_ADDR(0xA028b0)}, - .int_level_0_2 = {.phys = CALLIOPE_ADDR(0xA028b4)}, - .int_level_0_1 = {.phys = CALLIOPE_ADDR(0xA028b8)}, - .int_level_0_0 = {.phys = CALLIOPE_ADDR(0xA028bc)}, - .int_docsis_en = {.phys = CALLIOPE_ADDR(0xA028F4)}, - - .mips_pll_setup = {.phys = CALLIOPE_ADDR(0x980000)}, - .fs432x4b4_usb_ctl = {.phys = CALLIOPE_ADDR(0x980030)}, - .test_bus = {.phys = CALLIOPE_ADDR(0x9800CC)}, - .crt_spare = {.phys = CALLIOPE_ADDR(0x9800d4)}, - .usb2_ohci_int_mask = {.phys = CALLIOPE_ADDR(0x9A000c)}, - .usb2_strap = {.phys = CALLIOPE_ADDR(0x9A0014)}, - .ehci_hcapbase = {.phys = CALLIOPE_ADDR(0x9BFE00)}, - .ohci_hc_revision = {.phys = CALLIOPE_ADDR(0x9BFC00)}, - .bcm1_bs_lmi_steer = {.phys = CALLIOPE_ADDR(0x9E0004)}, - .usb2_control = {.phys = CALLIOPE_ADDR(0x9E0054)}, - .usb2_stbus_obc = {.phys = CALLIOPE_ADDR(0x9BFF00)}, - .usb2_stbus_mess_size = {.phys = CALLIOPE_ADDR(0x9BFF04)}, - .usb2_stbus_chunk_size = {.phys = CALLIOPE_ADDR(0x9BFF08)}, - - .pcie_regs = {.phys = 0x000000}, /* -doesn't exist- */ - .tim_ch = {.phys = CALLIOPE_ADDR(0xA02C10)}, - .tim_cl = {.phys = CALLIOPE_ADDR(0xA02C14)}, - .gpio_dout = {.phys = CALLIOPE_ADDR(0xA02c20)}, - .gpio_din = {.phys = CALLIOPE_ADDR(0xA02c24)}, - .gpio_dir = {.phys = CALLIOPE_ADDR(0xA02c2C)}, - .watchdog = {.phys = CALLIOPE_ADDR(0xA02c30)}, - .front_panel = {.phys = 0x000000}, /* -not used- */ -}; diff --git a/arch/mips/powertv/asic/asic-cronus.c b/arch/mips/powertv/asic/asic-cronus.c deleted file mode 100644 index 7f8f3429b35a..000000000000 --- a/arch/mips/powertv/asic/asic-cronus.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Locations of devices in the Cronus ASIC - * - * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: Ken Eppinett - * David Schleef <ds@schleef.org> - * - * Description: Defines the platform resources for the SA settop. - */ - -#include <linux/init.h> -#include <asm/mach-powertv/asic.h> - -#define CRONUS_ADDR(x) (CRONUS_IO_BASE + (x)) - -const struct register_map cronus_register_map __initconst = { - .eic_slow0_strt_add = {.phys = CRONUS_ADDR(0x000000)}, - .eic_cfg_bits = {.phys = CRONUS_ADDR(0x000038)}, - .eic_ready_status = {.phys = CRONUS_ADDR(0x00004C)}, - - .chipver3 = {.phys = CRONUS_ADDR(0x2A0800)}, - .chipver2 = {.phys = CRONUS_ADDR(0x2A0804)}, - .chipver1 = {.phys = CRONUS_ADDR(0x2A0808)}, - .chipver0 = {.phys = CRONUS_ADDR(0x2A080C)}, - - /* The registers of IRBlaster */ - .uart1_intstat = {.phys = CRONUS_ADDR(0x2A1800)}, - .uart1_inten = {.phys = CRONUS_ADDR(0x2A1804)}, - .uart1_config1 = {.phys = CRONUS_ADDR(0x2A1808)}, - .uart1_config2 = {.phys = CRONUS_ADDR(0x2A180C)}, - .uart1_divisorhi = {.phys = CRONUS_ADDR(0x2A1810)}, - .uart1_divisorlo = {.phys = CRONUS_ADDR(0x2A1814)}, - .uart1_data = {.phys = CRONUS_ADDR(0x2A1818)}, - .uart1_status = {.phys = CRONUS_ADDR(0x2A181C)}, - - .int_stat_3 = {.phys = CRONUS_ADDR(0x2A2800)}, - .int_stat_2 = {.phys = CRONUS_ADDR(0x2A2804)}, - .int_stat_1 = {.phys = CRONUS_ADDR(0x2A2808)}, - .int_stat_0 = {.phys = CRONUS_ADDR(0x2A280C)}, - .int_config = {.phys = CRONUS_ADDR(0x2A2810)}, - .int_int_scan = {.phys = CRONUS_ADDR(0x2A2818)}, - .ien_int_3 = {.phys = CRONUS_ADDR(0x2A2830)}, - .ien_int_2 = {.phys = CRONUS_ADDR(0x2A2834)}, - .ien_int_1 = {.phys = CRONUS_ADDR(0x2A2838)}, - .ien_int_0 = {.phys = CRONUS_ADDR(0x2A283C)}, - .int_level_3_3 = {.phys = CRONUS_ADDR(0x2A2880)}, - .int_level_3_2 = {.phys = CRONUS_ADDR(0x2A2884)}, - .int_level_3_1 = {.phys = CRONUS_ADDR(0x2A2888)}, - .int_level_3_0 = {.phys = CRONUS_ADDR(0x2A288C)}, - .int_level_2_3 = {.phys = CRONUS_ADDR(0x2A2890)}, - .int_level_2_2 = {.phys = CRONUS_ADDR(0x2A2894)}, - .int_level_2_1 = {.phys = CRONUS_ADDR(0x2A2898)}, - .int_level_2_0 = {.phys = CRONUS_ADDR(0x2A289C)}, - .int_level_1_3 = {.phys = CRONUS_ADDR(0x2A28A0)}, - .int_level_1_2 = {.phys = CRONUS_ADDR(0x2A28A4)}, - .int_level_1_1 = {.phys = CRONUS_ADDR(0x2A28A8)}, - .int_level_1_0 = {.phys = CRONUS_ADDR(0x2A28AC)}, - .int_level_0_3 = {.phys = CRONUS_ADDR(0x2A28B0)}, - .int_level_0_2 = {.phys = CRONUS_ADDR(0x2A28B4)}, - .int_level_0_1 = {.phys = CRONUS_ADDR(0x2A28B8)}, - .int_level_0_0 = {.phys = CRONUS_ADDR(0x2A28BC)}, - .int_docsis_en = {.phys = CRONUS_ADDR(0x2A28F4)}, - - .mips_pll_setup = {.phys = CRONUS_ADDR(0x1C0000)}, - .fs432x4b4_usb_ctl = {.phys = CRONUS_ADDR(0x1C0028)}, - .test_bus = {.phys = CRONUS_ADDR(0x1C00CC)}, - .crt_spare = {.phys = CRONUS_ADDR(0x1c00d4)}, - .usb2_ohci_int_mask = {.phys = CRONUS_ADDR(0x20000C)}, - .usb2_strap = {.phys = CRONUS_ADDR(0x200014)}, - .ehci_hcapbase = {.phys = CRONUS_ADDR(0x21FE00)}, - .ohci_hc_revision = {.phys = CRONUS_ADDR(0x21fc00)}, - .bcm1_bs_lmi_steer = {.phys = CRONUS_ADDR(0x2E0008)}, - .usb2_control = {.phys = CRONUS_ADDR(0x2E004C)}, - .usb2_stbus_obc = {.phys = CRONUS_ADDR(0x21FF00)}, - .usb2_stbus_mess_size = {.phys = CRONUS_ADDR(0x21FF04)}, - .usb2_stbus_chunk_size = {.phys = CRONUS_ADDR(0x21FF08)}, - - .pcie_regs = {.phys = CRONUS_ADDR(0x220000)}, - .tim_ch = {.phys = CRONUS_ADDR(0x2A2C10)}, - .tim_cl = {.phys = CRONUS_ADDR(0x2A2C14)}, - .gpio_dout = {.phys = CRONUS_ADDR(0x2A2C20)}, - .gpio_din = {.phys = CRONUS_ADDR(0x2A2C24)}, - .gpio_dir = {.phys = CRONUS_ADDR(0x2A2C2C)}, - .watchdog = {.phys = CRONUS_ADDR(0x2A2C30)}, - .front_panel = {.phys = CRONUS_ADDR(0x2A3800)}, -}; diff --git a/arch/mips/powertv/asic/asic-gaia.c b/arch/mips/powertv/asic/asic-gaia.c deleted file mode 100644 index 1265b49012e6..000000000000 --- a/arch/mips/powertv/asic/asic-gaia.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Locations of devices in the Gaia ASIC - * - * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: David VomLehn - */ - -#include <linux/init.h> -#include <asm/mach-powertv/asic.h> - -const struct register_map gaia_register_map __initconst = { - .eic_slow0_strt_add = {.phys = GAIA_IO_BASE + 0x000000}, - .eic_cfg_bits = {.phys = GAIA_IO_BASE + 0x000038}, - .eic_ready_status = {.phys = GAIA_IO_BASE + 0x00004C}, - - .chipver3 = {.phys = GAIA_IO_BASE + 0x2A0800}, - .chipver2 = {.phys = GAIA_IO_BASE + 0x2A0804}, - .chipver1 = {.phys = GAIA_IO_BASE + 0x2A0808}, - .chipver0 = {.phys = GAIA_IO_BASE + 0x2A080C}, - - /* The registers of IRBlaster */ - .uart1_intstat = {.phys = GAIA_IO_BASE + 0x2A1800}, - .uart1_inten = {.phys = GAIA_IO_BASE + 0x2A1804}, - .uart1_config1 = {.phys = GAIA_IO_BASE + 0x2A1808}, - .uart1_config2 = {.phys = GAIA_IO_BASE + 0x2A180C}, - .uart1_divisorhi = {.phys = GAIA_IO_BASE + 0x2A1810}, - .uart1_divisorlo = {.phys = GAIA_IO_BASE + 0x2A1814}, - .uart1_data = {.phys = GAIA_IO_BASE + 0x2A1818}, - .uart1_status = {.phys = GAIA_IO_BASE + 0x2A181C}, - - .int_stat_3 = {.phys = GAIA_IO_BASE + 0x2A2800}, - .int_stat_2 = {.phys = GAIA_IO_BASE + 0x2A2804}, - .int_stat_1 = {.phys = GAIA_IO_BASE + 0x2A2808}, - .int_stat_0 = {.phys = GAIA_IO_BASE + 0x2A280C}, - .int_config = {.phys = GAIA_IO_BASE + 0x2A2810}, - .int_int_scan = {.phys = GAIA_IO_BASE + 0x2A2818}, - .ien_int_3 = {.phys = GAIA_IO_BASE + 0x2A2830}, - .ien_int_2 = {.phys = GAIA_IO_BASE + 0x2A2834}, - .ien_int_1 = {.phys = GAIA_IO_BASE + 0x2A2838}, - .ien_int_0 = {.phys = GAIA_IO_BASE + 0x2A283C}, - .int_level_3_3 = {.phys = GAIA_IO_BASE + 0x2A2880}, - .int_level_3_2 = {.phys = GAIA_IO_BASE + 0x2A2884}, - .int_level_3_1 = {.phys = GAIA_IO_BASE + 0x2A2888}, - .int_level_3_0 = {.phys = GAIA_IO_BASE + 0x2A288C}, - .int_level_2_3 = {.phys = GAIA_IO_BASE + 0x2A2890}, - .int_level_2_2 = {.phys = GAIA_IO_BASE + 0x2A2894}, - .int_level_2_1 = {.phys = GAIA_IO_BASE + 0x2A2898}, - .int_level_2_0 = {.phys = GAIA_IO_BASE + 0x2A289C}, - .int_level_1_3 = {.phys = GAIA_IO_BASE + 0x2A28A0}, - .int_level_1_2 = {.phys = GAIA_IO_BASE + 0x2A28A4}, - .int_level_1_1 = {.phys = GAIA_IO_BASE + 0x2A28A8}, - .int_level_1_0 = {.phys = GAIA_IO_BASE + 0x2A28AC}, - .int_level_0_3 = {.phys = GAIA_IO_BASE + 0x2A28B0}, - .int_level_0_2 = {.phys = GAIA_IO_BASE + 0x2A28B4}, - .int_level_0_1 = {.phys = GAIA_IO_BASE + 0x2A28B8}, - .int_level_0_0 = {.phys = GAIA_IO_BASE + 0x2A28BC}, - .int_docsis_en = {.phys = GAIA_IO_BASE + 0x2A28F4}, - - .mips_pll_setup = {.phys = GAIA_IO_BASE + 0x1C0000}, - .fs432x4b4_usb_ctl = {.phys = GAIA_IO_BASE + 0x1C0024}, - .test_bus = {.phys = GAIA_IO_BASE + 0x1C00CC}, - .crt_spare = {.phys = GAIA_IO_BASE + 0x1c0108}, - .usb2_ohci_int_mask = {.phys = GAIA_IO_BASE + 0x20000C}, - .usb2_strap = {.phys = GAIA_IO_BASE + 0x200014}, - .ehci_hcapbase = {.phys = GAIA_IO_BASE + 0x21FE00}, - .ohci_hc_revision = {.phys = GAIA_IO_BASE + 0x21fc00}, - .bcm1_bs_lmi_steer = {.phys = GAIA_IO_BASE + 0x2E0004}, - .usb2_control = {.phys = GAIA_IO_BASE + 0x2E004C}, - .usb2_stbus_obc = {.phys = GAIA_IO_BASE + 0x21FF00}, - .usb2_stbus_mess_size = {.phys = GAIA_IO_BASE + 0x21FF04}, - .usb2_stbus_chunk_size = {.phys = GAIA_IO_BASE + 0x21FF08}, - - .pcie_regs = {.phys = GAIA_IO_BASE + 0x220000}, - .tim_ch = {.phys = GAIA_IO_BASE + 0x2A2C10}, - .tim_cl = {.phys = GAIA_IO_BASE + 0x2A2C14}, - .gpio_dout = {.phys = GAIA_IO_BASE + 0x2A2C20}, - .gpio_din = {.phys = GAIA_IO_BASE + 0x2A2C24}, - .gpio_dir = {.phys = GAIA_IO_BASE + 0x2A2C2C}, - .watchdog = {.phys = GAIA_IO_BASE + 0x2A2C30}, - .front_panel = {.phys = GAIA_IO_BASE + 0x2A3800}, -}; diff --git a/arch/mips/powertv/asic/asic-zeus.c b/arch/mips/powertv/asic/asic-zeus.c deleted file mode 100644 index 14e7de137e03..000000000000 --- a/arch/mips/powertv/asic/asic-zeus.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Locations of devices in the Zeus ASIC - * - * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: Ken Eppinett - * David Schleef <ds@schleef.org> - * - * Description: Defines the platform resources for the SA settop. - */ - -#include <linux/init.h> -#include <asm/mach-powertv/asic.h> - -#define ZEUS_ADDR(x) (ZEUS_IO_BASE + (x)) - -const struct register_map zeus_register_map __initconst = { - .eic_slow0_strt_add = {.phys = ZEUS_ADDR(0x000000)}, - .eic_cfg_bits = {.phys = ZEUS_ADDR(0x000038)}, - .eic_ready_status = {.phys = ZEUS_ADDR(0x00004c)}, - - .chipver3 = {.phys = ZEUS_ADDR(0x280800)}, - .chipver2 = {.phys = ZEUS_ADDR(0x280804)}, - .chipver1 = {.phys = ZEUS_ADDR(0x280808)}, - .chipver0 = {.phys = ZEUS_ADDR(0x28080c)}, - - /* The registers of IRBlaster */ - .uart1_intstat = {.phys = ZEUS_ADDR(0x281800)}, - .uart1_inten = {.phys = ZEUS_ADDR(0x281804)}, - .uart1_config1 = {.phys = ZEUS_ADDR(0x281808)}, - .uart1_config2 = {.phys = ZEUS_ADDR(0x28180C)}, - .uart1_divisorhi = {.phys = ZEUS_ADDR(0x281810)}, - .uart1_divisorlo = {.phys = ZEUS_ADDR(0x281814)}, - .uart1_data = {.phys = ZEUS_ADDR(0x281818)}, - .uart1_status = {.phys = ZEUS_ADDR(0x28181C)}, - - .int_stat_3 = {.phys = ZEUS_ADDR(0x282800)}, - .int_stat_2 = {.phys = ZEUS_ADDR(0x282804)}, - .int_stat_1 = {.phys = ZEUS_ADDR(0x282808)}, - .int_stat_0 = {.phys = ZEUS_ADDR(0x28280c)}, - .int_config = {.phys = ZEUS_ADDR(0x282810)}, - .int_int_scan = {.phys = ZEUS_ADDR(0x282818)}, - .ien_int_3 = {.phys = ZEUS_ADDR(0x282830)}, - .ien_int_2 = {.phys = ZEUS_ADDR(0x282834)}, - .ien_int_1 = {.phys = ZEUS_ADDR(0x282838)}, - .ien_int_0 = {.phys = ZEUS_ADDR(0x28283c)}, - .int_level_3_3 = {.phys = ZEUS_ADDR(0x282880)}, - .int_level_3_2 = {.phys = ZEUS_ADDR(0x282884)}, - .int_level_3_1 = {.phys = ZEUS_ADDR(0x282888)}, - .int_level_3_0 = {.phys = ZEUS_ADDR(0x28288c)}, - .int_level_2_3 = {.phys = ZEUS_ADDR(0x282890)}, - .int_level_2_2 = {.phys = ZEUS_ADDR(0x282894)}, - .int_level_2_1 = {.phys = ZEUS_ADDR(0x282898)}, - .int_level_2_0 = {.phys = ZEUS_ADDR(0x28289c)}, - .int_level_1_3 = {.phys = ZEUS_ADDR(0x2828a0)}, - .int_level_1_2 = {.phys = ZEUS_ADDR(0x2828a4)}, - .int_level_1_1 = {.phys = ZEUS_ADDR(0x2828a8)}, - .int_level_1_0 = {.phys = ZEUS_ADDR(0x2828ac)}, - .int_level_0_3 = {.phys = ZEUS_ADDR(0x2828b0)}, - .int_level_0_2 = {.phys = ZEUS_ADDR(0x2828b4)}, - .int_level_0_1 = {.phys = ZEUS_ADDR(0x2828b8)}, - .int_level_0_0 = {.phys = ZEUS_ADDR(0x2828bc)}, - .int_docsis_en = {.phys = ZEUS_ADDR(0x2828F4)}, - - .mips_pll_setup = {.phys = ZEUS_ADDR(0x1a0000)}, - .fs432x4b4_usb_ctl = {.phys = ZEUS_ADDR(0x1a0018)}, - .test_bus = {.phys = ZEUS_ADDR(0x1a0238)}, - .crt_spare = {.phys = ZEUS_ADDR(0x1a0090)}, - .usb2_ohci_int_mask = {.phys = ZEUS_ADDR(0x1e000c)}, - .usb2_strap = {.phys = ZEUS_ADDR(0x1e0014)}, - .ehci_hcapbase = {.phys = ZEUS_ADDR(0x1FFE00)}, - .ohci_hc_revision = {.phys = ZEUS_ADDR(0x1FFC00)}, - .bcm1_bs_lmi_steer = {.phys = ZEUS_ADDR(0x2C0008)}, - .usb2_control = {.phys = ZEUS_ADDR(0x2c01a0)}, - .usb2_stbus_obc = {.phys = ZEUS_ADDR(0x1FFF00)}, - .usb2_stbus_mess_size = {.phys = ZEUS_ADDR(0x1FFF04)}, - .usb2_stbus_chunk_size = {.phys = ZEUS_ADDR(0x1FFF08)}, - - .pcie_regs = {.phys = ZEUS_ADDR(0x200000)}, - .tim_ch = {.phys = ZEUS_ADDR(0x282C10)}, - .tim_cl = {.phys = ZEUS_ADDR(0x282C14)}, - .gpio_dout = {.phys = ZEUS_ADDR(0x282c20)}, - .gpio_din = {.phys = ZEUS_ADDR(0x282c24)}, - .gpio_dir = {.phys = ZEUS_ADDR(0x282c2C)}, - .watchdog = {.phys = ZEUS_ADDR(0x282c30)}, - .front_panel = {.phys = ZEUS_ADDR(0x283800)}, -}; diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c deleted file mode 100644 index 0238af1ba503..000000000000 --- a/arch/mips/powertv/asic/asic_devices.c +++ /dev/null @@ -1,559 +0,0 @@ -/* - * - * Description: Defines the platform resources for Gaia-based settops. - * - * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * NOTE: The bootloader allocates persistent memory at an address which is - * 16 MiB below the end of the highest address in KSEG0. All fixed - * address memory reservations must avoid this region. - */ - -#include <linux/device.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/resource.h> -#include <linux/serial_reg.h> -#include <linux/io.h> -#include <linux/bootmem.h> -#include <linux/mm.h> -#include <linux/platform_device.h> -#include <linux/module.h> -#include <asm/page.h> -#include <linux/swap.h> -#include <linux/highmem.h> -#include <linux/dma-mapping.h> - -#include <asm/mach-powertv/asic.h> -#include <asm/mach-powertv/asic_regs.h> -#include <asm/mach-powertv/interrupts.h> - -#ifdef CONFIG_BOOTLOADER_DRIVER -#include <asm/mach-powertv/kbldr.h> -#endif -#include <asm/bootinfo.h> - -#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0)) - -/* - * Forward Prototypes - */ -static void pmem_setup_resource(void); - -/* - * Global Variables - */ -enum asic_type asic; - -unsigned int platform_features; -unsigned int platform_family; -struct register_map _asic_register_map; -EXPORT_SYMBOL(_asic_register_map); /* Exported for testing */ -unsigned long asic_phy_base; -unsigned long asic_base; -EXPORT_SYMBOL(asic_base); /* Exported for testing */ -struct resource *gp_resources; - -/* - * Don't recommend to use it directly, it is usually used by kernel internally. - * Portable code should be using interfaces such as ioremp, dma_map_single, etc. - */ -unsigned long phys_to_dma_offset; -EXPORT_SYMBOL(phys_to_dma_offset); - -/* - * - * IO Resource Definition - * - */ - -struct resource asic_resource = { - .name = "ASIC Resource", - .start = 0, - .end = ASIC_IO_SIZE, - .flags = IORESOURCE_MEM, -}; - -/* - * Allow override of bootloader-specified model - * Returns zero on success, a negative errno value on failure. This parameter - * allows overriding of the bootloader-specified model. - */ -static char __initdata cmdline[COMMAND_LINE_SIZE]; - -#define FORCEFAMILY_PARAM "forcefamily" - -/* - * check_forcefamily - check for, and parse, forcefamily command line parameter - * @forced_family: Pointer to two-character array in which to store the - * value of the forcedfamily parameter, if any. - */ -static __init int check_forcefamily(unsigned char forced_family[2]) -{ - const char *p; - - forced_family[0] = '\0'; - forced_family[1] = '\0'; - - /* Check the command line for a forcefamily directive */ - strncpy(cmdline, arcs_cmdline, COMMAND_LINE_SIZE - 1); - p = strstr(cmdline, FORCEFAMILY_PARAM); - if (p && (p != cmdline) && (*(p - 1) != ' ')) - p = strstr(p, " " FORCEFAMILY_PARAM "="); - - if (p) { - p += strlen(FORCEFAMILY_PARAM "="); - - if (*p == '\0' || *(p + 1) == '\0' || - (*(p + 2) != '\0' && *(p + 2) != ' ')) - pr_err(FORCEFAMILY_PARAM " must be exactly two " - "characters long, ignoring value\n"); - - else { - forced_family[0] = *p; - forced_family[1] = *(p + 1); - } - } - - return 0; -} - -/* - * platform_set_family - determine major platform family type. - * - * Returns family type; -1 if none - * Returns the family type; -1 if none - * - */ -static __init noinline void platform_set_family(void) -{ - unsigned char forced_family[2]; - unsigned short bootldr_family; - - if (check_forcefamily(forced_family) == 0) - bootldr_family = BOOTLDRFAMILY(forced_family[0], - forced_family[1]); - else { - -#ifdef CONFIG_BOOTLOADER_DRIVER - bootldr_family = (unsigned short) kbldr_GetSWFamily(); -#else -#if defined(CONFIG_BOOTLOADER_FAMILY) - bootldr_family = (unsigned short) BOOTLDRFAMILY( - CONFIG_BOOTLOADER_FAMILY[0], - CONFIG_BOOTLOADER_FAMILY[1]); -#else -#error "Unknown Bootloader Family" -#endif -#endif - } - - pr_info("Bootloader Family = 0x%04X\n", bootldr_family); - - switch (bootldr_family) { - case BOOTLDRFAMILY('R', '1'): - platform_family = FAMILY_1500; - break; - case BOOTLDRFAMILY('4', '4'): - platform_family = FAMILY_4500; - break; - case BOOTLDRFAMILY('4', '6'): - platform_family = FAMILY_4600; - break; - case BOOTLDRFAMILY('A', '1'): - platform_family = FAMILY_4600VZA; - break; - case BOOTLDRFAMILY('8', '5'): - platform_family = FAMILY_8500; - break; - case BOOTLDRFAMILY('R', '2'): - platform_family = FAMILY_8500RNG; - break; - case BOOTLDRFAMILY('8', '6'): - platform_family = FAMILY_8600; - break; - case BOOTLDRFAMILY('B', '1'): - platform_family = FAMILY_8600VZB; - break; - case BOOTLDRFAMILY('E', '1'): - platform_family = FAMILY_1500VZE; - break; - case BOOTLDRFAMILY('F', '1'): - platform_family = FAMILY_1500VZF; - break; - case BOOTLDRFAMILY('8', '7'): - platform_family = FAMILY_8700; - break; - default: - platform_family = -1; - } -} - -unsigned int platform_get_family(void) -{ - return platform_family; -} -EXPORT_SYMBOL(platform_get_family); - -/* - * platform_get_asic - determine the ASIC type. - * - * Returns the ASIC type, or ASIC_UNKNOWN if unknown - * - */ -enum asic_type platform_get_asic(void) -{ - return asic; -} -EXPORT_SYMBOL(platform_get_asic); - -/* - * set_register_map - set ASIC register configuration - * @phys_base: Physical address of the base of the ASIC registers - * @map: Description of key ASIC registers - */ -static void __init set_register_map(unsigned long phys_base, - const struct register_map *map) -{ - asic_phy_base = phys_base; - _asic_register_map = *map; - register_map_virtualize(&_asic_register_map); - asic_base = (unsigned long)ioremap_nocache(phys_base, ASIC_IO_SIZE); -} - -/** - * configure_platform - configuration based on platform type. - */ -void __init configure_platform(void) -{ - platform_set_family(); - - switch (platform_family) { - case FAMILY_1500: - case FAMILY_1500VZE: - case FAMILY_1500VZF: - platform_features = FFS_CAPABLE; - asic = ASIC_CALLIOPE; - set_register_map(CALLIOPE_IO_BASE, &calliope_register_map); - - if (platform_family == FAMILY_1500VZE) { - gp_resources = non_dvr_vze_calliope_resources; - pr_info("Platform: 1500/Vz Class E - " - "CALLIOPE, NON_DVR_CAPABLE\n"); - } else if (platform_family == FAMILY_1500VZF) { - gp_resources = non_dvr_vzf_calliope_resources; - pr_info("Platform: 1500/Vz Class F - " - "CALLIOPE, NON_DVR_CAPABLE\n"); - } else { - gp_resources = non_dvr_calliope_resources; - pr_info("Platform: 1500/RNG100 - CALLIOPE, " - "NON_DVR_CAPABLE\n"); - } - break; - - case FAMILY_4500: - platform_features = FFS_CAPABLE | PCIE_CAPABLE | - DISPLAY_CAPABLE; - asic = ASIC_ZEUS; - set_register_map(ZEUS_IO_BASE, &zeus_register_map); - gp_resources = non_dvr_zeus_resources; - - pr_info("Platform: 4500 - ZEUS, NON_DVR_CAPABLE\n"); - break; - - case FAMILY_4600: - { - unsigned int chipversion = 0; - - /* The settop has PCIE but it isn't used, so don't advertise - * it*/ - platform_features = FFS_CAPABLE | DISPLAY_CAPABLE; - - /* Cronus and Cronus Lite have the same register map */ - set_register_map(CRONUS_IO_BASE, &cronus_register_map); - - /* ASIC version will determine if this is a real CronusLite or - * Castrati(Cronus) */ - chipversion = asic_read(chipver3) << 24; - chipversion |= asic_read(chipver2) << 16; - chipversion |= asic_read(chipver1) << 8; - chipversion |= asic_read(chipver0); - - if ((chipversion == CRONUS_10) || (chipversion == CRONUS_11)) - asic = ASIC_CRONUS; - else - asic = ASIC_CRONUSLITE; - - gp_resources = non_dvr_cronuslite_resources; - pr_info("Platform: 4600 - %s, NON_DVR_CAPABLE, " - "chipversion=0x%08X\n", - (asic == ASIC_CRONUS) ? "CRONUS" : "CRONUS LITE", - chipversion); - break; - } - case FAMILY_4600VZA: - platform_features = FFS_CAPABLE | DISPLAY_CAPABLE; - asic = ASIC_CRONUS; - set_register_map(CRONUS_IO_BASE, &cronus_register_map); - gp_resources = non_dvr_cronus_resources; - - pr_info("Platform: Vz Class A - CRONUS, NON_DVR_CAPABLE\n"); - break; - - case FAMILY_8500: - case FAMILY_8500RNG: - platform_features = DVR_CAPABLE | PCIE_CAPABLE | - DISPLAY_CAPABLE; - asic = ASIC_ZEUS; - set_register_map(ZEUS_IO_BASE, &zeus_register_map); - gp_resources = dvr_zeus_resources; - - pr_info("Platform: 8500/RNG200 - ZEUS, DVR_CAPABLE\n"); - break; - - case FAMILY_8600: - case FAMILY_8600VZB: - platform_features = DVR_CAPABLE | PCIE_CAPABLE | - DISPLAY_CAPABLE; - asic = ASIC_CRONUS; - set_register_map(CRONUS_IO_BASE, &cronus_register_map); - gp_resources = dvr_cronus_resources; - - pr_info("Platform: 8600/Vz Class B - CRONUS, " - "DVR_CAPABLE\n"); - break; - - case FAMILY_8700: - platform_features = FFS_CAPABLE | PCIE_CAPABLE; - asic = ASIC_GAIA; - set_register_map(GAIA_IO_BASE, &gaia_register_map); - gp_resources = dvr_gaia_resources; - - pr_info("Platform: 8700 - GAIA, DVR_CAPABLE\n"); - break; - - default: - pr_crit("Platform: UNKNOWN PLATFORM\n"); - break; - } - - switch (asic) { - case ASIC_ZEUS: - phys_to_dma_offset = 0x30000000; - break; - case ASIC_CALLIOPE: - phys_to_dma_offset = 0x10000000; - break; - case ASIC_CRONUSLITE: - /* Fall through */ - case ASIC_CRONUS: - /* - * TODO: We suppose 0x10000000 aliases into 0x20000000- - * 0x2XXXXXXX. If 0x10000000 aliases into 0x60000000- - * 0x6XXXXXXX, the offset should be 0x50000000, not 0x10000000. - */ - phys_to_dma_offset = 0x10000000; - break; - default: - phys_to_dma_offset = 0x00000000; - break; - } -} - -/* - * RESOURCE ALLOCATION - * - */ -/* - * Allocates/reserves the Platform memory resources early in the boot process. - * This ignores any resources that are designated IORESOURCE_IO - */ -void __init platform_alloc_bootmem(void) -{ - int i; - int total = 0; - - /* Get persistent memory data from command line before allocating - * resources. This need to happen before normal command line parsing - * has been done */ - pmem_setup_resource(); - - /* Loop through looking for resources that want a particular address */ - for (i = 0; gp_resources[i].flags != 0; i++) { - int size = resource_size(&gp_resources[i]); - if ((gp_resources[i].start != 0) && - ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) { - reserve_bootmem(dma_to_phys(gp_resources[i].start), - size, 0); - total += resource_size(&gp_resources[i]); - pr_info("reserve resource %s at %08x (%u bytes)\n", - gp_resources[i].name, gp_resources[i].start, - resource_size(&gp_resources[i])); - } - } - - /* Loop through assigning addresses for those that are left */ - for (i = 0; gp_resources[i].flags != 0; i++) { - int size = resource_size(&gp_resources[i]); - if ((gp_resources[i].start == 0) && - ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) { - void *mem = alloc_bootmem_pages(size); - - if (mem == NULL) - pr_err("Unable to allocate bootmem pages " - "for %s\n", gp_resources[i].name); - - else { - gp_resources[i].start = - phys_to_dma(virt_to_phys(mem)); - gp_resources[i].end = - gp_resources[i].start + size - 1; - total += size; - pr_info("allocate resource %s at %08x " - "(%u bytes)\n", - gp_resources[i].name, - gp_resources[i].start, size); - } - } - } - - pr_info("Total Platform driver memory allocation: 0x%08x\n", total); - - /* indicate resources that are platform I/O related */ - for (i = 0; gp_resources[i].flags != 0; i++) { - if ((gp_resources[i].start != 0) && - ((gp_resources[i].flags & IORESOURCE_IO) != 0)) { - pr_info("reserved platform resource %s at %08x\n", - gp_resources[i].name, gp_resources[i].start); - } - } -} - -/* - * - * PERSISTENT MEMORY (PMEM) CONFIGURATION - * - */ -static unsigned long pmemaddr __initdata; - -static int __init early_param_pmemaddr(char *p) -{ - pmemaddr = (unsigned long)simple_strtoul(p, NULL, 0); - return 0; -} -early_param("pmemaddr", early_param_pmemaddr); - -static long pmemlen __initdata; - -static int __init early_param_pmemlen(char *p) -{ -/* TODO: we can use this code when and if the bootloader ever changes this */ -#if 0 - pmemlen = (unsigned long)simple_strtoul(p, NULL, 0); -#else - pmemlen = 0x20000; -#endif - return 0; -} -early_param("pmemlen", early_param_pmemlen); - -/* - * Set up persistent memory. If we were given values, we patch the array of - * resources. Otherwise, persistent memory may be allocated anywhere at all. - */ -static void __init pmem_setup_resource(void) -{ - struct resource *resource; - resource = asic_resource_get("DiagPersistentMemory"); - - if (resource && pmemaddr && pmemlen) { - /* The address provided by bootloader is in kseg0. Convert to - * a bus address. */ - resource->start = phys_to_dma(pmemaddr - 0x80000000); - resource->end = resource->start + pmemlen - 1; - - pr_info("persistent memory: start=0x%x end=0x%x\n", - resource->start, resource->end); - } -} - -/* - * - * RESOURCE ACCESS FUNCTIONS - * - */ - -/** - * asic_resource_get - retrieves parameters for a platform resource. - * @name: string to match resource - * - * Returns a pointer to a struct resource corresponding to the given name. - * - * CANNOT BE NAMED platform_resource_get, which would be the obvious choice, - * as this function name is already declared - */ -struct resource *asic_resource_get(const char *name) -{ - int i; - - for (i = 0; gp_resources[i].flags != 0; i++) { - if (strcmp(gp_resources[i].name, name) == 0) - return &gp_resources[i]; - } - - return NULL; -} -EXPORT_SYMBOL(asic_resource_get); - -/** - * platform_release_memory - release pre-allocated memory - * @ptr: pointer to memory to release - * @size: size of resource - * - * This must only be called for memory allocated or reserved via the boot - * memory allocator. - */ -void platform_release_memory(void *ptr, int size) -{ - free_reserved_area(ptr, ptr + size, -1, NULL); -} -EXPORT_SYMBOL(platform_release_memory); - -/* - * - * FEATURE AVAILABILITY FUNCTIONS - * - */ -int platform_supports_dvr(void) -{ - return (platform_features & DVR_CAPABLE) != 0; -} - -int platform_supports_ffs(void) -{ - return (platform_features & FFS_CAPABLE) != 0; -} - -int platform_supports_pcie(void) -{ - return (platform_features & PCIE_CAPABLE) != 0; -} - -int platform_supports_display(void) -{ - return (platform_features & DISPLAY_CAPABLE) != 0; -} diff --git a/arch/mips/powertv/asic/asic_int.c b/arch/mips/powertv/asic/asic_int.c deleted file mode 100644 index f44cd9295cae..000000000000 --- a/arch/mips/powertv/asic/asic_int.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. - * Copyright (C) 2001 Ralf Baechle - * Portions copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Routines for generic manipulation of the interrupts found on the PowerTV - * platform. - * - * The interrupt controller is located in the South Bridge a PIIX4 device - * with two internal 82C95 interrupt controllers. - */ -#include <linux/init.h> -#include <linux/irq.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/kernel_stat.h> -#include <linux/kernel.h> -#include <linux/random.h> - -#include <asm/irq_cpu.h> -#include <linux/io.h> -#include <asm/irq_regs.h> -#include <asm/setup.h> -#include <asm/mips-boards/generic.h> - -#include <asm/mach-powertv/asic_regs.h> - -static DEFINE_RAW_SPINLOCK(asic_irq_lock); - -static inline int get_int(void) -{ - unsigned long flags; - int irq; - - raw_spin_lock_irqsave(&asic_irq_lock, flags); - - irq = (asic_read(int_int_scan) >> 4) - 1; - - if (irq == 0 || irq >= NR_IRQS) - irq = -1; - - raw_spin_unlock_irqrestore(&asic_irq_lock, flags); - - return irq; -} - -static void asic_irqdispatch(void) -{ - int irq; - - irq = get_int(); - if (irq < 0) - return; /* interrupt has already been cleared */ - - do_IRQ(irq); -} - -static inline int clz(unsigned long x) -{ - __asm__( - " .set push \n" - " .set mips32 \n" - " clz %0, %1 \n" - " .set pop \n" - : "=r" (x) - : "r" (x)); - - return x; -} - -/* - * Version of ffs that only looks at bits 12..15. - */ -static inline unsigned int irq_ffs(unsigned int pending) -{ - return fls(pending) - 1 + CAUSEB_IP; -} - -/* - * TODO: check how it works under EIC mode. - */ -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; - int irq; - - irq = irq_ffs(pending); - - if (irq == CAUSEF_IP3) - asic_irqdispatch(); - else if (irq >= 0) - do_IRQ(irq); - else - spurious_interrupt(); -} - -void __init arch_init_irq(void) -{ - int i; - - asic_irq_init(); - - /* - * Initialize interrupt exception vectors. - */ - if (cpu_has_veic || cpu_has_vint) { - int nvec = cpu_has_veic ? 64 : 8; - for (i = 0; i < nvec; i++) - set_vi_handler(i, asic_irqdispatch); - } -} diff --git a/arch/mips/powertv/asic/irq_asic.c b/arch/mips/powertv/asic/irq_asic.c deleted file mode 100644 index 9344902dc586..000000000000 --- a/arch/mips/powertv/asic/irq_asic.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Portions copyright (C) 2005-2009 Scientific Atlanta - * Portions copyright (C) 2009 Cisco Systems, Inc. - * - * Modified from arch/mips/kernel/irq-rm7000.c: - * Copyright (C) 2003 Ralf Baechle - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/kernel.h> -#include <linux/irq.h> - -#include <asm/irq_cpu.h> -#include <asm/mipsregs.h> - -#include <asm/mach-powertv/asic_regs.h> - -static inline void unmask_asic_irq(struct irq_data *d) -{ - unsigned long enable_bit; - unsigned int irq = d->irq; - - enable_bit = (1 << (irq & 0x1f)); - - switch (irq >> 5) { - case 0: - asic_write(asic_read(ien_int_0) | enable_bit, ien_int_0); - break; - case 1: - asic_write(asic_read(ien_int_1) | enable_bit, ien_int_1); - break; - case 2: - asic_write(asic_read(ien_int_2) | enable_bit, ien_int_2); - break; - case 3: - asic_write(asic_read(ien_int_3) | enable_bit, ien_int_3); - break; - default: - BUG(); - } -} - -static inline void mask_asic_irq(struct irq_data *d) -{ - unsigned long disable_mask; - unsigned int irq = d->irq; - - disable_mask = ~(1 << (irq & 0x1f)); - - switch (irq >> 5) { - case 0: - asic_write(asic_read(ien_int_0) & disable_mask, ien_int_0); - break; - case 1: - asic_write(asic_read(ien_int_1) & disable_mask, ien_int_1); - break; - case 2: - asic_write(asic_read(ien_int_2) & disable_mask, ien_int_2); - break; - case 3: - asic_write(asic_read(ien_int_3) & disable_mask, ien_int_3); - break; - default: - BUG(); - } -} - -static struct irq_chip asic_irq_chip = { - .name = "ASIC Level", - .irq_mask = mask_asic_irq, - .irq_unmask = unmask_asic_irq, -}; - -void __init asic_irq_init(void) -{ - int i; - - /* set priority to 0 */ - write_c0_status(read_c0_status() & ~(0x0000fc00)); - - asic_write(0, ien_int_0); - asic_write(0, ien_int_1); - asic_write(0, ien_int_2); - asic_write(0, ien_int_3); - - asic_write(0x0fffffff, int_level_3_3); - asic_write(0xffffffff, int_level_3_2); - asic_write(0xffffffff, int_level_3_1); - asic_write(0xffffffff, int_level_3_0); - asic_write(0xffffffff, int_level_2_3); - asic_write(0xffffffff, int_level_2_2); - asic_write(0xffffffff, int_level_2_1); - asic_write(0xffffffff, int_level_2_0); - asic_write(0xffffffff, int_level_1_3); - asic_write(0xffffffff, int_level_1_2); - asic_write(0xffffffff, int_level_1_1); - asic_write(0xffffffff, int_level_1_0); - asic_write(0xffffffff, int_level_0_3); - asic_write(0xffffffff, int_level_0_2); - asic_write(0xffffffff, int_level_0_1); - asic_write(0xffffffff, int_level_0_0); - - asic_write(0xf, int_int_scan); - - /* - * Initialize interrupt handlers. - */ - for (i = 0; i < NR_IRQS; i++) - irq_set_chip_and_handler(i, &asic_irq_chip, handle_level_irq); -} diff --git a/arch/mips/powertv/asic/prealloc-calliope.c b/arch/mips/powertv/asic/prealloc-calliope.c deleted file mode 100644 index 98dc51650577..000000000000 --- a/arch/mips/powertv/asic/prealloc-calliope.c +++ /dev/null @@ -1,385 +0,0 @@ -/* - * Memory pre-allocations for Calliope boxes. - * - * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: Ken Eppinett - * David Schleef <ds@schleef.org> - */ - -#include <linux/init.h> -#include <linux/ioport.h> -#include <asm/mach-powertv/asic.h> -#include "prealloc.h" - -/* - * NON_DVR_CAPABLE CALLIOPE RESOURCES - */ -struct resource non_dvr_calliope_resources[] __initdata = -{ - /* - * VIDEO / LX1 - */ - /* Delta-Mu 1 image (2MiB) */ - PREALLOC_NORMAL("ST231aImage", 0x24000000, 0x24200000-1, - IORESOURCE_MEM) - /* Delta-Mu 1 monitor (8KiB) */ - PREALLOC_NORMAL("ST231aMonitor", 0x24200000, 0x24202000-1, - IORESOURCE_MEM) - /* Delta-Mu 1 RAM (~36.9MiB (32MiB - (2MiB + 8KiB))) */ - PREALLOC_NORMAL("MediaMemory1", 0x24202000, 0x26700000-1, - IORESOURCE_MEM) - - /* - * Sysaudio Driver - */ - /* DSP code and data images (1MiB) */ - PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* ADSC CPU PCM buffer (40KiB) */ - PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* ADSC AUX buffer (128KiB) */ - PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* ADSC Main buffer (128KiB) */ - PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * STAVEM driver/STAPI - */ - /* 6MiB */ - PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00600000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * DOCSIS Subsystem - */ - /* 7MiB */ - PREALLOC_DOCSIS("Docsis", 0x27500000, 0x27c00000-1, IORESOURCE_MEM) - - /* - * GHW HAL Driver - */ - /* PowerTV Graphics Heap (14MiB) */ - PREALLOC_NORMAL("GraphicsHeap", 0x26700000, 0x26700000+(14*1048576)-1, - IORESOURCE_MEM) - - /* - * multi com buffer area - */ - /* 128KiB */ - PREALLOC_NORMAL("MulticomSHM", 0x23700000, 0x23720000-1, - IORESOURCE_MEM) - - /* - * DMA Ring buffer (don't need recording buffers) - */ - /* 680KiB */ - PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Display bins buffer for unit0 - */ - /* 4KiB */ - PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * AVFS: player HAL memory - */ - /* 945K * 3 for playback */ - PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * PMEM - */ - /* Persistent memory for diagnostics (64KiB) */ - PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Smartcard - */ - /* Read and write buffers for Internal/External cards (10KiB) */ - PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * NAND Flash - */ - /* 10KiB */ - PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1, - IORESOURCE_MEM) - - /* - * Synopsys GMAC Memory Region - */ - /* 64KiB */ - PREALLOC_NORMAL("GMAC", 0x00000000, 0x00010000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * TFTPBuffer - * - * This buffer is used in some minimal configurations (e.g. two-way - * loader) for storing software images - */ - PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Add other resources here - */ - - /* - * End of Resource marker - */ - { - .flags = 0, - }, -}; - - -struct resource non_dvr_vze_calliope_resources[] __initdata = -{ - /* - * VIDEO / LX1 - */ - /* Delta-Mu 1 image (2MiB) */ - PREALLOC_NORMAL("ST231aImage", 0x22000000, 0x22200000-1, - IORESOURCE_MEM) - /* Delta-Mu 1 monitor (8KiB) */ - PREALLOC_NORMAL("ST231aMonitor", 0x22200000, 0x22202000-1, - IORESOURCE_MEM) - /* Delta-Mu 1 RAM (10.12MiB) */ - PREALLOC_NORMAL("MediaMemory1", 0x22202000, 0x22C20B85-1, - IORESOURCE_MEM) - - /* - * Sysaudio Driver - */ - /* DSP code and data images (1MiB) */ - PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* ADSC CPU PCM buffer (40KiB) */ - PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* ADSC AUX buffer (16KiB) */ - PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00004000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* ADSC Main buffer (16KiB) */ - PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00004000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * STAVEM driver/STAPI - */ - /* 3.125MiB */ - PREALLOC_NORMAL("AVMEMPartition0", 0x20396000, 0x206B6000-1, - IORESOURCE_MEM) - - /* - * GHW HAL Driver - */ - /* PowerTV Graphics Heap (2.59MiB) */ - PREALLOC_NORMAL("GraphicsHeap", 0x20100000, 0x20396000-1, - IORESOURCE_MEM) - - /* - * multi com buffer area - */ - /* 128KiB */ - PREALLOC_NORMAL("MulticomSHM", 0x206B6000, 0x206D6000-1, - IORESOURCE_MEM) - - /* - * DMA Ring buffer (don't need recording buffers) - */ - /* 680KiB */ - PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Display bins buffer for unit0 - */ - /* 4KiB */ - PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * PMEM - */ - /* Persistent memory for diagnostics (64KiB) */ - PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Smartcard - */ - /* Read and write buffers for Internal/External cards (10KiB) */ - PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * NAND Flash - */ - /* 10KiB */ - PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1, - IORESOURCE_MEM) - - /* - * Synopsys GMAC Memory Region - */ - /* 64KiB */ - PREALLOC_NORMAL("GMAC", 0x00000000, 0x00010000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Add other resources here - */ - - /* - * End of Resource marker - */ - { - .flags = 0, - }, -}; - -struct resource non_dvr_vzf_calliope_resources[] __initdata = -{ - /* - * VIDEO / LX1 - */ - /* Delta-Mu 1 image (2MiB) */ - PREALLOC_NORMAL("ST231aImage", 0x24000000, 0x24200000-1, - IORESOURCE_MEM) - /* Delta-Mu 1 monitor (8KiB) */ - PREALLOC_NORMAL("ST231aMonitor", 0x24200000, 0x24202000-1, - IORESOURCE_MEM) - /* Delta-Mu 1 RAM (~19.4 (21.5MiB - (2MiB + 8KiB))) */ - PREALLOC_NORMAL("MediaMemory1", 0x24202000, 0x25580000-1, - IORESOURCE_MEM) - - /* - * Sysaudio Driver - */ - /* DSP code and data images (1MiB) */ - PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* ADSC CPU PCM buffer (40KiB) */ - PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* ADSC AUX buffer (128KiB) */ - PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* ADSC Main buffer (128KiB) */ - PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * STAVEM driver/STAPI - */ - /* 4.5MiB */ - PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00480000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * GHW HAL Driver - */ - /* PowerTV Graphics Heap (14MiB) */ - PREALLOC_NORMAL("GraphicsHeap", 0x25600000, 0x25600000+(14*1048576)-1, - IORESOURCE_MEM) - - /* - * multi com buffer area - */ - /* 128KiB */ - PREALLOC_NORMAL("MulticomSHM", 0x23700000, 0x23720000-1, - IORESOURCE_MEM) - - /* - * DMA Ring buffer (don't need recording buffers) - */ - /* 680KiB */ - PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Display bins buffer for unit0 - */ - /* 4KiB */ - PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Display bins buffer for unit1 - */ - /* 4KiB */ - PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * AVFS: player HAL memory - */ - /* 945K * 3 for playback */ - PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * PMEM - */ - /* Persistent memory for diagnostics (64KiB) */ - PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Smartcard - */ - /* Read and write buffers for Internal/External cards (10KiB) */ - PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * NAND Flash - */ - /* 10KiB */ - PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1, - IORESOURCE_MEM) - - /* - * Synopsys GMAC Memory Region - */ - /* 64KiB */ - PREALLOC_NORMAL("GMAC", 0x00000000, 0x00010000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Add other resources here - */ - - /* - * End of Resource marker - */ - { - .flags = 0, - }, -}; diff --git a/arch/mips/powertv/asic/prealloc-cronus.c b/arch/mips/powertv/asic/prealloc-cronus.c deleted file mode 100644 index 7c6ce7596935..000000000000 --- a/arch/mips/powertv/asic/prealloc-cronus.c +++ /dev/null @@ -1,340 +0,0 @@ -/* - * Memory pre-allocations for Cronus boxes. - * - * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: Ken Eppinett - * David Schleef <ds@schleef.org> - */ - -#include <linux/init.h> -#include <linux/ioport.h> -#include <asm/mach-powertv/asic.h> -#include "prealloc.h" - -/* - * DVR_CAPABLE CRONUS RESOURCES - */ -struct resource dvr_cronus_resources[] __initdata = -{ - /* - * VIDEO1 / LX1 - */ - /* Delta-Mu 1 image (2MiB) */ - PREALLOC_NORMAL("ST231aImage", 0x24000000, 0x24200000-1, - IORESOURCE_MEM) - /* Delta-Mu 1 monitor (8KiB) */ - PREALLOC_NORMAL("ST231aMonitor", 0x24200000, 0x24202000-1, - IORESOURCE_MEM) - /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */ - PREALLOC_NORMAL("MediaMemory1", 0x24202000, 0x26000000-1, - IORESOURCE_MEM) - - /* - * VIDEO2 / LX2 - */ - /* Delta-Mu 2 image (2MiB) */ - PREALLOC_NORMAL("ST231bImage", 0x60000000, 0x60200000-1, - IORESOURCE_MEM) - /* Delta-Mu 2 monitor (8KiB) */ - PREALLOC_NORMAL("ST231bMonitor", 0x60200000, 0x60202000-1, - IORESOURCE_MEM) - /* Delta-Mu 2 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */ - PREALLOC_NORMAL("MediaMemory2", 0x60202000, 0x62000000-1, - IORESOURCE_MEM) - - /* - * Sysaudio Driver - */ - /* DSP code and data images (1MiB) */ - PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* ADSC CPU PCM buffer (40KiB) */ - PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* ADSC AUX buffer (128KiB) */ - PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* ADSC Main buffer (128KiB) */ - PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * STAVEM driver/STAPI - * - * This memory area is used for allocating buffers for Video decoding - * purposes. Allocation/De-allocation within this buffer is managed - * by the STAVMEM driver of the STAPI. They could be Decimated - * Picture Buffers, Intermediate Buffers, as deemed necessary for - * video decoding purposes, for any video decoders on Zeus. - */ - /* 12MiB */ - PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00c00000-1, - IORESOURCE_MEM) - - /* - * DOCSIS Subsystem - */ - /* 7MiB */ - PREALLOC_DOCSIS("Docsis", 0x67500000, 0x67c00000-1, IORESOURCE_MEM) - - /* - * GHW HAL Driver - */ - /* PowerTV Graphics Heap (14MiB) */ - PREALLOC_NORMAL("GraphicsHeap", 0x62700000, 0x63500000-1, - IORESOURCE_MEM) - - /* - * multi com buffer area - */ - /* 128KiB */ - PREALLOC_NORMAL("MulticomSHM", 0x26000000, 0x26020000-1, - IORESOURCE_MEM) - - /* - * DMA Ring buffer - */ - PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x002EA000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Display bins buffer for unit0 - */ - /* 4KiB */ - PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Display bins buffer for unit1 - */ - /* 4KiB */ - PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1, - IORESOURCE_MEM) - - /* - * ITFS - */ - /* 815,104 bytes each for 2 ITFS partitions. */ - PREALLOC_NORMAL("ITFS", 0x00000000, 0x0018E000-1, IORESOURCE_MEM) - - /* - * AVFS - */ - /* (945K * 8) = (128K * 3) 5 playbacks / 3 server */ - PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x007c2000-1, - IORESOURCE_MEM) - - /* 4KiB */ - PREALLOC_NORMAL("AvfsFileSys", 0x00000000, 0x00001000-1, - IORESOURCE_MEM) - - /* - * PMEM - */ - /* Persistent memory for diagnostics (64KiB) */ - PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Smartcard - */ - /* Read and write buffers for Internal/External cards (10KiB) */ - PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, - IORESOURCE_MEM) - - /* - * KAVNET - */ - /* NP Reset Vector - must be of the form xxCxxxxx (4KiB) */ - PREALLOC_NORMAL("NP_Reset_Vector", 0x27c00000, 0x27c01000-1, - IORESOURCE_MEM) - /* NP Image - must be video bank 1 (320KiB) */ - PREALLOC_NORMAL("NP_Image", 0x27020000, 0x27070000-1, IORESOURCE_MEM) - /* NP IPC - must be video bank 2 (512KiB) */ - PREALLOC_NORMAL("NP_IPC", 0x63500000, 0x63580000-1, IORESOURCE_MEM) - - /* - * TFTPBuffer - * - * This buffer is used in some minimal configurations (e.g. two-way - * loader) for storing software images - */ - PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Add other resources here - */ - - /* - * End of Resource marker - */ - { - .flags = 0, - }, -}; - -/* - * NON_DVR_CAPABLE CRONUS RESOURCES - */ -struct resource non_dvr_cronus_resources[] __initdata = -{ - /* - * VIDEO1 / LX1 - */ - /* Delta-Mu 1 image (2MiB) */ - PREALLOC_NORMAL("ST231aImage", 0x24000000, 0x24200000-1, - IORESOURCE_MEM) - /* Delta-Mu 1 monitor (8KiB) */ - PREALLOC_NORMAL("ST231aMonitor", 0x24200000, 0x24202000-1, - IORESOURCE_MEM) - /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */ - PREALLOC_NORMAL("MediaMemory1", 0x24202000, 0x26000000-1, - IORESOURCE_MEM) - - /* - * VIDEO2 / LX2 - */ - /* Delta-Mu 2 image (2MiB) */ - PREALLOC_NORMAL("ST231bImage", 0x60000000, 0x60200000-1, - IORESOURCE_MEM) - /* Delta-Mu 2 monitor (8KiB) */ - PREALLOC_NORMAL("ST231bMonitor", 0x60200000, 0x60202000-1, - IORESOURCE_MEM) - /* Delta-Mu 2 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */ - PREALLOC_NORMAL("MediaMemory2", 0x60202000, 0x62000000-1, - IORESOURCE_MEM) - - /* - * Sysaudio Driver - */ - /* DSP code and data images (1MiB) */ - PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* ADSC CPU PCM buffer (40KiB) */ - PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* ADSC AUX buffer (128KiB) */ - PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* ADSC Main buffer (128KiB) */ - PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * STAVEM driver/STAPI - * - * This memory area is used for allocating buffers for Video decoding - * purposes. Allocation/De-allocation within this buffer is managed - * by the STAVMEM driver of the STAPI. They could be Decimated - * Picture Buffers, Intermediate Buffers, as deemed necessary for - * video decoding purposes, for any video decoders on Zeus. - */ - /* 12MiB */ - PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00c00000-1, - IORESOURCE_MEM) - - /* - * DOCSIS Subsystem - */ - /* 7MiB */ - PREALLOC_DOCSIS("Docsis", 0x67500000, 0x67c00000-1, IORESOURCE_MEM) - - /* - * GHW HAL Driver - */ - /* PowerTV Graphics Heap (14MiB) */ - PREALLOC_NORMAL("GraphicsHeap", 0x62700000, 0x63500000-1, - IORESOURCE_MEM) - - /* - * multi com buffer area - */ - /* 128KiB */ - PREALLOC_NORMAL("MulticomSHM", 0x26000000, 0x26020000-1, - IORESOURCE_MEM) - - /* - * DMA Ring buffer (don't need recording buffers) - */ - /* 680KiB */ - PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Display bins buffer for unit0 - */ - /* 4KiB */ - PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Display bins buffer for unit1 - */ - /* 4KiB */ - PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1, - IORESOURCE_MEM) - - /* - * AVFS: player HAL memory - */ - /* 945K * 3 for playback */ - PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1, IORESOURCE_MEM) - - /* - * PMEM - */ - /* Persistent memory for diagnostics (64KiB) */ - PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Smartcard - */ - /* Read and write buffers for Internal/External cards (10KiB) */ - PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, IORESOURCE_MEM) - - /* - * KAVNET - */ - /* NP Reset Vector - must be of the form xxCxxxxx (4KiB) */ - PREALLOC_NORMAL("NP_Reset_Vector", 0x27c00000, 0x27c01000-1, - IORESOURCE_MEM) - /* NP Image - must be video bank 1 (320KiB) */ - PREALLOC_NORMAL("NP_Image", 0x27020000, 0x27070000-1, IORESOURCE_MEM) - /* NP IPC - must be video bank 2 (512KiB) */ - PREALLOC_NORMAL("NP_IPC", 0x63500000, 0x63580000-1, IORESOURCE_MEM) - - /* - * NAND Flash - */ - /* 10KiB */ - PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1, - IORESOURCE_MEM) - - /* - * Add other resources here - */ - - /* - * End of Resource marker - */ - { - .flags = 0, - }, -}; diff --git a/arch/mips/powertv/asic/prealloc-cronuslite.c b/arch/mips/powertv/asic/prealloc-cronuslite.c deleted file mode 100644 index a7937ba7b4c0..000000000000 --- a/arch/mips/powertv/asic/prealloc-cronuslite.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * Memory pre-allocations for Cronus Lite boxes. - * - * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: Ken Eppinett - * David Schleef <ds@schleef.org> - */ - -#include <linux/init.h> -#include <linux/ioport.h> -#include <asm/mach-powertv/asic.h> -#include "prealloc.h" - -/* - * NON_DVR_CAPABLE CRONUSLITE RESOURCES - */ -struct resource non_dvr_cronuslite_resources[] __initdata = -{ - /* - * VIDEO2 / LX2 - */ - /* Delta-Mu 1 image (2MiB) */ - PREALLOC_NORMAL("ST231aImage", 0x60000000, 0x60200000-1, - IORESOURCE_MEM) - /* Delta-Mu 1 monitor (8KiB) */ - PREALLOC_NORMAL("ST231aMonitor", 0x60200000, 0x60202000-1, - IORESOURCE_MEM) - /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */ - PREALLOC_NORMAL("MediaMemory1", 0x60202000, 0x62000000-1, - IORESOURCE_MEM) - - /* - * Sysaudio Driver - */ - /* DSP code and data images (1MiB) */ - PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* ADSC CPU PCM buffer (40KiB) */ - PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* ADSC AUX buffer (128KiB) */ - PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* ADSC Main buffer (128KiB) */ - PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * STAVEM driver/STAPI - * - * This memory area is used for allocating buffers for Video decoding - * purposes. Allocation/De-allocation within this buffer is managed - * by the STAVMEM driver of the STAPI. They could be Decimated - * Picture Buffers, Intermediate Buffers, as deemed necessary for - * video decoding purposes, for any video decoders on Zeus. - */ - /* 6MiB */ - PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00600000-1, - IORESOURCE_MEM) - - /* - * DOCSIS Subsystem - */ - /* 7MiB */ - PREALLOC_DOCSIS("Docsis", 0x67500000, 0x67c00000-1, IORESOURCE_MEM) - - /* - * GHW HAL Driver - */ - /* PowerTV Graphics Heap (14MiB) */ - PREALLOC_NORMAL("GraphicsHeap", 0x62700000, 0x63500000-1, - IORESOURCE_MEM) - - /* - * multi com buffer area - */ - /* 128KiB */ - PREALLOC_NORMAL("MulticomSHM", 0x26000000, 0x26020000-1, - IORESOURCE_MEM) - - /* - * DMA Ring buffer (don't need recording buffers) - */ - /* 680KiB */ - PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Display bins buffer for unit0 - */ - /* 4KiB */ - PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Display bins buffer for unit1 - */ - /* 4KiB */ - PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1, - IORESOURCE_MEM) - - /* - * AVFS: player HAL memory - */ - /* 945K * 3 for playback */ - PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * PMEM - */ - /* Persistent memory for diagnostics (64KiB) */ - PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Smartcard - */ - /* Read and write buffers for Internal/External cards (10KiB) */ - PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, IORESOURCE_MEM) - - /* - * KAVNET - */ - /* NP Reset Vector - must be of the form xxCxxxxx (4KiB) */ - PREALLOC_NORMAL("NP_Reset_Vector", 0x27c00000, 0x27c01000-1, - IORESOURCE_MEM) - /* NP Image - must be video bank 1 (320KiB) */ - PREALLOC_NORMAL("NP_Image", 0x27020000, 0x27070000-1, IORESOURCE_MEM) - /* NP IPC - must be video bank 2 (512KiB) */ - PREALLOC_NORMAL("NP_IPC", 0x63500000, 0x63580000-1, IORESOURCE_MEM) - - /* - * NAND Flash - */ - /* 10KiB */ - PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1, - IORESOURCE_MEM) - - /* - * TFTPBuffer - * - * This buffer is used in some minimal configurations (e.g. two-way - * loader) for storing software images - */ - PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Add other resources here - */ - - /* - * End of Resource marker - */ - { - .flags = 0, - }, -}; diff --git a/arch/mips/powertv/asic/prealloc-gaia.c b/arch/mips/powertv/asic/prealloc-gaia.c deleted file mode 100644 index 2303bbfe6b82..000000000000 --- a/arch/mips/powertv/asic/prealloc-gaia.c +++ /dev/null @@ -1,589 +0,0 @@ -/* - * Memory pre-allocations for Gaia boxes. - * - * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: David VomLehn - */ - -#include <linux/init.h> -#include <asm/mach-powertv/asic.h> - -/* - * DVR_CAPABLE GAIA RESOURCES - */ -struct resource dvr_gaia_resources[] __initdata = { - /* - * - * VIDEO1 / LX1 - * - */ - { - .name = "ST231aImage", /* Delta-Mu 1 image and ram */ - .start = 0x24000000, - .end = 0x241FFFFF, /* 2MiB */ - .flags = IORESOURCE_MEM, - }, - { - .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ - .start = 0x24200000, - .end = 0x24201FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "MediaMemory1", - .start = 0x24202000, - .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_MEM, - }, - /* - * - * VIDEO2 / LX2 - * - */ - { - .name = "ST231bImage", /* Delta-Mu 2 image and ram */ - .start = 0x60000000, - .end = 0x601FFFFF, /* 2MiB */ - .flags = IORESOURCE_IO, - }, - { - .name = "ST231bMonitor", /* 8KiB block ST231b monitor */ - .start = 0x60200000, - .end = 0x60201FFF, - .flags = IORESOURCE_IO, - }, - { - .name = "MediaMemory2", - .start = 0x60202000, - .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_IO, - }, - /* - * - * Sysaudio Driver - * - * This driver requires: - * - * Arbitrary Based Buffers: - * DSP_Image_Buff - DSP code and data images (1MB) - * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) - * ADSC_AUX_Buff - ADSC AUX buffer (16KB) - * ADSC_Main_Buff - ADSC Main buffer (16KB) - * - */ - { - .name = "DSP_Image_Buff", - .start = 0x00000000, - .end = 0x000FFFFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_CPU_PCM_Buff", - .start = 0x00000000, - .end = 0x00009FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_AUX_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_Main_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - /* - * - * STAVEM driver/STAPI - * - * This driver requires: - * - * Arbitrary Based Buffers: - * This memory area is used for allocating buffers for Video decoding - * purposes. Allocation/De-allocation within this buffer is managed - * by the STAVMEM driver of the STAPI. They could be Decimated - * Picture Buffers, Intermediate Buffers, as deemed necessary for - * video decoding purposes, for any video decoders on Zeus. - * - */ - { - .name = "AVMEMPartition0", - .start = 0x63580000, - .end = 0x64180000 - 1, /* 12 MB total */ - .flags = IORESOURCE_IO, - }, - /* - * - * DOCSIS Subsystem - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * - */ - { - .name = "Docsis", - .start = 0x62000000, - .end = 0x62700000 - 1, /* 7 MB total */ - .flags = IORESOURCE_IO, - }, - /* - * - * GHW HAL Driver - * - * This driver requires: - * - * Arbitrary Based Buffers: - * GraphicsHeap - PowerTV Graphics Heap - * - */ - { - .name = "GraphicsHeap", - .start = 0x62700000, - .end = 0x63500000 - 1, /* 14 MB total */ - .flags = IORESOURCE_IO, - }, - /* - * - * multi com buffer area - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * - */ - { - .name = "MulticomSHM", - .start = 0x26000000, - .end = 0x26020000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * - * DMA Ring buffer - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * - */ - { - .name = "BMM_Buffer", - .start = 0x00000000, - .end = 0x00280000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * - * Display bins buffer for unit0 - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Display Bins for unit0 - * - */ - { - .name = "DisplayBins0", - .start = 0x00000000, - .end = 0x00000FFF, /* 4 KB total */ - .flags = IORESOURCE_MEM, - }, - /* - * - * Display bins buffer - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Display Bins for unit1 - * - */ - { - .name = "DisplayBins1", - .start = 0x64AD4000, - .end = 0x64AD5000 - 1, /* 4 KB total */ - .flags = IORESOURCE_IO, - }, - /* - * - * ITFS - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * - */ - { - .name = "ITFS", - .start = 0x64180000, - /* 815,104 bytes each for 2 ITFS partitions. */ - .end = 0x6430DFFF, - .flags = IORESOURCE_IO, - }, - /* - * - * AVFS - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * - */ - { - .name = "AvfsDmaMem", - .start = 0x6430E000, - /* (945K * 8) = (128K *3) 5 playbacks / 3 server */ - .end = 0x64AD0000 - 1, - .flags = IORESOURCE_IO, - }, - { - .name = "AvfsFileSys", - .start = 0x64AD0000, - .end = 0x64AD1000 - 1, /* 4K */ - .flags = IORESOURCE_IO, - }, - /* - * - * Smartcard - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Read and write buffers for Internal/External cards - * - */ - { - .name = "SmartCardInfo", - .start = 0x64AD1000, - .end = 0x64AD3800 - 1, - .flags = IORESOURCE_IO, - }, - /* - * - * KAVNET - * NP Reset Vector - must be of the form xxCxxxxx - * NP Image - must be video bank 1 - * NP IPC - must be video bank 2 - */ - { - .name = "NP_Reset_Vector", - .start = 0x27c00000, - .end = 0x27c01000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "NP_Image", - .start = 0x27020000, - .end = 0x27060000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "NP_IPC", - .start = 0x63500000, - .end = 0x63580000 - 1, - .flags = IORESOURCE_IO, - }, - /* - * Add other resources here - */ - { }, -}; - -/* - * NON_DVR_CAPABLE GAIA RESOURCES - */ -struct resource non_dvr_gaia_resources[] __initdata = { - /* - * - * VIDEO1 / LX1 - * - */ - { - .name = "ST231aImage", /* Delta-Mu 1 image and ram */ - .start = 0x24000000, - .end = 0x241FFFFF, /* 2MiB */ - .flags = IORESOURCE_MEM, - }, - { - .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ - .start = 0x24200000, - .end = 0x24201FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "MediaMemory1", - .start = 0x24202000, - .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_MEM, - }, - /* - * - * VIDEO2 / LX2 - * - */ - { - .name = "ST231bImage", /* Delta-Mu 2 image and ram */ - .start = 0x60000000, - .end = 0x601FFFFF, /* 2MiB */ - .flags = IORESOURCE_IO, - }, - { - .name = "ST231bMonitor", /* 8KiB block ST231b monitor */ - .start = 0x60200000, - .end = 0x60201FFF, - .flags = IORESOURCE_IO, - }, - { - .name = "MediaMemory2", - .start = 0x60202000, - .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_IO, - }, - /* - * - * Sysaudio Driver - * - * This driver requires: - * - * Arbitrary Based Buffers: - * DSP_Image_Buff - DSP code and data images (1MB) - * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) - * ADSC_AUX_Buff - ADSC AUX buffer (16KB) - * ADSC_Main_Buff - ADSC Main buffer (16KB) - * - */ - { - .name = "DSP_Image_Buff", - .start = 0x00000000, - .end = 0x000FFFFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_CPU_PCM_Buff", - .start = 0x00000000, - .end = 0x00009FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_AUX_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_Main_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - /* - * - * STAVEM driver/STAPI - * - * This driver requires: - * - * Arbitrary Based Buffers: - * This memory area is used for allocating buffers for Video decoding - * purposes. Allocation/De-allocation within this buffer is managed - * by the STAVMEM driver of the STAPI. They could be Decimated - * Picture Buffers, Intermediate Buffers, as deemed necessary for - * video decoding purposes, for any video decoders on Zeus. - * - */ - { - .name = "AVMEMPartition0", - .start = 0x63580000, - .end = 0x64180000 - 1, /* 12 MB total */ - .flags = IORESOURCE_IO, - }, - /* - * - * DOCSIS Subsystem - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * - */ - { - .name = "Docsis", - .start = 0x62000000, - .end = 0x62700000 - 1, /* 7 MB total */ - .flags = IORESOURCE_IO, - }, - /* - * - * GHW HAL Driver - * - * This driver requires: - * - * Arbitrary Based Buffers: - * GraphicsHeap - PowerTV Graphics Heap - * - */ - { - .name = "GraphicsHeap", - .start = 0x62700000, - .end = 0x63500000 - 1, /* 14 MB total */ - .flags = IORESOURCE_IO, - }, - /* - * - * multi com buffer area - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * - */ - { - .name = "MulticomSHM", - .start = 0x26000000, - .end = 0x26020000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * - * DMA Ring buffer - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * - */ - { - .name = "BMM_Buffer", - .start = 0x00000000, - .end = 0x000AA000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * - * Display bins buffer for unit0 - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Display Bins for unit0 - * - */ - { - .name = "DisplayBins0", - .start = 0x00000000, - .end = 0x00000FFF, /* 4 KB total */ - .flags = IORESOURCE_MEM, - }, - /* - * - * Display bins buffer - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Display Bins for unit1 - * - */ - { - .name = "DisplayBins1", - .start = 0x64AD4000, - .end = 0x64AD5000 - 1, /* 4 KB total */ - .flags = IORESOURCE_IO, - }, - /* - * - * AVFS: player HAL memory - * - * - */ - { - .name = "AvfsDmaMem", - .start = 0x6430E000, - .end = 0x645D2C00 - 1, /* 945K * 3 for playback */ - .flags = IORESOURCE_IO, - }, - /* - * - * PMEM - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Persistent memory for diagnostics. - * - */ - { - .name = "DiagPersistentMemory", - .start = 0x00000000, - .end = 0x10000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * - * Smartcard - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Read and write buffers for Internal/External cards - * - */ - { - .name = "SmartCardInfo", - .start = 0x64AD1000, - .end = 0x64AD3800 - 1, - .flags = IORESOURCE_IO, - }, - /* - * - * KAVNET - * NP Reset Vector - must be of the form xxCxxxxx - * NP Image - must be video bank 1 - * NP IPC - must be video bank 2 - */ - { - .name = "NP_Reset_Vector", - .start = 0x27c00000, - .end = 0x27c01000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "NP_Image", - .start = 0x27020000, - .end = 0x27060000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "NP_IPC", - .start = 0x63500000, - .end = 0x63580000 - 1, - .flags = IORESOURCE_IO, - }, - { }, -}; diff --git a/arch/mips/powertv/asic/prealloc-zeus.c b/arch/mips/powertv/asic/prealloc-zeus.c deleted file mode 100644 index 6e76f09c68d6..000000000000 --- a/arch/mips/powertv/asic/prealloc-zeus.c +++ /dev/null @@ -1,304 +0,0 @@ -/* - * Memory pre-allocations for Zeus boxes. - * - * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: Ken Eppinett - * David Schleef <ds@schleef.org> - */ - -#include <linux/init.h> -#include <linux/ioport.h> -#include <asm/mach-powertv/asic.h> -#include "prealloc.h" - -/* - * DVR_CAPABLE RESOURCES - */ -struct resource dvr_zeus_resources[] __initdata = -{ - /* - * VIDEO1 / LX1 - */ - /* Delta-Mu 1 image (2MiB) */ - PREALLOC_NORMAL("ST231aImage", 0x20000000, 0x20200000-1, - IORESOURCE_MEM) - /* Delta-Mu 1 monitor (8KiB) */ - PREALLOC_NORMAL("ST231aMonitor", 0x20200000, 0x20202000-1, - IORESOURCE_MEM) - /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */ - PREALLOC_NORMAL("MediaMemory1", 0x20202000, 0x22000000-1, - IORESOURCE_MEM) - - /* - * VIDEO2 / LX2 - */ - /* Delta-Mu 2 image (2MiB) */ - PREALLOC_NORMAL("ST231bImage", 0x30000000, 0x30200000-1, - IORESOURCE_MEM) - /* Delta-Mu 2 monitor (8KiB) */ - PREALLOC_NORMAL("ST231bMonitor", 0x30200000, 0x30202000-1, - IORESOURCE_MEM) - /* Delta-Mu 2 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */ - PREALLOC_NORMAL("MediaMemory2", 0x30202000, 0x32000000-1, - IORESOURCE_MEM) - - /* - * Sysaudio Driver - */ - /* DSP code and data images (1MiB) */ - PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* ADSC CPU PCM buffer (40KiB) */ - PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* ADSC AUX buffer (16KiB) */ - PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00004000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* ADSC Main buffer (16KiB) */ - PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00004000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * STAVEM driver/STAPI - * - * This memory area is used for allocating buffers for Video decoding - * purposes. Allocation/De-allocation within this buffer is managed - * by the STAVMEM driver of the STAPI. They could be Decimated - * Picture Buffers, Intermediate Buffers, as deemed necessary for - * video decoding purposes, for any video decoders on Zeus. - */ - /* 12MiB */ - PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00c00000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * DOCSIS Subsystem - */ - /* 7MiB */ - PREALLOC_DOCSIS("Docsis", 0x40100000, 0x40800000-1, IORESOURCE_MEM) - - /* - * GHW HAL Driver - */ - /* PowerTV Graphics Heap (14MiB) */ - PREALLOC_NORMAL("GraphicsHeap", 0x46900000, 0x47700000-1, - IORESOURCE_MEM) - - /* - * multi com buffer area - */ - /* 128KiB */ - PREALLOC_NORMAL("MulticomSHM", 0x47900000, 0x47920000-1, - IORESOURCE_MEM) - - /* - * DMA Ring buffer - */ - /* 2.5MiB */ - PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x00280000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Display bins buffer for unit0 - */ - /* 4KiB */ - PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Display bins buffer for unit1 - */ - /* 4KiB */ - PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * ITFS - */ - /* 815,104 bytes each for 2 ITFS partitions. */ - PREALLOC_NORMAL("ITFS", 0x00000000, 0x0018E000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * AVFS - */ - /* (945K * 8) = (128K * 3) 5 playbacks / 3 server */ - PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x007c2000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* 4KiB */ - PREALLOC_NORMAL("AvfsFileSys", 0x00000000, 0x00001000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * PMEM - */ - /* Persistent memory for diagnostics (64KiB) */ - PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Smartcard - */ - /* Read and write buffers for Internal/External cards (10KiB) */ - PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * TFTPBuffer - * - * This buffer is used in some minimal configurations (e.g. two-way - * loader) for storing software images - */ - PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Add other resources here - */ - - /* - * End of Resource marker - */ - { - .flags = 0, - }, -}; - -/* - * NON_DVR_CAPABLE ZEUS RESOURCES - */ -struct resource non_dvr_zeus_resources[] __initdata = -{ - /* - * VIDEO1 / LX1 - */ - /* Delta-Mu 1 image (2MiB) */ - PREALLOC_NORMAL("ST231aImage", 0x20000000, 0x20200000-1, - IORESOURCE_MEM) - /* Delta-Mu 1 monitor (8KiB) */ - PREALLOC_NORMAL("ST231aMonitor", 0x20200000, 0x20202000-1, - IORESOURCE_MEM) - /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */ - PREALLOC_NORMAL("MediaMemory1", 0x20202000, 0x22000000-1, - IORESOURCE_MEM) - - /* - * Sysaudio Driver - */ - /* DSP code and data images (1MiB) */ - PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* ADSC CPU PCM buffer (40KiB) */ - PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* ADSC AUX buffer (16KiB) */ - PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00004000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - /* ADSC Main buffer (16KiB) */ - PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00004000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * STAVEM driver/STAPI - */ - /* 6MiB */ - PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00600000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * DOCSIS Subsystem - */ - /* 7MiB */ - PREALLOC_DOCSIS("Docsis", 0x40100000, 0x40800000-1, IORESOURCE_MEM) - - /* - * GHW HAL Driver - */ - /* PowerTV Graphics Heap (14MiB) */ - PREALLOC_NORMAL("GraphicsHeap", 0x46900000, 0x47700000-1, - IORESOURCE_MEM) - - /* - * multi com buffer area - */ - /* 128KiB */ - PREALLOC_NORMAL("MulticomSHM", 0x47900000, 0x47920000-1, - IORESOURCE_MEM) - - /* - * DMA Ring buffer - */ - /* 2.5MiB */ - PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x00280000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Display bins buffer for unit0 - */ - /* 4KiB */ - PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * AVFS: player HAL memory - */ - /* 945K * 3 for playback */ - PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * PMEM - */ - /* Persistent memory for diagnostics (64KiB) */ - PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Smartcard - */ - /* Read and write buffers for Internal/External cards (10KiB) */ - PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * NAND Flash - */ - /* 10KiB */ - PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1, - IORESOURCE_MEM) - - /* - * TFTPBuffer - * - * This buffer is used in some minimal configurations (e.g. two-way - * loader) for storing software images - */ - PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1, - (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) - - /* - * Add other resources here - */ - - /* - * End of Resource marker - */ - { - .flags = 0, - }, -}; diff --git a/arch/mips/powertv/asic/prealloc.h b/arch/mips/powertv/asic/prealloc.h deleted file mode 100644 index 8e682df17856..000000000000 --- a/arch/mips/powertv/asic/prealloc.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Definitions for memory preallocations - * - * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _ARCH_MIPS_POWERTV_ASIC_PREALLOC_H -#define _ARCH_MIPS_POWERTV_ASIC_PREALLOC_H - -#define KIBIBYTE(n) ((n) * 1024) /* Number of kibibytes */ -#define MEBIBYTE(n) ((n) * KIBIBYTE(1024)) /* Number of mebibytes */ - -/* "struct resource" array element definition */ -#define PREALLOC(NAME, START, END, FLAGS) { \ - .name = (NAME), \ - .start = (START), \ - .end = (END), \ - .flags = (FLAGS) \ - }, - -/* Individual resources in the preallocated resource arrays are defined using - * macros. These macros are conditionally defined based on their - * corresponding kernel configuration flag: - * - CONFIG_PREALLOC_NORMAL: preallocate resources for a normal settop box - * - CONFIG_PREALLOC_TFTP: preallocate the TFTP download resource - * - CONFIG_PREALLOC_DOCSIS: preallocate the DOCSIS resource - * - CONFIG_PREALLOC_PMEM: reserve space for persistent memory - */ -#ifdef CONFIG_PREALLOC_NORMAL -#define PREALLOC_NORMAL(name, start, end, flags) \ - PREALLOC(name, start, end, flags) -#else -#define PREALLOC_NORMAL(name, start, end, flags) -#endif - -#ifdef CONFIG_PREALLOC_TFTP -#define PREALLOC_TFTP(name, start, end, flags) \ - PREALLOC(name, start, end, flags) -#else -#define PREALLOC_TFTP(name, start, end, flags) -#endif - -#ifdef CONFIG_PREALLOC_DOCSIS -#define PREALLOC_DOCSIS(name, start, end, flags) \ - PREALLOC(name, start, end, flags) -#else -#define PREALLOC_DOCSIS(name, start, end, flags) -#endif - -#ifdef CONFIG_PREALLOC_PMEM -#define PREALLOC_PMEM(name, start, end, flags) \ - PREALLOC(name, start, end, flags) -#else -#define PREALLOC_PMEM(name, start, end, flags) -#endif -#endif diff --git a/arch/mips/powertv/init.c b/arch/mips/powertv/init.c deleted file mode 100644 index a01baff52cae..000000000000 --- a/arch/mips/powertv/init.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. - * All rights reserved. - * Authors: Carsten Langgaard <carstenl@mips.com> - * Maciej W. Rozycki <macro@mips.com> - * Portions copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * PROM library initialisation code. - */ -#include <linux/init.h> -#include <linux/string.h> -#include <linux/kernel.h> - -#include <asm/bootinfo.h> -#include <linux/io.h> -#include <asm/cacheflush.h> -#include <asm/traps.h> - -#include <asm/mips-boards/generic.h> -#include <asm/mach-powertv/asic.h> - -#include "init.h" - -static int *_prom_envp; -unsigned long _prom_memsize; - -/* - * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. - * This macro take care of sign extension, if running in 64-bit mode. - */ -#define prom_envp(index) ((char *)(long)_prom_envp[(index)]) - -char *prom_getenv(char *envname) -{ - char *result = NULL; - - if (_prom_envp != NULL) { - /* - * Return a pointer to the given environment variable. - * In 64-bit mode: we're using 64-bit pointers, but all pointers - * in the PROM structures are only 32-bit, so we need some - * workarounds, if we are running in 64-bit mode. - */ - int i, index = 0; - - i = strlen(envname); - - while (prom_envp(index)) { - if (strncmp(envname, prom_envp(index), i) == 0) { - result = prom_envp(index + 1); - break; - } - index += 2; - } - } - - return result; -} - -void __init prom_init(void) -{ - int prom_argc; - char *prom_argv; - - prom_argc = fw_arg0; - prom_argv = (char *) fw_arg1; - _prom_envp = (int *) fw_arg2; - _prom_memsize = (unsigned long) fw_arg3; - - if (prom_argc == 1) { - strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE); - strlcat(arcs_cmdline, prom_argv, COMMAND_LINE_SIZE); - } - - configure_platform(); - prom_meminit(); - -#ifndef CONFIG_BOOTLOADER_DRIVER - pr_info("\nBootloader driver isn't loaded...\n"); -#endif -} diff --git a/arch/mips/powertv/init.h b/arch/mips/powertv/init.h deleted file mode 100644 index c1a8bd0dbe4b..000000000000 --- a/arch/mips/powertv/init.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Definitions from powertv init.c file - * - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: David VomLehn - */ - -#ifndef _POWERTV_INIT_H -#define _POWERTV_INIT_H -extern unsigned long _prom_memsize; -extern void prom_meminit(void); -extern char *prom_getenv(char *name); -#endif diff --git a/arch/mips/powertv/ioremap.c b/arch/mips/powertv/ioremap.c deleted file mode 100644 index d060478aab03..000000000000 --- a/arch/mips/powertv/ioremap.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * ioremap.c - * - * Support for mapping between dma_addr_t values a phys_addr_t values. - * - * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: David VomLehn <dvomlehn@cisco.com> - * - * Description: Defines the platform resources for the SA settop. - * - * NOTE: The bootloader allocates persistent memory at an address which is - * 16 MiB below the end of the highest address in KSEG0. All fixed - * address memory reservations must avoid this region. - */ - -#include <linux/kernel.h> -#include <linux/module.h> - -#include <asm/mach-powertv/ioremap.h> - -/* - * Define the sizes of and masks for grains in physical and DMA space. The - * values are the same but the types are not. - */ -#define IOR_PHYS_GRAIN ((phys_addr_t) 1 << IOR_LSBITS) -#define IOR_PHYS_GRAIN_MASK (IOR_PHYS_GRAIN - 1) - -#define IOR_DMA_GRAIN ((dma_addr_t) 1 << IOR_LSBITS) -#define IOR_DMA_GRAIN_MASK (IOR_DMA_GRAIN - 1) - -/* - * Values that, when accessed by an index derived from a phys_addr_t and - * added to phys_addr_t value, yield a DMA address - */ -struct ior_phys_to_dma _ior_phys_to_dma[IOR_NUM_PHYS_TO_DMA]; -EXPORT_SYMBOL(_ior_phys_to_dma); - -/* - * Values that, when accessed by an index derived from a dma_addr_t and - * added to that dma_addr_t value, yield a physical address - */ -struct ior_dma_to_phys _ior_dma_to_phys[IOR_NUM_DMA_TO_PHYS]; -EXPORT_SYMBOL(_ior_dma_to_phys); - -/** - * setup_dma_to_phys - set up conversion from DMA to physical addresses - * @dma_idx: Top IOR_LSBITS bits of the DMA address, i.e. an index - * into the array _dma_to_phys. - * @delta: Value that, when added to the DMA address, will yield the - * physical address - * @s: Number of bytes in the section of memory with the given delta - * between DMA and physical addresses. - */ -static void setup_dma_to_phys(dma_addr_t dma, phys_addr_t delta, dma_addr_t s) -{ - int dma_idx, first_idx, last_idx; - phys_addr_t first, last; - - /* - * Calculate the first and last indices, rounding the first up and - * the second down. - */ - first = dma & ~IOR_DMA_GRAIN_MASK; - last = (dma + s - 1) & ~IOR_DMA_GRAIN_MASK; - first_idx = first >> IOR_LSBITS; /* Convert to indices */ - last_idx = last >> IOR_LSBITS; - - for (dma_idx = first_idx; dma_idx <= last_idx; dma_idx++) - _ior_dma_to_phys[dma_idx].offset = delta >> IOR_DMA_SHIFT; -} - -/** - * setup_phys_to_dma - set up conversion from DMA to physical addresses - * @phys_idx: Top IOR_LSBITS bits of the DMA address, i.e. an index - * into the array _phys_to_dma. - * @delta: Value that, when added to the DMA address, will yield the - * physical address - * @s: Number of bytes in the section of memory with the given delta - * between DMA and physical addresses. - */ -static void setup_phys_to_dma(phys_addr_t phys, dma_addr_t delta, phys_addr_t s) -{ - int phys_idx, first_idx, last_idx; - phys_addr_t first, last; - - /* - * Calculate the first and last indices, rounding the first up and - * the second down. - */ - first = phys & ~IOR_PHYS_GRAIN_MASK; - last = (phys + s - 1) & ~IOR_PHYS_GRAIN_MASK; - first_idx = first >> IOR_LSBITS; /* Convert to indices */ - last_idx = last >> IOR_LSBITS; - - for (phys_idx = first_idx; phys_idx <= last_idx; phys_idx++) - _ior_phys_to_dma[phys_idx].offset = delta >> IOR_PHYS_SHIFT; -} - -/** - * ioremap_add_map - add to the physical and DMA address conversion arrays - * @phys: Process's view of the address of the start of the memory chunk - * @dma: DMA address of the start of the memory chunk - * @size: Size, in bytes, of the chunk of memory - * - * NOTE: It might be obvious, but the assumption is that all @size bytes have - * the same offset between the physical address and the DMA address. - */ -void ioremap_add_map(phys_addr_t phys, phys_addr_t dma, phys_addr_t size) -{ - if (size == 0) - return; - - if ((dma & IOR_DMA_GRAIN_MASK) != 0 || - (phys & IOR_PHYS_GRAIN_MASK) != 0 || - (size & IOR_PHYS_GRAIN_MASK) != 0) - pr_crit("Memory allocation must be in chunks of 0x%x bytes\n", - IOR_PHYS_GRAIN); - - setup_dma_to_phys(dma, phys - dma, size); - setup_phys_to_dma(phys, dma - phys, size); -} diff --git a/arch/mips/powertv/memory.c b/arch/mips/powertv/memory.c deleted file mode 100644 index bc2f3ca22b41..000000000000 --- a/arch/mips/powertv/memory.c +++ /dev/null @@ -1,353 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * Portions copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Apparently originally from arch/mips/malta-memory.c. Modified to work - * with the PowerTV bootloader. - */ -#include <linux/init.h> -#include <linux/mm.h> -#include <linux/bootmem.h> -#include <linux/pfn.h> -#include <linux/string.h> - -#include <asm/bootinfo.h> -#include <asm/page.h> -#include <asm/sections.h> - -#include <asm/mach-powertv/asic.h> -#include <asm/mach-powertv/ioremap.h> - -#include "init.h" - -/* Memory constants */ -#define KIBIBYTE(n) ((n) * 1024) /* Number of kibibytes */ -#define MEBIBYTE(n) ((n) * KIBIBYTE(1024)) /* Number of mebibytes */ -#define DEFAULT_MEMSIZE MEBIBYTE(128) /* If no memsize provided */ - -#define BLDR_SIZE KIBIBYTE(256) /* Memory reserved for bldr */ -#define RV_SIZE MEBIBYTE(4) /* Size of reset vector */ - -#define LOW_MEM_END 0x20000000 /* Highest low memory address */ -#define BLDR_ALIAS 0x10000000 /* Bootloader address */ -#define RV_PHYS 0x1fc00000 /* Reset vector address */ -#define LOW_RAM_END RV_PHYS /* End of real RAM in low mem */ - -/* - * Very low-level conversion from processor physical address to device - * DMA address for the first bank of memory. - */ -#define PHYS_TO_DMA(paddr) ((paddr) + (CONFIG_LOW_RAM_DMA - LOW_RAM_ALIAS)) - -unsigned long ptv_memsize; - -/* - * struct low_mem_reserved - Items in low memory that are reserved - * @start: Physical address of item - * @size: Size, in bytes, of this item - * @is_aliased: True if this is RAM aliased from another location. If false, - * it is something other than aliased RAM and the RAM in the - * unaliased address is still visible outside of low memory. - */ -struct low_mem_reserved { - phys_addr_t start; - phys_addr_t size; - bool is_aliased; -}; - -/* - * Must be in ascending address order - */ -struct low_mem_reserved low_mem_reserved[] = { - {BLDR_ALIAS, BLDR_SIZE, true}, /* Bootloader RAM */ - {RV_PHYS, RV_SIZE, false}, /* Reset vector */ -}; - -/* - * struct mem_layout - layout of a piece of the system RAM - * @phys: Physical address of the start of this piece of RAM. This is the - * address at which both the processor and I/O devices see the - * RAM. - * @alias: Alias of this piece of memory in order to make it appear in - * the low memory part of the processor's address space. I/O - * devices don't see anything here. - * @size: Size, in bytes, of this piece of RAM - */ -struct mem_layout { - phys_addr_t phys; - phys_addr_t alias; - phys_addr_t size; -}; - -/* - * struct mem_layout_list - list descriptor for layouts of system RAM pieces - * @family: Specifies the family being described - * @n: Number of &struct mem_layout elements - * @layout: Pointer to the list of &mem_layout structures - */ -struct mem_layout_list { - enum family_type family; - size_t n; - struct mem_layout *layout; -}; - -static struct mem_layout f1500_layout[] = { - {0x20000000, 0x10000000, MEBIBYTE(256)}, -}; - -static struct mem_layout f4500_layout[] = { - {0x40000000, 0x10000000, MEBIBYTE(256)}, - {0x20000000, 0x20000000, MEBIBYTE(32)}, -}; - -static struct mem_layout f8500_layout[] = { - {0x40000000, 0x10000000, MEBIBYTE(256)}, - {0x20000000, 0x20000000, MEBIBYTE(32)}, - {0x30000000, 0x30000000, MEBIBYTE(32)}, -}; - -static struct mem_layout fx600_layout[] = { - {0x20000000, 0x10000000, MEBIBYTE(256)}, - {0x60000000, 0x60000000, MEBIBYTE(128)}, -}; - -static struct mem_layout_list layout_list[] = { - {FAMILY_1500, ARRAY_SIZE(f1500_layout), f1500_layout}, - {FAMILY_1500VZE, ARRAY_SIZE(f1500_layout), f1500_layout}, - {FAMILY_1500VZF, ARRAY_SIZE(f1500_layout), f1500_layout}, - {FAMILY_4500, ARRAY_SIZE(f4500_layout), f4500_layout}, - {FAMILY_8500, ARRAY_SIZE(f8500_layout), f8500_layout}, - {FAMILY_8500RNG, ARRAY_SIZE(f8500_layout), f8500_layout}, - {FAMILY_4600, ARRAY_SIZE(fx600_layout), fx600_layout}, - {FAMILY_4600VZA, ARRAY_SIZE(fx600_layout), fx600_layout}, - {FAMILY_8600, ARRAY_SIZE(fx600_layout), fx600_layout}, - {FAMILY_8600VZB, ARRAY_SIZE(fx600_layout), fx600_layout}, -}; - -/* If we can't determine the layout, use this */ -static struct mem_layout default_layout[] = { - {0x20000000, 0x10000000, MEBIBYTE(128)}, -}; - -/** - * register_non_ram - register low memory not available for RAM usage - */ -static __init void register_non_ram(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(low_mem_reserved); i++) - add_memory_region(low_mem_reserved[i].start, - low_mem_reserved[i].size, BOOT_MEM_RESERVED); -} - -/** - * get_memsize - get the size of memory as a single bank - */ -static phys_addr_t get_memsize(void) -{ - static char cmdline[COMMAND_LINE_SIZE] __initdata; - phys_addr_t memsize = 0; - char *memsize_str; - char *ptr; - - /* Check the command line first for a memsize directive */ - strcpy(cmdline, arcs_cmdline); - ptr = strstr(cmdline, "memsize="); - if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) - ptr = strstr(ptr, " memsize="); - - if (ptr) { - memsize = memparse(ptr + 8, &ptr); - } else { - /* otherwise look in the environment */ - memsize_str = prom_getenv("memsize"); - - if (memsize_str != NULL) { - pr_info("prom memsize = %s\n", memsize_str); - memsize = simple_strtol(memsize_str, NULL, 0); - } - - if (memsize == 0) { - if (_prom_memsize != 0) { - memsize = _prom_memsize; - pr_info("_prom_memsize = 0x%x\n", memsize); - /* add in memory that the bootloader doesn't - * report */ - memsize += BLDR_SIZE; - } else { - memsize = DEFAULT_MEMSIZE; - pr_info("Memsize not passed by bootloader, " - "defaulting to 0x%x\n", memsize); - } - } - } - - return memsize; -} - -/** - * register_low_ram - register an aliased section of RAM - * @p: Alias address of memory - * @n: Number of bytes in this section of memory - * - * Returns the number of bytes registered - * - */ -static __init phys_addr_t register_low_ram(phys_addr_t p, phys_addr_t n) -{ - phys_addr_t s; - int i; - phys_addr_t orig_n; - - orig_n = n; - - BUG_ON(p + n > RV_PHYS); - - for (i = 0; n != 0 && i < ARRAY_SIZE(low_mem_reserved); i++) { - phys_addr_t start; - phys_addr_t size; - - start = low_mem_reserved[i].start; - size = low_mem_reserved[i].size; - - /* Handle memory before this low memory section */ - if (p < start) { - phys_addr_t s; - s = min(n, start - p); - add_memory_region(p, s, BOOT_MEM_RAM); - p += s; - n -= s; - } - - /* Handle the low memory section itself. If it's aliased, - * we reduce the number of byes left, but if not, the RAM - * is available elsewhere and we don't reduce the number of - * bytes remaining. */ - if (p == start) { - if (low_mem_reserved[i].is_aliased) { - s = min(n, size); - n -= s; - p += s; - } else - p += n; - } - } - - return orig_n - n; -} - -/* - * register_ram - register real RAM - * @p: Address of memory as seen by devices - * @alias: If the memory is seen at an additional address by the processor, - * this will be the address, otherwise it is the same as @p. - * @n: Number of bytes in this section of memory - */ -static __init void register_ram(phys_addr_t p, phys_addr_t alias, - phys_addr_t n) -{ - /* - * If some or all of this memory has an alias, break it into the - * aliased and non-aliased portion. - */ - if (p != alias) { - phys_addr_t alias_size; - phys_addr_t registered; - - alias_size = min(n, LOW_RAM_END - alias); - registered = register_low_ram(alias, alias_size); - ioremap_add_map(alias, p, n); - n -= registered; - p += registered; - } - -#ifdef CONFIG_HIGHMEM - if (n != 0) { - add_memory_region(p, n, BOOT_MEM_RAM); - ioremap_add_map(p, p, n); - } -#endif -} - -/** - * register_address_space - register things in the address space - * @memsize: Number of bytes of RAM installed - * - * Takes the given number of bytes of RAM and registers as many of the regions, - * or partial regions, as it can. So, the default configuration might have - * two regions with 256 MiB each. If the memsize passed in on the command line - * is 384 MiB, it will register the first region with 256 MiB and the second - * with 128 MiB. - */ -static __init void register_address_space(phys_addr_t memsize) -{ - int i; - phys_addr_t size; - size_t n; - struct mem_layout *layout; - enum family_type family; - - /* - * Register all of the things that aren't available to the kernel as - * memory. - */ - register_non_ram(); - - /* Find the appropriate memory description */ - family = platform_get_family(); - - for (i = 0; i < ARRAY_SIZE(layout_list); i++) { - if (layout_list[i].family == family) - break; - } - - if (i == ARRAY_SIZE(layout_list)) { - n = ARRAY_SIZE(default_layout); - layout = default_layout; - } else { - n = layout_list[i].n; - layout = layout_list[i].layout; - } - - for (i = 0; memsize != 0 && i < n; i++) { - size = min(memsize, layout[i].size); - register_ram(layout[i].phys, layout[i].alias, size); - memsize -= size; - } -} - -void __init prom_meminit(void) -{ - ptv_memsize = get_memsize(); - register_address_space(ptv_memsize); -} - -void __init prom_free_prom_memory(void) -{ - unsigned long addr; - int i; - - for (i = 0; i < boot_mem_map.nr_map; i++) { - if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) - continue; - - addr = boot_mem_map.map[i].addr; - free_init_pages("prom memory", - addr, addr + boot_mem_map.map[i].size); - } -} diff --git a/arch/mips/powertv/pci/Makefile b/arch/mips/powertv/pci/Makefile deleted file mode 100644 index 2610a6af5b2c..000000000000 --- a/arch/mips/powertv/pci/Makefile +++ /dev/null @@ -1,19 +0,0 @@ -# -# Copyright (C) 2009 Scientific-Atlanta, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -# - -obj-$(CONFIG_PCI) += fixup-powertv.o diff --git a/arch/mips/powertv/pci/fixup-powertv.c b/arch/mips/powertv/pci/fixup-powertv.c deleted file mode 100644 index d7ecbae64a6e..000000000000 --- a/arch/mips/powertv/pci/fixup-powertv.c +++ /dev/null @@ -1,37 +0,0 @@ -#include <linux/init.h> -#include <linux/export.h> -#include <linux/pci.h> -#include <asm/mach-powertv/interrupts.h> -#include "powertv-pci.h" - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - return asic_pcie_map_irq(dev, slot, pin); -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - -/* - * asic_pcie_map_irq - * - * Parameters: - * *dev - pointer to a pci_dev structure (not used) - * slot - slot number (not used) - * pin - pin number (not used) - * - * Return Value: - * Returns: IRQ number (always the PCI Express IRQ number) - * - * Description: - * asic_pcie_map_irq will return the IRQ number of the PCI Express interrupt. - * - */ -int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - return irq_pciexp; -} -EXPORT_SYMBOL(asic_pcie_map_irq); diff --git a/arch/mips/powertv/pci/powertv-pci.h b/arch/mips/powertv/pci/powertv-pci.h deleted file mode 100644 index 1b5886bbd759..000000000000 --- a/arch/mips/powertv/pci/powertv-pci.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * powertv-pci.c - * - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -/* - * Local definitions for the powertv PCI code - */ - -#ifndef _POWERTV_PCI_POWERTV_PCI_H_ -#define _POWERTV_PCI_POWERTV_PCI_H_ -extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); -extern int asic_pcie_init(void); -extern int asic_pcie_init(void); - -extern int log_level; -#endif diff --git a/arch/mips/powertv/powertv-clock.h b/arch/mips/powertv/powertv-clock.h deleted file mode 100644 index d94c54311485..000000000000 --- a/arch/mips/powertv/powertv-clock.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: David VomLehn - */ - -#ifndef _POWERTV_POWERTV_CLOCK_H -#define _POWERTV_POWERTV_CLOCK_H -extern int powertv_clockevent_init(void); -extern void powertv_clocksource_init(void); -extern unsigned int mips_get_pll_freq(void); -#endif diff --git a/arch/mips/powertv/powertv-usb.c b/arch/mips/powertv/powertv-usb.c deleted file mode 100644 index d845eace58e9..000000000000 --- a/arch/mips/powertv/powertv-usb.c +++ /dev/null @@ -1,404 +0,0 @@ -/* - * powertv-usb.c - * - * Description: ASIC-specific USB device setup and shutdown - * - * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: Ken Eppinett - * David Schleef <ds@schleef.org> - * - * NOTE: The bootloader allocates persistent memory at an address which is - * 16 MiB below the end of the highest address in KSEG0. All fixed - * address memory reservations must avoid this region. - */ - -#include <linux/kernel.h> -#include <linux/export.h> -#include <linux/ioport.h> -#include <linux/platform_device.h> -#include <asm/mach-powertv/asic.h> -#include <asm/mach-powertv/interrupts.h> - -/* misc_clk_ctl1 values */ -#define MCC1_30MHZ_POWERUP_SELECT (1 << 14) -#define MCC1_DIV9 (1 << 13) -#define MCC1_ETHMIPS_POWERUP_SELECT (1 << 11) -#define MCC1_USB_POWERUP_SELECT (1 << 1) -#define MCC1_CLOCK108_POWERUP_SELECT (1 << 0) - -/* Possible values for clock select */ -#define MCC1_USB_CLOCK_HIGH_Z (0 << 4) -#define MCC1_USB_CLOCK_48MHZ (1 << 4) -#define MCC1_USB_CLOCK_24MHZ (2 << 4) -#define MCC1_USB_CLOCK_6MHZ (3 << 4) - -#define MCC1_CONFIG (MCC1_30MHZ_POWERUP_SELECT | \ - MCC1_DIV9 | \ - MCC1_ETHMIPS_POWERUP_SELECT | \ - MCC1_USB_POWERUP_SELECT | \ - MCC1_CLOCK108_POWERUP_SELECT) - -/* misc_clk_ctl2 values */ -#define MCC2_GMII_GCLK_TO_PAD (1 << 31) -#define MCC2_ETHER125_0_CLOCK_SELECT (1 << 29) -#define MCC2_RMII_0_CLOCK_SELECT (1 << 28) -#define MCC2_GMII_TX0_CLOCK_SELECT (1 << 27) -#define MCC2_GMII_RX0_CLOCK_SELECT (1 << 26) -#define MCC2_ETHER125_1_CLOCK_SELECT (1 << 24) -#define MCC2_RMII_1_CLOCK_SELECT (1 << 23) -#define MCC2_GMII_TX1_CLOCK_SELECT (1 << 22) -#define MCC2_GMII_RX1_CLOCK_SELECT (1 << 21) -#define MCC2_ETHER125_2_CLOCK_SELECT (1 << 19) -#define MCC2_RMII_2_CLOCK_SELECT (1 << 18) -#define MCC2_GMII_TX2_CLOCK_SELECT (1 << 17) -#define MCC2_GMII_RX2_CLOCK_SELECT (1 << 16) - -#define ETHER_CLK_CONFIG (MCC2_GMII_GCLK_TO_PAD | \ - MCC2_ETHER125_0_CLOCK_SELECT | \ - MCC2_RMII_0_CLOCK_SELECT | \ - MCC2_GMII_TX0_CLOCK_SELECT | \ - MCC2_GMII_RX0_CLOCK_SELECT | \ - MCC2_ETHER125_1_CLOCK_SELECT | \ - MCC2_RMII_1_CLOCK_SELECT | \ - MCC2_GMII_TX1_CLOCK_SELECT | \ - MCC2_GMII_RX1_CLOCK_SELECT | \ - MCC2_ETHER125_2_CLOCK_SELECT | \ - MCC2_RMII_2_CLOCK_SELECT | \ - MCC2_GMII_TX2_CLOCK_SELECT | \ - MCC2_GMII_RX2_CLOCK_SELECT) - -/* misc_clk_ctl2 definitions for Gaia */ -#define FSX4A_REF_SELECT (1 << 16) -#define FSX4B_REF_SELECT (1 << 17) -#define FSX4C_REF_SELECT (1 << 18) -#define DDR_PLL_REF_SELECT (1 << 19) -#define MIPS_PLL_REF_SELECT (1 << 20) - -/* Definitions for the QAM frequency select register FS432X4A4_QAM_CTL */ -#define QAM_FS_SDIV_SHIFT 29 -#define QAM_FS_MD_SHIFT 24 -#define QAM_FS_MD_MASK 0x1f /* Cut down to 5 bits */ -#define QAM_FS_PE_SHIFT 8 - -#define QAM_FS_DISABLE_DIVIDE_BY_3 (1 << 5) -#define QAM_FS_ENABLE_PROGRAM (1 << 4) -#define QAM_FS_ENABLE_OUTPUT (1 << 3) -#define QAM_FS_SELECT_TEST_BYPASS (1 << 2) -#define QAM_FS_DISABLE_DIGITAL_STANDBY (1 << 1) -#define QAM_FS_CHOOSE_FS (1 << 0) - -/* Definitions for fs432x4a_ctl register */ -#define QAM_FS_NSDIV_54MHZ (1 << 2) - -/* Definitions for bcm1_usb2_ctl register */ -#define BCM1_USB2_CTL_BISTOK (1 << 11) -#define BCM1_USB2_CTL_PORT2_SHIFT_JK (1 << 7) -#define BCM1_USB2_CTL_PORT1_SHIFT_JK (1 << 6) -#define BCM1_USB2_CTL_PORT2_FAST_EDGE (1 << 5) -#define BCM1_USB2_CTL_PORT1_FAST_EDGE (1 << 4) -#define BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH (1 << 1) -#define BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH (1 << 0) - -/* Definitions for crt_spare register */ -#define CRT_SPARE_PORT2_SHIFT_JK (1 << 21) -#define CRT_SPARE_PORT1_SHIFT_JK (1 << 20) -#define CRT_SPARE_PORT2_FAST_EDGE (1 << 19) -#define CRT_SPARE_PORT1_FAST_EDGE (1 << 18) -#define CRT_SPARE_DIVIDE_BY_9_FROM_432 (1 << 17) -#define CRT_SPARE_USB_DIVIDE_BY_9 (1 << 16) - -/* Definitions for usb2_stbus_obc register */ -#define USB_STBUS_OBC_STORE32_LOAD32 0x3 - -/* Definitions for usb2_stbus_mess_size register */ -#define USB2_STBUS_MESS_SIZE_2 0x1 /* 2 packets */ - -/* Definitions for usb2_stbus_chunk_size register */ -#define USB2_STBUS_CHUNK_SIZE_2 0x1 /* 2 packets */ - -/* Definitions for usb2_strap register */ -#define USB2_STRAP_HFREQ_SELECT 0x1 - -/* - * USB Host Resource Definition - */ - -static struct resource ehci_resources[] = { - { - .parent = &asic_resource, - .start = 0, - .end = 0xff, - .flags = IORESOURCE_MEM, - }, - { - .start = irq_usbehci, - .end = irq_usbehci, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 ehci_dmamask = 0xffffffffULL; - -static struct platform_device ehci_device = { - .name = "powertv-ehci", - .id = 0, - .num_resources = 2, - .resource = ehci_resources, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = 0xffffffff, - }, -}; - -static struct resource ohci_resources[] = { - { - .parent = &asic_resource, - .start = 0, - .end = 0xff, - .flags = IORESOURCE_MEM, - }, - { - .start = irq_usbohci, - .end = irq_usbohci, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 ohci_dmamask = 0xffffffffULL; - -static struct platform_device ohci_device = { - .name = "powertv-ohci", - .id = 0, - .num_resources = 2, - .resource = ohci_resources, - .dev = { - .dma_mask = &ohci_dmamask, - .coherent_dma_mask = 0xffffffff, - }, -}; - -static unsigned usb_users; -static DEFINE_SPINLOCK(usb_regs_lock); - -/* - * - * fs_update - set frequency synthesizer for USB - * @pe_bits Phase tap setting - * @md_bits Coarse selector bus for algorithm of phase tap - * @sdiv_bits Output divider setting - * @disable_div_by_3 Either QAM_FS_DISABLE_DIVIDE_BY_3 or zero - * @standby Either QAM_FS_DISABLE_DIGITAL_STANDBY or zero - * - * QAM frequency selection code, which affects the frequency at which USB - * runs. The frequency is calculated as: - * 2^15 * ndiv * Fin - * Fout = ------------------------------------------------------------ - * (sdiv * (ipe * (1 + md/32) - (ipe - 2^15)*(1 + (md + 1)/32))) - * where: - * Fin 54 MHz - * ndiv QAM_FS_NSDIV_54MHZ ? 8 : 16 - * sdiv 1 << (sdiv_bits + 1) - * ipe Same as pe_bits - * md A five-bit, two's-complement integer (range [-16, 15]), which - * is the lower 5 bits of md_bits. - */ -static void fs_update(u32 pe_bits, int md_bits, u32 sdiv_bits, - u32 disable_div_by_3, u32 standby) -{ - u32 val; - - val = ((sdiv_bits << QAM_FS_SDIV_SHIFT) | - ((md_bits & QAM_FS_MD_MASK) << QAM_FS_MD_SHIFT) | - (pe_bits << QAM_FS_PE_SHIFT) | - QAM_FS_ENABLE_OUTPUT | - standby | - disable_div_by_3); - asic_write(val, fs432x4b4_usb_ctl); - asic_write(val | QAM_FS_ENABLE_PROGRAM, fs432x4b4_usb_ctl); - asic_write(val | QAM_FS_ENABLE_PROGRAM | QAM_FS_CHOOSE_FS, - fs432x4b4_usb_ctl); -} - -/* - * usb_eye_configure - for optimizing the shape USB eye waveform - * @set: Bits to set in the register - * @clear: Bits to clear in the register; each bit with a one will - * be set in the register, zero bits will not be modified - */ -static void usb_eye_configure(u32 set, u32 clear) -{ - u32 old; - - old = asic_read(crt_spare); - old |= set; - old &= ~clear; - asic_write(old, crt_spare); -} - -/* - * platform_configure_usb - usb configuration based on platform type. - */ -static void platform_configure_usb(void) -{ - u32 bcm1_usb2_ctl_value; - enum asic_type asic_type; - unsigned long flags; - - spin_lock_irqsave(&usb_regs_lock, flags); - usb_users++; - - if (usb_users != 1) { - spin_unlock_irqrestore(&usb_regs_lock, flags); - return; - } - - asic_type = platform_get_asic(); - - switch (asic_type) { - case ASIC_ZEUS: - fs_update(0x0000, -15, 0x02, 0, 0); - bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH | - BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH; - break; - - case ASIC_CRONUS: - case ASIC_CRONUSLITE: - usb_eye_configure(0, CRT_SPARE_USB_DIVIDE_BY_9); - fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3, - QAM_FS_DISABLE_DIGITAL_STANDBY); - bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH | - BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH; - break; - - case ASIC_CALLIOPE: - fs_update(0x0000, -15, 0x02, QAM_FS_DISABLE_DIVIDE_BY_3, - QAM_FS_DISABLE_DIGITAL_STANDBY); - - switch (platform_get_family()) { - case FAMILY_1500VZE: - break; - - case FAMILY_1500VZF: - usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK | - CRT_SPARE_PORT1_SHIFT_JK | - CRT_SPARE_PORT2_FAST_EDGE | - CRT_SPARE_PORT1_FAST_EDGE, 0); - break; - - default: - usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK | - CRT_SPARE_PORT1_SHIFT_JK, 0); - break; - } - - bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK | - BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH | - BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH; - break; - - case ASIC_GAIA: - fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3, - QAM_FS_DISABLE_DIGITAL_STANDBY); - bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK | - BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH | - BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH; - break; - - default: - pr_err("Unknown ASIC type: %d\n", asic_type); - bcm1_usb2_ctl_value = 0; - break; - } - - /* turn on USB power */ - asic_write(0, usb2_strap); - /* Enable all OHCI interrupts */ - asic_write(bcm1_usb2_ctl_value, usb2_control); - /* usb2_stbus_obc store32/load32 */ - asic_write(USB_STBUS_OBC_STORE32_LOAD32, usb2_stbus_obc); - /* usb2_stbus_mess_size 2 packets */ - asic_write(USB2_STBUS_MESS_SIZE_2, usb2_stbus_mess_size); - /* usb2_stbus_chunk_size 2 packets */ - asic_write(USB2_STBUS_CHUNK_SIZE_2, usb2_stbus_chunk_size); - spin_unlock_irqrestore(&usb_regs_lock, flags); -} - -static void platform_unconfigure_usb(void) -{ - unsigned long flags; - - spin_lock_irqsave(&usb_regs_lock, flags); - usb_users--; - if (usb_users == 0) - asic_write(USB2_STRAP_HFREQ_SELECT, usb2_strap); - spin_unlock_irqrestore(&usb_regs_lock, flags); -} - -/* - * Set up the USB EHCI interface - */ -void platform_configure_usb_ehci() -{ - platform_configure_usb(); -} -EXPORT_SYMBOL(platform_configure_usb_ehci); - -/* - * Set up the USB OHCI interface - */ -void platform_configure_usb_ohci() -{ - platform_configure_usb(); -} -EXPORT_SYMBOL(platform_configure_usb_ohci); - -/* - * Shut the USB EHCI interface down - */ -void platform_unconfigure_usb_ehci() -{ - platform_unconfigure_usb(); -} -EXPORT_SYMBOL(platform_unconfigure_usb_ehci); - -/* - * Shut the USB OHCI interface down - */ -void platform_unconfigure_usb_ohci() -{ - platform_unconfigure_usb(); -} -EXPORT_SYMBOL(platform_unconfigure_usb_ohci); - -/** - * platform_devices_init - sets up USB device resourse. - */ -int __init platform_usb_devices_init(struct platform_device **ehci_dev, - struct platform_device **ohci_dev) -{ - *ehci_dev = &ehci_device; - ehci_resources[0].start = asic_reg_phys_addr(ehci_hcapbase); - ehci_resources[0].end += ehci_resources[0].start; - - *ohci_dev = &ohci_device; - ohci_resources[0].start = asic_reg_phys_addr(ohci_hc_revision); - ohci_resources[0].end += ohci_resources[0].start; - - return 0; -} diff --git a/arch/mips/powertv/powertv_setup.c b/arch/mips/powertv/powertv_setup.c deleted file mode 100644 index 24689bff1039..000000000000 --- a/arch/mips/powertv/powertv_setup.c +++ /dev/null @@ -1,319 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * Portions copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#include <linux/init.h> -#include <linux/sched.h> -#include <linux/ioport.h> -#include <linux/pci.h> -#include <linux/screen_info.h> -#include <linux/notifier.h> -#include <linux/etherdevice.h> -#include <linux/if_ether.h> -#include <linux/ctype.h> -#include <linux/cpu.h> -#include <linux/time.h> - -#include <asm/bootinfo.h> -#include <asm/irq.h> -#include <asm/mips-boards/generic.h> -#include <asm/dma.h> -#include <asm/asm.h> -#include <asm/traps.h> -#include <asm/asm-offsets.h> -#include "reset.h" - -#define VAL(n) STR(n) - -/* - * Macros for loading addresses and storing registers: - * LONG_L_ Stringified version of LONG_L for use in asm() statement - * LONG_S_ Stringified version of LONG_S for use in asm() statement - * PTR_LA_ Stringified version of PTR_LA for use in asm() statement - * REG_SIZE Number of 8-bit bytes in a full width register - */ -#define LONG_L_ VAL(LONG_L) " " -#define LONG_S_ VAL(LONG_S) " " -#define PTR_LA_ VAL(PTR_LA) " " - -#ifdef CONFIG_64BIT -#warning TODO: 64-bit code needs to be verified -#define REG_SIZE "8" /* In bytes */ -#endif - -#ifdef CONFIG_32BIT -#define REG_SIZE "4" /* In bytes */ -#endif - -static void register_panic_notifier(void); -static int panic_handler(struct notifier_block *notifier_block, - unsigned long event, void *cause_string); - -const char *get_system_type(void) -{ - return "PowerTV"; -} - -void __init plat_mem_setup(void) -{ - panic_on_oops = 1; - register_panic_notifier(); - -#if 0 - mips_pcibios_init(); -#endif - mips_reboot_setup(); -} - -/* - * Install a panic notifier for platform-specific diagnostics - */ -static void register_panic_notifier() -{ - static struct notifier_block panic_notifier = { - .notifier_call = panic_handler, - .next = NULL, - .priority = INT_MAX - }; - atomic_notifier_chain_register(&panic_notifier_list, &panic_notifier); -} - -static int panic_handler(struct notifier_block *notifier_block, - unsigned long event, void *cause_string) -{ - struct pt_regs my_regs; - - /* Save all of the registers */ - { - unsigned long at, v0, v1; /* Must be on the stack */ - - /* Start by saving $at and v0 on the stack. We use $at - * ourselves, but it looks like the compiler may use v0 or v1 - * to load the address of the pt_regs structure. We'll come - * back later to store the registers in the pt_regs - * structure. */ - __asm__ __volatile__ ( - ".set noat\n" - LONG_S_ "$at, %[at]\n" - LONG_S_ "$2, %[v0]\n" - LONG_S_ "$3, %[v1]\n" - : - [at] "=m" (at), - [v0] "=m" (v0), - [v1] "=m" (v1) - : - : "at" - ); - - __asm__ __volatile__ ( - ".set noat\n" - "move $at, %[pt_regs]\n" - - /* Argument registers */ - LONG_S_ "$4, " VAL(PT_R4) "($at)\n" - LONG_S_ "$5, " VAL(PT_R5) "($at)\n" - LONG_S_ "$6, " VAL(PT_R6) "($at)\n" - LONG_S_ "$7, " VAL(PT_R7) "($at)\n" - - /* Temporary regs */ - LONG_S_ "$8, " VAL(PT_R8) "($at)\n" - LONG_S_ "$9, " VAL(PT_R9) "($at)\n" - LONG_S_ "$10, " VAL(PT_R10) "($at)\n" - LONG_S_ "$11, " VAL(PT_R11) "($at)\n" - LONG_S_ "$12, " VAL(PT_R12) "($at)\n" - LONG_S_ "$13, " VAL(PT_R13) "($at)\n" - LONG_S_ "$14, " VAL(PT_R14) "($at)\n" - LONG_S_ "$15, " VAL(PT_R15) "($at)\n" - - /* "Saved" registers */ - LONG_S_ "$16, " VAL(PT_R16) "($at)\n" - LONG_S_ "$17, " VAL(PT_R17) "($at)\n" - LONG_S_ "$18, " VAL(PT_R18) "($at)\n" - LONG_S_ "$19, " VAL(PT_R19) "($at)\n" - LONG_S_ "$20, " VAL(PT_R20) "($at)\n" - LONG_S_ "$21, " VAL(PT_R21) "($at)\n" - LONG_S_ "$22, " VAL(PT_R22) "($at)\n" - LONG_S_ "$23, " VAL(PT_R23) "($at)\n" - - /* Add'l temp regs */ - LONG_S_ "$24, " VAL(PT_R24) "($at)\n" - LONG_S_ "$25, " VAL(PT_R25) "($at)\n" - - /* Kernel temp regs */ - LONG_S_ "$26, " VAL(PT_R26) "($at)\n" - LONG_S_ "$27, " VAL(PT_R27) "($at)\n" - - /* Global pointer, stack pointer, frame pointer and - * return address */ - LONG_S_ "$gp, " VAL(PT_R28) "($at)\n" - LONG_S_ "$sp, " VAL(PT_R29) "($at)\n" - LONG_S_ "$fp, " VAL(PT_R30) "($at)\n" - LONG_S_ "$ra, " VAL(PT_R31) "($at)\n" - - /* Now we can get the $at and v0 registers back and - * store them */ - LONG_L_ "$8, %[at]\n" - LONG_S_ "$8, " VAL(PT_R1) "($at)\n" - LONG_L_ "$8, %[v0]\n" - LONG_S_ "$8, " VAL(PT_R2) "($at)\n" - LONG_L_ "$8, %[v1]\n" - LONG_S_ "$8, " VAL(PT_R3) "($at)\n" - : - : - [at] "m" (at), - [v0] "m" (v0), - [v1] "m" (v1), - [pt_regs] "r" (&my_regs) - : "at", "t0" - ); - - /* Set the current EPC value to be the current location in this - * function */ - __asm__ __volatile__ ( - ".set noat\n" - "1:\n" - PTR_LA_ "$at, 1b\n" - LONG_S_ "$at, %[cp0_epc]\n" - : - [cp0_epc] "=m" (my_regs.cp0_epc) - : - : "at" - ); - - my_regs.cp0_cause = read_c0_cause(); - my_regs.cp0_status = read_c0_status(); - } - - pr_crit("I'm feeling a bit sleepy. hmmmmm... perhaps a nap would... " - "zzzz... \n"); - - return NOTIFY_DONE; -} - -/* Information about the RF MAC address, if one was supplied on the - * command line. */ -static bool have_rfmac; -static u8 rfmac[ETH_ALEN]; - -static int rfmac_param(char *p) -{ - u8 *q; - bool is_high_nibble; - int c; - - /* Skip a leading "0x", if present */ - if (*p == '0' && *(p+1) == 'x') - p += 2; - - q = rfmac; - is_high_nibble = true; - - for (c = (unsigned char) *p++; - isxdigit(c) && q - rfmac < ETH_ALEN; - c = (unsigned char) *p++) { - int nibble; - - nibble = (isdigit(c) ? (c - '0') : - (isupper(c) ? c - 'A' + 10 : c - 'a' + 10)); - - if (is_high_nibble) - *q = nibble << 4; - else - *q++ |= nibble; - - is_high_nibble = !is_high_nibble; - } - - /* If we parsed all the way to the end of the parameter value and - * parsed all ETH_ALEN bytes, we have a usable RF MAC address */ - have_rfmac = (c == '\0' && q - rfmac == ETH_ALEN); - - return 0; -} - -early_param("rfmac", rfmac_param); - -/* - * Generate an Ethernet MAC address that has a good chance of being unique. - * @addr: Pointer to six-byte array containing the Ethernet address - * Generates an Ethernet MAC address that is highly likely to be unique for - * this particular system on a network with other systems of the same type. - * - * The problem we are solving is that, when eth_random_addr() is used to - * generate MAC addresses at startup, there isn't much entropy for the random - * number generator to use and the addresses it produces are fairly likely to - * be the same as those of other identical systems on the same local network. - * This is true even for relatively small numbers of systems (for the reason - * why, see the Wikipedia entry for "Birthday problem" at: - * http://en.wikipedia.org/wiki/Birthday_problem - * - * The good news is that we already have a MAC address known to be unique, the - * RF MAC address. The bad news is that this address is already in use on the - * RF interface. Worse, the obvious trick, taking the RF MAC address and - * turning on the locally managed bit, has already been used for other devices. - * Still, this does give us something to work with. - * - * The approach we take is: - * 1. If we can't get the RF MAC Address, just call eth_random_addr. - * 2. Use the 24-bit NIC-specific bits of the RF MAC address as the last 24 - * bits of the new address. This is very likely to be unique, except for - * the current box. - * 3. To avoid using addresses already on the current box, we set the top - * six bits of the address with a value different from any currently - * registered Scientific Atlanta organizationally unique identifyer - * (OUI). This avoids duplication with any addresses on the system that - * were generated from valid Scientific Atlanta-registered address by - * simply flipping the locally managed bit. - * 4. We aren't generating a multicast address, so we leave the multicast - * bit off. Since we aren't using a registered address, we have to set - * the locally managed bit. - * 5. We then randomly generate the remaining 16-bits. This does two - * things: - * a. It allows us to call this function for more than one device - * in this system - * b. It ensures that things will probably still work even if - * some device on the device network has a locally managed - * address that matches the top six bits from step 2. - */ -void platform_random_ether_addr(u8 addr[ETH_ALEN]) -{ - const int num_random_bytes = 2; - const unsigned char non_sciatl_oui_bits = 0xc0u; - const unsigned char mac_addr_locally_managed = (1 << 1); - - if (!have_rfmac) { - pr_warning("rfmac not available on command line; " - "generating random MAC address\n"); - eth_random_addr(addr); - } - - else { - int i; - - /* Set the first byte to something that won't match a Scientific - * Atlanta OUI, is locally managed, and isn't a multicast - * address */ - addr[0] = non_sciatl_oui_bits | mac_addr_locally_managed; - - /* Get some bytes of random address information */ - get_random_bytes(&addr[1], num_random_bytes); - - /* Copy over the NIC-specific bits of the RF MAC address */ - for (i = 1 + num_random_bytes; i < ETH_ALEN; i++) - addr[i] = rfmac[i]; - } -} diff --git a/arch/mips/powertv/reset.c b/arch/mips/powertv/reset.c deleted file mode 100644 index 0007652cb774..000000000000 --- a/arch/mips/powertv/reset.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * Portions copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#include <linux/pm.h> - -#include <linux/io.h> -#include <asm/reboot.h> /* Not included by linux/reboot.h */ - -#ifdef CONFIG_BOOTLOADER_DRIVER -#include <asm/mach-powertv/kbldr.h> -#endif - -#include <asm/mach-powertv/asic_regs.h> -#include "reset.h" - -static void mips_machine_restart(char *command) -{ -#ifdef CONFIG_BOOTLOADER_DRIVER - /* - * Call the bootloader's reset function to ensure - * that persistent data is flushed before hard reset - */ - kbldr_SetCauseAndReset(); -#else - writel(0x1, asic_reg_addr(watchdog)); -#endif -} - -void mips_reboot_setup(void) -{ - _machine_restart = mips_machine_restart; -} diff --git a/arch/mips/powertv/reset.h b/arch/mips/powertv/reset.h deleted file mode 100644 index 888fd09e2620..000000000000 --- a/arch/mips/powertv/reset.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Definitions from powertv reset.c file - * - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: David VomLehn - */ - -#ifndef _POWERTV_POWERTV_RESET_H -#define _POWERTV_POWERTV_RESET_H -extern void mips_reboot_setup(void); -#endif diff --git a/arch/mips/powertv/time.c b/arch/mips/powertv/time.c deleted file mode 100644 index f38b0d45eca9..000000000000 --- a/arch/mips/powertv/time.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * Portions copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Setting up the clock on the MIPS boards. - */ - -#include <linux/init.h> -#include <asm/mach-powertv/interrupts.h> -#include <asm/time.h> - -#include "powertv-clock.h" - -unsigned int get_c0_compare_int(void) -{ - return irq_mips_timer; -} - -void __init plat_time_init(void) -{ - powertv_clocksource_init(); -} diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig index 026e823d871d..424f03496d14 100644 --- a/arch/mips/ralink/Kconfig +++ b/arch/mips/ralink/Kconfig @@ -1,5 +1,12 @@ if RALINK +config CLKEVT_RT3352 + bool + depends on SOC_RT305X || SOC_MT7620 + default y + select CLKSRC_OF + select CLKSRC_MMIO + choice prompt "Ralink SoC selection" default SOC_RT305X @@ -19,9 +26,12 @@ choice bool "RT3883" select USB_ARCH_HAS_OHCI select USB_ARCH_HAS_EHCI + select HW_HAS_PCI config SOC_MT7620 bool "MT7620" + select USB_ARCH_HAS_OHCI + select USB_ARCH_HAS_EHCI endchoice diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile index 38cf1a880aaa..98ae349827be 100644 --- a/arch/mips/ralink/Makefile +++ b/arch/mips/ralink/Makefile @@ -6,7 +6,9 @@ # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> # Copyright (C) 2013 John Crispin <blogic@openwrt.org> -obj-y := prom.o of.o reset.o clk.o irq.o +obj-y := prom.o of.o reset.o clk.o irq.o timer.o + +obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o obj-$(CONFIG_SOC_RT288X) += rt288x.o obj-$(CONFIG_SOC_RT305X) += rt305x.o diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform index cda4b6645c50..6d9c8c499f98 100644 --- a/arch/mips/ralink/Platform +++ b/arch/mips/ralink/Platform @@ -26,3 +26,4 @@ cflags-$(CONFIG_SOC_RT3883) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt # Ralink MT7620 # load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000 +cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620 diff --git a/arch/mips/ralink/cevt-rt3352.c b/arch/mips/ralink/cevt-rt3352.c new file mode 100644 index 000000000000..cc17566d1934 --- /dev/null +++ b/arch/mips/ralink/cevt-rt3352.c @@ -0,0 +1,145 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2013 by John Crispin <blogic@openwrt.org> + */ + +#include <linux/clockchips.h> +#include <linux/clocksource.h> +#include <linux/interrupt.h> +#include <linux/reset.h> +#include <linux/init.h> +#include <linux/time.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/of_address.h> + +#include <asm/mach-ralink/ralink_regs.h> + +#define SYSTICK_FREQ (50 * 1000) + +#define SYSTICK_CONFIG 0x00 +#define SYSTICK_COMPARE 0x04 +#define SYSTICK_COUNT 0x08 + +/* route systick irq to mips irq 7 instead of the r4k-timer */ +#define CFG_EXT_STK_EN 0x2 +/* enable the counter */ +#define CFG_CNT_EN 0x1 + +struct systick_device { + void __iomem *membase; + struct clock_event_device dev; + int irq_requested; + int freq_scale; +}; + +static void systick_set_clock_mode(enum clock_event_mode mode, + struct clock_event_device *evt); + +static int systick_next_event(unsigned long delta, + struct clock_event_device *evt) +{ + struct systick_device *sdev; + u32 count; + + sdev = container_of(evt, struct systick_device, dev); + count = ioread32(sdev->membase + SYSTICK_COUNT); + count = (count + delta) % SYSTICK_FREQ; + iowrite32(count + delta, sdev->membase + SYSTICK_COMPARE); + + return 0; +} + +static void systick_event_handler(struct clock_event_device *dev) +{ + /* noting to do here */ +} + +static irqreturn_t systick_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *dev = (struct clock_event_device *) dev_id; + + dev->event_handler(dev); + + return IRQ_HANDLED; +} + +static struct systick_device systick = { + .dev = { + /* + * cevt-r4k uses 300, make sure systick + * gets used if available + */ + .rating = 310, + .features = CLOCK_EVT_FEAT_ONESHOT, + .set_next_event = systick_next_event, + .set_mode = systick_set_clock_mode, + .event_handler = systick_event_handler, + }, +}; + +static struct irqaction systick_irqaction = { + .handler = systick_interrupt, + .flags = IRQF_PERCPU | IRQF_TIMER, + .dev_id = &systick.dev, +}; + +static void systick_set_clock_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + struct systick_device *sdev; + + sdev = container_of(evt, struct systick_device, dev); + + switch (mode) { + case CLOCK_EVT_MODE_ONESHOT: + if (!sdev->irq_requested) + setup_irq(systick.dev.irq, &systick_irqaction); + sdev->irq_requested = 1; + iowrite32(CFG_EXT_STK_EN | CFG_CNT_EN, + systick.membase + SYSTICK_CONFIG); + break; + + case CLOCK_EVT_MODE_SHUTDOWN: + if (sdev->irq_requested) + free_irq(systick.dev.irq, &systick_irqaction); + sdev->irq_requested = 0; + iowrite32(0, systick.membase + SYSTICK_CONFIG); + break; + + default: + pr_err("%s: Unhandeled mips clock_mode\n", systick.dev.name); + break; + } +} + +static void __init ralink_systick_init(struct device_node *np) +{ + systick.membase = of_iomap(np, 0); + if (!systick.membase) + return; + + systick_irqaction.name = np->name; + systick.dev.name = np->name; + clockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60); + systick.dev.max_delta_ns = clockevent_delta2ns(0x7fff, &systick.dev); + systick.dev.min_delta_ns = clockevent_delta2ns(0x3, &systick.dev); + systick.dev.irq = irq_of_parse_and_map(np, 0); + if (!systick.dev.irq) { + pr_err("%s: request_irq failed", np->name); + return; + } + + clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name, + SYSTICK_FREQ, 301, 16, clocksource_mmio_readl_up); + + clockevents_register_device(&systick.dev); + + pr_info("%s: runing - mult: %d, shift: %d\n", + np->name, systick.dev.mult, systick.dev.shift); +} + +CLOCKSOURCE_OF_DECLARE(systick, "ralink,cevt-systick", ralink_systick_init); diff --git a/arch/mips/ralink/clk.c b/arch/mips/ralink/clk.c index 8dfa22ff300b..5d0983d47161 100644 --- a/arch/mips/ralink/clk.c +++ b/arch/mips/ralink/clk.c @@ -26,7 +26,7 @@ void ralink_clk_add(const char *dev, unsigned long rate) struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); if (!clk) - panic("failed to add clock\n"); + panic("failed to add clock"); clk->cl.dev_id = dev; clk->cl.clk = clk; @@ -69,4 +69,5 @@ void __init plat_time_init(void) pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000); mips_hpt_frequency = clk_get_rate(clk) / 2; clk_put(clk); + clocksource_of_init(); } diff --git a/arch/mips/ralink/common.h b/arch/mips/ralink/common.h index 83144c3fc5ac..42dfd6100a2d 100644 --- a/arch/mips/ralink/common.h +++ b/arch/mips/ralink/common.h @@ -46,6 +46,8 @@ extern void ralink_of_remap(void); extern void ralink_clk_init(void); extern void ralink_clk_add(const char *dev, unsigned long rate); +extern void ralink_rst_init(void); + extern void prom_soc_init(struct ralink_soc_info *soc_info); __iomem void *plat_of_remap_node(const char *node); diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c index 0018b1a661f6..a3ad56c2372d 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -23,9 +23,6 @@ /* does the board have sdram or ddram */ static int dram_type; -/* the pll dividers */ -static u32 mt7620_clk_divider[] = { 2, 3, 4, 8 }; - static struct ralink_pinmux_grp mode_mux[] = { { .name = "i2c", @@ -140,34 +137,189 @@ struct ralink_pinmux rt_gpio_pinmux = { .uart_mask = MT7620_GPIO_MODE_UART0_MASK, }; -void __init ralink_clk_init(void) +static __init u32 +mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) { - unsigned long cpu_rate, sys_rate; - u32 c0 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0); - u32 c1 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1); - u32 swconfig = (c0 >> CPLL_SW_CONFIG_SHIFT) & CPLL_SW_CONFIG_MASK; - u32 cpu_clk = (c1 >> CPLL_CPU_CLK_SHIFT) & CPLL_CPU_CLK_MASK; - - if (cpu_clk) { - cpu_rate = 480000000; - } else if (!swconfig) { - cpu_rate = 600000000; - } else { - u32 m = (c0 >> CPLL_MULT_RATIO_SHIFT) & CPLL_MULT_RATIO; - u32 d = (c0 >> CPLL_DIV_RATIO_SHIFT) & CPLL_DIV_RATIO; + u64 t; - cpu_rate = ((40 * (m + 24)) / mt7620_clk_divider[d]) * 1000000; - } + t = ref_rate; + t *= mul; + do_div(t, div); + + return t; +} + +#define MHZ(x) ((x) * 1000 * 1000) + +static __init unsigned long +mt7620_get_xtal_rate(void) +{ + u32 reg; + + reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); + if (reg & SYSCFG0_XTAL_FREQ_SEL) + return MHZ(40); + + return MHZ(20); +} + +static __init unsigned long +mt7620_get_periph_rate(unsigned long xtal_rate) +{ + u32 reg; + + reg = rt_sysc_r32(SYSC_REG_CLKCFG0); + if (reg & CLKCFG0_PERI_CLK_SEL) + return xtal_rate; + + return MHZ(40); +} + +static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 }; + +static __init unsigned long +mt7620_get_cpu_pll_rate(unsigned long xtal_rate) +{ + u32 reg; + u32 mul; + u32 div; + + reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0); + if (reg & CPLL_CFG0_BYPASS_REF_CLK) + return xtal_rate; + + if ((reg & CPLL_CFG0_SW_CFG) == 0) + return MHZ(600); + + mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) & + CPLL_CFG0_PLL_MULT_RATIO_MASK; + mul += 24; + if (reg & CPLL_CFG0_LC_CURFCK) + mul *= 2; + + div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) & + CPLL_CFG0_PLL_DIV_RATIO_MASK; + + WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider)); + + return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]); +} + +static __init unsigned long +mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate) +{ + u32 reg; + + reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1); + if (reg & CPLL_CFG1_CPU_AUX1) + return xtal_rate; + + if (reg & CPLL_CFG1_CPU_AUX0) + return MHZ(480); + return cpu_pll_rate; +} + +static __init unsigned long +mt7620_get_cpu_rate(unsigned long pll_rate) +{ + u32 reg; + u32 mul; + u32 div; + + reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); + + mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK; + div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) & + CPU_SYS_CLKCFG_CPU_FDIV_MASK; + + return mt7620_calc_rate(pll_rate, mul, div); +} + +static const u32 mt7620_ocp_dividers[16] __initconst = { + [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2, + [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3, + [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4, + [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5, + [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10, +}; + +static __init unsigned long +mt7620_get_dram_rate(unsigned long pll_rate) +{ if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM) - sys_rate = cpu_rate / 4; - else - sys_rate = cpu_rate / 3; + return pll_rate / 4; + + return pll_rate / 3; +} + +static __init unsigned long +mt7620_get_sys_rate(unsigned long cpu_rate) +{ + u32 reg; + u32 ocp_ratio; + u32 div; + + reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); + + ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) & + CPU_SYS_CLKCFG_OCP_RATIO_MASK; + + if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers))) + return cpu_rate; + + div = mt7620_ocp_dividers[ocp_ratio]; + if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio)) + return cpu_rate; + + return cpu_rate / div; +} + +void __init ralink_clk_init(void) +{ + unsigned long xtal_rate; + unsigned long cpu_pll_rate; + unsigned long pll_rate; + unsigned long cpu_rate; + unsigned long sys_rate; + unsigned long dram_rate; + unsigned long periph_rate; + + xtal_rate = mt7620_get_xtal_rate(); + + cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate); + pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate); + + cpu_rate = mt7620_get_cpu_rate(pll_rate); + dram_rate = mt7620_get_dram_rate(pll_rate); + sys_rate = mt7620_get_sys_rate(cpu_rate); + periph_rate = mt7620_get_periph_rate(xtal_rate); + +#define RFMT(label) label ":%lu.%03luMHz " +#define RINT(x) ((x) / 1000000) +#define RFRAC(x) (((x) / 1000) % 1000) + + pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"), + RINT(xtal_rate), RFRAC(xtal_rate), + RINT(cpu_pll_rate), RFRAC(cpu_pll_rate), + RINT(pll_rate), RFRAC(pll_rate)); + + pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"), + RINT(cpu_rate), RFRAC(cpu_rate), + RINT(dram_rate), RFRAC(dram_rate), + RINT(sys_rate), RFRAC(sys_rate), + RINT(periph_rate), RFRAC(periph_rate)); + +#undef RFRAC +#undef RINT +#undef RFMT ralink_clk_add("cpu", cpu_rate); - ralink_clk_add("10000100.timer", 40000000); - ralink_clk_add("10000500.uart", 40000000); - ralink_clk_add("10000c00.uartlite", 40000000); + ralink_clk_add("10000100.timer", periph_rate); + ralink_clk_add("10000120.watchdog", periph_rate); + ralink_clk_add("10000500.uart", periph_rate); + ralink_clk_add("10000b00.spi", sys_rate); + ralink_clk_add("10000c00.uartlite", periph_rate); } void __init ralink_of_remap(void) @@ -198,7 +350,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info) name = "MT7620A"; soc_info->compatible = "ralink,mt7620a-soc"; } else { - panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1); + panic("mt7620: unknown SoC, n0:%08x n1:%08x", n0, n1); } rev = __raw_readl(sysc + SYSC_REG_CHIP_REV); @@ -214,16 +366,19 @@ void prom_soc_init(struct ralink_soc_info *soc_info) switch (dram_type) { case SYSCFG0_DRAM_TYPE_SDRAM: + pr_info("Board has SDRAM\n"); soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN; soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX; break; case SYSCFG0_DRAM_TYPE_DDR1: + pr_info("Board has DDR1\n"); soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN; soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX; break; case SYSCFG0_DRAM_TYPE_DDR2: + pr_info("Board has DDR2\n"); soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN; soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX; break; diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c index f25ea5b45051..eccc5526155e 100644 --- a/arch/mips/ralink/of.c +++ b/arch/mips/ralink/of.c @@ -21,6 +21,7 @@ #include <asm/reboot.h> #include <asm/bootinfo.h> #include <asm/addrspace.h> +#include <asm/prom.h> #include "common.h" @@ -108,7 +109,10 @@ static int __init plat_of_setup(void) strncpy(of_ids[1].compatible, "palmbus", len); if (of_platform_populate(NULL, of_ids, NULL, NULL)) - panic("failed to populate DT\n"); + panic("failed to populate DT"); + + /* make sure ithat the reset controller is setup early */ + ralink_rst_init(); return 0; } diff --git a/arch/mips/ralink/reset.c b/arch/mips/ralink/reset.c index 22120e512e7e..55c7ec59df3c 100644 --- a/arch/mips/ralink/reset.c +++ b/arch/mips/ralink/reset.c @@ -10,6 +10,8 @@ #include <linux/pm.h> #include <linux/io.h> +#include <linux/of.h> +#include <linux/reset-controller.h> #include <asm/reboot.h> @@ -19,6 +21,66 @@ #define SYSC_REG_RESET_CTRL 0x034 #define RSTCTL_RESET_SYSTEM BIT(0) +static int ralink_assert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + u32 val; + + if (id < 8) + return -1; + + val = rt_sysc_r32(SYSC_REG_RESET_CTRL); + val |= BIT(id); + rt_sysc_w32(val, SYSC_REG_RESET_CTRL); + + return 0; +} + +static int ralink_deassert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + u32 val; + + if (id < 8) + return -1; + + val = rt_sysc_r32(SYSC_REG_RESET_CTRL); + val &= ~BIT(id); + rt_sysc_w32(val, SYSC_REG_RESET_CTRL); + + return 0; +} + +static int ralink_reset_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + ralink_assert_device(rcdev, id); + return ralink_deassert_device(rcdev, id); +} + +static struct reset_control_ops reset_ops = { + .reset = ralink_reset_device, + .assert = ralink_assert_device, + .deassert = ralink_deassert_device, +}; + +static struct reset_controller_dev reset_dev = { + .ops = &reset_ops, + .owner = THIS_MODULE, + .nr_resets = 32, + .of_reset_n_cells = 1, +}; + +void ralink_rst_init(void) +{ + reset_dev.of_node = of_find_compatible_node(NULL, NULL, + "ralink,rt2880-reset"); + if (!reset_dev.of_node) + pr_err("Failed to find reset controller node"); + else + reset_controller_register(&reset_dev); +} + static void ralink_restart(char *command) { local_irq_disable(); diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c index ca7ee3a33790..bb82a82da9e7 100644 --- a/arch/mips/ralink/rt305x.c +++ b/arch/mips/ralink/rt305x.c @@ -276,7 +276,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info) name = "RT5350"; soc_info->compatible = "ralink,rt5350-soc"; } else { - panic("rt305x: unknown SoC, n0:%08x n1:%08x\n", n0, n1); + panic("rt305x: unknown SoC, n0:%08x n1:%08x", n0, n1); } id = __raw_readl(sysc + SYSC_REG_CHIP_ID); diff --git a/arch/mips/ralink/timer.c b/arch/mips/ralink/timer.c new file mode 100644 index 000000000000..202785709441 --- /dev/null +++ b/arch/mips/ralink/timer.c @@ -0,0 +1,185 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2013 John Crispin <blogic@openwrt.org> +*/ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/timer.h> +#include <linux/of_gpio.h> +#include <linux/clk.h> + +#include <asm/mach-ralink/ralink_regs.h> + +#define TIMER_REG_TMRSTAT 0x00 +#define TIMER_REG_TMR0LOAD 0x10 +#define TIMER_REG_TMR0CTL 0x18 + +#define TMRSTAT_TMR0INT BIT(0) + +#define TMR0CTL_ENABLE BIT(7) +#define TMR0CTL_MODE_PERIODIC BIT(4) +#define TMR0CTL_PRESCALER 1 +#define TMR0CTL_PRESCALE_VAL (0xf - TMR0CTL_PRESCALER) +#define TMR0CTL_PRESCALE_DIV (65536 / BIT(TMR0CTL_PRESCALER)) + +struct rt_timer { + struct device *dev; + void __iomem *membase; + int irq; + unsigned long timer_freq; + unsigned long timer_div; +}; + +static inline void rt_timer_w32(struct rt_timer *rt, u8 reg, u32 val) +{ + __raw_writel(val, rt->membase + reg); +} + +static inline u32 rt_timer_r32(struct rt_timer *rt, u8 reg) +{ + return __raw_readl(rt->membase + reg); +} + +static irqreturn_t rt_timer_irq(int irq, void *_rt) +{ + struct rt_timer *rt = (struct rt_timer *) _rt; + + rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div); + rt_timer_w32(rt, TIMER_REG_TMRSTAT, TMRSTAT_TMR0INT); + + return IRQ_HANDLED; +} + + +static int rt_timer_request(struct rt_timer *rt) +{ + int err = request_irq(rt->irq, rt_timer_irq, IRQF_DISABLED, + dev_name(rt->dev), rt); + if (err) { + dev_err(rt->dev, "failed to request irq\n"); + } else { + u32 t = TMR0CTL_MODE_PERIODIC | TMR0CTL_PRESCALE_VAL; + rt_timer_w32(rt, TIMER_REG_TMR0CTL, t); + } + return err; +} + +static void rt_timer_free(struct rt_timer *rt) +{ + free_irq(rt->irq, rt); +} + +static int rt_timer_config(struct rt_timer *rt, unsigned long divisor) +{ + if (rt->timer_freq < divisor) + rt->timer_div = rt->timer_freq; + else + rt->timer_div = divisor; + + rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div); + + return 0; +} + +static int rt_timer_enable(struct rt_timer *rt) +{ + u32 t; + + rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div); + + t = rt_timer_r32(rt, TIMER_REG_TMR0CTL); + t |= TMR0CTL_ENABLE; + rt_timer_w32(rt, TIMER_REG_TMR0CTL, t); + + return 0; +} + +static void rt_timer_disable(struct rt_timer *rt) +{ + u32 t; + + t = rt_timer_r32(rt, TIMER_REG_TMR0CTL); + t &= ~TMR0CTL_ENABLE; + rt_timer_w32(rt, TIMER_REG_TMR0CTL, t); +} + +static int rt_timer_probe(struct platform_device *pdev) +{ + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + struct rt_timer *rt; + struct clk *clk; + + rt = devm_kzalloc(&pdev->dev, sizeof(*rt), GFP_KERNEL); + if (!rt) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + return -ENOMEM; + } + + rt->irq = platform_get_irq(pdev, 0); + if (!rt->irq) { + dev_err(&pdev->dev, "failed to load irq\n"); + return -ENOENT; + } + + rt->membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(rt->membase)) + return PTR_ERR(rt->membase); + + clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "failed get clock rate\n"); + return PTR_ERR(clk); + } + + rt->timer_freq = clk_get_rate(clk) / TMR0CTL_PRESCALE_DIV; + if (!rt->timer_freq) + return -EINVAL; + + rt->dev = &pdev->dev; + platform_set_drvdata(pdev, rt); + + rt_timer_request(rt); + rt_timer_config(rt, 2); + rt_timer_enable(rt); + + dev_info(&pdev->dev, "maximum frequncy is %luHz\n", rt->timer_freq); + + return 0; +} + +static int rt_timer_remove(struct platform_device *pdev) +{ + struct rt_timer *rt = platform_get_drvdata(pdev); + + rt_timer_disable(rt); + rt_timer_free(rt); + + return 0; +} + +static const struct of_device_id rt_timer_match[] = { + { .compatible = "ralink,rt2880-timer" }, + {}, +}; +MODULE_DEVICE_TABLE(of, rt_timer_match); + +static struct platform_driver rt_timer_driver = { + .probe = rt_timer_probe, + .remove = rt_timer_remove, + .driver = { + .name = "rt-timer", + .owner = THIS_MODULE, + .of_match_table = rt_timer_match + }, +}; + +module_platform_driver(rt_timer_driver); + +MODULE_DESCRIPTION("Ralink RT2880 timer"); +MODULE_AUTHOR("John Crispin <blogic@openwrt.org"); +MODULE_LICENSE("GPL"); diff --git a/arch/mips/sibyte/bcm1480/setup.c b/arch/mips/sibyte/bcm1480/setup.c index 05ed92c92b69..8e2e04f77870 100644 --- a/arch/mips/sibyte/bcm1480/setup.c +++ b/arch/mips/sibyte/bcm1480/setup.c @@ -22,6 +22,7 @@ #include <linux/string.h> #include <asm/bootinfo.h> +#include <asm/cpu.h> #include <asm/mipsregs.h> #include <asm/io.h> #include <asm/sibyte/sb1250.h> @@ -119,7 +120,7 @@ void __init bcm1480_setup(void) uint64_t sys_rev; int plldiv; - sb1_pass = read_c0_prid() & 0xff; + sb1_pass = read_c0_prid() & PRID_REV_MASK; sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION)); soc_type = SYS_SOC_TYPE(sys_rev); part_type = G_SYS_PART(sys_rev); diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c index a14bd4cb0bc0..3c02b2a77ae9 100644 --- a/arch/mips/sibyte/sb1250/setup.c +++ b/arch/mips/sibyte/sb1250/setup.c @@ -22,6 +22,7 @@ #include <linux/string.h> #include <asm/bootinfo.h> +#include <asm/cpu.h> #include <asm/mipsregs.h> #include <asm/io.h> #include <asm/sibyte/sb1250.h> @@ -182,7 +183,7 @@ void __init sb1250_setup(void) int plldiv; int bad_config = 0; - sb1_pass = read_c0_prid() & 0xff; + sb1_pass = read_c0_prid() & PRID_REV_MASK; sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION)); soc_type = SYS_SOC_TYPE(sys_rev); soc_pass = G_SYS_REVISION(sys_rev); diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c index 5b09b3544edd..efad85c8c823 100644 --- a/arch/mips/sni/setup.c +++ b/arch/mips/sni/setup.c @@ -25,6 +25,7 @@ #endif #include <asm/bootinfo.h> +#include <asm/cpu.h> #include <asm/io.h> #include <asm/reboot.h> #include <asm/sni.h> @@ -173,7 +174,7 @@ void __init plat_mem_setup(void) system_type = "RM300-Cxx"; break; case SNI_BRD_PCI_DESKTOP: - switch (read_c0_prid() & 0xff00) { + switch (read_c0_prid() & PRID_IMP_MASK) { case PRID_IMP_R4600: case PRID_IMP_R4700: system_type = "RM200-C20"; diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c index 681e7f86c080..2b0b83c171e0 100644 --- a/arch/mips/txx9/generic/setup.c +++ b/arch/mips/txx9/generic/setup.c @@ -350,7 +350,7 @@ static void __init select_board(void) } /* select "default" board */ -#ifdef CONFIG_CPU_TX39XX +#ifdef CONFIG_TOSHIBA_JMR3927 txx9_board_vec = &jmr3927_vec; #endif #ifdef CONFIG_CPU_TX49XX |