diff options
Diffstat (limited to 'arch/mips/netlogic/xlp')
| -rw-r--r-- | arch/mips/netlogic/xlp/Makefile | 11 | ||||
| -rw-r--r-- | arch/mips/netlogic/xlp/ahci-init-xlp2.c | 390 | ||||
| -rw-r--r-- | arch/mips/netlogic/xlp/ahci-init.c | 209 | ||||
| -rw-r--r-- | arch/mips/netlogic/xlp/cop2-ex.c | 121 | ||||
| -rw-r--r-- | arch/mips/netlogic/xlp/dt.c | 95 | ||||
| -rw-r--r-- | arch/mips/netlogic/xlp/nlm_hal.c | 508 | ||||
| -rw-r--r-- | arch/mips/netlogic/xlp/setup.c | 174 | ||||
| -rw-r--r-- | arch/mips/netlogic/xlp/usb-init-xlp2.c | 288 | ||||
| -rw-r--r-- | arch/mips/netlogic/xlp/usb-init.c | 149 | ||||
| -rw-r--r-- | arch/mips/netlogic/xlp/wakeup.c | 212 |
10 files changed, 0 insertions, 2157 deletions
diff --git a/arch/mips/netlogic/xlp/Makefile b/arch/mips/netlogic/xlp/Makefile deleted file mode 100644 index d62465717393..000000000000 --- a/arch/mips/netlogic/xlp/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -obj-y += setup.o nlm_hal.o cop2-ex.o dt.o -obj-$(CONFIG_SMP) += wakeup.o -ifdef CONFIG_USB -obj-y += usb-init.o -obj-y += usb-init-xlp2.o -endif -ifdef CONFIG_SATA_AHCI -obj-y += ahci-init.o -obj-y += ahci-init-xlp2.o -endif diff --git a/arch/mips/netlogic/xlp/ahci-init-xlp2.c b/arch/mips/netlogic/xlp/ahci-init-xlp2.c deleted file mode 100644 index c11b9c7dc7c8..000000000000 --- a/arch/mips/netlogic/xlp/ahci-init-xlp2.c +++ /dev/null @@ -1,390 +0,0 @@ -/* - * Copyright (c) 2003-2014 Broadcom Corporation - * All Rights Reserved - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the Broadcom - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/dma-mapping.h> -#include <linux/kernel.h> -#include <linux/delay.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/irq.h> -#include <linux/bitops.h> -#include <linux/pci_ids.h> -#include <linux/nodemask.h> - -#include <asm/cpu.h> -#include <asm/mipsregs.h> - -#include <asm/netlogic/common.h> -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/mips-extns.h> -#include <asm/netlogic/xlp-hal/xlp.h> -#include <asm/netlogic/xlp-hal/iomap.h> - -#define SATA_CTL 0x0 -#define SATA_STATUS 0x1 /* Status Reg */ -#define SATA_INT 0x2 /* Interrupt Reg */ -#define SATA_INT_MASK 0x3 /* Interrupt Mask Reg */ -#define SATA_BIU_TIMEOUT 0x4 -#define AXIWRSPERRLOG 0x5 -#define AXIRDSPERRLOG 0x6 -#define BiuTimeoutLow 0x7 -#define BiuTimeoutHi 0x8 -#define BiuSlvErLow 0x9 -#define BiuSlvErHi 0xa -#define IO_CONFIG_SWAP_DIS 0xb -#define CR_REG_TIMER 0xc -#define CORE_ID 0xd -#define AXI_SLAVE_OPT1 0xe -#define PHY_MEM_ACCESS 0xf -#define PHY0_CNTRL 0x10 -#define PHY0_STAT 0x11 -#define PHY0_RX_ALIGN 0x12 -#define PHY0_RX_EQ_LO 0x13 -#define PHY0_RX_EQ_HI 0x14 -#define PHY0_BIST_LOOP 0x15 -#define PHY1_CNTRL 0x16 -#define PHY1_STAT 0x17 -#define PHY1_RX_ALIGN 0x18 -#define PHY1_RX_EQ_LO 0x19 -#define PHY1_RX_EQ_HI 0x1a -#define PHY1_BIST_LOOP 0x1b -#define RdExBase 0x1c -#define RdExLimit 0x1d -#define CacheAllocBase 0x1e -#define CacheAllocLimit 0x1f -#define BiuSlaveCmdGstNum 0x20 - -/*SATA_CTL Bits */ -#define SATA_RST_N BIT(0) /* Active low reset sata_core phy */ -#define SataCtlReserve0 BIT(1) -#define M_CSYSREQ BIT(2) /* AXI master low power, not used */ -#define S_CSYSREQ BIT(3) /* AXI slave low power, not used */ -#define P0_CP_DET BIT(8) /* Reserved, bring in from pad */ -#define P0_MP_SW BIT(9) /* Mech Switch */ -#define P0_DISABLE BIT(10) /* disable p0 */ -#define P0_ACT_LED_EN BIT(11) /* Active LED enable */ -#define P0_IRST_HARD_SYNTH BIT(12) /* PHY hard synth reset */ -#define P0_IRST_HARD_TXRX BIT(13) /* PHY lane hard reset */ -#define P0_IRST_POR BIT(14) /* PHY power on reset*/ -#define P0_IPDTXL BIT(15) /* PHY Tx lane dis/power down */ -#define P0_IPDRXL BIT(16) /* PHY Rx lane dis/power down */ -#define P0_IPDIPDMSYNTH BIT(17) /* PHY synthesizer dis/porwer down */ -#define P0_CP_POD_EN BIT(18) /* CP_POD enable */ -#define P0_AT_BYPASS BIT(19) /* P0 address translation by pass */ -#define P1_CP_DET BIT(20) /* Reserved,Cold Detect */ -#define P1_MP_SW BIT(21) /* Mech Switch */ -#define P1_DISABLE BIT(22) /* disable p1 */ -#define P1_ACT_LED_EN BIT(23) /* Active LED enable */ -#define P1_IRST_HARD_SYNTH BIT(24) /* PHY hard synth reset */ -#define P1_IRST_HARD_TXRX BIT(25) /* PHY lane hard reset */ -#define P1_IRST_POR BIT(26) /* PHY power on reset*/ -#define P1_IPDTXL BIT(27) /* PHY Tx lane dis/porwer down */ -#define P1_IPDRXL BIT(28) /* PHY Rx lane dis/porwer down */ -#define P1_IPDIPDMSYNTH BIT(29) /* PHY synthesizer dis/porwer down */ -#define P1_CP_POD_EN BIT(30) -#define P1_AT_BYPASS BIT(31) /* P1 address translation by pass */ - -/* Status register */ -#define M_CACTIVE BIT(0) /* m_cactive, not used */ -#define S_CACTIVE BIT(1) /* s_cactive, not used */ -#define P0_PHY_READY BIT(8) /* phy is ready */ -#define P0_CP_POD BIT(9) /* Cold PowerOn */ -#define P0_SLUMBER BIT(10) /* power mode slumber */ -#define P0_PATIAL BIT(11) /* power mode patial */ -#define P0_PHY_SIG_DET BIT(12) /* phy dignal detect */ -#define P0_PHY_CALI BIT(13) /* phy calibration done */ -#define P1_PHY_READY BIT(16) /* phy is ready */ -#define P1_CP_POD BIT(17) /* Cold PowerOn */ -#define P1_SLUMBER BIT(18) /* power mode slumber */ -#define P1_PATIAL BIT(19) /* power mode patial */ -#define P1_PHY_SIG_DET BIT(20) /* phy dignal detect */ -#define P1_PHY_CALI BIT(21) /* phy calibration done */ - -/* SATA CR_REG_TIMER bits */ -#define CR_TIME_SCALE (0x1000 << 0) - -/* SATA PHY specific registers start and end address */ -#define RXCDRCALFOSC0 0x0065 -#define CALDUTY 0x006e -#define RXDPIF 0x8065 -#define PPMDRIFTMAX_HI 0x80A4 - -#define nlm_read_sata_reg(b, r) nlm_read_reg(b, r) -#define nlm_write_sata_reg(b, r, v) nlm_write_reg(b, r, v) -#define nlm_get_sata_pcibase(node) \ - nlm_pcicfg_base(XLP9XX_IO_SATA_OFFSET(node)) -#define nlm_get_sata_regbase(node) \ - (nlm_get_sata_pcibase(node) + 0x100) - -/* SATA PHY config for register block 1 0x0065 .. 0x006e */ -static const u8 sata_phy_config1[] = { - 0xC9, 0xC9, 0x07, 0x07, 0x18, 0x18, 0x01, 0x01, 0x22, 0x00 -}; - -/* SATA PHY config for register block 2 0x8065 .. 0x80A4 */ -static const u8 sata_phy_config2[] = { - 0xAA, 0x00, 0x4C, 0xC9, 0xC9, 0x07, 0x07, 0x18, - 0x18, 0x05, 0x0C, 0x10, 0x00, 0x10, 0x00, 0xFF, - 0xCF, 0xF7, 0xE1, 0xF5, 0xFD, 0xFD, 0xFF, 0xFF, - 0xFF, 0xFF, 0xE3, 0xE7, 0xDB, 0xF5, 0xFD, 0xFD, - 0xF5, 0xF5, 0xFF, 0xFF, 0xE3, 0xE7, 0xDB, 0xF5, - 0xFD, 0xFD, 0xF5, 0xF5, 0xFF, 0xFF, 0xFF, 0xF5, - 0x3F, 0x00, 0x32, 0x00, 0x03, 0x01, 0x05, 0x05, - 0x04, 0x00, 0x00, 0x08, 0x04, 0x00, 0x00, 0x04, -}; - -const int sata_phy_debug = 0; /* set to verify PHY writes */ - -static void sata_clear_glue_reg(u64 regbase, u32 off, u32 bit) -{ - u32 reg_val; - - reg_val = nlm_read_sata_reg(regbase, off); - nlm_write_sata_reg(regbase, off, (reg_val & ~bit)); -} - -static void sata_set_glue_reg(u64 regbase, u32 off, u32 bit) -{ - u32 reg_val; - - reg_val = nlm_read_sata_reg(regbase, off); - nlm_write_sata_reg(regbase, off, (reg_val | bit)); -} - -static void write_phy_reg(u64 regbase, u32 addr, u32 physel, u8 data) -{ - nlm_write_sata_reg(regbase, PHY_MEM_ACCESS, - (1u << 31) | (physel << 24) | (data << 16) | addr); - udelay(850); -} - -static u8 read_phy_reg(u64 regbase, u32 addr, u32 physel) -{ - u32 val; - - nlm_write_sata_reg(regbase, PHY_MEM_ACCESS, - (0 << 31) | (physel << 24) | (0 << 16) | addr); - udelay(850); - val = nlm_read_sata_reg(regbase, PHY_MEM_ACCESS); - return (val >> 16) & 0xff; -} - -static void config_sata_phy(u64 regbase) -{ - u32 port, i, reg; - u8 val; - - for (port = 0; port < 2; port++) { - for (i = 0, reg = RXCDRCALFOSC0; reg <= CALDUTY; reg++, i++) - write_phy_reg(regbase, reg, port, sata_phy_config1[i]); - - for (i = 0, reg = RXDPIF; reg <= PPMDRIFTMAX_HI; reg++, i++) - write_phy_reg(regbase, reg, port, sata_phy_config2[i]); - - /* Fix for PHY link up failures at lower temperatures */ - write_phy_reg(regbase, 0x800F, port, 0x1f); - - val = read_phy_reg(regbase, 0x0029, port); - write_phy_reg(regbase, 0x0029, port, val | (0x7 << 1)); - - val = read_phy_reg(regbase, 0x0056, port); - write_phy_reg(regbase, 0x0056, port, val & ~(1 << 3)); - - val = read_phy_reg(regbase, 0x0018, port); - write_phy_reg(regbase, 0x0018, port, val & ~(0x7 << 0)); - } -} - -static void check_phy_register(u64 regbase, u32 addr, u32 physel, u8 xdata) -{ - u8 data; - - data = read_phy_reg(regbase, addr, physel); - pr_info("PHY read addr = 0x%x physel = %d data = 0x%x %s\n", - addr, physel, data, data == xdata ? "TRUE" : "FALSE"); -} - -static void verify_sata_phy_config(u64 regbase) -{ - u32 port, i, reg; - - for (port = 0; port < 2; port++) { - for (i = 0, reg = RXCDRCALFOSC0; reg <= CALDUTY; reg++, i++) - check_phy_register(regbase, reg, port, - sata_phy_config1[i]); - - for (i = 0, reg = RXDPIF; reg <= PPMDRIFTMAX_HI; reg++, i++) - check_phy_register(regbase, reg, port, - sata_phy_config2[i]); - } -} - -static void nlm_sata_firmware_init(int node) -{ - u32 reg_val; - u64 regbase; - int n; - - pr_info("Initializing XLP9XX On-chip AHCI...\n"); - regbase = nlm_get_sata_regbase(node); - - /* Reset port0 */ - sata_clear_glue_reg(regbase, SATA_CTL, P0_IRST_POR); - sata_clear_glue_reg(regbase, SATA_CTL, P0_IRST_HARD_TXRX); - sata_clear_glue_reg(regbase, SATA_CTL, P0_IRST_HARD_SYNTH); - sata_clear_glue_reg(regbase, SATA_CTL, P0_IPDTXL); - sata_clear_glue_reg(regbase, SATA_CTL, P0_IPDRXL); - sata_clear_glue_reg(regbase, SATA_CTL, P0_IPDIPDMSYNTH); - - /* port1 */ - sata_clear_glue_reg(regbase, SATA_CTL, P1_IRST_POR); - sata_clear_glue_reg(regbase, SATA_CTL, P1_IRST_HARD_TXRX); - sata_clear_glue_reg(regbase, SATA_CTL, P1_IRST_HARD_SYNTH); - sata_clear_glue_reg(regbase, SATA_CTL, P1_IPDTXL); - sata_clear_glue_reg(regbase, SATA_CTL, P1_IPDRXL); - sata_clear_glue_reg(regbase, SATA_CTL, P1_IPDIPDMSYNTH); - udelay(300); - - /* Set PHY */ - sata_set_glue_reg(regbase, SATA_CTL, P0_IPDTXL); - sata_set_glue_reg(regbase, SATA_CTL, P0_IPDRXL); - sata_set_glue_reg(regbase, SATA_CTL, P0_IPDIPDMSYNTH); - sata_set_glue_reg(regbase, SATA_CTL, P1_IPDTXL); - sata_set_glue_reg(regbase, SATA_CTL, P1_IPDRXL); - sata_set_glue_reg(regbase, SATA_CTL, P1_IPDIPDMSYNTH); - - udelay(1000); - sata_set_glue_reg(regbase, SATA_CTL, P0_IRST_POR); - udelay(1000); - sata_set_glue_reg(regbase, SATA_CTL, P1_IRST_POR); - udelay(1000); - - /* setup PHY */ - config_sata_phy(regbase); - if (sata_phy_debug) - verify_sata_phy_config(regbase); - - udelay(1000); - sata_set_glue_reg(regbase, SATA_CTL, P0_IRST_HARD_TXRX); - sata_set_glue_reg(regbase, SATA_CTL, P0_IRST_HARD_SYNTH); - sata_set_glue_reg(regbase, SATA_CTL, P1_IRST_HARD_TXRX); - sata_set_glue_reg(regbase, SATA_CTL, P1_IRST_HARD_SYNTH); - udelay(300); - - /* Override reset in serial PHY mode */ - sata_set_glue_reg(regbase, CR_REG_TIMER, CR_TIME_SCALE); - /* Set reset SATA */ - sata_set_glue_reg(regbase, SATA_CTL, SATA_RST_N); - sata_set_glue_reg(regbase, SATA_CTL, M_CSYSREQ); - sata_set_glue_reg(regbase, SATA_CTL, S_CSYSREQ); - - pr_debug("Waiting for PHYs to come up.\n"); - n = 10000; - do { - reg_val = nlm_read_sata_reg(regbase, SATA_STATUS); - if ((reg_val & P1_PHY_READY) && (reg_val & P0_PHY_READY)) - break; - udelay(10); - } while (--n > 0); - - if (reg_val & P0_PHY_READY) - pr_info("PHY0 is up.\n"); - else - pr_info("PHY0 is down.\n"); - if (reg_val & P1_PHY_READY) - pr_info("PHY1 is up.\n"); - else - pr_info("PHY1 is down.\n"); - - pr_info("XLP AHCI Init Done.\n"); -} - -static int __init nlm_ahci_init(void) -{ - int node; - - if (!cpu_is_xlp9xx()) - return 0; - for (node = 0; node < NLM_NR_NODES; node++) - if (nlm_node_present(node)) - nlm_sata_firmware_init(node); - return 0; -} - -static void nlm_sata_intr_ack(struct irq_data *data) -{ - u64 regbase; - u32 val; - int node; - - node = data->irq / NLM_IRQS_PER_NODE; - regbase = nlm_get_sata_regbase(node); - val = nlm_read_sata_reg(regbase, SATA_INT); - sata_set_glue_reg(regbase, SATA_INT, val); -} - -static void nlm_sata_fixup_bar(struct pci_dev *dev) -{ - dev->resource[5] = dev->resource[0]; - memset(&dev->resource[0], 0, sizeof(dev->resource[0])); -} - -static void nlm_sata_fixup_final(struct pci_dev *dev) -{ - u32 val; - u64 regbase; - int node; - - /* Find end bridge function to find node */ - node = xlp_socdev_to_node(dev); - regbase = nlm_get_sata_regbase(node); - - /* clear pending interrupts and then enable them */ - val = nlm_read_sata_reg(regbase, SATA_INT); - sata_set_glue_reg(regbase, SATA_INT, val); - - /* Enable only the core interrupt */ - sata_set_glue_reg(regbase, SATA_INT_MASK, 0x1); - - dev->irq = nlm_irq_to_xirq(node, PIC_SATA_IRQ); - nlm_set_pic_extra_ack(node, PIC_SATA_IRQ, nlm_sata_intr_ack); -} - -arch_initcall(nlm_ahci_init); - -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_XLP9XX_SATA, - nlm_sata_fixup_bar); - -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_XLP9XX_SATA, - nlm_sata_fixup_final); diff --git a/arch/mips/netlogic/xlp/ahci-init.c b/arch/mips/netlogic/xlp/ahci-init.c deleted file mode 100644 index 92be1a3258b1..000000000000 --- a/arch/mips/netlogic/xlp/ahci-init.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright (c) 2003-2014 Broadcom Corporation - * All Rights Reserved - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the Broadcom - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/dma-mapping.h> -#include <linux/kernel.h> -#include <linux/delay.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/irq.h> -#include <linux/bitops.h> - -#include <asm/cpu.h> -#include <asm/mipsregs.h> - -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/xlp-hal/xlp.h> -#include <asm/netlogic/common.h> -#include <asm/netlogic/xlp-hal/iomap.h> -#include <asm/netlogic/mips-extns.h> - -#define SATA_CTL 0x0 -#define SATA_STATUS 0x1 /* Status Reg */ -#define SATA_INT 0x2 /* Interrupt Reg */ -#define SATA_INT_MASK 0x3 /* Interrupt Mask Reg */ -#define SATA_CR_REG_TIMER 0x4 /* PHY Conrol Timer Reg */ -#define SATA_CORE_ID 0x5 /* Core ID Reg */ -#define SATA_AXI_SLAVE_OPT1 0x6 /* AXI Slave Options Reg */ -#define SATA_PHY_LOS_LEV 0x7 /* PHY LOS Level Reg */ -#define SATA_PHY_MULTI 0x8 /* PHY Multiplier Reg */ -#define SATA_PHY_CLK_SEL 0x9 /* Clock Select Reg */ -#define SATA_PHY_AMP1_GEN1 0xa /* PHY Transmit Amplitude Reg 1 */ -#define SATA_PHY_AMP1_GEN2 0xb /* PHY Transmit Amplitude Reg 2 */ -#define SATA_PHY_AMP1_GEN3 0xc /* PHY Transmit Amplitude Reg 3 */ -#define SATA_PHY_PRE1 0xd /* PHY Transmit Preemphasis Reg 1 */ -#define SATA_PHY_PRE2 0xe /* PHY Transmit Preemphasis Reg 2 */ -#define SATA_PHY_PRE3 0xf /* PHY Transmit Preemphasis Reg 3 */ -#define SATA_SPDMODE 0x10 /* Speed Mode Reg */ -#define SATA_REFCLK 0x11 /* Reference Clock Control Reg */ -#define SATA_BYTE_SWAP_DIS 0x12 /* byte swap disable */ - -/*SATA_CTL Bits */ -#define SATA_RST_N BIT(0) -#define PHY0_RESET_N BIT(16) -#define PHY1_RESET_N BIT(17) -#define PHY2_RESET_N BIT(18) -#define PHY3_RESET_N BIT(19) -#define M_CSYSREQ BIT(2) -#define S_CSYSREQ BIT(3) - -/*SATA_STATUS Bits */ -#define P0_PHY_READY BIT(4) -#define P1_PHY_READY BIT(5) -#define P2_PHY_READY BIT(6) -#define P3_PHY_READY BIT(7) - -#define nlm_read_sata_reg(b, r) nlm_read_reg(b, r) -#define nlm_write_sata_reg(b, r, v) nlm_write_reg(b, r, v) -#define nlm_get_sata_pcibase(node) \ - nlm_pcicfg_base(XLP_IO_SATA_OFFSET(node)) -/* SATA device specific configuration registers are starts at 0x900 offset */ -#define nlm_get_sata_regbase(node) \ - (nlm_get_sata_pcibase(node) + 0x900) - -static void sata_clear_glue_reg(uint64_t regbase, uint32_t off, uint32_t bit) -{ - uint32_t reg_val; - - reg_val = nlm_read_sata_reg(regbase, off); - nlm_write_sata_reg(regbase, off, (reg_val & ~bit)); -} - -static void sata_set_glue_reg(uint64_t regbase, uint32_t off, uint32_t bit) -{ - uint32_t reg_val; - - reg_val = nlm_read_sata_reg(regbase, off); - nlm_write_sata_reg(regbase, off, (reg_val | bit)); -} - -static void nlm_sata_firmware_init(int node) -{ - uint32_t reg_val; - uint64_t regbase; - int i; - - pr_info("XLP AHCI Initialization started.\n"); - regbase = nlm_get_sata_regbase(node); - - /* Reset SATA */ - sata_clear_glue_reg(regbase, SATA_CTL, SATA_RST_N); - /* Reset PHY */ - sata_clear_glue_reg(regbase, SATA_CTL, - (PHY3_RESET_N | PHY2_RESET_N - | PHY1_RESET_N | PHY0_RESET_N)); - - /* Set SATA */ - sata_set_glue_reg(regbase, SATA_CTL, SATA_RST_N); - /* Set PHY */ - sata_set_glue_reg(regbase, SATA_CTL, - (PHY3_RESET_N | PHY2_RESET_N - | PHY1_RESET_N | PHY0_RESET_N)); - - pr_debug("Waiting for PHYs to come up.\n"); - i = 0; - do { - reg_val = nlm_read_sata_reg(regbase, SATA_STATUS); - i++; - } while (((reg_val & 0xF0) != 0xF0) && (i < 10000)); - - for (i = 0; i < 4; i++) { - if (reg_val & (P0_PHY_READY << i)) - pr_info("PHY%d is up.\n", i); - else - pr_info("PHY%d is down.\n", i); - } - - pr_info("XLP AHCI init done.\n"); -} - -static int __init nlm_ahci_init(void) -{ - int node = 0; - int chip = read_c0_prid() & PRID_IMP_MASK; - - if (chip == PRID_IMP_NETLOGIC_XLP3XX) - nlm_sata_firmware_init(node); - return 0; -} - -static void nlm_sata_intr_ack(struct irq_data *data) -{ - uint32_t val = 0; - uint64_t regbase; - - regbase = nlm_get_sata_regbase(nlm_nodeid()); - val = nlm_read_sata_reg(regbase, SATA_INT); - sata_set_glue_reg(regbase, SATA_INT, val); -} - -static void nlm_sata_fixup_bar(struct pci_dev *dev) -{ - /* - * The AHCI resource is in BAR 0, move it to - * BAR 5, where it is expected - */ - dev->resource[5] = dev->resource[0]; - memset(&dev->resource[0], 0, sizeof(dev->resource[0])); -} - -static void nlm_sata_fixup_final(struct pci_dev *dev) -{ - uint32_t val; - uint64_t regbase; - int node = 0; /* XLP3XX does not support multi-node */ - - regbase = nlm_get_sata_regbase(node); - - /* clear pending interrupts and then enable them */ - val = nlm_read_sata_reg(regbase, SATA_INT); - sata_set_glue_reg(regbase, SATA_INT, val); - - /* Mask the core interrupt. If all the interrupts - * are enabled there are spurious interrupt flow - * happening, to avoid only enable core interrupt - * mask. - */ - sata_set_glue_reg(regbase, SATA_INT_MASK, 0x1); - - dev->irq = PIC_SATA_IRQ; - nlm_set_pic_extra_ack(node, PIC_SATA_IRQ, nlm_sata_intr_ack); -} - -arch_initcall(nlm_ahci_init); - -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_SATA, - nlm_sata_fixup_bar); -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_SATA, - nlm_sata_fixup_final); diff --git a/arch/mips/netlogic/xlp/cop2-ex.c b/arch/mips/netlogic/xlp/cop2-ex.c deleted file mode 100644 index 21e439b3db70..000000000000 --- a/arch/mips/netlogic/xlp/cop2-ex.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2013 Broadcom Corporation. - * - * based on arch/mips/cavium-octeon/cpu.c - * Copyright (C) 2009 Wind River Systems, - * written by Ralf Baechle <ralf@linux-mips.org> - */ -#include <linux/capability.h> -#include <linux/init.h> -#include <linux/irqflags.h> -#include <linux/notifier.h> -#include <linux/prefetch.h> -#include <linux/ptrace.h> -#include <linux/sched.h> -#include <linux/sched/task_stack.h> - -#include <asm/cop2.h> -#include <asm/current.h> -#include <asm/mipsregs.h> -#include <asm/page.h> - -#include <asm/netlogic/mips-extns.h> - -/* - * 64 bit ops are done in inline assembly to support 32 bit - * compilation - */ -void nlm_cop2_save(struct nlm_cop2_state *r) -{ - asm volatile( - ".set push\n" - ".set noat\n" - "dmfc2 $1, $0, 0\n" - "sd $1, 0(%1)\n" - "dmfc2 $1, $0, 1\n" - "sd $1, 8(%1)\n" - "dmfc2 $1, $0, 2\n" - "sd $1, 16(%1)\n" - "dmfc2 $1, $0, 3\n" - "sd $1, 24(%1)\n" - "dmfc2 $1, $1, 0\n" - "sd $1, 0(%2)\n" - "dmfc2 $1, $1, 1\n" - "sd $1, 8(%2)\n" - "dmfc2 $1, $1, 2\n" - "sd $1, 16(%2)\n" - "dmfc2 $1, $1, 3\n" - "sd $1, 24(%2)\n" - ".set pop\n" - : "=m"(*r) - : "r"(r->tx), "r"(r->rx)); - - r->tx_msg_status = __read_32bit_c2_register($2, 0); - r->rx_msg_status = __read_32bit_c2_register($3, 0) & 0x0fffffff; -} - -void nlm_cop2_restore(struct nlm_cop2_state *r) -{ - u32 rstat; - - asm volatile( - ".set push\n" - ".set noat\n" - "ld $1, 0(%1)\n" - "dmtc2 $1, $0, 0\n" - "ld $1, 8(%1)\n" - "dmtc2 $1, $0, 1\n" - "ld $1, 16(%1)\n" - "dmtc2 $1, $0, 2\n" - "ld $1, 24(%1)\n" - "dmtc2 $1, $0, 3\n" - "ld $1, 0(%2)\n" - "dmtc2 $1, $1, 0\n" - "ld $1, 8(%2)\n" - "dmtc2 $1, $1, 1\n" - "ld $1, 16(%2)\n" - "dmtc2 $1, $1, 2\n" - "ld $1, 24(%2)\n" - "dmtc2 $1, $1, 3\n" - ".set pop\n" - : : "m"(*r), "r"(r->tx), "r"(r->rx)); - - __write_32bit_c2_register($2, 0, r->tx_msg_status); - rstat = __read_32bit_c2_register($3, 0) & 0xf0000000u; - __write_32bit_c2_register($3, 0, r->rx_msg_status | rstat); -} - -static int nlm_cu2_call(struct notifier_block *nfb, unsigned long action, - void *data) -{ - unsigned long flags; - unsigned int status; - - switch (action) { - case CU2_EXCEPTION: - if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO)) - break; - local_irq_save(flags); - KSTK_STATUS(current) |= ST0_CU2; - status = read_c0_status(); - write_c0_status(status | ST0_CU2); - nlm_cop2_restore(&(current->thread.cp2)); - write_c0_status(status & ~ST0_CU2); - local_irq_restore(flags); - pr_info("COP2 access enabled for pid %d (%s)\n", - current->pid, current->comm); - return NOTIFY_BAD; /* Don't call default notifier */ - } - - return NOTIFY_OK; /* Let default notifier send signals */ -} - -static int __init nlm_cu2_setup(void) -{ - return cu2_notifier(nlm_cu2_call, 0); -} -early_initcall(nlm_cu2_setup); diff --git a/arch/mips/netlogic/xlp/dt.c b/arch/mips/netlogic/xlp/dt.c deleted file mode 100644 index c856f2a3ea42..000000000000 --- a/arch/mips/netlogic/xlp/dt.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2003-2013 Broadcom Corporation. - * All Rights Reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the Broadcom - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/kernel.h> -#include <linux/memblock.h> - -#include <linux/of_fdt.h> -#include <linux/of_platform.h> -#include <linux/of_device.h> - -#include <asm/prom.h> - -extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[], __dtb_xlp_fvp_begin[], - __dtb_xlp_gvp_begin[], __dtb_xlp_rvp_begin[]; -static void *xlp_fdt_blob; - -void __init *xlp_dt_init(void *fdtp) -{ - if (!fdtp) { - switch (current_cpu_data.processor_id & PRID_IMP_MASK) { -#ifdef CONFIG_DT_XLP_RVP - case PRID_IMP_NETLOGIC_XLP5XX: - fdtp = __dtb_xlp_rvp_begin; - break; -#endif -#ifdef CONFIG_DT_XLP_GVP - case PRID_IMP_NETLOGIC_XLP9XX: - fdtp = __dtb_xlp_gvp_begin; - break; -#endif -#ifdef CONFIG_DT_XLP_FVP - case PRID_IMP_NETLOGIC_XLP2XX: - fdtp = __dtb_xlp_fvp_begin; - break; -#endif -#ifdef CONFIG_DT_XLP_SVP - case PRID_IMP_NETLOGIC_XLP3XX: - fdtp = __dtb_xlp_svp_begin; - break; -#endif -#ifdef CONFIG_DT_XLP_EVP - case PRID_IMP_NETLOGIC_XLP8XX: - fdtp = __dtb_xlp_evp_begin; - break; -#endif - default: - /* Pick a built-in if any, and hope for the best */ - fdtp = __dtb_start; - break; - } - } - xlp_fdt_blob = fdtp; - return fdtp; -} - -void __init xlp_early_init_devtree(void) -{ - __dt_setup_arch(xlp_fdt_blob); -} - -void __init device_tree_init(void) -{ - unflatten_and_copy_device_tree(); -} diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c deleted file mode 100644 index 25ee69489e5e..000000000000 --- a/arch/mips/netlogic/xlp/nlm_hal.c +++ /dev/null @@ -1,508 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/mm.h> -#include <linux/delay.h> - -#include <asm/mipsregs.h> -#include <asm/time.h> - -#include <asm/netlogic/common.h> -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/xlp-hal/iomap.h> -#include <asm/netlogic/xlp-hal/xlp.h> -#include <asm/netlogic/xlp-hal/bridge.h> -#include <asm/netlogic/xlp-hal/pic.h> -#include <asm/netlogic/xlp-hal/sys.h> - -/* Main initialization */ -void nlm_node_init(int node) -{ - struct nlm_soc_info *nodep; - - nodep = nlm_get_node(node); - if (node == 0) - nodep->coremask = 1; /* node 0, boot cpu */ - nodep->sysbase = nlm_get_sys_regbase(node); - nodep->picbase = nlm_get_pic_regbase(node); - nodep->ebase = read_c0_ebase() & MIPS_EBASE_BASE; - if (cpu_is_xlp9xx()) - nodep->socbus = xlp9xx_get_socbus(node); - else - nodep->socbus = 0; - spin_lock_init(&nodep->piclock); -} - -static int xlp9xx_irq_to_irt(int irq) -{ - switch (irq) { - case PIC_GPIO_IRQ: - return 12; - case PIC_I2C_0_IRQ: - return 125; - case PIC_I2C_1_IRQ: - return 126; - case PIC_I2C_2_IRQ: - return 127; - case PIC_I2C_3_IRQ: - return 128; - case PIC_9XX_XHCI_0_IRQ: - return 114; - case PIC_9XX_XHCI_1_IRQ: - return 115; - case PIC_9XX_XHCI_2_IRQ: - return 116; - case PIC_UART_0_IRQ: - return 133; - case PIC_UART_1_IRQ: - return 134; - case PIC_SATA_IRQ: - return 143; - case PIC_NAND_IRQ: - return 151; - case PIC_SPI_IRQ: - return 152; - case PIC_MMC_IRQ: - return 153; - case PIC_PCIE_LINK_LEGACY_IRQ(0): - case PIC_PCIE_LINK_LEGACY_IRQ(1): - case PIC_PCIE_LINK_LEGACY_IRQ(2): - case PIC_PCIE_LINK_LEGACY_IRQ(3): - return 191 + irq - PIC_PCIE_LINK_LEGACY_IRQ_BASE; - } - return -1; -} - -static int xlp_irq_to_irt(int irq) -{ - uint64_t pcibase; - int devoff, irt; - - devoff = 0; - switch (irq) { - case PIC_UART_0_IRQ: - devoff = XLP_IO_UART0_OFFSET(0); - break; - case PIC_UART_1_IRQ: - devoff = XLP_IO_UART1_OFFSET(0); - break; - case PIC_MMC_IRQ: - devoff = XLP_IO_MMC_OFFSET(0); - break; - case PIC_I2C_0_IRQ: /* I2C will be fixed up */ - case PIC_I2C_1_IRQ: - case PIC_I2C_2_IRQ: - case PIC_I2C_3_IRQ: - if (cpu_is_xlpii()) - devoff = XLP2XX_IO_I2C_OFFSET(0); - else - devoff = XLP_IO_I2C0_OFFSET(0); - break; - case PIC_SATA_IRQ: - devoff = XLP_IO_SATA_OFFSET(0); - break; - case PIC_GPIO_IRQ: - devoff = XLP_IO_GPIO_OFFSET(0); - break; - case PIC_NAND_IRQ: - devoff = XLP_IO_NAND_OFFSET(0); - break; - case PIC_SPI_IRQ: - devoff = XLP_IO_SPI_OFFSET(0); - break; - default: - if (cpu_is_xlpii()) { - switch (irq) { - /* XLP2XX has three XHCI USB controller */ - case PIC_2XX_XHCI_0_IRQ: - devoff = XLP2XX_IO_USB_XHCI0_OFFSET(0); - break; - case PIC_2XX_XHCI_1_IRQ: - devoff = XLP2XX_IO_USB_XHCI1_OFFSET(0); - break; - case PIC_2XX_XHCI_2_IRQ: - devoff = XLP2XX_IO_USB_XHCI2_OFFSET(0); - break; - } - } else { - switch (irq) { - case PIC_EHCI_0_IRQ: - devoff = XLP_IO_USB_EHCI0_OFFSET(0); - break; - case PIC_EHCI_1_IRQ: - devoff = XLP_IO_USB_EHCI1_OFFSET(0); - break; - case PIC_OHCI_0_IRQ: - devoff = XLP_IO_USB_OHCI0_OFFSET(0); - break; - case PIC_OHCI_1_IRQ: - devoff = XLP_IO_USB_OHCI1_OFFSET(0); - break; - case PIC_OHCI_2_IRQ: - devoff = XLP_IO_USB_OHCI2_OFFSET(0); - break; - case PIC_OHCI_3_IRQ: - devoff = XLP_IO_USB_OHCI3_OFFSET(0); - break; - } - } - } - - if (devoff != 0) { - uint32_t val; - - pcibase = nlm_pcicfg_base(devoff); - val = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG); - if (val == 0xffffffff) { - irt = -1; - } else { - irt = val & 0xffff; - /* HW weirdness, I2C IRT entry has to be fixed up */ - switch (irq) { - case PIC_I2C_1_IRQ: - irt = irt + 1; break; - case PIC_I2C_2_IRQ: - irt = irt + 2; break; - case PIC_I2C_3_IRQ: - irt = irt + 3; break; - } - } - } else if (irq >= PIC_PCIE_LINK_LEGACY_IRQ(0) && - irq <= PIC_PCIE_LINK_LEGACY_IRQ(3)) { - /* HW bug, PCI IRT entries are bad on early silicon, fix */ - irt = PIC_IRT_PCIE_LINK_INDEX(irq - - PIC_PCIE_LINK_LEGACY_IRQ_BASE); - } else { - irt = -1; - } - return irt; -} - -int nlm_irq_to_irt(int irq) -{ - /* return -2 for irqs without 1-1 mapping */ - if (irq >= PIC_PCIE_LINK_MSI_IRQ(0) && irq <= PIC_PCIE_LINK_MSI_IRQ(3)) - return -2; - if (irq >= PIC_PCIE_MSIX_IRQ(0) && irq <= PIC_PCIE_MSIX_IRQ(3)) - return -2; - - if (cpu_is_xlp9xx()) - return xlp9xx_irq_to_irt(irq); - else - return xlp_irq_to_irt(irq); -} - -static unsigned int nlm_xlp2_get_core_frequency(int node, int core) -{ - unsigned int pll_post_div, ctrl_val0, ctrl_val1, denom; - uint64_t num, sysbase, clockbase; - - if (cpu_is_xlp9xx()) { - clockbase = nlm_get_clock_regbase(node); - ctrl_val0 = nlm_read_sys_reg(clockbase, - SYS_9XX_CPU_PLL_CTRL0(core)); - ctrl_val1 = nlm_read_sys_reg(clockbase, - SYS_9XX_CPU_PLL_CTRL1(core)); - } else { - sysbase = nlm_get_node(node)->sysbase; - ctrl_val0 = nlm_read_sys_reg(sysbase, - SYS_CPU_PLL_CTRL0(core)); - ctrl_val1 = nlm_read_sys_reg(sysbase, - SYS_CPU_PLL_CTRL1(core)); - } - - /* Find PLL post divider value */ - switch ((ctrl_val0 >> 24) & 0x7) { - case 1: - pll_post_div = 2; - break; - case 3: - pll_post_div = 4; - break; - case 7: - pll_post_div = 8; - break; - case 6: - pll_post_div = 16; - break; - case 0: - default: - pll_post_div = 1; - break; - } - - num = 1000000ULL * (400 * 3 + 100 * (ctrl_val1 & 0x3f)); - denom = 3 * pll_post_div; - do_div(num, denom); - - return (unsigned int)num; -} - -static unsigned int nlm_xlp_get_core_frequency(int node, int core) -{ - unsigned int pll_divf, pll_divr, dfs_div, ext_div; - unsigned int rstval, dfsval, denom; - uint64_t num, sysbase; - - sysbase = nlm_get_node(node)->sysbase; - rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG); - dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE); - pll_divf = ((rstval >> 10) & 0x7f) + 1; - pll_divr = ((rstval >> 8) & 0x3) + 1; - ext_div = ((rstval >> 30) & 0x3) + 1; - dfs_div = ((dfsval >> (core * 4)) & 0xf) + 1; - - num = 800000000ULL * pll_divf; - denom = 3 * pll_divr * ext_div * dfs_div; - do_div(num, denom); - - return (unsigned int)num; -} - -unsigned int nlm_get_core_frequency(int node, int core) -{ - if (cpu_is_xlpii()) - return nlm_xlp2_get_core_frequency(node, core); - else - return nlm_xlp_get_core_frequency(node, core); -} - -/* - * Calculate PIC frequency from PLL registers. - * freq_out = (ref_freq/2 * (6 + ctrl2[7:0]) + ctrl2[20:8]/2^13) / - * ((2^ctrl0[7:5]) * Table(ctrl0[26:24])) - */ -static unsigned int nlm_xlp2_get_pic_frequency(int node) -{ - u32 ctrl_val0, ctrl_val2, vco_post_div, pll_post_div, cpu_xlp9xx; - u32 mdiv, fdiv, pll_out_freq_den, reg_select, ref_div, pic_div; - u64 sysbase, pll_out_freq_num, ref_clk_select, clockbase, ref_clk; - - sysbase = nlm_get_node(node)->sysbase; - clockbase = nlm_get_clock_regbase(node); - cpu_xlp9xx = cpu_is_xlp9xx(); - - /* Find ref_clk_base */ - if (cpu_xlp9xx) - ref_clk_select = (nlm_read_sys_reg(sysbase, - SYS_9XX_POWER_ON_RESET_CFG) >> 18) & 0x3; - else - ref_clk_select = (nlm_read_sys_reg(sysbase, - SYS_POWER_ON_RESET_CFG) >> 18) & 0x3; - switch (ref_clk_select) { - case 0: - ref_clk = 200000000ULL; - ref_div = 3; - break; - case 1: - ref_clk = 100000000ULL; - ref_div = 1; - break; - case 2: - ref_clk = 125000000ULL; - ref_div = 1; - break; - case 3: - ref_clk = 400000000ULL; - ref_div = 3; - break; - } - - /* Find the clock source PLL device for PIC */ - if (cpu_xlp9xx) { - reg_select = nlm_read_sys_reg(clockbase, - SYS_9XX_CLK_DEV_SEL_REG) & 0x3; - switch (reg_select) { - case 0: - ctrl_val0 = nlm_read_sys_reg(clockbase, - SYS_9XX_PLL_CTRL0); - ctrl_val2 = nlm_read_sys_reg(clockbase, - SYS_9XX_PLL_CTRL2); - break; - case 1: - ctrl_val0 = nlm_read_sys_reg(clockbase, - SYS_9XX_PLL_CTRL0_DEVX(0)); - ctrl_val2 = nlm_read_sys_reg(clockbase, - SYS_9XX_PLL_CTRL2_DEVX(0)); - break; - case 2: - ctrl_val0 = nlm_read_sys_reg(clockbase, - SYS_9XX_PLL_CTRL0_DEVX(1)); - ctrl_val2 = nlm_read_sys_reg(clockbase, - SYS_9XX_PLL_CTRL2_DEVX(1)); - break; - case 3: - ctrl_val0 = nlm_read_sys_reg(clockbase, - SYS_9XX_PLL_CTRL0_DEVX(2)); - ctrl_val2 = nlm_read_sys_reg(clockbase, - SYS_9XX_PLL_CTRL2_DEVX(2)); - break; - } - } else { - reg_select = (nlm_read_sys_reg(sysbase, - SYS_CLK_DEV_SEL_REG) >> 22) & 0x3; - switch (reg_select) { - case 0: - ctrl_val0 = nlm_read_sys_reg(sysbase, - SYS_PLL_CTRL0); - ctrl_val2 = nlm_read_sys_reg(sysbase, - SYS_PLL_CTRL2); - break; - case 1: - ctrl_val0 = nlm_read_sys_reg(sysbase, - SYS_PLL_CTRL0_DEVX(0)); - ctrl_val2 = nlm_read_sys_reg(sysbase, - SYS_PLL_CTRL2_DEVX(0)); - break; - case 2: - ctrl_val0 = nlm_read_sys_reg(sysbase, - SYS_PLL_CTRL0_DEVX(1)); - ctrl_val2 = nlm_read_sys_reg(sysbase, - SYS_PLL_CTRL2_DEVX(1)); - break; - case 3: - ctrl_val0 = nlm_read_sys_reg(sysbase, - SYS_PLL_CTRL0_DEVX(2)); - ctrl_val2 = nlm_read_sys_reg(sysbase, - SYS_PLL_CTRL2_DEVX(2)); - break; - } - } - - vco_post_div = (ctrl_val0 >> 5) & 0x7; - pll_post_div = (ctrl_val0 >> 24) & 0x7; - mdiv = ctrl_val2 & 0xff; - fdiv = (ctrl_val2 >> 8) & 0x1fff; - - /* Find PLL post divider value */ - switch (pll_post_div) { - case 1: - pll_post_div = 2; - break; - case 3: - pll_post_div = 4; - break; - case 7: - pll_post_div = 8; - break; - case 6: - pll_post_div = 16; - break; - case 0: - default: - pll_post_div = 1; - break; - } - - fdiv = fdiv/(1 << 13); - pll_out_freq_num = ((ref_clk >> 1) * (6 + mdiv)) + fdiv; - pll_out_freq_den = (1 << vco_post_div) * pll_post_div * ref_div; - - if (pll_out_freq_den > 0) - do_div(pll_out_freq_num, pll_out_freq_den); - - /* PIC post divider, which happens after PLL */ - if (cpu_xlp9xx) - pic_div = nlm_read_sys_reg(clockbase, - SYS_9XX_CLK_DEV_DIV_REG) & 0x3; - else - pic_div = (nlm_read_sys_reg(sysbase, - SYS_CLK_DEV_DIV_REG) >> 22) & 0x3; - do_div(pll_out_freq_num, 1 << pic_div); - - return pll_out_freq_num; -} - -unsigned int nlm_get_pic_frequency(int node) -{ - if (cpu_is_xlpii()) - return nlm_xlp2_get_pic_frequency(node); - else - return 133333333; -} - -unsigned int nlm_get_cpu_frequency(void) -{ - return nlm_get_core_frequency(0, 0); -} - -/* - * Fills upto 8 pairs of entries containing the DRAM map of a node - * if node < 0, get dram map for all nodes - */ -int nlm_get_dram_map(int node, uint64_t *dram_map, int nentries) -{ - uint64_t bridgebase, base, lim; - uint32_t val; - unsigned int barreg, limreg, xlatreg; - int i, n, rv; - - /* Look only at mapping on Node 0, we don't handle crazy configs */ - bridgebase = nlm_get_bridge_regbase(0); - rv = 0; - for (i = 0; i < 8; i++) { - if (rv + 1 >= nentries) - break; - if (cpu_is_xlp9xx()) { - barreg = BRIDGE_9XX_DRAM_BAR(i); - limreg = BRIDGE_9XX_DRAM_LIMIT(i); - xlatreg = BRIDGE_9XX_DRAM_NODE_TRANSLN(i); - } else { - barreg = BRIDGE_DRAM_BAR(i); - limreg = BRIDGE_DRAM_LIMIT(i); - xlatreg = BRIDGE_DRAM_NODE_TRANSLN(i); - } - if (node >= 0) { - /* node specified, get node mapping of BAR */ - val = nlm_read_bridge_reg(bridgebase, xlatreg); - n = (val >> 1) & 0x3; - if (n != node) - continue; - } - val = nlm_read_bridge_reg(bridgebase, barreg); - val = (val >> 12) & 0xfffff; - base = (uint64_t) val << 20; - val = nlm_read_bridge_reg(bridgebase, limreg); - val = (val >> 12) & 0xfffff; - if (val == 0) /* BAR not used */ - continue; - lim = ((uint64_t)val + 1) << 20; - dram_map[rv] = base; - dram_map[rv + 1] = lim; - rv += 2; - } - return rv; -} diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c deleted file mode 100644 index 9fbaa1e5b340..000000000000 --- a/arch/mips/netlogic/xlp/setup.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/kernel.h> -#include <linux/of_fdt.h> -#include <linux/memblock.h> - -#include <asm/idle.h> -#include <asm/reboot.h> -#include <asm/time.h> -#include <asm/bootinfo.h> - -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/common.h> - -#include <asm/netlogic/xlp-hal/iomap.h> -#include <asm/netlogic/xlp-hal/xlp.h> -#include <asm/netlogic/xlp-hal/sys.h> - -uint64_t nlm_io_base; -struct nlm_soc_info nlm_nodes[NLM_NR_NODES]; -cpumask_t nlm_cpumask = CPU_MASK_CPU0; -unsigned int nlm_threads_per_core; - -static void nlm_linux_exit(void) -{ - uint64_t sysbase = nlm_get_node(0)->sysbase; - - if (cpu_is_xlp9xx()) - nlm_write_sys_reg(sysbase, SYS_9XX_CHIP_RESET, 1); - else - nlm_write_sys_reg(sysbase, SYS_CHIP_RESET, 1); - for ( ; ; ) - cpu_wait(); -} - -static void nlm_fixup_mem(void) -{ - const int pref_backup = 512; - struct memblock_region *mem; - - for_each_mem_region(mem) { - memblock_remove(mem->base + mem->size - pref_backup, - pref_backup); - } -} - -static void __init xlp_init_mem_from_bars(void) -{ - uint64_t map[16]; - int i, n; - - n = nlm_get_dram_map(-1, map, ARRAY_SIZE(map)); /* -1 : all nodes */ - for (i = 0; i < n; i += 2) { - /* exclude 0x1000_0000-0x2000_0000, u-boot device */ - if (map[i] <= 0x10000000 && map[i+1] > 0x10000000) - map[i+1] = 0x10000000; - if (map[i] > 0x10000000 && map[i] < 0x20000000) - map[i] = 0x20000000; - - memblock_add(map[i], map[i+1] - map[i]); - } -} - -void __init plat_mem_setup(void) -{ -#ifdef CONFIG_SMP - nlm_wakeup_secondary_cpus(); - - /* update TLB size after waking up threads */ - current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; - - register_smp_ops(&nlm_smp_ops); -#endif - _machine_restart = (void (*)(char *))nlm_linux_exit; - _machine_halt = nlm_linux_exit; - pm_power_off = nlm_linux_exit; - - /* memory and bootargs from DT */ - xlp_early_init_devtree(); - - if (memblock_end_of_DRAM() == 0) { - pr_info("Using DRAM BARs for memory map.\n"); - xlp_init_mem_from_bars(); - } - /* Calculate and setup wired entries for mapped kernel */ - nlm_fixup_mem(); -} - -const char *get_system_type(void) -{ - switch (read_c0_prid() & PRID_IMP_MASK) { - case PRID_IMP_NETLOGIC_XLP9XX: - case PRID_IMP_NETLOGIC_XLP5XX: - case PRID_IMP_NETLOGIC_XLP2XX: - return "Broadcom XLPII Series"; - default: - return "Netlogic XLP Series"; - } -} - -void xlp_mmu_init(void) -{ - u32 conf4; - - if (cpu_is_xlpii()) { - /* XLPII series has extended pagesize in config 4 */ - conf4 = read_c0_config4() & ~0x1f00u; - write_c0_config4(conf4 | ((PAGE_SHIFT - 10) / 2 << 8)); - } else { - /* enable extended TLB and Large Fixed TLB */ - write_c0_config6(read_c0_config6() | 0x24); - - /* set page mask of extended Fixed TLB in config7 */ - write_c0_config7(PM_DEFAULT_MASK >> - (13 + (ffz(PM_DEFAULT_MASK >> 13) / 2))); - } -} - -void nlm_percpu_init(int hwcpuid) -{ -} - -void __init prom_init(void) -{ - void *reset_vec; - - nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE); - nlm_init_boot_cpu(); - xlp_mmu_init(); - nlm_node_init(0); - xlp_dt_init((void *)(long)fw_arg0); - - /* Update reset entry point with CPU init code */ - reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS); - memset(reset_vec, 0, RESET_VEC_SIZE); - memcpy(reset_vec, (void *)nlm_reset_entry, - (nlm_reset_entry_end - nlm_reset_entry)); - -#ifdef CONFIG_SMP - cpumask_setall(&nlm_cpumask); -#endif -} diff --git a/arch/mips/netlogic/xlp/usb-init-xlp2.c b/arch/mips/netlogic/xlp/usb-init-xlp2.c deleted file mode 100644 index 2524939a5e3a..000000000000 --- a/arch/mips/netlogic/xlp/usb-init-xlp2.c +++ /dev/null @@ -1,288 +0,0 @@ -/* - * Copyright (c) 2003-2013 Broadcom Corporation - * All Rights Reserved - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the Broadcom - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/dma-mapping.h> -#include <linux/kernel.h> -#include <linux/delay.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/pci_ids.h> -#include <linux/platform_device.h> -#include <linux/irq.h> - -#include <asm/netlogic/common.h> -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/xlp-hal/iomap.h> -#include <asm/netlogic/xlp-hal/xlp.h> - -#define XLPII_USB3_CTL_0 0xc0 -#define XLPII_VAUXRST BIT(0) -#define XLPII_VCCRST BIT(1) -#define XLPII_NUM2PORT 9 -#define XLPII_NUM3PORT 13 -#define XLPII_RTUNEREQ BIT(20) -#define XLPII_MS_CSYSREQ BIT(21) -#define XLPII_XS_CSYSREQ BIT(22) -#define XLPII_RETENABLEN BIT(23) -#define XLPII_TX2RX BIT(24) -#define XLPII_XHCIREV BIT(25) -#define XLPII_ECCDIS BIT(26) - -#define XLPII_USB3_INT_REG 0xc2 -#define XLPII_USB3_INT_MASK 0xc3 - -#define XLPII_USB_PHY_TEST 0xc6 -#define XLPII_PRESET BIT(0) -#define XLPII_ATERESET BIT(1) -#define XLPII_LOOPEN BIT(2) -#define XLPII_TESTPDHSP BIT(3) -#define XLPII_TESTPDSSP BIT(4) -#define XLPII_TESTBURNIN BIT(5) - -#define XLPII_USB_PHY_LOS_LV 0xc9 -#define XLPII_LOSLEV 0 -#define XLPII_LOSBIAS 5 -#define XLPII_SQRXTX 8 -#define XLPII_TXBOOST 11 -#define XLPII_RSLKSEL 16 -#define XLPII_FSEL 20 - -#define XLPII_USB_RFCLK_REG 0xcc -#define XLPII_VVLD 30 - -#define nlm_read_usb_reg(b, r) nlm_read_reg(b, r) -#define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v) - -#define nlm_xlpii_get_usb_pcibase(node, inst) \ - nlm_pcicfg_base(cpu_is_xlp9xx() ? \ - XLP9XX_IO_USB_OFFSET(node, inst) : \ - XLP2XX_IO_USB_OFFSET(node, inst)) -#define nlm_xlpii_get_usb_regbase(node, inst) \ - (nlm_xlpii_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ) - -static void xlp2xx_usb_ack(struct irq_data *data) -{ - u64 port_addr; - - switch (data->irq) { - case PIC_2XX_XHCI_0_IRQ: - port_addr = nlm_xlpii_get_usb_regbase(0, 1); - break; - case PIC_2XX_XHCI_1_IRQ: - port_addr = nlm_xlpii_get_usb_regbase(0, 2); - break; - case PIC_2XX_XHCI_2_IRQ: - port_addr = nlm_xlpii_get_usb_regbase(0, 3); - break; - default: - pr_err("No matching USB irq!\n"); - return; - } - nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff); -} - -static void xlp9xx_usb_ack(struct irq_data *data) -{ - u64 port_addr; - int node, irq; - - /* Find the node and irq on the node */ - irq = data->irq % NLM_IRQS_PER_NODE; - node = data->irq / NLM_IRQS_PER_NODE; - - switch (irq) { - case PIC_9XX_XHCI_0_IRQ: - port_addr = nlm_xlpii_get_usb_regbase(node, 1); - break; - case PIC_9XX_XHCI_1_IRQ: - port_addr = nlm_xlpii_get_usb_regbase(node, 2); - break; - case PIC_9XX_XHCI_2_IRQ: - port_addr = nlm_xlpii_get_usb_regbase(node, 3); - break; - default: - pr_err("No matching USB irq %d node %d!\n", irq, node); - return; - } - nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff); -} - -static void nlm_xlpii_usb_hw_reset(int node, int port) -{ - u64 port_addr, xhci_base, pci_base; - void __iomem *corebase; - u32 val; - - port_addr = nlm_xlpii_get_usb_regbase(node, port); - - /* Set frequency */ - val = nlm_read_usb_reg(port_addr, XLPII_USB_PHY_LOS_LV); - val &= ~(0x3f << XLPII_FSEL); - val |= (0x27 << XLPII_FSEL); - nlm_write_usb_reg(port_addr, XLPII_USB_PHY_LOS_LV, val); - - val = nlm_read_usb_reg(port_addr, XLPII_USB_RFCLK_REG); - val |= (1 << XLPII_VVLD); - nlm_write_usb_reg(port_addr, XLPII_USB_RFCLK_REG, val); - - /* PHY reset */ - val = nlm_read_usb_reg(port_addr, XLPII_USB_PHY_TEST); - val &= (XLPII_ATERESET | XLPII_LOOPEN | XLPII_TESTPDHSP - | XLPII_TESTPDSSP | XLPII_TESTBURNIN); - nlm_write_usb_reg(port_addr, XLPII_USB_PHY_TEST, val); - - /* Setup control register */ - val = XLPII_VAUXRST | XLPII_VCCRST | (1 << XLPII_NUM2PORT) - | (1 << XLPII_NUM3PORT) | XLPII_MS_CSYSREQ | XLPII_XS_CSYSREQ - | XLPII_RETENABLEN | XLPII_XHCIREV; - nlm_write_usb_reg(port_addr, XLPII_USB3_CTL_0, val); - - /* Enable interrupts */ - nlm_write_usb_reg(port_addr, XLPII_USB3_INT_MASK, 0x00000001); - - /* Clear all interrupts */ - nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff); - - udelay(2000); - - /* XHCI configuration at PCI mem */ - pci_base = nlm_xlpii_get_usb_pcibase(node, port); - xhci_base = nlm_read_usb_reg(pci_base, 0x4) & ~0xf; - corebase = ioremap(xhci_base, 0x10000); - if (!corebase) - return; - - writel(0x240002, corebase + 0xc2c0); - /* GCTL 0xc110 */ - val = readl(corebase + 0xc110); - val &= ~(0x3 << 12); - val |= (1 << 12); - writel(val, corebase + 0xc110); - udelay(100); - - /* PHYCFG 0xc200 */ - val = readl(corebase + 0xc200); - val &= ~(1 << 6); - writel(val, corebase + 0xc200); - udelay(100); - - /* PIPECTL 0xc2c0 */ - val = readl(corebase + 0xc2c0); - val &= ~(1 << 17); - writel(val, corebase + 0xc2c0); - - iounmap(corebase); -} - -static int __init nlm_platform_xlpii_usb_init(void) -{ - int node; - - if (!cpu_is_xlpii()) - return 0; - - if (!cpu_is_xlp9xx()) { - /* XLP 2XX single node */ - pr_info("Initializing 2XX USB Interface\n"); - nlm_xlpii_usb_hw_reset(0, 1); - nlm_xlpii_usb_hw_reset(0, 2); - nlm_xlpii_usb_hw_reset(0, 3); - nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_0_IRQ, xlp2xx_usb_ack); - nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_1_IRQ, xlp2xx_usb_ack); - nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_2_IRQ, xlp2xx_usb_ack); - return 0; - } - - /* XLP 9XX, multi-node */ - pr_info("Initializing 9XX/5XX USB Interface\n"); - for (node = 0; node < NLM_NR_NODES; node++) { - if (!nlm_node_present(node)) - continue; - nlm_xlpii_usb_hw_reset(node, 1); - nlm_xlpii_usb_hw_reset(node, 2); - nlm_xlpii_usb_hw_reset(node, 3); - nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_0_IRQ, xlp9xx_usb_ack); - nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_1_IRQ, xlp9xx_usb_ack); - nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_2_IRQ, xlp9xx_usb_ack); - } - return 0; -} - -arch_initcall(nlm_platform_xlpii_usb_init); - -static u64 xlp_usb_dmamask = ~(u32)0; - -/* Fixup the IRQ for USB devices which is exist on XLP9XX SOC PCIE bus */ -static void nlm_xlp9xx_usb_fixup_final(struct pci_dev *dev) -{ - int node; - - node = xlp_socdev_to_node(dev); - dev->dev.dma_mask = &xlp_usb_dmamask; - dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); - switch (dev->devfn) { - case 0x21: - dev->irq = nlm_irq_to_xirq(node, PIC_9XX_XHCI_0_IRQ); - break; - case 0x22: - dev->irq = nlm_irq_to_xirq(node, PIC_9XX_XHCI_1_IRQ); - break; - case 0x23: - dev->irq = nlm_irq_to_xirq(node, PIC_9XX_XHCI_2_IRQ); - break; - } -} - -/* Fixup the IRQ for USB devices which is exist on XLP2XX SOC PCIE bus */ -static void nlm_xlp2xx_usb_fixup_final(struct pci_dev *dev) -{ - dev->dev.dma_mask = &xlp_usb_dmamask; - dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); - switch (dev->devfn) { - case 0x21: - dev->irq = PIC_2XX_XHCI_0_IRQ; - break; - case 0x22: - dev->irq = PIC_2XX_XHCI_1_IRQ; - break; - case 0x23: - dev->irq = PIC_2XX_XHCI_2_IRQ; - break; - } -} - -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_XLP9XX_XHCI, - nlm_xlp9xx_usb_fixup_final); -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_XHCI, - nlm_xlp2xx_usb_fixup_final); diff --git a/arch/mips/netlogic/xlp/usb-init.c b/arch/mips/netlogic/xlp/usb-init.c deleted file mode 100644 index f8117985f0f8..000000000000 --- a/arch/mips/netlogic/xlp/usb-init.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (c) 2003-2012 Broadcom Corporation - * All Rights Reserved - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the Broadcom - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/dma-mapping.h> -#include <linux/kernel.h> -#include <linux/delay.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/platform_device.h> - -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/xlp-hal/iomap.h> -#include <asm/netlogic/xlp-hal/xlp.h> - -/* - * USB glue logic registers, used only during initialization - */ -#define USB_CTL_0 0x01 -#define USB_PHY_0 0x0A -#define USB_PHY_RESET 0x01 -#define USB_PHY_PORT_RESET_0 0x10 -#define USB_PHY_PORT_RESET_1 0x20 -#define USB_CONTROLLER_RESET 0x01 -#define USB_INT_STATUS 0x0E -#define USB_INT_EN 0x0F -#define USB_PHY_INTERRUPT_EN 0x01 -#define USB_OHCI_INTERRUPT_EN 0x02 -#define USB_OHCI_INTERRUPT1_EN 0x04 -#define USB_OHCI_INTERRUPT2_EN 0x08 -#define USB_CTRL_INTERRUPT_EN 0x10 - -#define nlm_read_usb_reg(b, r) nlm_read_reg(b, r) -#define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v) -#define nlm_get_usb_pcibase(node, inst) \ - nlm_pcicfg_base(XLP_IO_USB_OFFSET(node, inst)) -#define nlm_get_usb_regbase(node, inst) \ - (nlm_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ) - -static void nlm_usb_intr_en(int node, int port) -{ - uint32_t val; - uint64_t port_addr; - - port_addr = nlm_get_usb_regbase(node, port); - val = nlm_read_usb_reg(port_addr, USB_INT_EN); - val = USB_CTRL_INTERRUPT_EN | USB_OHCI_INTERRUPT_EN | - USB_OHCI_INTERRUPT1_EN | USB_OHCI_INTERRUPT2_EN; - nlm_write_usb_reg(port_addr, USB_INT_EN, val); -} - -static void nlm_usb_hw_reset(int node, int port) -{ - uint64_t port_addr; - uint32_t val; - - /* reset USB phy */ - port_addr = nlm_get_usb_regbase(node, port); - val = nlm_read_usb_reg(port_addr, USB_PHY_0); - val &= ~(USB_PHY_RESET | USB_PHY_PORT_RESET_0 | USB_PHY_PORT_RESET_1); - nlm_write_usb_reg(port_addr, USB_PHY_0, val); - - mdelay(100); - val = nlm_read_usb_reg(port_addr, USB_CTL_0); - val &= ~(USB_CONTROLLER_RESET); - val |= 0x4; - nlm_write_usb_reg(port_addr, USB_CTL_0, val); -} - -static int __init nlm_platform_usb_init(void) -{ - if (cpu_is_xlpii()) - return 0; - - pr_info("Initializing USB Interface\n"); - nlm_usb_hw_reset(0, 0); - nlm_usb_hw_reset(0, 3); - - /* Enable PHY interrupts */ - nlm_usb_intr_en(0, 0); - nlm_usb_intr_en(0, 3); - - return 0; -} - -arch_initcall(nlm_platform_usb_init); - -static u64 xlp_usb_dmamask = ~(u32)0; - -/* Fixup the IRQ for USB devices which is exist on XLP SOC PCIE bus */ -static void nlm_usb_fixup_final(struct pci_dev *dev) -{ - dev->dev.dma_mask = &xlp_usb_dmamask; - dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); - switch (dev->devfn) { - case 0x10: - dev->irq = PIC_EHCI_0_IRQ; - break; - case 0x11: - dev->irq = PIC_OHCI_0_IRQ; - break; - case 0x12: - dev->irq = PIC_OHCI_1_IRQ; - break; - case 0x13: - dev->irq = PIC_EHCI_1_IRQ; - break; - case 0x14: - dev->irq = PIC_OHCI_2_IRQ; - break; - case 0x15: - dev->irq = PIC_OHCI_3_IRQ; - break; - } -} -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_EHCI, - nlm_usb_fixup_final); -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_OHCI, - nlm_usb_fixup_final); diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c deleted file mode 100644 index d61004dd71b4..000000000000 --- a/arch/mips/netlogic/xlp/wakeup.c +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/kernel.h> -#include <linux/threads.h> - -#include <asm/asm.h> -#include <asm/asm-offsets.h> -#include <asm/mipsregs.h> -#include <asm/addrspace.h> -#include <asm/string.h> - -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/common.h> -#include <asm/netlogic/mips-extns.h> - -#include <asm/netlogic/xlp-hal/iomap.h> -#include <asm/netlogic/xlp-hal/xlp.h> -#include <asm/netlogic/xlp-hal/pic.h> -#include <asm/netlogic/xlp-hal/sys.h> - -static int xlp_wakeup_core(uint64_t sysbase, int node, int core) -{ - uint32_t coremask, value; - int count, resetreg; - - coremask = (1 << core); - - /* Enable CPU clock in case of 8xx/3xx */ - if (!cpu_is_xlpii()) { - value = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL); - value &= ~coremask; - nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value); - } - - /* On 9XX, mark coherent first */ - if (cpu_is_xlp9xx()) { - value = nlm_read_sys_reg(sysbase, SYS_9XX_CPU_NONCOHERENT_MODE); - value &= ~coremask; - nlm_write_sys_reg(sysbase, SYS_9XX_CPU_NONCOHERENT_MODE, value); - } - - /* Remove CPU Reset */ - resetreg = cpu_is_xlp9xx() ? SYS_9XX_CPU_RESET : SYS_CPU_RESET; - value = nlm_read_sys_reg(sysbase, resetreg); - value &= ~coremask; - nlm_write_sys_reg(sysbase, resetreg, value); - - /* We are done on 9XX */ - if (cpu_is_xlp9xx()) - return 1; - - /* Poll for CPU to mark itself coherent on other type of XLP */ - count = 100000; - do { - value = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE); - } while ((value & coremask) != 0 && --count > 0); - - return count != 0; -} - -static int wait_for_cpus(int cpu, int bootcpu) -{ - volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); - int i, count, notready; - - count = 0x800000; - do { - notready = nlm_threads_per_core; - for (i = 0; i < nlm_threads_per_core; i++) - if (cpu_ready[cpu + i] || (cpu + i) == bootcpu) - --notready; - } while (notready != 0 && --count > 0); - - return count != 0; -} - -static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask) -{ - struct nlm_soc_info *nodep; - uint64_t syspcibase, fusebase; - uint32_t syscoremask, mask, fusemask; - int core, n, cpu, ncores; - - for (n = 0; n < NLM_NR_NODES; n++) { - if (n != 0) { - /* check if node exists and is online */ - if (cpu_is_xlp9xx()) { - int b = xlp9xx_get_socbus(n); - pr_info("Node %d SoC PCI bus %d.\n", n, b); - if (b == 0) - break; - } else { - syspcibase = nlm_get_sys_pcibase(n); - if (nlm_read_reg(syspcibase, 0) == 0xffffffff) - break; - } - nlm_node_init(n); - } - - /* read cores in reset from SYS */ - nodep = nlm_get_node(n); - - if (cpu_is_xlp9xx()) { - fusebase = nlm_get_fuse_regbase(n); - fusemask = nlm_read_reg(fusebase, FUSE_9XX_DEVCFG6); - switch (read_c0_prid() & PRID_IMP_MASK) { - case PRID_IMP_NETLOGIC_XLP5XX: - mask = 0xff; - break; - case PRID_IMP_NETLOGIC_XLP9XX: - default: - mask = 0xfffff; - break; - } - } else { - fusemask = nlm_read_sys_reg(nodep->sysbase, - SYS_EFUSE_DEVICE_CFG_STATUS0); - switch (read_c0_prid() & PRID_IMP_MASK) { - case PRID_IMP_NETLOGIC_XLP3XX: - mask = 0xf; - break; - case PRID_IMP_NETLOGIC_XLP2XX: - mask = 0x3; - break; - case PRID_IMP_NETLOGIC_XLP8XX: - default: - mask = 0xff; - break; - } - } - - /* - * Fused out cores are set in the fusemask, and the remaining - * cores are renumbered to range 0 .. nactive-1 - */ - syscoremask = (1 << hweight32(~fusemask & mask)) - 1; - - pr_info("Node %d - SYS/FUSE coremask %x\n", n, syscoremask); - ncores = nlm_cores_per_node(); - for (core = 0; core < ncores; core++) { - /* we will be on node 0 core 0 */ - if (n == 0 && core == 0) - continue; - - /* see if the core exists */ - if ((syscoremask & (1 << core)) == 0) - continue; - - /* see if at least the first hw thread is enabled */ - cpu = (n * ncores + core) * NLM_THREADS_PER_CORE; - if (!cpumask_test_cpu(cpu, wakeup_mask)) - continue; - - /* wake up the core */ - if (!xlp_wakeup_core(nodep->sysbase, n, core)) - continue; - - /* core is up */ - nodep->coremask |= 1u << core; - - /* spin until the hw threads sets their ready */ - if (!wait_for_cpus(cpu, 0)) - pr_err("Node %d : timeout core %d\n", n, core); - } - } -} - -void xlp_wakeup_secondary_cpus(void) -{ - /* - * In case of u-boot, the secondaries are in reset - * first wakeup core 0 threads - */ - xlp_boot_core0_siblings(); - if (!wait_for_cpus(0, 0)) - pr_err("Node 0 : timeout core 0\n"); - - /* now get other cores out of reset */ - xlp_enable_secondary_cores(&nlm_cpumask); -} |