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-rw-r--r--arch/mips/include/asm/netlogic/common.h132
-rw-r--r--arch/mips/include/asm/netlogic/haldefs.h171
-rw-r--r--arch/mips/include/asm/netlogic/interrupt.h45
-rw-r--r--arch/mips/include/asm/netlogic/mips-extns.h301
-rw-r--r--arch/mips/include/asm/netlogic/psb-bootinfo.h95
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/bridge.h186
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h89
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/iomap.h214
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pcibus.h113
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pic.h366
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/sys.h213
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/uart.h192
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/xlp.h119
-rw-r--r--arch/mips/include/asm/netlogic/xlr/bridge.h104
-rw-r--r--arch/mips/include/asm/netlogic/xlr/flash.h55
-rw-r--r--arch/mips/include/asm/netlogic/xlr/fmn.h365
-rw-r--r--arch/mips/include/asm/netlogic/xlr/gpio.h74
-rw-r--r--arch/mips/include/asm/netlogic/xlr/iomap.h109
-rw-r--r--arch/mips/include/asm/netlogic/xlr/msidef.h84
-rw-r--r--arch/mips/include/asm/netlogic/xlr/pic.h306
-rw-r--r--arch/mips/include/asm/netlogic/xlr/xlr.h59
21 files changed, 0 insertions, 3392 deletions
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
deleted file mode 100644
index 57616649b4f3..000000000000
--- a/arch/mips/include/asm/netlogic/common.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _NETLOGIC_COMMON_H_
-#define _NETLOGIC_COMMON_H_
-
-/*
- * Common SMP definitions
- */
-#define RESET_VEC_PHYS 0x1fc00000
-#define RESET_VEC_SIZE 8192 /* 8KB reset code and data */
-#define RESET_DATA_PHYS (RESET_VEC_PHYS + (1<<10))
-
-/* Offsets of parameters in the RESET_DATA_PHYS area */
-#define BOOT_THREAD_MODE 0
-#define BOOT_NMI_LOCK 4
-#define BOOT_NMI_HANDLER 8
-
-/* CPU ready flags for each CPU */
-#define BOOT_CPU_READY 2048
-
-#ifndef __ASSEMBLY__
-#include <linux/cpumask.h>
-#include <linux/spinlock.h>
-#include <asm/irq.h>
-#include <asm/mach-netlogic/multi-node.h>
-
-struct irq_desc;
-void nlm_smp_function_ipi_handler(struct irq_desc *desc);
-void nlm_smp_resched_ipi_handler(struct irq_desc *desc);
-void nlm_smp_irq_init(int hwcpuid);
-void nlm_boot_secondary_cpus(void);
-int nlm_wakeup_secondary_cpus(void);
-void nlm_rmiboot_preboot(void);
-void nlm_percpu_init(int hwcpuid);
-
-static inline void *
-nlm_get_boot_data(int offset)
-{
- return (void *)(CKSEG1ADDR(RESET_DATA_PHYS) + offset);
-}
-
-static inline void
-nlm_set_nmi_handler(void *handler)
-{
- void *nmih = nlm_get_boot_data(BOOT_NMI_HANDLER);
-
- *(int64_t *)nmih = (long)handler;
-}
-
-/*
- * Misc.
- */
-void nlm_init_boot_cpu(void);
-unsigned int nlm_get_cpu_frequency(void);
-extern const struct plat_smp_ops nlm_smp_ops;
-extern char nlm_reset_entry[], nlm_reset_entry_end[];
-
-extern unsigned int nlm_threads_per_core;
-extern cpumask_t nlm_cpumask;
-
-struct irq_data;
-uint64_t nlm_pci_irqmask(int node);
-void nlm_setup_pic_irq(int node, int picirq, int irq, int irt);
-void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *));
-
-#ifdef CONFIG_PCI_MSI
-void nlm_dispatch_msi(int node, int lirq);
-void nlm_dispatch_msix(int node, int msixirq);
-#endif
-
-/*
- * The NR_IRQs is divided between nodes, each of them has a separate irq space
- */
-static inline int nlm_irq_to_xirq(int node, int irq)
-{
- return node * NR_IRQS / NLM_NR_NODES + irq;
-}
-
-#ifdef CONFIG_CPU_XLR
-#define nlm_cores_per_node() 8
-#else
-static inline int nlm_cores_per_node(void)
-{
- return ((read_c0_prid() & PRID_IMP_MASK)
- == PRID_IMP_NETLOGIC_XLP9XX) ? 32 : 8;
-}
-#endif
-static inline int nlm_threads_per_node(void)
-{
- return nlm_cores_per_node() * NLM_THREADS_PER_CORE;
-}
-
-static inline int nlm_hwtid_to_node(int hwtid)
-{
- return hwtid / nlm_threads_per_node();
-}
-
-extern int nlm_cpu_ready[];
-#endif /* __ASSEMBLY__ */
-#endif /* _NETLOGIC_COMMON_H_ */
diff --git a/arch/mips/include/asm/netlogic/haldefs.h b/arch/mips/include/asm/netlogic/haldefs.h
deleted file mode 100644
index 79c7cccdc22c..000000000000
--- a/arch/mips/include/asm/netlogic/haldefs.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __NLM_HAL_HALDEFS_H__
-#define __NLM_HAL_HALDEFS_H__
-
-#include <linux/irqflags.h> /* for local_irq_disable */
-
-/*
- * This file contains platform specific memory mapped IO implementation
- * and will provide a way to read 32/64 bit memory mapped registers in
- * all ABIs
- */
-static inline uint32_t
-nlm_read_reg(uint64_t base, uint32_t reg)
-{
- volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
-
- return *addr;
-}
-
-static inline void
-nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val)
-{
- volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
-
- *addr = val;
-}
-
-/*
- * For o32 compilation, we have to disable interrupts to access 64 bit
- * registers
- *
- * We need to disable interrupts because we save just the lower 32 bits of
- * registers in interrupt handling. So if we get hit by an interrupt while
- * using the upper 32 bits of a register, we lose.
- */
-
-static inline uint64_t
-nlm_read_reg64(uint64_t base, uint32_t reg)
-{
- uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
- volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
- uint64_t val;
-
- if (sizeof(unsigned long) == 4) {
- unsigned long flags;
-
- local_irq_save(flags);
- __asm__ __volatile__(
- ".set push" "\n\t"
- ".set mips64" "\n\t"
- "ld %L0, %1" "\n\t"
- "dsra32 %M0, %L0, 0" "\n\t"
- "sll %L0, %L0, 0" "\n\t"
- ".set pop" "\n"
- : "=r" (val)
- : "m" (*ptr));
- local_irq_restore(flags);
- } else
- val = *ptr;
-
- return val;
-}
-
-static inline void
-nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val)
-{
- uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
- volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
-
- if (sizeof(unsigned long) == 4) {
- unsigned long flags;
- uint64_t tmp;
-
- local_irq_save(flags);
- __asm__ __volatile__(
- ".set push" "\n\t"
- ".set mips64" "\n\t"
- "dsll32 %L0, %L0, 0" "\n\t"
- "dsrl32 %L0, %L0, 0" "\n\t"
- "dsll32 %M0, %M0, 0" "\n\t"
- "or %L0, %L0, %M0" "\n\t"
- "sd %L0, %2" "\n\t"
- ".set pop" "\n"
- : "=r" (tmp)
- : "0" (val), "m" (*ptr));
- local_irq_restore(flags);
- } else
- *ptr = val;
-}
-
-/*
- * Routines to store 32/64 bit values to 64 bit addresses,
- * used when going thru XKPHYS to access registers
- */
-static inline uint32_t
-nlm_read_reg_xkphys(uint64_t base, uint32_t reg)
-{
- return nlm_read_reg(base, reg);
-}
-
-static inline void
-nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val)
-{
- nlm_write_reg(base, reg, val);
-}
-
-static inline uint64_t
-nlm_read_reg64_xkphys(uint64_t base, uint32_t reg)
-{
- return nlm_read_reg64(base, reg);
-}
-
-static inline void
-nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val)
-{
- nlm_write_reg64(base, reg, val);
-}
-
-/* Location where IO base is mapped */
-extern uint64_t nlm_io_base;
-
-#if defined(CONFIG_CPU_XLP)
-static inline uint64_t
-nlm_pcicfg_base(uint32_t devoffset)
-{
- return nlm_io_base + devoffset;
-}
-
-#elif defined(CONFIG_CPU_XLR)
-
-static inline uint64_t
-nlm_mmio_base(uint32_t devoffset)
-{
- return nlm_io_base + devoffset;
-}
-#endif
-
-#endif
diff --git a/arch/mips/include/asm/netlogic/interrupt.h b/arch/mips/include/asm/netlogic/interrupt.h
deleted file mode 100644
index ed5993d9b7b8..000000000000
--- a/arch/mips/include/asm/netlogic/interrupt.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _ASM_NLM_INTERRUPT_H
-#define _ASM_NLM_INTERRUPT_H
-
-/* Defines for the IRQ numbers */
-
-#define IRQ_IPI_SMP_FUNCTION 3
-#define IRQ_IPI_SMP_RESCHEDULE 4
-#define IRQ_FMN 5
-#define IRQ_TIMER 7
-
-#endif
diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h
deleted file mode 100644
index 788baf399e69..000000000000
--- a/arch/mips/include/asm/netlogic/mips-extns.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _ASM_NLM_MIPS_EXTS_H
-#define _ASM_NLM_MIPS_EXTS_H
-
-/*
- * XLR and XLP interrupt request and interrupt mask registers
- */
-/*
- * NOTE: Do not save/restore flags around write_c0_eimr().
- * On non-R2 platforms the flags has part of EIMR that is shadowed in STATUS
- * register. Restoring flags will overwrite the lower 8 bits of EIMR.
- *
- * Call with interrupts disabled.
- */
-#define write_c0_eimr(val) \
-do { \
- if (sizeof(unsigned long) == 4) { \
- __asm__ __volatile__( \
- ".set\tmips64\n\t" \
- "dsll\t%L0, %L0, 32\n\t" \
- "dsrl\t%L0, %L0, 32\n\t" \
- "dsll\t%M0, %M0, 32\n\t" \
- "or\t%L0, %L0, %M0\n\t" \
- "dmtc0\t%L0, $9, 7\n\t" \
- ".set\tmips0" \
- : : "r" (val)); \
- } else \
- __write_64bit_c0_register($9, 7, (val)); \
-} while (0)
-
-/*
- * Handling the 64 bit EIMR and EIRR registers in 32-bit mode with
- * standard functions will be very inefficient. This provides
- * optimized functions for the normal operations on the registers.
- *
- * Call with interrupts disabled.
- */
-static inline void ack_c0_eirr(int irq)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set mips64\n\t"
- ".set noat\n\t"
- "li $1, 1\n\t"
- "dsllv $1, $1, %0\n\t"
- "dmtc0 $1, $9, 6\n\t"
- ".set pop"
- : : "r" (irq));
-}
-
-static inline void set_c0_eimr(int irq)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set mips64\n\t"
- ".set noat\n\t"
- "li $1, 1\n\t"
- "dsllv %0, $1, %0\n\t"
- "dmfc0 $1, $9, 7\n\t"
- "or $1, %0\n\t"
- "dmtc0 $1, $9, 7\n\t"
- ".set pop"
- : "+r" (irq));
-}
-
-static inline void clear_c0_eimr(int irq)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set mips64\n\t"
- ".set noat\n\t"
- "li $1, 1\n\t"
- "dsllv %0, $1, %0\n\t"
- "dmfc0 $1, $9, 7\n\t"
- "or $1, %0\n\t"
- "xor $1, %0\n\t"
- "dmtc0 $1, $9, 7\n\t"
- ".set pop"
- : "+r" (irq));
-}
-
-/*
- * Read c0 eimr and c0 eirr, do AND of the two values, the result is
- * the interrupts which are raised and are not masked.
- */
-static inline uint64_t read_c0_eirr_and_eimr(void)
-{
- uint64_t val;
-
-#ifdef CONFIG_64BIT
- val = __read_64bit_c0_register($9, 6) & __read_64bit_c0_register($9, 7);
-#else
- __asm__ __volatile__(
- ".set push\n\t"
- ".set mips64\n\t"
- ".set noat\n\t"
- "dmfc0 %M0, $9, 6\n\t"
- "dmfc0 %L0, $9, 7\n\t"
- "and %M0, %L0\n\t"
- "dsll %L0, %M0, 32\n\t"
- "dsra %M0, %M0, 32\n\t"
- "dsra %L0, %L0, 32\n\t"
- ".set pop"
- : "=r" (val));
-#endif
- return val;
-}
-
-static inline int hard_smp_processor_id(void)
-{
- return __read_32bit_c0_register($15, 1) & 0x3ff;
-}
-
-static inline int nlm_nodeid(void)
-{
- uint32_t prid = read_c0_prid() & PRID_IMP_MASK;
-
- if ((prid == PRID_IMP_NETLOGIC_XLP9XX) ||
- (prid == PRID_IMP_NETLOGIC_XLP5XX))
- return (__read_32bit_c0_register($15, 1) >> 7) & 0x7;
- else
- return (__read_32bit_c0_register($15, 1) >> 5) & 0x3;
-}
-
-static inline unsigned int nlm_core_id(void)
-{
- uint32_t prid = read_c0_prid() & PRID_IMP_MASK;
-
- if ((prid == PRID_IMP_NETLOGIC_XLP9XX) ||
- (prid == PRID_IMP_NETLOGIC_XLP5XX))
- return (read_c0_ebase() & 0x7c) >> 2;
- else
- return (read_c0_ebase() & 0x1c) >> 2;
-}
-
-static inline unsigned int nlm_thread_id(void)
-{
- return read_c0_ebase() & 0x3;
-}
-
-#define __read_64bit_c2_split(source, sel) \
-({ \
- unsigned long long __val; \
- unsigned long __flags; \
- \
- local_irq_save(__flags); \
- if (sel == 0) \
- __asm__ __volatile__( \
- ".set\tmips64\n\t" \
- "dmfc2\t%M0, " #source "\n\t" \
- "dsll\t%L0, %M0, 32\n\t" \
- "dsra\t%M0, %M0, 32\n\t" \
- "dsra\t%L0, %L0, 32\n\t" \
- ".set\tmips0\n\t" \
- : "=r" (__val)); \
- else \
- __asm__ __volatile__( \
- ".set\tmips64\n\t" \
- "dmfc2\t%M0, " #source ", " #sel "\n\t" \
- "dsll\t%L0, %M0, 32\n\t" \
- "dsra\t%M0, %M0, 32\n\t" \
- "dsra\t%L0, %L0, 32\n\t" \
- ".set\tmips0\n\t" \
- : "=r" (__val)); \
- local_irq_restore(__flags); \
- \
- __val; \
-})
-
-#define __write_64bit_c2_split(source, sel, val) \
-do { \
- unsigned long __flags; \
- \
- local_irq_save(__flags); \
- if (sel == 0) \
- __asm__ __volatile__( \
- ".set\tmips64\n\t" \
- "dsll\t%L0, %L0, 32\n\t" \
- "dsrl\t%L0, %L0, 32\n\t" \
- "dsll\t%M0, %M0, 32\n\t" \
- "or\t%L0, %L0, %M0\n\t" \
- "dmtc2\t%L0, " #source "\n\t" \
- ".set\tmips0\n\t" \
- : : "r" (val)); \
- else \
- __asm__ __volatile__( \
- ".set\tmips64\n\t" \
- "dsll\t%L0, %L0, 32\n\t" \
- "dsrl\t%L0, %L0, 32\n\t" \
- "dsll\t%M0, %M0, 32\n\t" \
- "or\t%L0, %L0, %M0\n\t" \
- "dmtc2\t%L0, " #source ", " #sel "\n\t" \
- ".set\tmips0\n\t" \
- : : "r" (val)); \
- local_irq_restore(__flags); \
-} while (0)
-
-#define __read_32bit_c2_register(source, sel) \
-({ uint32_t __res; \
- if (sel == 0) \
- __asm__ __volatile__( \
- ".set\tmips32\n\t" \
- "mfc2\t%0, " #source "\n\t" \
- ".set\tmips0\n\t" \
- : "=r" (__res)); \
- else \
- __asm__ __volatile__( \
- ".set\tmips32\n\t" \
- "mfc2\t%0, " #source ", " #sel "\n\t" \
- ".set\tmips0\n\t" \
- : "=r" (__res)); \
- __res; \
-})
-
-#define __read_64bit_c2_register(source, sel) \
-({ unsigned long long __res; \
- if (sizeof(unsigned long) == 4) \
- __res = __read_64bit_c2_split(source, sel); \
- else if (sel == 0) \
- __asm__ __volatile__( \
- ".set\tmips64\n\t" \
- "dmfc2\t%0, " #source "\n\t" \
- ".set\tmips0\n\t" \
- : "=r" (__res)); \
- else \
- __asm__ __volatile__( \
- ".set\tmips64\n\t" \
- "dmfc2\t%0, " #source ", " #sel "\n\t" \
- ".set\tmips0\n\t" \
- : "=r" (__res)); \
- __res; \
-})
-
-#define __write_64bit_c2_register(register, sel, value) \
-do { \
- if (sizeof(unsigned long) == 4) \
- __write_64bit_c2_split(register, sel, value); \
- else if (sel == 0) \
- __asm__ __volatile__( \
- ".set\tmips64\n\t" \
- "dmtc2\t%z0, " #register "\n\t" \
- ".set\tmips0\n\t" \
- : : "Jr" (value)); \
- else \
- __asm__ __volatile__( \
- ".set\tmips64\n\t" \
- "dmtc2\t%z0, " #register ", " #sel "\n\t" \
- ".set\tmips0\n\t" \
- : : "Jr" (value)); \
-} while (0)
-
-#define __write_32bit_c2_register(reg, sel, value) \
-({ \
- if (sel == 0) \
- __asm__ __volatile__( \
- ".set\tmips32\n\t" \
- "mtc2\t%z0, " #reg "\n\t" \
- ".set\tmips0\n\t" \
- : : "Jr" (value)); \
- else \
- __asm__ __volatile__( \
- ".set\tmips32\n\t" \
- "mtc2\t%z0, " #reg ", " #sel "\n\t" \
- ".set\tmips0\n\t" \
- : : "Jr" (value)); \
-})
-
-#endif /*_ASM_NLM_MIPS_EXTS_H */
diff --git a/arch/mips/include/asm/netlogic/psb-bootinfo.h b/arch/mips/include/asm/netlogic/psb-bootinfo.h
deleted file mode 100644
index c716e9397113..000000000000
--- a/arch/mips/include/asm/netlogic/psb-bootinfo.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _ASM_NETLOGIC_BOOTINFO_H
-#define _ASM_NETLOGIC_BOOTINFO_H
-
-struct psb_info {
- uint64_t boot_level;
- uint64_t io_base;
- uint64_t output_device;
- uint64_t uart_print;
- uint64_t led_output;
- uint64_t init;
- uint64_t exit;
- uint64_t warm_reset;
- uint64_t wakeup;
- uint64_t online_cpu_map;
- uint64_t master_reentry_sp;
- uint64_t master_reentry_gp;
- uint64_t master_reentry_fn;
- uint64_t slave_reentry_fn;
- uint64_t magic_dword;
- uint64_t uart_putchar;
- uint64_t size;
- uint64_t uart_getchar;
- uint64_t nmi_handler;
- uint64_t psb_version;
- uint64_t mac_addr;
- uint64_t cpu_frequency;
- uint64_t board_version;
- uint64_t malloc;
- uint64_t free;
- uint64_t global_shmem_addr;
- uint64_t global_shmem_size;
- uint64_t psb_os_cpu_map;
- uint64_t userapp_cpu_map;
- uint64_t wakeup_os;
- uint64_t psb_mem_map;
- uint64_t board_major_version;
- uint64_t board_minor_version;
- uint64_t board_manf_revision;
- uint64_t board_serial_number;
- uint64_t psb_physaddr_map;
- uint64_t xlr_loaderip_config;
- uint64_t bldr_envp;
- uint64_t avail_mem_map;
-};
-
-/* This is what netlboot passes and linux boot_mem_map is subtly different */
-#define NLM_BOOT_MEM_MAP_MAX 32
-struct nlm_boot_mem_map {
- int nr_map;
- struct nlm_boot_mem_map_entry {
- uint64_t addr; /* start of memory segment */
- uint64_t size; /* size of memory segment */
- uint32_t type; /* type of memory segment */
- } map[NLM_BOOT_MEM_MAP_MAX];
-};
-#define NLM_BOOT_MEM_RAM 1
-
-/* Pointer to saved boot loader info */
-extern struct psb_info nlm_prom_info;
-
-#endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
deleted file mode 100644
index 3067f983495d..000000000000
--- a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __NLM_HAL_BRIDGE_H__
-#define __NLM_HAL_BRIDGE_H__
-
-/**
-* @file_name mio.h
-* @author Netlogic Microsystems
-* @brief Basic definitions of XLP memory and io subsystem
-*/
-
-/*
- * BRIDGE specific registers
- *
- * These registers start after the PCIe header, which has 0x40
- * standard entries
- */
-#define BRIDGE_MODE 0x00
-#define BRIDGE_PCI_CFG_BASE 0x01
-#define BRIDGE_PCI_CFG_LIMIT 0x02
-#define BRIDGE_PCIE_CFG_BASE 0x03
-#define BRIDGE_PCIE_CFG_LIMIT 0x04
-#define BRIDGE_BUSNUM_BAR0 0x05
-#define BRIDGE_BUSNUM_BAR1 0x06
-#define BRIDGE_BUSNUM_BAR2 0x07
-#define BRIDGE_BUSNUM_BAR3 0x08
-#define BRIDGE_BUSNUM_BAR4 0x09
-#define BRIDGE_BUSNUM_BAR5 0x0a
-#define BRIDGE_BUSNUM_BAR6 0x0b
-#define BRIDGE_FLASH_BAR0 0x0c
-#define BRIDGE_FLASH_BAR1 0x0d
-#define BRIDGE_FLASH_BAR2 0x0e
-#define BRIDGE_FLASH_BAR3 0x0f
-#define BRIDGE_FLASH_LIMIT0 0x10
-#define BRIDGE_FLASH_LIMIT1 0x11
-#define BRIDGE_FLASH_LIMIT2 0x12
-#define BRIDGE_FLASH_LIMIT3 0x13
-
-#define BRIDGE_DRAM_BAR(i) (0x14 + (i))
-#define BRIDGE_DRAM_LIMIT(i) (0x1c + (i))
-#define BRIDGE_DRAM_NODE_TRANSLN(i) (0x24 + (i))
-#define BRIDGE_DRAM_CHNL_TRANSLN(i) (0x2c + (i))
-
-#define BRIDGE_PCIEMEM_BASE0 0x34
-#define BRIDGE_PCIEMEM_BASE1 0x35
-#define BRIDGE_PCIEMEM_BASE2 0x36
-#define BRIDGE_PCIEMEM_BASE3 0x37
-#define BRIDGE_PCIEMEM_LIMIT0 0x38
-#define BRIDGE_PCIEMEM_LIMIT1 0x39
-#define BRIDGE_PCIEMEM_LIMIT2 0x3a
-#define BRIDGE_PCIEMEM_LIMIT3 0x3b
-#define BRIDGE_PCIEIO_BASE0 0x3c
-#define BRIDGE_PCIEIO_BASE1 0x3d
-#define BRIDGE_PCIEIO_BASE2 0x3e
-#define BRIDGE_PCIEIO_BASE3 0x3f
-#define BRIDGE_PCIEIO_LIMIT0 0x40
-#define BRIDGE_PCIEIO_LIMIT1 0x41
-#define BRIDGE_PCIEIO_LIMIT2 0x42
-#define BRIDGE_PCIEIO_LIMIT3 0x43
-#define BRIDGE_PCIEMEM_BASE4 0x44
-#define BRIDGE_PCIEMEM_BASE5 0x45
-#define BRIDGE_PCIEMEM_BASE6 0x46
-#define BRIDGE_PCIEMEM_LIMIT4 0x47
-#define BRIDGE_PCIEMEM_LIMIT5 0x48
-#define BRIDGE_PCIEMEM_LIMIT6 0x49
-#define BRIDGE_PCIEIO_BASE4 0x4a
-#define BRIDGE_PCIEIO_BASE5 0x4b
-#define BRIDGE_PCIEIO_BASE6 0x4c
-#define BRIDGE_PCIEIO_LIMIT4 0x4d
-#define BRIDGE_PCIEIO_LIMIT5 0x4e
-#define BRIDGE_PCIEIO_LIMIT6 0x4f
-#define BRIDGE_NBU_EVENT_CNT_CTL 0x50
-#define BRIDGE_EVNTCTR1_LOW 0x51
-#define BRIDGE_EVNTCTR1_HI 0x52
-#define BRIDGE_EVNT_CNT_CTL2 0x53
-#define BRIDGE_EVNTCTR2_LOW 0x54
-#define BRIDGE_EVNTCTR2_HI 0x55
-#define BRIDGE_TRACEBUF_MATCH0 0x56
-#define BRIDGE_TRACEBUF_MATCH1 0x57
-#define BRIDGE_TRACEBUF_MATCH_LOW 0x58
-#define BRIDGE_TRACEBUF_MATCH_HI 0x59
-#define BRIDGE_TRACEBUF_CTRL 0x5a
-#define BRIDGE_TRACEBUF_INIT 0x5b
-#define BRIDGE_TRACEBUF_ACCESS 0x5c
-#define BRIDGE_TRACEBUF_READ_DATA0 0x5d
-#define BRIDGE_TRACEBUF_READ_DATA1 0x5d
-#define BRIDGE_TRACEBUF_READ_DATA2 0x5f
-#define BRIDGE_TRACEBUF_READ_DATA3 0x60
-#define BRIDGE_TRACEBUF_STATUS 0x61
-#define BRIDGE_ADDRESS_ERROR0 0x62
-#define BRIDGE_ADDRESS_ERROR1 0x63
-#define BRIDGE_ADDRESS_ERROR2 0x64
-#define BRIDGE_TAG_ECC_ADDR_ERROR0 0x65
-#define BRIDGE_TAG_ECC_ADDR_ERROR1 0x66
-#define BRIDGE_TAG_ECC_ADDR_ERROR2 0x67
-#define BRIDGE_LINE_FLUSH0 0x68
-#define BRIDGE_LINE_FLUSH1 0x69
-#define BRIDGE_NODE_ID 0x6a
-#define BRIDGE_ERROR_INTERRUPT_EN 0x6b
-#define BRIDGE_PCIE0_WEIGHT 0x2c0
-#define BRIDGE_PCIE1_WEIGHT 0x2c1
-#define BRIDGE_PCIE2_WEIGHT 0x2c2
-#define BRIDGE_PCIE3_WEIGHT 0x2c3
-#define BRIDGE_USB_WEIGHT 0x2c4
-#define BRIDGE_NET_WEIGHT 0x2c5
-#define BRIDGE_POE_WEIGHT 0x2c6
-#define BRIDGE_CMS_WEIGHT 0x2c7
-#define BRIDGE_DMAENG_WEIGHT 0x2c8
-#define BRIDGE_SEC_WEIGHT 0x2c9
-#define BRIDGE_COMP_WEIGHT 0x2ca
-#define BRIDGE_GIO_WEIGHT 0x2cb
-#define BRIDGE_FLASH_WEIGHT 0x2cc
-
-/* FIXME verify */
-#define BRIDGE_9XX_FLASH_BAR(i) (0x11 + (i))
-#define BRIDGE_9XX_FLASH_BAR_LIMIT(i) (0x15 + (i))
-
-#define BRIDGE_9XX_DRAM_BAR(i) (0x19 + (i))
-#define BRIDGE_9XX_DRAM_LIMIT(i) (0x29 + (i))
-#define BRIDGE_9XX_DRAM_NODE_TRANSLN(i) (0x39 + (i))
-#define BRIDGE_9XX_DRAM_CHNL_TRANSLN(i) (0x49 + (i))
-
-#define BRIDGE_9XX_ADDRESS_ERROR0 0x9d
-#define BRIDGE_9XX_ADDRESS_ERROR1 0x9e
-#define BRIDGE_9XX_ADDRESS_ERROR2 0x9f
-
-#define BRIDGE_9XX_PCIEMEM_BASE0 0x59
-#define BRIDGE_9XX_PCIEMEM_BASE1 0x5a
-#define BRIDGE_9XX_PCIEMEM_BASE2 0x5b
-#define BRIDGE_9XX_PCIEMEM_BASE3 0x5c
-#define BRIDGE_9XX_PCIEMEM_LIMIT0 0x5d
-#define BRIDGE_9XX_PCIEMEM_LIMIT1 0x5e
-#define BRIDGE_9XX_PCIEMEM_LIMIT2 0x5f
-#define BRIDGE_9XX_PCIEMEM_LIMIT3 0x60
-#define BRIDGE_9XX_PCIEIO_BASE0 0x61
-#define BRIDGE_9XX_PCIEIO_BASE1 0x62
-#define BRIDGE_9XX_PCIEIO_BASE2 0x63
-#define BRIDGE_9XX_PCIEIO_BASE3 0x64
-#define BRIDGE_9XX_PCIEIO_LIMIT0 0x65
-#define BRIDGE_9XX_PCIEIO_LIMIT1 0x66
-#define BRIDGE_9XX_PCIEIO_LIMIT2 0x67
-#define BRIDGE_9XX_PCIEIO_LIMIT3 0x68
-
-#ifndef __ASSEMBLY__
-
-#define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r)
-#define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v)
-#define nlm_get_bridge_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \
- XLP9XX_IO_BRIDGE_OFFSET(node) : XLP_IO_BRIDGE_OFFSET(node))
-#define nlm_get_bridge_regbase(node) \
- (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
-
-#endif /* __ASSEMBLY__ */
-#endif /* __NLM_HAL_BRIDGE_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
deleted file mode 100644
index a06b59292153..000000000000
--- a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __NLM_HAL_CPUCONTROL_H__
-#define __NLM_HAL_CPUCONTROL_H__
-
-#define CPU_BLOCKID_IFU 0
-#define CPU_BLOCKID_ICU 1
-#define CPU_BLOCKID_IEU 2
-#define CPU_BLOCKID_LSU 3
-#define CPU_BLOCKID_MMU 4
-#define CPU_BLOCKID_PRF 5
-#define CPU_BLOCKID_SCH 7
-#define CPU_BLOCKID_SCU 8
-#define CPU_BLOCKID_FPU 9
-#define CPU_BLOCKID_MAP 10
-
-#define IFU_BRUB_RESERVE 0x007
-
-#define ICU_DEFEATURE 0x100
-
-#define LSU_DEFEATURE 0x304
-#define LSU_DEBUG_ADDR 0x305
-#define LSU_DEBUG_DATA0 0x306
-#define LSU_CERRLOG_REGID 0x309
-#define SCHED_DEFEATURE 0x700
-
-/* Offsets of interest from the 'MAP' Block */
-#define MAP_THREADMODE 0x00
-#define MAP_EXT_EBASE_ENABLE 0x04
-#define MAP_CCDI_CONFIG 0x08
-#define MAP_THRD0_CCDI_STATUS 0x0c
-#define MAP_THRD1_CCDI_STATUS 0x10
-#define MAP_THRD2_CCDI_STATUS 0x14
-#define MAP_THRD3_CCDI_STATUS 0x18
-#define MAP_THRD0_DEBUG_MODE 0x1c
-#define MAP_THRD1_DEBUG_MODE 0x20
-#define MAP_THRD2_DEBUG_MODE 0x24
-#define MAP_THRD3_DEBUG_MODE 0x28
-#define MAP_MISC_STATE 0x60
-#define MAP_DEBUG_READ_CTL 0x64
-#define MAP_DEBUG_READ_REG0 0x68
-#define MAP_DEBUG_READ_REG1 0x6c
-
-#define MMU_SETUP 0x400
-#define MMU_LFSRSEED 0x401
-#define MMU_HPW_NUM_PAGE_LVL 0x410
-#define MMU_PGWKR_PGDBASE 0x411
-#define MMU_PGWKR_PGDSHFT 0x412
-#define MMU_PGWKR_PGDMASK 0x413
-#define MMU_PGWKR_PUDSHFT 0x414
-#define MMU_PGWKR_PUDMASK 0x415
-#define MMU_PGWKR_PMDSHFT 0x416
-#define MMU_PGWKR_PMDMASK 0x417
-#define MMU_PGWKR_PTESHFT 0x418
-#define MMU_PGWKR_PTEMASK 0x419
-
-#endif /* __NLM_CPUCONTROL_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
deleted file mode 100644
index 805bfd21f33e..000000000000
--- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __NLM_HAL_IOMAP_H__
-#define __NLM_HAL_IOMAP_H__
-
-#define XLP_DEFAULT_IO_BASE 0x18000000
-#define XLP_DEFAULT_PCI_ECFG_BASE XLP_DEFAULT_IO_BASE
-#define XLP_DEFAULT_PCI_CFG_BASE 0x1c000000
-
-#define NMI_BASE 0xbfc00000
-#define XLP_IO_CLK 133333333
-
-#define XLP_PCIE_CFG_SIZE 0x1000 /* 4K */
-#define XLP_PCIE_DEV_BLK_SIZE (8 * XLP_PCIE_CFG_SIZE)
-#define XLP_PCIE_BUS_BLK_SIZE (256 * XLP_PCIE_DEV_BLK_SIZE)
-#define XLP_IO_SIZE (64 << 20) /* ECFG space size */
-#define XLP_IO_PCI_HDRSZ 0x100
-#define XLP_IO_DEV(node, dev) ((dev) + (node) * 8)
-#define XLP_IO_PCI_OFFSET(b, d, f) (((b) << 20) | ((d) << 15) | ((f) << 12))
-
-#define XLP_HDR_OFFSET(node, bus, dev, fn) \
- XLP_IO_PCI_OFFSET(bus, XLP_IO_DEV(node, dev), fn)
-
-#define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0)
-/* coherent inter chip */
-#define XLP_IO_CIC0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 1)
-#define XLP_IO_CIC1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 2)
-#define XLP_IO_CIC2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 3)
-#define XLP_IO_PIC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 4)
-
-#define XLP_IO_PCIE_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 1, i)
-#define XLP_IO_PCIE0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 0)
-#define XLP_IO_PCIE1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 1)
-#define XLP_IO_PCIE2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 2)
-#define XLP_IO_PCIE3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 3)
-
-#define XLP_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 2, i)
-#define XLP_IO_USB_EHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 0)
-#define XLP_IO_USB_OHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 1)
-#define XLP_IO_USB_OHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 2)
-#define XLP_IO_USB_EHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 3)
-#define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4)
-#define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5)
-
-#define XLP_IO_SATA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 2)
-
-/* XLP2xx has an updated USB block */
-#define XLP2XX_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 4, i)
-#define XLP2XX_IO_USB_XHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 1)
-#define XLP2XX_IO_USB_XHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 2)
-#define XLP2XX_IO_USB_XHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 3)
-
-#define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0)
-#define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1)
-
-#define XLP_IO_CMS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 0)
-
-#define XLP_IO_DMA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 1)
-#define XLP_IO_SEC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 2)
-#define XLP_IO_CMP_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 3)
-
-#define XLP_IO_UART_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, i)
-#define XLP_IO_UART0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 0)
-#define XLP_IO_UART1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 1)
-#define XLP_IO_I2C_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, 2 + i)
-#define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2)
-#define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3)
-#define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4)
-/* on 2XX, all I2C busses are on the same block */
-#define XLP2XX_IO_I2C_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 7)
-
-/* system management */
-#define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5)
-#define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6)
-
-/* Flash */
-#define XLP_IO_NOR_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 0)
-#define XLP_IO_NAND_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 1)
-#define XLP_IO_SPI_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 2)
-#define XLP_IO_MMC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3)
-
-/* Things have changed drastically in XLP 9XX */
-#define XLP9XX_HDR_OFFSET(n, d, f) \
- XLP_IO_PCI_OFFSET(xlp9xx_get_socbus(n), d, f)
-
-#define XLP9XX_IO_BRIDGE_OFFSET(node) XLP_IO_PCI_OFFSET(0, 0, node)
-#define XLP9XX_IO_PIC_OFFSET(node) XLP9XX_HDR_OFFSET(node, 2, 0)
-#define XLP9XX_IO_UART_OFFSET(node) XLP9XX_HDR_OFFSET(node, 2, 2)
-#define XLP9XX_IO_SYS_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 0)
-#define XLP9XX_IO_FUSE_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 1)
-#define XLP9XX_IO_CLOCK_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 2)
-#define XLP9XX_IO_POWER_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 3)
-#define XLP9XX_IO_JTAG_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 4)
-
-#define XLP9XX_IO_PCIE_OFFSET(node, i) XLP9XX_HDR_OFFSET(node, 1, i)
-#define XLP9XX_IO_PCIE0_OFFSET(node) XLP9XX_HDR_OFFSET(node, 1, 0)
-#define XLP9XX_IO_PCIE2_OFFSET(node) XLP9XX_HDR_OFFSET(node, 1, 2)
-#define XLP9XX_IO_PCIE3_OFFSET(node) XLP9XX_HDR_OFFSET(node, 1, 3)
-
-/* XLP9xx USB block */
-#define XLP9XX_IO_USB_OFFSET(node, i) XLP9XX_HDR_OFFSET(node, 4, i)
-#define XLP9XX_IO_USB_XHCI0_OFFSET(node) XLP9XX_HDR_OFFSET(node, 4, 1)
-#define XLP9XX_IO_USB_XHCI1_OFFSET(node) XLP9XX_HDR_OFFSET(node, 4, 2)
-
-/* XLP9XX on-chip SATA controller */
-#define XLP9XX_IO_SATA_OFFSET(node) XLP9XX_HDR_OFFSET(node, 3, 2)
-
-/* Flash */
-#define XLP9XX_IO_NOR_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 0)
-#define XLP9XX_IO_NAND_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 1)
-#define XLP9XX_IO_SPI_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 2)
-#define XLP9XX_IO_MMC_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 3)
-
-/* PCI config header register id's */
-#define XLP_PCI_CFGREG0 0x00
-#define XLP_PCI_CFGREG1 0x01
-#define XLP_PCI_CFGREG2 0x02
-#define XLP_PCI_CFGREG3 0x03
-#define XLP_PCI_CFGREG4 0x04
-#define XLP_PCI_CFGREG5 0x05
-#define XLP_PCI_DEVINFO_REG0 0x30
-#define XLP_PCI_DEVINFO_REG1 0x31
-#define XLP_PCI_DEVINFO_REG2 0x32
-#define XLP_PCI_DEVINFO_REG3 0x33
-#define XLP_PCI_DEVINFO_REG4 0x34
-#define XLP_PCI_DEVINFO_REG5 0x35
-#define XLP_PCI_DEVINFO_REG6 0x36
-#define XLP_PCI_DEVINFO_REG7 0x37
-#define XLP_PCI_DEVSCRATCH_REG0 0x38
-#define XLP_PCI_DEVSCRATCH_REG1 0x39
-#define XLP_PCI_DEVSCRATCH_REG2 0x3a
-#define XLP_PCI_DEVSCRATCH_REG3 0x3b
-#define XLP_PCI_MSGSTN_REG 0x3c
-#define XLP_PCI_IRTINFO_REG 0x3d
-#define XLP_PCI_UCODEINFO_REG 0x3e
-#define XLP_PCI_SBB_WT_REG 0x3f
-
-/* PCI IDs for SoC device */
-#define PCI_VENDOR_NETLOGIC 0x184e
-
-#define PCI_DEVICE_ID_NLM_ROOT 0x1001
-#define PCI_DEVICE_ID_NLM_ICI 0x1002
-#define PCI_DEVICE_ID_NLM_PIC 0x1003
-#define PCI_DEVICE_ID_NLM_PCIE 0x1004
-#define PCI_DEVICE_ID_NLM_EHCI 0x1007
-#define PCI_DEVICE_ID_NLM_OHCI 0x1008
-#define PCI_DEVICE_ID_NLM_NAE 0x1009
-#define PCI_DEVICE_ID_NLM_POE 0x100A
-#define PCI_DEVICE_ID_NLM_FMN 0x100B
-#define PCI_DEVICE_ID_NLM_RAID 0x100D
-#define PCI_DEVICE_ID_NLM_SAE 0x100D
-#define PCI_DEVICE_ID_NLM_RSA 0x100E
-#define PCI_DEVICE_ID_NLM_CMP 0x100F
-#define PCI_DEVICE_ID_NLM_UART 0x1010
-#define PCI_DEVICE_ID_NLM_I2C 0x1011
-#define PCI_DEVICE_ID_NLM_NOR 0x1015
-#define PCI_DEVICE_ID_NLM_NAND 0x1016
-#define PCI_DEVICE_ID_NLM_MMC 0x1018
-#define PCI_DEVICE_ID_NLM_SATA 0x101A
-#define PCI_DEVICE_ID_NLM_XHCI 0x101D
-
-#define PCI_DEVICE_ID_XLP9XX_MMC 0x9018
-#define PCI_DEVICE_ID_XLP9XX_SATA 0x901A
-#define PCI_DEVICE_ID_XLP9XX_XHCI 0x901D
-
-#ifndef __ASSEMBLY__
-
-#define nlm_read_pci_reg(b, r) nlm_read_reg(b, r)
-#define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v)
-
-static inline int xlp9xx_get_socbus(int node)
-{
- uint64_t socbridge;
-
- if (node == 0)
- return 1;
- socbridge = nlm_pcicfg_base(XLP9XX_IO_BRIDGE_OFFSET(node));
- return (nlm_read_pci_reg(socbridge, 0x6) >> 8) & 0xff;
-}
-#endif /* !__ASSEMBLY */
-
-#endif /* __NLM_HAL_IOMAP_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
deleted file mode 100644
index 91540f41e1e4..000000000000
--- a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Copyright (c) 2003-2012 Broadcom Corporation
- * All Rights Reserved
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the Broadcom
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __NLM_HAL_PCIBUS_H__
-#define __NLM_HAL_PCIBUS_H__
-
-/* PCIE Memory and IO regions */
-#define PCIE_MEM_BASE 0xd0000000ULL
-#define PCIE_MEM_LIMIT 0xdfffffffULL
-#define PCIE_IO_BASE 0x14000000ULL
-#define PCIE_IO_LIMIT 0x15ffffffULL
-
-#define PCIE_BRIDGE_CMD 0x1
-#define PCIE_BRIDGE_MSI_CAP 0x14
-#define PCIE_BRIDGE_MSI_ADDRL 0x15
-#define PCIE_BRIDGE_MSI_ADDRH 0x16
-#define PCIE_BRIDGE_MSI_DATA 0x17
-
-/* XLP Global PCIE configuration space registers */
-#define PCIE_BYTE_SWAP_MEM_BASE 0x247
-#define PCIE_BYTE_SWAP_MEM_LIM 0x248
-#define PCIE_BYTE_SWAP_IO_BASE 0x249
-#define PCIE_BYTE_SWAP_IO_LIM 0x24A
-
-#define PCIE_BRIDGE_MSIX_ADDR_BASE 0x24F
-#define PCIE_BRIDGE_MSIX_ADDR_LIMIT 0x250
-#define PCIE_MSI_STATUS 0x25A
-#define PCIE_MSI_EN 0x25B
-#define PCIE_MSIX_STATUS 0x25D
-#define PCIE_INT_STATUS0 0x25F
-#define PCIE_INT_STATUS1 0x260
-#define PCIE_INT_EN0 0x261
-#define PCIE_INT_EN1 0x262
-
-/* XLP9XX has basic changes */
-#define PCIE_9XX_BYTE_SWAP_MEM_BASE 0x25c
-#define PCIE_9XX_BYTE_SWAP_MEM_LIM 0x25d
-#define PCIE_9XX_BYTE_SWAP_IO_BASE 0x25e
-#define PCIE_9XX_BYTE_SWAP_IO_LIM 0x25f
-
-#define PCIE_9XX_BRIDGE_MSIX_ADDR_BASE 0x264
-#define PCIE_9XX_BRIDGE_MSIX_ADDR_LIMIT 0x265
-#define PCIE_9XX_MSI_STATUS 0x283
-#define PCIE_9XX_MSI_EN 0x284
-/* 128 MSIX vectors available in 9xx */
-#define PCIE_9XX_MSIX_STATUS0 0x286
-#define PCIE_9XX_MSIX_STATUSX(n) (n + 0x286)
-#define PCIE_9XX_MSIX_VEC 0x296
-#define PCIE_9XX_MSIX_VECX(n) (n + 0x296)
-#define PCIE_9XX_INT_STATUS0 0x397
-#define PCIE_9XX_INT_STATUS1 0x398
-#define PCIE_9XX_INT_EN0 0x399
-#define PCIE_9XX_INT_EN1 0x39a
-
-/* other */
-#define PCIE_NLINKS 4
-
-/* MSI addresses */
-#define MSI_ADDR_BASE 0xfffee00000ULL
-#define MSI_ADDR_SZ 0x10000
-#define MSI_LINK_ADDR(n, l) (MSI_ADDR_BASE + \
- (PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ)
-#define MSIX_ADDR_BASE 0xfffef00000ULL
-#define MSIX_LINK_ADDR(n, l) (MSIX_ADDR_BASE + \
- (PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ)
-#ifndef __ASSEMBLY__
-
-#define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r)
-#define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v)
-#define nlm_get_pcie_base(node, inst) nlm_pcicfg_base(cpu_is_xlp9xx() ? \
- XLP9XX_IO_PCIE_OFFSET(node, inst) : XLP_IO_PCIE_OFFSET(node, inst))
-
-#ifdef CONFIG_PCI_MSI
-void xlp_init_node_msi_irqs(int node, int link);
-#else
-static inline void xlp_init_node_msi_irqs(int node, int link) {}
-#endif
-
-struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev);
-
-#endif
-#endif /* __NLM_HAL_PCIBUS_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
deleted file mode 100644
index 41cefe94f0c9..000000000000
--- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h
+++ /dev/null
@@ -1,366 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _NLM_HAL_PIC_H
-#define _NLM_HAL_PIC_H
-
-/* PIC Specific registers */
-#define PIC_CTRL 0x00
-
-/* PIC control register defines */
-#define PIC_CTRL_ITV 32 /* interrupt timeout value */
-#define PIC_CTRL_ICI 19 /* ICI interrupt timeout enable */
-#define PIC_CTRL_ITE 18 /* interrupt timeout enable */
-#define PIC_CTRL_STE 10 /* system timer interrupt enable */
-#define PIC_CTRL_WWR1 8 /* watchdog 1 wraparound count for reset */
-#define PIC_CTRL_WWR0 6 /* watchdog 0 wraparound count for reset */
-#define PIC_CTRL_WWN1 4 /* watchdog 1 wraparound count for NMI */
-#define PIC_CTRL_WWN0 2 /* watchdog 0 wraparound count for NMI */
-#define PIC_CTRL_WTE 0 /* watchdog timer enable */
-
-/* PIC Status register defines */
-#define PIC_ICI_STATUS 33 /* ICI interrupt timeout status */
-#define PIC_ITE_STATUS 32 /* interrupt timeout status */
-#define PIC_STS_STATUS 4 /* System timer interrupt status */
-#define PIC_WNS_STATUS 2 /* NMI status for watchdog timers */
-#define PIC_WIS_STATUS 0 /* Interrupt status for watchdog timers */
-
-/* PIC IPI control register offsets */
-#define PIC_IPICTRL_NMI 32
-#define PIC_IPICTRL_RIV 20 /* received interrupt vector */
-#define PIC_IPICTRL_IDB 16 /* interrupt destination base */
-#define PIC_IPICTRL_DTE 0 /* interrupt destination thread enables */
-
-/* PIC IRT register offsets */
-#define PIC_IRT_ENABLE 31
-#define PIC_IRT_NMI 29
-#define PIC_IRT_SCH 28 /* Scheduling scheme */
-#define PIC_IRT_RVEC 20 /* Interrupt receive vectors */
-#define PIC_IRT_DT 19 /* Destination type */
-#define PIC_IRT_DB 16 /* Destination base */
-#define PIC_IRT_DTE 0 /* Destination thread enables */
-
-#define PIC_BYTESWAP 0x02
-#define PIC_STATUS 0x04
-#define PIC_INTR_TIMEOUT 0x06
-#define PIC_ICI0_INTR_TIMEOUT 0x08
-#define PIC_ICI1_INTR_TIMEOUT 0x0a
-#define PIC_ICI2_INTR_TIMEOUT 0x0c
-#define PIC_IPI_CTL 0x0e
-#define PIC_INT_ACK 0x10
-#define PIC_INT_PENDING0 0x12
-#define PIC_INT_PENDING1 0x14
-#define PIC_INT_PENDING2 0x16
-
-#define PIC_WDOG0_MAXVAL 0x18
-#define PIC_WDOG0_COUNT 0x1a
-#define PIC_WDOG0_ENABLE0 0x1c
-#define PIC_WDOG0_ENABLE1 0x1e
-#define PIC_WDOG0_BEATCMD 0x20
-#define PIC_WDOG0_BEAT0 0x22
-#define PIC_WDOG0_BEAT1 0x24
-
-#define PIC_WDOG1_MAXVAL 0x26
-#define PIC_WDOG1_COUNT 0x28
-#define PIC_WDOG1_ENABLE0 0x2a
-#define PIC_WDOG1_ENABLE1 0x2c
-#define PIC_WDOG1_BEATCMD 0x2e
-#define PIC_WDOG1_BEAT0 0x30
-#define PIC_WDOG1_BEAT1 0x32
-
-#define PIC_WDOG_MAXVAL(i) (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0))
-#define PIC_WDOG_COUNT(i) (PIC_WDOG0_COUNT + ((i) ? 7 : 0))
-#define PIC_WDOG_ENABLE0(i) (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0))
-#define PIC_WDOG_ENABLE1(i) (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0))
-#define PIC_WDOG_BEATCMD(i) (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0))
-#define PIC_WDOG_BEAT0(i) (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0))
-#define PIC_WDOG_BEAT1(i) (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0))
-
-#define PIC_TIMER0_MAXVAL 0x34
-#define PIC_TIMER1_MAXVAL 0x36
-#define PIC_TIMER2_MAXVAL 0x38
-#define PIC_TIMER3_MAXVAL 0x3a
-#define PIC_TIMER4_MAXVAL 0x3c
-#define PIC_TIMER5_MAXVAL 0x3e
-#define PIC_TIMER6_MAXVAL 0x40
-#define PIC_TIMER7_MAXVAL 0x42
-#define PIC_TIMER_MAXVAL(i) (PIC_TIMER0_MAXVAL + ((i) * 2))
-
-#define PIC_TIMER0_COUNT 0x44
-#define PIC_TIMER1_COUNT 0x46
-#define PIC_TIMER2_COUNT 0x48
-#define PIC_TIMER3_COUNT 0x4a
-#define PIC_TIMER4_COUNT 0x4c
-#define PIC_TIMER5_COUNT 0x4e
-#define PIC_TIMER6_COUNT 0x50
-#define PIC_TIMER7_COUNT 0x52
-#define PIC_TIMER_COUNT(i) (PIC_TIMER0_COUNT + ((i) * 2))
-
-#define PIC_ITE0_N0_N1 0x54
-#define PIC_ITE1_N0_N1 0x58
-#define PIC_ITE2_N0_N1 0x5c
-#define PIC_ITE3_N0_N1 0x60
-#define PIC_ITE4_N0_N1 0x64
-#define PIC_ITE5_N0_N1 0x68
-#define PIC_ITE6_N0_N1 0x6c
-#define PIC_ITE7_N0_N1 0x70
-#define PIC_ITE_N0_N1(i) (PIC_ITE0_N0_N1 + ((i) * 4))
-
-#define PIC_ITE0_N2_N3 0x56
-#define PIC_ITE1_N2_N3 0x5a
-#define PIC_ITE2_N2_N3 0x5e
-#define PIC_ITE3_N2_N3 0x62
-#define PIC_ITE4_N2_N3 0x66
-#define PIC_ITE5_N2_N3 0x6a
-#define PIC_ITE6_N2_N3 0x6e
-#define PIC_ITE7_N2_N3 0x72
-#define PIC_ITE_N2_N3(i) (PIC_ITE0_N2_N3 + ((i) * 4))
-
-#define PIC_IRT0 0x74
-#define PIC_IRT(i) (PIC_IRT0 + ((i) * 2))
-
-#define PIC_9XX_PENDING_0 0x6
-#define PIC_9XX_PENDING_1 0x8
-#define PIC_9XX_PENDING_2 0xa
-#define PIC_9XX_PENDING_3 0xc
-
-#define PIC_9XX_IRT0 0x1c0
-#define PIC_9XX_IRT(i) (PIC_9XX_IRT0 + ((i) * 2))
-
-/*
- * IRT Map
- */
-#define PIC_NUM_IRTS 160
-#define PIC_9XX_NUM_IRTS 256
-
-#define PIC_IRT_WD_0_INDEX 0
-#define PIC_IRT_WD_1_INDEX 1
-#define PIC_IRT_WD_NMI_0_INDEX 2
-#define PIC_IRT_WD_NMI_1_INDEX 3
-#define PIC_IRT_TIMER_0_INDEX 4
-#define PIC_IRT_TIMER_1_INDEX 5
-#define PIC_IRT_TIMER_2_INDEX 6
-#define PIC_IRT_TIMER_3_INDEX 7
-#define PIC_IRT_TIMER_4_INDEX 8
-#define PIC_IRT_TIMER_5_INDEX 9
-#define PIC_IRT_TIMER_6_INDEX 10
-#define PIC_IRT_TIMER_7_INDEX 11
-#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX
-#define PIC_IRT_TIMER_INDEX(num) ((num) + PIC_IRT_TIMER_0_INDEX)
-
-
-/* 11 and 12 */
-#define PIC_NUM_MSG_Q_IRTS 32
-#define PIC_IRT_MSG_Q0_INDEX 12
-#define PIC_IRT_MSG_Q_INDEX(qid) ((qid) + PIC_IRT_MSG_Q0_INDEX)
-/* 12 to 43 */
-#define PIC_IRT_MSG_0_INDEX 44
-#define PIC_IRT_MSG_1_INDEX 45
-/* 44 and 45 */
-#define PIC_NUM_PCIE_MSIX_IRTS 32
-#define PIC_IRT_PCIE_MSIX_0_INDEX 46
-#define PIC_IRT_PCIE_MSIX_INDEX(num) ((num) + PIC_IRT_PCIE_MSIX_0_INDEX)
-/* 46 to 77 */
-#define PIC_NUM_PCIE_LINK_IRTS 4
-#define PIC_IRT_PCIE_LINK_0_INDEX 78
-#define PIC_IRT_PCIE_LINK_1_INDEX 79
-#define PIC_IRT_PCIE_LINK_2_INDEX 80
-#define PIC_IRT_PCIE_LINK_3_INDEX 81
-#define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX)
-
-#define PIC_9XX_IRT_PCIE_LINK_0_INDEX 191
-#define PIC_9XX_IRT_PCIE_LINK_INDEX(num) \
- ((num) + PIC_9XX_IRT_PCIE_LINK_0_INDEX)
-
-#define PIC_CLOCK_TIMER 7
-
-#if !defined(LOCORE) && !defined(__ASSEMBLY__)
-
-/*
- * Misc
- */
-#define PIC_IRT_VALID 1
-#define PIC_LOCAL_SCHEDULING 1
-#define PIC_GLOBAL_SCHEDULING 0
-
-#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r)
-#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
-#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \
- XLP9XX_IO_PIC_OFFSET(node) : XLP_IO_PIC_OFFSET(node))
-#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
-
-/* We use PIC on node 0 as a timer */
-#define pic_timer_freq() nlm_get_pic_frequency(0)
-
-/* IRT and h/w interrupt routines */
-static inline void
-nlm_9xx_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
- int sch, int vec, int dt, int db, int cpu)
-{
- uint64_t val;
-
- val = (((uint64_t)en & 0x1) << 22) | ((nmi & 0x1) << 23) |
- ((0 /*mc*/) << 20) | ((vec & 0x3f) << 24) |
- ((dt & 0x1) << 21) | (0 /*ptr*/ << 16) |
- (cpu & 0x3ff);
-
- nlm_write_pic_reg(base, PIC_9XX_IRT(irt_num), val);
-}
-
-static inline void
-nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
- int sch, int vec, int dt, int db, int dte)
-{
- uint64_t val;
-
- val = (((uint64_t)en & 0x1) << 31) | ((nmi & 0x1) << 29) |
- ((sch & 0x1) << 28) | ((vec & 0x3f) << 20) |
- ((dt & 0x1) << 19) | ((db & 0x7) << 16) |
- (dte & 0xffff);
-
- nlm_write_pic_reg(base, PIC_IRT(irt_num), val);
-}
-
-static inline void
-nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,
- int sch, int vec, int cpu)
-{
- if (cpu_is_xlp9xx())
- nlm_9xx_pic_write_irt(base, irt_num, en, nmi, sch, vec,
- 1, 0, cpu);
- else
- nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
- (cpu >> 4), /* thread group */
- 1 << (cpu & 0xf)); /* thread mask */
-}
-
-static inline uint64_t
-nlm_pic_read_timer(uint64_t base, int timer)
-{
- return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
-}
-
-static inline uint32_t
-nlm_pic_read_timer32(uint64_t base, int timer)
-{
- return (uint32_t)nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
-}
-
-static inline void
-nlm_pic_write_timer(uint64_t base, int timer, uint64_t value)
-{
- nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value);
-}
-
-static inline void
-nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu)
-{
- uint64_t pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL);
- int en;
-
- en = (irq > 0);
- nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value);
- nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer),
- en, 0, 0, irq, cpu);
-
- /* enable the timer */
- pic_ctrl |= (1 << (PIC_CTRL_STE + timer));
- nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl);
-}
-
-static inline void
-nlm_pic_enable_irt(uint64_t base, int irt)
-{
- uint64_t reg;
-
- if (cpu_is_xlp9xx()) {
- reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt));
- nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg | (1 << 22));
- } else {
- reg = nlm_read_pic_reg(base, PIC_IRT(irt));
- nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31));
- }
-}
-
-static inline void
-nlm_pic_disable_irt(uint64_t base, int irt)
-{
- uint64_t reg;
-
- if (cpu_is_xlp9xx()) {
- reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt));
- reg &= ~((uint64_t)1 << 22);
- nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg);
- } else {
- reg = nlm_read_pic_reg(base, PIC_IRT(irt));
- reg &= ~((uint64_t)1 << 31);
- nlm_write_pic_reg(base, PIC_IRT(irt), reg);
- }
-}
-
-static inline void
-nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
-{
- uint64_t ipi;
-
- if (cpu_is_xlp9xx())
- ipi = (nmi << 23) | (irq << 24) |
- (0/*mcm*/ << 20) | (0/*ptr*/ << 16) | hwt;
- else
- ipi = ((uint64_t)nmi << 31) | (irq << 20) |
- ((hwt >> 4) << 16) | (1 << (hwt & 0xf));
-
- nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
-}
-
-static inline void
-nlm_pic_ack(uint64_t base, int irt_num)
-{
- nlm_write_pic_reg(base, PIC_INT_ACK, irt_num);
-
- /* Ack the Status register for Watchdog & System timers */
- if (irt_num < 12)
- nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num));
-}
-
-static inline void
-nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en)
-{
- nlm_pic_write_irt_direct(base, irt, en, 0, 0, irq, hwt);
-}
-
-int nlm_irq_to_irt(int irq);
-
-#endif /* __ASSEMBLY__ */
-#endif /* _NLM_HAL_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
deleted file mode 100644
index 6bcf3952e556..000000000000
--- a/arch/mips/include/asm/netlogic/xlp-hal/sys.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __NLM_HAL_SYS_H__
-#define __NLM_HAL_SYS_H__
-
-/**
-* @file_name sys.h
-* @author Netlogic Microsystems
-* @brief HAL for System configuration registers
-*/
-#define SYS_CHIP_RESET 0x00
-#define SYS_POWER_ON_RESET_CFG 0x01
-#define SYS_EFUSE_DEVICE_CFG_STATUS0 0x02
-#define SYS_EFUSE_DEVICE_CFG_STATUS1 0x03
-#define SYS_EFUSE_DEVICE_CFG_STATUS2 0x04
-#define SYS_EFUSE_DEVICE_CFG3 0x05
-#define SYS_EFUSE_DEVICE_CFG4 0x06
-#define SYS_EFUSE_DEVICE_CFG5 0x07
-#define SYS_EFUSE_DEVICE_CFG6 0x08
-#define SYS_EFUSE_DEVICE_CFG7 0x09
-#define SYS_PLL_CTRL 0x0a
-#define SYS_CPU_RESET 0x0b
-#define SYS_CPU_NONCOHERENT_MODE 0x0d
-#define SYS_CORE_DFS_DIS_CTRL 0x0e
-#define SYS_CORE_DFS_RST_CTRL 0x0f
-#define SYS_CORE_DFS_BYP_CTRL 0x10
-#define SYS_CORE_DFS_PHA_CTRL 0x11
-#define SYS_CORE_DFS_DIV_INC_CTRL 0x12
-#define SYS_CORE_DFS_DIV_DEC_CTRL 0x13
-#define SYS_CORE_DFS_DIV_VALUE 0x14
-#define SYS_RESET 0x15
-#define SYS_DFS_DIS_CTRL 0x16
-#define SYS_DFS_RST_CTRL 0x17
-#define SYS_DFS_BYP_CTRL 0x18
-#define SYS_DFS_DIV_INC_CTRL 0x19
-#define SYS_DFS_DIV_DEC_CTRL 0x1a
-#define SYS_DFS_DIV_VALUE0 0x1b
-#define SYS_DFS_DIV_VALUE1 0x1c
-#define SYS_SENSE_AMP_DLY 0x1d
-#define SYS_SOC_SENSE_AMP_DLY 0x1e
-#define SYS_CTRL0 0x1f
-#define SYS_CTRL1 0x20
-#define SYS_TIMEOUT_BS1 0x21
-#define SYS_BYTE_SWAP 0x22
-#define SYS_VRM_VID 0x23
-#define SYS_PWR_RAM_CMD 0x24
-#define SYS_PWR_RAM_ADDR 0x25
-#define SYS_PWR_RAM_DATA0 0x26
-#define SYS_PWR_RAM_DATA1 0x27
-#define SYS_PWR_RAM_DATA2 0x28
-#define SYS_PWR_UCODE 0x29
-#define SYS_CPU0_PWR_STATUS 0x2a
-#define SYS_CPU1_PWR_STATUS 0x2b
-#define SYS_CPU2_PWR_STATUS 0x2c
-#define SYS_CPU3_PWR_STATUS 0x2d
-#define SYS_CPU4_PWR_STATUS 0x2e
-#define SYS_CPU5_PWR_STATUS 0x2f
-#define SYS_CPU6_PWR_STATUS 0x30
-#define SYS_CPU7_PWR_STATUS 0x31
-#define SYS_STATUS 0x32
-#define SYS_INT_POL 0x33
-#define SYS_INT_TYPE 0x34
-#define SYS_INT_STATUS 0x35
-#define SYS_INT_MASK0 0x36
-#define SYS_INT_MASK1 0x37
-#define SYS_UCO_S_ECC 0x38
-#define SYS_UCO_M_ECC 0x39
-#define SYS_UCO_ADDR 0x3a
-#define SYS_UCO_INSTR 0x3b
-#define SYS_MEM_BIST0 0x3c
-#define SYS_MEM_BIST1 0x3d
-#define SYS_MEM_BIST2 0x3e
-#define SYS_MEM_BIST3 0x3f
-#define SYS_MEM_BIST4 0x40
-#define SYS_MEM_BIST5 0x41
-#define SYS_MEM_BIST6 0x42
-#define SYS_MEM_BIST7 0x43
-#define SYS_MEM_BIST8 0x44
-#define SYS_MEM_BIST9 0x45
-#define SYS_MEM_BIST10 0x46
-#define SYS_MEM_BIST11 0x47
-#define SYS_MEM_BIST12 0x48
-#define SYS_SCRTCH0 0x49
-#define SYS_SCRTCH1 0x4a
-#define SYS_SCRTCH2 0x4b
-#define SYS_SCRTCH3 0x4c
-
-/* PLL registers XLP2XX */
-#define SYS_CPU_PLL_CTRL0(core) (0x1c0 + (core * 4))
-#define SYS_CPU_PLL_CTRL1(core) (0x1c1 + (core * 4))
-#define SYS_CPU_PLL_CTRL2(core) (0x1c2 + (core * 4))
-#define SYS_CPU_PLL_CTRL3(core) (0x1c3 + (core * 4))
-#define SYS_PLL_CTRL0 0x240
-#define SYS_PLL_CTRL1 0x241
-#define SYS_PLL_CTRL2 0x242
-#define SYS_PLL_CTRL3 0x243
-#define SYS_DMC_PLL_CTRL0 0x244
-#define SYS_DMC_PLL_CTRL1 0x245
-#define SYS_DMC_PLL_CTRL2 0x246
-#define SYS_DMC_PLL_CTRL3 0x247
-
-#define SYS_PLL_CTRL0_DEVX(x) (0x248 + (x) * 4)
-#define SYS_PLL_CTRL1_DEVX(x) (0x249 + (x) * 4)
-#define SYS_PLL_CTRL2_DEVX(x) (0x24a + (x) * 4)
-#define SYS_PLL_CTRL3_DEVX(x) (0x24b + (x) * 4)
-
-#define SYS_CPU_PLL_CHG_CTRL 0x288
-#define SYS_PLL_CHG_CTRL 0x289
-#define SYS_CLK_DEV_DIS 0x28a
-#define SYS_CLK_DEV_SEL 0x28b
-#define SYS_CLK_DEV_DIV 0x28c
-#define SYS_CLK_DEV_CHG 0x28d
-#define SYS_CLK_DEV_SEL_REG 0x28e
-#define SYS_CLK_DEV_DIV_REG 0x28f
-#define SYS_CPU_PLL_LOCK 0x29f
-#define SYS_SYS_PLL_LOCK 0x2a0
-#define SYS_PLL_MEM_CMD 0x2a1
-#define SYS_CPU_PLL_MEM_REQ 0x2a2
-#define SYS_SYS_PLL_MEM_REQ 0x2a3
-#define SYS_PLL_MEM_STAT 0x2a4
-
-/* PLL registers XLP9XX */
-#define SYS_9XX_CPU_PLL_CTRL0(core) (0xc0 + (core * 4))
-#define SYS_9XX_CPU_PLL_CTRL1(core) (0xc1 + (core * 4))
-#define SYS_9XX_CPU_PLL_CTRL2(core) (0xc2 + (core * 4))
-#define SYS_9XX_CPU_PLL_CTRL3(core) (0xc3 + (core * 4))
-#define SYS_9XX_DMC_PLL_CTRL0 0x140
-#define SYS_9XX_DMC_PLL_CTRL1 0x141
-#define SYS_9XX_DMC_PLL_CTRL2 0x142
-#define SYS_9XX_DMC_PLL_CTRL3 0x143
-#define SYS_9XX_PLL_CTRL0 0x144
-#define SYS_9XX_PLL_CTRL1 0x145
-#define SYS_9XX_PLL_CTRL2 0x146
-#define SYS_9XX_PLL_CTRL3 0x147
-
-#define SYS_9XX_PLL_CTRL0_DEVX(x) (0x148 + (x) * 4)
-#define SYS_9XX_PLL_CTRL1_DEVX(x) (0x149 + (x) * 4)
-#define SYS_9XX_PLL_CTRL2_DEVX(x) (0x14a + (x) * 4)
-#define SYS_9XX_PLL_CTRL3_DEVX(x) (0x14b + (x) * 4)
-
-#define SYS_9XX_CPU_PLL_CHG_CTRL 0x188
-#define SYS_9XX_PLL_CHG_CTRL 0x189
-#define SYS_9XX_CLK_DEV_DIS 0x18a
-#define SYS_9XX_CLK_DEV_SEL 0x18b
-#define SYS_9XX_CLK_DEV_DIV 0x18d
-#define SYS_9XX_CLK_DEV_CHG 0x18f
-
-#define SYS_9XX_CLK_DEV_SEL_REG 0x1a4
-#define SYS_9XX_CLK_DEV_DIV_REG 0x1a6
-
-/* Registers changed on 9XX */
-#define SYS_9XX_POWER_ON_RESET_CFG 0x00
-#define SYS_9XX_CHIP_RESET 0x01
-#define SYS_9XX_CPU_RESET 0x02
-#define SYS_9XX_CPU_NONCOHERENT_MODE 0x03
-
-/* XLP 9XX fuse block registers */
-#define FUSE_9XX_DEVCFG6 0xc6
-
-#ifndef __ASSEMBLY__
-
-#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r)
-#define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v)
-#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \
- XLP9XX_IO_SYS_OFFSET(node) : XLP_IO_SYS_OFFSET(node))
-#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
-
-/* XLP9XX fuse block */
-#define nlm_get_fuse_pcibase(node) \
- nlm_pcicfg_base(XLP9XX_IO_FUSE_OFFSET(node))
-#define nlm_get_fuse_regbase(node) \
- (nlm_get_fuse_pcibase(node) + XLP_IO_PCI_HDRSZ)
-
-#define nlm_get_clock_pcibase(node) \
- nlm_pcicfg_base(XLP9XX_IO_CLOCK_OFFSET(node))
-#define nlm_get_clock_regbase(node) \
- (nlm_get_clock_pcibase(node) + XLP_IO_PCI_HDRSZ)
-
-unsigned int nlm_get_pic_frequency(int node);
-#endif
-#endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/uart.h b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
deleted file mode 100644
index a6c54424dd95..000000000000
--- a/arch/mips/include/asm/netlogic/xlp-hal/uart.h
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __XLP_HAL_UART_H__
-#define __XLP_HAL_UART_H__
-
-/* UART Specific registers */
-#define UART_RX_DATA 0x00
-#define UART_TX_DATA 0x00
-
-#define UART_INT_EN 0x01
-#define UART_INT_ID 0x02
-#define UART_FIFO_CTL 0x02
-#define UART_LINE_CTL 0x03
-#define UART_MODEM_CTL 0x04
-#define UART_LINE_STS 0x05
-#define UART_MODEM_STS 0x06
-
-#define UART_DIVISOR0 0x00
-#define UART_DIVISOR1 0x01
-
-#define BASE_BAUD (XLP_IO_CLK/16)
-#define BAUD_DIVISOR(baud) (BASE_BAUD / baud)
-
-/* LCR mask values */
-#define LCR_5BITS 0x00
-#define LCR_6BITS 0x01
-#define LCR_7BITS 0x02
-#define LCR_8BITS 0x03
-#define LCR_STOPB 0x04
-#define LCR_PENAB 0x08
-#define LCR_PODD 0x00
-#define LCR_PEVEN 0x10
-#define LCR_PONE 0x20
-#define LCR_PZERO 0x30
-#define LCR_SBREAK 0x40
-#define LCR_EFR_ENABLE 0xbf
-#define LCR_DLAB 0x80
-
-/* MCR mask values */
-#define MCR_DTR 0x01
-#define MCR_RTS 0x02
-#define MCR_DRS 0x04
-#define MCR_IE 0x08
-#define MCR_LOOPBACK 0x10
-
-/* FCR mask values */
-#define FCR_RCV_RST 0x02
-#define FCR_XMT_RST 0x04
-#define FCR_RX_LOW 0x00
-#define FCR_RX_MEDL 0x40
-#define FCR_RX_MEDH 0x80
-#define FCR_RX_HIGH 0xc0
-
-/* IER mask values */
-#define IER_ERXRDY 0x1
-#define IER_ETXRDY 0x2
-#define IER_ERLS 0x4
-#define IER_EMSC 0x8
-
-#if !defined(LOCORE) && !defined(__ASSEMBLY__)
-
-#define nlm_read_uart_reg(b, r) nlm_read_reg(b, r)
-#define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v)
-#define nlm_get_uart_pcibase(node, inst) \
- nlm_pcicfg_base(cpu_is_xlp9xx() ? XLP9XX_IO_UART_OFFSET(node) : \
- XLP_IO_UART_OFFSET(node, inst))
-#define nlm_get_uart_regbase(node, inst) \
- (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
-
-static inline void
-nlm_uart_set_baudrate(uint64_t base, int baud)
-{
- uint32_t lcr;
-
- lcr = nlm_read_uart_reg(base, UART_LINE_CTL);
-
- /* enable divisor register, and write baud values */
- nlm_write_uart_reg(base, UART_LINE_CTL, lcr | (1 << 7));
- nlm_write_uart_reg(base, UART_DIVISOR0,
- (BAUD_DIVISOR(baud) & 0xff));
- nlm_write_uart_reg(base, UART_DIVISOR1,
- ((BAUD_DIVISOR(baud) >> 8) & 0xff));
-
- /* restore default lcr */
- nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
-}
-
-static inline void
-nlm_uart_outbyte(uint64_t base, char c)
-{
- uint32_t lsr;
-
- for (;;) {
- lsr = nlm_read_uart_reg(base, UART_LINE_STS);
- if (lsr & 0x20)
- break;
- }
-
- nlm_write_uart_reg(base, UART_TX_DATA, (int)c);
-}
-
-static inline char
-nlm_uart_inbyte(uint64_t base)
-{
- int data, lsr;
-
- for (;;) {
- lsr = nlm_read_uart_reg(base, UART_LINE_STS);
- if (lsr & 0x80) { /* parity/frame/break-error - push a zero */
- data = 0;
- break;
- }
- if (lsr & 0x01) { /* Rx data */
- data = nlm_read_uart_reg(base, UART_RX_DATA);
- break;
- }
- }
-
- return (char)data;
-}
-
-static inline int
-nlm_uart_init(uint64_t base, int baud, int databits, int stopbits,
- int parity, int int_en, int loopback)
-{
- uint32_t lcr;
-
- lcr = 0;
- if (databits >= 8)
- lcr |= LCR_8BITS;
- else if (databits == 7)
- lcr |= LCR_7BITS;
- else if (databits == 6)
- lcr |= LCR_6BITS;
- else
- lcr |= LCR_5BITS;
-
- if (stopbits > 1)
- lcr |= LCR_STOPB;
-
- lcr |= parity << 3;
-
- /* setup default lcr */
- nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
-
- /* Reset the FIFOs */
- nlm_write_uart_reg(base, UART_LINE_CTL, FCR_RCV_RST | FCR_XMT_RST);
-
- nlm_uart_set_baudrate(base, baud);
-
- if (loopback)
- nlm_write_uart_reg(base, UART_MODEM_CTL, 0x1f);
-
- if (int_en)
- nlm_write_uart_reg(base, UART_INT_EN, IER_ERXRDY | IER_ETXRDY);
-
- return 0;
-}
-#endif /* !LOCORE && !__ASSEMBLY__ */
-#endif /* __XLP_HAL_UART_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
deleted file mode 100644
index feb6ed807ec6..000000000000
--- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _NLM_HAL_XLP_H
-#define _NLM_HAL_XLP_H
-
-#define PIC_UART_0_IRQ 17
-#define PIC_UART_1_IRQ 18
-
-#define PIC_PCIE_LINK_LEGACY_IRQ_BASE 19
-#define PIC_PCIE_LINK_LEGACY_IRQ(i) (19 + (i))
-
-#define PIC_EHCI_0_IRQ 23
-#define PIC_EHCI_1_IRQ 24
-#define PIC_OHCI_0_IRQ 25
-#define PIC_OHCI_1_IRQ 26
-#define PIC_OHCI_2_IRQ 27
-#define PIC_OHCI_3_IRQ 28
-#define PIC_2XX_XHCI_0_IRQ 23
-#define PIC_2XX_XHCI_1_IRQ 24
-#define PIC_2XX_XHCI_2_IRQ 25
-#define PIC_9XX_XHCI_0_IRQ 23
-#define PIC_9XX_XHCI_1_IRQ 24
-#define PIC_9XX_XHCI_2_IRQ 25
-
-#define PIC_MMC_IRQ 29
-#define PIC_I2C_0_IRQ 30
-#define PIC_I2C_1_IRQ 31
-#define PIC_I2C_2_IRQ 32
-#define PIC_I2C_3_IRQ 33
-#define PIC_SPI_IRQ 34
-#define PIC_NAND_IRQ 37
-#define PIC_SATA_IRQ 38
-#define PIC_GPIO_IRQ 39
-
-#define PIC_PCIE_LINK_MSI_IRQ_BASE 44 /* 44 - 47 MSI IRQ */
-#define PIC_PCIE_LINK_MSI_IRQ(i) (44 + (i))
-
-/* MSI-X with second link-level dispatch */
-#define PIC_PCIE_MSIX_IRQ_BASE 48 /* 48 - 51 MSI-X IRQ */
-#define PIC_PCIE_MSIX_IRQ(i) (48 + (i))
-
-/* XLP9xx and XLP8xx has 128 and 32 MSIX vectors respectively */
-#define NLM_MSIX_VEC_BASE 96 /* 96 - 223 - MSIX mapped */
-#define NLM_MSI_VEC_BASE 224 /* 224 -351 - MSI mapped */
-
-#define NLM_PIC_INDIRECT_VEC_BASE 512
-#define NLM_GPIO_VEC_BASE 768
-
-#define PIC_IRQ_BASE 8
-#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE
-#define PIC_IRT_LAST_IRQ 63
-
-#ifndef __ASSEMBLY__
-
-/* SMP support functions */
-void xlp_boot_core0_siblings(void);
-void xlp_wakeup_secondary_cpus(void);
-
-void xlp_mmu_init(void);
-void nlm_hal_init(void);
-int nlm_get_dram_map(int node, uint64_t *dram_map, int nentries);
-
-struct pci_dev;
-int xlp_socdev_to_node(const struct pci_dev *dev);
-
-/* Device tree related */
-void xlp_early_init_devtree(void);
-void *xlp_dt_init(void *fdtp);
-
-static inline int cpu_is_xlpii(void)
-{
- int chip = read_c0_prid() & PRID_IMP_MASK;
-
- return chip == PRID_IMP_NETLOGIC_XLP2XX ||
- chip == PRID_IMP_NETLOGIC_XLP9XX ||
- chip == PRID_IMP_NETLOGIC_XLP5XX;
-}
-
-static inline int cpu_is_xlp9xx(void)
-{
- int chip = read_c0_prid() & PRID_IMP_MASK;
-
- return chip == PRID_IMP_NETLOGIC_XLP9XX ||
- chip == PRID_IMP_NETLOGIC_XLP5XX;
-}
-#endif /* !__ASSEMBLY__ */
-#endif /* _ASM_NLM_XLP_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/bridge.h b/arch/mips/include/asm/netlogic/xlr/bridge.h
deleted file mode 100644
index 2d02428c4f1b..000000000000
--- a/arch/mips/include/asm/netlogic/xlr/bridge.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Copyright (c) 2003-2012 Broadcom Corporation
- * All Rights Reserved
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the Broadcom
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _ASM_NLM_BRIDGE_H_
-#define _ASM_NLM_BRIDGE_H_
-
-#define BRIDGE_DRAM_0_BAR 0
-#define BRIDGE_DRAM_1_BAR 1
-#define BRIDGE_DRAM_2_BAR 2
-#define BRIDGE_DRAM_3_BAR 3
-#define BRIDGE_DRAM_4_BAR 4
-#define BRIDGE_DRAM_5_BAR 5
-#define BRIDGE_DRAM_6_BAR 6
-#define BRIDGE_DRAM_7_BAR 7
-#define BRIDGE_DRAM_CHN_0_MTR_0_BAR 8
-#define BRIDGE_DRAM_CHN_0_MTR_1_BAR 9
-#define BRIDGE_DRAM_CHN_0_MTR_2_BAR 10
-#define BRIDGE_DRAM_CHN_0_MTR_3_BAR 11
-#define BRIDGE_DRAM_CHN_0_MTR_4_BAR 12
-#define BRIDGE_DRAM_CHN_0_MTR_5_BAR 13
-#define BRIDGE_DRAM_CHN_0_MTR_6_BAR 14
-#define BRIDGE_DRAM_CHN_0_MTR_7_BAR 15
-#define BRIDGE_DRAM_CHN_1_MTR_0_BAR 16
-#define BRIDGE_DRAM_CHN_1_MTR_1_BAR 17
-#define BRIDGE_DRAM_CHN_1_MTR_2_BAR 18
-#define BRIDGE_DRAM_CHN_1_MTR_3_BAR 19
-#define BRIDGE_DRAM_CHN_1_MTR_4_BAR 20
-#define BRIDGE_DRAM_CHN_1_MTR_5_BAR 21
-#define BRIDGE_DRAM_CHN_1_MTR_6_BAR 22
-#define BRIDGE_DRAM_CHN_1_MTR_7_BAR 23
-#define BRIDGE_CFG_BAR 24
-#define BRIDGE_PHNX_IO_BAR 25
-#define BRIDGE_FLASH_BAR 26
-#define BRIDGE_SRAM_BAR 27
-#define BRIDGE_HTMEM_BAR 28
-#define BRIDGE_HTINT_BAR 29
-#define BRIDGE_HTPIC_BAR 30
-#define BRIDGE_HTSM_BAR 31
-#define BRIDGE_HTIO_BAR 32
-#define BRIDGE_HTCFG_BAR 33
-#define BRIDGE_PCIXCFG_BAR 34
-#define BRIDGE_PCIXMEM_BAR 35
-#define BRIDGE_PCIXIO_BAR 36
-#define BRIDGE_DEVICE_MASK 37
-#define BRIDGE_AERR_INTR_LOG1 38
-#define BRIDGE_AERR_INTR_LOG2 39
-#define BRIDGE_AERR_INTR_LOG3 40
-#define BRIDGE_AERR_DEV_STAT 41
-#define BRIDGE_AERR1_LOG1 42
-#define BRIDGE_AERR1_LOG2 43
-#define BRIDGE_AERR1_LOG3 44
-#define BRIDGE_AERR1_DEV_STAT 45
-#define BRIDGE_AERR_INTR_EN 46
-#define BRIDGE_AERR_UPG 47
-#define BRIDGE_AERR_CLEAR 48
-#define BRIDGE_AERR1_CLEAR 49
-#define BRIDGE_SBE_COUNTS 50
-#define BRIDGE_DBE_COUNTS 51
-#define BRIDGE_BITERR_INT_EN 52
-
-#define BRIDGE_SYS2IO_CREDITS 53
-#define BRIDGE_EVNT_CNT_CTRL1 54
-#define BRIDGE_EVNT_COUNTER1 55
-#define BRIDGE_EVNT_CNT_CTRL2 56
-#define BRIDGE_EVNT_COUNTER2 57
-#define BRIDGE_RESERVED1 58
-
-#define BRIDGE_DEFEATURE 59
-#define BRIDGE_SCRATCH0 60
-#define BRIDGE_SCRATCH1 61
-#define BRIDGE_SCRATCH2 62
-#define BRIDGE_SCRATCH3 63
-
-#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/flash.h b/arch/mips/include/asm/netlogic/xlr/flash.h
deleted file mode 100644
index f8aca5472b6c..000000000000
--- a/arch/mips/include/asm/netlogic/xlr/flash.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (c) 2003-2012 Broadcom Corporation
- * All Rights Reserved
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the Broadcom
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _ASM_NLM_FLASH_H_
-#define _ASM_NLM_FLASH_H_
-
-#define FLASH_CSBASE_ADDR(cs) (cs)
-#define FLASH_CSADDR_MASK(cs) (0x10 + (cs))
-#define FLASH_CSDEV_PARM(cs) (0x20 + (cs))
-#define FLASH_CSTIME_PARMA(cs) (0x30 + (cs))
-#define FLASH_CSTIME_PARMB(cs) (0x40 + (cs))
-
-#define FLASH_INT_MASK 0x50
-#define FLASH_INT_STATUS 0x60
-#define FLASH_ERROR_STATUS 0x70
-#define FLASH_ERROR_ADDR 0x80
-
-#define FLASH_NAND_CLE(cs) (0x90 + (cs))
-#define FLASH_NAND_ALE(cs) (0xa0 + (cs))
-
-#define FLASH_NAND_CSDEV_PARAM 0x000041e6
-#define FLASH_NAND_CSTIME_PARAMA 0x4f400e22
-#define FLASH_NAND_CSTIME_PARAMB 0x000083cf
-
-#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/fmn.h b/arch/mips/include/asm/netlogic/xlr/fmn.h
deleted file mode 100644
index d79c68fa78d9..000000000000
--- a/arch/mips/include/asm/netlogic/xlr/fmn.h
+++ /dev/null
@@ -1,365 +0,0 @@
-/*
- * Copyright (c) 2003-2012 Broadcom Corporation
- * All Rights Reserved
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the Broadcom
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _NLM_FMN_H_
-#define _NLM_FMN_H_
-
-#include <asm/netlogic/mips-extns.h> /* for COP2 access */
-
-/* Station IDs */
-#define FMN_STNID_CPU0 0x00
-#define FMN_STNID_CPU1 0x08
-#define FMN_STNID_CPU2 0x10
-#define FMN_STNID_CPU3 0x18
-#define FMN_STNID_CPU4 0x20
-#define FMN_STNID_CPU5 0x28
-#define FMN_STNID_CPU6 0x30
-#define FMN_STNID_CPU7 0x38
-
-#define FMN_STNID_XGS0_TX 64
-#define FMN_STNID_XMAC0_00_TX 64
-#define FMN_STNID_XMAC0_01_TX 65
-#define FMN_STNID_XMAC0_02_TX 66
-#define FMN_STNID_XMAC0_03_TX 67
-#define FMN_STNID_XMAC0_04_TX 68
-#define FMN_STNID_XMAC0_05_TX 69
-#define FMN_STNID_XMAC0_06_TX 70
-#define FMN_STNID_XMAC0_07_TX 71
-#define FMN_STNID_XMAC0_08_TX 72
-#define FMN_STNID_XMAC0_09_TX 73
-#define FMN_STNID_XMAC0_10_TX 74
-#define FMN_STNID_XMAC0_11_TX 75
-#define FMN_STNID_XMAC0_12_TX 76
-#define FMN_STNID_XMAC0_13_TX 77
-#define FMN_STNID_XMAC0_14_TX 78
-#define FMN_STNID_XMAC0_15_TX 79
-
-#define FMN_STNID_XGS1_TX 80
-#define FMN_STNID_XMAC1_00_TX 80
-#define FMN_STNID_XMAC1_01_TX 81
-#define FMN_STNID_XMAC1_02_TX 82
-#define FMN_STNID_XMAC1_03_TX 83
-#define FMN_STNID_XMAC1_04_TX 84
-#define FMN_STNID_XMAC1_05_TX 85
-#define FMN_STNID_XMAC1_06_TX 86
-#define FMN_STNID_XMAC1_07_TX 87
-#define FMN_STNID_XMAC1_08_TX 88
-#define FMN_STNID_XMAC1_09_TX 89
-#define FMN_STNID_XMAC1_10_TX 90
-#define FMN_STNID_XMAC1_11_TX 91
-#define FMN_STNID_XMAC1_12_TX 92
-#define FMN_STNID_XMAC1_13_TX 93
-#define FMN_STNID_XMAC1_14_TX 94
-#define FMN_STNID_XMAC1_15_TX 95
-
-#define FMN_STNID_GMAC 96
-#define FMN_STNID_GMACJFR_0 96
-#define FMN_STNID_GMACRFR_0 97
-#define FMN_STNID_GMACTX0 98
-#define FMN_STNID_GMACTX1 99
-#define FMN_STNID_GMACTX2 100
-#define FMN_STNID_GMACTX3 101
-#define FMN_STNID_GMACJFR_1 102
-#define FMN_STNID_GMACRFR_1 103
-
-#define FMN_STNID_DMA 104
-#define FMN_STNID_DMA_0 104
-#define FMN_STNID_DMA_1 105
-#define FMN_STNID_DMA_2 106
-#define FMN_STNID_DMA_3 107
-
-#define FMN_STNID_XGS0FR 112
-#define FMN_STNID_XMAC0JFR 112
-#define FMN_STNID_XMAC0RFR 113
-
-#define FMN_STNID_XGS1FR 114
-#define FMN_STNID_XMAC1JFR 114
-#define FMN_STNID_XMAC1RFR 115
-#define FMN_STNID_SEC 120
-#define FMN_STNID_SEC0 120
-#define FMN_STNID_SEC1 121
-#define FMN_STNID_SEC2 122
-#define FMN_STNID_SEC3 123
-#define FMN_STNID_PK0 124
-#define FMN_STNID_SEC_RSA 124
-#define FMN_STNID_SEC_RSVD0 125
-#define FMN_STNID_SEC_RSVD1 126
-#define FMN_STNID_SEC_RSVD2 127
-
-#define FMN_STNID_GMAC1 80
-#define FMN_STNID_GMAC1_FR_0 81
-#define FMN_STNID_GMAC1_TX0 82
-#define FMN_STNID_GMAC1_TX1 83
-#define FMN_STNID_GMAC1_TX2 84
-#define FMN_STNID_GMAC1_TX3 85
-#define FMN_STNID_GMAC1_FR_1 87
-#define FMN_STNID_GMAC0 96
-#define FMN_STNID_GMAC0_FR_0 97
-#define FMN_STNID_GMAC0_TX0 98
-#define FMN_STNID_GMAC0_TX1 99
-#define FMN_STNID_GMAC0_TX2 100
-#define FMN_STNID_GMAC0_TX3 101
-#define FMN_STNID_GMAC0_FR_1 103
-#define FMN_STNID_CMP_0 108
-#define FMN_STNID_CMP_1 109
-#define FMN_STNID_CMP_2 110
-#define FMN_STNID_CMP_3 111
-#define FMN_STNID_PCIE_0 116
-#define FMN_STNID_PCIE_1 117
-#define FMN_STNID_PCIE_2 118
-#define FMN_STNID_PCIE_3 119
-#define FMN_STNID_XLS_PK0 121
-
-#define nlm_read_c2_cc0(s) __read_32bit_c2_register($16, s)
-#define nlm_read_c2_cc1(s) __read_32bit_c2_register($17, s)
-#define nlm_read_c2_cc2(s) __read_32bit_c2_register($18, s)
-#define nlm_read_c2_cc3(s) __read_32bit_c2_register($19, s)
-#define nlm_read_c2_cc4(s) __read_32bit_c2_register($20, s)
-#define nlm_read_c2_cc5(s) __read_32bit_c2_register($21, s)
-#define nlm_read_c2_cc6(s) __read_32bit_c2_register($22, s)
-#define nlm_read_c2_cc7(s) __read_32bit_c2_register($23, s)
-#define nlm_read_c2_cc8(s) __read_32bit_c2_register($24, s)
-#define nlm_read_c2_cc9(s) __read_32bit_c2_register($25, s)
-#define nlm_read_c2_cc10(s) __read_32bit_c2_register($26, s)
-#define nlm_read_c2_cc11(s) __read_32bit_c2_register($27, s)
-#define nlm_read_c2_cc12(s) __read_32bit_c2_register($28, s)
-#define nlm_read_c2_cc13(s) __read_32bit_c2_register($29, s)
-#define nlm_read_c2_cc14(s) __read_32bit_c2_register($30, s)
-#define nlm_read_c2_cc15(s) __read_32bit_c2_register($31, s)
-
-#define nlm_write_c2_cc0(s, v) __write_32bit_c2_register($16, s, v)
-#define nlm_write_c2_cc1(s, v) __write_32bit_c2_register($17, s, v)
-#define nlm_write_c2_cc2(s, v) __write_32bit_c2_register($18, s, v)
-#define nlm_write_c2_cc3(s, v) __write_32bit_c2_register($19, s, v)
-#define nlm_write_c2_cc4(s, v) __write_32bit_c2_register($20, s, v)
-#define nlm_write_c2_cc5(s, v) __write_32bit_c2_register($21, s, v)
-#define nlm_write_c2_cc6(s, v) __write_32bit_c2_register($22, s, v)
-#define nlm_write_c2_cc7(s, v) __write_32bit_c2_register($23, s, v)
-#define nlm_write_c2_cc8(s, v) __write_32bit_c2_register($24, s, v)
-#define nlm_write_c2_cc9(s, v) __write_32bit_c2_register($25, s, v)
-#define nlm_write_c2_cc10(s, v) __write_32bit_c2_register($26, s, v)
-#define nlm_write_c2_cc11(s, v) __write_32bit_c2_register($27, s, v)
-#define nlm_write_c2_cc12(s, v) __write_32bit_c2_register($28, s, v)
-#define nlm_write_c2_cc13(s, v) __write_32bit_c2_register($29, s, v)
-#define nlm_write_c2_cc14(s, v) __write_32bit_c2_register($30, s, v)
-#define nlm_write_c2_cc15(s, v) __write_32bit_c2_register($31, s, v)
-
-#define nlm_read_c2_status0() __read_32bit_c2_register($2, 0)
-#define nlm_write_c2_status0(v) __write_32bit_c2_register($2, 0, v)
-#define nlm_read_c2_status1() __read_32bit_c2_register($2, 1)
-#define nlm_write_c2_status1(v) __write_32bit_c2_register($2, 1, v)
-#define nlm_read_c2_status(sel) __read_32bit_c2_register($2, 0)
-#define nlm_read_c2_config() __read_32bit_c2_register($3, 0)
-#define nlm_write_c2_config(v) __write_32bit_c2_register($3, 0, v)
-#define nlm_read_c2_bucksize(b) __read_32bit_c2_register($4, b)
-#define nlm_write_c2_bucksize(b, v) __write_32bit_c2_register($4, b, v)
-
-#define nlm_read_c2_rx_msg0() __read_64bit_c2_register($1, 0)
-#define nlm_read_c2_rx_msg1() __read_64bit_c2_register($1, 1)
-#define nlm_read_c2_rx_msg2() __read_64bit_c2_register($1, 2)
-#define nlm_read_c2_rx_msg3() __read_64bit_c2_register($1, 3)
-
-#define nlm_write_c2_tx_msg0(v) __write_64bit_c2_register($0, 0, v)
-#define nlm_write_c2_tx_msg1(v) __write_64bit_c2_register($0, 1, v)
-#define nlm_write_c2_tx_msg2(v) __write_64bit_c2_register($0, 2, v)
-#define nlm_write_c2_tx_msg3(v) __write_64bit_c2_register($0, 3, v)
-
-#define FMN_STN_RX_QSIZE 256
-#define FMN_NSTATIONS 128
-#define FMN_CORE_NBUCKETS 8
-
-static inline void nlm_msgsnd(unsigned int stid)
-{
- __asm__ volatile (
- ".set push\n"
- ".set noreorder\n"
- ".set noat\n"
- "move $1, %0\n"
- "c2 0x10001\n" /* msgsnd $1 */
- ".set pop\n"
- : : "r" (stid) : "$1"
- );
-}
-
-static inline void nlm_msgld(unsigned int pri)
-{
- __asm__ volatile (
- ".set push\n"
- ".set noreorder\n"
- ".set noat\n"
- "move $1, %0\n"
- "c2 0x10002\n" /* msgld $1 */
- ".set pop\n"
- : : "r" (pri) : "$1"
- );
-}
-
-static inline void nlm_msgwait(unsigned int mask)
-{
- __asm__ volatile (
- ".set push\n"
- ".set noreorder\n"
- ".set noat\n"
- "move $8, %0\n"
- "c2 0x10003\n" /* msgwait $1 */
- ".set pop\n"
- : : "r" (mask) : "$1"
- );
-}
-
-/*
- * Disable interrupts and enable COP2 access
- */
-static inline uint32_t nlm_cop2_enable_irqsave(void)
-{
- uint32_t sr = read_c0_status();
-
- write_c0_status((sr & ~ST0_IE) | ST0_CU2);
- return sr;
-}
-
-static inline void nlm_cop2_disable_irqrestore(uint32_t sr)
-{
- write_c0_status(sr);
-}
-
-static inline void nlm_fmn_setup_intr(int irq, unsigned int tmask)
-{
- uint32_t config;
-
- config = (1 << 24) /* interrupt water mark - 1 msg */
- | (irq << 16) /* irq */
- | (tmask << 8) /* thread mask */
- | 0x2; /* enable watermark intr, disable empty intr */
- nlm_write_c2_config(config);
-}
-
-struct nlm_fmn_msg {
- uint64_t msg0;
- uint64_t msg1;
- uint64_t msg2;
- uint64_t msg3;
-};
-
-static inline int nlm_fmn_send(unsigned int size, unsigned int code,
- unsigned int stid, struct nlm_fmn_msg *msg)
-{
- unsigned int dest;
- uint32_t status;
- int i;
-
- /*
- * Make sure that all the writes pending at the cpu are flushed.
- * Any writes pending on CPU will not be see by devices. L1/L2
- * caches are coherent with IO, so no cache flush needed.
- */
- __asm __volatile("sync");
-
- /* Load TX message buffers */
- nlm_write_c2_tx_msg0(msg->msg0);
- nlm_write_c2_tx_msg1(msg->msg1);
- nlm_write_c2_tx_msg2(msg->msg2);
- nlm_write_c2_tx_msg3(msg->msg3);
- dest = ((size - 1) << 16) | (code << 8) | stid;
-
- /*
- * Retry a few times on credit fail, this should be a
- * transient condition, unless there is a configuration
- * failure, or the receiver is stuck.
- */
- for (i = 0; i < 8; i++) {
- nlm_msgsnd(dest);
- status = nlm_read_c2_status0();
- if ((status & 0x4) == 0)
- return 0;
- }
-
- /* If there is a credit failure, return error */
- return status & 0x06;
-}
-
-static inline int nlm_fmn_receive(int bucket, int *size, int *code, int *stid,
- struct nlm_fmn_msg *msg)
-{
- uint32_t status, tmp;
-
- nlm_msgld(bucket);
-
- /* wait for load pending to clear */
- do {
- status = nlm_read_c2_status0();
- } while ((status & 0x08) != 0);
-
- /* receive error bits */
- tmp = status & 0x30;
- if (tmp != 0)
- return tmp;
-
- *size = ((status & 0xc0) >> 6) + 1;
- *code = (status & 0xff00) >> 8;
- *stid = (status & 0x7f0000) >> 16;
- msg->msg0 = nlm_read_c2_rx_msg0();
- msg->msg1 = nlm_read_c2_rx_msg1();
- msg->msg2 = nlm_read_c2_rx_msg2();
- msg->msg3 = nlm_read_c2_rx_msg3();
-
- return 0;
-}
-
-struct xlr_fmn_info {
- int num_buckets;
- int start_stn_id;
- int end_stn_id;
- int credit_config[128];
-};
-
-struct xlr_board_fmn_config {
- int bucket_size[128]; /* size of buckets for all stations */
- struct xlr_fmn_info cpu[8];
- struct xlr_fmn_info gmac[2];
- struct xlr_fmn_info dma;
- struct xlr_fmn_info cmp;
- struct xlr_fmn_info sae;
- struct xlr_fmn_info xgmac[2];
-};
-
-extern int nlm_register_fmn_handler(int start, int end,
- void (*fn)(int, int, int, int, struct nlm_fmn_msg *, void *),
- void *arg);
-extern void xlr_percpu_fmn_init(void);
-extern void nlm_setup_fmn_irq(void);
-extern void xlr_board_info_setup(void);
-
-extern struct xlr_board_fmn_config xlr_board_fmn_config;
-#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/gpio.h b/arch/mips/include/asm/netlogic/xlr/gpio.h
deleted file mode 100644
index 8492e835b110..000000000000
--- a/arch/mips/include/asm/netlogic/xlr/gpio.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _ASM_NLM_GPIO_H
-#define _ASM_NLM_GPIO_H
-
-#define GPIO_INT_EN_REG 0
-#define GPIO_INPUT_INVERSION_REG 1
-#define GPIO_IO_DIR_REG 2
-#define GPIO_IO_DATA_WR_REG 3
-#define GPIO_IO_DATA_RD_REG 4
-
-#define GPIO_SWRESET_REG 8
-#define GPIO_DRAM1_CNTRL_REG 9
-#define GPIO_DRAM1_RATIO_REG 10
-#define GPIO_DRAM1_RESET_REG 11
-#define GPIO_DRAM1_STATUS_REG 12
-#define GPIO_DRAM2_CNTRL_REG 13
-#define GPIO_DRAM2_RATIO_REG 14
-#define GPIO_DRAM2_RESET_REG 15
-#define GPIO_DRAM2_STATUS_REG 16
-
-#define GPIO_PWRON_RESET_CFG_REG 21
-#define GPIO_BIST_ALL_GO_STATUS_REG 24
-#define GPIO_BIST_CPU_GO_STATUS_REG 25
-#define GPIO_BIST_DEV_GO_STATUS_REG 26
-
-#define GPIO_FUSE_BANK_REG 35
-#define GPIO_CPU_RESET_REG 40
-#define GPIO_RNG_REG 43
-
-#define PWRON_RESET_PCMCIA_BOOT 17
-
-#define GPIO_LED_BITMAP 0x1700000
-#define GPIO_LED_0_SHIFT 20
-#define GPIO_LED_1_SHIFT 24
-
-#define GPIO_LED_OUTPUT_CODE_RESET 0x01
-#define GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02
-#define GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03
-#define GPIO_LED_OUTPUT_CODE_MAIN 0x04
-
-#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/iomap.h b/arch/mips/include/asm/netlogic/xlr/iomap.h
deleted file mode 100644
index ff4533d6ee64..000000000000
--- a/arch/mips/include/asm/netlogic/xlr/iomap.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _ASM_NLM_IOMAP_H
-#define _ASM_NLM_IOMAP_H
-
-#define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000)
-#define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000
-#define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000
-#define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000
-#define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000
-#define NETLOGIC_IO_PIC_OFFSET 0x08000
-#define NETLOGIC_IO_UART_0_OFFSET 0x14000
-#define NETLOGIC_IO_UART_1_OFFSET 0x15100
-
-#define NETLOGIC_IO_SIZE 0x1000
-
-#define NETLOGIC_IO_BRIDGE_OFFSET 0x00000
-
-#define NETLOGIC_IO_RLD2_CHN0_OFFSET 0x05000
-#define NETLOGIC_IO_RLD2_CHN1_OFFSET 0x06000
-
-#define NETLOGIC_IO_SRAM_OFFSET 0x07000
-
-#define NETLOGIC_IO_PCIX_OFFSET 0x09000
-#define NETLOGIC_IO_HT_OFFSET 0x0A000
-
-#define NETLOGIC_IO_SECURITY_OFFSET 0x0B000
-
-#define NETLOGIC_IO_GMAC_0_OFFSET 0x0C000
-#define NETLOGIC_IO_GMAC_1_OFFSET 0x0D000
-#define NETLOGIC_IO_GMAC_2_OFFSET 0x0E000
-#define NETLOGIC_IO_GMAC_3_OFFSET 0x0F000
-
-/* XLS devices */
-#define NETLOGIC_IO_GMAC_4_OFFSET 0x20000
-#define NETLOGIC_IO_GMAC_5_OFFSET 0x21000
-#define NETLOGIC_IO_GMAC_6_OFFSET 0x22000
-#define NETLOGIC_IO_GMAC_7_OFFSET 0x23000
-
-#define NETLOGIC_IO_PCIE_0_OFFSET 0x1E000
-#define NETLOGIC_IO_PCIE_1_OFFSET 0x1F000
-#define NETLOGIC_IO_SRIO_0_OFFSET 0x1E000
-#define NETLOGIC_IO_SRIO_1_OFFSET 0x1F000
-
-#define NETLOGIC_IO_USB_0_OFFSET 0x24000
-#define NETLOGIC_IO_USB_1_OFFSET 0x25000
-
-#define NETLOGIC_IO_COMP_OFFSET 0x1D000
-/* end XLS devices */
-
-/* XLR devices */
-#define NETLOGIC_IO_SPI4_0_OFFSET 0x10000
-#define NETLOGIC_IO_XGMAC_0_OFFSET 0x11000
-#define NETLOGIC_IO_SPI4_1_OFFSET 0x12000
-#define NETLOGIC_IO_XGMAC_1_OFFSET 0x13000
-/* end XLR devices */
-
-#define NETLOGIC_IO_I2C_0_OFFSET 0x16000
-#define NETLOGIC_IO_I2C_1_OFFSET 0x17000
-
-#define NETLOGIC_IO_GPIO_OFFSET 0x18000
-#define NETLOGIC_IO_FLASH_OFFSET 0x19000
-#define NETLOGIC_IO_TB_OFFSET 0x1C000
-
-#define NETLOGIC_CPLD_OFFSET KSEG1ADDR(0x1d840000)
-
-/*
- * Base Address (Virtual) of the PCI Config address space
- * For now, choose 256M phys in kseg1 = 0xA0000000 + (1<<28)
- * Config space spans 256 (num of buses) * 256 (num functions) * 256 bytes
- * ie 1<<24 = 16M
- */
-#define DEFAULT_PCI_CONFIG_BASE 0x18000000
-#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000
-#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000
-
-#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/msidef.h b/arch/mips/include/asm/netlogic/xlr/msidef.h
deleted file mode 100644
index c95d18edf12f..000000000000
--- a/arch/mips/include/asm/netlogic/xlr/msidef.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef ASM_RMI_MSIDEF_H
-#define ASM_RMI_MSIDEF_H
-
-/*
- * Constants for Intel APIC based MSI messages.
- * Adapted for the RMI XLR using identical defines
- */
-
-/*
- * Shifts for MSI data
- */
-
-#define MSI_DATA_VECTOR_SHIFT 0
-#define MSI_DATA_VECTOR_MASK 0x000000ff
-#define MSI_DATA_VECTOR(v) (((v) << MSI_DATA_VECTOR_SHIFT) & \
- MSI_DATA_VECTOR_MASK)
-
-#define MSI_DATA_DELIVERY_MODE_SHIFT 8
-#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_MODE_SHIFT)
-#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_MODE_SHIFT)
-
-#define MSI_DATA_LEVEL_SHIFT 14
-#define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT)
-#define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT)
-
-#define MSI_DATA_TRIGGER_SHIFT 15
-#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT)
-#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT)
-
-/*
- * Shift/mask fields for msi address
- */
-
-#define MSI_ADDR_BASE_HI 0
-#define MSI_ADDR_BASE_LO 0xfee00000
-
-#define MSI_ADDR_DEST_MODE_SHIFT 2
-#define MSI_ADDR_DEST_MODE_PHYSICAL (0 << MSI_ADDR_DEST_MODE_SHIFT)
-#define MSI_ADDR_DEST_MODE_LOGICAL (1 << MSI_ADDR_DEST_MODE_SHIFT)
-
-#define MSI_ADDR_REDIRECTION_SHIFT 3
-#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT)
-#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT)
-
-#define MSI_ADDR_DEST_ID_SHIFT 12
-#define MSI_ADDR_DEST_ID_MASK 0x00ffff0
-#define MSI_ADDR_DEST_ID(dest) (((dest) << MSI_ADDR_DEST_ID_SHIFT) & \
- MSI_ADDR_DEST_ID_MASK)
-
-#endif /* ASM_RMI_MSIDEF_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h
deleted file mode 100644
index 3c80a75233bd..000000000000
--- a/arch/mips/include/asm/netlogic/xlr/pic.h
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _ASM_NLM_XLR_PIC_H
-#define _ASM_NLM_XLR_PIC_H
-
-#define PIC_CLK_HZ 66666666
-#define pic_timer_freq() PIC_CLK_HZ
-
-/* PIC hardware interrupt numbers */
-#define PIC_IRT_WD_INDEX 0
-#define PIC_IRT_TIMER_0_INDEX 1
-#define PIC_IRT_TIMER_INDEX(i) ((i) + PIC_IRT_TIMER_0_INDEX)
-#define PIC_IRT_TIMER_1_INDEX 2
-#define PIC_IRT_TIMER_2_INDEX 3
-#define PIC_IRT_TIMER_3_INDEX 4
-#define PIC_IRT_TIMER_4_INDEX 5
-#define PIC_IRT_TIMER_5_INDEX 6
-#define PIC_IRT_TIMER_6_INDEX 7
-#define PIC_IRT_TIMER_7_INDEX 8
-#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX
-#define PIC_IRT_UART_0_INDEX 9
-#define PIC_IRT_UART_1_INDEX 10
-#define PIC_IRT_I2C_0_INDEX 11
-#define PIC_IRT_I2C_1_INDEX 12
-#define PIC_IRT_PCMCIA_INDEX 13
-#define PIC_IRT_GPIO_INDEX 14
-#define PIC_IRT_HYPER_INDEX 15
-#define PIC_IRT_PCIX_INDEX 16
-/* XLS */
-#define PIC_IRT_CDE_INDEX 15
-#define PIC_IRT_BRIDGE_TB_XLS_INDEX 16
-/* XLS */
-#define PIC_IRT_GMAC0_INDEX 17
-#define PIC_IRT_GMAC1_INDEX 18
-#define PIC_IRT_GMAC2_INDEX 19
-#define PIC_IRT_GMAC3_INDEX 20
-#define PIC_IRT_XGS0_INDEX 21
-#define PIC_IRT_XGS1_INDEX 22
-#define PIC_IRT_HYPER_FATAL_INDEX 23
-#define PIC_IRT_PCIX_FATAL_INDEX 24
-#define PIC_IRT_BRIDGE_AERR_INDEX 25
-#define PIC_IRT_BRIDGE_BERR_INDEX 26
-#define PIC_IRT_BRIDGE_TB_XLR_INDEX 27
-#define PIC_IRT_BRIDGE_AERR_NMI_INDEX 28
-/* XLS */
-#define PIC_IRT_GMAC4_INDEX 21
-#define PIC_IRT_GMAC5_INDEX 22
-#define PIC_IRT_GMAC6_INDEX 23
-#define PIC_IRT_GMAC7_INDEX 24
-#define PIC_IRT_BRIDGE_ERR_INDEX 25
-#define PIC_IRT_PCIE_LINK0_INDEX 26
-#define PIC_IRT_PCIE_LINK1_INDEX 27
-#define PIC_IRT_PCIE_LINK2_INDEX 23
-#define PIC_IRT_PCIE_LINK3_INDEX 24
-#define PIC_IRT_PCIE_XLSB0_LINK2_INDEX 28
-#define PIC_IRT_PCIE_XLSB0_LINK3_INDEX 29
-#define PIC_IRT_SRIO_LINK0_INDEX 26
-#define PIC_IRT_SRIO_LINK1_INDEX 27
-#define PIC_IRT_SRIO_LINK2_INDEX 28
-#define PIC_IRT_SRIO_LINK3_INDEX 29
-#define PIC_IRT_PCIE_INT_INDEX 28
-#define PIC_IRT_PCIE_FATAL_INDEX 29
-#define PIC_IRT_GPIO_B_INDEX 30
-#define PIC_IRT_USB_INDEX 31
-/* XLS */
-#define PIC_NUM_IRTS 32
-
-
-#define PIC_CLOCK_TIMER 7
-
-/* PIC Registers */
-#define PIC_CTRL 0x00
-#define PIC_CTRL_STE 8 /* timer enable start bit */
-#define PIC_IPI 0x04
-#define PIC_INT_ACK 0x06
-
-#define WD_MAX_VAL_0 0x08
-#define WD_MAX_VAL_1 0x09
-#define WD_MASK_0 0x0a
-#define WD_MASK_1 0x0b
-#define WD_HEARBEAT_0 0x0c
-#define WD_HEARBEAT_1 0x0d
-
-#define PIC_IRT_0_BASE 0x40
-#define PIC_IRT_1_BASE 0x80
-#define PIC_TIMER_MAXVAL_0_BASE 0x100
-#define PIC_TIMER_MAXVAL_1_BASE 0x110
-#define PIC_TIMER_COUNT_0_BASE 0x120
-#define PIC_TIMER_COUNT_1_BASE 0x130
-
-#define PIC_IRT_0(picintr) (PIC_IRT_0_BASE + (picintr))
-#define PIC_IRT_1(picintr) (PIC_IRT_1_BASE + (picintr))
-
-#define PIC_TIMER_MAXVAL_0(i) (PIC_TIMER_MAXVAL_0_BASE + (i))
-#define PIC_TIMER_MAXVAL_1(i) (PIC_TIMER_MAXVAL_1_BASE + (i))
-#define PIC_TIMER_COUNT_0(i) (PIC_TIMER_COUNT_0_BASE + (i))
-#define PIC_TIMER_COUNT_1(i) (PIC_TIMER_COUNT_0_BASE + (i))
-
-/*
- * Mapping between hardware interrupt numbers and IRQs on CPU
- * we use a simple scheme to map PIC interrupts 0-31 to IRQs
- * 8-39. This leaves the IRQ 0-7 for cpu interrupts like
- * count/compare and FMN
- */
-#define PIC_IRQ_BASE 8
-#define PIC_INTR_TO_IRQ(i) (PIC_IRQ_BASE + (i))
-#define PIC_IRQ_TO_INTR(i) ((i) - PIC_IRQ_BASE)
-
-#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE
-#define PIC_WD_IRQ PIC_INTR_TO_IRQ(PIC_IRT_WD_INDEX)
-#define PIC_TIMER_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_0_INDEX)
-#define PIC_TIMER_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_1_INDEX)
-#define PIC_TIMER_2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_2_INDEX)
-#define PIC_TIMER_3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_3_INDEX)
-#define PIC_TIMER_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_4_INDEX)
-#define PIC_TIMER_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_5_INDEX)
-#define PIC_TIMER_6_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_6_INDEX)
-#define PIC_TIMER_7_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_7_INDEX)
-#define PIC_CLOCK_IRQ (PIC_TIMER_7_IRQ)
-#define PIC_UART_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_UART_0_INDEX)
-#define PIC_UART_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_UART_1_INDEX)
-#define PIC_I2C_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_I2C_0_INDEX)
-#define PIC_I2C_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_I2C_1_INDEX)
-#define PIC_PCMCIA_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCMCIA_INDEX)
-#define PIC_GPIO_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GPIO_INDEX)
-#define PIC_HYPER_IRQ PIC_INTR_TO_IRQ(PIC_IRT_HYPER_INDEX)
-#define PIC_PCIX_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIX_INDEX)
-/* XLS */
-#define PIC_CDE_IRQ PIC_INTR_TO_IRQ(PIC_IRT_CDE_INDEX)
-#define PIC_BRIDGE_TB_XLS_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLS_INDEX)
-/* end XLS */
-#define PIC_GMAC_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC0_INDEX)
-#define PIC_GMAC_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC1_INDEX)
-#define PIC_GMAC_2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC2_INDEX)
-#define PIC_GMAC_3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC3_INDEX)
-#define PIC_XGS_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_XGS0_INDEX)
-#define PIC_XGS_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_XGS1_INDEX)
-#define PIC_HYPER_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_HYPER_FATAL_INDEX)
-#define PIC_PCIX_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIX_FATAL_INDEX)
-#define PIC_BRIDGE_AERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_INDEX)
-#define PIC_BRIDGE_BERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_BERR_INDEX)
-#define PIC_BRIDGE_TB_XLR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLR_INDEX)
-#define PIC_BRIDGE_AERR_NMI_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_NMI_INDEX)
-/* XLS defines */
-#define PIC_GMAC_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC4_INDEX)
-#define PIC_GMAC_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC5_INDEX)
-#define PIC_GMAC_6_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC6_INDEX)
-#define PIC_GMAC_7_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC7_INDEX)
-#define PIC_BRIDGE_ERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_ERR_INDEX)
-#define PIC_PCIE_LINK0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK0_INDEX)
-#define PIC_PCIE_LINK1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK1_INDEX)
-#define PIC_PCIE_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK2_INDEX)
-#define PIC_PCIE_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK3_INDEX)
-#define PIC_PCIE_XLSB0_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK2_INDEX)
-#define PIC_PCIE_XLSB0_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK3_INDEX)
-#define PIC_SRIO_LINK0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK0_INDEX)
-#define PIC_SRIO_LINK1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK1_INDEX)
-#define PIC_SRIO_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK2_INDEX)
-#define PIC_SRIO_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK3_INDEX)
-#define PIC_PCIE_INT_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_INT__INDEX)
-#define PIC_PCIE_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_FATAL_INDEX)
-#define PIC_GPIO_B_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GPIO_B_INDEX)
-#define PIC_USB_IRQ PIC_INTR_TO_IRQ(PIC_IRT_USB_INDEX)
-#define PIC_IRT_LAST_IRQ PIC_USB_IRQ
-/* end XLS */
-
-#ifndef __ASSEMBLY__
-
-#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \
- ((irq) <= PIC_TIMER_7_IRQ))
-#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \
- ((irq) <= PIC_IRT_LAST_IRQ))
-
-static inline int
-nlm_irq_to_irt(int irq)
-{
- if (PIC_IRQ_IS_IRT(irq) == 0)
- return -1;
-
- return PIC_IRQ_TO_INTR(irq);
-}
-
-static inline int
-nlm_irt_to_irq(int irt)
-{
-
- return PIC_INTR_TO_IRQ(irt);
-}
-
-static inline void
-nlm_pic_enable_irt(uint64_t base, int irt)
-{
- uint32_t reg;
-
- reg = nlm_read_reg(base, PIC_IRT_1(irt));
- nlm_write_reg(base, PIC_IRT_1(irt), reg | (1u << 31));
-}
-
-static inline void
-nlm_pic_disable_irt(uint64_t base, int irt)
-{
- uint32_t reg;
-
- reg = nlm_read_reg(base, PIC_IRT_1(irt));
- nlm_write_reg(base, PIC_IRT_1(irt), reg & ~(1u << 31));
-}
-
-static inline void
-nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
-{
- unsigned int tid, pid;
-
- tid = hwt & 0x3;
- pid = (hwt >> 2) & 0x07;
- nlm_write_reg(base, PIC_IPI,
- (pid << 20) | (tid << 16) | (nmi << 8) | irq);
-}
-
-static inline void
-nlm_pic_ack(uint64_t base, int irt)
-{
- nlm_write_reg(base, PIC_INT_ACK, 1u << irt);
-}
-
-static inline void
-nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en)
-{
- nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt));
- /* local scheduling, invalid, level by default */
- nlm_write_reg(base, PIC_IRT_1(irt),
- (en << 30) | (1 << 6) | irq);
-}
-
-static inline uint64_t
-nlm_pic_read_timer(uint64_t base, int timer)
-{
- uint32_t up1, up2, low;
-
- up1 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer));
- low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer));
- up2 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer));
-
- if (up1 != up2) /* wrapped, get the new low */
- low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer));
- return ((uint64_t)up2 << 32) | low;
-
-}
-
-static inline uint32_t
-nlm_pic_read_timer32(uint64_t base, int timer)
-{
- return nlm_read_reg(base, PIC_TIMER_COUNT_0(timer));
-}
-
-static inline void
-nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu)
-{
- uint32_t up, low;
- uint64_t pic_ctrl = nlm_read_reg(base, PIC_CTRL);
- int en;
-
- en = (irq > 0);
- up = value >> 32;
- low = value & 0xFFFFFFFF;
- nlm_write_reg(base, PIC_TIMER_MAXVAL_0(timer), low);
- nlm_write_reg(base, PIC_TIMER_MAXVAL_1(timer), up);
- nlm_pic_init_irt(base, PIC_IRT_TIMER_INDEX(timer), irq, cpu, 0);
-
- /* enable the timer */
- pic_ctrl |= (1 << (PIC_CTRL_STE + timer));
- nlm_write_reg(base, PIC_CTRL, pic_ctrl);
-}
-#endif
-#endif /* _ASM_NLM_XLR_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h
deleted file mode 100644
index ceb991ca8436..000000000000
--- a/arch/mips/include/asm/netlogic/xlr/xlr.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _ASM_NLM_XLR_H
-#define _ASM_NLM_XLR_H
-
-/* SMP helpers */
-void xlr_wakeup_secondary_cpus(void);
-
-/* XLS B silicon "Rook" */
-static inline unsigned int nlm_chip_is_xls_b(void)
-{
- uint32_t prid = read_c0_prid();
-
- return ((prid & 0xf000) == 0x4000);
-}
-
-/* XLR chip types */
-/* The XLS product line has chip versions 0x[48c]? */
-static inline unsigned int nlm_chip_is_xls(void)
-{
- uint32_t prid = read_c0_prid();
-
- return ((prid & 0xf000) == 0x8000 || (prid & 0xf000) == 0x4000 ||
- (prid & 0xf000) == 0xc000);
-}
-
-#endif /* _ASM_NLM_XLR_H */