diff options
Diffstat (limited to 'arch/mips/include/asm/mipsregs.h')
| -rw-r--r-- | arch/mips/include/asm/mipsregs.h | 802 |
1 files changed, 694 insertions, 108 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 3ad19ad04d8a..e1ca65c62f6a 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -48,6 +48,9 @@ #define CP0_CONF $3 #define CP0_CONTEXT $4 #define CP0_PAGEMASK $5 +#define CP0_SEGCTL0 $5, 2 +#define CP0_SEGCTL1 $5, 3 +#define CP0_SEGCTL2 $5, 4 #define CP0_WIRED $6 #define CP0_INFO $7 #define CP0_HWRENA $7, 0 @@ -55,8 +58,14 @@ #define CP0_BADINSTR $8, 1 #define CP0_COUNT $9 #define CP0_ENTRYHI $10 +#define CP0_GUESTCTL1 $10, 4 +#define CP0_GUESTCTL2 $10, 5 +#define CP0_GUESTCTL3 $10, 6 #define CP0_COMPARE $11 +#define CP0_GUESTCTL0EXT $11, 4 #define CP0_STATUS $12 +#define CP0_GUESTCTL0 $12, 6 +#define CP0_GTOFFSET $12, 7 #define CP0_CAUSE $13 #define CP0_EPC $14 #define CP0_PRID $15 @@ -229,6 +238,8 @@ /* MIPS32/64 EntryHI bit definitions */ #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10) +#define MIPS_ENTRYHI_ASIDX (_ULCAST_(0x3) << 8) +#define MIPS_ENTRYHI_ASID (_ULCAST_(0xff) << 0) /* * R4x00 interrupt enable / cause bits @@ -390,6 +401,8 @@ #define CAUSEF_IP7 (_ULCAST_(1) << 15) #define CAUSEB_FDCI 21 #define CAUSEF_FDCI (_ULCAST_(1) << 21) +#define CAUSEB_WP 22 +#define CAUSEF_WP (_ULCAST_(1) << 22) #define CAUSEB_IV 23 #define CAUSEF_IV (_ULCAST_(1) << 23) #define CAUSEB_PCI 26 @@ -611,7 +624,8 @@ #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14) #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14) -#define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16) +#define MIPS_CONF4_KSCREXIST_SHIFT (16) +#define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT) #define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24) #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT) #define MIPS_CONF4_AE (_ULCAST_(1) << 28) @@ -623,6 +637,7 @@ #define MIPS_CONF5_MRP (_ULCAST_(1) << 3) #define MIPS_CONF5_LLB (_ULCAST_(1) << 4) #define MIPS_CONF5_MVH (_ULCAST_(1) << 5) +#define MIPS_CONF5_VP (_ULCAST_(1) << 7) #define MIPS_CONF5_FRE (_ULCAST_(1) << 8) #define MIPS_CONF5_UFE (_ULCAST_(1) << 9) #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27) @@ -633,6 +648,8 @@ #define MIPS_CONF6_SYND (_ULCAST_(1) << 13) /* proAptiv FTLB on/off bit */ #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15) +/* Loongson-3 FTLB on/off bit */ +#define MIPS_CONF6_FTLBDIS (_ULCAST_(1) << 22) /* FTLB probability bits */ #define MIPS_CONF6_FTLBP_SHIFT (16) @@ -645,12 +662,38 @@ /* FTLB probability bits for R6 */ #define MIPS_CONF7_FTLBP_SHIFT (18) +/* WatchLo* register definitions */ +#define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0) + +/* WatchHi* register definitions */ +#define MIPS_WATCHHI_M (_ULCAST_(1) << 31) +#define MIPS_WATCHHI_G (_ULCAST_(1) << 30) +#define MIPS_WATCHHI_WM (_ULCAST_(0x3) << 28) +#define MIPS_WATCHHI_WM_R_RVA (_ULCAST_(0) << 28) +#define MIPS_WATCHHI_WM_R_GPA (_ULCAST_(1) << 28) +#define MIPS_WATCHHI_WM_G_GVA (_ULCAST_(2) << 28) +#define MIPS_WATCHHI_EAS (_ULCAST_(0x3) << 24) +#define MIPS_WATCHHI_ASID (_ULCAST_(0xff) << 16) +#define MIPS_WATCHHI_MASK (_ULCAST_(0x1ff) << 3) +#define MIPS_WATCHHI_I (_ULCAST_(1) << 2) +#define MIPS_WATCHHI_R (_ULCAST_(1) << 1) +#define MIPS_WATCHHI_W (_ULCAST_(1) << 0) +#define MIPS_WATCHHI_IRW (_ULCAST_(0x7) << 0) + /* MAAR bit definitions */ #define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12) #define MIPS_MAAR_ADDR_SHIFT 12 #define MIPS_MAAR_S (_ULCAST_(1) << 1) #define MIPS_MAAR_V (_ULCAST_(1) << 0) +/* EBase bit definitions */ +#define MIPS_EBASE_CPUNUM_SHIFT 0 +#define MIPS_EBASE_CPUNUM (_ULCAST_(0x3ff) << 0) +#define MIPS_EBASE_WG_SHIFT 11 +#define MIPS_EBASE_WG (_ULCAST_(1) << 11) +#define MIPS_EBASE_BASE_SHIFT 12 +#define MIPS_EBASE_BASE (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1)) + /* CMGCRBase bit definitions */ #define MIPS_CMGCRB_BASE 11 #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1)) @@ -686,6 +729,8 @@ #define MIPS_PWFIELD_PTEI_SHIFT 0 #define MIPS_PWFIELD_PTEI_MASK 0x0000003f +#define MIPS_PWSIZE_PS_SHIFT 30 +#define MIPS_PWSIZE_PS_MASK 0x40000000 #define MIPS_PWSIZE_GDW_SHIFT 24 #define MIPS_PWSIZE_GDW_MASK 0x3f000000 #define MIPS_PWSIZE_UDW_SHIFT 18 @@ -699,6 +744,12 @@ #define MIPS_PWCTL_PWEN_SHIFT 31 #define MIPS_PWCTL_PWEN_MASK 0x80000000 +#define MIPS_PWCTL_XK_SHIFT 28 +#define MIPS_PWCTL_XK_MASK 0x10000000 +#define MIPS_PWCTL_XS_SHIFT 27 +#define MIPS_PWCTL_XS_MASK 0x08000000 +#define MIPS_PWCTL_XU_SHIFT 26 +#define MIPS_PWCTL_XU_MASK 0x04000000 #define MIPS_PWCTL_DPH_SHIFT 7 #define MIPS_PWCTL_DPH_MASK 0x00000080 #define MIPS_PWCTL_HUGEPG_SHIFT 6 @@ -706,6 +757,94 @@ #define MIPS_PWCTL_PSN_SHIFT 0 #define MIPS_PWCTL_PSN_MASK 0x0000003f +/* GuestCtl0 fields */ +#define MIPS_GCTL0_GM_SHIFT 31 +#define MIPS_GCTL0_GM (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT) +#define MIPS_GCTL0_RI_SHIFT 30 +#define MIPS_GCTL0_RI (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT) +#define MIPS_GCTL0_MC_SHIFT 29 +#define MIPS_GCTL0_MC (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT) +#define MIPS_GCTL0_CP0_SHIFT 28 +#define MIPS_GCTL0_CP0 (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT) +#define MIPS_GCTL0_AT_SHIFT 26 +#define MIPS_GCTL0_AT (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT) +#define MIPS_GCTL0_GT_SHIFT 25 +#define MIPS_GCTL0_GT (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT) +#define MIPS_GCTL0_CG_SHIFT 24 +#define MIPS_GCTL0_CG (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT) +#define MIPS_GCTL0_CF_SHIFT 23 +#define MIPS_GCTL0_CF (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT) +#define MIPS_GCTL0_G1_SHIFT 22 +#define MIPS_GCTL0_G1 (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT) +#define MIPS_GCTL0_G0E_SHIFT 19 +#define MIPS_GCTL0_G0E (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT) +#define MIPS_GCTL0_PT_SHIFT 18 +#define MIPS_GCTL0_PT (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT) +#define MIPS_GCTL0_RAD_SHIFT 9 +#define MIPS_GCTL0_RAD (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT) +#define MIPS_GCTL0_DRG_SHIFT 8 +#define MIPS_GCTL0_DRG (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT) +#define MIPS_GCTL0_G2_SHIFT 7 +#define MIPS_GCTL0_G2 (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT) +#define MIPS_GCTL0_GEXC_SHIFT 2 +#define MIPS_GCTL0_GEXC (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT) +#define MIPS_GCTL0_SFC2_SHIFT 1 +#define MIPS_GCTL0_SFC2 (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT) +#define MIPS_GCTL0_SFC1_SHIFT 0 +#define MIPS_GCTL0_SFC1 (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT) + +/* GuestCtl0.AT Guest address translation control */ +#define MIPS_GCTL0_AT_ROOT 1 /* Guest MMU under Root control */ +#define MIPS_GCTL0_AT_GUEST 3 /* Guest MMU under Guest control */ + +/* GuestCtl0.GExcCode Hypervisor exception cause codes */ +#define MIPS_GCTL0_GEXC_GPSI 0 /* Guest Privileged Sensitive Instruction */ +#define MIPS_GCTL0_GEXC_GSFC 1 /* Guest Software Field Change */ +#define MIPS_GCTL0_GEXC_HC 2 /* Hypercall */ +#define MIPS_GCTL0_GEXC_GRR 3 /* Guest Reserved Instruction Redirect */ +#define MIPS_GCTL0_GEXC_GVA 8 /* Guest Virtual Address available */ +#define MIPS_GCTL0_GEXC_GHFC 9 /* Guest Hardware Field Change */ +#define MIPS_GCTL0_GEXC_GPA 10 /* Guest Physical Address available */ + +/* GuestCtl0Ext fields */ +#define MIPS_GCTL0EXT_RPW_SHIFT 8 +#define MIPS_GCTL0EXT_RPW (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT) +#define MIPS_GCTL0EXT_NCC_SHIFT 6 +#define MIPS_GCTL0EXT_NCC (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT) +#define MIPS_GCTL0EXT_CGI_SHIFT 4 +#define MIPS_GCTL0EXT_CGI (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT) +#define MIPS_GCTL0EXT_FCD_SHIFT 3 +#define MIPS_GCTL0EXT_FCD (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT) +#define MIPS_GCTL0EXT_OG_SHIFT 2 +#define MIPS_GCTL0EXT_OG (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT) +#define MIPS_GCTL0EXT_BG_SHIFT 1 +#define MIPS_GCTL0EXT_BG (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT) +#define MIPS_GCTL0EXT_MG_SHIFT 0 +#define MIPS_GCTL0EXT_MG (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT) + +/* GuestCtl0Ext.RPW Root page walk configuration */ +#define MIPS_GCTL0EXT_RPW_BOTH 0 /* Root PW for GPA->RPA and RVA->RPA */ +#define MIPS_GCTL0EXT_RPW_GPA 2 /* Root PW for GPA->RPA */ +#define MIPS_GCTL0EXT_RPW_RVA 3 /* Root PW for RVA->RPA */ + +/* GuestCtl0Ext.NCC Nested cache coherency attributes */ +#define MIPS_GCTL0EXT_NCC_IND 0 /* Guest CCA independent of Root CCA */ +#define MIPS_GCTL0EXT_NCC_MOD 1 /* Guest CCA modified by Root CCA */ + +/* GuestCtl1 fields */ +#define MIPS_GCTL1_ID_SHIFT 0 +#define MIPS_GCTL1_ID_WIDTH 8 +#define MIPS_GCTL1_ID (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT) +#define MIPS_GCTL1_RID_SHIFT 16 +#define MIPS_GCTL1_RID_WIDTH 8 +#define MIPS_GCTL1_RID (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT) +#define MIPS_GCTL1_EID_SHIFT 24 +#define MIPS_GCTL1_EID_WIDTH 8 +#define MIPS_GCTL1_EID (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT) + +/* GuestID reserved for root context */ +#define MIPS_GCTL1_ROOT_GUESTID 0 + /* CDMMBase register bit definitions */ #define MIPS_CDMMBASE_SIZE_SHIFT 0 #define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT) @@ -757,6 +896,15 @@ /* Disable Branch Return Cache */ #define R10K_DIAG_D_BRC (_ULCAST_(1) << 22) +/* Flush ITLB */ +#define LOONGSON_DIAG_ITLB (_ULCAST_(1) << 2) +/* Flush DTLB */ +#define LOONGSON_DIAG_DTLB (_ULCAST_(1) << 3) +/* Flush VTLB */ +#define LOONGSON_DIAG_VTLB (_ULCAST_(1) << 12) +/* Flush FTLB */ +#define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13) + /* * Coprocessor 1 (FPU) register names */ @@ -909,6 +1057,33 @@ static inline int mm_insn_16bit(u16 insn) } /* + * Helper macros for generating raw instruction encodings in inline asm. + */ +#ifdef CONFIG_CPU_MICROMIPS +#define _ASM_INSN16_IF_MM(_enc) \ + ".insn\n\t" \ + ".hword (" #_enc ")\n\t" +#define _ASM_INSN32_IF_MM(_enc) \ + ".insn\n\t" \ + ".hword ((" #_enc ") >> 16)\n\t" \ + ".hword ((" #_enc ") & 0xffff)\n\t" +#else +#define _ASM_INSN_IF_MIPS(_enc) \ + ".insn\n\t" \ + ".word (" #_enc ")\n\t" +#endif + +#ifndef _ASM_INSN16_IF_MM +#define _ASM_INSN16_IF_MM(_enc) +#endif +#ifndef _ASM_INSN32_IF_MM +#define _ASM_INSN32_IF_MM(_enc) +#endif +#ifndef _ASM_INSN_IF_MIPS +#define _ASM_INSN_IF_MIPS(_enc) +#endif + +/* * TLB Invalidate Flush */ static inline void tlbinvf(void) @@ -916,7 +1091,9 @@ static inline void tlbinvf(void) __asm__ __volatile__( ".set push\n\t" ".set noreorder\n\t" - ".word 0x42000004\n\t" /* tlbinvf */ + "# tlbinvf\n\t" + _ASM_INSN_IF_MIPS(0x42000004) + _ASM_INSN32_IF_MM(0x0000537c) ".set pop"); } @@ -1137,9 +1314,9 @@ do { \ " .set push \n" \ " .set noat \n" \ " .set mips32r2 \n" \ - " .insn \n" \ " # mfhc0 $1, %1 \n" \ - " .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \ + _ASM_INSN_IF_MIPS(0x40410000 | ((%1 & 0x1f) << 11)) \ + _ASM_INSN32_IF_MM(0x002000f4 | ((%1 & 0x1f) << 16)) \ " move %0, $1 \n" \ " .set pop \n" \ : "=r" (__res) \ @@ -1155,8 +1332,8 @@ do { \ " .set mips32r2 \n" \ " move $1, %0 \n" \ " # mthc0 $1, %1 \n" \ - " .insn \n" \ - " .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \ + _ASM_INSN_IF_MIPS(0x40c10000 | ((%1 & 0x1f) << 11)) \ + _ASM_INSN32_IF_MM(0x002002f4 | ((%1 & 0x1f) << 16)) \ " .set pop \n" \ : \ : "r" (value), "i" (register)); \ @@ -1186,9 +1363,15 @@ do { \ #define read_c0_context() __read_ulong_c0_register($4, 0) #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) +#define read_c0_contextconfig() __read_32bit_c0_register($4, 1) +#define write_c0_contextconfig(val) __write_32bit_c0_register($4, 1, val) + #define read_c0_userlocal() __read_ulong_c0_register($4, 2) #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) +#define read_c0_xcontextconfig() __read_ulong_c0_register($4, 3) +#define write_c0_xcontextconfig(val) __write_ulong_c0_register($4, 3, val) + #define read_c0_pagemask() __read_32bit_c0_register($5, 0) #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) @@ -1206,6 +1389,9 @@ do { \ #define read_c0_badvaddr() __read_ulong_c0_register($8, 0) #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) +#define read_c0_badinstr() __read_32bit_c0_register($8, 1) +#define read_c0_badinstrp() __read_32bit_c0_register($8, 2) + #define read_c0_count() __read_32bit_c0_register($9, 0) #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) @@ -1218,9 +1404,21 @@ do { \ #define read_c0_entryhi() __read_ulong_c0_register($10, 0) #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) +#define read_c0_guestctl1() __read_32bit_c0_register($10, 4) +#define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val) + +#define read_c0_guestctl2() __read_32bit_c0_register($10, 5) +#define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val) + +#define read_c0_guestctl3() __read_32bit_c0_register($10, 6) +#define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val) + #define read_c0_compare() __read_32bit_c0_register($11, 0) #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) +#define read_c0_guestctl0ext() __read_32bit_c0_register($11, 4) +#define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val) + #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) @@ -1231,6 +1429,12 @@ do { \ #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) +#define read_c0_guestctl0() __read_32bit_c0_register($12, 6) +#define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val) + +#define read_c0_gtoffset() __read_32bit_c0_register($12, 7) +#define write_c0_gtoffset(val) __write_32bit_c0_register($12, 7, val) + #define read_c0_cause() __read_32bit_c0_register($13, 0) #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) @@ -1416,6 +1620,9 @@ do { \ #define read_c0_ebase() __read_32bit_c0_register($15, 1) #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) +#define read_c0_ebase_64() __read_64bit_c0_register($15, 1) +#define write_c0_ebase_64(val) __write_64bit_c0_register($15, 1, val) + #define read_c0_cdmmbase() __read_ulong_c0_register($15, 2) #define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val) @@ -1442,6 +1649,12 @@ do { \ #define read_c0_pwctl() __read_32bit_c0_register($6, 6) #define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val) +#define read_c0_pgd() __read_64bit_c0_register($9, 7) +#define write_c0_pgd(val) __write_64bit_c0_register($9, 7, val) + +#define read_c0_kpgd() __read_64bit_c0_register($31, 7) +#define write_c0_kpgd(val) __write_64bit_c0_register($31, 7, val) + /* Cavium OCTEON (cnMIPS) */ #define read_c0_cvmcount() __read_ulong_c0_register($9, 6) #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) @@ -1507,6 +1720,321 @@ do { \ #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val) /* + * Macros to access the guest system control coprocessor + */ + +#ifdef TOOLCHAIN_SUPPORTS_VIRT + +#define __read_32bit_gc0_register(source, sel) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\tmips32r2\n\t" \ + ".set\tvirt\n\t" \ + "mfgc0\t%0, $%1, %2\n\t" \ + ".set\tpop" \ + : "=r" (__res) \ + : "i" (source), "i" (sel)); \ + __res; \ +}) + +#define __read_64bit_gc0_register(source, sel) \ +({ unsigned long long __res; \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\tmips64r2\n\t" \ + ".set\tvirt\n\t" \ + "dmfgc0\t%0, $%1, %2\n\t" \ + ".set\tpop" \ + : "=r" (__res) \ + : "i" (source), "i" (sel)); \ + __res; \ +}) + +#define __write_32bit_gc0_register(register, sel, value) \ +do { \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\tmips32r2\n\t" \ + ".set\tvirt\n\t" \ + "mtgc0\t%z0, $%1, %2\n\t" \ + ".set\tpop" \ + : : "Jr" ((unsigned int)(value)), \ + "i" (register), "i" (sel)); \ +} while (0) + +#define __write_64bit_gc0_register(register, sel, value) \ +do { \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\tmips64r2\n\t" \ + ".set\tvirt\n\t" \ + "dmtgc0\t%z0, $%1, %2\n\t" \ + ".set\tpop" \ + : : "Jr" (value), \ + "i" (register), "i" (sel)); \ +} while (0) + +#else /* TOOLCHAIN_SUPPORTS_VIRT */ + +#define __read_32bit_gc0_register(source, sel) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\tnoat\n\t" \ + "# mfgc0\t$1, $%1, %2\n\t" \ + _ASM_INSN_IF_MIPS(0x40610000 | %1 << 11 | %2) \ + _ASM_INSN32_IF_MM(0x002004fc | %1 << 16 | %2 << 11) \ + "move\t%0, $1\n\t" \ + ".set\tpop" \ + : "=r" (__res) \ + : "i" (source), "i" (sel)); \ + __res; \ +}) + +#define __read_64bit_gc0_register(source, sel) \ +({ unsigned long long __res; \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\tnoat\n\t" \ + "# dmfgc0\t$1, $%1, %2\n\t" \ + _ASM_INSN_IF_MIPS(0x40610100 | %1 << 11 | %2) \ + _ASM_INSN32_IF_MM(0x582004fc | %1 << 16 | %2 << 11) \ + "move\t%0, $1\n\t" \ + ".set\tpop" \ + : "=r" (__res) \ + : "i" (source), "i" (sel)); \ + __res; \ +}) + +#define __write_32bit_gc0_register(register, sel, value) \ +do { \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\tnoat\n\t" \ + "move\t$1, %z0\n\t" \ + "# mtgc0\t$1, $%1, %2\n\t" \ + _ASM_INSN_IF_MIPS(0x40610200 | %1 << 11 | %2) \ + _ASM_INSN32_IF_MM(0x002006fc | %1 << 16 | %2 << 11) \ + ".set\tpop" \ + : : "Jr" ((unsigned int)(value)), \ + "i" (register), "i" (sel)); \ +} while (0) + +#define __write_64bit_gc0_register(register, sel, value) \ +do { \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\tnoat\n\t" \ + "move\t$1, %z0\n\t" \ + "# dmtgc0\t$1, $%1, %2\n\t" \ + _ASM_INSN_IF_MIPS(0x40610300 | %1 << 11 | %2) \ + _ASM_INSN32_IF_MM(0x582006fc | %1 << 16 | %2 << 11) \ + ".set\tpop" \ + : : "Jr" (value), \ + "i" (register), "i" (sel)); \ +} while (0) + +#endif /* !TOOLCHAIN_SUPPORTS_VIRT */ + +#define __read_ulong_gc0_register(reg, sel) \ + ((sizeof(unsigned long) == 4) ? \ + (unsigned long) __read_32bit_gc0_register(reg, sel) : \ + (unsigned long) __read_64bit_gc0_register(reg, sel)) + +#define __write_ulong_gc0_register(reg, sel, val) \ +do { \ + if (sizeof(unsigned long) == 4) \ + __write_32bit_gc0_register(reg, sel, val); \ + else \ + __write_64bit_gc0_register(reg, sel, val); \ +} while (0) + +#define read_gc0_index() __read_32bit_gc0_register(0, 0) +#define write_gc0_index(val) __write_32bit_gc0_register(0, 0, val) + +#define read_gc0_entrylo0() __read_ulong_gc0_register(2, 0) +#define write_gc0_entrylo0(val) __write_ulong_gc0_register(2, 0, val) + +#define read_gc0_entrylo1() __read_ulong_gc0_register(3, 0) +#define write_gc0_entrylo1(val) __write_ulong_gc0_register(3, 0, val) + +#define read_gc0_context() __read_ulong_gc0_register(4, 0) +#define write_gc0_context(val) __write_ulong_gc0_register(4, 0, val) + +#define read_gc0_contextconfig() __read_32bit_gc0_register(4, 1) +#define write_gc0_contextconfig(val) __write_32bit_gc0_register(4, 1, val) + +#define read_gc0_userlocal() __read_ulong_gc0_register(4, 2) +#define write_gc0_userlocal(val) __write_ulong_gc0_register(4, 2, val) + +#define read_gc0_xcontextconfig() __read_ulong_gc0_register(4, 3) +#define write_gc0_xcontextconfig(val) __write_ulong_gc0_register(4, 3, val) + +#define read_gc0_pagemask() __read_32bit_gc0_register(5, 0) +#define write_gc0_pagemask(val) __write_32bit_gc0_register(5, 0, val) + +#define read_gc0_pagegrain() __read_32bit_gc0_register(5, 1) +#define write_gc0_pagegrain(val) __write_32bit_gc0_register(5, 1, val) + +#define read_gc0_segctl0() __read_ulong_gc0_register(5, 2) +#define write_gc0_segctl0(val) __write_ulong_gc0_register(5, 2, val) + +#define read_gc0_segctl1() __read_ulong_gc0_register(5, 3) +#define write_gc0_segctl1(val) __write_ulong_gc0_register(5, 3, val) + +#define read_gc0_segctl2() __read_ulong_gc0_register(5, 4) +#define write_gc0_segctl2(val) __write_ulong_gc0_register(5, 4, val) + +#define read_gc0_pwbase() __read_ulong_gc0_register(5, 5) +#define write_gc0_pwbase(val) __write_ulong_gc0_register(5, 5, val) + +#define read_gc0_pwfield() __read_ulong_gc0_register(5, 6) +#define write_gc0_pwfield(val) __write_ulong_gc0_register(5, 6, val) + +#define read_gc0_pwsize() __read_ulong_gc0_register(5, 7) +#define write_gc0_pwsize(val) __write_ulong_gc0_register(5, 7, val) + +#define read_gc0_wired() __read_32bit_gc0_register(6, 0) +#define write_gc0_wired(val) __write_32bit_gc0_register(6, 0, val) + +#define read_gc0_pwctl() __read_32bit_gc0_register(6, 6) +#define write_gc0_pwctl(val) __write_32bit_gc0_register(6, 6, val) + +#define read_gc0_hwrena() __read_32bit_gc0_register(7, 0) +#define write_gc0_hwrena(val) __write_32bit_gc0_register(7, 0, val) + +#define read_gc0_badvaddr() __read_ulong_gc0_register(8, 0) +#define write_gc0_badvaddr(val) __write_ulong_gc0_register(8, 0, val) + +#define read_gc0_badinstr() __read_32bit_gc0_register(8, 1) +#define write_gc0_badinstr(val) __write_32bit_gc0_register(8, 1, val) + +#define read_gc0_badinstrp() __read_32bit_gc0_register(8, 2) +#define write_gc0_badinstrp(val) __write_32bit_gc0_register(8, 2, val) + +#define read_gc0_count() __read_32bit_gc0_register(9, 0) + +#define read_gc0_entryhi() __read_ulong_gc0_register(10, 0) +#define write_gc0_entryhi(val) __write_ulong_gc0_register(10, 0, val) + +#define read_gc0_compare() __read_32bit_gc0_register(11, 0) +#define write_gc0_compare(val) __write_32bit_gc0_register(11, 0, val) + +#define read_gc0_status() __read_32bit_gc0_register(12, 0) +#define write_gc0_status(val) __write_32bit_gc0_register(12, 0, val) + +#define read_gc0_intctl() __read_32bit_gc0_register(12, 1) +#define write_gc0_intctl(val) __write_32bit_gc0_register(12, 1, val) + +#define read_gc0_cause() __read_32bit_gc0_register(13, 0) +#define write_gc0_cause(val) __write_32bit_gc0_register(13, 0, val) + +#define read_gc0_epc() __read_ulong_gc0_register(14, 0) +#define write_gc0_epc(val) __write_ulong_gc0_register(14, 0, val) + +#define read_gc0_ebase() __read_32bit_gc0_register(15, 1) +#define write_gc0_ebase(val) __write_32bit_gc0_register(15, 1, val) + +#define read_gc0_ebase_64() __read_64bit_gc0_register(15, 1) +#define write_gc0_ebase_64(val) __write_64bit_gc0_register(15, 1, val) + +#define read_gc0_config() __read_32bit_gc0_register(16, 0) +#define read_gc0_config1() __read_32bit_gc0_register(16, 1) +#define read_gc0_config2() __read_32bit_gc0_register(16, 2) +#define read_gc0_config3() __read_32bit_gc0_register(16, 3) +#define read_gc0_config4() __read_32bit_gc0_register(16, 4) +#define read_gc0_config5() __read_32bit_gc0_register(16, 5) +#define read_gc0_config6() __read_32bit_gc0_register(16, 6) +#define read_gc0_config7() __read_32bit_gc0_register(16, 7) +#define write_gc0_config(val) __write_32bit_gc0_register(16, 0, val) +#define write_gc0_config1(val) __write_32bit_gc0_register(16, 1, val) +#define write_gc0_config2(val) __write_32bit_gc0_register(16, 2, val) +#define write_gc0_config3(val) __write_32bit_gc0_register(16, 3, val) +#define write_gc0_config4(val) __write_32bit_gc0_register(16, 4, val) +#define write_gc0_config5(val) __write_32bit_gc0_register(16, 5, val) +#define write_gc0_config6(val) __write_32bit_gc0_register(16, 6, val) +#define write_gc0_config7(val) __write_32bit_gc0_register(16, 7, val) + +#define read_gc0_watchlo0() __read_ulong_gc0_register(18, 0) +#define read_gc0_watchlo1() __read_ulong_gc0_register(18, 1) +#define read_gc0_watchlo2() __read_ulong_gc0_register(18, 2) +#define read_gc0_watchlo3() __read_ulong_gc0_register(18, 3) +#define read_gc0_watchlo4() __read_ulong_gc0_register(18, 4) +#define read_gc0_watchlo5() __read_ulong_gc0_register(18, 5) +#define read_gc0_watchlo6() __read_ulong_gc0_register(18, 6) +#define read_gc0_watchlo7() __read_ulong_gc0_register(18, 7) +#define write_gc0_watchlo0(val) __write_ulong_gc0_register(18, 0, val) +#define write_gc0_watchlo1(val) __write_ulong_gc0_register(18, 1, val) +#define write_gc0_watchlo2(val) __write_ulong_gc0_register(18, 2, val) +#define write_gc0_watchlo3(val) __write_ulong_gc0_register(18, 3, val) +#define write_gc0_watchlo4(val) __write_ulong_gc0_register(18, 4, val) +#define write_gc0_watchlo5(val) __write_ulong_gc0_register(18, 5, val) +#define write_gc0_watchlo6(val) __write_ulong_gc0_register(18, 6, val) +#define write_gc0_watchlo7(val) __write_ulong_gc0_register(18, 7, val) + +#define read_gc0_watchhi0() __read_32bit_gc0_register(19, 0) +#define read_gc0_watchhi1() __read_32bit_gc0_register(19, 1) +#define read_gc0_watchhi2() __read_32bit_gc0_register(19, 2) +#define read_gc0_watchhi3() __read_32bit_gc0_register(19, 3) +#define read_gc0_watchhi4() __read_32bit_gc0_register(19, 4) +#define read_gc0_watchhi5() __read_32bit_gc0_register(19, 5) +#define read_gc0_watchhi6() __read_32bit_gc0_register(19, 6) +#define read_gc0_watchhi7() __read_32bit_gc0_register(19, 7) +#define write_gc0_watchhi0(val) __write_32bit_gc0_register(19, 0, val) +#define write_gc0_watchhi1(val) __write_32bit_gc0_register(19, 1, val) +#define write_gc0_watchhi2(val) __write_32bit_gc0_register(19, 2, val) +#define write_gc0_watchhi3(val) __write_32bit_gc0_register(19, 3, val) +#define write_gc0_watchhi4(val) __write_32bit_gc0_register(19, 4, val) +#define write_gc0_watchhi5(val) __write_32bit_gc0_register(19, 5, val) +#define write_gc0_watchhi6(val) __write_32bit_gc0_register(19, 6, val) +#define write_gc0_watchhi7(val) __write_32bit_gc0_register(19, 7, val) + +#define read_gc0_xcontext() __read_ulong_gc0_register(20, 0) +#define write_gc0_xcontext(val) __write_ulong_gc0_register(20, 0, val) + +#define read_gc0_perfctrl0() __read_32bit_gc0_register(25, 0) +#define write_gc0_perfctrl0(val) __write_32bit_gc0_register(25, 0, val) +#define read_gc0_perfcntr0() __read_32bit_gc0_register(25, 1) +#define write_gc0_perfcntr0(val) __write_32bit_gc0_register(25, 1, val) +#define read_gc0_perfcntr0_64() __read_64bit_gc0_register(25, 1) +#define write_gc0_perfcntr0_64(val) __write_64bit_gc0_register(25, 1, val) +#define read_gc0_perfctrl1() __read_32bit_gc0_register(25, 2) +#define write_gc0_perfctrl1(val) __write_32bit_gc0_register(25, 2, val) +#define read_gc0_perfcntr1() __read_32bit_gc0_register(25, 3) +#define write_gc0_perfcntr1(val) __write_32bit_gc0_register(25, 3, val) +#define read_gc0_perfcntr1_64() __read_64bit_gc0_register(25, 3) +#define write_gc0_perfcntr1_64(val) __write_64bit_gc0_register(25, 3, val) +#define read_gc0_perfctrl2() __read_32bit_gc0_register(25, 4) +#define write_gc0_perfctrl2(val) __write_32bit_gc0_register(25, 4, val) +#define read_gc0_perfcntr2() __read_32bit_gc0_register(25, 5) +#define write_gc0_perfcntr2(val) __write_32bit_gc0_register(25, 5, val) +#define read_gc0_perfcntr2_64() __read_64bit_gc0_register(25, 5) +#define write_gc0_perfcntr2_64(val) __write_64bit_gc0_register(25, 5, val) +#define read_gc0_perfctrl3() __read_32bit_gc0_register(25, 6) +#define write_gc0_perfctrl3(val) __write_32bit_gc0_register(25, 6, val) +#define read_gc0_perfcntr3() __read_32bit_gc0_register(25, 7) +#define write_gc0_perfcntr3(val) __write_32bit_gc0_register(25, 7, val) +#define read_gc0_perfcntr3_64() __read_64bit_gc0_register(25, 7) +#define write_gc0_perfcntr3_64(val) __write_64bit_gc0_register(25, 7, val) + +#define read_gc0_errorepc() __read_ulong_gc0_register(30, 0) +#define write_gc0_errorepc(val) __write_ulong_gc0_register(30, 0, val) + +#define read_gc0_kscratch1() __read_ulong_gc0_register(31, 2) +#define read_gc0_kscratch2() __read_ulong_gc0_register(31, 3) +#define read_gc0_kscratch3() __read_ulong_gc0_register(31, 4) +#define read_gc0_kscratch4() __read_ulong_gc0_register(31, 5) +#define read_gc0_kscratch5() __read_ulong_gc0_register(31, 6) +#define read_gc0_kscratch6() __read_ulong_gc0_register(31, 7) +#define write_gc0_kscratch1(val) __write_ulong_gc0_register(31, 2, val) +#define write_gc0_kscratch2(val) __write_ulong_gc0_register(31, 3, val) +#define write_gc0_kscratch3(val) __write_ulong_gc0_register(31, 4, val) +#define write_gc0_kscratch4(val) __write_ulong_gc0_register(31, 5, val) +#define write_gc0_kscratch5(val) __write_ulong_gc0_register(31, 6, val) +#define write_gc0_kscratch6(val) __write_ulong_gc0_register(31, 7, val) + +/* * Macros to access the floating point coprocessor control registers */ #define _read_32bit_cp1_register(source, gas_hardfloat) \ @@ -1762,7 +2290,6 @@ do { \ #else -#ifdef CONFIG_CPU_MICROMIPS #define rddsp(mask) \ ({ \ unsigned int __res; \ @@ -1771,8 +2298,8 @@ do { \ " .set push \n" \ " .set noat \n" \ " # rddsp $1, %x1 \n" \ - " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \ - " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \ + _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16)) \ + _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14)) \ " move %0, $1 \n" \ " .set pop \n" \ : "=r" (__res) \ @@ -1787,22 +2314,22 @@ do { \ " .set noat \n" \ " move $1, %0 \n" \ " # wrdsp $1, %x1 \n" \ - " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \ - " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \ + _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11)) \ + _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14)) \ " .set pop \n" \ : \ : "r" (val), "i" (mask)); \ } while (0) -#define _umips_dsp_mfxxx(ins) \ +#define _dsp_mfxxx(ins) \ ({ \ unsigned long __treg; \ \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ - " .hword 0x0001 \n" \ - " .hword %x1 \n" \ + _ASM_INSN_IF_MIPS(0x00000810 | %X1) \ + _ASM_INSN32_IF_MM(0x0001007c | %x1) \ " move %0, $1 \n" \ " .set pop \n" \ : "=r" (__treg) \ @@ -1810,101 +2337,28 @@ do { \ __treg; \ }) -#define _umips_dsp_mtxxx(val, ins) \ +#define _dsp_mtxxx(val, ins) \ do { \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ " move $1, %0 \n" \ - " .hword 0x0001 \n" \ - " .hword %x1 \n" \ + _ASM_INSN_IF_MIPS(0x00200011 | %X1) \ + _ASM_INSN32_IF_MM(0x0001207c | %x1) \ " .set pop \n" \ : \ : "r" (val), "i" (ins)); \ } while (0) -#define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c) -#define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c) - -#define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c)) -#define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c)) - -#define mflo0() _umips_dsp_mflo(0) -#define mflo1() _umips_dsp_mflo(1) -#define mflo2() _umips_dsp_mflo(2) -#define mflo3() _umips_dsp_mflo(3) - -#define mfhi0() _umips_dsp_mfhi(0) -#define mfhi1() _umips_dsp_mfhi(1) -#define mfhi2() _umips_dsp_mfhi(2) -#define mfhi3() _umips_dsp_mfhi(3) +#ifdef CONFIG_CPU_MICROMIPS -#define mtlo0(x) _umips_dsp_mtlo(x, 0) -#define mtlo1(x) _umips_dsp_mtlo(x, 1) -#define mtlo2(x) _umips_dsp_mtlo(x, 2) -#define mtlo3(x) _umips_dsp_mtlo(x, 3) +#define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000) +#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000) -#define mthi0(x) _umips_dsp_mthi(x, 0) -#define mthi1(x) _umips_dsp_mthi(x, 1) -#define mthi2(x) _umips_dsp_mthi(x, 2) -#define mthi3(x) _umips_dsp_mthi(x, 3) +#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000)) +#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000)) #else /* !CONFIG_CPU_MICROMIPS */ -#define rddsp(mask) \ -({ \ - unsigned int __res; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # rddsp $1, %x1 \n" \ - " .word 0x7c000cb8 | (%x1 << 16) \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__res) \ - : "i" (mask)); \ - __res; \ -}) - -#define wrdsp(val, mask) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # wrdsp $1, %x1 \n" \ - " .word 0x7c2004f8 | (%x1 << 11) \n" \ - " .set pop \n" \ - : \ - : "r" (val), "i" (mask)); \ -} while (0) - -#define _dsp_mfxxx(ins) \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " .word (0x00000810 | %1) \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg) \ - : "i" (ins)); \ - __treg; \ -}) - -#define _dsp_mtxxx(val, ins) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " .word (0x00200011 | %1) \n" \ - " .set pop \n" \ - : \ - : "r" (val), "i" (ins)); \ -} while (0) #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) @@ -1912,6 +2366,8 @@ do { \ #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) +#endif /* CONFIG_CPU_MICROMIPS */ + #define mflo0() _dsp_mflo(0) #define mflo1() _dsp_mflo(1) #define mflo2() _dsp_mflo(2) @@ -1932,7 +2388,6 @@ do { \ #define mthi2(x) _dsp_mthi(x, 2) #define mthi3(x) _dsp_mthi(x, 3) -#endif /* CONFIG_CPU_MICROMIPS */ #endif /* @@ -2001,47 +2456,164 @@ static inline void tlb_write_random(void) ".set reorder"); } +#ifdef TOOLCHAIN_SUPPORTS_VIRT + /* - * Manipulate bits in a c0 register. + * Guest TLB operations. + * + * It is responsibility of the caller to take care of any TLB hazards. */ -#define __BUILD_SET_C0(name) \ +static inline void guest_tlb_probe(void) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set noreorder\n\t" + ".set virt\n\t" + "tlbgp\n\t" + ".set pop"); +} + +static inline void guest_tlb_read(void) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set noreorder\n\t" + ".set virt\n\t" + "tlbgr\n\t" + ".set pop"); +} + +static inline void guest_tlb_write_indexed(void) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set noreorder\n\t" + ".set virt\n\t" + "tlbgwi\n\t" + ".set pop"); +} + +static inline void guest_tlb_write_random(void) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set noreorder\n\t" + ".set virt\n\t" + "tlbgwr\n\t" + ".set pop"); +} + +/* + * Guest TLB Invalidate Flush + */ +static inline void guest_tlbinvf(void) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set noreorder\n\t" + ".set virt\n\t" + "tlbginvf\n\t" + ".set pop"); +} + +#else /* TOOLCHAIN_SUPPORTS_VIRT */ + +/* + * Guest TLB operations. + * + * It is responsibility of the caller to take care of any TLB hazards. + */ +static inline void guest_tlb_probe(void) +{ + __asm__ __volatile__( + "# tlbgp\n\t" + _ASM_INSN_IF_MIPS(0x42000010) + _ASM_INSN32_IF_MM(0x0000017c)); +} + +static inline void guest_tlb_read(void) +{ + __asm__ __volatile__( + "# tlbgr\n\t" + _ASM_INSN_IF_MIPS(0x42000009) + _ASM_INSN32_IF_MM(0x0000117c)); +} + +static inline void guest_tlb_write_indexed(void) +{ + __asm__ __volatile__( + "# tlbgwi\n\t" + _ASM_INSN_IF_MIPS(0x4200000a) + _ASM_INSN32_IF_MM(0x0000217c)); +} + +static inline void guest_tlb_write_random(void) +{ + __asm__ __volatile__( + "# tlbgwr\n\t" + _ASM_INSN_IF_MIPS(0x4200000e) + _ASM_INSN32_IF_MM(0x0000317c)); +} + +/* + * Guest TLB Invalidate Flush + */ +static inline void guest_tlbinvf(void) +{ + __asm__ __volatile__( + "# tlbginvf\n\t" + _ASM_INSN_IF_MIPS(0x4200000c) + _ASM_INSN32_IF_MM(0x0000517c)); +} + +#endif /* !TOOLCHAIN_SUPPORTS_VIRT */ + +/* + * Manipulate bits in a register. + */ +#define __BUILD_SET_COMMON(name) \ static inline unsigned int \ -set_c0_##name(unsigned int set) \ +set_##name(unsigned int set) \ { \ unsigned int res, new; \ \ - res = read_c0_##name(); \ + res = read_##name(); \ new = res | set; \ - write_c0_##name(new); \ + write_##name(new); \ \ return res; \ } \ \ static inline unsigned int \ -clear_c0_##name(unsigned int clear) \ +clear_##name(unsigned int clear) \ { \ unsigned int res, new; \ \ - res = read_c0_##name(); \ + res = read_##name(); \ new = res & ~clear; \ - write_c0_##name(new); \ + write_##name(new); \ \ return res; \ } \ \ static inline unsigned int \ -change_c0_##name(unsigned int change, unsigned int val) \ +change_##name(unsigned int change, unsigned int val) \ { \ unsigned int res, new; \ \ - res = read_c0_##name(); \ + res = read_##name(); \ new = res & ~change; \ new |= (val & change); \ - write_c0_##name(new); \ + write_##name(new); \ \ return res; \ } +/* + * Manipulate bits in a c0 register. + */ +#define __BUILD_SET_C0(name) __BUILD_SET_COMMON(c0_##name) + __BUILD_SET_C0(status) __BUILD_SET_C0(cause) __BUILD_SET_C0(config) @@ -2050,6 +2622,11 @@ __BUILD_SET_C0(intcontrol) __BUILD_SET_C0(intctl) __BUILD_SET_C0(srsmap) __BUILD_SET_C0(pagegrain) +__BUILD_SET_C0(guestctl0) +__BUILD_SET_C0(guestctl0ext) +__BUILD_SET_C0(guestctl1) +__BUILD_SET_C0(guestctl2) +__BUILD_SET_C0(guestctl3) __BUILD_SET_C0(brcm_config_0) __BUILD_SET_C0(brcm_bus_pll) __BUILD_SET_C0(brcm_reset) @@ -2059,12 +2636,21 @@ __BUILD_SET_C0(brcm_config) __BUILD_SET_C0(brcm_mode) /* + * Manipulate bits in a guest c0 register. + */ +#define __BUILD_SET_GC0(name) __BUILD_SET_COMMON(gc0_##name) + +__BUILD_SET_GC0(status) +__BUILD_SET_GC0(cause) +__BUILD_SET_GC0(ebase) + +/* * Return low 10 bits of ebase. * Note that under KVM (MIPSVZ) this returns vcpu id. */ static inline unsigned int get_ebase_cpunum(void) { - return read_c0_ebase() & 0x3ff; + return read_c0_ebase() & MIPS_EBASE_CPUNUM; } #endif /* !__ASSEMBLY__ */ |