diff options
Diffstat (limited to 'arch/blackfin/mach-bf548/include')
25 files changed, 22051 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h new file mode 100644 index 000000000000..3ad59655881a --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h @@ -0,0 +1,100 @@ +/* + * File: include/asm-blackfin/mach-bf548/anomaly.h + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * Copyright (C) 2004-2007 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +/* This file shoule be up to date with: + * - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List + */ + +#ifndef _MACH_ANOMALY_H_ +#define _MACH_ANOMALY_H_ + +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ +#define ANOMALY_05000074 (1) +/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ +#define ANOMALY_05000119 (1) +/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ +#define ANOMALY_05000122 (1) +/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ +#define ANOMALY_05000245 (1) +/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ +#define ANOMALY_05000265 (1) +/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ +#define ANOMALY_05000272 (1) +/* False Hardware Error Exception when ISR context is not restored */ +#define ANOMALY_05000281 (__SILICON_REVISION__ < 1) +/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ +#define ANOMALY_05000304 (__SILICON_REVISION__ < 1) +/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ +#define ANOMALY_05000310 (1) +/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +#define ANOMALY_05000312 (__SILICON_REVISION__ < 1) +/* TWI Slave Boot Mode Is Not Functional */ +#define ANOMALY_05000324 (__SILICON_REVISION__ < 1) +/* External FIFO Boot Mode Is Not Functional */ +#define ANOMALY_05000325 (__SILICON_REVISION__ < 1) +/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ +#define ANOMALY_05000327 (__SILICON_REVISION__ < 1) +/* Incorrect Access of OTP_STATUS During otp_write() Function */ +#define ANOMALY_05000328 (__SILICON_REVISION__ < 1) +/* Synchronous Burst Flash Boot Mode Is Not Functional */ +#define ANOMALY_05000329 (__SILICON_REVISION__ < 1) +/* Host DMA Boot Mode Is Not Functional */ +#define ANOMALY_05000330 (__SILICON_REVISION__ < 1) +/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ +#define ANOMALY_05000334 (__SILICON_REVISION__ < 1) +/* Inadequate Rotary Debounce Logic Duration */ +#define ANOMALY_05000335 (__SILICON_REVISION__ < 1) +/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ +#define ANOMALY_05000336 (__SILICON_REVISION__ < 1) +/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ +#define ANOMALY_05000337 (__SILICON_REVISION__ < 1) +/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ +#define ANOMALY_05000338 (__SILICON_REVISION__ < 1) +/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ +#define ANOMALY_05000340 (__SILICON_REVISION__ < 1) +/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ +#define ANOMALY_05000344 (__SILICON_REVISION__ < 1) +/* USB Calibration Value Is Not Intialized */ +#define ANOMALY_05000346 (__SILICON_REVISION__ < 1) +/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */ +#define ANOMALY_05000347 (__SILICON_REVISION__ < 1) +/* Data Lost when Core Reads SDH Data FIFO */ +#define ANOMALY_05000349 (__SILICON_REVISION__ < 1) +/* PLL Status Register Is Inaccurate */ +#define ANOMALY_05000351 (__SILICON_REVISION__ < 1) +/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ +#define ANOMALY_05000357 (1) +/* External Memory Read Access Hangs Core With PLL Bypass */ +#define ANOMALY_05000360 (1) +/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ +#define ANOMALY_05000365 (1) +/* Addressing Conflict between Boot ROM and Asynchronous Memory */ +#define ANOMALY_05000369 (1) +/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ +#define ANOMALY_05000371 (1) +/* Mobile DDR Operation Not Functional */ +#define ANOMALY_05000377 (1) +/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ +#define ANOMALY_05000378 (1) + +/* Anomalies that don't exist on this proc */ +#define ANOMALY_05000125 (0) +#define ANOMALY_05000158 (0) +#define ANOMALY_05000183 (0) +#define ANOMALY_05000198 (0) +#define ANOMALY_05000230 (0) +#define ANOMALY_05000244 (0) +#define ANOMALY_05000261 (0) +#define ANOMALY_05000263 (0) +#define ANOMALY_05000266 (0) +#define ANOMALY_05000273 (0) +#define ANOMALY_05000311 (0) +#define ANOMALY_05000323 (0) +#define ANOMALY_05000363 (0) + +#endif diff --git a/arch/blackfin/mach-bf548/include/mach/bf548.h b/arch/blackfin/mach-bf548/include/mach/bf548.h new file mode 100644 index 000000000000..e748588e8930 --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/bf548.h @@ -0,0 +1,127 @@ +/* + * File: include/asm-blackfin/mach-bf548/bf548.h + * Based on: + * Author: + * + * Created: + * Description: System MMR register and memory map for ADSP-BF548 + * + * Modified: + * Copyright 2004-2007 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MACH_BF548_H__ +#define __MACH_BF548_H__ + +#define SUPPORTED_REVID 0 + +#define OFFSET_(x) ((x) & 0x0000FFFF) + +/*some misc defines*/ +#define IMASK_IVG15 0x8000 +#define IMASK_IVG14 0x4000 +#define IMASK_IVG13 0x2000 +#define IMASK_IVG12 0x1000 + +#define IMASK_IVG11 0x0800 +#define IMASK_IVG10 0x0400 +#define IMASK_IVG9 0x0200 +#define IMASK_IVG8 0x0100 + +#define IMASK_IVG7 0x0080 +#define IMASK_IVGTMR 0x0040 +#define IMASK_IVGHW 0x0020 + +/***************************/ + + +#define BFIN_DSUBBANKS 4 +#define BFIN_DWAYS 2 +#define BFIN_DLINES 64 +#define BFIN_ISUBBANKS 4 +#define BFIN_IWAYS 4 +#define BFIN_ILINES 32 + +#define WAY0_L 0x1 +#define WAY1_L 0x2 +#define WAY01_L 0x3 +#define WAY2_L 0x4 +#define WAY02_L 0x5 +#define WAY12_L 0x6 +#define WAY012_L 0x7 + +#define WAY3_L 0x8 +#define WAY03_L 0x9 +#define WAY13_L 0xA +#define WAY013_L 0xB + +#define WAY32_L 0xC +#define WAY320_L 0xD +#define WAY321_L 0xE +#define WAYALL_L 0xF + +#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ + +/********************************* EBIU Settings ************************************/ +#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0) +#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2) + +#ifdef CONFIG_C_AMBEN_ALL +#define V_AMBEN AMBEN_ALL +#endif +#ifdef CONFIG_C_AMBEN +#define V_AMBEN 0x0 +#endif +#ifdef CONFIG_C_AMBEN_B0 +#define V_AMBEN AMBEN_B0 +#endif +#ifdef CONFIG_C_AMBEN_B0_B1 +#define V_AMBEN AMBEN_B0_B1 +#endif +#ifdef CONFIG_C_AMBEN_B0_B1_B2 +#define V_AMBEN AMBEN_B0_B1_B2 +#endif +#ifdef CONFIG_C_AMCKEN +#define V_AMCKEN AMCKEN +#else +#define V_AMCKEN 0x0 +#endif + +#define AMGCTLVAL (V_AMBEN | V_AMCKEN) + +#if defined(CONFIG_BF542) +# define CPU "BF542" +# define CPUID 0x027c8000 +#elif defined(CONFIG_BF544) +# define CPU "BF544" +# define CPUID 0x027c8000 +#elif defined(CONFIG_BF547) +# define CPU "BF547" +#elif defined(CONFIG_BF548) +# define CPU "BF548" +# define CPUID 0x027c6000 +#elif defined(CONFIG_BF549) +# define CPU "BF549" +#else +# define CPU "UNKNOWN" +# define CPUID 0x0 +#endif + +#endif /* __MACH_BF48_H__ */ diff --git a/arch/blackfin/mach-bf548/include/mach/bf54x-lq043.h b/arch/blackfin/mach-bf548/include/mach/bf54x-lq043.h new file mode 100644 index 000000000000..9c7ca62a45eb --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/bf54x-lq043.h @@ -0,0 +1,30 @@ +#ifndef BF54X_LQ043_H +#define BF54X_LQ043_H + +struct bfin_bf54xfb_val { + unsigned int defval; + unsigned int min; + unsigned int max; +}; + +struct bfin_bf54xfb_mach_info { + unsigned char fixed_syncs; /* do not update sync/border */ + + /* LCD types */ + int type; + + /* Screen size */ + int width; + int height; + + /* Screen info */ + struct bfin_bf54xfb_val xres; + struct bfin_bf54xfb_val yres; + struct bfin_bf54xfb_val bpp; + + /* GPIOs */ + unsigned short disp; + +}; + +#endif /* BF54X_LQ043_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/bf54x_keys.h b/arch/blackfin/mach-bf548/include/mach/bf54x_keys.h new file mode 100644 index 000000000000..1fb4ec77cc25 --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/bf54x_keys.h @@ -0,0 +1,17 @@ +#ifndef _BFIN_KPAD_H +#define _BFIN_KPAD_H + +struct bfin_kpad_platform_data { + int rows; + int cols; + const unsigned int *keymap; + unsigned short keymapsize; + unsigned short repeat; + u32 debounce_time; /* in ns */ + u32 coldrive_time; /* in ns */ + u32 keyup_test_interval; /* in ms */ +}; + +#define KEYVAL(col, row, val) (((1 << col) << 24) | ((1 << row) << 16) | (val)) + +#endif diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h new file mode 100644 index 000000000000..5e29446a8e03 --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h @@ -0,0 +1,220 @@ +/* + * file: include/asm-blackfin/mach-bf548/bfin_serial_5xx.h + * based on: + * author: + * + * created: + * description: + * blackfin serial driver head file + * rev: + * + * modified: + * + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + +#include <linux/serial.h> +#include <asm/dma.h> +#include <asm/portmux.h> + +#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) +#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) +#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) +#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER_SET)) +#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) +#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR)) +#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) +#define UART_GET_MSR(uart) bfin_read16(((uart)->port.membase + OFFSET_MSR)) +#define UART_GET_MCR(uart) bfin_read16(((uart)->port.membase + OFFSET_MCR)) + +#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) +#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) +#define UART_SET_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v) +#define UART_CLEAR_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v) +#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) +#define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v) +#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) +#define UART_CLEAR_LSR(uart) bfin_write16(((uart)->port.membase + OFFSET_LSR), -1) +#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) +#define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v) + +#define UART_SET_DLAB(uart) /* MMRs not muxed on BF54x */ +#define UART_CLEAR_DLAB(uart) /* MMRs not muxed on BF54x */ + +#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS) +#define UART_SET_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS)) +#define UART_CLEAR_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) & ~MRTS)) +#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v) +#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF) + +#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) +# define CONFIG_SERIAL_BFIN_CTSRTS + +# ifndef CONFIG_UART0_CTS_PIN +# define CONFIG_UART0_CTS_PIN -1 +# endif + +# ifndef CONFIG_UART0_RTS_PIN +# define CONFIG_UART0_RTS_PIN -1 +# endif + +# ifndef CONFIG_UART1_CTS_PIN +# define CONFIG_UART1_CTS_PIN -1 +# endif + +# ifndef CONFIG_UART1_RTS_PIN +# define CONFIG_UART1_RTS_PIN -1 +# endif +#endif +/* + * The pin configuration is different from schematic + */ +struct bfin_serial_port { + struct uart_port port; + unsigned int old_status; +#ifdef CONFIG_SERIAL_BFIN_DMA + int tx_done; + int tx_count; + struct circ_buf rx_dma_buf; + struct timer_list rx_dma_timer; + int rx_dma_nrows; + unsigned int tx_dma_channel; + unsigned int rx_dma_channel; + struct work_struct tx_dma_workqueue; +#endif +#ifdef CONFIG_SERIAL_BFIN_CTSRTS + struct timer_list cts_timer; + int cts_pin; + int rts_pin; +#endif +}; + +struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS]; +struct bfin_serial_res { + unsigned long uart_base_addr; + int uart_irq; +#ifdef CONFIG_SERIAL_BFIN_DMA + unsigned int uart_tx_dma_channel; + unsigned int uart_rx_dma_channel; +#endif +#ifdef CONFIG_SERIAL_BFIN_CTSRTS + int uart_cts_pin; + int uart_rts_pin; +#endif +}; + +struct bfin_serial_res bfin_serial_resource[] = { +#ifdef CONFIG_SERIAL_BFIN_UART0 + { + 0xFFC00400, + IRQ_UART0_RX, +#ifdef CONFIG_SERIAL_BFIN_DMA + CH_UART0_TX, + CH_UART0_RX, +#endif +#ifdef CONFIG_BFIN_UART0_CTSRTS + CONFIG_UART0_CTS_PIN, + CONFIG_UART0_RTS_PIN, +#endif + }, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + { + 0xFFC02000, + IRQ_UART1_RX, +#ifdef CONFIG_SERIAL_BFIN_DMA + CH_UART1_TX, + CH_UART1_RX, +#endif + }, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART2 + { + 0xFFC02100, + IRQ_UART2_RX, +#ifdef CONFIG_SERIAL_BFIN_DMA + CH_UART2_TX, + CH_UART2_RX, +#endif +#ifdef CONFIG_BFIN_UART2_CTSRTS + CONFIG_UART2_CTS_PIN, + CONFIG_UART2_RTS_PIN, +#endif + }, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART3 + { + 0xFFC03100, + IRQ_UART3_RX, +#ifdef CONFIG_SERIAL_BFIN_DMA + CH_UART3_TX, + CH_UART3_RX, +#endif + }, +#endif +}; + +int nr_ports = ARRAY_SIZE(bfin_serial_resource); + +#define DRIVER_NAME "bfin-uart" + +static void bfin_serial_hw_init(struct bfin_serial_port *uart) +{ +#ifdef CONFIG_SERIAL_BFIN_UART0 + peripheral_request(P_UART0_TX, DRIVER_NAME); + peripheral_request(P_UART0_RX, DRIVER_NAME); +#endif + +#ifdef CONFIG_SERIAL_BFIN_UART1 + peripheral_request(P_UART1_TX, DRIVER_NAME); + peripheral_request(P_UART1_RX, DRIVER_NAME); + +#ifdef CONFIG_BFIN_UART1_CTSRTS + peripheral_request(P_UART1_RTS, DRIVER_NAME); + peripheral_request(P_UART1_CTS, DRIVER_NAME); +#endif +#endif + +#ifdef CONFIG_SERIAL_BFIN_UART2 + peripheral_request(P_UART2_TX, DRIVER_NAME); + peripheral_request(P_UART2_RX, DRIVER_NAME); +#endif + +#ifdef CONFIG_SERIAL_BFIN_UART3 + peripheral_request(P_UART3_TX, DRIVER_NAME); + peripheral_request(P_UART3_RX, DRIVER_NAME); + +#ifdef CONFIG_BFIN_UART3_CTSRTS + peripheral_request(P_UART3_RTS, DRIVER_NAME); + peripheral_request(P_UART3_CTS, DRIVER_NAME); +#endif +#endif + SSYNC(); +#ifdef CONFIG_SERIAL_BFIN_CTSRTS + if (uart->cts_pin >= 0) { + gpio_request(uart->cts_pin, DRIVER_NAME); + gpio_direction_input(uart->cts_pin); + } + + if (uart->rts_pin >= 0) { + gpio_request(uart->rts_pin, DRIVER_NAME); + gpio_direction_output(uart->rts_pin, 0); + } +#endif +} diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_sir.h b/arch/blackfin/mach-bf548/include/mach/bfin_sir.h new file mode 100644 index 000000000000..c41f9cf00268 --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/bfin_sir.h @@ -0,0 +1,166 @@ +/* + * Blackfin Infra-red Driver + * + * Copyright 2006-2008 Analog Devices Inc. + * + * Enter bugs at http://blackfin.uclinux.org/ + * + * Licensed under the GPL-2 or later. + * + */ + +#include <linux/serial.h> +#include <asm/dma.h> +#include <asm/portmux.h> + +#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR) +#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL) +#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER_SET) +#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH) +#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR) +#define SIR_UART_GET_LSR(port) bfin_read16((port)->membase + OFFSET_LSR) +#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL) + +#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v) +#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v) +#define SIR_UART_SET_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_SET), v) +#define SIR_UART_CLEAR_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_CLEAR), v) +#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v) +#define SIR_UART_PUT_LSR(port, v) bfin_write16(((port)->membase + OFFSET_LSR), v) +#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v) +#define SIR_UART_CLEAR_LSR(port) bfin_write16(((port)->membase + OFFSET_LSR), -1) +#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v) + +#ifdef CONFIG_SIR_BFIN_DMA +struct dma_rx_buf { + char *buf; + int head; + int tail; + }; +#endif /* CONFIG_SIR_BFIN_DMA */ + +struct bfin_sir_port { + unsigned char __iomem *membase; + unsigned int irq; + unsigned int lsr; + unsigned long clk; + struct net_device *dev; +#ifdef CONFIG_SIR_BFIN_DMA + int tx_done; + struct dma_rx_buf rx_dma_buf; + struct timer_list rx_dma_timer; + int rx_dma_nrows; +#endif /* CONFIG_SIR_BFIN_DMA */ + unsigned int tx_dma_channel; + unsigned int rx_dma_channel; +}; + +struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS]; + +struct bfin_sir_port_res { + unsigned long base_addr; + int irq; + unsigned int rx_dma_channel; + unsigned int tx_dma_channel; +}; + +struct bfin_sir_port_res bfin_sir_port_resource[] = { +#ifdef CONFIG_BFIN_SIR0 + { + 0xFFC00400, + IRQ_UART0_RX, + CH_UART0_RX, + CH_UART0_TX, + }, +#endif +#ifdef CONFIG_BFIN_SIR1 + { + 0xFFC02000, + IRQ_UART1_RX, + CH_UART1_RX, + CH_UART1_TX, + }, +#endif +#ifdef CONFIG_BFIN_SIR2 + { + 0xFFC02100, + IRQ_UART2_RX, + CH_UART2_RX, + CH_UART2_TX, + }, +#endif +#ifdef CONFIG_BFIN_SIR3 + { + 0xFFC03100, + IRQ_UART3_RX, + CH_UART3_RX, + CH_UART3_TX, + }, +#endif +}; + +int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource); + +struct bfin_sir_self { + struct bfin_sir_port *sir_port; + spinlock_t lock; + unsigned int open; + int speed; + int newspeed; + + struct sk_buff *txskb; + struct sk_buff *rxskb; + struct net_device_stats stats; + struct device *dev; + struct irlap_cb *irlap; + struct qos_info qos; + + iobuff_t tx_buff; + iobuff_t rx_buff; + + struct work_struct work; + int mtt; +}; + +#define DRIVER_NAME "bfin_sir" + +static int bfin_sir_hw_init(void) +{ + int ret = -ENODEV; +#ifdef CONFIG_BFIN_SIR0 + ret = peripheral_request(P_UART0_TX, DRIVER_NAME); + if (ret) + return ret; + ret = peripheral_request(P_UART0_RX, DRIVER_NAME); + if (ret) + return ret; +#endif + +#ifdef CONFIG_BFIN_SIR1 + ret = peripheral_request(P_UART1_TX, DRIVER_NAME); + if (ret) + return ret; + ret = peripheral_request(P_UART1_RX, DRIVER_NAME); + if (ret) + return ret; +#endif + +#ifdef CONFIG_BFIN_SIR2 + ret = peripheral_request(P_UART2_TX, DRIVER_NAME); + if (ret) + return ret; + ret = peripheral_request(P_UART2_RX, DRIVER_NAME); + if (ret) + return ret; +#endif + +#ifdef CONFIG_BFIN_SIR3 + ret = peripheral_request(P_UART3_TX, DRIVER_NAME); + if (ret) + return ret; + ret = peripheral_request(P_UART3_RX, DRIVER_NAME); + if (ret) + return ret; +#endif + return ret; +} diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h new file mode 100644 index 000000000000..d6ee74ac0460 --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h @@ -0,0 +1,190 @@ +/* + * File: include/asm-blackfin/mach-bf548/blackfin.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _MACH_BLACKFIN_H_ +#define _MACH_BLACKFIN_H_ + +#define BF548_FAMILY + +#include "bf548.h" +#include "mem_map.h" +#include "anomaly.h" + +#ifdef CONFIG_BF542 +#include "defBF542.h" +#endif + +#ifdef CONFIG_BF544 +#include "defBF544.h" +#endif + +#ifdef CONFIG_BF547 +#include "defBF547.h" +#endif + +#ifdef CONFIG_BF548 +#include "defBF548.h" +#endif + +#ifdef CONFIG_BF549 +#include "defBF549.h" +#endif + +#if !defined(__ASSEMBLY__) +#ifdef CONFIG_BF542 +#include "cdefBF542.h" +#endif +#ifdef CONFIG_BF544 +#include "cdefBF544.h" +#endif +#ifdef CONFIG_BF547 +#include "cdefBF547.h" +#endif +#ifdef CONFIG_BF548 +#include "cdefBF548.h" +#endif +#ifdef CONFIG_BF549 +#include "cdefBF549.h" +#endif + +/* UART 1*/ +#define bfin_read_UART_THR() bfin_read_UART1_THR() +#define bfin_write_UART_THR(val) bfin_write_UART1_THR(val) +#define bfin_read_UART_RBR() bfin_read_UART1_RBR() +#define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val) +#define bfin_read_UART_DLL() bfin_read_UART1_DLL() +#define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val) +#define bfin_read_UART_IER() bfin_read_UART1_IER() +#define bfin_write_UART_IER(val) bfin_write_UART1_IER(val) +#define bfin_read_UART_DLH() bfin_read_UART1_DLH() +#define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val) +#define bfin_read_UART_IIR() bfin_read_UART1_IIR() +#define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val) +#define bfin_read_UART_LCR() bfin_read_UART1_LCR() +#define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val) +#define bfin_read_UART_MCR() bfin_read_UART1_MCR() +#define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val) +#define bfin_read_UART_LSR() bfin_read_UART1_LSR() +#define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val) +#define bfin_read_UART_SCR() bfin_read_UART1_SCR() +#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val) +#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL() +#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val) + +#endif + +/* MAP used DEFINES from BF533 to BF54x - so we don't need to change + * them in the driver, kernel, etc. */ + +/* UART_IIR Register */ +#define STATUS(x) ((x << 1) & 0x06) +#define STATUS_P1 0x02 +#define STATUS_P0 0x01 + +/* UART 0*/ + +/* DMA Channnel */ +#define bfin_read_CH_UART_RX() bfin_read_CH_UART1_RX() +#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART1_RX(val) +#define bfin_read_CH_UART_TX() bfin_read_CH_UART1_TX() +#define bfin_write_CH_UART_TX(val) bfin_write_CH_UART1_TX(val) +#define CH_UART_RX CH_UART1_RX +#define CH_UART_TX CH_UART1_TX + +/* System Interrupt Controller */ +#define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART1_RX() +#define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART1_RX(val) +#define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART1_TX() +#define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART1_TX(val) +#define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART1_ERROR() +#define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART1_ERROR(val) +#define IRQ_UART_RX IRQ_UART1_RX +#define IRQ_UART_TX IRQ_UART1_TX +#define IRQ_UART_ERROR IRQ_UART1_ERROR + +/* MMR Registers*/ +#define bfin_read_UART_THR() bfin_read_UART1_THR() +#define bfin_write_UART_THR(val) bfin_write_UART1_THR(val) +#define bfin_read_UART_RBR() bfin_read_UART1_RBR() +#define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val) +#define bfin_read_UART_DLL() bfin_read_UART1_DLL() +#define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val) +#define bfin_read_UART_IER() bfin_read_UART1_IER() +#define bfin_write_UART_IER(val) bfin_write_UART1_IER(val) +#define bfin_read_UART_DLH() bfin_read_UART1_DLH() +#define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val) +#define bfin_read_UART_IIR() bfin_read_UART1_IIR() +#define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val) +#define bfin_read_UART_LCR() bfin_read_UART1_LCR() +#define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val) +#define bfin_read_UART_MCR() bfin_read_UART1_MCR() +#define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val) +#define bfin_read_UART_LSR() bfin_read_UART1_LSR() +#define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val) +#define bfin_read_UART_SCR() bfin_read_UART1_SCR() +#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val) +#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL() +#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val) + +#define BFIN_UART_THR UART1_THR +#define BFIN_UART_RBR UART1_RBR +#define BFIN_UART_DLL UART1_DLL +#define BFIN_UART_IER UART1_IER +#define BFIN_UART_DLH UART1_DLH +#define BFIN_UART_IIR UART1_IIR +#define BFIN_UART_LCR UART1_LCR +#define BFIN_UART_MCR UART1_MCR +#define BFIN_UART_LSR UART1_LSR +#define BFIN_UART_SCR UART1_SCR +#define BFIN_UART_GCTL UART1_GCTL + +#define BFIN_UART_NR_PORTS 4 + +#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ +#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ +#define OFFSET_GCTL 0x08 /* Global Control Register */ +#define OFFSET_LCR 0x0C /* Line Control Register */ +#define OFFSET_MCR 0x10 /* Modem Control Register */ +#define OFFSET_LSR 0x14 /* Line Status Register */ +#define OFFSET_MSR 0x18 /* Modem Status Register */ +#define OFFSET_SCR 0x1C /* SCR Scratch Register */ +#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */ +#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */ +#define OFFSET_THR 0x28 /* Transmit Holding register */ +#define OFFSET_RBR 0x2C /* Receive Buffer register */ + +/* PLL_DIV Masks */ +#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ +#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ +#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */ +#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */ + +#endif diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF542.h b/arch/blackfin/mach-bf548/include/mach/cdefBF542.h new file mode 100644 index 000000000000..07aefb9ed79b --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/cdefBF542.h @@ -0,0 +1,590 @@ +/* + * File: include/asm-blackfin/mach-bf548/cdefBF542.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _CDEF_BF542_H +#define _CDEF_BF542_H + +/* include all Core registers and bit definitions */ +#include "defBF542.h" + +/* include core sbfin_read_()ecific register pointer definitions */ +#include <asm/cdef_LPBlackfin.h> + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */ + +/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ +#include "cdefBF54x_base.h" + +/* The following are the #defines needed by ADSP-BF542 that are not in the common header */ + +/* ATAPI Registers */ + +#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL) +#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val) +#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS) +#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val) +#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR) +#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val) +#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF) +#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val) +#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF) +#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val) +#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK) +#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val) +#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS) +#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val) +#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN) +#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val) +#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS) +#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val) +#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE) +#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val) +#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE) +#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val) +#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT) +#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val) +#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT) +#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val) +#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT) +#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val) +#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT) +#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val) +#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0) +#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val) +#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0) +#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val) +#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1) +#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val) +#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0) +#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val) +#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1) +#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val) +#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2) +#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val) +#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0) +#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val) +#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1) +#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val) +#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2) +#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val) +#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3) +#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val) + +/* SDH Registers */ + +#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL) +#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val) +#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL) +#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val) +#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT) +#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val) +#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND) +#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val) +#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD) +#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val) +#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0) +#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val) +#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1) +#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val) +#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2) +#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val) +#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3) +#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val) +#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER) +#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val) +#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH) +#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val) +#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL) +#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val) +#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT) +#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val) +#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS) +#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val) +#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR) +#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val) +#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0) +#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val) +#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1) +#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val) +#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT) +#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val) +#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO) +#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val) +#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS) +#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val) +#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK) +#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val) +#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG) +#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val) +#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN) +#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val) +#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0) +#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val) +#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1) +#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val) +#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2) +#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val) +#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3) +#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val) +#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4) +#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val) +#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5) +#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val) +#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6) +#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val) +#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7) +#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val) + +/* USB Control Registers */ + +#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) +#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) +#define bfin_read_USB_POWER() bfin_read16(USB_POWER) +#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) +#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) +#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) +#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) +#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) +#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) +#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) +#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) +#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) +#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) +#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) +#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) +#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) +#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) +#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) +#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) +#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) +#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) +#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) +#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) +#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) +#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) +#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) + +/* USB Packet Control Registers */ + +#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) +#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) +#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) +#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) +#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) +#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) +#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) +#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) +#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) +#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) +#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) +#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) +#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) +#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) +#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) +#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) +#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) +#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) +#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) +#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) +#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) +#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) +#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) +#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) +#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) +#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) + +/* USB Endbfin_read_()oint FIFO Registers */ + +#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) +#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) +#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) +#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) +#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) +#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) +#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) +#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) +#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) +#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) +#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) +#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) +#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) +#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) +#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) +#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) + +/* USB OTG Control Registers */ + +#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) +#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) +#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) +#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) +#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) +#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) + +/* USB Phy Control Registers */ + +#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) +#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) +#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) +#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) +#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) +#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) +#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) +#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) +#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) +#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) + +/* (APHY_CNTRL is for ADI usage only) */ + +#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) +#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) + +/* (APHY_CALIB is for ADI usage only) */ + +#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) +#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) +#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) +#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) + +/* (PHY_TEST is for ADI usage only) */ + +#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) +#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) +#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) +#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) +#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) +#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) + +/* USB Endbfin_read_()oint 0 Control Registers */ + +#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) +#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) +#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) +#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) +#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) +#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) +#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) +#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) +#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) +#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) +#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) +#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) +#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) +#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) +#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) +#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) +#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) +#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 1 Control Registers */ + +#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) +#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) +#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) +#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) +#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) +#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) +#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) +#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) +#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) +#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) +#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) +#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) +#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) +#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) +#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) +#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) +#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) +#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) +#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) +#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 2 Control Registers */ + +#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) +#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) +#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) +#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) +#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) +#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) +#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) +#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) +#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) +#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) +#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) +#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) +#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) +#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) +#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) +#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) +#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) +#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) +#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) +#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 3 Control Registers */ + +#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) +#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) +#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) +#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) +#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) +#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) +#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) +#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) +#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) +#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) +#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) +#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) +#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) +#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) +#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) +#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) +#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) +#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) +#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) +#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 4 Control Registers */ + +#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) +#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) +#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) +#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) +#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) +#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) +#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) +#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) +#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) +#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) +#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) +#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) +#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) +#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) +#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) +#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) +#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) +#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) +#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) +#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 5 Control Registers */ + +#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) +#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) +#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) +#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) +#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) +#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) +#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) +#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) +#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) +#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) +#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) +#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) +#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) +#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) +#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) +#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) +#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) +#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) +#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) +#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 6 Control Registers */ + +#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) +#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) +#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) +#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) +#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) +#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) +#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) +#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) +#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) +#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) +#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) +#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) +#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) +#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) +#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) +#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) +#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) +#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) +#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) +#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 7 Control Registers */ + +#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) +#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) +#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) +#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) +#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) +#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) +#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) +#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) +#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) +#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) +#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) +#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) +#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) +#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) +#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) +#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) +#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) +#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) +#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) +#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) +#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) +#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) +#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) +#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) + +/* USB Channel 0 Config Registers */ + +#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL) +#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val) +#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW) +#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val) +#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH) +#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val) +#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW) +#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val) +#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH) +#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val) + +/* USB Channel 1 Config Registers */ + +#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL) +#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val) +#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW) +#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val) +#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH) +#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val) +#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW) +#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val) +#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH) +#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val) + +/* USB Channel 2 Config Registers */ + +#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL) +#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val) +#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW) +#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val) +#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH) +#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val) +#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW) +#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val) +#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH) +#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val) + +/* USB Channel 3 Config Registers */ + +#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL) +#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val) +#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW) +#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val) +#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH) +#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val) +#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW) +#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val) +#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH) +#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val) + +/* USB Channel 4 Config Registers */ + +#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL) +#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val) +#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW) +#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val) +#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH) +#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val) +#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW) +#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val) +#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH) +#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val) + +/* USB Channel 5 Config Registers */ + +#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL) +#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val) +#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW) +#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val) +#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH) +#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val) +#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW) +#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val) +#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH) +#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val) + +/* USB Channel 6 Config Registers */ + +#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL) +#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val) +#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW) +#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val) +#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH) +#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val) +#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW) +#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val) +#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH) +#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val) + +/* USB Channel 7 Config Registers */ + +#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL) +#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val) +#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW) +#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val) +#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH) +#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val) +#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW) +#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val) +#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH) +#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val) + +/* Keybfin_read_()ad Registers */ + +#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL) +#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val) +#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE) +#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val) +#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL) +#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val) +#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL) +#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val) +#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT) +#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val) +#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL) +#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val) + +#endif /* _CDEF_BF542_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF544.h b/arch/blackfin/mach-bf548/include/mach/cdefBF544.h new file mode 100644 index 000000000000..431a69278991 --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/cdefBF544.h @@ -0,0 +1,945 @@ +/* + * File: include/asm-blackfin/mach-bf548/cdefBF544.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _CDEF_BF544_H +#define _CDEF_BF544_H + +/* include all Core registers and bit definitions */ +#include "defBF544.h" + +/* include core sbfin_read_()ecific register pointer definitions */ +#include <asm/cdef_LPBlackfin.h> + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */ + +/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ +#include "cdefBF54x_base.h" + +/* The following are the #defines needed by ADSP-BF544 that are not in the common header */ + +/* Timer Registers */ + +#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) +#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) +#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) +#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) +#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) +#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) +#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) +#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) +#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) +#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) +#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) +#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) +#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) +#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) +#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) +#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) +#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) +#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) +#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) +#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) +#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) +#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val) +#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) +#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val) + +/* Timer Groubfin_read_() of 3 */ + +#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1) +#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val) +#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1) +#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val) +#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1) +#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val) + +/* EPPI0 Registers */ + +#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS) +#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val) +#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT) +#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val) +#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY) +#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val) +#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT) +#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val) +#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY) +#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val) +#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME) +#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val) +#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE) +#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val) +#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV) +#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val) +#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL) +#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val) +#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL) +#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val) +#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL) +#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val) +#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB) +#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val) +#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF) +#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val) +#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP) +#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val) + +/* Two Wire Interface Registers (TWI1) */ + +/* CAN Controller 1 Config 1 Registers */ + +#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1) +#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val) +#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1) +#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val) +#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1) +#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val) +#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1) +#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val) +#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1) +#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val) +#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1) +#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val) +#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1) +#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val) +#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1) +#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val) +#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1) +#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val) +#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1) +#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val) +#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1) +#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val) +#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1) +#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val) +#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1) +#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val) + +/* CAN Controller 1 Config 2 Registers */ + +#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2) +#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val) +#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2) +#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val) +#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2) +#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val) +#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2) +#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val) +#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2) +#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val) +#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2) +#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val) +#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2) +#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val) +#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2) +#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val) +#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2) +#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val) +#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2) +#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val) +#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2) +#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val) +#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2) +#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val) +#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2) +#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val) + +/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */ + +#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK) +#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val) +#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING) +#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val) +#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG) +#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val) +#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS) +#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val) +#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC) +#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val) +#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS) +#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val) +#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM) +#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val) +#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF) +#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val) +#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL) +#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val) +#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR) +#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val) +#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD) +#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val) +#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR) +#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val) +#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR) +#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val) +#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT) +#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val) +#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC) +#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val) +#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF) +#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val) + +/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */ + +#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L) +#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val) +#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H) +#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val) +#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L) +#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val) +#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H) +#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val) +#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L) +#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val) +#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H) +#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val) +#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L) +#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val) +#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H) +#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val) +#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L) +#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val) +#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H) +#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val) +#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L) +#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val) +#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H) +#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val) +#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L) +#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val) +#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H) +#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val) +#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L) +#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val) +#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H) +#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val) +#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L) +#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val) +#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H) +#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val) +#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L) +#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val) +#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H) +#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val) +#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L) +#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val) +#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H) +#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val) +#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L) +#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val) +#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H) +#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val) +#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L) +#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val) +#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H) +#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val) +#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L) +#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val) +#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H) +#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val) +#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L) +#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val) +#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H) +#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val) +#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L) +#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val) +#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H) +#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val) + +/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */ + +#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L) +#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val) +#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H) +#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val) +#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L) +#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val) +#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H) +#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val) +#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L) +#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val) +#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H) +#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val) +#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L) +#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val) +#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H) +#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val) +#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L) +#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val) +#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H) +#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val) +#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L) +#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val) +#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H) +#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val) +#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L) +#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val) +#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H) +#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val) +#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L) +#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val) +#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H) +#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val) +#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L) +#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val) +#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H) +#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val) +#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L) +#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val) +#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H) +#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val) +#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L) +#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val) +#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H) +#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val) +#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L) +#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val) +#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H) +#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val) +#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L) +#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val) +#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H) +#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val) +#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L) +#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val) +#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H) +#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val) +#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L) +#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val) +#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H) +#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val) +#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L) +#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val) +#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H) +#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val) + +/* CAN Controller 1 Mailbox Data Registers */ + +#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0) +#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val) +#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1) +#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val) +#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2) +#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val) +#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3) +#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val) +#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH) +#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val) +#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP) +#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val) +#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0) +#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val) +#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1) +#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val) +#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0) +#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val) +#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1) +#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val) +#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2) +#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val) +#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3) +#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val) +#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH) +#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val) +#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP) +#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val) +#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0) +#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val) +#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1) +#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val) +#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0) +#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val) +#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1) +#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val) +#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2) +#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val) +#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3) +#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val) +#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH) +#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val) +#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP) +#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val) +#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0) +#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val) +#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1) +#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val) +#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0) +#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val) +#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1) +#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val) +#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2) +#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val) +#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3) +#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val) +#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH) +#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val) +#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP) +#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val) +#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0) +#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val) +#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1) +#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val) +#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0) +#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val) +#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1) +#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val) +#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2) +#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val) +#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3) +#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val) +#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH) +#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val) +#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP) +#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val) +#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0) +#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val) +#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1) +#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val) +#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0) +#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val) +#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1) +#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val) +#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2) +#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val) +#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3) +#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val) +#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH) +#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val) +#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP) +#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val) +#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0) +#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val) +#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1) +#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val) +#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0) +#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val) +#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1) +#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val) +#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2) +#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val) +#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3) +#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val) +#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH) +#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val) +#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP) +#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val) +#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0) +#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val) +#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1) +#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val) +#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0) +#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val) +#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1) +#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val) +#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2) +#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val) +#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3) +#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val) +#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH) +#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val) +#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP) +#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val) +#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0) +#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val) +#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1) +#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val) +#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0) +#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val) +#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1) +#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val) +#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2) +#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val) +#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3) +#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val) +#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH) +#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val) +#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP) +#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val) +#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0) +#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val) +#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1) +#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val) +#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0) +#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val) +#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1) +#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val) +#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2) +#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val) +#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3) +#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val) +#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH) +#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val) +#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP) +#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val) +#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0) +#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val) +#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1) +#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val) +#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0) +#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val) +#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1) +#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val) +#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2) +#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val) +#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3) +#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val) +#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH) +#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val) +#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP) +#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val) +#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0) +#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val) +#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1) +#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val) +#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0) +#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val) +#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1) +#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val) +#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2) +#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val) +#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3) +#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val) +#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH) +#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val) +#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP) +#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val) +#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0) +#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val) +#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1) +#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val) +#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0) +#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val) +#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1) +#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val) +#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2) +#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val) +#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3) +#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val) +#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH) +#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val) +#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP) +#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val) +#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0) +#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val) +#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1) +#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val) +#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0) +#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val) +#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1) +#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val) +#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2) +#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val) +#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3) +#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val) +#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH) +#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val) +#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP) +#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val) +#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0) +#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val) +#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1) +#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val) +#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0) +#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val) +#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1) +#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val) +#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2) +#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val) +#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3) +#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val) +#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH) +#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val) +#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP) +#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val) +#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0) +#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val) +#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1) +#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val) +#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0) +#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val) +#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1) +#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val) +#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2) +#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val) +#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3) +#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val) +#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH) +#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val) +#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP) +#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val) +#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0) +#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val) +#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1) +#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val) + +/* CAN Controller 1 Mailbox Data Registers */ + +#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0) +#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val) +#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1) +#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val) +#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2) +#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val) +#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3) +#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val) +#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH) +#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val) +#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP) +#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val) +#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0) +#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val) +#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1) +#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val) +#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0) +#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val) +#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1) +#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val) +#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2) +#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val) +#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3) +#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val) +#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH) +#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val) +#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP) +#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val) +#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0) +#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val) +#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1) +#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val) +#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0) +#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val) +#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1) +#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val) +#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2) +#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val) +#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3) +#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val) +#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH) +#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val) +#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP) +#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val) +#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0) +#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val) +#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1) +#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val) +#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0) +#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val) +#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1) +#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val) +#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2) +#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val) +#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3) +#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val) +#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH) +#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val) +#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP) +#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val) +#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0) +#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val) +#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1) +#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val) +#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0) +#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val) +#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1) +#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val) +#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2) +#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val) +#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3) +#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val) +#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH) +#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val) +#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP) +#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val) +#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0) +#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val) +#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1) +#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val) +#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0) +#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val) +#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1) +#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val) +#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2) +#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val) +#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3) +#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val) +#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH) +#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val) +#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP) +#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val) +#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0) +#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val) +#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1) +#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val) +#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0) +#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val) +#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1) +#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val) +#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2) +#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val) +#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3) +#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val) +#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH) +#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val) +#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP) +#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val) +#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0) +#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val) +#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1) +#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val) +#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0) +#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val) +#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1) +#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val) +#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2) +#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val) +#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3) +#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val) +#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH) +#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val) +#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP) +#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val) +#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0) +#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val) +#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1) +#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val) +#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0) +#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val) +#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1) +#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val) +#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2) +#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val) +#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3) +#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val) +#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH) +#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val) +#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP) +#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val) +#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0) +#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val) +#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1) +#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val) +#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0) +#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val) +#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1) +#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val) +#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2) +#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val) +#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3) +#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val) +#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH) +#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val) +#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP) +#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val) +#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0) +#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val) +#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1) +#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val) +#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0) +#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val) +#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1) +#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val) +#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2) +#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val) +#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3) +#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val) +#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH) +#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val) +#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP) +#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val) +#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0) +#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val) +#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1) +#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val) +#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0) +#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val) +#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1) +#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val) +#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2) +#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val) +#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3) +#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val) +#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH) +#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val) +#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP) +#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val) +#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0) +#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val) +#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1) +#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val) +#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0) +#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val) +#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1) +#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val) +#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2) +#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val) +#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3) +#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val) +#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH) +#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val) +#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP) +#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val) +#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0) +#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val) +#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1) +#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val) +#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0) +#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val) +#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1) +#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val) +#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2) +#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val) +#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3) +#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val) +#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH) +#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val) +#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP) +#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val) +#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0) +#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val) +#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1) +#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val) +#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0) +#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val) +#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1) +#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val) +#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2) +#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val) +#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3) +#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val) +#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH) +#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val) +#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP) +#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val) +#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0) +#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val) +#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1) +#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val) +#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0) +#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val) +#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1) +#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val) +#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2) +#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val) +#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3) +#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val) +#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH) +#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val) +#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP) +#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val) +#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0) +#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val) +#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1) +#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val) + +/* HOST Port Registers */ + +#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) +#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) +#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) +#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) +#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) +#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) + +/* Pixel Combfin_read_()ositor (PIXC) Registers */ + +#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL) +#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val) +#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL) +#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val) +#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF) +#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val) +#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART) +#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val) +#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND) +#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val) +#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART) +#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val) +#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND) +#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val) +#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP) +#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val) +#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART) +#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val) +#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND) +#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val) +#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART) +#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val) +#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND) +#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val) +#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP) +#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val) +#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT) +#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val) +#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON) +#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val) +#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON) +#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val) +#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON) +#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val) +#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS) +#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val) +#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC) +#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val) + +/* Handshake MDMA 0 Registers */ + +#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) +#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) +#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) +#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) +#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) +#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) +#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) +#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) +#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) +#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) +#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) +#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) +#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) +#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) + +/* Handshake MDMA 1 Registers */ + +#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) +#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) +#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) +#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) +#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) +#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) +#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) +#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) +#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) +#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) +#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) +#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) +#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) +#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) + +#endif /* _CDEF_BF544_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF547.h b/arch/blackfin/mach-bf548/include/mach/cdefBF547.h new file mode 100644 index 000000000000..93376e90dfc5 --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/cdefBF547.h @@ -0,0 +1,832 @@ +/* + * File: include/asm-blackfin/mach-bf548/cdefBF547.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _CDEF_BF548_H +#define _CDEF_BF548_H + +/* include all Core registers and bit definitions */ +#include "defBF548.h" + +/* include core sbfin_read_()ecific register pointer definitions */ +#include <asm/cdef_LPBlackfin.h> + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */ + +/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ +#include "cdefBF54x_base.h" + +/* The following are the #defines needed by ADSP-BF548 that are not in the common header */ + +/* Timer Registers */ + +#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) +#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) +#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) +#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) +#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) +#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) +#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) +#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) +#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) +#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) +#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) +#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) +#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) +#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) +#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) +#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) +#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) +#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) +#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) +#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) +#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) +#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val) +#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) +#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val) + +/* Timer Groubfin_read_() of 3 */ + +#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1) +#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val) +#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1) +#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val) +#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1) +#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val) + +/* SPORT0 Registers */ + +#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) +#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) +#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) +#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) +#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) +#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) +#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) +#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) +#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) +#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) +#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) +#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) +#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) +#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) +#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) +#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) +#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) +#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) +#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) +#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) +#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) +#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) +#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) +#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) +#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) +#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) +#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) +#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) +#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) +#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) +#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) +#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) +#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) +#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) +#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) +#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) +#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) +#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) +#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) +#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) +#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) +#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) +#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) +#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) + +/* EPPI0 Registers */ + +#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS) +#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val) +#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT) +#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val) +#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY) +#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val) +#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT) +#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val) +#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY) +#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val) +#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME) +#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val) +#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE) +#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val) +#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV) +#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val) +#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL) +#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val) +#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL) +#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val) +#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL) +#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val) +#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB) +#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val) +#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF) +#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val) +#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP) +#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val) + +/* UART2 Registers */ + +#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL) +#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val) +#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH) +#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val) +#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL) +#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val) +#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR) +#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val) +#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR) +#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val) +#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR) +#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val) +#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR) +#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val) +#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR) +#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val) +#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET) +#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val) +#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR) +#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val) +#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR) +#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val) + +/* Two Wire Interface Registers (TWI1) */ + +/* SPI2 Registers */ + +#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) +#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val) +#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG) +#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val) +#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT) +#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val) +#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR) +#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val) +#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR) +#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val) +#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD) +#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val) +#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW) +#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val) + +/* ATAPI Registers */ + +#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL) +#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val) +#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS) +#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val) +#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR) +#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val) +#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF) +#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val) +#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF) +#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val) +#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK) +#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val) +#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS) +#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val) +#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN) +#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val) +#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS) +#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val) +#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE) +#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val) +#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE) +#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val) +#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT) +#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val) +#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT) +#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val) +#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT) +#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val) +#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT) +#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val) +#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0) +#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val) +#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0) +#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val) +#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1) +#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val) +#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0) +#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val) +#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1) +#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val) +#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2) +#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val) +#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0) +#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val) +#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1) +#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val) +#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2) +#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val) +#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3) +#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val) + +/* SDH Registers */ + +#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL) +#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val) +#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL) +#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val) +#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT) +#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val) +#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND) +#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val) +#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD) +#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val) +#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0) +#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val) +#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1) +#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val) +#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2) +#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val) +#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3) +#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val) +#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER) +#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val) +#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH) +#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val) +#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL) +#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val) +#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT) +#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val) +#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS) +#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val) +#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR) +#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val) +#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0) +#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val) +#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1) +#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val) +#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT) +#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val) +#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO) +#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val) +#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS) +#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val) +#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK) +#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val) +#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG) +#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val) +#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN) +#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val) +#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0) +#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val) +#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1) +#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val) +#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2) +#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val) +#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3) +#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val) +#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4) +#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val) +#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5) +#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val) +#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6) +#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val) +#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7) +#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val) + +/* HOST Port Registers */ + +#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) +#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) +#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) +#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) +#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) +#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) + +/* USB Control Registers */ + +#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) +#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) +#define bfin_read_USB_POWER() bfin_read16(USB_POWER) +#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) +#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) +#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) +#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) +#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) +#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) +#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) +#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) +#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) +#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) +#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) +#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) +#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) +#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) +#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) +#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) +#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) +#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) +#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) +#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) +#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) +#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) +#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) + +/* USB Packet Control Registers */ + +#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) +#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) +#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) +#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) +#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) +#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) +#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) +#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) +#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) +#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) +#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) +#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) +#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) +#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) +#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) +#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) +#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) +#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) +#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) +#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) +#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) +#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) +#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) +#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) +#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) +#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) + +/* USB Endbfin_read_()oint FIFO Registers */ + +#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) +#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) +#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) +#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) +#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) +#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) +#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) +#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) +#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) +#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) +#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) +#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) +#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) +#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) +#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) +#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) + +/* USB OTG Control Registers */ + +#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) +#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) +#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) +#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) +#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) +#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) + +/* USB Phy Control Registers */ + +#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) +#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) +#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) +#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) +#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) +#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) +#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) +#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) +#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) +#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) + +/* (APHY_CNTRL is for ADI usage only) */ + +#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) +#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) + +/* (APHY_CALIB is for ADI usage only) */ + +#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) +#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) +#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) +#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) + +/* (PHY_TEST is for ADI usage only) */ + +#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) +#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) +#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) +#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) +#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) +#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) + +/* USB Endbfin_read_()oint 0 Control Registers */ + +#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) +#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) +#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) +#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) +#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) +#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) +#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) +#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) +#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) +#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) +#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) +#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) +#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) +#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) +#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) +#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) +#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) +#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 1 Control Registers */ + +#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) +#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) +#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) +#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) +#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) +#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) +#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) +#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) +#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) +#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) +#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) +#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) +#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) +#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) +#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) +#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) +#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) +#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) +#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) +#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 2 Control Registers */ + +#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) +#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) +#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) +#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) +#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) +#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) +#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) +#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) +#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) +#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) +#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) +#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) +#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) +#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) +#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) +#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) +#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) +#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) +#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) +#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 3 Control Registers */ + +#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) +#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) +#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) +#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) +#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) +#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) +#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) +#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) +#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) +#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) +#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) +#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) +#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) +#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) +#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) +#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) +#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) +#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) +#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) +#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 4 Control Registers */ + +#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) +#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) +#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) +#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) +#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) +#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) +#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) +#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) +#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) +#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) +#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) +#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) +#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) +#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) +#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) +#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) +#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) +#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) +#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) +#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 5 Control Registers */ + +#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) +#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) +#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) +#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) +#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) +#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) +#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) +#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) +#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) +#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) +#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) +#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) +#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) +#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) +#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) +#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) +#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) +#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) +#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) +#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 6 Control Registers */ + +#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) +#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) +#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) +#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) +#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) +#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) +#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) +#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) +#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) +#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) +#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) +#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) +#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) +#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) +#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) +#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) +#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) +#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) +#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) +#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 7 Control Registers */ + +#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) +#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) +#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) +#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) +#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) +#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) +#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) +#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) +#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) +#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) +#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) +#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) +#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) +#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) +#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) +#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) +#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) +#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) +#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) +#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) +#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) +#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) +#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) +#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) + +/* USB Channel 0 Config Registers */ + +#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL) +#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val) +#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW) +#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val) +#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH) +#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val) +#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW) +#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val) +#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH) +#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val) + +/* USB Channel 1 Config Registers */ + +#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL) +#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val) +#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW) +#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val) +#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH) +#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val) +#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW) +#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val) +#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH) +#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val) + +/* USB Channel 2 Config Registers */ + +#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL) +#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val) +#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW) +#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val) +#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH) +#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val) +#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW) +#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val) +#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH) +#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val) + +/* USB Channel 3 Config Registers */ + +#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL) +#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val) +#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW) +#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val) +#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH) +#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val) +#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW) +#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val) +#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH) +#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val) + +/* USB Channel 4 Config Registers */ + +#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL) +#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val) +#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW) +#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val) +#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH) +#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val) +#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW) +#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val) +#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH) +#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val) + +/* USB Channel 5 Config Registers */ + +#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL) +#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val) +#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW) +#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val) +#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH) +#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val) +#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW) +#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val) +#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH) +#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val) + +/* USB Channel 6 Config Registers */ + +#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL) +#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val) +#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW) +#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val) +#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH) +#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val) +#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW) +#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val) +#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH) +#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val) + +/* USB Channel 7 Config Registers */ + +#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL) +#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val) +#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW) +#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val) +#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH) +#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val) +#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW) +#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val) +#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH) +#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val) + +/* Keybfin_read_()ad Registers */ + +#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL) +#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val) +#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE) +#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val) +#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL) +#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val) +#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL) +#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val) +#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT) +#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val) +#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL) +#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val) + +/* Pixel Combfin_read_()ositor (PIXC) Registers */ + +#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL) +#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val) +#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL) +#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val) +#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF) +#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val) +#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART) +#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val) +#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND) +#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val) +#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART) +#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val) +#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND) +#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val) +#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP) +#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val) +#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART) +#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val) +#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND) +#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val) +#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART) +#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val) +#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND) +#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val) +#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP) +#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val) +#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT) +#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val) +#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON) +#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val) +#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON) +#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val) +#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON) +#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val) +#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS) +#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val) +#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC) +#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val) + +/* Handshake MDMA 0 Registers */ + +#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) +#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) +#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) +#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) +#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) +#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) +#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) +#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) +#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) +#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) +#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) +#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) +#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) +#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) + +/* Handshake MDMA 1 Registers */ + +#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) +#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) +#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) +#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) +#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) +#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) +#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) +#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) +#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) +#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) +#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) +#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) +#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) +#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) + +#endif /* _CDEF_BF548_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h b/arch/blackfin/mach-bf548/include/mach/cdefBF548.h new file mode 100644 index 000000000000..9cd74384136f --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/cdefBF548.h @@ -0,0 +1,1577 @@ +/* + * File: include/asm-blackfin/mach-bf548/cdefBF548.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _CDEF_BF548_H +#define _CDEF_BF548_H + +/* include all Core registers and bit definitions */ +#include "defBF548.h" + +/* include core sbfin_read_()ecific register pointer definitions */ +#include <asm/cdef_LPBlackfin.h> + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */ + +/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ +#include "cdefBF54x_base.h" + +/* The following are the #defines needed by ADSP-BF548 that are not in the common header */ + +/* Timer Registers */ + +#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) +#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) +#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) +#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) +#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) +#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) +#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) +#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) +#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) +#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) +#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) +#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) +#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) +#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) +#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) +#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) +#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) +#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) +#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) +#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) +#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) +#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val) +#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) +#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val) + +/* Timer Groubfin_read_() of 3 */ + +#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1) +#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val) +#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1) +#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val) +#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1) +#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val) + +/* SPORT0 Registers */ + +#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) +#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) +#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) +#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) +#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) +#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) +#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) +#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) +#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) +#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) +#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) +#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) +#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) +#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) +#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) +#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) +#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) +#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) +#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) +#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) +#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) +#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) +#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) +#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) +#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) +#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) +#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) +#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) +#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) +#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) +#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) +#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) +#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) +#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) +#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) +#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) +#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) +#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) +#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) +#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) +#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) +#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) +#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) +#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) + +/* EPPI0 Registers */ + +#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS) +#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val) +#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT) +#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val) +#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY) +#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val) +#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT) +#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val) +#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY) +#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val) +#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME) +#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val) +#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE) +#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val) +#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV) +#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val) +#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL) +#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val) +#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL) +#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val) +#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL) +#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val) +#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB) +#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val) +#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF) +#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val) +#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP) +#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val) + +/* UART2 Registers */ + +#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL) +#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val) +#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH) +#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val) +#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL) +#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val) +#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR) +#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val) +#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR) +#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val) +#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR) +#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val) +#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR) +#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val) +#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR) +#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val) +#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET) +#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val) +#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR) +#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val) +#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR) +#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val) + +/* Two Wire Interface Registers (TWI1) */ + +/* SPI2 Registers */ + +#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) +#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val) +#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG) +#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val) +#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT) +#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val) +#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR) +#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val) +#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR) +#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val) +#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD) +#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val) +#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW) +#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val) + +/* CAN Controller 1 Config 1 Registers */ + +#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1) +#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val) +#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1) +#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val) +#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1) +#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val) +#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1) +#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val) +#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1) +#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val) +#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1) +#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val) +#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1) +#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val) +#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1) +#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val) +#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1) +#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val) +#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1) +#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val) +#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1) +#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val) +#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1) +#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val) +#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1) +#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val) + +/* CAN Controller 1 Config 2 Registers */ + +#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2) +#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val) +#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2) +#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val) +#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2) +#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val) +#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2) +#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val) +#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2) +#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val) +#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2) +#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val) +#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2) +#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val) +#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2) +#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val) +#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2) +#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val) +#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2) +#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val) +#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2) +#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val) +#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2) +#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val) +#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2) +#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val) + +/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */ + +#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK) +#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val) +#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING) +#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val) +#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG) +#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val) +#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS) +#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val) +#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC) +#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val) +#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS) +#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val) +#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM) +#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val) +#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF) +#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val) +#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL) +#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val) +#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR) +#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val) +#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD) +#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val) +#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR) +#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val) +#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR) +#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val) +#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT) +#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val) +#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC) +#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val) +#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF) +#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val) + +/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */ + +#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L) +#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val) +#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H) +#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val) +#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L) +#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val) +#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H) +#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val) +#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L) +#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val) +#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H) +#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val) +#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L) +#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val) +#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H) +#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val) +#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L) +#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val) +#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H) +#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val) +#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L) +#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val) +#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H) +#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val) +#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L) +#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val) +#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H) +#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val) +#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L) +#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val) +#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H) +#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val) +#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L) +#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val) +#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H) +#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val) +#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L) +#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val) +#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H) +#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val) +#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L) +#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val) +#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H) +#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val) +#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L) +#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val) +#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H) +#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val) +#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L) +#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val) +#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H) +#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val) +#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L) +#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val) +#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H) +#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val) +#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L) +#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val) +#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H) +#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val) +#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L) +#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val) +#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H) +#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val) + +/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */ + +#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L) +#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val) +#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H) +#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val) +#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L) +#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val) +#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H) +#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val) +#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L) +#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val) +#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H) +#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val) +#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L) +#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val) +#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H) +#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val) +#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L) +#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val) +#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H) +#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val) +#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L) +#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val) +#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H) +#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val) +#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L) +#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val) +#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H) +#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val) +#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L) +#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val) +#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H) +#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val) +#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L) +#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val) +#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H) +#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val) +#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L) +#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val) +#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H) +#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val) +#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L) +#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val) +#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H) +#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val) +#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L) +#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val) +#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H) +#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val) +#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L) +#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val) +#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H) +#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val) +#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L) +#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val) +#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H) +#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val) +#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L) +#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val) +#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H) +#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val) +#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L) +#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val) +#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H) +#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val) + +/* CAN Controller 1 Mailbox Data Registers */ + +#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0) +#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val) +#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1) +#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val) +#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2) +#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val) +#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3) +#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val) +#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH) +#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val) +#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP) +#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val) +#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0) +#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val) +#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1) +#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val) +#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0) +#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val) +#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1) +#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val) +#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2) +#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val) +#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3) +#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val) +#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH) +#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val) +#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP) +#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val) +#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0) +#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val) +#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1) +#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val) +#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0) +#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val) +#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1) +#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val) +#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2) +#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val) +#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3) +#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val) +#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH) +#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val) +#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP) +#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val) +#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0) +#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val) +#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1) +#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val) +#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0) +#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val) +#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1) +#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val) +#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2) +#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val) +#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3) +#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val) +#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH) +#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val) +#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP) +#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val) +#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0) +#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val) +#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1) +#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val) +#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0) +#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val) +#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1) +#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val) +#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2) +#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val) +#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3) +#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val) +#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH) +#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val) +#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP) +#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val) +#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0) +#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val) +#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1) +#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val) +#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0) +#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val) +#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1) +#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val) +#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2) +#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val) +#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3) +#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val) +#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH) +#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val) +#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP) +#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val) +#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0) +#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val) +#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1) +#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val) +#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0) +#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val) +#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1) +#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val) +#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2) +#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val) +#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3) +#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val) +#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH) +#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val) +#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP) +#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val) +#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0) +#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val) +#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1) +#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val) +#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0) +#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val) +#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1) +#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val) +#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2) +#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val) +#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3) +#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val) +#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH) +#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val) +#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP) +#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val) +#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0) +#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val) +#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1) +#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val) +#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0) +#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val) +#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1) +#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val) +#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2) +#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val) +#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3) +#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val) +#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH) +#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val) +#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP) +#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val) +#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0) +#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val) +#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1) +#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val) +#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0) +#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val) +#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1) +#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val) +#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2) +#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val) +#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3) +#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val) +#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH) +#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val) +#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP) +#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val) +#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0) +#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val) +#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1) +#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val) +#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0) +#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val) +#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1) +#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val) +#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2) +#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val) +#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3) +#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val) +#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH) +#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val) +#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP) +#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val) +#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0) +#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val) +#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1) +#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val) +#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0) +#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val) +#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1) +#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val) +#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2) +#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val) +#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3) +#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val) +#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH) +#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val) +#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP) +#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val) +#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0) +#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val) +#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1) +#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val) +#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0) +#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val) +#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1) +#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val) +#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2) +#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val) +#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3) +#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val) +#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH) +#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val) +#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP) +#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val) +#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0) +#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val) +#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1) +#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val) +#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0) +#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val) +#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1) +#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val) +#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2) +#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val) +#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3) +#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val) +#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH) +#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val) +#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP) +#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val) +#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0) +#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val) +#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1) +#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val) +#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0) +#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val) +#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1) +#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val) +#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2) +#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val) +#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3) +#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val) +#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH) +#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val) +#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP) +#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val) +#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0) +#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val) +#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1) +#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val) +#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0) +#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val) +#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1) +#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val) +#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2) +#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val) +#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3) +#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val) +#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH) +#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val) +#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP) +#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val) +#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0) +#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val) +#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1) +#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val) + +/* CAN Controller 1 Mailbox Data Registers */ + +#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0) +#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val) +#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1) +#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val) +#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2) +#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val) +#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3) +#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val) +#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH) +#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val) +#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP) +#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val) +#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0) +#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val) +#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1) +#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val) +#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0) +#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val) +#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1) +#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val) +#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2) +#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val) +#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3) +#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val) +#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH) +#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val) +#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP) +#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val) +#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0) +#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val) +#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1) +#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val) +#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0) +#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val) +#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1) +#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val) +#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2) +#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val) +#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3) +#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val) +#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH) +#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val) +#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP) +#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val) +#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0) +#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val) +#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1) +#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val) +#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0) +#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val) +#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1) +#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val) +#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2) +#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val) +#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3) +#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val) +#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH) +#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val) +#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP) +#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val) +#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0) +#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val) +#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1) +#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val) +#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0) +#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val) +#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1) +#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val) +#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2) +#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val) +#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3) +#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val) +#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH) +#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val) +#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP) +#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val) +#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0) +#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val) +#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1) +#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val) +#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0) +#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val) +#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1) +#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val) +#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2) +#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val) +#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3) +#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val) +#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH) +#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val) +#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP) +#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val) +#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0) +#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val) +#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1) +#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val) +#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0) +#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val) +#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1) +#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val) +#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2) +#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val) +#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3) +#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val) +#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH) +#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val) +#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP) +#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val) +#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0) +#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val) +#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1) +#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val) +#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0) +#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val) +#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1) +#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val) +#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2) +#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val) +#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3) +#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val) +#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH) +#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val) +#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP) +#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val) +#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0) +#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val) +#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1) +#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val) +#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0) +#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val) +#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1) +#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val) +#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2) +#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val) +#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3) +#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val) +#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH) +#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val) +#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP) +#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val) +#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0) +#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val) +#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1) +#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val) +#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0) +#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val) +#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1) +#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val) +#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2) +#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val) +#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3) +#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val) +#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH) +#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val) +#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP) +#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val) +#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0) +#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val) +#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1) +#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val) +#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0) +#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val) +#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1) +#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val) +#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2) +#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val) +#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3) +#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val) +#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH) +#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val) +#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP) +#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val) +#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0) +#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val) +#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1) +#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val) +#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0) +#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val) +#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1) +#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val) +#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2) +#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val) +#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3) +#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val) +#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH) +#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val) +#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP) +#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val) +#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0) +#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val) +#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1) +#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val) +#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0) +#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val) +#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1) +#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val) +#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2) +#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val) +#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3) +#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val) +#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH) +#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val) +#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP) +#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val) +#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0) +#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val) +#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1) +#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val) +#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0) +#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val) +#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1) +#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val) +#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2) +#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val) +#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3) +#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val) +#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH) +#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val) +#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP) +#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val) +#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0) +#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val) +#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1) +#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val) +#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0) +#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val) +#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1) +#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val) +#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2) +#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val) +#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3) +#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val) +#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH) +#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val) +#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP) +#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val) +#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0) +#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val) +#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1) +#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val) +#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0) +#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val) +#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1) +#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val) +#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2) +#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val) +#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3) +#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val) +#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH) +#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val) +#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP) +#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val) +#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0) +#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val) +#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1) +#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val) + +/* ATAPI Registers */ + +#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL) +#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val) +#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS) +#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val) +#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR) +#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val) +#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF) +#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val) +#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF) +#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val) +#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK) +#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val) +#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS) +#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val) +#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN) +#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val) +#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS) +#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val) +#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE) +#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val) +#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE) +#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val) +#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT) +#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val) +#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT) +#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val) +#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT) +#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val) +#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT) +#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val) +#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0) +#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val) +#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0) +#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val) +#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1) +#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val) +#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0) +#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val) +#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1) +#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val) +#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2) +#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val) +#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0) +#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val) +#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1) +#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val) +#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2) +#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val) +#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3) +#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val) + +/* SDH Registers */ + +#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL) +#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val) +#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL) +#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val) +#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT) +#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val) +#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND) +#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val) +#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD) +#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val) +#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0) +#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val) +#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1) +#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val) +#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2) +#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val) +#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3) +#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val) +#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER) +#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val) +#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH) +#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val) +#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL) +#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val) +#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT) +#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val) +#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS) +#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val) +#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR) +#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val) +#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0) +#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val) +#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1) +#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val) +#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT) +#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val) +#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO) +#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val) +#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS) +#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val) +#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK) +#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val) +#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG) +#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val) +#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN) +#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val) +#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0) +#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val) +#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1) +#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val) +#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2) +#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val) +#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3) +#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val) +#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4) +#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val) +#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5) +#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val) +#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6) +#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val) +#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7) +#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val) + +/* HOST Port Registers */ + +#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) +#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) +#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) +#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) +#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) +#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) + +/* USB Control Registers */ + +#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) +#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) +#define bfin_read_USB_POWER() bfin_read16(USB_POWER) +#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) +#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) +#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) +#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) +#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) +#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) +#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) +#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) +#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) +#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) +#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) +#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) +#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) +#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) +#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) +#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) +#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) +#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) +#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) +#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) +#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) +#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) +#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) + +/* USB Packet Control Registers */ + +#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) +#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) +#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) +#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) +#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) +#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) +#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) +#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) +#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) +#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) +#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) +#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) +#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) +#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) +#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) +#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) +#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) +#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) +#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) +#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) +#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) +#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) +#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) +#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) +#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) +#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) + +/* USB Endbfin_read_()oint FIFO Registers */ + +#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) +#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) +#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) +#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) +#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) +#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) +#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) +#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) +#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) +#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) +#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) +#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) +#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) +#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) +#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) +#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) + +/* USB OTG Control Registers */ + +#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) +#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) +#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) +#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) +#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) +#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) + +/* USB Phy Control Registers */ + +#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) +#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) +#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) +#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) +#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) +#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) +#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) +#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) +#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) +#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) + +/* (APHY_CNTRL is for ADI usage only) */ + +#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) +#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) + +/* (APHY_CALIB is for ADI usage only) */ + +#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) +#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) +#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) +#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) + +/* (PHY_TEST is for ADI usage only) */ + +#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) +#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) +#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) +#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) +#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) +#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) + +/* USB Endbfin_read_()oint 0 Control Registers */ + +#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) +#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) +#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) +#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) +#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) +#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) +#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) +#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) +#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) +#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) +#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) +#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) +#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) +#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) +#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) +#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) +#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) +#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 1 Control Registers */ + +#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) +#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) +#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) +#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) +#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) +#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) +#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) +#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) +#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) +#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) +#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) +#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) +#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) +#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) +#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) +#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) +#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) +#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) +#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) +#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 2 Control Registers */ + +#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) +#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) +#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) +#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) +#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) +#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) +#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) +#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) +#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) +#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) +#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) +#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) +#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) +#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) +#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) +#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) +#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) +#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) +#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) +#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 3 Control Registers */ + +#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) +#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) +#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) +#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) +#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) +#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) +#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) +#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) +#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) +#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) +#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) +#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) +#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) +#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) +#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) +#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) +#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) +#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) +#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) +#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 4 Control Registers */ + +#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) +#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) +#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) +#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) +#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) +#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) +#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) +#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) +#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) +#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) +#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) +#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) +#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) +#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) +#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) +#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) +#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) +#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) +#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) +#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 5 Control Registers */ + +#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) +#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) +#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) +#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) +#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) +#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) +#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) +#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) +#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) +#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) +#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) +#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) +#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) +#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) +#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) +#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) +#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) +#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) +#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) +#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 6 Control Registers */ + +#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) +#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) +#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) +#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) +#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) +#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) +#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) +#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) +#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) +#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) +#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) +#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) +#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) +#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) +#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) +#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) +#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) +#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) +#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) +#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 7 Control Registers */ + +#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) +#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) +#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) +#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) +#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) +#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) +#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) +#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) +#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) +#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) +#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) +#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) +#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) +#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) +#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) +#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) +#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) +#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) +#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) +#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) +#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) +#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) +#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) +#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) + +/* USB Channel 0 Config Registers */ + +#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL) +#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val) +#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW) +#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val) +#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH) +#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val) +#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW) +#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val) +#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH) +#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val) + +/* USB Channel 1 Config Registers */ + +#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL) +#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val) +#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW) +#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val) +#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH) +#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val) +#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW) +#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val) +#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH) +#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val) + +/* USB Channel 2 Config Registers */ + +#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL) +#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val) +#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW) +#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val) +#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH) +#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val) +#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW) +#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val) +#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH) +#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val) + +/* USB Channel 3 Config Registers */ + +#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL) +#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val) +#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW) +#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val) +#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH) +#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val) +#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW) +#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val) +#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH) +#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val) + +/* USB Channel 4 Config Registers */ + +#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL) +#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val) +#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW) +#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val) +#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH) +#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val) +#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW) +#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val) +#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH) +#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val) + +/* USB Channel 5 Config Registers */ + +#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL) +#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val) +#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW) +#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val) +#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH) +#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val) +#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW) +#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val) +#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH) +#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val) + +/* USB Channel 6 Config Registers */ + +#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL) +#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val) +#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW) +#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val) +#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH) +#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val) +#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW) +#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val) +#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH) +#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val) + +/* USB Channel 7 Config Registers */ + +#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL) +#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val) +#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW) +#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val) +#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH) +#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val) +#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW) +#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val) +#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH) +#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val) + +/* Keybfin_read_()ad Registers */ + +#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL) +#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val) +#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE) +#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val) +#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL) +#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val) +#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL) +#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val) +#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT) +#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val) +#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL) +#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val) + +/* Pixel Combfin_read_()ositor (PIXC) Registers */ + +#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL) +#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val) +#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL) +#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val) +#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF) +#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val) +#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART) +#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val) +#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND) +#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val) +#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART) +#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val) +#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND) +#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val) +#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP) +#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val) +#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART) +#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val) +#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND) +#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val) +#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART) +#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val) +#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND) +#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val) +#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP) +#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val) +#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT) +#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val) +#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON) +#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val) +#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON) +#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val) +#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON) +#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val) +#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS) +#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val) +#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC) +#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val) + +/* Handshake MDMA 0 Registers */ + +#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) +#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) +#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) +#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) +#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) +#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) +#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) +#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) +#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) +#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) +#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) +#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) +#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) +#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) + +/* Handshake MDMA 1 Registers */ + +#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) +#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) +#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) +#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) +#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) +#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) +#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) +#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) +#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) +#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) +#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) +#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) +#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) +#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) + +#endif /* _CDEF_BF548_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h b/arch/blackfin/mach-bf548/include/mach/cdefBF549.h new file mode 100644 index 000000000000..ead360b69dea --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/cdefBF549.h @@ -0,0 +1,1863 @@ +/* + * File: include/asm-blackfin/mach-bf549/cdefBF549.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _CDEF_BF549_H +#define _CDEF_BF549_H + +/* include all Core registers and bit definitions */ +#include "defBF549.h" + +/* include core sbfin_read_()ecific register pointer definitions */ +#include <asm/cdef_LPBlackfin.h> + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */ + +/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ +#include "cdefBF54x_base.h" + +/* The following are the #defines needed by ADSP-BF549 that are not in the common header */ + +/* Timer Registers */ + +#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) +#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) +#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) +#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) +#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) +#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) +#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) +#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) +#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) +#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) +#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) +#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) +#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) +#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) +#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) +#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) +#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) +#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) +#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) +#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) +#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) +#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val) +#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) +#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val) + +/* Timer Groubfin_read_() of 3 */ + +#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1) +#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val) +#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1) +#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val) +#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1) +#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val) + +/* SPORT0 Registers */ + +#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) +#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) +#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) +#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) +#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) +#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) +#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) +#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) +#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) +#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) +#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) +#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) +#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) +#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) +#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) +#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) +#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) +#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) +#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) +#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) +#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) +#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) +#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) +#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) +#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) +#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) +#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) +#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) +#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) +#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) +#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) +#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) +#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) +#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) +#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) +#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) +#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) +#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) +#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) +#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) +#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) +#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) +#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) +#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) + +/* EPPI0 Registers */ + +#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS) +#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val) +#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT) +#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val) +#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY) +#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val) +#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT) +#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val) +#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY) +#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val) +#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME) +#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val) +#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE) +#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val) +#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV) +#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val) +#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL) +#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val) +#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL) +#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val) +#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL) +#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val) +#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB) +#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val) +#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF) +#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val) +#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP) +#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val) + +/* UART2 Registers */ + +#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL) +#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val) +#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH) +#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val) +#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL) +#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val) +#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR) +#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val) +#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR) +#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val) +#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR) +#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val) +#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR) +#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val) +#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR) +#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val) +#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET) +#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val) +#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR) +#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val) +#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR) +#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val) + +/* Two Wire Interface Registers (TWI1) */ + +/* SPI2 Registers */ + +#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) +#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val) +#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG) +#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val) +#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT) +#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val) +#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR) +#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val) +#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR) +#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val) +#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD) +#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val) +#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW) +#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val) + +/* MXVR Registers */ + +#define bfin_read_MXVR_CONFIG() bfin_read16(MXVR_CONFIG) +#define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val) +#define bfin_read_MXVR_STATE_0() bfin_read32(MXVR_STATE_0) +#define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val) +#define bfin_read_MXVR_STATE_1() bfin_read32(MXVR_STATE_1) +#define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val) +#define bfin_read_MXVR_INT_STAT_0() bfin_read32(MXVR_INT_STAT_0) +#define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val) +#define bfin_read_MXVR_INT_STAT_1() bfin_read32(MXVR_INT_STAT_1) +#define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val) +#define bfin_read_MXVR_INT_EN_0() bfin_read32(MXVR_INT_EN_0) +#define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val) +#define bfin_read_MXVR_INT_EN_1() bfin_read32(MXVR_INT_EN_1) +#define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val) +#define bfin_read_MXVR_POSITION() bfin_read16(MXVR_POSITION) +#define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val) +#define bfin_read_MXVR_MAX_POSITION() bfin_read16(MXVR_MAX_POSITION) +#define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val) +#define bfin_read_MXVR_DELAY() bfin_read16(MXVR_DELAY) +#define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val) +#define bfin_read_MXVR_MAX_DELAY() bfin_read16(MXVR_MAX_DELAY) +#define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val) +#define bfin_read_MXVR_LADDR() bfin_read32(MXVR_LADDR) +#define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val) +#define bfin_read_MXVR_GADDR() bfin_read16(MXVR_GADDR) +#define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val) +#define bfin_read_MXVR_AADDR() bfin_read32(MXVR_AADDR) +#define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val) + +/* MXVR Allocation Table Registers */ + +#define bfin_read_MXVR_ALLOC_0() bfin_read32(MXVR_ALLOC_0) +#define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val) +#define bfin_read_MXVR_ALLOC_1() bfin_read32(MXVR_ALLOC_1) +#define bfin_write_MXVR_ALLOC_1(val) bfin_write32(MXVR_ALLOC_1, val) +#define bfin_read_MXVR_ALLOC_2() bfin_read32(MXVR_ALLOC_2) +#define bfin_write_MXVR_ALLOC_2(val) bfin_write32(MXVR_ALLOC_2, val) +#define bfin_read_MXVR_ALLOC_3() bfin_read32(MXVR_ALLOC_3) +#define bfin_write_MXVR_ALLOC_3(val) bfin_write32(MXVR_ALLOC_3, val) +#define bfin_read_MXVR_ALLOC_4() bfin_read32(MXVR_ALLOC_4) +#define bfin_write_MXVR_ALLOC_4(val) bfin_write32(MXVR_ALLOC_4, val) +#define bfin_read_MXVR_ALLOC_5() bfin_read32(MXVR_ALLOC_5) +#define bfin_write_MXVR_ALLOC_5(val) bfin_write32(MXVR_ALLOC_5, val) +#define bfin_read_MXVR_ALLOC_6() bfin_read32(MXVR_ALLOC_6) +#define bfin_write_MXVR_ALLOC_6(val) bfin_write32(MXVR_ALLOC_6, val) +#define bfin_read_MXVR_ALLOC_7() bfin_read32(MXVR_ALLOC_7) +#define bfin_write_MXVR_ALLOC_7(val) bfin_write32(MXVR_ALLOC_7, val) +#define bfin_read_MXVR_ALLOC_8() bfin_read32(MXVR_ALLOC_8) +#define bfin_write_MXVR_ALLOC_8(val) bfin_write32(MXVR_ALLOC_8, val) +#define bfin_read_MXVR_ALLOC_9() bfin_read32(MXVR_ALLOC_9) +#define bfin_write_MXVR_ALLOC_9(val) bfin_write32(MXVR_ALLOC_9, val) +#define bfin_read_MXVR_ALLOC_10() bfin_read32(MXVR_ALLOC_10) +#define bfin_write_MXVR_ALLOC_10(val) bfin_write32(MXVR_ALLOC_10, val) +#define bfin_read_MXVR_ALLOC_11() bfin_read32(MXVR_ALLOC_11) +#define bfin_write_MXVR_ALLOC_11(val) bfin_write32(MXVR_ALLOC_11, val) +#define bfin_read_MXVR_ALLOC_12() bfin_read32(MXVR_ALLOC_12) +#define bfin_write_MXVR_ALLOC_12(val) bfin_write32(MXVR_ALLOC_12, val) +#define bfin_read_MXVR_ALLOC_13() bfin_read32(MXVR_ALLOC_13) +#define bfin_write_MXVR_ALLOC_13(val) bfin_write32(MXVR_ALLOC_13, val) +#define bfin_read_MXVR_ALLOC_14() bfin_read32(MXVR_ALLOC_14) +#define bfin_write_MXVR_ALLOC_14(val) bfin_write32(MXVR_ALLOC_14, val) + +/* MXVR Channel Assign Registers */ + +#define bfin_read_MXVR_SYNC_LCHAN_0() bfin_read32(MXVR_SYNC_LCHAN_0) +#define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val) +#define bfin_read_MXVR_SYNC_LCHAN_1() bfin_read32(MXVR_SYNC_LCHAN_1) +#define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val) +#define bfin_read_MXVR_SYNC_LCHAN_2() bfin_read32(MXVR_SYNC_LCHAN_2) +#define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val) +#define bfin_read_MXVR_SYNC_LCHAN_3() bfin_read32(MXVR_SYNC_LCHAN_3) +#define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val) +#define bfin_read_MXVR_SYNC_LCHAN_4() bfin_read32(MXVR_SYNC_LCHAN_4) +#define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val) +#define bfin_read_MXVR_SYNC_LCHAN_5() bfin_read32(MXVR_SYNC_LCHAN_5) +#define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val) +#define bfin_read_MXVR_SYNC_LCHAN_6() bfin_read32(MXVR_SYNC_LCHAN_6) +#define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val) +#define bfin_read_MXVR_SYNC_LCHAN_7() bfin_read32(MXVR_SYNC_LCHAN_7) +#define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val) + +/* MXVR DMA0 Registers */ + +#define bfin_read_MXVR_DMA0_CONFIG() bfin_read32(MXVR_DMA0_CONFIG) +#define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val) +#define bfin_read_MXVR_DMA0_START_ADDR() bfin_read32(MXVR_DMA0_START_ADDR) +#define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_write32(MXVR_DMA0_START_ADDR) +#define bfin_read_MXVR_DMA0_COUNT() bfin_read16(MXVR_DMA0_COUNT) +#define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val) +#define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_read32(MXVR_DMA0_CURR_ADDR) +#define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_write32(MXVR_DMA0_CURR_ADDR) +#define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT) +#define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val) + +/* MXVR DMA1 Registers */ + +#define bfin_read_MXVR_DMA1_CONFIG() bfin_read32(MXVR_DMA1_CONFIG) +#define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val) +#define bfin_read_MXVR_DMA1_START_ADDR() bfin_read32(MXVR_DMA1_START_ADDR) +#define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_write32(MXVR_DMA1_START_ADDR) +#define bfin_read_MXVR_DMA1_COUNT() bfin_read16(MXVR_DMA1_COUNT) +#define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val) +#define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_read32(MXVR_DMA1_CURR_ADDR) +#define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_write32(MXVR_DMA1_CURR_ADDR) +#define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT) +#define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val) + +/* MXVR DMA2 Registers */ + +#define bfin_read_MXVR_DMA2_CONFIG() bfin_read32(MXVR_DMA2_CONFIG) +#define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val) +#define bfin_read_MXVR_DMA2_START_ADDR() bfin_read32(MXVR_DMA2_START_ADDR) +#define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_write32(MXVR_DMA2_START_ADDR) +#define bfin_read_MXVR_DMA2_COUNT() bfin_read16(MXVR_DMA2_COUNT) +#define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val) +#define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_read32(MXVR_DMA2_CURR_ADDR) +#define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_write32(MXVR_DMA2_CURR_ADDR) +#define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT) +#define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val) + +/* MXVR DMA3 Registers */ + +#define bfin_read_MXVR_DMA3_CONFIG() bfin_read32(MXVR_DMA3_CONFIG) +#define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val) +#define bfin_read_MXVR_DMA3_START_ADDR() bfin_read32(MXVR_DMA3_START_ADDR) +#define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_write32(MXVR_DMA3_START_ADDR) +#define bfin_read_MXVR_DMA3_COUNT() bfin_read16(MXVR_DMA3_COUNT) +#define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val) +#define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_read32(MXVR_DMA3_CURR_ADDR) +#define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_write32(MXVR_DMA3_CURR_ADDR) +#define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT) +#define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val) + +/* MXVR DMA4 Registers */ + +#define bfin_read_MXVR_DMA4_CONFIG() bfin_read32(MXVR_DMA4_CONFIG) +#define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val) +#define bfin_read_MXVR_DMA4_START_ADDR() bfin_read32(MXVR_DMA4_START_ADDR) +#define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_write32(MXVR_DMA4_START_ADDR) +#define bfin_read_MXVR_DMA4_COUNT() bfin_read16(MXVR_DMA4_COUNT) +#define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val) +#define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_read32(MXVR_DMA4_CURR_ADDR) +#define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_write32(MXVR_DMA4_CURR_ADDR) +#define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT) +#define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val) + +/* MXVR DMA5 Registers */ + +#define bfin_read_MXVR_DMA5_CONFIG() bfin_read32(MXVR_DMA5_CONFIG) +#define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val) +#define bfin_read_MXVR_DMA5_START_ADDR() bfin_read32(MXVR_DMA5_START_ADDR) +#define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_write32(MXVR_DMA5_START_ADDR) +#define bfin_read_MXVR_DMA5_COUNT() bfin_read16(MXVR_DMA5_COUNT) +#define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val) +#define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_read32(MXVR_DMA5_CURR_ADDR) +#define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_write32(MXVR_DMA5_CURR_ADDR) +#define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT) +#define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val) + +/* MXVR DMA6 Registers */ + +#define bfin_read_MXVR_DMA6_CONFIG() bfin_read32(MXVR_DMA6_CONFIG) +#define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val) +#define bfin_read_MXVR_DMA6_START_ADDR() bfin_read32(MXVR_DMA6_START_ADDR) +#define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_write32(MXVR_DMA6_START_ADDR) +#define bfin_read_MXVR_DMA6_COUNT() bfin_read16(MXVR_DMA6_COUNT) +#define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val) +#define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_read32(MXVR_DMA6_CURR_ADDR) +#define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_write32(MXVR_DMA6_CURR_ADDR) +#define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT) +#define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val) + +/* MXVR DMA7 Registers */ + +#define bfin_read_MXVR_DMA7_CONFIG() bfin_read32(MXVR_DMA7_CONFIG) +#define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val) +#define bfin_read_MXVR_DMA7_START_ADDR() bfin_read32(MXVR_DMA7_START_ADDR) +#define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_write32(MXVR_DMA7_START_ADDR) +#define bfin_read_MXVR_DMA7_COUNT() bfin_read16(MXVR_DMA7_COUNT) +#define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val) +#define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_read32(MXVR_DMA7_CURR_ADDR) +#define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_write32(MXVR_DMA7_CURR_ADDR) +#define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT) +#define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val) + +/* MXVR Asynch Packet Registers */ + +#define bfin_read_MXVR_AP_CTL() bfin_read16(MXVR_AP_CTL) +#define bfin_write_MXVR_AP_CTL(val) bfin_write16(MXVR_AP_CTL, val) +#define bfin_read_MXVR_APRB_START_ADDR() bfin_read32(MXVR_APRB_START_ADDR) +#define bfin_write_MXVR_APRB_START_ADDR(val) bfin_write32(MXVR_APRB_START_ADDR) +#define bfin_read_MXVR_APRB_CURR_ADDR() bfin_read32(MXVR_APRB_CURR_ADDR) +#define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_write32(MXVR_APRB_CURR_ADDR) +#define bfin_read_MXVR_APTB_START_ADDR() bfin_read32(MXVR_APTB_START_ADDR) +#define bfin_write_MXVR_APTB_START_ADDR(val) bfin_write32(MXVR_APTB_START_ADDR) +#define bfin_read_MXVR_APTB_CURR_ADDR() bfin_read32(MXVR_APTB_CURR_ADDR) +#define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_write32(MXVR_APTB_CURR_ADDR) + +/* MXVR Control Message Registers */ + +#define bfin_read_MXVR_CM_CTL() bfin_read32(MXVR_CM_CTL) +#define bfin_write_MXVR_CM_CTL(val) bfin_write32(MXVR_CM_CTL, val) +#define bfin_read_MXVR_CMRB_START_ADDR() bfin_read32(MXVR_CMRB_START_ADDR) +#define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_write32(MXVR_CMRB_START_ADDR) +#define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_read32(MXVR_CMRB_CURR_ADDR) +#define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_write32(MXVR_CMRB_CURR_ADDR) +#define bfin_read_MXVR_CMTB_START_ADDR() bfin_read32(MXVR_CMTB_START_ADDR) +#define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_write32(MXVR_CMTB_START_ADDR) +#define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_read32(MXVR_CMTB_CURR_ADDR) +#define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_write32(MXVR_CMTB_CURR_ADDR) + +/* MXVR Remote Read Registers */ + +#define bfin_read_MXVR_RRDB_START_ADDR() bfin_read32(MXVR_RRDB_START_ADDR) +#define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_write32(MXVR_RRDB_START_ADDR) +#define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_read32(MXVR_RRDB_CURR_ADDR) +#define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_write32(MXVR_RRDB_CURR_ADDR) + +/* MXVR Pattern Data Registers */ + +#define bfin_read_MXVR_PAT_DATA_0() bfin_read32(MXVR_PAT_DATA_0) +#define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val) +#define bfin_read_MXVR_PAT_EN_0() bfin_read32(MXVR_PAT_EN_0) +#define bfin_write_MXVR_PAT_EN_0(val) bfin_write32(MXVR_PAT_EN_0, val) +#define bfin_read_MXVR_PAT_DATA_1() bfin_read32(MXVR_PAT_DATA_1) +#define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val) +#define bfin_read_MXVR_PAT_EN_1() bfin_read32(MXVR_PAT_EN_1) +#define bfin_write_MXVR_PAT_EN_1(val) bfin_write32(MXVR_PAT_EN_1, val) + +/* MXVR Frame Counter Registers */ + +#define bfin_read_MXVR_FRAME_CNT_0() bfin_read16(MXVR_FRAME_CNT_0) +#define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val) +#define bfin_read_MXVR_FRAME_CNT_1() bfin_read16(MXVR_FRAME_CNT_1) +#define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val) + +/* MXVR Routing Table Registers */ + +#define bfin_read_MXVR_ROUTING_0() bfin_read32(MXVR_ROUTING_0) +#define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val) +#define bfin_read_MXVR_ROUTING_1() bfin_read32(MXVR_ROUTING_1) +#define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val) +#define bfin_read_MXVR_ROUTING_2() bfin_read32(MXVR_ROUTING_2) +#define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val) +#define bfin_read_MXVR_ROUTING_3() bfin_read32(MXVR_ROUTING_3) +#define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val) +#define bfin_read_MXVR_ROUTING_4() bfin_read32(MXVR_ROUTING_4) +#define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val) +#define bfin_read_MXVR_ROUTING_5() bfin_read32(MXVR_ROUTING_5) +#define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val) +#define bfin_read_MXVR_ROUTING_6() bfin_read32(MXVR_ROUTING_6) +#define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val) +#define bfin_read_MXVR_ROUTING_7() bfin_read32(MXVR_ROUTING_7) +#define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val) +#define bfin_read_MXVR_ROUTING_8() bfin_read32(MXVR_ROUTING_8) +#define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val) +#define bfin_read_MXVR_ROUTING_9() bfin_read32(MXVR_ROUTING_9) +#define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val) +#define bfin_read_MXVR_ROUTING_10() bfin_read32(MXVR_ROUTING_10) +#define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val) +#define bfin_read_MXVR_ROUTING_11() bfin_read32(MXVR_ROUTING_11) +#define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val) +#define bfin_read_MXVR_ROUTING_12() bfin_read32(MXVR_ROUTING_12) +#define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val) +#define bfin_read_MXVR_ROUTING_13() bfin_read32(MXVR_ROUTING_13) +#define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val) +#define bfin_read_MXVR_ROUTING_14() bfin_read32(MXVR_ROUTING_14) +#define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val) + +/* MXVR Counter-Clock-Control Registers */ + +#define bfin_read_MXVR_BLOCK_CNT() bfin_read16(MXVR_BLOCK_CNT) +#define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val) +#define bfin_read_MXVR_CLK_CTL() bfin_read32(MXVR_CLK_CTL) +#define bfin_write_MXVR_CLK_CTL(val) bfin_write32(MXVR_CLK_CTL, val) +#define bfin_read_MXVR_CDRPLL_CTL() bfin_read32(MXVR_CDRPLL_CTL) +#define bfin_write_MXVR_CDRPLL_CTL(val) bfin_write32(MXVR_CDRPLL_CTL, val) +#define bfin_read_MXVR_FMPLL_CTL() bfin_read32(MXVR_FMPLL_CTL) +#define bfin_write_MXVR_FMPLL_CTL(val) bfin_write32(MXVR_FMPLL_CTL, val) +#define bfin_read_MXVR_PIN_CTL() bfin_read16(MXVR_PIN_CTL) +#define bfin_write_MXVR_PIN_CTL(val) bfin_write16(MXVR_PIN_CTL, val) +#define bfin_read_MXVR_SCLK_CNT() bfin_read16(MXVR_SCLK_CNT) +#define bfin_write_MXVR_SCLK_CNT(val) bfin_write16(MXVR_SCLK_CNT, val) + +/* CAN Controller 1 Config 1 Registers */ + +#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1) +#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val) +#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1) +#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val) +#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1) +#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val) +#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1) +#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val) +#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1) +#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val) +#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1) +#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val) +#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1) +#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val) +#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1) +#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val) +#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1) +#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val) +#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1) +#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val) +#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1) +#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val) +#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1) +#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val) +#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1) +#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val) + +/* CAN Controller 1 Config 2 Registers */ + +#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2) +#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val) +#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2) +#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val) +#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2) +#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val) +#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2) +#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val) +#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2) +#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val) +#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2) +#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val) +#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2) +#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val) +#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2) +#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val) +#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2) +#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val) +#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2) +#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val) +#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2) +#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val) +#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2) +#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val) +#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2) +#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val) + +/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */ + +#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK) +#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val) +#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING) +#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val) +#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG) +#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val) +#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS) +#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val) +#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC) +#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val) +#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS) +#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val) +#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM) +#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val) +#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF) +#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val) +#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL) +#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val) +#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR) +#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val) +#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD) +#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val) +#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR) +#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val) +#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR) +#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val) +#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT) +#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val) +#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC) +#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val) +#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF) +#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val) + +/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */ + +#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L) +#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val) +#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H) +#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val) +#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L) +#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val) +#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H) +#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val) +#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L) +#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val) +#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H) +#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val) +#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L) +#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val) +#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H) +#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val) +#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L) +#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val) +#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H) +#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val) +#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L) +#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val) +#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H) +#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val) +#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L) +#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val) +#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H) +#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val) +#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L) +#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val) +#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H) +#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val) +#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L) +#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val) +#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H) +#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val) +#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L) +#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val) +#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H) +#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val) +#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L) +#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val) +#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H) +#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val) +#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L) +#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val) +#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H) +#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val) +#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L) +#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val) +#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H) +#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val) +#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L) +#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val) +#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H) +#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val) +#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L) +#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val) +#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H) +#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val) +#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L) +#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val) +#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H) +#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val) + +/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */ + +#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L) +#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val) +#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H) +#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val) +#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L) +#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val) +#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H) +#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val) +#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L) +#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val) +#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H) +#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val) +#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L) +#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val) +#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H) +#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val) +#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L) +#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val) +#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H) +#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val) +#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L) +#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val) +#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H) +#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val) +#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L) +#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val) +#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H) +#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val) +#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L) +#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val) +#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H) +#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val) +#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L) +#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val) +#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H) +#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val) +#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L) +#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val) +#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H) +#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val) +#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L) +#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val) +#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H) +#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val) +#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L) +#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val) +#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H) +#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val) +#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L) +#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val) +#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H) +#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val) +#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L) +#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val) +#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H) +#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val) +#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L) +#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val) +#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H) +#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val) +#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L) +#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val) +#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H) +#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val) + +/* CAN Controller 1 Mailbox Data Registers */ + +#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0) +#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val) +#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1) +#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val) +#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2) +#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val) +#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3) +#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val) +#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH) +#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val) +#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP) +#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val) +#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0) +#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val) +#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1) +#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val) +#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0) +#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val) +#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1) +#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val) +#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2) +#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val) +#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3) +#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val) +#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH) +#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val) +#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP) +#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val) +#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0) +#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val) +#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1) +#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val) +#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0) +#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val) +#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1) +#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val) +#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2) +#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val) +#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3) +#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val) +#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH) +#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val) +#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP) +#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val) +#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0) +#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val) +#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1) +#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val) +#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0) +#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val) +#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1) +#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val) +#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2) +#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val) +#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3) +#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val) +#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH) +#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val) +#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP) +#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val) +#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0) +#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val) +#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1) +#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val) +#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0) +#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val) +#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1) +#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val) +#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2) +#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val) +#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3) +#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val) +#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH) +#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val) +#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP) +#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val) +#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0) +#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val) +#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1) +#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val) +#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0) +#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val) +#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1) +#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val) +#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2) +#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val) +#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3) +#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val) +#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH) +#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val) +#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP) +#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val) +#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0) +#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val) +#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1) +#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val) +#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0) +#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val) +#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1) +#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val) +#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2) +#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val) +#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3) +#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val) +#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH) +#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val) +#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP) +#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val) +#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0) +#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val) +#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1) +#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val) +#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0) +#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val) +#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1) +#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val) +#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2) +#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val) +#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3) +#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val) +#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH) +#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val) +#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP) +#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val) +#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0) +#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val) +#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1) +#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val) +#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0) +#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val) +#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1) +#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val) +#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2) +#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val) +#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3) +#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val) +#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH) +#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val) +#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP) +#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val) +#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0) +#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val) +#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1) +#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val) +#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0) +#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val) +#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1) +#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val) +#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2) +#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val) +#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3) +#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val) +#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH) +#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val) +#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP) +#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val) +#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0) +#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val) +#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1) +#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val) +#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0) +#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val) +#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1) +#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val) +#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2) +#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val) +#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3) +#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val) +#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH) +#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val) +#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP) +#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val) +#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0) +#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val) +#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1) +#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val) +#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0) +#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val) +#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1) +#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val) +#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2) +#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val) +#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3) +#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val) +#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH) +#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val) +#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP) +#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val) +#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0) +#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val) +#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1) +#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val) +#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0) +#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val) +#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1) +#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val) +#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2) +#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val) +#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3) +#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val) +#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH) +#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val) +#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP) +#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val) +#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0) +#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val) +#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1) +#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val) +#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0) +#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val) +#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1) +#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val) +#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2) +#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val) +#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3) +#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val) +#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH) +#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val) +#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP) +#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val) +#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0) +#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val) +#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1) +#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val) +#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0) +#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val) +#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1) +#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val) +#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2) +#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val) +#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3) +#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val) +#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH) +#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val) +#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP) +#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val) +#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0) +#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val) +#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1) +#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val) +#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0) +#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val) +#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1) +#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val) +#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2) +#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val) +#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3) +#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val) +#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH) +#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val) +#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP) +#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val) +#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0) +#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val) +#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1) +#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val) + +/* CAN Controller 1 Mailbox Data Registers */ + +#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0) +#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val) +#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1) +#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val) +#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2) +#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val) +#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3) +#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val) +#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH) +#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val) +#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP) +#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val) +#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0) +#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val) +#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1) +#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val) +#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0) +#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val) +#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1) +#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val) +#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2) +#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val) +#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3) +#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val) +#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH) +#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val) +#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP) +#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val) +#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0) +#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val) +#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1) +#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val) +#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0) +#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val) +#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1) +#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val) +#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2) +#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val) +#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3) +#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val) +#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH) +#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val) +#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP) +#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val) +#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0) +#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val) +#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1) +#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val) +#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0) +#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val) +#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1) +#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val) +#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2) +#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val) +#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3) +#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val) +#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH) +#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val) +#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP) +#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val) +#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0) +#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val) +#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1) +#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val) +#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0) +#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val) +#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1) +#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val) +#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2) +#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val) +#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3) +#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val) +#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH) +#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val) +#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP) +#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val) +#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0) +#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val) +#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1) +#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val) +#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0) +#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val) +#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1) +#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val) +#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2) +#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val) +#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3) +#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val) +#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH) +#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val) +#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP) +#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val) +#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0) +#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val) +#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1) +#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val) +#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0) +#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val) +#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1) +#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val) +#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2) +#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val) +#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3) +#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val) +#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH) +#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val) +#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP) +#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val) +#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0) +#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val) +#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1) +#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val) +#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0) +#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val) +#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1) +#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val) +#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2) +#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val) +#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3) +#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val) +#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH) +#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val) +#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP) +#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val) +#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0) +#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val) +#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1) +#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val) +#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0) +#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val) +#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1) +#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val) +#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2) +#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val) +#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3) +#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val) +#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH) +#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val) +#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP) +#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val) +#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0) +#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val) +#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1) +#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val) +#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0) +#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val) +#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1) +#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val) +#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2) +#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val) +#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3) +#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val) +#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH) +#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val) +#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP) +#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val) +#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0) +#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val) +#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1) +#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val) +#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0) +#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val) +#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1) +#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val) +#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2) +#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val) +#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3) +#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val) +#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH) +#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val) +#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP) +#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val) +#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0) +#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val) +#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1) +#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val) +#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0) +#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val) +#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1) +#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val) +#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2) +#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val) +#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3) +#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val) +#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH) +#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val) +#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP) +#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val) +#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0) +#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val) +#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1) +#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val) +#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0) +#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val) +#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1) +#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val) +#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2) +#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val) +#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3) +#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val) +#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH) +#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val) +#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP) +#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val) +#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0) +#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val) +#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1) +#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val) +#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0) +#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val) +#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1) +#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val) +#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2) +#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val) +#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3) +#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val) +#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH) +#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val) +#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP) +#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val) +#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0) +#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val) +#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1) +#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val) +#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0) +#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val) +#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1) +#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val) +#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2) +#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val) +#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3) +#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val) +#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH) +#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val) +#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP) +#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val) +#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0) +#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val) +#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1) +#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val) +#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0) +#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val) +#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1) +#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val) +#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2) +#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val) +#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3) +#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val) +#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH) +#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val) +#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP) +#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val) +#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0) +#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val) +#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1) +#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val) + +/* ATAPI Registers */ + +#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL) +#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val) +#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS) +#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val) +#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR) +#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val) +#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF) +#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val) +#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF) +#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val) +#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK) +#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val) +#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS) +#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val) +#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN) +#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val) +#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS) +#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val) +#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE) +#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val) +#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE) +#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val) +#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT) +#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val) +#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT) +#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val) +#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT) +#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val) +#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT) +#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val) +#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0) +#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val) +#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0) +#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val) +#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1) +#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val) +#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0) +#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val) +#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1) +#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val) +#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2) +#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val) +#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0) +#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val) +#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1) +#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val) +#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2) +#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val) +#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3) +#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val) + +/* SDH Registers */ + +#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL) +#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val) +#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL) +#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val) +#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT) +#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val) +#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND) +#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val) +#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD) +#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val) +#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0) +#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val) +#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1) +#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val) +#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2) +#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val) +#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3) +#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val) +#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER) +#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val) +#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH) +#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val) +#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL) +#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val) +#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT) +#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val) +#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS) +#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val) +#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR) +#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val) +#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0) +#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val) +#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1) +#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val) +#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT) +#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val) +#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO) +#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val) +#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS) +#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val) +#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK) +#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val) +#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG) +#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val) +#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN) +#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val) +#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0) +#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val) +#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1) +#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val) +#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2) +#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val) +#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3) +#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val) +#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4) +#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val) +#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5) +#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val) +#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6) +#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val) +#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7) +#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val) + +/* HOST Port Registers */ + +#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) +#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) +#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) +#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) +#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) +#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) + +/* USB Control Registers */ + +#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) +#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) +#define bfin_read_USB_POWER() bfin_read16(USB_POWER) +#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) +#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) +#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) +#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) +#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) +#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) +#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) +#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) +#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) +#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) +#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) +#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) +#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) +#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) +#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) +#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) +#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) +#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) +#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) +#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) +#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) +#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) +#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) + +/* USB Packet Control Registers */ + +#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) +#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) +#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) +#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) +#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) +#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) +#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) +#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) +#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) +#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) +#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) +#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) +#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) +#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) +#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) +#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) +#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) +#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) +#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) +#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) +#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) +#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) +#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) +#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) +#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) +#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) + +/* USB Endbfin_read_()oint FIFO Registers */ + +#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) +#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) +#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) +#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) +#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) +#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) +#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) +#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) +#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) +#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) +#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) +#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) +#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) +#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) +#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) +#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) + +/* USB OTG Control Registers */ + +#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) +#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) +#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) +#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) +#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) +#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) + +/* USB Phy Control Registers */ + +#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) +#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) +#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) +#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) +#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) +#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) +#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) +#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) +#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) +#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) + +/* (APHY_CNTRL is for ADI usage only) */ + +#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) +#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) + +/* (APHY_CALIB is for ADI usage only) */ + +#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) +#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) +#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) +#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) + +/* (PHY_TEST is for ADI usage only) */ + +#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) +#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) +#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) +#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) +#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) +#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) + +/* USB Endbfin_read_()oint 0 Control Registers */ + +#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) +#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) +#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) +#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) +#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) +#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) +#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) +#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) +#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) +#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) +#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) +#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) +#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) +#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) +#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) +#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) +#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) +#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 1 Control Registers */ + +#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) +#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) +#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) +#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) +#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) +#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) +#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) +#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) +#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) +#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) +#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) +#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) +#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) +#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) +#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) +#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) +#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) +#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) +#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) +#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 2 Control Registers */ + +#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) +#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) +#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) +#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) +#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) +#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) +#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) +#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) +#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) +#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) +#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) +#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) +#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) +#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) +#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) +#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) +#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) +#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) +#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) +#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 3 Control Registers */ + +#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) +#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) +#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) +#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) +#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) +#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) +#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) +#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) +#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) +#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) +#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) +#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) +#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) +#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) +#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) +#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) +#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) +#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) +#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) +#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 4 Control Registers */ + +#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) +#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) +#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) +#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) +#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) +#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) +#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) +#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) +#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) +#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) +#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) +#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) +#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) +#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) +#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) +#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) +#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) +#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) +#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) +#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 5 Control Registers */ + +#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) +#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) +#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) +#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) +#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) +#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) +#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) +#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) +#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) +#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) +#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) +#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) +#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) +#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) +#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) +#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) +#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) +#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) +#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) +#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 6 Control Registers */ + +#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) +#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) +#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) +#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) +#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) +#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) +#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) +#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) +#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) +#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) +#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) +#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) +#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) +#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) +#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) +#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) +#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) +#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) +#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) +#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 7 Control Registers */ + +#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) +#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) +#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) +#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) +#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) +#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) +#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) +#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) +#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) +#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) +#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) +#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) +#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) +#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) +#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) +#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) +#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) +#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) +#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) +#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) +#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) +#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) +#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) +#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) + +/* USB Channel 0 Config Registers */ + +#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL) +#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val) +#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW) +#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val) +#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH) +#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val) +#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW) +#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val) +#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH) +#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val) + +/* USB Channel 1 Config Registers */ + +#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL) +#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val) +#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW) +#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val) +#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH) +#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val) +#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW) +#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val) +#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH) +#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val) + +/* USB Channel 2 Config Registers */ + +#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL) +#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val) +#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW) +#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val) +#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH) +#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val) +#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW) +#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val) +#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH) +#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val) + +/* USB Channel 3 Config Registers */ + +#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL) +#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val) +#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW) +#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val) +#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH) +#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val) +#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW) +#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val) +#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH) +#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val) + +/* USB Channel 4 Config Registers */ + +#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL) +#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val) +#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW) +#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val) +#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH) +#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val) +#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW) +#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val) +#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH) +#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val) + +/* USB Channel 5 Config Registers */ + +#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL) +#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val) +#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW) +#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val) +#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH) +#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val) +#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW) +#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val) +#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH) +#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val) + +/* USB Channel 6 Config Registers */ + +#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL) +#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val) +#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW) +#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val) +#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH) +#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val) +#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW) +#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val) +#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH) +#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val) + +/* USB Channel 7 Config Registers */ + +#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL) +#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val) +#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW) +#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val) +#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH) +#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val) +#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW) +#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val) +#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH) +#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val) + +/* Keybfin_read_()ad Registers */ + +#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL) +#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val) +#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE) +#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val) +#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL) +#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val) +#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL) +#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val) +#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT) +#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val) +#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL) +#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val) + +/* Pixel Combfin_read_()ositor (PIXC) Registers */ + +#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL) +#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val) +#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL) +#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val) +#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF) +#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val) +#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART) +#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val) +#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND) +#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val) +#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART) +#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val) +#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND) +#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val) +#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP) +#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val) +#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART) +#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val) +#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND) +#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val) +#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART) +#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val) +#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND) +#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val) +#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP) +#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val) +#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT) +#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val) +#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON) +#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val) +#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON) +#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val) +#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON) +#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val) +#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS) +#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val) +#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC) +#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val) + +/* Handshake MDMA 0 Registers */ + +#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) +#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) +#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) +#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) +#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) +#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) +#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) +#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) +#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) +#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) +#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) +#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) +#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) +#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) + +/* Handshake MDMA 1 Registers */ + +#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) +#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) +#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) +#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) +#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) +#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) +#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) +#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) +#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) +#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) +#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) +#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) +#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) +#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) + +#endif /* _CDEF_BF549_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h new file mode 100644 index 000000000000..57ac8cb9b1f6 --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h @@ -0,0 +1,2750 @@ +/* + * File: include/asm-blackfin/mach-bf548/cdefBF54x_base.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _CDEF_BF54X_H +#define _CDEF_BF54X_H + +#include <asm/blackfin.h> + +#include "defBF54x_base.h" +#include <asm/system.h> + +/* ************************************************************** */ +/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ +/* ************************************************************** */ + +/* PLL Registers */ + +#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) +/* Writing to PLL_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_PLL_CTL(unsigned int val) +{ + unsigned long flags, iwr0, iwr1, iwr2; + + if (val == bfin_read_PLL_CTL()) + return; + + local_irq_save(flags); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr0 = bfin_read32(SIC_IWR0); + iwr1 = bfin_read32(SIC_IWR1); + iwr2 = bfin_read32(SIC_IWR2); + /* Only allow PPL Wakeup) */ + bfin_write32(SIC_IWR0, IWR_ENABLE(0)); + bfin_write32(SIC_IWR1, 0); + bfin_write32(SIC_IWR2, 0); + + bfin_write16(PLL_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SIC_IWR0, iwr0); + bfin_write32(SIC_IWR1, iwr1); + bfin_write32(SIC_IWR2, iwr2); + local_irq_restore(flags); +} +#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) +#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) +#define bfin_read_VR_CTL() bfin_read16(VR_CTL) +/* Writing to VR_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_VR_CTL(unsigned int val) +{ + unsigned long flags, iwr0, iwr1, iwr2; + + if (val == bfin_read_VR_CTL()) + return; + + local_irq_save(flags); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr0 = bfin_read32(SIC_IWR0); + iwr1 = bfin_read32(SIC_IWR1); + iwr2 = bfin_read32(SIC_IWR2); + /* Only allow PPL Wakeup) */ + bfin_write32(SIC_IWR0, IWR_ENABLE(0)); + bfin_write32(SIC_IWR1, 0); + bfin_write32(SIC_IWR2, 0); + + bfin_write16(VR_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SIC_IWR0, iwr0); + bfin_write32(SIC_IWR1, iwr1); + bfin_write32(SIC_IWR2, iwr2); + local_irq_restore(flags); +} +#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) +#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) +#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) +#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) + +/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */ + +#define bfin_read_CHIPID() bfin_read32(CHIPID) +#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) + +/* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */ + +#define bfin_read_SWRST() bfin_read16(SWRST) +#define bfin_write_SWRST(val) bfin_write16(SWRST, val) +#define bfin_read_SYSCR() bfin_read16(SYSCR) +#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) + +/* SIC Registers */ + +#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) +#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) +#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) +#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) +#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2) +#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) +#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 2)) +#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val) + +#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) +#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) +#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) +#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) +#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2) +#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) +#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 2)) +#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val) + +#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) +#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) +#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) +#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) +#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2) +#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val) +#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) +#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) +#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) +#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) +#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) +#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) +#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) +#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) +#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) +#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) +#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) +#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) +#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) +#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) +#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) +#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) +#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8) +#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val) +#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9) +#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val) +#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10) +#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val) +#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11) +#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val) + +/* Watchdog Timer Registers */ + +#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) +#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) +#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) +#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) +#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) +#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) + +/* RTC Registers */ + +#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) +#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) +#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) +#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) +#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) +#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) +#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) +#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) +#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) +#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) +#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) +#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) + +/* UART0 Registers */ + +#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) +#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) +#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) +#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) +#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) +#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) +#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) +#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) +#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) +#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) +#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) +#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) +#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) +#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) +#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) +#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) +#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET) +#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val) +#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR) +#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val) +#define bfin_read_UART0_THR() bfin_read16(UART0_THR) +#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) +#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) +#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) + +/* SPI0 Registers */ + +#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL) +#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val) +#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG) +#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val) +#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT) +#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val) +#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR) +#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val) +#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR) +#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val) +#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD) +#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val) +#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW) +#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val) + +/* Timer Groubfin_read_() of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */ + +/* Two Wire Interface Registers (TWI0) */ + +/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */ + +/* SPORT1 Registers */ + +#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) +#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) +#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) +#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) +#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) +#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) +#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) +#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) +#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) +#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) +#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) +#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) +#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) +#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) +#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) +#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) +#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) +#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) +#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) +#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) +#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) +#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) +#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) +#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) +#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) +#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) +#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) +#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) +#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) +#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) +#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) +#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) +#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) +#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) +#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) +#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) +#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) +#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) +#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) +#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) +#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) +#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) +#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) +#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) + +/* Asynchronous Memory Control Registers */ + +#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) +#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) +#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) +#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) +#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) +#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) +#define bfin_read_EBIU_MBSCTL() bfin_read16(EBIU_MBSCTL) +#define bfin_write_EBIU_MBSCTL(val) bfin_write16(EBIU_MBSCTL, val) +#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT) +#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val) +#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE) +#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val) +#define bfin_read_EBIU_FCTL() bfin_read16(EBIU_FCTL) +#define bfin_write_EBIU_FCTL(val) bfin_write16(EBIU_FCTL, val) + +/* DDR Memory Control Registers */ + +#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0) +#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val) +#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1) +#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val) +#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2) +#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val) +#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3) +#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val) +#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE) +#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val) +#define bfin_read_EBIU_ERRADD() bfin_read32(EBIU_ERRADD) +#define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD, val) +#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST) +#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val) +#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL) +#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val) + +/* DDR BankRead and Write Count Registers */ + +#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) +#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val) +#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1) +#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val) +#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2) +#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val) +#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3) +#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val) +#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4) +#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val) +#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5) +#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val) +#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6) +#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val) +#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7) +#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val) +#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0) +#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val) +#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1) +#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val) +#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2) +#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val) +#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3) +#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val) +#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4) +#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val) +#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5) +#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val) +#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6) +#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val) +#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7) +#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val) +#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT) +#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val) +#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT) +#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val) +#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT) +#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val) +#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0) +#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val) +#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1) +#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val) +#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2) +#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val) +#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3) +#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val) +#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN) +#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val) +#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL) +#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val) + +/* DMAC0 Registers */ + +#define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER) +#define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val) +#define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT) +#define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val) + +/* DMA Channel 0 Registers */ + +#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) +#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) +#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) +#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) +#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) +#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) +#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) +#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) +#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) +#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) +#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) +#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) +#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) +#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) +#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) +#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) +#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) +#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) +#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) +#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) +#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) +#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) +#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) +#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) +#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) +#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) + +/* DMA Channel 1 Registers */ + +#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) +#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) +#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) +#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) +#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) +#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) +#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) +#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) +#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) +#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) +#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) +#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) +#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) +#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) +#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) +#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) +#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) +#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) +#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) +#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) +#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) +#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) +#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) +#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) +#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) +#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) + +/* DMA Channel 2 Registers */ + +#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) +#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) +#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) +#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) +#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) +#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) +#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) +#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) +#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) +#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) +#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) +#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) +#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) +#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) +#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) +#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) +#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) +#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) +#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) +#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) +#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) +#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) +#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) +#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) +#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) +#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) + +/* DMA Channel 3 Registers */ + +#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) +#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) +#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) +#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) +#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) +#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) +#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) +#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) +#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) +#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) +#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) +#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) +#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) +#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) +#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) +#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) +#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) +#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) +#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) +#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) +#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) +#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) +#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) +#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) +#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) +#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) + +/* DMA Channel 4 Registers */ + +#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) +#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) +#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) +#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) +#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) +#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) +#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) +#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) +#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) +#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) +#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) +#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) +#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) +#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) +#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) +#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) +#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) +#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) +#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) +#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) +#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) +#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) +#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) +#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) +#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) +#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) + +/* DMA Channel 5 Registers */ + +#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) +#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) +#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) +#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) +#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) +#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) +#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) +#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) +#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) +#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) +#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) +#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) +#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) +#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) +#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) +#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) +#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) +#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) +#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) +#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) +#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) +#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) +#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) +#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) +#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) +#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) + +/* DMA Channel 6 Registers */ + +#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) +#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) +#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) +#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) +#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) +#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) +#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) +#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) +#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) +#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) +#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) +#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) +#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) +#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) +#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) +#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) +#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) +#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) +#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) +#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) +#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) +#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) +#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) +#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) +#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) +#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) + +/* DMA Channel 7 Registers */ + +#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) +#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) +#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) +#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) +#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) +#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) +#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) +#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) +#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) +#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) +#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) +#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) +#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) +#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) +#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) +#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) +#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) +#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) +#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) +#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) +#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) +#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) +#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) +#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) +#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) +#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) + +/* DMA Channel 8 Registers */ + +#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) +#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val) +#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) +#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val) +#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) +#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) +#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) +#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) +#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) +#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) +#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) +#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) +#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) +#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) +#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) +#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val) +#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) +#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val) +#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) +#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) +#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) +#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) +#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) +#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) +#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) +#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) + +/* DMA Channel 9 Registers */ + +#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) +#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val) +#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) +#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val) +#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) +#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) +#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) +#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) +#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) +#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) +#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) +#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) +#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) +#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) +#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) +#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val) +#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) +#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val) +#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) +#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) +#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) +#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) +#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) +#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) +#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) +#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) + +/* DMA Channel 10 Registers */ + +#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) +#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val) +#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) +#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val) +#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) +#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) +#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) +#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) +#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) +#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) +#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) +#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) +#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) +#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) +#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) +#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val) +#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) +#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val) +#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) +#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) +#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) +#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) +#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) +#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) +#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) +#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) + +/* DMA Channel 11 Registers */ + +#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) +#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val) +#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) +#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val) +#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) +#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) +#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) +#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) +#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) +#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) +#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) +#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) +#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) +#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) +#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) +#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val) +#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) +#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val) +#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) +#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) +#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) +#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) +#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) +#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) +#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) +#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) + +/* MDMA Stream 0 Registers */ + +#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) +#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) +#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) +#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) +#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) +#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) +#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) +#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) +#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) +#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) +#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) +#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) +#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) +#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) +#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val) +#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) +#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val) +#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) +#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) +#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) +#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) +#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) +#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) +#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) +#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) +#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) +#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val) +#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) +#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) +#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) +#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) +#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) +#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) +#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) +#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) +#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) +#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) +#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) +#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val) +#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) +#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val) +#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) +#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) +#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) +#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) +#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) +#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) +#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) + +/* MDMA Stream 1 Registers */ + +#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) +#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) +#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val) +#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) +#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) +#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) +#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) +#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) +#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) +#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) +#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) +#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) +#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) +#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) +#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) +#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) +#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val) +#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) +#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) +#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) +#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) +#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) +#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) +#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) +#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) +#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) +#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val) +#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) +#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) +#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) +#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) +#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) +#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) +#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) +#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) +#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) +#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) +#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) +#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) +#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) +#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val) +#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) +#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) +#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) +#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) +#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) +#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) +#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) + +/* EPPI1 Registers */ + +#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS) +#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val) +#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT) +#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val) +#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY) +#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val) +#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT) +#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val) +#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY) +#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val) +#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME) +#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val) +#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE) +#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val) +#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV) +#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val) +#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL) +#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val) +#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL) +#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val) +#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL) +#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val) +#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB) +#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val) +#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF) +#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val) +#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP) +#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val) + +/* Port Interrubfin_read_()t 0 Registers (32-bit) */ + +#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET) +#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val) +#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR) +#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val) +#define bfin_read_PINT0_REQUEST() bfin_read32(PINT0_REQUEST) +#define bfin_write_PINT0_REQUEST(val) bfin_write32(PINT0_REQUEST, val) +#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN) +#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val) +#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET) +#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val) +#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR) +#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val) +#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET) +#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val) +#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR) +#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val) +#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE) +#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val) +#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH) +#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val) + +/* Port Interrubfin_read_()t 1 Registers (32-bit) */ + +#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET) +#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val) +#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR) +#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val) +#define bfin_read_PINT1_REQUEST() bfin_read32(PINT1_REQUEST) +#define bfin_write_PINT1_REQUEST(val) bfin_write32(PINT1_REQUEST, val) +#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN) +#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val) +#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET) +#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val) +#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR) +#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val) +#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET) +#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val) +#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR) +#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val) +#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE) +#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val) +#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH) +#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val) + +/* Port Interrubfin_read_()t 2 Registers (32-bit) */ + +#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET) +#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val) +#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR) +#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val) +#define bfin_read_PINT2_REQUEST() bfin_read32(PINT2_REQUEST) +#define bfin_write_PINT2_REQUEST(val) bfin_write32(PINT2_REQUEST, val) +#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN) +#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val) +#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET) +#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val) +#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR) +#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val) +#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET) +#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val) +#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR) +#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val) +#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE) +#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val) +#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH) +#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val) + +/* Port Interrubfin_read_()t 3 Registers (32-bit) */ + +#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET) +#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val) +#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR) +#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val) +#define bfin_read_PINT3_REQUEST() bfin_read32(PINT3_REQUEST) +#define bfin_write_PINT3_REQUEST(val) bfin_write32(PINT3_REQUEST, val) +#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN) +#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val) +#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET) +#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val) +#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR) +#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val) +#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET) +#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val) +#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR) +#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val) +#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE) +#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val) +#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH) +#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val) + +/* Port A Registers */ + +#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER) +#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val) +#define bfin_read_PORTA() bfin_read16(PORTA) +#define bfin_write_PORTA(val) bfin_write16(PORTA, val) +#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET) +#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val) +#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR) +#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val) +#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET) +#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val) +#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR) +#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val) +#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN) +#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val) +#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX) +#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val) + +/* Port B Registers */ + +#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER) +#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val) +#define bfin_read_PORTB() bfin_read16(PORTB) +#define bfin_write_PORTB(val) bfin_write16(PORTB, val) +#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET) +#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val) +#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR) +#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val) +#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET) +#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val) +#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR) +#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val) +#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN) +#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val) +#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX) +#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val) + +/* Port C Registers */ + +#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER) +#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val) +#define bfin_read_PORTC() bfin_read16(PORTC) +#define bfin_write_PORTC(val) bfin_write16(PORTC, val) +#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET) +#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val) +#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR) +#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val) +#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET) +#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val) +#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR) +#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val) +#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN) +#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val) +#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX) +#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val) + +/* Port D Registers */ + +#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER) +#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val) +#define bfin_read_PORTD() bfin_read16(PORTD) +#define bfin_write_PORTD(val) bfin_write16(PORTD, val) +#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET) +#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val) +#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR) +#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val) +#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET) +#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val) +#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR) +#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val) +#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN) +#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val) +#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX) +#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val) + +/* Port E Registers */ + +#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER) +#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val) +#define bfin_read_PORTE() bfin_read16(PORTE) +#define bfin_write_PORTE(val) bfin_write16(PORTE, val) +#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET) +#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val) +#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR) +#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val) +#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET) +#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val) +#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR) +#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val) +#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN) +#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val) +#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX) +#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val) + +/* Port F Registers */ + +#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) +#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) +#define bfin_read_PORTF() bfin_read16(PORTF) +#define bfin_write_PORTF(val) bfin_write16(PORTF, val) +#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET) +#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val) +#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR) +#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val) +#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET) +#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val) +#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR) +#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val) +#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN) +#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val) +#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX) +#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val) + +/* Port G Registers */ + +#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) +#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) +#define bfin_read_PORTG() bfin_read16(PORTG) +#define bfin_write_PORTG(val) bfin_write16(PORTG, val) +#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET) +#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val) +#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR) +#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val) +#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET) +#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val) +#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR) +#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val) +#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN) +#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val) +#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX) +#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val) + +/* Port H Registers */ + +#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) +#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) +#define bfin_read_PORTH() bfin_read16(PORTH) +#define bfin_write_PORTH(val) bfin_write16(PORTH, val) +#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET) +#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val) +#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR) +#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val) +#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET) +#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val) +#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR) +#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val) +#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN) +#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val) +#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX) +#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val) + +/* Port I Registers */ + +#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER) +#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val) +#define bfin_read_PORTI() bfin_read16(PORTI) +#define bfin_write_PORTI(val) bfin_write16(PORTI, val) +#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET) +#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val) +#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR) +#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val) +#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET) +#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val) +#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR) +#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val) +#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN) +#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val) +#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX) +#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val) + +/* Port J Registers */ + +#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER) +#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val) +#define bfin_read_PORTJ() bfin_read16(PORTJ) +#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val) +#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET) +#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val) +#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR) +#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val) +#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET) +#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val) +#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR) +#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val) +#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN) +#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val) +#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX) +#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val) + +/* PWM Timer Registers */ + +#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) +#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) +#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) +#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) +#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) +#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) +#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) +#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) +#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) +#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) +#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) +#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) +#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) +#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) +#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) +#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) +#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) +#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) +#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) +#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) +#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) +#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) +#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) +#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) +#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) +#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) +#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) +#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) +#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) +#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) +#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) +#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) +#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) +#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) +#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) +#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) +#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) +#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) +#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) +#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) +#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) +#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) +#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) +#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) +#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) +#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) +#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) +#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) +#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) +#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) +#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) +#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) +#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) +#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) +#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) +#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) +#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) +#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) +#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) +#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) +#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) +#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) +#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) +#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) + +/* Timer Groubfin_read_() of 8 */ + +#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0) +#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val) +#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0) +#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val) +#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0) +#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val) + +/* DMAC1 Registers */ + +#define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER) +#define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val) +#define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT) +#define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val) + +/* DMA Channel 12 Registers */ + +#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR) +#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val) +#define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR) +#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val) +#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG) +#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val) +#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT) +#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val) +#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY) +#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val) +#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT) +#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val) +#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY) +#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val) +#define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR) +#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val) +#define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR) +#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val) +#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS) +#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val) +#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP) +#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val) +#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT) +#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val) +#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT) +#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val) + +/* DMA Channel 13 Registers */ + +#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR) +#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val) +#define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR) +#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val) +#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG) +#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val) +#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT) +#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val) +#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY) +#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val) +#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT) +#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val) +#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY) +#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val) +#define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR) +#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val) +#define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR) +#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val) +#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS) +#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val) +#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP) +#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val) +#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT) +#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val) +#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT) +#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val) + +/* DMA Channel 14 Registers */ + +#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR) +#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val) +#define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR) +#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val) +#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG) +#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val) +#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT) +#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val) +#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY) +#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val) +#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT) +#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val) +#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY) +#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val) +#define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR) +#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val) +#define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR) +#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val) +#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS) +#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val) +#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP) +#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val) +#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT) +#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val) +#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT) +#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val) + +/* DMA Channel 15 Registers */ + +#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR) +#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val) +#define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR) +#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val) +#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG) +#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val) +#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT) +#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val) +#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY) +#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val) +#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT) +#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val) +#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY) +#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val) +#define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR) +#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val) +#define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR) +#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val) +#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS) +#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val) +#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP) +#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val) +#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT) +#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val) +#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT) +#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val) + +/* DMA Channel 16 Registers */ + +#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR) +#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val) +#define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR) +#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val) +#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG) +#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val) +#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT) +#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val) +#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY) +#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val) +#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT) +#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val) +#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY) +#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val) +#define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR) +#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val) +#define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR) +#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val) +#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS) +#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val) +#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP) +#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val) +#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT) +#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val) +#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT) +#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val) + +/* DMA Channel 17 Registers */ + +#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR) +#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val) +#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR) +#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val) +#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG) +#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val) +#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT) +#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val) +#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY) +#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val) +#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT) +#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val) +#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY) +#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val) +#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR) +#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val) +#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR) +#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val) +#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS) +#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val) +#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP) +#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val) +#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT) +#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val) +#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT) +#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val) + +/* DMA Channel 18 Registers */ + +#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR) +#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val) +#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR) +#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val) +#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG) +#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val) +#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT) +#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val) +#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY) +#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val) +#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT) +#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val) +#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY) +#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val) +#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR) +#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val) +#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR) +#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val) +#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS) +#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val) +#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP) +#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val) +#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT) +#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val) +#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT) +#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val) + +/* DMA Channel 19 Registers */ + +#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR) +#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val) +#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR) +#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val) +#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG) +#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val) +#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT) +#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val) +#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY) +#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val) +#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT) +#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val) +#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY) +#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val) +#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR) +#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val) +#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR) +#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val) +#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS) +#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val) +#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP) +#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val) +#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT) +#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val) +#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT) +#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val) + +/* DMA Channel 20 Registers */ + +#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR) +#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val) +#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR) +#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val) +#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG) +#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val) +#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT) +#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val) +#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY) +#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val) +#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT) +#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val) +#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY) +#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val) +#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR) +#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val) +#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR) +#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val) +#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS) +#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val) +#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP) +#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val) +#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT) +#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val) +#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT) +#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val) + +/* DMA Channel 21 Registers */ + +#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_read32(DMA21_NEXT_DESC_PTR) +#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR, val) +#define bfin_read_DMA21_START_ADDR() bfin_read32(DMA21_START_ADDR) +#define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR, val) +#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG) +#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val) +#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT) +#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val) +#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY) +#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val) +#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT) +#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val) +#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY) +#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val) +#define bfin_read_DMA21_CURR_DESC_PTR() bfin_read32(DMA21_CURR_DESC_PTR) +#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR, val) +#define bfin_read_DMA21_CURR_ADDR() bfin_read32(DMA21_CURR_ADDR) +#define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR, val) +#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS) +#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val) +#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP) +#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val) +#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT) +#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val) +#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT) +#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val) + +/* DMA Channel 22 Registers */ + +#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_read32(DMA22_NEXT_DESC_PTR) +#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR, val) +#define bfin_read_DMA22_START_ADDR() bfin_read32(DMA22_START_ADDR) +#define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR, val) +#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG) +#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val) +#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT) +#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val) +#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY) +#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val) +#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT) +#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val) +#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY) +#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val) +#define bfin_read_DMA22_CURR_DESC_PTR() bfin_read32(DMA22_CURR_DESC_PTR) +#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR, val) +#define bfin_read_DMA22_CURR_ADDR() bfin_read32(DMA22_CURR_ADDR) +#define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR, val) +#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS) +#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val) +#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP) +#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val) +#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT) +#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val) +#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT) +#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val) + +/* DMA Channel 23 Registers */ + +#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_read32(DMA23_NEXT_DESC_PTR) +#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR, val) +#define bfin_read_DMA23_START_ADDR() bfin_read32(DMA23_START_ADDR) +#define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR, val) +#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG) +#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val) +#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT) +#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val) +#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY) +#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val) +#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT) +#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val) +#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY) +#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val) +#define bfin_read_DMA23_CURR_DESC_PTR() bfin_read32(DMA23_CURR_DESC_PTR) +#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR, val) +#define bfin_read_DMA23_CURR_ADDR() bfin_read32(DMA23_CURR_ADDR) +#define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR, val) +#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS) +#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val) +#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP) +#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val) +#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT) +#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val) +#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT) +#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val) + +/* MDMA Stream 2 Registers */ + +#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR) +#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR) +#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR, val) +#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG) +#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val) +#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT) +#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val) +#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY) +#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val) +#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT) +#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val) +#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY) +#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val) +#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR) +#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR, val) +#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR) +#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR, val) +#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS) +#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val) +#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP) +#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT) +#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val) +#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT) +#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val) +#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR) +#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR) +#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR, val) +#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG) +#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val) +#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT) +#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val) +#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY) +#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val) +#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT) +#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val) +#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY) +#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val) +#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR) +#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR, val) +#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR) +#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR, val) +#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS) +#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val) +#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP) +#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT) +#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val) +#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT) +#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val) + +/* MDMA Stream 3 Registers */ + +#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR) +#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR) +#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR, val) +#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG) +#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val) +#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT) +#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val) +#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY) +#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val) +#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT) +#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val) +#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY) +#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val) +#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR) +#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR, val) +#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR) +#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR, val) +#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS) +#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val) +#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP) +#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT) +#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val) +#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT) +#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val) +#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR) +#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR) +#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR, val) +#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG) +#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val) +#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT) +#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val) +#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY) +#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val) +#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT) +#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val) +#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY) +#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val) +#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR) +#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR, val) +#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR) +#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR, val) +#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS) +#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val) +#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP) +#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT) +#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val) +#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT) +#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val) + +/* UART1 Registers */ + +#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) +#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) +#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) +#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) +#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) +#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) +#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) +#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) +#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) +#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) +#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) +#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) +#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) +#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) +#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) +#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) +#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET) +#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val) +#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR) +#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val) +#define bfin_read_UART1_THR() bfin_read16(UART1_THR) +#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) +#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) +#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) + +/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */ + +/* SPI1 Registers */ + +#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL) +#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val) +#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG) +#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val) +#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT) +#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val) +#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR) +#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val) +#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR) +#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val) +#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD) +#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val) +#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW) +#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val) + +/* SPORT2 Registers */ + +#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1) +#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val) +#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2) +#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val) +#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV) +#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val) +#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) +#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) +#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX) +#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) +#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX) +#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val) +#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) +#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val) +#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2) +#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val) +#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV) +#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val) +#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV) +#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val) +#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT) +#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val) +#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL) +#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val) +#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1) +#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val) +#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2) +#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val) +#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0) +#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val) +#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1) +#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val) +#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2) +#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val) +#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3) +#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val) +#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0) +#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val) +#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1) +#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val) +#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2) +#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val) +#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3) +#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val) + +/* SPORT3 Registers */ + +#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1) +#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val) +#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2) +#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val) +#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV) +#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val) +#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) +#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) +#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX) +#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) +#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX) +#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val) +#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) +#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val) +#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2) +#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val) +#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV) +#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val) +#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV) +#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val) +#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT) +#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val) +#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL) +#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val) +#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1) +#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val) +#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2) +#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val) +#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0) +#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val) +#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1) +#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val) +#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2) +#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val) +#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3) +#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val) +#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0) +#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val) +#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1) +#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val) +#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2) +#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val) +#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3) +#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val) + +/* EPPI2 Registers */ + +#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS) +#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val) +#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT) +#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val) +#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY) +#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val) +#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT) +#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val) +#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY) +#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val) +#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME) +#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val) +#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE) +#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val) +#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV) +#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val) +#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL) +#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val) +#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL) +#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val) +#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL) +#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val) +#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB) +#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val) +#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF) +#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val) +#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP) +#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val) + +/* CAN Controller 0 Config 1 Registers */ + +#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1) +#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val) +#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1) +#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val) +#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1) +#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val) +#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1) +#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val) +#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1) +#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val) +#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1) +#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val) +#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1) +#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val) +#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1) +#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val) +#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1) +#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val) +#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1) +#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val) +#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1) +#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val) +#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1) +#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val) +#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1) +#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val) + +/* CAN Controller 0 Config 2 Registers */ + +#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2) +#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val) +#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2) +#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val) +#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2) +#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val) +#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2) +#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val) +#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2) +#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val) +#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2) +#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val) +#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2) +#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val) +#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2) +#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val) +#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2) +#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val) +#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2) +#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val) +#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2) +#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val) +#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2) +#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val) +#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2) +#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val) + +/* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */ + +#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK) +#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val) +#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING) +#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val) +#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG) +#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val) +#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS) +#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val) +#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC) +#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val) +#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS) +#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val) +#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM) +#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val) +#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF) +#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val) +#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL) +#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val) +#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR) +#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val) +#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD) +#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val) +#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR) +#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val) +#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR) +#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val) +#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT) +#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val) +#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC) +#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val) +#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF) +#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val) + +/* CAN Controller 0 Accebfin_read_()tance Registers */ + +#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L) +#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val) +#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H) +#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val) +#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L) +#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val) +#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H) +#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val) +#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L) +#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val) +#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H) +#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val) +#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L) +#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val) +#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H) +#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val) +#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L) +#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val) +#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H) +#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val) +#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L) +#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val) +#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H) +#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val) +#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L) +#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val) +#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H) +#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val) +#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L) +#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val) +#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H) +#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val) +#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L) +#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val) +#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H) +#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val) +#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L) +#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val) +#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H) +#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val) +#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L) +#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val) +#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H) +#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val) +#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L) +#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val) +#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H) +#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val) +#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L) +#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val) +#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H) +#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val) +#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L) +#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val) +#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H) +#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val) +#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L) +#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val) +#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H) +#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val) +#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L) +#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val) +#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H) +#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val) + +/* CAN Controller 0 Accebfin_read_()tance Registers */ + +#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L) +#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val) +#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H) +#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val) +#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L) +#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val) +#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H) +#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val) +#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L) +#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val) +#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H) +#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val) +#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L) +#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val) +#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H) +#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val) +#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L) +#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val) +#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H) +#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val) +#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L) +#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val) +#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H) +#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val) +#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L) +#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val) +#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H) +#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val) +#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L) +#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val) +#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H) +#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val) +#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L) +#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val) +#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H) +#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val) +#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L) +#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val) +#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H) +#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val) +#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L) +#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val) +#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H) +#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val) +#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L) +#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val) +#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H) +#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val) +#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L) +#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val) +#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H) +#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val) +#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L) +#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val) +#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H) +#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val) +#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L) +#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val) +#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H) +#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val) +#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L) +#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val) +#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H) +#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val) + +/* CAN Controller 0 Mailbox Data Registers */ + +#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0) +#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val) +#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1) +#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val) +#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2) +#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val) +#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3) +#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val) +#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH) +#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val) +#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP) +#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val) +#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0) +#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val) +#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1) +#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val) +#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0) +#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val) +#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1) +#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val) +#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2) +#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val) +#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3) +#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val) +#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH) +#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val) +#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP) +#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val) +#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0) +#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val) +#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1) +#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val) +#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0) +#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val) +#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1) +#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val) +#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2) +#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val) +#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3) +#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val) +#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH) +#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val) +#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP) +#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val) +#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0) +#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val) +#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1) +#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val) +#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0) +#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val) +#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1) +#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val) +#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2) +#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val) +#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3) +#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val) +#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH) +#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val) +#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP) +#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val) +#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0) +#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val) +#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1) +#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val) +#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0) +#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val) +#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1) +#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val) +#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2) +#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val) +#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3) +#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val) +#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH) +#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val) +#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP) +#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val) +#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0) +#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val) +#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1) +#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val) +#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0) +#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val) +#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1) +#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val) +#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2) +#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val) +#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3) +#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val) +#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH) +#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val) +#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP) +#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val) +#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0) +#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val) +#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1) +#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val) +#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0) +#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val) +#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1) +#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val) +#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2) +#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val) +#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3) +#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val) +#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH) +#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val) +#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP) +#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val) +#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0) +#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val) +#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1) +#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val) +#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0) +#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val) +#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1) +#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val) +#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2) +#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val) +#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3) +#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val) +#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH) +#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val) +#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP) +#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val) +#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0) +#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val) +#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1) +#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val) +#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0) +#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val) +#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1) +#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val) +#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2) +#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val) +#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3) +#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val) +#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH) +#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val) +#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP) +#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val) +#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0) +#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val) +#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1) +#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val) +#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0) +#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val) +#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1) +#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val) +#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2) +#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val) +#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3) +#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val) +#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH) +#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val) +#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP) +#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val) +#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0) +#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val) +#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1) +#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val) +#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0) +#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val) +#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1) +#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val) +#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2) +#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val) +#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3) +#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val) +#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH) +#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val) +#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP) +#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val) +#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0) +#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val) +#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1) +#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val) +#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0) +#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val) +#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1) +#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val) +#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2) +#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val) +#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3) +#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val) +#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH) +#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val) +#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP) +#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val) +#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0) +#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val) +#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1) +#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val) +#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0) +#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val) +#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1) +#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val) +#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2) +#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val) +#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3) +#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val) +#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH) +#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val) +#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP) +#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val) +#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0) +#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val) +#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1) +#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val) +#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0) +#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val) +#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1) +#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val) +#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2) +#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val) +#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3) +#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val) +#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH) +#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val) +#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP) +#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val) +#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0) +#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val) +#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1) +#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val) +#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0) +#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val) +#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1) +#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val) +#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2) +#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val) +#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3) +#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val) +#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH) +#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val) +#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP) +#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val) +#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0) +#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val) +#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1) +#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val) +#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0) +#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val) +#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1) +#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val) +#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2) +#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val) +#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3) +#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val) +#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH) +#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val) +#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP) +#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val) +#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0) +#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val) +#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1) +#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val) + +/* CAN Controller 0 Mailbox Data Registers */ + +#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0) +#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val) +#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1) +#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val) +#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2) +#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val) +#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3) +#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val) +#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH) +#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val) +#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP) +#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val) +#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0) +#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val) +#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1) +#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val) +#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0) +#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val) +#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1) +#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val) +#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2) +#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val) +#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3) +#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val) +#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH) +#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val) +#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP) +#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val) +#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0) +#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val) +#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1) +#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val) +#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0) +#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val) +#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1) +#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val) +#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2) +#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val) +#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3) +#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val) +#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH) +#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val) +#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP) +#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val) +#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0) +#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val) +#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1) +#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val) +#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0) +#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val) +#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1) +#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val) +#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2) +#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val) +#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3) +#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val) +#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH) +#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val) +#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP) +#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val) +#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0) +#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val) +#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1) +#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val) +#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0) +#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val) +#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1) +#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val) +#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2) +#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val) +#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3) +#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val) +#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH) +#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val) +#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP) +#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val) +#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0) +#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val) +#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1) +#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val) +#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0) +#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val) +#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1) +#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val) +#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2) +#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val) +#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3) +#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val) +#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH) +#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val) +#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP) +#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val) +#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0) +#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val) +#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1) +#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val) +#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0) +#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val) +#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1) +#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val) +#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2) +#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val) +#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3) +#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val) +#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH) +#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val) +#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP) +#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val) +#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0) +#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val) +#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1) +#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val) +#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0) +#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val) +#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1) +#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val) +#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2) +#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val) +#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3) +#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val) +#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH) +#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val) +#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP) +#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val) +#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0) +#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val) +#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1) +#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val) +#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0) +#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val) +#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1) +#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val) +#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2) +#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val) +#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3) +#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val) +#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH) +#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val) +#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP) +#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val) +#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0) +#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val) +#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1) +#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val) +#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0) +#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val) +#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1) +#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val) +#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2) +#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val) +#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3) +#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val) +#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH) +#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val) +#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP) +#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val) +#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0) +#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val) +#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1) +#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val) +#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0) +#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val) +#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1) +#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val) +#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2) +#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val) +#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3) +#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val) +#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH) +#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val) +#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP) +#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val) +#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0) +#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val) +#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1) +#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val) +#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0) +#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val) +#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1) +#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val) +#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2) +#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val) +#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3) +#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val) +#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH) +#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val) +#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP) +#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val) +#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0) +#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val) +#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1) +#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val) +#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0) +#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val) +#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1) +#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val) +#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2) +#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val) +#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3) +#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val) +#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH) +#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val) +#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP) +#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val) +#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0) +#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val) +#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1) +#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val) +#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0) +#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val) +#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1) +#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val) +#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2) +#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val) +#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3) +#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val) +#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH) +#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val) +#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP) +#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val) +#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0) +#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val) +#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1) +#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val) +#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0) +#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val) +#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1) +#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val) +#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2) +#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val) +#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3) +#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val) +#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH) +#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val) +#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP) +#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val) +#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0) +#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val) +#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1) +#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val) +#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0) +#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val) +#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1) +#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val) +#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2) +#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val) +#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3) +#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val) +#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH) +#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val) +#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP) +#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val) +#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0) +#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val) +#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1) +#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val) + +/* UART3 Registers */ + +#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL) +#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val) +#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH) +#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val) +#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL) +#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val) +#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR) +#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val) +#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR) +#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val) +#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR) +#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val) +#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR) +#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val) +#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR) +#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val) +#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET) +#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val) +#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR) +#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val) +#define bfin_read_UART3_THR() bfin_read16(UART3_THR) +#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val) +#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR) +#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val) + +/* NFC Registers */ + +#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) +#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) +#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) +#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) +#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) +#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) +#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) +#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) +#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) +#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) +#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) +#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) +#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) +#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) +#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) +#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) +#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) +#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) +#define bfin_read_NFC_RST() bfin_read16(NFC_RST) +#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) +#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) +#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) +#define bfin_read_NFC_READ() bfin_read16(NFC_READ) +#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) +#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) +#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) +#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) +#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) +#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) +#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) +#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) +#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) + +/* Counter Registers */ + +#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) +#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) +#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) +#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) +#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) +#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) +#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) +#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) +#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) +#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) +#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) +#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) +#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) +#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) +#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) +#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) + +/* OTP/FUSE Registers */ + +#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) +#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) +#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) +#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) +#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) +#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) +#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) +#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) + +/* Security Registers */ + +#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) +#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) +#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) +#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) +#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) +#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) + +/* DMA Peribfin_read_()heral Mux Register */ + +#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX) +#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val) + +/* OTP Read/Write Data Buffer Registers */ + +#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) +#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) +#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) +#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) +#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) +#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) +#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) +#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) + +/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */ + +/* legacy definitions */ +#define bfin_read_EBIU_AMCBCTL0 bfin_read_EBIU_AMBCTL0 +#define bfin_write_EBIU_AMCBCTL0 bfin_write_EBIU_AMBCTL0 +#define bfin_read_EBIU_AMCBCTL1 bfin_read_EBIU_AMBCTL1 +#define bfin_write_EBIU_AMCBCTL1 bfin_write_EBIU_AMBCTL1 +#define bfin_read_PINT0_IRQ bfin_read_PINT0_REQUEST +#define bfin_write_PINT0_IRQ bfin_write_PINT0_REQUEST +#define bfin_read_PINT1_IRQ bfin_read_PINT1_REQUEST +#define bfin_write_PINT1_IRQ bfin_write_PINT1_REQUEST +#define bfin_read_PINT2_IRQ bfin_read_PINT2_REQUEST +#define bfin_write_PINT2_IRQ bfin_write_PINT2_REQUEST +#define bfin_read_PINT3_IRQ bfin_read_PINT3_REQUEST +#define bfin_write_PINT3_IRQ bfin_write_PINT3_REQUEST + +#endif /* _CDEF_BF54X_H */ + diff --git a/arch/blackfin/mach-bf548/include/mach/defBF542.h b/arch/blackfin/mach-bf548/include/mach/defBF542.h new file mode 100644 index 000000000000..b1316541b8d6 --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/defBF542.h @@ -0,0 +1,925 @@ +/* + * File: include/asm-blackfin/mach-bf548/defBF542.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _DEF_BF542_H +#define _DEF_BF542_H + +/* Include all Core registers and bit definitions */ +#include <asm/def_LPBlackfin.h> + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */ + +/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ +#include "defBF54x_base.h" + +/* The following are the #defines needed by ADSP-BF542 that are not in the common header */ + +/* ATAPI Registers */ + +#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */ +#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */ +#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */ +#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */ +#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */ +#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */ +#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */ +#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */ +#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */ +#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */ +#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */ +#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */ +#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */ +#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */ +#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */ +#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */ +#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */ +#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */ +#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */ +#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */ +#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */ +#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */ +#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */ +#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */ +#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */ + +/* SDH Registers */ + +#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */ +#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */ +#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */ +#define SDH_COMMAND 0xffc0390c /* SDH Command */ +#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */ +#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */ +#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */ +#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */ +#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */ +#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */ +#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */ +#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */ +#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */ +#define SDH_STATUS 0xffc03934 /* SDH Status */ +#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */ +#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */ +#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */ +#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */ +#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */ +#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */ +#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */ +#define SDH_CFG 0xffc039c8 /* SDH Configuration */ +#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */ +#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */ +#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */ +#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */ +#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */ +#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */ +#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */ +#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */ +#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */ + +/* USB Control Registers */ + +#define USB_FADDR 0xffc03c00 /* Function address register */ +#define USB_POWER 0xffc03c04 /* Power management register */ +#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ +#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */ +#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */ +#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */ +#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */ +#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */ +#define USB_FRAME 0xffc03c20 /* USB frame number */ +#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */ +#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */ +#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ +#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */ + +/* USB Packet Control Registers */ + +#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */ +#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ +#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ +#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */ +#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */ +#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ +#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ +#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ +#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ +#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ +#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ +#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ +#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */ + +/* USB Endpoint FIFO Registers */ + +#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */ +#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */ +#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */ +#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */ +#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */ +#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */ +#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */ +#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */ + +/* USB OTG Control Registers */ + +#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */ +#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */ +#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */ + +/* USB Phy Control Registers */ + +#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */ +#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */ +#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */ +#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */ +#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */ + +/* (APHY_CNTRL is for ADI usage only) */ + +#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */ + +/* (APHY_CALIB is for ADI usage only) */ + +#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */ +#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ + +/* (PHY_TEST is for ADI usage only) */ + +#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */ +#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */ +#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ + +/* USB Endpoint 0 Control Registers */ + +#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */ +#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */ +#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */ +#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */ +#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */ +#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ +#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */ +#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ +#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ + +/* USB Endpoint 1 Control Registers */ + +#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ +#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */ +#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */ +#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */ +#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */ +#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */ +#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ +#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */ +#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ +#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ + +/* USB Endpoint 2 Control Registers */ + +#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ +#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */ +#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */ +#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */ +#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */ +#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */ +#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ +#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */ +#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ +#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ + +/* USB Endpoint 3 Control Registers */ + +#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ +#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */ +#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */ +#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */ +#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */ +#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */ +#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ +#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */ +#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ +#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ + +/* USB Endpoint 4 Control Registers */ + +#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ +#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */ +#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */ +#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */ +#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */ +#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */ +#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ +#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */ +#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ +#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ + +/* USB Endpoint 5 Control Registers */ + +#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ +#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */ +#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */ +#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */ +#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */ +#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */ +#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ +#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */ +#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ +#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ + +/* USB Endpoint 6 Control Registers */ + +#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */ +#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */ +#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */ +#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */ +#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */ +#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */ +#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ +#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */ +#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ +#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ + +/* USB Endpoint 7 Control Registers */ + +#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ +#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */ +#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */ +#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */ +#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */ +#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */ +#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ +#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */ +#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ +#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ +#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ +#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */ + +/* USB Channel 0 Config Registers */ + +#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */ +#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ +#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ +#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ +#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ + +/* USB Channel 1 Config Registers */ + +#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */ +#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ +#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ +#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ +#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ + +/* USB Channel 2 Config Registers */ + +#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */ +#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ +#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ +#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ +#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ + +/* USB Channel 3 Config Registers */ + +#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */ +#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ +#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ +#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ +#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ + +/* USB Channel 4 Config Registers */ + +#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */ +#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ +#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ +#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ +#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ + +/* USB Channel 5 Config Registers */ + +#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */ +#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ +#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ +#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ +#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ + +/* USB Channel 6 Config Registers */ + +#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */ +#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ +#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ +#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ +#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ + +/* USB Channel 7 Config Registers */ + +#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */ +#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ +#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ +#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ +#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ + +/* Keypad Registers */ + +#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */ +#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */ +#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */ +#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */ +#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */ +#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */ + + +/* ********************************************************** */ +/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ +/* and MULTI BIT READ MACROS */ +/* ********************************************************** */ + +/* Bit masks for KPAD_CTL */ + +#define KPAD_EN 0x1 /* Keypad Enable */ +#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ +#define KPAD_ROWEN 0x1c00 /* Row Enable Width */ +#define KPAD_COLEN 0xe000 /* Column Enable Width */ + +/* Bit masks for KPAD_PRESCALE */ + +#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */ + +/* Bit masks for KPAD_MSEL */ + +#define DBON_SCALE 0xff /* Debounce Scale Value */ +#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */ + +/* Bit masks for KPAD_ROWCOL */ + +#define KPAD_ROW 0xff /* Rows Pressed */ +#define KPAD_COL 0xff00 /* Columns Pressed */ + +/* Bit masks for KPAD_STAT */ + +#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ +#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ +#define KPAD_PRESSED 0x8 /* Key press current status */ + +/* Bit masks for KPAD_SOFTEVAL */ + +#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ + +/* Bit masks for SDH_COMMAND */ + +#define CMD_IDX 0x3f /* Command Index */ +#define CMD_RSP 0x40 /* Response */ +#define CMD_L_RSP 0x80 /* Long Response */ +#define CMD_INT_E 0x100 /* Command Interrupt */ +#define CMD_PEND_E 0x200 /* Command Pending */ +#define CMD_E 0x400 /* Command Enable */ + +/* Bit masks for SDH_PWR_CTL */ + +#define PWR_ON 0x3 /* Power On */ +#if 0 +#define TBD 0x3c /* TBD */ +#endif +#define SD_CMD_OD 0x40 /* Open Drain Output */ +#define ROD_CTL 0x80 /* Rod Control */ + +/* Bit masks for SDH_CLK_CTL */ + +#define CLKDIV 0xff /* MC_CLK Divisor */ +#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ +#define PWR_SV_E 0x200 /* Power Save Enable */ +#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ +#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ + +/* Bit masks for SDH_RESP_CMD */ + +#define RESP_CMD 0x3f /* Response Command */ + +/* Bit masks for SDH_DATA_CTL */ + +#define DTX_E 0x1 /* Data Transfer Enable */ +#define DTX_DIR 0x2 /* Data Transfer Direction */ +#define DTX_MODE 0x4 /* Data Transfer Mode */ +#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ +#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ + +/* Bit masks for SDH_STATUS */ + +#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ +#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ +#define CMD_TIME_OUT 0x4 /* CMD Time Out */ +#define DAT_TIME_OUT 0x8 /* Data Time Out */ +#define TX_UNDERRUN 0x10 /* Transmit Underrun */ +#define RX_OVERRUN 0x20 /* Receive Overrun */ +#define CMD_RESP_END 0x40 /* CMD Response End */ +#define CMD_SENT 0x80 /* CMD Sent */ +#define DAT_END 0x100 /* Data End */ +#define START_BIT_ERR 0x200 /* Start Bit Error */ +#define DAT_BLK_END 0x400 /* Data Block End */ +#define CMD_ACT 0x800 /* CMD Active */ +#define TX_ACT 0x1000 /* Transmit Active */ +#define RX_ACT 0x2000 /* Receive Active */ +#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ +#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ +#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ +#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ +#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ +#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ +#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ +#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ + +/* Bit masks for SDH_STATUS_CLR */ + +#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ +#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ +#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ +#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ +#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ +#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ +#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ +#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ +#define DAT_END_STAT 0x100 /* Data End Status */ +#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ +#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ + +/* Bit masks for SDH_MASK0 */ + +#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ +#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ +#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ +#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ +#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ +#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ +#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ +#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ +#define DAT_END_MASK 0x100 /* Data End Mask */ +#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ +#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ +#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ +#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ +#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ +#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ +#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ +#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ +#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ +#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ +#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ +#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ +#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ + +/* Bit masks for SDH_FIFO_CNT */ + +#define FIFO_COUNT 0x7fff /* FIFO Count */ + +/* Bit masks for SDH_E_STATUS */ + +#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ +#define SD_CARD_DET 0x10 /* SD Card Detect */ + +/* Bit masks for SDH_E_MASK */ + +#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ +#define SCD_MSK 0x40 /* Mask Card Detect */ + +/* Bit masks for SDH_CFG */ + +#define CLKS_EN 0x1 /* Clocks Enable */ +#define SD4E 0x4 /* SDIO 4-Bit Enable */ +#define MWE 0x8 /* Moving Window Enable */ +#define SD_RST 0x10 /* SDMMC Reset */ +#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ +#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ +#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ + +/* Bit masks for SDH_RD_WAIT_EN */ + +#define RWR 0x1 /* Read Wait Request */ + +/* Bit masks for ATAPI_CONTROL */ + +#define PIO_START 0x1 /* Start PIO/Reg Op */ +#define MULTI_START 0x2 /* Start Multi-DMA Op */ +#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ +#define XFER_DIR 0x8 /* Transfer Direction */ +#define IORDY_EN 0x10 /* IORDY Enable */ +#define FIFO_FLUSH 0x20 /* Flush FIFOs */ +#define SOFT_RST 0x40 /* Soft Reset */ +#define DEV_RST 0x80 /* Device Reset */ +#define TFRCNT_RST 0x100 /* Trans Count Reset */ +#define END_ON_TERM 0x200 /* End/Terminate Select */ +#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ +#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ + +/* Bit masks for ATAPI_STATUS */ + +#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ +#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ +#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ +#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ + +/* Bit masks for ATAPI_DEV_ADDR */ + +#define DEV_ADDR 0x1f /* Device Address */ + +/* Bit masks for ATAPI_INT_MASK */ + +#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ +#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ +#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ +#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ +#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ +#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ +#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ +#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ +#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ + +/* Bit masks for ATAPI_INT_STATUS */ + +#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ +#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ +#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ +#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ +#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ +#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ +#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ +#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ +#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ + +/* Bit masks for ATAPI_LINE_STATUS */ + +#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ +#define ATAPI_DASP 0x2 /* Device dasp to host line status */ +#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ +#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ +#define ATAPI_ADDR 0x70 /* ATAPI address line status */ +#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ +#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ +#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ +#define ATAPI_DIORN 0x400 /* ATAPI read line status */ +#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_SM_STATE */ + +#define PIO_CSTATE 0xf /* PIO mode state machine current state */ +#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */ +#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */ +#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_TERMINATE */ + +#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ + +/* Bit masks for ATAPI_REG_TIM_0 */ + +#define T2_REG 0xff /* End of cycle time for register access transfers */ +#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */ + +/* Bit masks for ATAPI_PIO_TIM_0 */ + +#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */ +#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */ +#define T4_REG 0xf000 /* DIOW data hold */ + +/* Bit masks for ATAPI_PIO_TIM_1 */ + +#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */ + +/* Bit masks for ATAPI_MULTI_TIM_0 */ + +#define TD 0xff /* DIOR/DIOW asserted pulsewidth */ +#define TM 0xff00 /* Time from address valid to DIOR/DIOW */ + +/* Bit masks for ATAPI_MULTI_TIM_1 */ + +#define TKW 0xff /* Selects DIOW negated pulsewidth */ +#define TKR 0xff00 /* Selects DIOR negated pulsewidth */ + +/* Bit masks for ATAPI_MULTI_TIM_2 */ + +#define TH 0xff /* Selects DIOW data hold */ +#define TEOC 0xff00 /* Selects end of cycle for DMA */ + +/* Bit masks for ATAPI_ULTRA_TIM_0 */ + +#define TACK 0xff /* Selects setup and hold times for TACK */ +#define TENV 0xff00 /* Selects envelope time */ + +/* Bit masks for ATAPI_ULTRA_TIM_1 */ + +#define TDVS 0xff /* Selects data valid setup time */ +#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */ + +/* Bit masks for ATAPI_ULTRA_TIM_2 */ + +#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */ +#define TMLI 0xff00 /* Selects interlock time */ + +/* Bit masks for ATAPI_ULTRA_TIM_3 */ + +#define TZAH 0xff /* Selects minimum delay required for output */ +#define READY_PAUSE 0xff00 /* Selects ready to pause */ + +/* Bit masks for USB_FADDR */ + +#define FUNCTION_ADDRESS 0x7f /* Function address */ + +/* Bit masks for USB_POWER */ + +#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ +#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ +#define RESUME_MODE 0x4 /* DMA Mode */ +#define RESET 0x8 /* Reset indicator */ +#define HS_MODE 0x10 /* High Speed mode indicator */ +#define HS_ENABLE 0x20 /* high Speed Enable */ +#define SOFT_CONN 0x40 /* Soft connect */ +#define ISO_UPDATE 0x80 /* Isochronous update */ + +/* Bit masks for USB_INTRTX */ + +#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ +#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ +#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ +#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ +#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ +#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ +#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ +#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ + +/* Bit masks for USB_INTRRX */ + +#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ +#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ +#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ +#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ +#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ +#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ +#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ + +/* Bit masks for USB_INTRTXE */ + +#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ +#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ +#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ +#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ +#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ +#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ +#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ +#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ + +/* Bit masks for USB_INTRRXE */ + +#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ +#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ +#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ +#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ +#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ +#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ +#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ + +/* Bit masks for USB_INTRUSB */ + +#define SUSPEND_B 0x1 /* Suspend indicator */ +#define RESUME_B 0x2 /* Resume indicator */ +#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ +#define SOF_B 0x8 /* Start of frame */ +#define CONN_B 0x10 /* Connection indicator */ +#define DISCON_B 0x20 /* Disconnect indicator */ +#define SESSION_REQ_B 0x40 /* Session Request */ +#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ + +/* Bit masks for USB_INTRUSBE */ + +#define SUSPEND_BE 0x1 /* Suspend indicator int enable */ +#define RESUME_BE 0x2 /* Resume indicator int enable */ +#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ +#define SOF_BE 0x8 /* Start of frame int enable */ +#define CONN_BE 0x10 /* Connection indicator int enable */ +#define DISCON_BE 0x20 /* Disconnect indicator int enable */ +#define SESSION_REQ_BE 0x40 /* Session Request int enable */ +#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ + +/* Bit masks for USB_FRAME */ + +#define FRAME_NUMBER 0x7ff /* Frame number */ + +/* Bit masks for USB_INDEX */ + +#define SELECTED_ENDPOINT 0xf /* selected endpoint */ + +/* Bit masks for USB_GLOBAL_CTL */ + +#define GLOBAL_ENA 0x1 /* enables USB module */ +#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ +#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ +#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ +#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ +#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ +#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ +#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ +#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ +#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ +#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ +#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ +#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ +#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ +#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ + +/* Bit masks for USB_OTG_DEV_CTL */ + +#define SESSION 0x1 /* session indicator */ +#define HOST_REQ 0x2 /* Host negotiation request */ +#define HOST_MODE 0x4 /* indicates USBDRC is a host */ +#define VBUS0 0x8 /* Vbus level indicator[0] */ +#define VBUS1 0x10 /* Vbus level indicator[1] */ +#define LSDEV 0x20 /* Low-speed indicator */ +#define FSDEV 0x40 /* Full or High-speed indicator */ +#define B_DEVICE 0x80 /* A' or 'B' device indicator */ + +/* Bit masks for USB_OTG_VBUS_IRQ */ + +#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ +#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ +#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ +#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ +#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ +#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ + +/* Bit masks for USB_OTG_VBUS_MASK */ + +#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ +#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ +#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ +#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ +#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ +#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ + +/* Bit masks for USB_CSR0 */ + +#define RXPKTRDY 0x1 /* data packet receive indicator */ +#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ +#define STALL_SENT 0x4 /* STALL handshake sent */ +#define DATAEND 0x8 /* Data end indicator */ +#define SETUPEND 0x10 /* Setup end */ +#define SENDSTALL 0x20 /* Send STALL handshake */ +#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ +#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ +#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ +#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ +#define SETUPPKT_H 0x8 /* send Setup token host mode */ +#define ERROR_H 0x10 /* timeout error indicator host mode */ +#define REQPKT_H 0x20 /* Request an IN transaction host mode */ +#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ +#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ + +/* Bit masks for USB_COUNT0 */ + +#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ + +/* Bit masks for USB_NAKLIMIT0 */ + +#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ + +/* Bit masks for USB_TX_MAX_PACKET */ + +#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ + +/* Bit masks for USB_RX_MAX_PACKET */ + +#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ + +/* Bit masks for USB_TXCSR */ + +#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ +#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ +#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ +#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ +#define STALL_SEND_T 0x10 /* issue a Stall handshake */ +#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ +#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ +#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ +#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ +#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ +#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ +#define ISO_T 0x4000 /* enable Isochronous transfers */ +#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ +#define ERROR_TH 0x4 /* error condition host mode */ +#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ +#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ + +/* Bit masks for USB_TXCOUNT */ + +#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ + +/* Bit masks for USB_RXCSR */ + +#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ +#define FIFO_FULL_R 0x2 /* FIFO not empty */ +#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ +#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ +#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ +#define STALL_SEND_R 0x20 /* issue a Stall handshake */ +#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ +#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ +#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ +#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ +#define DISNYET_R 0x1000 /* disable Nyet handshakes */ +#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ +#define ISO_R 0x4000 /* enable Isochronous transfers */ +#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ +#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ +#define REQPKT_RH 0x20 /* request an IN transaction host mode */ +#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ +#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ +#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ +#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ + +/* Bit masks for USB_RXCOUNT */ + +#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ + +/* Bit masks for USB_TXTYPE */ + +#define TARGET_EP_NO_T 0xf /* EP number */ +#define PROTOCOL_T 0xc /* transfer type */ + +/* Bit masks for USB_TXINTERVAL */ + +#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ + +/* Bit masks for USB_RXTYPE */ + +#define TARGET_EP_NO_R 0xf /* EP number */ +#define PROTOCOL_R 0xc /* transfer type */ + +/* Bit masks for USB_RXINTERVAL */ + +#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ + +/* Bit masks for USB_DMA_INTERRUPT */ + +#define DMA0_INT 0x1 /* DMA0 pending interrupt */ +#define DMA1_INT 0x2 /* DMA1 pending interrupt */ +#define DMA2_INT 0x4 /* DMA2 pending interrupt */ +#define DMA3_INT 0x8 /* DMA3 pending interrupt */ +#define DMA4_INT 0x10 /* DMA4 pending interrupt */ +#define DMA5_INT 0x20 /* DMA5 pending interrupt */ +#define DMA6_INT 0x40 /* DMA6 pending interrupt */ +#define DMA7_INT 0x80 /* DMA7 pending interrupt */ + +/* Bit masks for USB_DMAxCONTROL */ + +#define DMA_ENA 0x1 /* DMA enable */ +#define DIRECTION 0x2 /* direction of DMA transfer */ +#define MODE 0x4 /* DMA Bus error */ +#define INT_ENA 0x8 /* Interrupt enable */ +#define EPNUM 0xf0 /* EP number */ +#define BUSERROR 0x100 /* DMA Bus error */ + +/* Bit masks for USB_DMAxADDRHIGH */ + +#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ + +/* Bit masks for USB_DMAxADDRLOW */ + +#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ + +/* Bit masks for USB_DMAxCOUNTHIGH */ + +#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ + +/* Bit masks for USB_DMAxCOUNTLOW */ + +#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ + + +/* ******************************************* */ +/* MULTI BIT MACRO ENUMERATIONS */ +/* ******************************************* */ + + +#endif /* _DEF_BF542_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h new file mode 100644 index 000000000000..c2c785bdc5fc --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h @@ -0,0 +1,707 @@ +/* + * File: include/asm-blackfin/mach-bf548/defBF544.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _DEF_BF544_H +#define _DEF_BF544_H + +/* Include all Core registers and bit definitions */ +#include <asm/def_LPBlackfin.h> + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */ + +/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ +#include "defBF54x_base.h" + +/* The following are the #defines needed by ADSP-BF544 that are not in the common header */ + +/* Timer Registers */ + +#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */ +#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */ +#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */ +#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */ +#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */ +#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */ +#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */ +#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */ +#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */ +#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */ +#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */ +#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */ + +/* Timer Group of 3 Registers */ + +#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */ +#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */ +#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */ + +/* EPPI0 Registers */ + +#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */ +#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */ +#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */ +#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */ +#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */ +#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */ +#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */ +#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */ +#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */ +#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ +#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ +#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ +#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ +#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */ + +/* Two Wire Interface Registers (TWI1) */ + +#define TWI1_REGBASE 0xffc02200 +#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ +#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ +#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ +#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ +#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ +#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */ +#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ +#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ +#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ +#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ +#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */ +#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ +#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ +#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ +#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */ +#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */ + +/* CAN Controller 1 Config 1 Registers */ + +#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */ +#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */ +#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */ +#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */ +#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */ +#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */ +#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */ +#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */ +#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */ +#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */ +#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */ +#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */ +#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */ + +/* CAN Controller 1 Config 2 Registers */ + +#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */ +#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */ +#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */ +#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */ +#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */ +#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */ +#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */ +#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */ +#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */ +#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */ +#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */ +#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */ +#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */ + +/* CAN Controller 1 Clock/Interrupt/Counter Registers */ + +#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */ +#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */ +#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */ +#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */ +#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */ +#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */ +#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */ +#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */ +#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */ +#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */ +#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */ +#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */ +#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */ +#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */ +#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */ +#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */ + +/* CAN Controller 1 Mailbox Acceptance Registers */ + +#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */ +#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */ +#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */ +#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */ +#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */ +#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */ +#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */ +#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */ +#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */ +#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */ +#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */ +#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */ +#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */ +#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */ +#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */ +#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */ +#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */ +#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */ +#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */ +#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */ +#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */ +#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */ +#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */ +#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */ +#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */ +#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */ +#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */ +#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */ +#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */ +#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */ +#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */ +#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */ + +/* CAN Controller 1 Mailbox Acceptance Registers */ + +#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */ +#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */ +#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */ +#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */ +#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */ +#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */ +#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */ +#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */ +#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */ +#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */ +#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */ +#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */ +#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */ +#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */ +#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */ +#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */ +#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */ +#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */ +#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */ +#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */ +#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */ +#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */ +#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */ +#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */ +#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */ +#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */ +#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */ +#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */ +#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */ +#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */ +#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */ +#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */ + +/* CAN Controller 1 Mailbox Data Registers */ + +#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */ +#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */ +#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */ +#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */ +#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */ +#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */ +#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */ +#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */ +#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */ +#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */ +#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */ +#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */ +#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */ +#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */ +#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */ +#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */ +#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */ +#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */ +#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */ +#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */ +#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */ +#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */ +#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */ +#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */ +#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */ +#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */ +#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */ +#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */ +#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */ +#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */ +#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */ +#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */ +#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */ +#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */ +#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */ +#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */ +#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */ +#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */ +#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */ +#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */ +#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */ +#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */ +#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */ +#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */ +#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */ +#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */ +#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */ +#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */ +#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */ +#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */ +#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */ +#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */ +#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */ +#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */ +#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */ +#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */ +#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */ +#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */ +#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */ +#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */ +#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */ +#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */ +#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */ +#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */ +#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */ +#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */ +#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */ +#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */ +#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */ +#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */ +#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */ +#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */ +#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */ +#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */ +#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */ +#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */ +#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */ +#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */ +#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */ +#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */ +#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */ +#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */ +#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */ +#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */ +#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */ +#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */ +#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */ +#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */ +#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */ +#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */ +#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */ +#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */ +#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */ +#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */ +#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */ +#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */ +#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */ +#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */ +#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */ +#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */ +#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */ +#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */ +#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */ +#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */ +#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */ +#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */ +#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */ +#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */ +#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */ +#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */ +#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */ +#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */ +#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */ +#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */ +#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */ +#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */ +#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */ +#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */ +#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */ +#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */ +#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */ +#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */ +#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */ +#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */ +#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */ +#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */ +#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */ +#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */ + +/* CAN Controller 1 Mailbox Data Registers */ + +#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */ +#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */ +#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */ +#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */ +#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */ +#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */ +#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */ +#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */ +#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */ +#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */ +#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */ +#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */ +#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */ +#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */ +#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */ +#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */ +#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */ +#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */ +#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */ +#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */ +#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */ +#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */ +#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */ +#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */ +#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */ +#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */ +#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */ +#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */ +#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */ +#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */ +#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */ +#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */ +#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */ +#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */ +#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */ +#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */ +#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */ +#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */ +#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */ +#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */ +#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */ +#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */ +#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */ +#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */ +#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */ +#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */ +#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */ +#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */ +#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */ +#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */ +#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */ +#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */ +#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */ +#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */ +#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */ +#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */ +#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */ +#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */ +#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */ +#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */ +#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */ +#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */ +#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */ +#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */ +#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */ +#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */ +#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */ +#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */ +#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */ +#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */ +#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */ +#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */ +#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */ +#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */ +#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */ +#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */ +#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */ +#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */ +#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */ +#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */ +#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */ +#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */ +#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */ +#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */ +#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */ +#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */ +#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */ +#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */ +#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */ +#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */ +#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */ +#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */ +#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */ +#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */ +#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */ +#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */ +#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */ +#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */ +#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */ +#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */ +#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */ +#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */ +#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */ +#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */ +#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */ +#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */ +#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */ +#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */ +#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */ +#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */ +#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */ +#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */ +#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */ +#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */ +#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */ +#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */ +#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */ +#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */ +#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */ +#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */ +#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */ +#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */ +#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */ +#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */ +#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */ +#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */ +#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */ +#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */ + +/* HOST Port Registers */ + +#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */ +#define HOST_STATUS 0xffc03a04 /* HOST Status Register */ +#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */ + +/* Pixel Compositor (PIXC) Registers */ + +#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ +#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */ +#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */ +#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */ +#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */ +#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */ +#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */ +#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */ +#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */ +#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */ +#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */ +#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */ +#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */ +#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */ +#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ +#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */ +#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */ +#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */ +#define PIXC_TC 0xffc04450 /* Holds the transparent color value */ + +/* Handshake MDMA 0 Registers */ + +#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */ +#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */ +#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */ +#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ +#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ +#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */ +#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */ + +/* Handshake MDMA 1 Registers */ + +#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */ +#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */ +#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */ +#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ +#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ +#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */ +#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */ + + +/* ********************************************************** */ +/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ +/* and MULTI BIT READ MACROS */ +/* ********************************************************** */ + +/* Bit masks for PIXC_CTL */ + +#define PIXC_EN 0x1 /* Pixel Compositor Enable */ +#define OVR_A_EN 0x2 /* Overlay A Enable */ +#define OVR_B_EN 0x4 /* Overlay B Enable */ +#define IMG_FORM 0x8 /* Image Data Format */ +#define OVR_FORM 0x10 /* Overlay Data Format */ +#define OUT_FORM 0x20 /* Output Data Format */ +#define UDS_MOD 0x40 /* Resampling Mode */ +#define TC_EN 0x80 /* Transparent Color Enable */ +#define IMG_STAT 0x300 /* Image FIFO Status */ +#define OVR_STAT 0xc00 /* Overlay FIFO Status */ +#define WM_LVL 0x3000 /* FIFO Watermark Level */ + +/* Bit masks for PIXC_AHSTART */ + +#define A_HSTART 0xfff /* Horizontal Start Coordinates */ + +/* Bit masks for PIXC_AHEND */ + +#define A_HEND 0xfff /* Horizontal End Coordinates */ + +/* Bit masks for PIXC_AVSTART */ + +#define A_VSTART 0x3ff /* Vertical Start Coordinates */ + +/* Bit masks for PIXC_AVEND */ + +#define A_VEND 0x3ff /* Vertical End Coordinates */ + +/* Bit masks for PIXC_ATRANSP */ + +#define A_TRANSP 0xf /* Transparency Value */ + +/* Bit masks for PIXC_BHSTART */ + +#define B_HSTART 0xfff /* Horizontal Start Coordinates */ + +/* Bit masks for PIXC_BHEND */ + +#define B_HEND 0xfff /* Horizontal End Coordinates */ + +/* Bit masks for PIXC_BVSTART */ + +#define B_VSTART 0x3ff /* Vertical Start Coordinates */ + +/* Bit masks for PIXC_BVEND */ + +#define B_VEND 0x3ff /* Vertical End Coordinates */ + +/* Bit masks for PIXC_BTRANSP */ + +#define B_TRANSP 0xf /* Transparency Value */ + +/* Bit masks for PIXC_INTRSTAT */ + +#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ +#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ +#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ +#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ + +/* Bit masks for PIXC_RYCON */ + +#define A11 0x3ff /* A11 in the Coefficient Matrix */ +#define A12 0xffc00 /* A12 in the Coefficient Matrix */ +#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ +#define RY_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_GUCON */ + +#define A21 0x3ff /* A21 in the Coefficient Matrix */ +#define A22 0xffc00 /* A22 in the Coefficient Matrix */ +#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ +#define GU_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_BVCON */ + +#define A31 0x3ff /* A31 in the Coefficient Matrix */ +#define A32 0xffc00 /* A32 in the Coefficient Matrix */ +#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ +#define BV_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_CCBIAS */ + +#define A14 0x3ff /* A14 in the Bias Vector */ +#define A24 0xffc00 /* A24 in the Bias Vector */ +#define A34 0x3ff00000 /* A34 in the Bias Vector */ + +/* Bit masks for PIXC_TC */ + +#define RY_TRANS 0xff /* Transparent Color - R/Y Component */ +#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */ +#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */ + +/* Bit masks for HOST_CONTROL */ + +#define HOST_EN 0x1 /* Host Enable */ +#define HOST_END 0x2 /* Host Endianess */ +#define DATA_SIZE 0x4 /* Data Size */ +#define HOST_RST 0x8 /* Host Reset */ +#define HRDY_OVR 0x20 /* Host Ready Override */ +#define INT_MODE 0x40 /* Interrupt Mode */ +#define BT_EN 0x80 /* Bus Timeout Enable */ +#define EHW 0x100 /* Enable Host Write */ +#define EHR 0x200 /* Enable Host Read */ +#define BDR 0x400 /* Burst DMA Requests */ + +/* Bit masks for HOST_STATUS */ + +#define DMA_READY 0x1 /* DMA Ready */ +#define FIFOFULL 0x2 /* FIFO Full */ +#define FIFOEMPTY 0x4 /* FIFO Empty */ +#define COMPLETE 0x8 /* DMA Complete */ +#define HSHK 0x10 /* Host Handshake */ +#define TIMEOUT 0x20 /* Host Timeout */ +#define HIRQ 0x40 /* Host Interrupt Request */ +#define ALLOW_CNFG 0x80 /* Allow New Configuration */ +#define DMA_DIR 0x100 /* DMA Direction */ +#define BTE 0x200 /* Bus Timeout Enabled */ + +/* Bit masks for HOST_TIMEOUT */ + +#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */ + +/* Bit masks for TIMER_ENABLE1 */ + +#define TIMEN8 0x1 /* Timer 8 Enable */ +#define TIMEN9 0x2 /* Timer 9 Enable */ +#define TIMEN10 0x4 /* Timer 10 Enable */ + +/* Bit masks for TIMER_DISABLE1 */ + +#define TIMDIS8 0x1 /* Timer 8 Disable */ +#define TIMDIS9 0x2 /* Timer 9 Disable */ +#define TIMDIS10 0x4 /* Timer 10 Disable */ + +/* Bit masks for TIMER_STATUS1 */ + +#define TIMIL8 0x1 /* Timer 8 Interrupt */ +#define TIMIL9 0x2 /* Timer 9 Interrupt */ +#define TIMIL10 0x4 /* Timer 10 Interrupt */ +#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ +#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ +#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ +#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ +#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ +#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ + +/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ + +/* Bit masks for HMDMAx_CONTROL */ + +#define HMDMAEN 0x1 /* Handshake MDMA Enable */ +#define REP 0x2 /* Handshake MDMA Request Polarity */ +#define UTE 0x8 /* Urgency Threshold Enable */ +#define OIE 0x10 /* Overflow Interrupt Enable */ +#define BDIE 0x20 /* Block Done Interrupt Enable */ +#define MBDI 0x40 /* Mask Block Done Interrupt */ +#define DRQ 0x300 /* Handshake MDMA Request Type */ +#define RBC 0x1000 /* Force Reload of BCOUNT */ +#define PS 0x2000 /* Pin Status */ +#define OI 0x4000 /* Overflow Interrupt Generated */ +#define BDI 0x8000 /* Block Done Interrupt Generated */ + +/* ******************************************* */ +/* MULTI BIT MACRO ENUMERATIONS */ +/* ******************************************* */ + +#endif /* _DEF_BF544_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h new file mode 100644 index 000000000000..661f0d877bd1 --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h @@ -0,0 +1,1244 @@ +/* + * File: include/asm-blackfin/mach-bf548/defBF547.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _DEF_BF548_H +#define _DEF_BF548_H + +/* Include all Core registers and bit definitions */ +#include <asm/def_LPBlackfin.h> + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */ + +/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ +#include "defBF54x_base.h" + +/* The following are the #defines needed by ADSP-BF548 that are not in the common header */ + +/* Timer Registers */ + +#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */ +#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */ +#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */ +#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */ +#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */ +#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */ +#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */ +#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */ +#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */ +#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */ +#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */ +#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */ + +/* Timer Group of 3 Registers */ + +#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */ +#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */ +#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */ + +/* SPORT0 Registers */ + +#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */ +#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */ +#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */ +#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */ +#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */ +#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */ +#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */ +#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */ +#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */ +#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */ +#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */ +#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */ +#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */ +#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */ +#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */ +#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */ +#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */ +#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */ +#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */ +#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */ + +/* EPPI0 Registers */ + +#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */ +#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */ +#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */ +#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */ +#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */ +#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */ +#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */ +#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */ +#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */ +#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ +#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ +#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ +#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ +#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */ + +/* UART2 Registers */ + +#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */ +#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */ +#define UART2_GCTL 0xffc02108 /* Global Control Register */ +#define UART2_LCR 0xffc0210c /* Line Control Register */ +#define UART2_MCR 0xffc02110 /* Modem Control Register */ +#define UART2_LSR 0xffc02114 /* Line Status Register */ +#define UART2_MSR 0xffc02118 /* Modem Status Register */ +#define UART2_SCR 0xffc0211c /* Scratch Register */ +#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */ +#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */ +#define UART2_RBR 0xffc0212c /* Receive Buffer Register */ + +/* Two Wire Interface Registers (TWI1) */ + +#define TWI1_REGBASE 0xffc02200 +#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ +#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ +#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ +#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ +#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ +#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */ +#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ +#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ +#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ +#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ +#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */ +#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ +#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ +#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ +#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */ +#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */ + +/* SPI2 Registers */ + +#define SPI2_REGBASE 0xffc02400 +#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ +#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ +#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ +#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */ +#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */ +#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */ +#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */ + +/* ATAPI Registers */ + +#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */ +#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */ +#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */ +#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */ +#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */ +#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */ +#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */ +#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */ +#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */ +#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */ +#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */ +#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */ +#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */ +#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */ +#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */ +#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */ +#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */ +#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */ +#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */ +#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */ +#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */ +#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */ +#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */ +#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */ +#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */ + +/* SDH Registers */ + +#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */ +#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */ +#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */ +#define SDH_COMMAND 0xffc0390c /* SDH Command */ +#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */ +#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */ +#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */ +#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */ +#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */ +#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */ +#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */ +#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */ +#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */ +#define SDH_STATUS 0xffc03934 /* SDH Status */ +#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */ +#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */ +#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */ +#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */ +#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */ +#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */ +#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */ +#define SDH_CFG 0xffc039c8 /* SDH Configuration */ +#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */ +#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */ +#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */ +#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */ +#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */ +#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */ +#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */ +#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */ +#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */ + +/* HOST Port Registers */ + +#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */ +#define HOST_STATUS 0xffc03a04 /* HOST Status Register */ +#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */ + +/* USB Control Registers */ + +#define USB_FADDR 0xffc03c00 /* Function address register */ +#define USB_POWER 0xffc03c04 /* Power management register */ +#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ +#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */ +#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */ +#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */ +#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */ +#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */ +#define USB_FRAME 0xffc03c20 /* USB frame number */ +#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */ +#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */ +#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ +#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */ + +/* USB Packet Control Registers */ + +#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */ +#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ +#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ +#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */ +#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */ +#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ +#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ +#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ +#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ +#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ +#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ +#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ +#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */ + +/* USB Endpoint FIFO Registers */ + +#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */ +#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */ +#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */ +#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */ +#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */ +#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */ +#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */ +#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */ + +/* USB OTG Control Registers */ + +#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */ +#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */ +#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */ + +/* USB Phy Control Registers */ + +#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */ +#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */ +#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */ +#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */ +#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */ + +/* (APHY_CNTRL is for ADI usage only) */ + +#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */ + +/* (APHY_CALIB is for ADI usage only) */ + +#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */ +#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ + +/* (PHY_TEST is for ADI usage only) */ + +#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */ +#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */ +#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ + +/* USB Endpoint 0 Control Registers */ + +#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */ +#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */ +#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */ +#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */ +#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */ +#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ +#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */ +#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ +#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ + +/* USB Endpoint 1 Control Registers */ + +#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ +#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */ +#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */ +#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */ +#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */ +#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */ +#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ +#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */ +#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ +#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ + +/* USB Endpoint 2 Control Registers */ + +#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ +#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */ +#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */ +#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */ +#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */ +#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */ +#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ +#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */ +#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ +#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ + +/* USB Endpoint 3 Control Registers */ + +#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ +#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */ +#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */ +#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */ +#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */ +#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */ +#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ +#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */ +#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ +#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ + +/* USB Endpoint 4 Control Registers */ + +#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ +#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */ +#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */ +#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */ +#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */ +#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */ +#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ +#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */ +#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ +#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ + +/* USB Endpoint 5 Control Registers */ + +#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ +#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */ +#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */ +#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */ +#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */ +#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */ +#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ +#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */ +#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ +#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ + +/* USB Endpoint 6 Control Registers */ + +#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */ +#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */ +#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */ +#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */ +#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */ +#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */ +#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ +#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */ +#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ +#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ + +/* USB Endpoint 7 Control Registers */ + +#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ +#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */ +#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */ +#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */ +#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */ +#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */ +#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ +#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */ +#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ +#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ +#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ +#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */ + +/* USB Channel 0 Config Registers */ + +#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */ +#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ +#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ +#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ +#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ + +/* USB Channel 1 Config Registers */ + +#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */ +#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ +#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ +#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ +#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ + +/* USB Channel 2 Config Registers */ + +#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */ +#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ +#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ +#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ +#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ + +/* USB Channel 3 Config Registers */ + +#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */ +#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ +#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ +#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ +#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ + +/* USB Channel 4 Config Registers */ + +#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */ +#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ +#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ +#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ +#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ + +/* USB Channel 5 Config Registers */ + +#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */ +#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ +#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ +#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ +#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ + +/* USB Channel 6 Config Registers */ + +#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */ +#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ +#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ +#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ +#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ + +/* USB Channel 7 Config Registers */ + +#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */ +#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ +#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ +#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ +#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ + +/* Keypad Registers */ + +#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */ +#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */ +#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */ +#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */ +#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */ +#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */ + +/* Pixel Compositor (PIXC) Registers */ + +#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ +#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */ +#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */ +#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */ +#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */ +#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */ +#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */ +#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */ +#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */ +#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */ +#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */ +#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */ +#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */ +#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */ +#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ +#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */ +#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */ +#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */ +#define PIXC_TC 0xffc04450 /* Holds the transparent color value */ + +/* Handshake MDMA 0 Registers */ + +#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */ +#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */ +#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */ +#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ +#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ +#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */ +#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */ + +/* Handshake MDMA 1 Registers */ + +#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */ +#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */ +#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */ +#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ +#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ +#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */ +#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */ + + +/* ********************************************************** */ +/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ +/* and MULTI BIT READ MACROS */ +/* ********************************************************** */ + +/* Bit masks for PIXC_CTL */ + +#define PIXC_EN 0x1 /* Pixel Compositor Enable */ +#define OVR_A_EN 0x2 /* Overlay A Enable */ +#define OVR_B_EN 0x4 /* Overlay B Enable */ +#define IMG_FORM 0x8 /* Image Data Format */ +#define OVR_FORM 0x10 /* Overlay Data Format */ +#define OUT_FORM 0x20 /* Output Data Format */ +#define UDS_MOD 0x40 /* Resampling Mode */ +#define TC_EN 0x80 /* Transparent Color Enable */ +#define IMG_STAT 0x300 /* Image FIFO Status */ +#define OVR_STAT 0xc00 /* Overlay FIFO Status */ +#define WM_LVL 0x3000 /* FIFO Watermark Level */ + +/* Bit masks for PIXC_AHSTART */ + +#define A_HSTART 0xfff /* Horizontal Start Coordinates */ + +/* Bit masks for PIXC_AHEND */ + +#define A_HEND 0xfff /* Horizontal End Coordinates */ + +/* Bit masks for PIXC_AVSTART */ + +#define A_VSTART 0x3ff /* Vertical Start Coordinates */ + +/* Bit masks for PIXC_AVEND */ + +#define A_VEND 0x3ff /* Vertical End Coordinates */ + +/* Bit masks for PIXC_ATRANSP */ + +#define A_TRANSP 0xf /* Transparency Value */ + +/* Bit masks for PIXC_BHSTART */ + +#define B_HSTART 0xfff /* Horizontal Start Coordinates */ + +/* Bit masks for PIXC_BHEND */ + +#define B_HEND 0xfff /* Horizontal End Coordinates */ + +/* Bit masks for PIXC_BVSTART */ + +#define B_VSTART 0x3ff /* Vertical Start Coordinates */ + +/* Bit masks for PIXC_BVEND */ + +#define B_VEND 0x3ff /* Vertical End Coordinates */ + +/* Bit masks for PIXC_BTRANSP */ + +#define B_TRANSP 0xf /* Transparency Value */ + +/* Bit masks for PIXC_INTRSTAT */ + +#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ +#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ +#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ +#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ + +/* Bit masks for PIXC_RYCON */ + +#define A11 0x3ff /* A11 in the Coefficient Matrix */ +#define A12 0xffc00 /* A12 in the Coefficient Matrix */ +#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ +#define RY_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_GUCON */ + +#define A21 0x3ff /* A21 in the Coefficient Matrix */ +#define A22 0xffc00 /* A22 in the Coefficient Matrix */ +#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ +#define GU_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_BVCON */ + +#define A31 0x3ff /* A31 in the Coefficient Matrix */ +#define A32 0xffc00 /* A32 in the Coefficient Matrix */ +#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ +#define BV_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_CCBIAS */ + +#define A14 0x3ff /* A14 in the Bias Vector */ +#define A24 0xffc00 /* A24 in the Bias Vector */ +#define A34 0x3ff00000 /* A34 in the Bias Vector */ + +/* Bit masks for PIXC_TC */ + +#define RY_TRANS 0xff /* Transparent Color - R/Y Component */ +#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */ +#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */ + +/* Bit masks for HOST_CONTROL */ + +#define HOST_EN 0x1 /* Host Enable */ +#define HOST_END 0x2 /* Host Endianess */ +#define DATA_SIZE 0x4 /* Data Size */ +#define HOST_RST 0x8 /* Host Reset */ +#define HRDY_OVR 0x20 /* Host Ready Override */ +#define INT_MODE 0x40 /* Interrupt Mode */ +#define BT_EN 0x80 /* Bus Timeout Enable */ +#define EHW 0x100 /* Enable Host Write */ +#define EHR 0x200 /* Enable Host Read */ +#define BDR 0x400 /* Burst DMA Requests */ + +/* Bit masks for HOST_STATUS */ + +#define DMA_READY 0x1 /* DMA Ready */ +#define FIFOFULL 0x2 /* FIFO Full */ +#define FIFOEMPTY 0x4 /* FIFO Empty */ +#define DMA_COMPLETE 0x8 /* DMA Complete */ +#define HSHK 0x10 /* Host Handshake */ +#define HSTIMEOUT 0x20 /* Host Timeout */ +#define HIRQ 0x40 /* Host Interrupt Request */ +#define ALLOW_CNFG 0x80 /* Allow New Configuration */ +#define DMA_DIR 0x100 /* DMA Direction */ +#define BTE 0x200 /* Bus Timeout Enabled */ + +/* Bit masks for HOST_TIMEOUT */ + +#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */ + +/* Bit masks for KPAD_CTL */ + +#define KPAD_EN 0x1 /* Keypad Enable */ +#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ +#define KPAD_ROWEN 0x1c00 /* Row Enable Width */ +#define KPAD_COLEN 0xe000 /* Column Enable Width */ + +/* Bit masks for KPAD_PRESCALE */ + +#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */ + +/* Bit masks for KPAD_MSEL */ + +#define DBON_SCALE 0xff /* Debounce Scale Value */ +#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */ + +/* Bit masks for KPAD_ROWCOL */ + +#define KPAD_ROW 0xff /* Rows Pressed */ +#define KPAD_COL 0xff00 /* Columns Pressed */ + +/* Bit masks for KPAD_STAT */ + +#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ +#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ +#define KPAD_PRESSED 0x8 /* Key press current status */ + +/* Bit masks for KPAD_SOFTEVAL */ + +#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ + +/* Bit masks for SDH_COMMAND */ + +#define CMD_IDX 0x3f /* Command Index */ +#define CMD_RSP 0x40 /* Response */ +#define CMD_L_RSP 0x80 /* Long Response */ +#define CMD_INT_E 0x100 /* Command Interrupt */ +#define CMD_PEND_E 0x200 /* Command Pending */ +#define CMD_E 0x400 /* Command Enable */ + +/* Bit masks for SDH_PWR_CTL */ + +#define PWR_ON 0x3 /* Power On */ +#if 0 +#define TBD 0x3c /* TBD */ +#endif +#define SD_CMD_OD 0x40 /* Open Drain Output */ +#define ROD_CTL 0x80 /* Rod Control */ + +/* Bit masks for SDH_CLK_CTL */ + +#define CLKDIV 0xff /* MC_CLK Divisor */ +#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ +#define PWR_SV_E 0x200 /* Power Save Enable */ +#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ +#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ + +/* Bit masks for SDH_RESP_CMD */ + +#define RESP_CMD 0x3f /* Response Command */ + +/* Bit masks for SDH_DATA_CTL */ + +#define DTX_E 0x1 /* Data Transfer Enable */ +#define DTX_DIR 0x2 /* Data Transfer Direction */ +#define DTX_MODE 0x4 /* Data Transfer Mode */ +#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ +#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ + +/* Bit masks for SDH_STATUS */ + +#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ +#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ +#define CMD_TIME_OUT 0x4 /* CMD Time Out */ +#define DAT_TIME_OUT 0x8 /* Data Time Out */ +#define TX_UNDERRUN 0x10 /* Transmit Underrun */ +#define RX_OVERRUN 0x20 /* Receive Overrun */ +#define CMD_RESP_END 0x40 /* CMD Response End */ +#define CMD_SENT 0x80 /* CMD Sent */ +#define DAT_END 0x100 /* Data End */ +#define START_BIT_ERR 0x200 /* Start Bit Error */ +#define DAT_BLK_END 0x400 /* Data Block End */ +#define CMD_ACT 0x800 /* CMD Active */ +#define TX_ACT 0x1000 /* Transmit Active */ +#define RX_ACT 0x2000 /* Receive Active */ +#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ +#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ +#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ +#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ +#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ +#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ +#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ +#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ + +/* Bit masks for SDH_STATUS_CLR */ + +#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ +#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ +#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ +#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ +#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ +#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ +#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ +#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ +#define DAT_END_STAT 0x100 /* Data End Status */ +#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ +#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ + +/* Bit masks for SDH_MASK0 */ + +#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ +#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ +#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ +#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ +#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ +#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ +#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ +#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ +#define DAT_END_MASK 0x100 /* Data End Mask */ +#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ +#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ +#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ +#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ +#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ +#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ +#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ +#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ +#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ +#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ +#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ +#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ +#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ + +/* Bit masks for SDH_FIFO_CNT */ + +#define FIFO_COUNT 0x7fff /* FIFO Count */ + +/* Bit masks for SDH_E_STATUS */ + +#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ +#define SD_CARD_DET 0x10 /* SD Card Detect */ + +/* Bit masks for SDH_E_MASK */ + +#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ +#define SCD_MSK 0x40 /* Mask Card Detect */ + +/* Bit masks for SDH_CFG */ + +#define CLKS_EN 0x1 /* Clocks Enable */ +#define SD4E 0x4 /* SDIO 4-Bit Enable */ +#define MWE 0x8 /* Moving Window Enable */ +#define SD_RST 0x10 /* SDMMC Reset */ +#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ +#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ +#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ + +/* Bit masks for SDH_RD_WAIT_EN */ + +#define RWR 0x1 /* Read Wait Request */ + +/* Bit masks for ATAPI_CONTROL */ + +#define PIO_START 0x1 /* Start PIO/Reg Op */ +#define MULTI_START 0x2 /* Start Multi-DMA Op */ +#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ +#define XFER_DIR 0x8 /* Transfer Direction */ +#define IORDY_EN 0x10 /* IORDY Enable */ +#define FIFO_FLUSH 0x20 /* Flush FIFOs */ +#define SOFT_RST 0x40 /* Soft Reset */ +#define DEV_RST 0x80 /* Device Reset */ +#define TFRCNT_RST 0x100 /* Trans Count Reset */ +#define END_ON_TERM 0x200 /* End/Terminate Select */ +#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ +#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ + +/* Bit masks for ATAPI_STATUS */ + +#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ +#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ +#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ +#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ + +/* Bit masks for ATAPI_DEV_ADDR */ + +#define DEV_ADDR 0x1f /* Device Address */ + +/* Bit masks for ATAPI_INT_MASK */ + +#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ +#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ +#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ +#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ +#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ +#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ +#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ +#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ +#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ + +/* Bit masks for ATAPI_INT_STATUS */ + +#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ +#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ +#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ +#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ +#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ +#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ +#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ +#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ +#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ + +/* Bit masks for ATAPI_LINE_STATUS */ + +#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ +#define ATAPI_DASP 0x2 /* Device dasp to host line status */ +#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ +#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ +#define ATAPI_ADDR 0x70 /* ATAPI address line status */ +#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ +#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ +#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ +#define ATAPI_DIORN 0x400 /* ATAPI read line status */ +#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_SM_STATE */ + +#define PIO_CSTATE 0xf /* PIO mode state machine current state */ +#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */ +#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */ +#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_TERMINATE */ + +#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ + +/* Bit masks for ATAPI_REG_TIM_0 */ + +#define T2_REG 0xff /* End of cycle time for register access transfers */ +#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */ + +/* Bit masks for ATAPI_PIO_TIM_0 */ + +#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */ +#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */ +#define T4_REG 0xf000 /* DIOW data hold */ + +/* Bit masks for ATAPI_PIO_TIM_1 */ + +#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */ + +/* Bit masks for ATAPI_MULTI_TIM_0 */ + +#define TD 0xff /* DIOR/DIOW asserted pulsewidth */ +#define TM 0xff00 /* Time from address valid to DIOR/DIOW */ + +/* Bit masks for ATAPI_MULTI_TIM_1 */ + +#define TKW 0xff /* Selects DIOW negated pulsewidth */ +#define TKR 0xff00 /* Selects DIOR negated pulsewidth */ + +/* Bit masks for ATAPI_MULTI_TIM_2 */ + +#define TH 0xff /* Selects DIOW data hold */ +#define TEOC 0xff00 /* Selects end of cycle for DMA */ + +/* Bit masks for ATAPI_ULTRA_TIM_0 */ + +#define TACK 0xff /* Selects setup and hold times for TACK */ +#define TENV 0xff00 /* Selects envelope time */ + +/* Bit masks for ATAPI_ULTRA_TIM_1 */ + +#define TDVS 0xff /* Selects data valid setup time */ +#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */ + +/* Bit masks for ATAPI_ULTRA_TIM_2 */ + +#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */ +#define TMLI 0xff00 /* Selects interlock time */ + +/* Bit masks for ATAPI_ULTRA_TIM_3 */ + +#define TZAH 0xff /* Selects minimum delay required for output */ +#define READY_PAUSE 0xff00 /* Selects ready to pause */ + +/* Bit masks for TIMER_ENABLE1 */ + +#define TIMEN8 0x1 /* Timer 8 Enable */ +#define TIMEN9 0x2 /* Timer 9 Enable */ +#define TIMEN10 0x4 /* Timer 10 Enable */ + +/* Bit masks for TIMER_DISABLE1 */ + +#define TIMDIS8 0x1 /* Timer 8 Disable */ +#define TIMDIS9 0x2 /* Timer 9 Disable */ +#define TIMDIS10 0x4 /* Timer 10 Disable */ + +/* Bit masks for TIMER_STATUS1 */ + +#define TIMIL8 0x1 /* Timer 8 Interrupt */ +#define TIMIL9 0x2 /* Timer 9 Interrupt */ +#define TIMIL10 0x4 /* Timer 10 Interrupt */ +#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ +#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ +#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ +#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ +#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ +#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ + +/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ + +/* Bit masks for USB_FADDR */ + +#define FUNCTION_ADDRESS 0x7f /* Function address */ + +/* Bit masks for USB_POWER */ + +#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ +#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ +#define RESUME_MODE 0x4 /* DMA Mode */ +#define RESET 0x8 /* Reset indicator */ +#define HS_MODE 0x10 /* High Speed mode indicator */ +#define HS_ENABLE 0x20 /* high Speed Enable */ +#define SOFT_CONN 0x40 /* Soft connect */ +#define ISO_UPDATE 0x80 /* Isochronous update */ + +/* Bit masks for USB_INTRTX */ + +#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ +#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ +#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ +#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ +#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ +#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ +#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ +#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ + +/* Bit masks for USB_INTRRX */ + +#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ +#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ +#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ +#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ +#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ +#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ +#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ + +/* Bit masks for USB_INTRTXE */ + +#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ +#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ +#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ +#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ +#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ +#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ +#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ +#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ + +/* Bit masks for USB_INTRRXE */ + +#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ +#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ +#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ +#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ +#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ +#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ +#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ + +/* Bit masks for USB_INTRUSB */ + +#define SUSPEND_B 0x1 /* Suspend indicator */ +#define RESUME_B 0x2 /* Resume indicator */ +#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ +#define SOF_B 0x8 /* Start of frame */ +#define CONN_B 0x10 /* Connection indicator */ +#define DISCON_B 0x20 /* Disconnect indicator */ +#define SESSION_REQ_B 0x40 /* Session Request */ +#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ + +/* Bit masks for USB_INTRUSBE */ + +#define SUSPEND_BE 0x1 /* Suspend indicator int enable */ +#define RESUME_BE 0x2 /* Resume indicator int enable */ +#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ +#define SOF_BE 0x8 /* Start of frame int enable */ +#define CONN_BE 0x10 /* Connection indicator int enable */ +#define DISCON_BE 0x20 /* Disconnect indicator int enable */ +#define SESSION_REQ_BE 0x40 /* Session Request int enable */ +#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ + +/* Bit masks for USB_FRAME */ + +#define FRAME_NUMBER 0x7ff /* Frame number */ + +/* Bit masks for USB_INDEX */ + +#define SELECTED_ENDPOINT 0xf /* selected endpoint */ + +/* Bit masks for USB_GLOBAL_CTL */ + +#define GLOBAL_ENA 0x1 /* enables USB module */ +#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ +#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ +#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ +#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ +#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ +#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ +#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ +#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ +#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ +#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ +#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ +#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ +#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ +#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ + +/* Bit masks for USB_OTG_DEV_CTL */ + +#define SESSION 0x1 /* session indicator */ +#define HOST_REQ 0x2 /* Host negotiation request */ +#define HOST_MODE 0x4 /* indicates USBDRC is a host */ +#define VBUS0 0x8 /* Vbus level indicator[0] */ +#define VBUS1 0x10 /* Vbus level indicator[1] */ +#define LSDEV 0x20 /* Low-speed indicator */ +#define FSDEV 0x40 /* Full or High-speed indicator */ +#define B_DEVICE 0x80 /* A' or 'B' device indicator */ + +/* Bit masks for USB_OTG_VBUS_IRQ */ + +#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ +#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ +#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ +#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ +#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ +#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ + +/* Bit masks for USB_OTG_VBUS_MASK */ + +#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ +#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ +#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ +#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ +#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ +#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ + +/* Bit masks for USB_CSR0 */ + +#define RXPKTRDY 0x1 /* data packet receive indicator */ +#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ +#define STALL_SENT 0x4 /* STALL handshake sent */ +#define DATAEND 0x8 /* Data end indicator */ +#define SETUPEND 0x10 /* Setup end */ +#define SENDSTALL 0x20 /* Send STALL handshake */ +#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ +#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ +#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ +#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ +#define SETUPPKT_H 0x8 /* send Setup token host mode */ +#define ERROR_H 0x10 /* timeout error indicator host mode */ +#define REQPKT_H 0x20 /* Request an IN transaction host mode */ +#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ +#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ + +/* Bit masks for USB_COUNT0 */ + +#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ + +/* Bit masks for USB_NAKLIMIT0 */ + +#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ + +/* Bit masks for USB_TX_MAX_PACKET */ + +#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ + +/* Bit masks for USB_RX_MAX_PACKET */ + +#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ + +/* Bit masks for USB_TXCSR */ + +#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ +#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ +#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ +#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ +#define STALL_SEND_T 0x10 /* issue a Stall handshake */ +#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ +#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ +#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ +#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ +#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ +#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ +#define ISO_T 0x4000 /* enable Isochronous transfers */ +#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ +#define ERROR_TH 0x4 /* error condition host mode */ +#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ +#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ + +/* Bit masks for USB_TXCOUNT */ + +#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ + +/* Bit masks for USB_RXCSR */ + +#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ +#define FIFO_FULL_R 0x2 /* FIFO not empty */ +#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ +#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ +#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ +#define STALL_SEND_R 0x20 /* issue a Stall handshake */ +#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ +#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ +#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ +#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ +#define DISNYET_R 0x1000 /* disable Nyet handshakes */ +#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ +#define ISO_R 0x4000 /* enable Isochronous transfers */ +#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ +#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ +#define REQPKT_RH 0x20 /* request an IN transaction host mode */ +#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ +#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ +#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ +#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ + +/* Bit masks for USB_RXCOUNT */ + +#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ + +/* Bit masks for USB_TXTYPE */ + +#define TARGET_EP_NO_T 0xf /* EP number */ +#define PROTOCOL_T 0xc /* transfer type */ + +/* Bit masks for USB_TXINTERVAL */ + +#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ + +/* Bit masks for USB_RXTYPE */ + +#define TARGET_EP_NO_R 0xf /* EP number */ +#define PROTOCOL_R 0xc /* transfer type */ + +/* Bit masks for USB_RXINTERVAL */ + +#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ + +/* Bit masks for USB_DMA_INTERRUPT */ + +#define DMA0_INT 0x1 /* DMA0 pending interrupt */ +#define DMA1_INT 0x2 /* DMA1 pending interrupt */ +#define DMA2_INT 0x4 /* DMA2 pending interrupt */ +#define DMA3_INT 0x8 /* DMA3 pending interrupt */ +#define DMA4_INT 0x10 /* DMA4 pending interrupt */ +#define DMA5_INT 0x20 /* DMA5 pending interrupt */ +#define DMA6_INT 0x40 /* DMA6 pending interrupt */ +#define DMA7_INT 0x80 /* DMA7 pending interrupt */ + +/* Bit masks for USB_DMAxCONTROL */ + +#define DMA_ENA 0x1 /* DMA enable */ +#define DIRECTION 0x2 /* direction of DMA transfer */ +#define MODE 0x4 /* DMA Bus error */ +#define INT_ENA 0x8 /* Interrupt enable */ +#define EPNUM 0xf0 /* EP number */ +#define BUSERROR 0x100 /* DMA Bus error */ + +/* Bit masks for USB_DMAxADDRHIGH */ + +#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ + +/* Bit masks for USB_DMAxADDRLOW */ + +#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ + +/* Bit masks for USB_DMAxCOUNTHIGH */ + +#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ + +/* Bit masks for USB_DMAxCOUNTLOW */ + +#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ + +/* Bit masks for HMDMAx_CONTROL */ + +#define HMDMAEN 0x1 /* Handshake MDMA Enable */ +#define REP 0x2 /* Handshake MDMA Request Polarity */ +#define UTE 0x8 /* Urgency Threshold Enable */ +#define OIE 0x10 /* Overflow Interrupt Enable */ +#define BDIE 0x20 /* Block Done Interrupt Enable */ +#define MBDI 0x40 /* Mask Block Done Interrupt */ +#define DRQ 0x300 /* Handshake MDMA Request Type */ +#define RBC 0x1000 /* Force Reload of BCOUNT */ +#define PS 0x2000 /* Pin Status */ +#define OI 0x4000 /* Overflow Interrupt Generated */ +#define BDI 0x8000 /* Block Done Interrupt Generated */ + +/* ******************************************* */ +/* MULTI BIT MACRO ENUMERATIONS */ +/* ******************************************* */ + + +#endif /* _DEF_BF548_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/defBF548.h b/arch/blackfin/mach-bf548/include/mach/defBF548.h new file mode 100644 index 000000000000..85d4bade911d --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/defBF548.h @@ -0,0 +1,1627 @@ +/* + * File: include/asm-blackfin/mach-bf548/defBF548.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _DEF_BF548_H +#define _DEF_BF548_H + +/* Include all Core registers and bit definitions */ +#include <asm/def_LPBlackfin.h> + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */ + +/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ +#include "defBF54x_base.h" + +/* The following are the #defines needed by ADSP-BF548 that are not in the common header */ + +/* Timer Registers */ + +#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */ +#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */ +#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */ +#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */ +#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */ +#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */ +#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */ +#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */ +#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */ +#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */ +#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */ +#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */ + +/* Timer Group of 3 Registers */ + +#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */ +#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */ +#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */ + +/* SPORT0 Registers */ + +#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */ +#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */ +#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */ +#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */ +#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */ +#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */ +#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */ +#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */ +#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */ +#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */ +#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */ +#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */ +#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */ +#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */ +#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */ +#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */ +#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */ +#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */ +#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */ +#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */ + +/* EPPI0 Registers */ + +#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */ +#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */ +#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */ +#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */ +#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */ +#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */ +#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */ +#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */ +#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */ +#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ +#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ +#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ +#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ +#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */ + +/* UART2 Registers */ + +#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */ +#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */ +#define UART2_GCTL 0xffc02108 /* Global Control Register */ +#define UART2_LCR 0xffc0210c /* Line Control Register */ +#define UART2_MCR 0xffc02110 /* Modem Control Register */ +#define UART2_LSR 0xffc02114 /* Line Status Register */ +#define UART2_MSR 0xffc02118 /* Modem Status Register */ +#define UART2_SCR 0xffc0211c /* Scratch Register */ +#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */ +#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */ +#define UART2_RBR 0xffc0212c /* Receive Buffer Register */ + +/* Two Wire Interface Registers (TWI1) */ + +#define TWI1_REGBASE 0xffc02200 +#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ +#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ +#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ +#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ +#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ +#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */ +#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ +#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ +#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ +#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ +#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */ +#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ +#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ +#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ +#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */ +#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */ + +/* SPI2 Registers */ + +#define SPI2_REGBASE 0xffc02400 +#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ +#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ +#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ +#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */ +#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */ +#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */ +#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */ + +/* CAN Controller 1 Config 1 Registers */ + +#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */ +#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */ +#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */ +#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */ +#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */ +#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */ +#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */ +#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */ +#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */ +#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */ +#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */ +#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */ +#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */ + +/* CAN Controller 1 Config 2 Registers */ + +#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */ +#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */ +#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */ +#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */ +#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */ +#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */ +#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */ +#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */ +#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */ +#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */ +#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */ +#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */ +#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */ + +/* CAN Controller 1 Clock/Interrupt/Counter Registers */ + +#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */ +#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */ +#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */ +#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */ +#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */ +#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */ +#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */ +#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */ +#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */ +#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */ +#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */ +#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */ +#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */ +#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */ +#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */ +#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */ + +/* CAN Controller 1 Mailbox Acceptance Registers */ + +#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */ +#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */ +#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */ +#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */ +#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */ +#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */ +#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */ +#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */ +#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */ +#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */ +#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */ +#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */ +#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */ +#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */ +#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */ +#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */ +#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */ +#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */ +#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */ +#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */ +#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */ +#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */ +#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */ +#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */ +#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */ +#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */ +#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */ +#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */ +#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */ +#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */ +#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */ +#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */ + +/* CAN Controller 1 Mailbox Acceptance Registers */ + +#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */ +#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */ +#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */ +#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */ +#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */ +#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */ +#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */ +#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */ +#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */ +#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */ +#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */ +#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */ +#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */ +#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */ +#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */ +#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */ +#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */ +#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */ +#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */ +#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */ +#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */ +#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */ +#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */ +#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */ +#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */ +#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */ +#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */ +#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */ +#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */ +#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */ +#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */ +#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */ + +/* CAN Controller 1 Mailbox Data Registers */ + +#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */ +#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */ +#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */ +#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */ +#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */ +#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */ +#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */ +#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */ +#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */ +#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */ +#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */ +#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */ +#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */ +#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */ +#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */ +#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */ +#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */ +#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */ +#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */ +#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */ +#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */ +#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */ +#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */ +#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */ +#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */ +#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */ +#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */ +#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */ +#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */ +#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */ +#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */ +#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */ +#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */ +#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */ +#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */ +#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */ +#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */ +#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */ +#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */ +#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */ +#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */ +#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */ +#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */ +#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */ +#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */ +#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */ +#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */ +#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */ +#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */ +#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */ +#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */ +#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */ +#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */ +#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */ +#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */ +#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */ +#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */ +#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */ +#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */ +#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */ +#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */ +#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */ +#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */ +#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */ +#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */ +#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */ +#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */ +#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */ +#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */ +#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */ +#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */ +#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */ +#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */ +#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */ +#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */ +#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */ +#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */ +#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */ +#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */ +#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */ +#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */ +#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */ +#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */ +#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */ +#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */ +#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */ +#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */ +#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */ +#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */ +#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */ +#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */ +#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */ +#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */ +#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */ +#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */ +#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */ +#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */ +#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */ +#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */ +#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */ +#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */ +#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */ +#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */ +#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */ +#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */ +#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */ +#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */ +#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */ +#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */ +#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */ +#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */ +#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */ +#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */ +#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */ +#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */ +#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */ +#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */ +#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */ +#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */ +#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */ +#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */ +#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */ +#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */ +#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */ +#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */ +#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */ +#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */ +#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */ + +/* CAN Controller 1 Mailbox Data Registers */ + +#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */ +#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */ +#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */ +#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */ +#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */ +#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */ +#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */ +#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */ +#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */ +#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */ +#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */ +#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */ +#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */ +#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */ +#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */ +#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */ +#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */ +#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */ +#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */ +#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */ +#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */ +#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */ +#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */ +#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */ +#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */ +#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */ +#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */ +#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */ +#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */ +#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */ +#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */ +#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */ +#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */ +#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */ +#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */ +#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */ +#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */ +#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */ +#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */ +#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */ +#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */ +#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */ +#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */ +#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */ +#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */ +#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */ +#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */ +#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */ +#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */ +#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */ +#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */ +#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */ +#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */ +#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */ +#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */ +#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */ +#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */ +#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */ +#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */ +#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */ +#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */ +#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */ +#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */ +#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */ +#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */ +#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */ +#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */ +#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */ +#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */ +#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */ +#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */ +#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */ +#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */ +#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */ +#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */ +#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */ +#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */ +#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */ +#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */ +#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */ +#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */ +#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */ +#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */ +#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */ +#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */ +#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */ +#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */ +#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */ +#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */ +#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */ +#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */ +#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */ +#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */ +#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */ +#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */ +#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */ +#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */ +#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */ +#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */ +#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */ +#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */ +#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */ +#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */ +#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */ +#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */ +#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */ +#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */ +#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */ +#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */ +#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */ +#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */ +#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */ +#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */ +#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */ +#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */ +#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */ +#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */ +#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */ +#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */ +#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */ +#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */ +#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */ +#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */ +#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */ +#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */ +#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */ +#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */ +#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */ + +/* ATAPI Registers */ + +#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */ +#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */ +#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */ +#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */ +#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */ +#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */ +#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */ +#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */ +#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */ +#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */ +#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */ +#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */ +#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */ +#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */ +#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */ +#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */ +#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */ +#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */ +#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */ +#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */ +#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */ +#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */ +#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */ +#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */ +#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */ + +/* SDH Registers */ + +#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */ +#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */ +#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */ +#define SDH_COMMAND 0xffc0390c /* SDH Command */ +#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */ +#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */ +#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */ +#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */ +#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */ +#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */ +#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */ +#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */ +#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */ +#define SDH_STATUS 0xffc03934 /* SDH Status */ +#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */ +#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */ +#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */ +#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */ +#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */ +#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */ +#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */ +#define SDH_CFG 0xffc039c8 /* SDH Configuration */ +#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */ +#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */ +#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */ +#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */ +#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */ +#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */ +#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */ +#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */ +#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */ + +/* HOST Port Registers */ + +#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */ +#define HOST_STATUS 0xffc03a04 /* HOST Status Register */ +#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */ + +/* USB Control Registers */ + +#define USB_FADDR 0xffc03c00 /* Function address register */ +#define USB_POWER 0xffc03c04 /* Power management register */ +#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ +#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */ +#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */ +#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */ +#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */ +#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */ +#define USB_FRAME 0xffc03c20 /* USB frame number */ +#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */ +#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */ +#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ +#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */ + +/* USB Packet Control Registers */ + +#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */ +#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ +#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ +#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */ +#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */ +#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ +#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ +#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ +#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ +#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ +#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ +#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ +#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */ + +/* USB Endpoint FIFO Registers */ + +#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */ +#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */ +#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */ +#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */ +#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */ +#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */ +#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */ +#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */ + +/* USB OTG Control Registers */ + +#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */ +#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */ +#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */ + +/* USB Phy Control Registers */ + +#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */ +#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */ +#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */ +#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */ +#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */ + +/* (APHY_CNTRL is for ADI usage only) */ + +#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */ + +/* (APHY_CALIB is for ADI usage only) */ + +#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */ +#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ + +/* (PHY_TEST is for ADI usage only) */ + +#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */ +#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */ +#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ + +/* USB Endpoint 0 Control Registers */ + +#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */ +#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */ +#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */ +#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */ +#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */ +#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ +#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */ +#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ +#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ + +/* USB Endpoint 1 Control Registers */ + +#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ +#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */ +#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */ +#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */ +#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */ +#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */ +#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ +#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */ +#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ +#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ + +/* USB Endpoint 2 Control Registers */ + +#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ +#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */ +#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */ +#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */ +#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */ +#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */ +#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ +#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */ +#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ +#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ + +/* USB Endpoint 3 Control Registers */ + +#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ +#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */ +#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */ +#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */ +#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */ +#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */ +#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ +#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */ +#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ +#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ + +/* USB Endpoint 4 Control Registers */ + +#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ +#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */ +#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */ +#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */ +#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */ +#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */ +#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ +#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */ +#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ +#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ + +/* USB Endpoint 5 Control Registers */ + +#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ +#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */ +#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */ +#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */ +#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */ +#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */ +#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ +#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */ +#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ +#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ + +/* USB Endpoint 6 Control Registers */ + +#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */ +#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */ +#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */ +#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */ +#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */ +#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */ +#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ +#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */ +#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ +#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ + +/* USB Endpoint 7 Control Registers */ + +#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ +#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */ +#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */ +#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */ +#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */ +#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */ +#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ +#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */ +#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ +#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ +#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ +#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */ + +/* USB Channel 0 Config Registers */ + +#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */ +#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ +#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ +#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ +#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ + +/* USB Channel 1 Config Registers */ + +#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */ +#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ +#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ +#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ +#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ + +/* USB Channel 2 Config Registers */ + +#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */ +#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ +#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ +#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ +#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ + +/* USB Channel 3 Config Registers */ + +#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */ +#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ +#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ +#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ +#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ + +/* USB Channel 4 Config Registers */ + +#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */ +#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ +#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ +#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ +#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ + +/* USB Channel 5 Config Registers */ + +#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */ +#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ +#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ +#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ +#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ + +/* USB Channel 6 Config Registers */ + +#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */ +#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ +#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ +#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ +#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ + +/* USB Channel 7 Config Registers */ + +#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */ +#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ +#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ +#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ +#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ + +/* Keypad Registers */ + +#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */ +#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */ +#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */ +#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */ +#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */ +#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */ + +/* Pixel Compositor (PIXC) Registers */ + +#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ +#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */ +#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */ +#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */ +#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */ +#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */ +#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */ +#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */ +#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */ +#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */ +#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */ +#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */ +#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */ +#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */ +#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ +#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */ +#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */ +#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */ +#define PIXC_TC 0xffc04450 /* Holds the transparent color value */ + +/* Handshake MDMA 0 Registers */ + +#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */ +#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */ +#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */ +#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ +#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ +#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */ +#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */ + +/* Handshake MDMA 1 Registers */ + +#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */ +#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */ +#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */ +#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ +#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ +#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */ +#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */ + + +/* ********************************************************** */ +/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ +/* and MULTI BIT READ MACROS */ +/* ********************************************************** */ + +/* Bit masks for PIXC_CTL */ + +#define PIXC_EN 0x1 /* Pixel Compositor Enable */ +#define OVR_A_EN 0x2 /* Overlay A Enable */ +#define OVR_B_EN 0x4 /* Overlay B Enable */ +#define IMG_FORM 0x8 /* Image Data Format */ +#define OVR_FORM 0x10 /* Overlay Data Format */ +#define OUT_FORM 0x20 /* Output Data Format */ +#define UDS_MOD 0x40 /* Resampling Mode */ +#define TC_EN 0x80 /* Transparent Color Enable */ +#define IMG_STAT 0x300 /* Image FIFO Status */ +#define OVR_STAT 0xc00 /* Overlay FIFO Status */ +#define WM_LVL 0x3000 /* FIFO Watermark Level */ + +/* Bit masks for PIXC_AHSTART */ + +#define A_HSTART 0xfff /* Horizontal Start Coordinates */ + +/* Bit masks for PIXC_AHEND */ + +#define A_HEND 0xfff /* Horizontal End Coordinates */ + +/* Bit masks for PIXC_AVSTART */ + +#define A_VSTART 0x3ff /* Vertical Start Coordinates */ + +/* Bit masks for PIXC_AVEND */ + +#define A_VEND 0x3ff /* Vertical End Coordinates */ + +/* Bit masks for PIXC_ATRANSP */ + +#define A_TRANSP 0xf /* Transparency Value */ + +/* Bit masks for PIXC_BHSTART */ + +#define B_HSTART 0xfff /* Horizontal Start Coordinates */ + +/* Bit masks for PIXC_BHEND */ + +#define B_HEND 0xfff /* Horizontal End Coordinates */ + +/* Bit masks for PIXC_BVSTART */ + +#define B_VSTART 0x3ff /* Vertical Start Coordinates */ + +/* Bit masks for PIXC_BVEND */ + +#define B_VEND 0x3ff /* Vertical End Coordinates */ + +/* Bit masks for PIXC_BTRANSP */ + +#define B_TRANSP 0xf /* Transparency Value */ + +/* Bit masks for PIXC_INTRSTAT */ + +#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ +#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ +#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ +#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ + +/* Bit masks for PIXC_RYCON */ + +#define A11 0x3ff /* A11 in the Coefficient Matrix */ +#define A12 0xffc00 /* A12 in the Coefficient Matrix */ +#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ +#define RY_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_GUCON */ + +#define A21 0x3ff /* A21 in the Coefficient Matrix */ +#define A22 0xffc00 /* A22 in the Coefficient Matrix */ +#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ +#define GU_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_BVCON */ + +#define A31 0x3ff /* A31 in the Coefficient Matrix */ +#define A32 0xffc00 /* A32 in the Coefficient Matrix */ +#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ +#define BV_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_CCBIAS */ + +#define A14 0x3ff /* A14 in the Bias Vector */ +#define A24 0xffc00 /* A24 in the Bias Vector */ +#define A34 0x3ff00000 /* A34 in the Bias Vector */ + +/* Bit masks for PIXC_TC */ + +#define RY_TRANS 0xff /* Transparent Color - R/Y Component */ +#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */ +#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */ + +/* Bit masks for HOST_CONTROL */ + +#define HOST_EN 0x1 /* Host Enable */ +#define HOST_END 0x2 /* Host Endianess */ +#define DATA_SIZE 0x4 /* Data Size */ +#define HOST_RST 0x8 /* Host Reset */ +#define HRDY_OVR 0x20 /* Host Ready Override */ +#define INT_MODE 0x40 /* Interrupt Mode */ +#define BT_EN 0x80 /* Bus Timeout Enable */ +#define EHW 0x100 /* Enable Host Write */ +#define EHR 0x200 /* Enable Host Read */ +#define BDR 0x400 /* Burst DMA Requests */ + +/* Bit masks for HOST_STATUS */ + +#define DMA_READY 0x1 /* DMA Ready */ +#define FIFOFULL 0x2 /* FIFO Full */ +#define FIFOEMPTY 0x4 /* FIFO Empty */ +#define DMA_COMPLETE 0x8 /* DMA Complete */ +#define HSHK 0x10 /* Host Handshake */ +#define HSTIMEOUT 0x20 /* Host Timeout */ +#define HIRQ 0x40 /* Host Interrupt Request */ +#define ALLOW_CNFG 0x80 /* Allow New Configuration */ +#define DMA_DIR 0x100 /* DMA Direction */ +#define BTE 0x200 /* Bus Timeout Enabled */ + +/* Bit masks for HOST_TIMEOUT */ + +#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */ + +/* Bit masks for KPAD_CTL */ + +#define KPAD_EN 0x1 /* Keypad Enable */ +#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ +#define KPAD_ROWEN 0x1c00 /* Row Enable Width */ +#define KPAD_COLEN 0xe000 /* Column Enable Width */ + +/* Bit masks for KPAD_PRESCALE */ + +#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */ + +/* Bit masks for KPAD_MSEL */ + +#define DBON_SCALE 0xff /* Debounce Scale Value */ +#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */ + +/* Bit masks for KPAD_ROWCOL */ + +#define KPAD_ROW 0xff /* Rows Pressed */ +#define KPAD_COL 0xff00 /* Columns Pressed */ + +/* Bit masks for KPAD_STAT */ + +#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ +#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ +#define KPAD_PRESSED 0x8 /* Key press current status */ + +/* Bit masks for KPAD_SOFTEVAL */ + +#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ + +/* Bit masks for SDH_COMMAND */ + +#define CMD_IDX 0x3f /* Command Index */ +#define CMD_RSP 0x40 /* Response */ +#define CMD_L_RSP 0x80 /* Long Response */ +#define CMD_INT_E 0x100 /* Command Interrupt */ +#define CMD_PEND_E 0x200 /* Command Pending */ +#define CMD_E 0x400 /* Command Enable */ + +/* Bit masks for SDH_PWR_CTL */ + +#define PWR_ON 0x3 /* Power On */ +#if 0 +#define TBD 0x3c /* TBD */ +#endif +#define SD_CMD_OD 0x40 /* Open Drain Output */ +#define ROD_CTL 0x80 /* Rod Control */ + +/* Bit masks for SDH_CLK_CTL */ + +#define CLKDIV 0xff /* MC_CLK Divisor */ +#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ +#define PWR_SV_E 0x200 /* Power Save Enable */ +#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ +#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ + +/* Bit masks for SDH_RESP_CMD */ + +#define RESP_CMD 0x3f /* Response Command */ + +/* Bit masks for SDH_DATA_CTL */ + +#define DTX_E 0x1 /* Data Transfer Enable */ +#define DTX_DIR 0x2 /* Data Transfer Direction */ +#define DTX_MODE 0x4 /* Data Transfer Mode */ +#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ +#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ + +/* Bit masks for SDH_STATUS */ + +#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ +#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ +#define CMD_TIME_OUT 0x4 /* CMD Time Out */ +#define DAT_TIME_OUT 0x8 /* Data Time Out */ +#define TX_UNDERRUN 0x10 /* Transmit Underrun */ +#define RX_OVERRUN 0x20 /* Receive Overrun */ +#define CMD_RESP_END 0x40 /* CMD Response End */ +#define CMD_SENT 0x80 /* CMD Sent */ +#define DAT_END 0x100 /* Data End */ +#define START_BIT_ERR 0x200 /* Start Bit Error */ +#define DAT_BLK_END 0x400 /* Data Block End */ +#define CMD_ACT 0x800 /* CMD Active */ +#define TX_ACT 0x1000 /* Transmit Active */ +#define RX_ACT 0x2000 /* Receive Active */ +#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ +#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ +#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ +#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ +#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ +#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ +#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ +#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ + +/* Bit masks for SDH_STATUS_CLR */ + +#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ +#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ +#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ +#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ +#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ +#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ +#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ +#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ +#define DAT_END_STAT 0x100 /* Data End Status */ +#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ +#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ + +/* Bit masks for SDH_MASK0 */ + +#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ +#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ +#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ +#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ +#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ +#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ +#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ +#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ +#define DAT_END_MASK 0x100 /* Data End Mask */ +#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ +#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ +#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ +#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ +#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ +#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ +#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ +#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ +#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ +#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ +#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ +#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ +#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ + +/* Bit masks for SDH_FIFO_CNT */ + +#define FIFO_COUNT 0x7fff /* FIFO Count */ + +/* Bit masks for SDH_E_STATUS */ + +#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ +#define SD_CARD_DET 0x10 /* SD Card Detect */ + +/* Bit masks for SDH_E_MASK */ + +#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ +#define SCD_MSK 0x40 /* Mask Card Detect */ + +/* Bit masks for SDH_CFG */ + +#define CLKS_EN 0x1 /* Clocks Enable */ +#define SD4E 0x4 /* SDIO 4-Bit Enable */ +#define MWE 0x8 /* Moving Window Enable */ +#define SD_RST 0x10 /* SDMMC Reset */ +#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ +#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ +#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ + +/* Bit masks for SDH_RD_WAIT_EN */ + +#define RWR 0x1 /* Read Wait Request */ + +/* Bit masks for ATAPI_CONTROL */ + +#define PIO_START 0x1 /* Start PIO/Reg Op */ +#define MULTI_START 0x2 /* Start Multi-DMA Op */ +#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ +#define XFER_DIR 0x8 /* Transfer Direction */ +#define IORDY_EN 0x10 /* IORDY Enable */ +#define FIFO_FLUSH 0x20 /* Flush FIFOs */ +#define SOFT_RST 0x40 /* Soft Reset */ +#define DEV_RST 0x80 /* Device Reset */ +#define TFRCNT_RST 0x100 /* Trans Count Reset */ +#define END_ON_TERM 0x200 /* End/Terminate Select */ +#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ +#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ + +/* Bit masks for ATAPI_STATUS */ + +#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ +#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ +#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ +#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ + +/* Bit masks for ATAPI_DEV_ADDR */ + +#define DEV_ADDR 0x1f /* Device Address */ + +/* Bit masks for ATAPI_INT_MASK */ + +#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ +#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ +#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ +#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ +#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ +#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ +#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ +#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ +#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ + +/* Bit masks for ATAPI_INT_STATUS */ + +#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ +#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ +#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ +#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ +#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ +#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ +#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ +#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ +#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ + +/* Bit masks for ATAPI_LINE_STATUS */ + +#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ +#define ATAPI_DASP 0x2 /* Device dasp to host line status */ +#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ +#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ +#define ATAPI_ADDR 0x70 /* ATAPI address line status */ +#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ +#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ +#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ +#define ATAPI_DIORN 0x400 /* ATAPI read line status */ +#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_SM_STATE */ + +#define PIO_CSTATE 0xf /* PIO mode state machine current state */ +#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */ +#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */ +#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_TERMINATE */ + +#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ + +/* Bit masks for ATAPI_REG_TIM_0 */ + +#define T2_REG 0xff /* End of cycle time for register access transfers */ +#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */ + +/* Bit masks for ATAPI_PIO_TIM_0 */ + +#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */ +#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */ +#define T4_REG 0xf000 /* DIOW data hold */ + +/* Bit masks for ATAPI_PIO_TIM_1 */ + +#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */ + +/* Bit masks for ATAPI_MULTI_TIM_0 */ + +#define TD 0xff /* DIOR/DIOW asserted pulsewidth */ +#define TM 0xff00 /* Time from address valid to DIOR/DIOW */ + +/* Bit masks for ATAPI_MULTI_TIM_1 */ + +#define TKW 0xff /* Selects DIOW negated pulsewidth */ +#define TKR 0xff00 /* Selects DIOR negated pulsewidth */ + +/* Bit masks for ATAPI_MULTI_TIM_2 */ + +#define TH 0xff /* Selects DIOW data hold */ +#define TEOC 0xff00 /* Selects end of cycle for DMA */ + +/* Bit masks for ATAPI_ULTRA_TIM_0 */ + +#define TACK 0xff /* Selects setup and hold times for TACK */ +#define TENV 0xff00 /* Selects envelope time */ + +/* Bit masks for ATAPI_ULTRA_TIM_1 */ + +#define TDVS 0xff /* Selects data valid setup time */ +#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */ + +/* Bit masks for ATAPI_ULTRA_TIM_2 */ + +#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */ +#define TMLI 0xff00 /* Selects interlock time */ + +/* Bit masks for ATAPI_ULTRA_TIM_3 */ + +#define TZAH 0xff /* Selects minimum delay required for output */ +#define READY_PAUSE 0xff00 /* Selects ready to pause */ + +/* Bit masks for TIMER_ENABLE1 */ + +#define TIMEN8 0x1 /* Timer 8 Enable */ +#define TIMEN9 0x2 /* Timer 9 Enable */ +#define TIMEN10 0x4 /* Timer 10 Enable */ + +/* Bit masks for TIMER_DISABLE1 */ + +#define TIMDIS8 0x1 /* Timer 8 Disable */ +#define TIMDIS9 0x2 /* Timer 9 Disable */ +#define TIMDIS10 0x4 /* Timer 10 Disable */ + +/* Bit masks for TIMER_STATUS1 */ + +#define TIMIL8 0x1 /* Timer 8 Interrupt */ +#define TIMIL9 0x2 /* Timer 9 Interrupt */ +#define TIMIL10 0x4 /* Timer 10 Interrupt */ +#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ +#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ +#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ +#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ +#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ +#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ + +/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ + +/* Bit masks for USB_FADDR */ + +#define FUNCTION_ADDRESS 0x7f /* Function address */ + +/* Bit masks for USB_POWER */ + +#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ +#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ +#define RESUME_MODE 0x4 /* DMA Mode */ +#define RESET 0x8 /* Reset indicator */ +#define HS_MODE 0x10 /* High Speed mode indicator */ +#define HS_ENABLE 0x20 /* high Speed Enable */ +#define SOFT_CONN 0x40 /* Soft connect */ +#define ISO_UPDATE 0x80 /* Isochronous update */ + +/* Bit masks for USB_INTRTX */ + +#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ +#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ +#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ +#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ +#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ +#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ +#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ +#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ + +/* Bit masks for USB_INTRRX */ + +#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ +#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ +#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ +#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ +#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ +#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ +#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ + +/* Bit masks for USB_INTRTXE */ + +#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ +#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ +#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ +#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ +#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ +#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ +#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ +#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ + +/* Bit masks for USB_INTRRXE */ + +#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ +#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ +#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ +#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ +#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ +#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ +#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ + +/* Bit masks for USB_INTRUSB */ + +#define SUSPEND_B 0x1 /* Suspend indicator */ +#define RESUME_B 0x2 /* Resume indicator */ +#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ +#define SOF_B 0x8 /* Start of frame */ +#define CONN_B 0x10 /* Connection indicator */ +#define DISCON_B 0x20 /* Disconnect indicator */ +#define SESSION_REQ_B 0x40 /* Session Request */ +#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ + +/* Bit masks for USB_INTRUSBE */ + +#define SUSPEND_BE 0x1 /* Suspend indicator int enable */ +#define RESUME_BE 0x2 /* Resume indicator int enable */ +#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ +#define SOF_BE 0x8 /* Start of frame int enable */ +#define CONN_BE 0x10 /* Connection indicator int enable */ +#define DISCON_BE 0x20 /* Disconnect indicator int enable */ +#define SESSION_REQ_BE 0x40 /* Session Request int enable */ +#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ + +/* Bit masks for USB_FRAME */ + +#define FRAME_NUMBER 0x7ff /* Frame number */ + +/* Bit masks for USB_INDEX */ + +#define SELECTED_ENDPOINT 0xf /* selected endpoint */ + +/* Bit masks for USB_GLOBAL_CTL */ + +#define GLOBAL_ENA 0x1 /* enables USB module */ +#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ +#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ +#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ +#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ +#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ +#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ +#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ +#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ +#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ +#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ +#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ +#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ +#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ +#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ + +/* Bit masks for USB_OTG_DEV_CTL */ + +#define SESSION 0x1 /* session indicator */ +#define HOST_REQ 0x2 /* Host negotiation request */ +#define HOST_MODE 0x4 /* indicates USBDRC is a host */ +#define VBUS0 0x8 /* Vbus level indicator[0] */ +#define VBUS1 0x10 /* Vbus level indicator[1] */ +#define LSDEV 0x20 /* Low-speed indicator */ +#define FSDEV 0x40 /* Full or High-speed indicator */ +#define B_DEVICE 0x80 /* A' or 'B' device indicator */ + +/* Bit masks for USB_OTG_VBUS_IRQ */ + +#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ +#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ +#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ +#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ +#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ +#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ + +/* Bit masks for USB_OTG_VBUS_MASK */ + +#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ +#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ +#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ +#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ +#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ +#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ + +/* Bit masks for USB_CSR0 */ + +#define RXPKTRDY 0x1 /* data packet receive indicator */ +#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ +#define STALL_SENT 0x4 /* STALL handshake sent */ +#define DATAEND 0x8 /* Data end indicator */ +#define SETUPEND 0x10 /* Setup end */ +#define SENDSTALL 0x20 /* Send STALL handshake */ +#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ +#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ +#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ +#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ +#define SETUPPKT_H 0x8 /* send Setup token host mode */ +#define ERROR_H 0x10 /* timeout error indicator host mode */ +#define REQPKT_H 0x20 /* Request an IN transaction host mode */ +#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ +#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ + +/* Bit masks for USB_COUNT0 */ + +#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ + +/* Bit masks for USB_NAKLIMIT0 */ + +#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ + +/* Bit masks for USB_TX_MAX_PACKET */ + +#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ + +/* Bit masks for USB_RX_MAX_PACKET */ + +#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ + +/* Bit masks for USB_TXCSR */ + +#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ +#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ +#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ +#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ +#define STALL_SEND_T 0x10 /* issue a Stall handshake */ +#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ +#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ +#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ +#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ +#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ +#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ +#define ISO_T 0x4000 /* enable Isochronous transfers */ +#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ +#define ERROR_TH 0x4 /* error condition host mode */ +#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ +#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ + +/* Bit masks for USB_TXCOUNT */ + +#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ + +/* Bit masks for USB_RXCSR */ + +#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ +#define FIFO_FULL_R 0x2 /* FIFO not empty */ +#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ +#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ +#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ +#define STALL_SEND_R 0x20 /* issue a Stall handshake */ +#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ +#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ +#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ +#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ +#define DISNYET_R 0x1000 /* disable Nyet handshakes */ +#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ +#define ISO_R 0x4000 /* enable Isochronous transfers */ +#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ +#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ +#define REQPKT_RH 0x20 /* request an IN transaction host mode */ +#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ +#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ +#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ +#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ + +/* Bit masks for USB_RXCOUNT */ + +#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ + +/* Bit masks for USB_TXTYPE */ + +#define TARGET_EP_NO_T 0xf /* EP number */ +#define PROTOCOL_T 0xc /* transfer type */ + +/* Bit masks for USB_TXINTERVAL */ + +#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ + +/* Bit masks for USB_RXTYPE */ + +#define TARGET_EP_NO_R 0xf /* EP number */ +#define PROTOCOL_R 0xc /* transfer type */ + +/* Bit masks for USB_RXINTERVAL */ + +#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ + +/* Bit masks for USB_DMA_INTERRUPT */ + +#define DMA0_INT 0x1 /* DMA0 pending interrupt */ +#define DMA1_INT 0x2 /* DMA1 pending interrupt */ +#define DMA2_INT 0x4 /* DMA2 pending interrupt */ +#define DMA3_INT 0x8 /* DMA3 pending interrupt */ +#define DMA4_INT 0x10 /* DMA4 pending interrupt */ +#define DMA5_INT 0x20 /* DMA5 pending interrupt */ +#define DMA6_INT 0x40 /* DMA6 pending interrupt */ +#define DMA7_INT 0x80 /* DMA7 pending interrupt */ + +/* Bit masks for USB_DMAxCONTROL */ + +#define DMA_ENA 0x1 /* DMA enable */ +#define DIRECTION 0x2 /* direction of DMA transfer */ +#define MODE 0x4 /* DMA Bus error */ +#define INT_ENA 0x8 /* Interrupt enable */ +#define EPNUM 0xf0 /* EP number */ +#define BUSERROR 0x100 /* DMA Bus error */ + +/* Bit masks for USB_DMAxADDRHIGH */ + +#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ + +/* Bit masks for USB_DMAxADDRLOW */ + +#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ + +/* Bit masks for USB_DMAxCOUNTHIGH */ + +#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ + +/* Bit masks for USB_DMAxCOUNTLOW */ + +#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ + +/* Bit masks for HMDMAx_CONTROL */ + +#define HMDMAEN 0x1 /* Handshake MDMA Enable */ +#define REP 0x2 /* Handshake MDMA Request Polarity */ +#define UTE 0x8 /* Urgency Threshold Enable */ +#define OIE 0x10 /* Overflow Interrupt Enable */ +#define BDIE 0x20 /* Block Done Interrupt Enable */ +#define MBDI 0x40 /* Mask Block Done Interrupt */ +#define DRQ 0x300 /* Handshake MDMA Request Type */ +#define RBC 0x1000 /* Force Reload of BCOUNT */ +#define PS 0x2000 /* Pin Status */ +#define OI 0x4000 /* Overflow Interrupt Generated */ +#define BDI 0x8000 /* Block Done Interrupt Generated */ + +/* ******************************************* */ +/* MULTI BIT MACRO ENUMERATIONS */ +/* ******************************************* */ + + +#endif /* _DEF_BF548_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/defBF549.h b/arch/blackfin/mach-bf548/include/mach/defBF549.h new file mode 100644 index 000000000000..096734541644 --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/defBF549.h @@ -0,0 +1,2737 @@ +/* + * File: include/asm-blackfin/mach-bf548/defBF549.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _DEF_BF549_H +#define _DEF_BF549_H + +/* Include all Core registers and bit definitions */ +#include <asm/def_LPBlackfin.h> + + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */ + +/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ +#include "defBF54x_base.h" + +/* The following are the #defines needed by ADSP-BF549 that are not in the common header */ + +/* Timer Registers */ + +#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */ +#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */ +#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */ +#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */ +#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */ +#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */ +#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */ +#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */ +#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */ +#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */ +#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */ +#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */ + +/* Timer Group of 3 Registers */ + +#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */ +#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */ +#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */ + +/* SPORT0 Registers */ + +#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */ +#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */ +#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */ +#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */ +#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */ +#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */ +#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */ +#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */ +#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */ +#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */ +#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */ +#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */ +#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */ +#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */ +#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */ +#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */ +#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */ +#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */ +#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */ +#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */ + +/* EPPI0 Registers */ + +#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */ +#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */ +#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */ +#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */ +#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */ +#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */ +#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */ +#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */ +#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */ +#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ +#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ +#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ +#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ +#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */ + +/* UART2 Registers */ + +#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */ +#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */ +#define UART2_GCTL 0xffc02108 /* Global Control Register */ +#define UART2_LCR 0xffc0210c /* Line Control Register */ +#define UART2_MCR 0xffc02110 /* Modem Control Register */ +#define UART2_LSR 0xffc02114 /* Line Status Register */ +#define UART2_MSR 0xffc02118 /* Modem Status Register */ +#define UART2_SCR 0xffc0211c /* Scratch Register */ +#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */ +#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */ +#define UART2_RBR 0xffc0212c /* Receive Buffer Register */ + +/* Two Wire Interface Registers (TWI1) */ + +#define TWI1_REGBASE 0xffc02200 +#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ +#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ +#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ +#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ +#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ +#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */ +#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ +#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ +#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ +#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ +#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */ +#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ +#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ +#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ +#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */ +#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */ + +/* SPI2 Registers */ + +#define SPI2_REGBASE 0xffc02400 +#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ +#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ +#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ +#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */ +#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */ +#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */ +#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */ + +/* MXVR Registers */ + +#define MXVR_CONFIG 0xffc02700 /* MXVR Configuration Register */ +#define MXVR_STATE_0 0xffc02708 /* MXVR State Register 0 */ +#define MXVR_STATE_1 0xffc0270c /* MXVR State Register 1 */ +#define MXVR_INT_STAT_0 0xffc02710 /* MXVR Interrupt Status Register 0 */ +#define MXVR_INT_STAT_1 0xffc02714 /* MXVR Interrupt Status Register 1 */ +#define MXVR_INT_EN_0 0xffc02718 /* MXVR Interrupt Enable Register 0 */ +#define MXVR_INT_EN_1 0xffc0271c /* MXVR Interrupt Enable Register 1 */ +#define MXVR_POSITION 0xffc02720 /* MXVR Node Position Register */ +#define MXVR_MAX_POSITION 0xffc02724 /* MXVR Maximum Node Position Register */ +#define MXVR_DELAY 0xffc02728 /* MXVR Node Frame Delay Register */ +#define MXVR_MAX_DELAY 0xffc0272c /* MXVR Maximum Node Frame Delay Register */ +#define MXVR_LADDR 0xffc02730 /* MXVR Logical Address Register */ +#define MXVR_GADDR 0xffc02734 /* MXVR Group Address Register */ +#define MXVR_AADDR 0xffc02738 /* MXVR Alternate Address Register */ + +/* MXVR Allocation Table Registers */ + +#define MXVR_ALLOC_0 0xffc0273c /* MXVR Allocation Table Register 0 */ +#define MXVR_ALLOC_1 0xffc02740 /* MXVR Allocation Table Register 1 */ +#define MXVR_ALLOC_2 0xffc02744 /* MXVR Allocation Table Register 2 */ +#define MXVR_ALLOC_3 0xffc02748 /* MXVR Allocation Table Register 3 */ +#define MXVR_ALLOC_4 0xffc0274c /* MXVR Allocation Table Register 4 */ +#define MXVR_ALLOC_5 0xffc02750 /* MXVR Allocation Table Register 5 */ +#define MXVR_ALLOC_6 0xffc02754 /* MXVR Allocation Table Register 6 */ +#define MXVR_ALLOC_7 0xffc02758 /* MXVR Allocation Table Register 7 */ +#define MXVR_ALLOC_8 0xffc0275c /* MXVR Allocation Table Register 8 */ +#define MXVR_ALLOC_9 0xffc02760 /* MXVR Allocation Table Register 9 */ +#define MXVR_ALLOC_10 0xffc02764 /* MXVR Allocation Table Register 10 */ +#define MXVR_ALLOC_11 0xffc02768 /* MXVR Allocation Table Register 11 */ +#define MXVR_ALLOC_12 0xffc0276c /* MXVR Allocation Table Register 12 */ +#define MXVR_ALLOC_13 0xffc02770 /* MXVR Allocation Table Register 13 */ +#define MXVR_ALLOC_14 0xffc02774 /* MXVR Allocation Table Register 14 */ + +/* MXVR Channel Assign Registers */ + +#define MXVR_SYNC_LCHAN_0 0xffc02778 /* MXVR Sync Data Logical Channel Assign Register 0 */ +#define MXVR_SYNC_LCHAN_1 0xffc0277c /* MXVR Sync Data Logical Channel Assign Register 1 */ +#define MXVR_SYNC_LCHAN_2 0xffc02780 /* MXVR Sync Data Logical Channel Assign Register 2 */ +#define MXVR_SYNC_LCHAN_3 0xffc02784 /* MXVR Sync Data Logical Channel Assign Register 3 */ +#define MXVR_SYNC_LCHAN_4 0xffc02788 /* MXVR Sync Data Logical Channel Assign Register 4 */ +#define MXVR_SYNC_LCHAN_5 0xffc0278c /* MXVR Sync Data Logical Channel Assign Register 5 */ +#define MXVR_SYNC_LCHAN_6 0xffc02790 /* MXVR Sync Data Logical Channel Assign Register 6 */ +#define MXVR_SYNC_LCHAN_7 0xffc02794 /* MXVR Sync Data Logical Channel Assign Register 7 */ + +/* MXVR DMA0 Registers */ + +#define MXVR_DMA0_CONFIG 0xffc02798 /* MXVR Sync Data DMA0 Config Register */ +#define MXVR_DMA0_START_ADDR 0xffc0279c /* MXVR Sync Data DMA0 Start Address */ +#define MXVR_DMA0_COUNT 0xffc027a0 /* MXVR Sync Data DMA0 Loop Count Register */ +#define MXVR_DMA0_CURR_ADDR 0xffc027a4 /* MXVR Sync Data DMA0 Current Address */ +#define MXVR_DMA0_CURR_COUNT 0xffc027a8 /* MXVR Sync Data DMA0 Current Loop Count */ + +/* MXVR DMA1 Registers */ + +#define MXVR_DMA1_CONFIG 0xffc027ac /* MXVR Sync Data DMA1 Config Register */ +#define MXVR_DMA1_START_ADDR 0xffc027b0 /* MXVR Sync Data DMA1 Start Address */ +#define MXVR_DMA1_COUNT 0xffc027b4 /* MXVR Sync Data DMA1 Loop Count Register */ +#define MXVR_DMA1_CURR_ADDR 0xffc027b8 /* MXVR Sync Data DMA1 Current Address */ +#define MXVR_DMA1_CURR_COUNT 0xffc027bc /* MXVR Sync Data DMA1 Current Loop Count */ + +/* MXVR DMA2 Registers */ + +#define MXVR_DMA2_CONFIG 0xffc027c0 /* MXVR Sync Data DMA2 Config Register */ +#define MXVR_DMA2_START_ADDR 0xffc027c4 /* MXVR Sync Data DMA2 Start Address */ +#define MXVR_DMA2_COUNT 0xffc027c8 /* MXVR Sync Data DMA2 Loop Count Register */ +#define MXVR_DMA2_CURR_ADDR 0xffc027cc /* MXVR Sync Data DMA2 Current Address */ +#define MXVR_DMA2_CURR_COUNT 0xffc027d0 /* MXVR Sync Data DMA2 Current Loop Count */ + +/* MXVR DMA3 Registers */ + +#define MXVR_DMA3_CONFIG 0xffc027d4 /* MXVR Sync Data DMA3 Config Register */ +#define MXVR_DMA3_START_ADDR 0xffc027d8 /* MXVR Sync Data DMA3 Start Address */ +#define MXVR_DMA3_COUNT 0xffc027dc /* MXVR Sync Data DMA3 Loop Count Register */ +#define MXVR_DMA3_CURR_ADDR 0xffc027e0 /* MXVR Sync Data DMA3 Current Address */ +#define MXVR_DMA3_CURR_COUNT 0xffc027e4 /* MXVR Sync Data DMA3 Current Loop Count */ + +/* MXVR DMA4 Registers */ + +#define MXVR_DMA4_CONFIG 0xffc027e8 /* MXVR Sync Data DMA4 Config Register */ +#define MXVR_DMA4_START_ADDR 0xffc027ec /* MXVR Sync Data DMA4 Start Address */ +#define MXVR_DMA4_COUNT 0xffc027f0 /* MXVR Sync Data DMA4 Loop Count Register */ +#define MXVR_DMA4_CURR_ADDR 0xffc027f4 /* MXVR Sync Data DMA4 Current Address */ +#define MXVR_DMA4_CURR_COUNT 0xffc027f8 /* MXVR Sync Data DMA4 Current Loop Count */ + +/* MXVR DMA5 Registers */ + +#define MXVR_DMA5_CONFIG 0xffc027fc /* MXVR Sync Data DMA5 Config Register */ +#define MXVR_DMA5_START_ADDR 0xffc02800 /* MXVR Sync Data DMA5 Start Address */ +#define MXVR_DMA5_COUNT 0xffc02804 /* MXVR Sync Data DMA5 Loop Count Register */ +#define MXVR_DMA5_CURR_ADDR 0xffc02808 /* MXVR Sync Data DMA5 Current Address */ +#define MXVR_DMA5_CURR_COUNT 0xffc0280c /* MXVR Sync Data DMA5 Current Loop Count */ + +/* MXVR DMA6 Registers */ + +#define MXVR_DMA6_CONFIG 0xffc02810 /* MXVR Sync Data DMA6 Config Register */ +#define MXVR_DMA6_START_ADDR 0xffc02814 /* MXVR Sync Data DMA6 Start Address */ +#define MXVR_DMA6_COUNT 0xffc02818 /* MXVR Sync Data DMA6 Loop Count Register */ +#define MXVR_DMA6_CURR_ADDR 0xffc0281c /* MXVR Sync Data DMA6 Current Address */ +#define MXVR_DMA6_CURR_COUNT 0xffc02820 /* MXVR Sync Data DMA6 Current Loop Count */ + +/* MXVR DMA7 Registers */ + +#define MXVR_DMA7_CONFIG 0xffc02824 /* MXVR Sync Data DMA7 Config Register */ +#define MXVR_DMA7_START_ADDR 0xffc02828 /* MXVR Sync Data DMA7 Start Address */ +#define MXVR_DMA7_COUNT 0xffc0282c /* MXVR Sync Data DMA7 Loop Count Register */ +#define MXVR_DMA7_CURR_ADDR 0xffc02830 /* MXVR Sync Data DMA7 Current Address */ +#define MXVR_DMA7_CURR_COUNT 0xffc02834 /* MXVR Sync Data DMA7 Current Loop Count */ + +/* MXVR Asynch Packet Registers */ + +#define MXVR_AP_CTL 0xffc02838 /* MXVR Async Packet Control Register */ +#define MXVR_APRB_START_ADDR 0xffc0283c /* MXVR Async Packet RX Buffer Start Addr Register */ +#define MXVR_APRB_CURR_ADDR 0xffc02840 /* MXVR Async Packet RX Buffer Current Addr Register */ +#define MXVR_APTB_START_ADDR 0xffc02844 /* MXVR Async Packet TX Buffer Start Addr Register */ +#define MXVR_APTB_CURR_ADDR 0xffc02848 /* MXVR Async Packet TX Buffer Current Addr Register */ + +/* MXVR Control Message Registers */ + +#define MXVR_CM_CTL 0xffc0284c /* MXVR Control Message Control Register */ +#define MXVR_CMRB_START_ADDR 0xffc02850 /* MXVR Control Message RX Buffer Start Addr Register */ +#define MXVR_CMRB_CURR_ADDR 0xffc02854 /* MXVR Control Message RX Buffer Current Address */ +#define MXVR_CMTB_START_ADDR 0xffc02858 /* MXVR Control Message TX Buffer Start Addr Register */ +#define MXVR_CMTB_CURR_ADDR 0xffc0285c /* MXVR Control Message TX Buffer Current Address */ + +/* MXVR Remote Read Registers */ + +#define MXVR_RRDB_START_ADDR 0xffc02860 /* MXVR Remote Read Buffer Start Addr Register */ +#define MXVR_RRDB_CURR_ADDR 0xffc02864 /* MXVR Remote Read Buffer Current Addr Register */ + +/* MXVR Pattern Data Registers */ + +#define MXVR_PAT_DATA_0 0xffc02868 /* MXVR Pattern Data Register 0 */ +#define MXVR_PAT_EN_0 0xffc0286c /* MXVR Pattern Enable Register 0 */ +#define MXVR_PAT_DATA_1 0xffc02870 /* MXVR Pattern Data Register 1 */ +#define MXVR_PAT_EN_1 0xffc02874 /* MXVR Pattern Enable Register 1 */ + +/* MXVR Frame Counter Registers */ + +#define MXVR_FRAME_CNT_0 0xffc02878 /* MXVR Frame Counter 0 */ +#define MXVR_FRAME_CNT_1 0xffc0287c /* MXVR Frame Counter 1 */ + +/* MXVR Routing Table Registers */ + +#define MXVR_ROUTING_0 0xffc02880 /* MXVR Routing Table Register 0 */ +#define MXVR_ROUTING_1 0xffc02884 /* MXVR Routing Table Register 1 */ +#define MXVR_ROUTING_2 0xffc02888 /* MXVR Routing Table Register 2 */ +#define MXVR_ROUTING_3 0xffc0288c /* MXVR Routing Table Register 3 */ +#define MXVR_ROUTING_4 0xffc02890 /* MXVR Routing Table Register 4 */ +#define MXVR_ROUTING_5 0xffc02894 /* MXVR Routing Table Register 5 */ +#define MXVR_ROUTING_6 0xffc02898 /* MXVR Routing Table Register 6 */ +#define MXVR_ROUTING_7 0xffc0289c /* MXVR Routing Table Register 7 */ +#define MXVR_ROUTING_8 0xffc028a0 /* MXVR Routing Table Register 8 */ +#define MXVR_ROUTING_9 0xffc028a4 /* MXVR Routing Table Register 9 */ +#define MXVR_ROUTING_10 0xffc028a8 /* MXVR Routing Table Register 10 */ +#define MXVR_ROUTING_11 0xffc028ac /* MXVR Routing Table Register 11 */ +#define MXVR_ROUTING_12 0xffc028b0 /* MXVR Routing Table Register 12 */ +#define MXVR_ROUTING_13 0xffc028b4 /* MXVR Routing Table Register 13 */ +#define MXVR_ROUTING_14 0xffc028b8 /* MXVR Routing Table Register 14 */ + +/* MXVR Counter-Clock-Control Registers */ + +#define MXVR_BLOCK_CNT 0xffc028c0 /* MXVR Block Counter */ +#define MXVR_CLK_CTL 0xffc028d0 /* MXVR Clock Control Register */ +#define MXVR_CDRPLL_CTL 0xffc028d4 /* MXVR Clock/Data Recovery PLL Control Register */ +#define MXVR_FMPLL_CTL 0xffc028d8 /* MXVR Frequency Multiply PLL Control Register */ +#define MXVR_PIN_CTL 0xffc028dc /* MXVR Pin Control Register */ +#define MXVR_SCLK_CNT 0xffc028e0 /* MXVR System Clock Counter Register */ + +/* CAN Controller 1 Config 1 Registers */ + +#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */ +#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */ +#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */ +#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */ +#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */ +#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */ +#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */ +#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */ +#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */ +#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */ +#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */ +#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */ +#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */ + +/* CAN Controller 1 Config 2 Registers */ + +#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */ +#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */ +#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */ +#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */ +#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */ +#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */ +#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */ +#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */ +#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */ +#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */ +#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */ +#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */ +#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */ + +/* CAN Controller 1 Clock/Interrupt/Counter Registers */ + +#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */ +#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */ +#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */ +#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */ +#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */ +#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */ +#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */ +#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */ +#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */ +#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */ +#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */ +#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */ +#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */ +#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */ +#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */ +#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */ + +/* CAN Controller 1 Mailbox Acceptance Registers */ + +#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */ +#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */ +#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */ +#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */ +#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */ +#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */ +#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */ +#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */ +#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */ +#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */ +#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */ +#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */ +#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */ +#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */ +#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */ +#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */ +#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */ +#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */ +#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */ +#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */ +#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */ +#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */ +#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */ +#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */ +#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */ +#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */ +#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */ +#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */ +#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */ +#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */ +#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */ +#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */ + +/* CAN Controller 1 Mailbox Acceptance Registers */ + +#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */ +#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */ +#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */ +#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */ +#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */ +#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */ +#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */ +#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */ +#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */ +#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */ +#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */ +#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */ +#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */ +#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */ +#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */ +#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */ +#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */ +#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */ +#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */ +#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */ +#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */ +#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */ +#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */ +#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */ +#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */ +#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */ +#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */ +#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */ +#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */ +#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */ +#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */ +#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */ + +/* CAN Controller 1 Mailbox Data Registers */ + +#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */ +#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */ +#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */ +#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */ +#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */ +#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */ +#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */ +#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */ +#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */ +#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */ +#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */ +#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */ +#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */ +#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */ +#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */ +#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */ +#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */ +#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */ +#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */ +#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */ +#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */ +#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */ +#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */ +#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */ +#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */ +#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */ +#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */ +#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */ +#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */ +#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */ +#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */ +#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */ +#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */ +#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */ +#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */ +#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */ +#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */ +#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */ +#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */ +#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */ +#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */ +#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */ +#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */ +#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */ +#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */ +#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */ +#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */ +#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */ +#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */ +#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */ +#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */ +#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */ +#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */ +#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */ +#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */ +#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */ +#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */ +#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */ +#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */ +#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */ +#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */ +#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */ +#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */ +#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */ +#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */ +#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */ +#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */ +#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */ +#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */ +#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */ +#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */ +#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */ +#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */ +#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */ +#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */ +#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */ +#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */ +#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */ +#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */ +#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */ +#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */ +#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */ +#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */ +#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */ +#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */ +#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */ +#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */ +#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */ +#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */ +#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */ +#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */ +#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */ +#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */ +#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */ +#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */ +#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */ +#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */ +#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */ +#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */ +#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */ +#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */ +#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */ +#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */ +#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */ +#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */ +#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */ +#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */ +#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */ +#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */ +#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */ +#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */ +#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */ +#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */ +#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */ +#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */ +#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */ +#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */ +#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */ +#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */ +#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */ +#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */ +#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */ +#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */ +#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */ +#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */ +#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */ +#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */ +#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */ + +/* CAN Controller 1 Mailbox Data Registers */ + +#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */ +#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */ +#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */ +#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */ +#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */ +#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */ +#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */ +#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */ +#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */ +#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */ +#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */ +#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */ +#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */ +#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */ +#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */ +#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */ +#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */ +#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */ +#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */ +#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */ +#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */ +#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */ +#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */ +#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */ +#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */ +#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */ +#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */ +#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */ +#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */ +#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */ +#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */ +#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */ +#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */ +#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */ +#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */ +#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */ +#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */ +#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */ +#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */ +#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */ +#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */ +#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */ +#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */ +#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */ +#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */ +#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */ +#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */ +#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */ +#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */ +#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */ +#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */ +#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */ +#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */ +#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */ +#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */ +#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */ +#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */ +#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */ +#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */ +#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */ +#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */ +#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */ +#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */ +#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */ +#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */ +#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */ +#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */ +#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */ +#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */ +#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */ +#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */ +#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */ +#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */ +#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */ +#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */ +#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */ +#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */ +#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */ +#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */ +#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */ +#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */ +#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */ +#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */ +#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */ +#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */ +#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */ +#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */ +#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */ +#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */ +#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */ +#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */ +#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */ +#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */ +#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */ +#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */ +#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */ +#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */ +#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */ +#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */ +#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */ +#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */ +#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */ +#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */ +#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */ +#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */ +#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */ +#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */ +#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */ +#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */ +#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */ +#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */ +#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */ +#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */ +#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */ +#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */ +#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */ +#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */ +#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */ +#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */ +#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */ +#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */ +#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */ +#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */ +#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */ +#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */ +#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */ +#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */ +#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */ + +/* ATAPI Registers */ + +#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */ +#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */ +#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */ +#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */ +#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */ +#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */ +#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */ +#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */ +#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */ +#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */ +#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */ +#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */ +#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */ +#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */ +#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */ +#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */ +#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */ +#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */ +#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */ +#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */ +#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */ +#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */ +#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */ +#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */ +#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */ + +/* SDH Registers */ + +#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */ +#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */ +#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */ +#define SDH_COMMAND 0xffc0390c /* SDH Command */ +#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */ +#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */ +#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */ +#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */ +#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */ +#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */ +#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */ +#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */ +#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */ +#define SDH_STATUS 0xffc03934 /* SDH Status */ +#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */ +#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */ +#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */ +#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */ +#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */ +#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */ +#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */ +#define SDH_CFG 0xffc039c8 /* SDH Configuration */ +#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */ +#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */ +#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */ +#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */ +#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */ +#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */ +#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */ +#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */ +#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */ + +/* HOST Port Registers */ + +#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */ +#define HOST_STATUS 0xffc03a04 /* HOST Status Register */ +#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */ + +/* USB Control Registers */ + +#define USB_FADDR 0xffc03c00 /* Function address register */ +#define USB_POWER 0xffc03c04 /* Power management register */ +#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ +#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */ +#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */ +#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */ +#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */ +#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */ +#define USB_FRAME 0xffc03c20 /* USB frame number */ +#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */ +#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */ +#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ +#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */ + +/* USB Packet Control Registers */ + +#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */ +#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ +#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ +#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */ +#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */ +#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ +#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ +#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ +#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ +#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ +#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ +#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ +#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */ + +/* USB Endpoint FIFO Registers */ + +#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */ +#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */ +#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */ +#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */ +#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */ +#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */ +#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */ +#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */ + +/* USB OTG Control Registers */ + +#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */ +#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */ +#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */ + +/* USB Phy Control Registers */ + +#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */ +#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */ +#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */ +#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */ +#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */ + +/* (APHY_CNTRL is for ADI usage only) */ + +#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */ + +/* (APHY_CALIB is for ADI usage only) */ + +#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */ +#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ + +/* (PHY_TEST is for ADI usage only) */ + +#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */ +#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */ +#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ + +/* USB Endpoint 0 Control Registers */ + +#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */ +#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */ +#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */ +#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */ +#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */ +#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ +#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */ +#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ +#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ + +/* USB Endpoint 1 Control Registers */ + +#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ +#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */ +#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */ +#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */ +#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */ +#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */ +#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ +#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */ +#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ +#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ + +/* USB Endpoint 2 Control Registers */ + +#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ +#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */ +#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */ +#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */ +#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */ +#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */ +#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ +#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */ +#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ +#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ + +/* USB Endpoint 3 Control Registers */ + +#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ +#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */ +#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */ +#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */ +#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */ +#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */ +#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ +#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */ +#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ +#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ + +/* USB Endpoint 4 Control Registers */ + +#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ +#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */ +#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */ +#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */ +#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */ +#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */ +#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ +#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */ +#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ +#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ + +/* USB Endpoint 5 Control Registers */ + +#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ +#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */ +#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */ +#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */ +#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */ +#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */ +#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ +#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */ +#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ +#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ + +/* USB Endpoint 6 Control Registers */ + +#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */ +#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */ +#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */ +#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */ +#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */ +#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */ +#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ +#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */ +#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ +#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ + +/* USB Endpoint 7 Control Registers */ + +#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ +#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */ +#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */ +#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */ +#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */ +#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */ +#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ +#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */ +#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ +#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ +#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ +#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */ + +/* USB Channel 0 Config Registers */ + +#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */ +#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ +#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ +#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ +#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ + +/* USB Channel 1 Config Registers */ + +#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */ +#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ +#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ +#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ +#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ + +/* USB Channel 2 Config Registers */ + +#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */ +#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ +#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ +#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ +#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ + +/* USB Channel 3 Config Registers */ + +#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */ +#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ +#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ +#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ +#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ + +/* USB Channel 4 Config Registers */ + +#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */ +#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ +#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ +#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ +#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ + +/* USB Channel 5 Config Registers */ + +#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */ +#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ +#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ +#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ +#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ + +/* USB Channel 6 Config Registers */ + +#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */ +#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ +#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ +#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ +#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ + +/* USB Channel 7 Config Registers */ + +#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */ +#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ +#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ +#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ +#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ + +/* Keypad Registers */ + +#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */ +#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */ +#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */ +#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */ +#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */ +#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */ + +/* Pixel Compositor (PIXC) Registers */ + +#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ +#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */ +#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */ +#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */ +#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */ +#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */ +#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */ +#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */ +#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */ +#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */ +#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */ +#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */ +#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */ +#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */ +#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ +#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */ +#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */ +#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */ +#define PIXC_TC 0xffc04450 /* Holds the transparent color value */ + +/* Handshake MDMA 0 Registers */ + +#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */ +#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */ +#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */ +#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ +#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ +#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */ +#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */ + +/* Handshake MDMA 1 Registers */ + +#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */ +#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */ +#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */ +#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ +#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ +#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */ +#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */ + + +/* ********************************************************** */ +/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ +/* and MULTI BIT READ MACROS */ +/* ********************************************************** */ + +/* Bit masks for PIXC_CTL */ + +#define PIXC_EN 0x1 /* Pixel Compositor Enable */ +#define OVR_A_EN 0x2 /* Overlay A Enable */ +#define OVR_B_EN 0x4 /* Overlay B Enable */ +#define IMG_FORM 0x8 /* Image Data Format */ +#define OVR_FORM 0x10 /* Overlay Data Format */ +#define OUT_FORM 0x20 /* Output Data Format */ +#define UDS_MOD 0x40 /* Resampling Mode */ +#define TC_EN 0x80 /* Transparent Color Enable */ +#define IMG_STAT 0x300 /* Image FIFO Status */ +#define OVR_STAT 0xc00 /* Overlay FIFO Status */ +#define WM_LVL 0x3000 /* FIFO Watermark Level */ + +/* Bit masks for PIXC_AHSTART */ + +#define A_HSTART 0xfff /* Horizontal Start Coordinates */ + +/* Bit masks for PIXC_AHEND */ + +#define A_HEND 0xfff /* Horizontal End Coordinates */ + +/* Bit masks for PIXC_AVSTART */ + +#define A_VSTART 0x3ff /* Vertical Start Coordinates */ + +/* Bit masks for PIXC_AVEND */ + +#define A_VEND 0x3ff /* Vertical End Coordinates */ + +/* Bit masks for PIXC_ATRANSP */ + +#define A_TRANSP 0xf /* Transparency Value */ + +/* Bit masks for PIXC_BHSTART */ + +#define B_HSTART 0xfff /* Horizontal Start Coordinates */ + +/* Bit masks for PIXC_BHEND */ + +#define B_HEND 0xfff /* Horizontal End Coordinates */ + +/* Bit masks for PIXC_BVSTART */ + +#define B_VSTART 0x3ff /* Vertical Start Coordinates */ + +/* Bit masks for PIXC_BVEND */ + +#define B_VEND 0x3ff /* Vertical End Coordinates */ + +/* Bit masks for PIXC_BTRANSP */ + +#define B_TRANSP 0xf /* Transparency Value */ + +/* Bit masks for PIXC_INTRSTAT */ + +#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ +#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ +#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ +#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ + +/* Bit masks for PIXC_RYCON */ + +#define A11 0x3ff /* A11 in the Coefficient Matrix */ +#define A12 0xffc00 /* A12 in the Coefficient Matrix */ +#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ +#define RY_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_GUCON */ + +#define A21 0x3ff /* A21 in the Coefficient Matrix */ +#define A22 0xffc00 /* A22 in the Coefficient Matrix */ +#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ +#define GU_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_BVCON */ + +#define A31 0x3ff /* A31 in the Coefficient Matrix */ +#define A32 0xffc00 /* A32 in the Coefficient Matrix */ +#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ +#define BV_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_CCBIAS */ + +#define A14 0x3ff /* A14 in the Bias Vector */ +#define A24 0xffc00 /* A24 in the Bias Vector */ +#define A34 0x3ff00000 /* A34 in the Bias Vector */ + +/* Bit masks for PIXC_TC */ + +#define RY_TRANS 0xff /* Transparent Color - R/Y Component */ +#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */ +#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */ + +/* Bit masks for HOST_CONTROL */ + +#define HOST_EN 0x1 /* Host Enable */ +#define HOST_END 0x2 /* Host Endianess */ +#define DATA_SIZE 0x4 /* Data Size */ +#define HOST_RST 0x8 /* Host Reset */ +#define HRDY_OVR 0x20 /* Host Ready Override */ +#define INT_MODE 0x40 /* Interrupt Mode */ +#define BT_EN 0x80 /* Bus Timeout Enable */ +#define EHW 0x100 /* Enable Host Write */ +#define EHR 0x200 /* Enable Host Read */ +#define BDR 0x400 /* Burst DMA Requests */ + +/* Bit masks for HOST_STATUS */ + +#define DMA_READY 0x1 /* DMA Ready */ +#define FIFOFULL 0x2 /* FIFO Full */ +#define FIFOEMPTY 0x4 /* FIFO Empty */ +#define DMA_COMPLETE 0x8 /* DMA Complete */ +#define HSHK 0x10 /* Host Handshake */ +#define TIMEOUT 0x20 /* Host Timeout */ +#define HIRQ 0x40 /* Host Interrupt Request */ +#define ALLOW_CNFG 0x80 /* Allow New Configuration */ +#define DMA_DIR 0x100 /* DMA Direction */ +#define BTE 0x200 /* Bus Timeout Enabled */ + +/* Bit masks for HOST_TIMEOUT */ + +#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */ + +/* Bit masks for MXVR_CONFIG */ + +#define MXVREN 0x1 /* MXVR Enable */ +#define MMSM 0x2 /* MXVR Master/Slave Mode Select */ +#define ACTIVE 0x4 /* Active Mode */ +#define SDELAY 0x8 /* Synchronous Data Delay */ +#define NCMRXEN 0x10 /* Normal Control Message Receive Enable */ +#define RWRRXEN 0x20 /* Remote Write Receive Enable */ +#define MTXEN 0x40 /* MXVR Transmit Data Enable */ +#define MTXONB 0x80 /* MXVR Phy Transmitter On */ +#define EPARITY 0x100 /* Even Parity Select */ +#define MSB 0x1e00 /* Master Synchronous Boundary */ +#define APRXEN 0x2000 /* Asynchronous Packet Receive Enable */ +#define WAKEUP 0x4000 /* Wake-Up */ +#define LMECH 0x8000 /* Lock Mechanism Select */ + +/* Bit masks for MXVR_STATE_0 */ + +#define NACT 0x1 /* Network Activity */ +#define SBLOCK 0x2 /* Super Block Lock */ +#define FMPLLST 0xc /* Frequency Multiply PLL SM State */ +#define CDRPLLST 0xe0 /* Clock/Data Recovery PLL SM State */ +#define APBSY 0x100 /* Asynchronous Packet Transmit Buffer Busy */ +#define APARB 0x200 /* Asynchronous Packet Arbitrating */ +#define APTX 0x400 /* Asynchronous Packet Transmitting */ +#define APRX 0x800 /* Receiving Asynchronous Packet */ +#define CMBSY 0x1000 /* Control Message Transmit Buffer Busy */ +#define CMARB 0x2000 /* Control Message Arbitrating */ +#define CMTX 0x4000 /* Control Message Transmitting */ +#define CMRX 0x8000 /* Receiving Control Message */ +#define MRXONB 0x10000 /* MRXONB Pin State */ +#define RGSIP 0x20000 /* Remote Get Source In Progress */ +#define DALIP 0x40000 /* Resource Deallocate In Progress */ +#define ALIP 0x80000 /* Resource Allocate In Progress */ +#define RRDIP 0x100000 /* Remote Read In Progress */ +#define RWRIP 0x200000 /* Remote Write In Progress */ +#define FLOCK 0x400000 /* Frame Lock */ +#define BLOCK 0x800000 /* Block Lock */ +#define RSB 0xf000000 /* Received Synchronous Boundary */ +#define DERRNUM 0xf0000000 /* DMA Error Channel Number */ + +/* Bit masks for MXVR_STATE_1 */ + +#define SRXNUMB 0xf /* Synchronous Receive FIFO Number of Bytes */ +#define STXNUMB 0xf0 /* Synchronous Transmit FIFO Number of Bytes */ +#define APCONT 0x100 /* Asynchronous Packet Continuation */ +#define OBERRNUM 0xe00 /* DMA Out of Bounds Error Channel Number */ +#define DMAACTIVE0 0x10000 /* DMA0 Active */ +#define DMAACTIVE1 0x20000 /* DMA1 Active */ +#define DMAACTIVE2 0x40000 /* DMA2 Active */ +#define DMAACTIVE3 0x80000 /* DMA3 Active */ +#define DMAACTIVE4 0x100000 /* DMA4 Active */ +#define DMAACTIVE5 0x200000 /* DMA5 Active */ +#define DMAACTIVE6 0x400000 /* DMA6 Active */ +#define DMAACTIVE7 0x800000 /* DMA7 Active */ +#define DMAPMEN0 0x1000000 /* DMA0 Pattern Matching Enabled */ +#define DMAPMEN1 0x2000000 /* DMA1 Pattern Matching Enabled */ +#define DMAPMEN2 0x4000000 /* DMA2 Pattern Matching Enabled */ +#define DMAPMEN3 0x8000000 /* DMA3 Pattern Matching Enabled */ +#define DMAPMEN4 0x10000000 /* DMA4 Pattern Matching Enabled */ +#define DMAPMEN5 0x20000000 /* DMA5 Pattern Matching Enabled */ +#define DMAPMEN6 0x40000000 /* DMA6 Pattern Matching Enabled */ +#define DMAPMEN7 0x80000000 /* DMA7 Pattern Matching Enabled */ + +/* Bit masks for MXVR_INT_STAT_0 */ + +#define NI2A 0x1 /* Network Inactive to Active */ +#define NA2I 0x2 /* Network Active to Inactive */ +#define SBU2L 0x4 /* Super Block Unlock to Lock */ +#define SBL2U 0x8 /* Super Block Lock to Unlock */ +#define PRU 0x10 /* Position Register Updated */ +#define MPRU 0x20 /* Maximum Position Register Updated */ +#define DRU 0x40 /* Delay Register Updated */ +#define MDRU 0x80 /* Maximum Delay Register Updated */ +#define SBU 0x100 /* Synchronous Boundary Updated */ +#define ATU 0x200 /* Allocation Table Updated */ +#define FCZ0 0x400 /* Frame Counter 0 Zero */ +#define FCZ1 0x800 /* Frame Counter 1 Zero */ +#define PERR 0x1000 /* Parity Error */ +#define MH2L 0x2000 /* MRXONB High to Low */ +#define ML2H 0x4000 /* MRXONB Low to High */ +#define WUP 0x8000 /* Wake-Up Preamble Received */ +#define FU2L 0x10000 /* Frame Unlock to Lock */ +#define FL2U 0x20000 /* Frame Lock to Unlock */ +#define BU2L 0x40000 /* Block Unlock to Lock */ +#define BL2U 0x80000 /* Block Lock to Unlock */ +#define OBERR 0x100000 /* DMA Out of Bounds Error */ +#define PFL 0x200000 /* PLL Frequency Locked */ +#define SCZ 0x400000 /* System Clock Counter Zero */ +#define FERR 0x800000 /* FIFO Error */ +#define CMR 0x1000000 /* Control Message Received */ +#define CMROF 0x2000000 /* Control Message Receive Buffer Overflow */ +#define CMTS 0x4000000 /* Control Message Transmit Buffer Successfully Sent */ +#define CMTC 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled */ +#define RWRC 0x10000000 /* Remote Write Control Message Completed */ +#define BCZ 0x20000000 /* Block Counter Zero */ +#define BMERR 0x40000000 /* Biphase Mark Coding Error */ +#define DERR 0x80000000 /* DMA Error */ + +/* Bit masks for MXVR_INT_STAT_1 */ + +#define HDONE0 0x1 /* DMA0 Half Done */ +#define DONE0 0x2 /* DMA0 Done */ +#define APR 0x4 /* Asynchronous Packet Received */ +#define APROF 0x8 /* Asynchronous Packet Receive Buffer Overflow */ +#define HDONE1 0x10 /* DMA1 Half Done */ +#define DONE1 0x20 /* DMA1 Done */ +#define APTS 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent */ +#define APTC 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled */ +#define HDONE2 0x100 /* DMA2 Half Done */ +#define DONE2 0x200 /* DMA2 Done */ +#define APRCE 0x400 /* Asynchronous Packet Receive CRC Error */ +#define APRPE 0x800 /* Asynchronous Packet Receive Packet Error */ +#define HDONE3 0x1000 /* DMA3 Half Done */ +#define DONE3 0x2000 /* DMA3 Done */ +#define HDONE4 0x10000 /* DMA4 Half Done */ +#define DONE4 0x20000 /* DMA4 Done */ +#define HDONE5 0x100000 /* DMA5 Half Done */ +#define DONE5 0x200000 /* DMA5 Done */ +#define HDONE6 0x1000000 /* DMA6 Half Done */ +#define DONE6 0x2000000 /* DMA6 Done */ +#define HDONE7 0x10000000 /* DMA7 Half Done */ +#define DONE7 0x20000000 /* DMA7 Done */ + +/* Bit masks for MXVR_INT_EN_0 */ + +#define NI2AEN 0x1 /* Network Inactive to Active Interrupt Enable */ +#define NA2IEN 0x2 /* Network Active to Inactive Interrupt Enable */ +#define SBU2LEN 0x4 /* Super Block Unlock to Lock Interrupt Enable */ +#define SBL2UEN 0x8 /* Super Block Lock to Unlock Interrupt Enable */ +#define PRUEN 0x10 /* Position Register Updated Interrupt Enable */ +#define MPRUEN 0x20 /* Maximum Position Register Updated Interrupt Enable */ +#define DRUEN 0x40 /* Delay Register Updated Interrupt Enable */ +#define MDRUEN 0x80 /* Maximum Delay Register Updated Interrupt Enable */ +#define SBUEN 0x100 /* Synchronous Boundary Updated Interrupt Enable */ +#define ATUEN 0x200 /* Allocation Table Updated Interrupt Enable */ +#define FCZ0EN 0x400 /* Frame Counter 0 Zero Interrupt Enable */ +#define FCZ1EN 0x800 /* Frame Counter 1 Zero Interrupt Enable */ +#define PERREN 0x1000 /* Parity Error Interrupt Enable */ +#define MH2LEN 0x2000 /* MRXONB High to Low Interrupt Enable */ +#define ML2HEN 0x4000 /* MRXONB Low to High Interrupt Enable */ +#define WUPEN 0x8000 /* Wake-Up Preamble Received Interrupt Enable */ +#define FU2LEN 0x10000 /* Frame Unlock to Lock Interrupt Enable */ +#define FL2UEN 0x20000 /* Frame Lock to Unlock Interrupt Enable */ +#define BU2LEN 0x40000 /* Block Unlock to Lock Interrupt Enable */ +#define BL2UEN 0x80000 /* Block Lock to Unlock Interrupt Enable */ +#define OBERREN 0x100000 /* DMA Out of Bounds Error Interrupt Enable */ +#define PFLEN 0x200000 /* PLL Frequency Locked Interrupt Enable */ +#define SCZEN 0x400000 /* System Clock Counter Zero Interrupt Enable */ +#define FERREN 0x800000 /* FIFO Error Interrupt Enable */ +#define CMREN 0x1000000 /* Control Message Received Interrupt Enable */ +#define CMROFEN 0x2000000 /* Control Message Receive Buffer Overflow Interrupt Enable */ +#define CMTSEN 0x4000000 /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */ +#define CMTCEN 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */ +#define RWRCEN 0x10000000 /* Remote Write Control Message Completed Interrupt Enable */ +#define BCZEN 0x20000000 /* Block Counter Zero Interrupt Enable */ +#define BMERREN 0x40000000 /* Biphase Mark Coding Error Interrupt Enable */ +#define DERREN 0x80000000 /* DMA Error Interrupt Enable */ + +/* Bit masks for MXVR_INT_EN_1 */ + +#define HDONEEN0 0x1 /* DMA0 Half Done Interrupt Enable */ +#define DONEEN0 0x2 /* DMA0 Done Interrupt Enable */ +#define APREN 0x4 /* Asynchronous Packet Received Interrupt Enable */ +#define APROFEN 0x8 /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */ +#define HDONEEN1 0x10 /* DMA1 Half Done Interrupt Enable */ +#define DONEEN1 0x20 /* DMA1 Done Interrupt Enable */ +#define APTSEN 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */ +#define APTCEN 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */ +#define HDONEEN2 0x100 /* DMA2 Half Done Interrupt Enable */ +#define DONEEN2 0x200 /* DMA2 Done Interrupt Enable */ +#define APRCEEN 0x400 /* Asynchronous Packet Receive CRC Error Interrupt Enable */ +#define APRPEEN 0x800 /* Asynchronous Packet Receive Packet Error Interrupt Enable */ +#define HDONEEN3 0x1000 /* DMA3 Half Done Interrupt Enable */ +#define DONEEN3 0x2000 /* DMA3 Done Interrupt Enable */ +#define HDONEEN4 0x10000 /* DMA4 Half Done Interrupt Enable */ +#define DONEEN4 0x20000 /* DMA4 Done Interrupt Enable */ +#define HDONEEN5 0x100000 /* DMA5 Half Done Interrupt Enable */ +#define DONEEN5 0x200000 /* DMA5 Done Interrupt Enable */ +#define HDONEEN6 0x1000000 /* DMA6 Half Done Interrupt Enable */ +#define DONEEN6 0x2000000 /* DMA6 Done Interrupt Enable */ +#define HDONEEN7 0x10000000 /* DMA7 Half Done Interrupt Enable */ +#define DONEEN7 0x20000000 /* DMA7 Done Interrupt Enable */ + +/* Bit masks for MXVR_POSITION */ + +#define POSITION 0x3f /* Node Position */ +#define PVALID 0x8000 /* Node Position Valid */ + +/* Bit masks for MXVR_MAX_POSITION */ + +#define MPOSITION 0x3f /* Maximum Node Position */ +#define MPVALID 0x8000 /* Maximum Node Position Valid */ + +/* Bit masks for MXVR_DELAY */ + +#define DELAY 0x3f /* Node Frame Delay */ +#define DVALID 0x8000 /* Node Frame Delay Valid */ + +/* Bit masks for MXVR_MAX_DELAY */ + +#define MDELAY 0x3f /* Maximum Node Frame Delay */ +#define MDVALID 0x8000 /* Maximum Node Frame Delay Valid */ + +/* Bit masks for MXVR_LADDR */ + +#define LADDR 0xffff /* Logical Address */ +#define LVALID 0x80000000 /* Logical Address Valid */ + +/* Bit masks for MXVR_GADDR */ + +#define GADDRL 0xff /* Group Address Lower Byte */ +#define GVALID 0x8000 /* Group Address Valid */ + +/* Bit masks for MXVR_AADDR */ + +#define AADDR 0xffff /* Alternate Address */ +#define AVALID 0x80000000 /* Alternate Address Valid */ + +/* Bit masks for MXVR_ALLOC_0 */ + +#define CL0 0x7f /* Channel 0 Connection Label */ +#define CIU0 0x80 /* Channel 0 In Use */ +#define CL1 0x7f00 /* Channel 0 Connection Label */ +#define CIU1 0x8000 /* Channel 0 In Use */ +#define CL2 0x7f0000 /* Channel 0 Connection Label */ +#define CIU2 0x800000 /* Channel 0 In Use */ +#define CL3 0x7f000000 /* Channel 0 Connection Label */ +#define CIU3 0x80000000 /* Channel 0 In Use */ + +/* Bit masks for MXVR_ALLOC_1 */ + +#define CL4 0x7f /* Channel 4 Connection Label */ +#define CIU4 0x80 /* Channel 4 In Use */ +#define CL5 0x7f00 /* Channel 5 Connection Label */ +#define CIU5 0x8000 /* Channel 5 In Use */ +#define CL6 0x7f0000 /* Channel 6 Connection Label */ +#define CIU6 0x800000 /* Channel 6 In Use */ +#define CL7 0x7f000000 /* Channel 7 Connection Label */ +#define CIU7 0x80000000 /* Channel 7 In Use */ + +/* Bit masks for MXVR_ALLOC_2 */ + +#define CL8 0x7f /* Channel 8 Connection Label */ +#define CIU8 0x80 /* Channel 8 In Use */ +#define CL9 0x7f00 /* Channel 9 Connection Label */ +#define CIU9 0x8000 /* Channel 9 In Use */ +#define CL10 0x7f0000 /* Channel 10 Connection Label */ +#define CIU10 0x800000 /* Channel 10 In Use */ +#define CL11 0x7f000000 /* Channel 11 Connection Label */ +#define CIU11 0x80000000 /* Channel 11 In Use */ + +/* Bit masks for MXVR_ALLOC_3 */ + +#define CL12 0x7f /* Channel 12 Connection Label */ +#define CIU12 0x80 /* Channel 12 In Use */ +#define CL13 0x7f00 /* Channel 13 Connection Label */ +#define CIU13 0x8000 /* Channel 13 In Use */ +#define CL14 0x7f0000 /* Channel 14 Connection Label */ +#define CIU14 0x800000 /* Channel 14 In Use */ +#define CL15 0x7f000000 /* Channel 15 Connection Label */ +#define CIU15 0x80000000 /* Channel 15 In Use */ + +/* Bit masks for MXVR_ALLOC_4 */ + +#define CL16 0x7f /* Channel 16 Connection Label */ +#define CIU16 0x80 /* Channel 16 In Use */ +#define CL17 0x7f00 /* Channel 17 Connection Label */ +#define CIU17 0x8000 /* Channel 17 In Use */ +#define CL18 0x7f0000 /* Channel 18 Connection Label */ +#define CIU18 0x800000 /* Channel 18 In Use */ +#define CL19 0x7f000000 /* Channel 19 Connection Label */ +#define CIU19 0x80000000 /* Channel 19 In Use */ + +/* Bit masks for MXVR_ALLOC_5 */ + +#define CL20 0x7f /* Channel 20 Connection Label */ +#define CIU20 0x80 /* Channel 20 In Use */ +#define CL21 0x7f00 /* Channel 21 Connection Label */ +#define CIU21 0x8000 /* Channel 21 In Use */ +#define CL22 0x7f0000 /* Channel 22 Connection Label */ +#define CIU22 0x800000 /* Channel 22 In Use */ +#define CL23 0x7f000000 /* Channel 23 Connection Label */ +#define CIU23 0x80000000 /* Channel 23 In Use */ + +/* Bit masks for MXVR_ALLOC_6 */ + +#define CL24 0x7f /* Channel 24 Connection Label */ +#define CIU24 0x80 /* Channel 24 In Use */ +#define CL25 0x7f00 /* Channel 25 Connection Label */ +#define CIU25 0x8000 /* Channel 25 In Use */ +#define CL26 0x7f0000 /* Channel 26 Connection Label */ +#define CIU26 0x800000 /* Channel 26 In Use */ +#define CL27 0x7f000000 /* Channel 27 Connection Label */ +#define CIU27 0x80000000 /* Channel 27 In Use */ + +/* Bit masks for MXVR_ALLOC_7 */ + +#define CL28 0x7f /* Channel 28 Connection Label */ +#define CIU28 0x80 /* Channel 28 In Use */ +#define CL29 0x7f00 /* Channel 29 Connection Label */ +#define CIU29 0x8000 /* Channel 29 In Use */ +#define CL30 0x7f0000 /* Channel 30 Connection Label */ +#define CIU30 0x800000 /* Channel 30 In Use */ +#define CL31 0x7f000000 /* Channel 31 Connection Label */ +#define CIU31 0x80000000 /* Channel 31 In Use */ + +/* Bit masks for MXVR_ALLOC_8 */ + +#define CL32 0x7f /* Channel 32 Connection Label */ +#define CIU32 0x80 /* Channel 32 In Use */ +#define CL33 0x7f00 /* Channel 33 Connection Label */ +#define CIU33 0x8000 /* Channel 33 In Use */ +#define CL34 0x7f0000 /* Channel 34 Connection Label */ +#define CIU34 0x800000 /* Channel 34 In Use */ +#define CL35 0x7f000000 /* Channel 35 Connection Label */ +#define CIU35 0x80000000 /* Channel 35 In Use */ + +/* Bit masks for MXVR_ALLOC_9 */ + +#define CL36 0x7f /* Channel 36 Connection Label */ +#define CIU36 0x80 /* Channel 36 In Use */ +#define CL37 0x7f00 /* Channel 37 Connection Label */ +#define CIU37 0x8000 /* Channel 37 In Use */ +#define CL38 0x7f0000 /* Channel 38 Connection Label */ +#define CIU38 0x800000 /* Channel 38 In Use */ +#define CL39 0x7f000000 /* Channel 39 Connection Label */ +#define CIU39 0x80000000 /* Channel 39 In Use */ + +/* Bit masks for MXVR_ALLOC_10 */ + +#define CL40 0x7f /* Channel 40 Connection Label */ +#define CIU40 0x80 /* Channel 40 In Use */ +#define CL41 0x7f00 /* Channel 41 Connection Label */ +#define CIU41 0x8000 /* Channel 41 In Use */ +#define CL42 0x7f0000 /* Channel 42 Connection Label */ +#define CIU42 0x800000 /* Channel 42 In Use */ +#define CL43 0x7f000000 /* Channel 43 Connection Label */ +#define CIU43 0x80000000 /* Channel 43 In Use */ + +/* Bit masks for MXVR_ALLOC_11 */ + +#define CL44 0x7f /* Channel 44 Connection Label */ +#define CIU44 0x80 /* Channel 44 In Use */ +#define CL45 0x7f00 /* Channel 45 Connection Label */ +#define CIU45 0x8000 /* Channel 45 In Use */ +#define CL46 0x7f0000 /* Channel 46 Connection Label */ +#define CIU46 0x800000 /* Channel 46 In Use */ +#define CL47 0x7f000000 /* Channel 47 Connection Label */ +#define CIU47 0x80000000 /* Channel 47 In Use */ + +/* Bit masks for MXVR_ALLOC_12 */ + +#define CL48 0x7f /* Channel 48 Connection Label */ +#define CIU48 0x80 /* Channel 48 In Use */ +#define CL49 0x7f00 /* Channel 49 Connection Label */ +#define CIU49 0x8000 /* Channel 49 In Use */ +#define CL50 0x7f0000 /* Channel 50 Connection Label */ +#define CIU50 0x800000 /* Channel 50 In Use */ +#define CL51 0x7f000000 /* Channel 51 Connection Label */ +#define CIU51 0x80000000 /* Channel 51 In Use */ + +/* Bit masks for MXVR_ALLOC_13 */ + +#define CL52 0x7f /* Channel 52 Connection Label */ +#define CIU52 0x80 /* Channel 52 In Use */ +#define CL53 0x7f00 /* Channel 53 Connection Label */ +#define CIU53 0x8000 /* Channel 53 In Use */ +#define CL54 0x7f0000 /* Channel 54 Connection Label */ +#define CIU54 0x800000 /* Channel 54 In Use */ +#define CL55 0x7f000000 /* Channel 55 Connection Label */ +#define CIU55 0x80000000 /* Channel 55 In Use */ + +/* Bit masks for MXVR_ALLOC_14 */ + +#define CL56 0x7f /* Channel 56 Connection Label */ +#define CIU56 0x80 /* Channel 56 In Use */ +#define CL57 0x7f00 /* Channel 57 Connection Label */ +#define CIU57 0x8000 /* Channel 57 In Use */ +#define CL58 0x7f0000 /* Channel 58 Connection Label */ +#define CIU58 0x800000 /* Channel 58 In Use */ +#define CL59 0x7f000000 /* Channel 59 Connection Label */ +#define CIU59 0x80000000 /* Channel 59 In Use */ + +/* MXVR_SYNC_LCHAN_0 Masks */ + +#define LCHANPC0 0x0000000Flu +#define LCHANPC1 0x000000F0lu +#define LCHANPC2 0x00000F00lu +#define LCHANPC3 0x0000F000lu +#define LCHANPC4 0x000F0000lu +#define LCHANPC5 0x00F00000lu +#define LCHANPC6 0x0F000000lu +#define LCHANPC7 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_1 Masks */ + +#define LCHANPC8 0x0000000Flu +#define LCHANPC9 0x000000F0lu +#define LCHANPC10 0x00000F00lu +#define LCHANPC11 0x0000F000lu +#define LCHANPC12 0x000F0000lu +#define LCHANPC13 0x00F00000lu +#define LCHANPC14 0x0F000000lu +#define LCHANPC15 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_2 Masks */ + +#define LCHANPC16 0x0000000Flu +#define LCHANPC17 0x000000F0lu +#define LCHANPC18 0x00000F00lu +#define LCHANPC19 0x0000F000lu +#define LCHANPC20 0x000F0000lu +#define LCHANPC21 0x00F00000lu +#define LCHANPC22 0x0F000000lu +#define LCHANPC23 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_3 Masks */ + +#define LCHANPC24 0x0000000Flu +#define LCHANPC25 0x000000F0lu +#define LCHANPC26 0x00000F00lu +#define LCHANPC27 0x0000F000lu +#define LCHANPC28 0x000F0000lu +#define LCHANPC29 0x00F00000lu +#define LCHANPC30 0x0F000000lu +#define LCHANPC31 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_4 Masks */ + +#define LCHANPC32 0x0000000Flu +#define LCHANPC33 0x000000F0lu +#define LCHANPC34 0x00000F00lu +#define LCHANPC35 0x0000F000lu +#define LCHANPC36 0x000F0000lu +#define LCHANPC37 0x00F00000lu +#define LCHANPC38 0x0F000000lu +#define LCHANPC39 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_5 Masks */ + +#define LCHANPC40 0x0000000Flu +#define LCHANPC41 0x000000F0lu +#define LCHANPC42 0x00000F00lu +#define LCHANPC43 0x0000F000lu +#define LCHANPC44 0x000F0000lu +#define LCHANPC45 0x00F00000lu +#define LCHANPC46 0x0F000000lu +#define LCHANPC47 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_6 Masks */ + +#define LCHANPC48 0x0000000Flu +#define LCHANPC49 0x000000F0lu +#define LCHANPC50 0x00000F00lu +#define LCHANPC51 0x0000F000lu +#define LCHANPC52 0x000F0000lu +#define LCHANPC53 0x00F00000lu +#define LCHANPC54 0x0F000000lu +#define LCHANPC55 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_7 Masks */ + +#define LCHANPC56 0x0000000Flu +#define LCHANPC57 0x000000F0lu +#define LCHANPC58 0x00000F00lu +#define LCHANPC59 0x0000F000lu + +/* Bit masks for MXVR_DMAx_CONFIG */ + +#define MDMAEN 0x1 /* DMA Channel Enable */ +#define DMADD 0x2 /* DMA Channel Direction */ +#define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */ +#define LCHAN 0x3c0 /* DMA Channel Logical Channel */ +#define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */ +#define BY2SWAPEN 0x800 /* DMA Channel Two Byte Swap Enable */ +#define MFLOW 0x7000 /* DMA Channel Operation Flow */ +#define FIXEDPM 0x80000 /* DMA Channel Fixed Pattern Matching Select */ +#define STARTPAT 0x300000 /* DMA Channel Start Pattern Select */ +#define STOPPAT 0xc00000 /* DMA Channel Stop Pattern Select */ +#define COUNTPOS 0x1c000000 /* DMA Channel Count Position */ + +/* Bit masks for MXVR_AP_CTL */ + +#define STARTAP 0x1 /* Start Asynchronous Packet Transmission */ +#define CANCELAP 0x2 /* Cancel Asynchronous Packet Transmission */ +#define RESETAP 0x4 /* Reset Asynchronous Packet Arbitration */ +#define APRBE0 0x4000 /* Asynchronous Packet Receive Buffer Entry 0 */ +#define APRBE1 0x8000 /* Asynchronous Packet Receive Buffer Entry 1 */ + +/* Bit masks for MXVR_APRB_START_ADDR */ + +#define MXVR_APRB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */ + +/* Bit masks for MXVR_APRB_CURR_ADDR */ + +#define MXVR_APRB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Receive Buffer Current Address */ + +/* Bit masks for MXVR_APTB_START_ADDR */ + +#define MXVR_APTB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Transmit Buffer Start Address */ + +/* Bit masks for MXVR_APTB_CURR_ADDR */ + +#define MXVR_APTB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */ + +/* Bit masks for MXVR_CM_CTL */ + +#define STARTCM 0x1 /* Start Control Message Transmission */ +#define CANCELCM 0x2 /* Cancel Control Message Transmission */ +#define CMRBE0 0x10000 /* Control Message Receive Buffer Entry 0 */ +#define CMRBE1 0x20000 /* Control Message Receive Buffer Entry 1 */ +#define CMRBE2 0x40000 /* Control Message Receive Buffer Entry 2 */ +#define CMRBE3 0x80000 /* Control Message Receive Buffer Entry 3 */ +#define CMRBE4 0x100000 /* Control Message Receive Buffer Entry 4 */ +#define CMRBE5 0x200000 /* Control Message Receive Buffer Entry 5 */ +#define CMRBE6 0x400000 /* Control Message Receive Buffer Entry 6 */ +#define CMRBE7 0x800000 /* Control Message Receive Buffer Entry 7 */ +#define CMRBE8 0x1000000 /* Control Message Receive Buffer Entry 8 */ +#define CMRBE9 0x2000000 /* Control Message Receive Buffer Entry 9 */ +#define CMRBE10 0x4000000 /* Control Message Receive Buffer Entry 10 */ +#define CMRBE11 0x8000000 /* Control Message Receive Buffer Entry 11 */ +#define CMRBE12 0x10000000 /* Control Message Receive Buffer Entry 12 */ +#define CMRBE13 0x20000000 /* Control Message Receive Buffer Entry 13 */ +#define CMRBE14 0x40000000 /* Control Message Receive Buffer Entry 14 */ +#define CMRBE15 0x80000000 /* Control Message Receive Buffer Entry 15 */ + +/* Bit masks for MXVR_CMRB_START_ADDR */ + +#define MXVR_CMRB_START_ADDR_MASK 0x1fffffe /* Control Message Receive Buffer Start Address */ + +/* Bit masks for MXVR_CMRB_CURR_ADDR */ + +#define MXVR_CMRB_CURR_ADDR_MASK 0xffffffff /* Control Message Receive Buffer Current Address */ + +/* Bit masks for MXVR_CMTB_START_ADDR */ + +#define MXVR_CMTB_START_ADDR_MASK 0x1fffffe /* Control Message Transmit Buffer Start Address */ + +/* Bit masks for MXVR_CMTB_CURR_ADDR */ + +#define MXVR_CMTB_CURR_ADDR_MASK 0xffffffff /* Control Message Transmit Buffer Current Address */ + +/* Bit masks for MXVR_RRDB_START_ADDR */ + +#define MXVR_RRDB_START_ADDR_MASK 0x1fffffe /* Remote Read Buffer Start Address */ + +/* Bit masks for MXVR_RRDB_CURR_ADDR */ + +#define MXVR_RRDB_CURR_ADDR_MASK 0xffffffff /* Remote Read Buffer Current Address */ + +/* Bit masks for MXVR_PAT_DATAx */ + +#define MATCH_DATA_0 0xff /* Pattern Match Data Byte 0 */ +#define MATCH_DATA_1 0xff00 /* Pattern Match Data Byte 1 */ +#define MATCH_DATA_2 0xff0000 /* Pattern Match Data Byte 2 */ +#define MATCH_DATA_3 0xff000000 /* Pattern Match Data Byte 3 */ + +/* Bit masks for MXVR_PAT_EN_0 */ + +#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */ +#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */ +#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */ +#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */ +#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */ +#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */ +#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */ +#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */ +#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */ +#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */ +#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */ +#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */ +#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */ +#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */ +#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */ +#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */ +#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */ +#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */ +#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */ +#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */ +#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */ +#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */ +#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */ +#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */ +#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */ +#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */ +#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */ +#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */ +#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */ +#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */ +#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */ +#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */ + +/* Bit masks for MXVR_PAT_EN_1 */ + +#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */ +#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */ +#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */ +#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */ +#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */ +#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */ +#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */ +#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */ +#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */ +#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */ +#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */ +#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */ +#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */ +#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */ +#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */ +#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */ +#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */ +#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */ +#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */ +#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */ +#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */ +#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */ +#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */ +#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */ +#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */ +#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */ +#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */ +#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */ +#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */ +#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */ +#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */ +#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */ + +/* Bit masks for MXVR_FRAME_CNT_0 */ + +#define FCNT 0xffff /* Frame Count */ + +/* Bit masks for MXVR_FRAME_CNT_1 */ + +#define FCNT 0xffff /* Frame Count */ + +/* Bit masks for MXVR_ROUTING_0 */ + +#define TX_CH0 0x3f /* Transmit Channel 0 */ +#define MUTE_CH0 0x80 /* Mute Channel 0 */ +#define TX_CH1 0x3f00 /* Transmit Channel 0 */ +#define MUTE_CH1 0x8000 /* Mute Channel 0 */ +#define TX_CH2 0x3f0000 /* Transmit Channel 0 */ +#define MUTE_CH2 0x800000 /* Mute Channel 0 */ +#define TX_CH3 0x3f000000 /* Transmit Channel 0 */ +#define MUTE_CH3 0x80000000 /* Mute Channel 0 */ + +/* Bit masks for MXVR_ROUTING_1 */ + +#define TX_CH4 0x3f /* Transmit Channel 4 */ +#define MUTE_CH4 0x80 /* Mute Channel 4 */ +#define TX_CH5 0x3f00 /* Transmit Channel 5 */ +#define MUTE_CH5 0x8000 /* Mute Channel 5 */ +#define TX_CH6 0x3f0000 /* Transmit Channel 6 */ +#define MUTE_CH6 0x800000 /* Mute Channel 6 */ +#define TX_CH7 0x3f000000 /* Transmit Channel 7 */ +#define MUTE_CH7 0x80000000 /* Mute Channel 7 */ + +/* Bit masks for MXVR_ROUTING_2 */ + +#define TX_CH8 0x3f /* Transmit Channel 8 */ +#define MUTE_CH8 0x80 /* Mute Channel 8 */ +#define TX_CH9 0x3f00 /* Transmit Channel 9 */ +#define MUTE_CH9 0x8000 /* Mute Channel 9 */ +#define TX_CH10 0x3f0000 /* Transmit Channel 10 */ +#define MUTE_CH10 0x800000 /* Mute Channel 10 */ +#define TX_CH11 0x3f000000 /* Transmit Channel 11 */ +#define MUTE_CH11 0x80000000 /* Mute Channel 11 */ + +/* Bit masks for MXVR_ROUTING_3 */ + +#define TX_CH12 0x3f /* Transmit Channel 12 */ +#define MUTE_CH12 0x80 /* Mute Channel 12 */ +#define TX_CH13 0x3f00 /* Transmit Channel 13 */ +#define MUTE_CH13 0x8000 /* Mute Channel 13 */ +#define TX_CH14 0x3f0000 /* Transmit Channel 14 */ +#define MUTE_CH14 0x800000 /* Mute Channel 14 */ +#define TX_CH15 0x3f000000 /* Transmit Channel 15 */ +#define MUTE_CH15 0x80000000 /* Mute Channel 15 */ + +/* Bit masks for MXVR_ROUTING_4 */ + +#define TX_CH16 0x3f /* Transmit Channel 16 */ +#define MUTE_CH16 0x80 /* Mute Channel 16 */ +#define TX_CH17 0x3f00 /* Transmit Channel 17 */ +#define MUTE_CH17 0x8000 /* Mute Channel 17 */ +#define TX_CH18 0x3f0000 /* Transmit Channel 18 */ +#define MUTE_CH18 0x800000 /* Mute Channel 18 */ +#define TX_CH19 0x3f000000 /* Transmit Channel 19 */ +#define MUTE_CH19 0x80000000 /* Mute Channel 19 */ + +/* Bit masks for MXVR_ROUTING_5 */ + +#define TX_CH20 0x3f /* Transmit Channel 20 */ +#define MUTE_CH20 0x80 /* Mute Channel 20 */ +#define TX_CH21 0x3f00 /* Transmit Channel 21 */ +#define MUTE_CH21 0x8000 /* Mute Channel 21 */ +#define TX_CH22 0x3f0000 /* Transmit Channel 22 */ +#define MUTE_CH22 0x800000 /* Mute Channel 22 */ +#define TX_CH23 0x3f000000 /* Transmit Channel 23 */ +#define MUTE_CH23 0x80000000 /* Mute Channel 23 */ + +/* Bit masks for MXVR_ROUTING_6 */ + +#define TX_CH24 0x3f /* Transmit Channel 24 */ +#define MUTE_CH24 0x80 /* Mute Channel 24 */ +#define TX_CH25 0x3f00 /* Transmit Channel 25 */ +#define MUTE_CH25 0x8000 /* Mute Channel 25 */ +#define TX_CH26 0x3f0000 /* Transmit Channel 26 */ +#define MUTE_CH26 0x800000 /* Mute Channel 26 */ +#define TX_CH27 0x3f000000 /* Transmit Channel 27 */ +#define MUTE_CH27 0x80000000 /* Mute Channel 27 */ + +/* Bit masks for MXVR_ROUTING_7 */ + +#define TX_CH28 0x3f /* Transmit Channel 28 */ +#define MUTE_CH28 0x80 /* Mute Channel 28 */ +#define TX_CH29 0x3f00 /* Transmit Channel 29 */ +#define MUTE_CH29 0x8000 /* Mute Channel 29 */ +#define TX_CH30 0x3f0000 /* Transmit Channel 30 */ +#define MUTE_CH30 0x800000 /* Mute Channel 30 */ +#define TX_CH31 0x3f000000 /* Transmit Channel 31 */ +#define MUTE_CH31 0x80000000 /* Mute Channel 31 */ + +/* Bit masks for MXVR_ROUTING_8 */ + +#define TX_CH32 0x3f /* Transmit Channel 32 */ +#define MUTE_CH32 0x80 /* Mute Channel 32 */ +#define TX_CH33 0x3f00 /* Transmit Channel 33 */ +#define MUTE_CH33 0x8000 /* Mute Channel 33 */ +#define TX_CH34 0x3f0000 /* Transmit Channel 34 */ +#define MUTE_CH34 0x800000 /* Mute Channel 34 */ +#define TX_CH35 0x3f000000 /* Transmit Channel 35 */ +#define MUTE_CH35 0x80000000 /* Mute Channel 35 */ + +/* Bit masks for MXVR_ROUTING_9 */ + +#define TX_CH36 0x3f /* Transmit Channel 36 */ +#define MUTE_CH36 0x80 /* Mute Channel 36 */ +#define TX_CH37 0x3f00 /* Transmit Channel 37 */ +#define MUTE_CH37 0x8000 /* Mute Channel 37 */ +#define TX_CH38 0x3f0000 /* Transmit Channel 38 */ +#define MUTE_CH38 0x800000 /* Mute Channel 38 */ +#define TX_CH39 0x3f000000 /* Transmit Channel 39 */ +#define MUTE_CH39 0x80000000 /* Mute Channel 39 */ + +/* Bit masks for MXVR_ROUTING_10 */ + +#define TX_CH40 0x3f /* Transmit Channel 40 */ +#define MUTE_CH40 0x80 /* Mute Channel 40 */ +#define TX_CH41 0x3f00 /* Transmit Channel 41 */ +#define MUTE_CH41 0x8000 /* Mute Channel 41 */ +#define TX_CH42 0x3f0000 /* Transmit Channel 42 */ +#define MUTE_CH42 0x800000 /* Mute Channel 42 */ +#define TX_CH43 0x3f000000 /* Transmit Channel 43 */ +#define MUTE_CH43 0x80000000 /* Mute Channel 43 */ + +/* Bit masks for MXVR_ROUTING_11 */ + +#define TX_CH44 0x3f /* Transmit Channel 44 */ +#define MUTE_CH44 0x80 /* Mute Channel 44 */ +#define TX_CH45 0x3f00 /* Transmit Channel 45 */ +#define MUTE_CH45 0x8000 /* Mute Channel 45 */ +#define TX_CH46 0x3f0000 /* Transmit Channel 46 */ +#define MUTE_CH46 0x800000 /* Mute Channel 46 */ +#define TX_CH47 0x3f000000 /* Transmit Channel 47 */ +#define MUTE_CH47 0x80000000 /* Mute Channel 47 */ + +/* Bit masks for MXVR_ROUTING_12 */ + +#define TX_CH48 0x3f /* Transmit Channel 48 */ +#define MUTE_CH48 0x80 /* Mute Channel 48 */ +#define TX_CH49 0x3f00 /* Transmit Channel 49 */ +#define MUTE_CH49 0x8000 /* Mute Channel 49 */ +#define TX_CH50 0x3f0000 /* Transmit Channel 50 */ +#define MUTE_CH50 0x800000 /* Mute Channel 50 */ +#define TX_CH51 0x3f000000 /* Transmit Channel 51 */ +#define MUTE_CH51 0x80000000 /* Mute Channel 51 */ + +/* Bit masks for MXVR_ROUTING_13 */ + +#define TX_CH52 0x3f /* Transmit Channel 52 */ +#define MUTE_CH52 0x80 /* Mute Channel 52 */ +#define TX_CH53 0x3f00 /* Transmit Channel 53 */ +#define MUTE_CH53 0x8000 /* Mute Channel 53 */ +#define TX_CH54 0x3f0000 /* Transmit Channel 54 */ +#define MUTE_CH54 0x800000 /* Mute Channel 54 */ +#define TX_CH55 0x3f000000 /* Transmit Channel 55 */ +#define MUTE_CH55 0x80000000 /* Mute Channel 55 */ + +/* Bit masks for MXVR_ROUTING_14 */ + +#define TX_CH56 0x3f /* Transmit Channel 56 */ +#define MUTE_CH56 0x80 /* Mute Channel 56 */ +#define TX_CH57 0x3f00 /* Transmit Channel 57 */ +#define MUTE_CH57 0x8000 /* Mute Channel 57 */ +#define TX_CH58 0x3f0000 /* Transmit Channel 58 */ +#define MUTE_CH58 0x800000 /* Mute Channel 58 */ +#define TX_CH59 0x3f000000 /* Transmit Channel 59 */ +#define MUTE_CH59 0x80000000 /* Mute Channel 59 */ + +/* Bit masks for MXVR_BLOCK_CNT */ + +#define BCNT 0xffff /* Block Count */ + +/* Bit masks for MXVR_CLK_CTL */ + +#define MXTALCEN 0x1 /* MXVR Crystal Oscillator Clock Enable */ +#define MXTALFEN 0x2 /* MXVR Crystal Oscillator Feedback Enable */ +#define MXTALMUL 0x30 /* MXVR Crystal Multiplier */ +#define CLKX3SEL 0x80 /* Clock Generation Source Select */ +#define MMCLKEN 0x100 /* Master Clock Enable */ +#define MMCLKMUL 0x1e00 /* Master Clock Multiplication Factor */ +#define PLLSMPS 0xe000 /* MXVR PLL State Machine Prescaler */ +#define MBCLKEN 0x10000 /* Bit Clock Enable */ +#define MBCLKDIV 0x1e0000 /* Bit Clock Divide Factor */ +#define INVRX 0x800000 /* Invert Receive Data */ +#define MFSEN 0x1000000 /* Frame Sync Enable */ +#define MFSDIV 0x1e000000 /* Frame Sync Divide Factor */ +#define MFSSEL 0x60000000 /* Frame Sync Select */ +#define MFSSYNC 0x80000000 /* Frame Sync Synchronization Select */ + +/* Bit masks for MXVR_CDRPLL_CTL */ + +#define CDRSMEN 0x1 /* MXVR CDRPLL State Machine Enable */ +#define CDRRSTB 0x2 /* MXVR CDRPLL Reset */ +#define CDRSVCO 0x4 /* MXVR CDRPLL Start VCO */ +#define CDRMODE 0x8 /* MXVR CDRPLL CDR Mode Select */ +#define CDRSCNT 0x3f0 /* MXVR CDRPLL Start Counter */ +#define CDRLCNT 0xfc00 /* MXVR CDRPLL Lock Counter */ +#define CDRSHPSEL 0x3f0000 /* MXVR CDRPLL Shaper Select */ +#define CDRSHPEN 0x800000 /* MXVR CDRPLL Shaper Enable */ +#define CDRCPSEL 0xff000000 /* MXVR CDRPLL Charge Pump Current Select */ + +/* Bit masks for MXVR_FMPLL_CTL */ + +#define FMSMEN 0x1 /* MXVR FMPLL State Machine Enable */ +#define FMRSTB 0x2 /* MXVR FMPLL Reset */ +#define FMSVCO 0x4 /* MXVR FMPLL Start VCO */ +#define FMSCNT 0x3f0 /* MXVR FMPLL Start Counter */ +#define FMLCNT 0xfc00 /* MXVR FMPLL Lock Counter */ +#define FMCPSEL 0xff000000 /* MXVR FMPLL Charge Pump Current Select */ + +/* Bit masks for MXVR_PIN_CTL */ + +#define MTXONBOD 0x1 /* MTXONB Open Drain Select */ +#define MTXONBG 0x2 /* MTXONB Gates MTX Select */ +#define MFSOE 0x10 /* MFS Output Enable */ +#define MFSGPSEL 0x20 /* MFS General Purpose Output Select */ +#define MFSGPDAT 0x40 /* MFS General Purpose Output Data */ + +/* Bit masks for MXVR_SCLK_CNT */ + +#define SCNT 0xffff /* System Clock Count */ + +/* Bit masks for KPAD_CTL */ + +#define KPAD_EN 0x1 /* Keypad Enable */ +#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ +#define KPAD_ROWEN 0x1c00 /* Row Enable Width */ +#define KPAD_COLEN 0xe000 /* Column Enable Width */ + +/* Bit masks for KPAD_PRESCALE */ + +#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */ + +/* Bit masks for KPAD_MSEL */ + +#define DBON_SCALE 0xff /* Debounce Scale Value */ +#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */ + +/* Bit masks for KPAD_ROWCOL */ + +#define KPAD_ROW 0xff /* Rows Pressed */ +#define KPAD_COL 0xff00 /* Columns Pressed */ + +/* Bit masks for KPAD_STAT */ + +#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ +#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ +#define KPAD_PRESSED 0x8 /* Key press current status */ + +/* Bit masks for KPAD_SOFTEVAL */ + +#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ + +/* Bit masks for SDH_COMMAND */ + +#define CMD_IDX 0x3f /* Command Index */ +#define CMD_RSP 0x40 /* Response */ +#define CMD_L_RSP 0x80 /* Long Response */ +#define CMD_INT_E 0x100 /* Command Interrupt */ +#define CMD_PEND_E 0x200 /* Command Pending */ +#define CMD_E 0x400 /* Command Enable */ + +/* Bit masks for SDH_PWR_CTL */ + +#define PWR_ON 0x3 /* Power On */ +#if 0 +#define TBD 0x3c /* TBD */ +#endif +#define SD_CMD_OD 0x40 /* Open Drain Output */ +#define ROD_CTL 0x80 /* Rod Control */ + +/* Bit masks for SDH_CLK_CTL */ + +#define CLKDIV 0xff /* MC_CLK Divisor */ +#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ +#define PWR_SV_E 0x200 /* Power Save Enable */ +#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ +#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ + +/* Bit masks for SDH_RESP_CMD */ + +#define RESP_CMD 0x3f /* Response Command */ + +/* Bit masks for SDH_DATA_CTL */ + +#define DTX_E 0x1 /* Data Transfer Enable */ +#define DTX_DIR 0x2 /* Data Transfer Direction */ +#define DTX_MODE 0x4 /* Data Transfer Mode */ +#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ +#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ + +/* Bit masks for SDH_STATUS */ + +#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ +#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ +#define CMD_TIME_OUT 0x4 /* CMD Time Out */ +#define DAT_TIME_OUT 0x8 /* Data Time Out */ +#define TX_UNDERRUN 0x10 /* Transmit Underrun */ +#define RX_OVERRUN 0x20 /* Receive Overrun */ +#define CMD_RESP_END 0x40 /* CMD Response End */ +#define CMD_SENT 0x80 /* CMD Sent */ +#define DAT_END 0x100 /* Data End */ +#define START_BIT_ERR 0x200 /* Start Bit Error */ +#define DAT_BLK_END 0x400 /* Data Block End */ +#define CMD_ACT 0x800 /* CMD Active */ +#define TX_ACT 0x1000 /* Transmit Active */ +#define RX_ACT 0x2000 /* Receive Active */ +#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ +#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ +#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ +#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ +#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ +#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ +#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ +#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ + +/* Bit masks for SDH_STATUS_CLR */ + +#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ +#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ +#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ +#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ +#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ +#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ +#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ +#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ +#define DAT_END_STAT 0x100 /* Data End Status */ +#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ +#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ + +/* Bit masks for SDH_MASK0 */ + +#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ +#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ +#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ +#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ +#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ +#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ +#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ +#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ +#define DAT_END_MASK 0x100 /* Data End Mask */ +#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ +#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ +#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ +#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ +#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ +#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ +#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ +#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ +#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ +#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ +#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ +#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ +#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ + +/* Bit masks for SDH_FIFO_CNT */ + +#define FIFO_COUNT 0x7fff /* FIFO Count */ + +/* Bit masks for SDH_E_STATUS */ + +#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ +#define SD_CARD_DET 0x10 /* SD Card Detect */ + +/* Bit masks for SDH_E_MASK */ + +#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ +#define SCD_MSK 0x40 /* Mask Card Detect */ + +/* Bit masks for SDH_CFG */ + +#define CLKS_EN 0x1 /* Clocks Enable */ +#define SD4E 0x4 /* SDIO 4-Bit Enable */ +#define MWE 0x8 /* Moving Window Enable */ +#define SD_RST 0x10 /* SDMMC Reset */ +#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ +#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ +#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ + +/* Bit masks for SDH_RD_WAIT_EN */ + +#define RWR 0x1 /* Read Wait Request */ + +/* Bit masks for ATAPI_CONTROL */ + +#define PIO_START 0x1 /* Start PIO/Reg Op */ +#define MULTI_START 0x2 /* Start Multi-DMA Op */ +#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ +#define XFER_DIR 0x8 /* Transfer Direction */ +#define IORDY_EN 0x10 /* IORDY Enable */ +#define FIFO_FLUSH 0x20 /* Flush FIFOs */ +#define SOFT_RST 0x40 /* Soft Reset */ +#define DEV_RST 0x80 /* Device Reset */ +#define TFRCNT_RST 0x100 /* Trans Count Reset */ +#define END_ON_TERM 0x200 /* End/Terminate Select */ +#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ +#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ + +/* Bit masks for ATAPI_STATUS */ + +#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ +#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ +#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ +#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ + +/* Bit masks for ATAPI_DEV_ADDR */ + +#define DEV_ADDR 0x1f /* Device Address */ + +/* Bit masks for ATAPI_INT_MASK */ + +#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ +#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ +#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ +#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ +#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ +#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ +#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ +#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ +#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ + +/* Bit masks for ATAPI_INT_STATUS */ + +#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ +#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ +#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ +#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ +#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ +#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ +#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ +#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ +#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ + +/* Bit masks for ATAPI_LINE_STATUS */ + +#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ +#define ATAPI_DASP 0x2 /* Device dasp to host line status */ +#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ +#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ +#define ATAPI_ADDR 0x70 /* ATAPI address line status */ +#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ +#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ +#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ +#define ATAPI_DIORN 0x400 /* ATAPI read line status */ +#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_SM_STATE */ + +#define PIO_CSTATE 0xf /* PIO mode state machine current state */ +#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */ +#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */ +#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_TERMINATE */ + +#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ + +/* Bit masks for ATAPI_REG_TIM_0 */ + +#define T2_REG 0xff /* End of cycle time for register access transfers */ +#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */ + +/* Bit masks for ATAPI_PIO_TIM_0 */ + +#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */ +#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */ +#define T4_REG 0xf000 /* DIOW data hold */ + +/* Bit masks for ATAPI_PIO_TIM_1 */ + +#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */ + +/* Bit masks for ATAPI_MULTI_TIM_0 */ + +#define TD 0xff /* DIOR/DIOW asserted pulsewidth */ +#define TM 0xff00 /* Time from address valid to DIOR/DIOW */ + +/* Bit masks for ATAPI_MULTI_TIM_1 */ + +#define TKW 0xff /* Selects DIOW negated pulsewidth */ +#define TKR 0xff00 /* Selects DIOR negated pulsewidth */ + +/* Bit masks for ATAPI_MULTI_TIM_2 */ + +#define TH 0xff /* Selects DIOW data hold */ +#define TEOC 0xff00 /* Selects end of cycle for DMA */ + +/* Bit masks for ATAPI_ULTRA_TIM_0 */ + +#define TACK 0xff /* Selects setup and hold times for TACK */ +#define TENV 0xff00 /* Selects envelope time */ + +/* Bit masks for ATAPI_ULTRA_TIM_1 */ + +#define TDVS 0xff /* Selects data valid setup time */ +#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */ + +/* Bit masks for ATAPI_ULTRA_TIM_2 */ + +#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */ +#define TMLI 0xff00 /* Selects interlock time */ + +/* Bit masks for ATAPI_ULTRA_TIM_3 */ + +#define TZAH 0xff /* Selects minimum delay required for output */ +#define READY_PAUSE 0xff00 /* Selects ready to pause */ + +/* Bit masks for TIMER_ENABLE1 */ + +#define TIMEN8 0x1 /* Timer 8 Enable */ +#define TIMEN9 0x2 /* Timer 9 Enable */ +#define TIMEN10 0x4 /* Timer 10 Enable */ + +/* Bit masks for TIMER_DISABLE1 */ + +#define TIMDIS8 0x1 /* Timer 8 Disable */ +#define TIMDIS9 0x2 /* Timer 9 Disable */ +#define TIMDIS10 0x4 /* Timer 10 Disable */ + +/* Bit masks for TIMER_STATUS1 */ + +#define TIMIL8 0x1 /* Timer 8 Interrupt */ +#define TIMIL9 0x2 /* Timer 9 Interrupt */ +#define TIMIL10 0x4 /* Timer 10 Interrupt */ +#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ +#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ +#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ +#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ +#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ +#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ + +/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ + +/* Bit masks for USB_FADDR */ + +#define FUNCTION_ADDRESS 0x7f /* Function address */ + +/* Bit masks for USB_POWER */ + +#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ +#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ +#define RESUME_MODE 0x4 /* DMA Mode */ +#define RESET 0x8 /* Reset indicator */ +#define HS_MODE 0x10 /* High Speed mode indicator */ +#define HS_ENABLE 0x20 /* high Speed Enable */ +#define SOFT_CONN 0x40 /* Soft connect */ +#define ISO_UPDATE 0x80 /* Isochronous update */ + +/* Bit masks for USB_INTRTX */ + +#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ +#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ +#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ +#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ +#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ +#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ +#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ +#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ + +/* Bit masks for USB_INTRRX */ + +#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ +#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ +#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ +#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ +#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ +#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ +#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ + +/* Bit masks for USB_INTRTXE */ + +#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ +#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ +#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ +#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ +#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ +#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ +#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ +#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ + +/* Bit masks for USB_INTRRXE */ + +#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ +#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ +#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ +#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ +#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ +#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ +#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ + +/* Bit masks for USB_INTRUSB */ + +#define SUSPEND_B 0x1 /* Suspend indicator */ +#define RESUME_B 0x2 /* Resume indicator */ +#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ +#define SOF_B 0x8 /* Start of frame */ +#define CONN_B 0x10 /* Connection indicator */ +#define DISCON_B 0x20 /* Disconnect indicator */ +#define SESSION_REQ_B 0x40 /* Session Request */ +#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ + +/* Bit masks for USB_INTRUSBE */ + +#define SUSPEND_BE 0x1 /* Suspend indicator int enable */ +#define RESUME_BE 0x2 /* Resume indicator int enable */ +#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ +#define SOF_BE 0x8 /* Start of frame int enable */ +#define CONN_BE 0x10 /* Connection indicator int enable */ +#define DISCON_BE 0x20 /* Disconnect indicator int enable */ +#define SESSION_REQ_BE 0x40 /* Session Request int enable */ +#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ + +/* Bit masks for USB_FRAME */ + +#define FRAME_NUMBER 0x7ff /* Frame number */ + +/* Bit masks for USB_INDEX */ + +#define SELECTED_ENDPOINT 0xf /* selected endpoint */ + +/* Bit masks for USB_GLOBAL_CTL */ + +#define GLOBAL_ENA 0x1 /* enables USB module */ +#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ +#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ +#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ +#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ +#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ +#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ +#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ +#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ +#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ +#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ +#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ +#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ +#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ +#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ + +/* Bit masks for USB_OTG_DEV_CTL */ + +#define SESSION 0x1 /* session indicator */ +#define HOST_REQ 0x2 /* Host negotiation request */ +#define HOST_MODE 0x4 /* indicates USBDRC is a host */ +#define VBUS0 0x8 /* Vbus level indicator[0] */ +#define VBUS1 0x10 /* Vbus level indicator[1] */ +#define LSDEV 0x20 /* Low-speed indicator */ +#define FSDEV 0x40 /* Full or High-speed indicator */ +#define B_DEVICE 0x80 /* A' or 'B' device indicator */ + +/* Bit masks for USB_OTG_VBUS_IRQ */ + +#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ +#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ +#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ +#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ +#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ +#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ + +/* Bit masks for USB_OTG_VBUS_MASK */ + +#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ +#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ +#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ +#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ +#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ +#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ + +/* Bit masks for USB_CSR0 */ + +#define RXPKTRDY 0x1 /* data packet receive indicator */ +#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ +#define STALL_SENT 0x4 /* STALL handshake sent */ +#define DATAEND 0x8 /* Data end indicator */ +#define SETUPEND 0x10 /* Setup end */ +#define SENDSTALL 0x20 /* Send STALL handshake */ +#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ +#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ +#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ +#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ +#define SETUPPKT_H 0x8 /* send Setup token host mode */ +#define ERROR_H 0x10 /* timeout error indicator host mode */ +#define REQPKT_H 0x20 /* Request an IN transaction host mode */ +#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ +#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ + +/* Bit masks for USB_COUNT0 */ + +#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ + +/* Bit masks for USB_NAKLIMIT0 */ + +#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ + +/* Bit masks for USB_TX_MAX_PACKET */ + +#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ + +/* Bit masks for USB_RX_MAX_PACKET */ + +#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ + +/* Bit masks for USB_TXCSR */ + +#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ +#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ +#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ +#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ +#define STALL_SEND_T 0x10 /* issue a Stall handshake */ +#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ +#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ +#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ +#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ +#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ +#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ +#define ISO_T 0x4000 /* enable Isochronous transfers */ +#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ +#define ERROR_TH 0x4 /* error condition host mode */ +#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ +#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ + +/* Bit masks for USB_TXCOUNT */ + +#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ + +/* Bit masks for USB_RXCSR */ + +#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ +#define FIFO_FULL_R 0x2 /* FIFO not empty */ +#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ +#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ +#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ +#define STALL_SEND_R 0x20 /* issue a Stall handshake */ +#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ +#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ +#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ +#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ +#define DISNYET_R 0x1000 /* disable Nyet handshakes */ +#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ +#define ISO_R 0x4000 /* enable Isochronous transfers */ +#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ +#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ +#define REQPKT_RH 0x20 /* request an IN transaction host mode */ +#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ +#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ +#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ +#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ + +/* Bit masks for USB_RXCOUNT */ + +#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ + +/* Bit masks for USB_TXTYPE */ + +#define TARGET_EP_NO_T 0xf /* EP number */ +#define PROTOCOL_T 0xc /* transfer type */ + +/* Bit masks for USB_TXINTERVAL */ + +#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ + +/* Bit masks for USB_RXTYPE */ + +#define TARGET_EP_NO_R 0xf /* EP number */ +#define PROTOCOL_R 0xc /* transfer type */ + +/* Bit masks for USB_RXINTERVAL */ + +#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ + +/* Bit masks for USB_DMA_INTERRUPT */ + +#define DMA0_INT 0x1 /* DMA0 pending interrupt */ +#define DMA1_INT 0x2 /* DMA1 pending interrupt */ +#define DMA2_INT 0x4 /* DMA2 pending interrupt */ +#define DMA3_INT 0x8 /* DMA3 pending interrupt */ +#define DMA4_INT 0x10 /* DMA4 pending interrupt */ +#define DMA5_INT 0x20 /* DMA5 pending interrupt */ +#define DMA6_INT 0x40 /* DMA6 pending interrupt */ +#define DMA7_INT 0x80 /* DMA7 pending interrupt */ + +/* Bit masks for USB_DMAxCONTROL */ + +#define DMA_ENA 0x1 /* DMA enable */ +#define DIRECTION 0x2 /* direction of DMA transfer */ +#define MODE 0x4 /* DMA Bus error */ +#define INT_ENA 0x8 /* Interrupt enable */ +#define EPNUM 0xf0 /* EP number */ +#define BUSERROR 0x100 /* DMA Bus error */ + +/* Bit masks for USB_DMAxADDRHIGH */ + +#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ + +/* Bit masks for USB_DMAxADDRLOW */ + +#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ + +/* Bit masks for USB_DMAxCOUNTHIGH */ + +#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ + +/* Bit masks for USB_DMAxCOUNTLOW */ + +#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ + +/* Bit masks for HMDMAx_CONTROL */ + +#define HMDMAEN 0x1 /* Handshake MDMA Enable */ +#define REP 0x2 /* Handshake MDMA Request Polarity */ +#define UTE 0x8 /* Urgency Threshold Enable */ +#define OIE 0x10 /* Overflow Interrupt Enable */ +#define BDIE 0x20 /* Block Done Interrupt Enable */ +#define MBDI 0x40 /* Mask Block Done Interrupt */ +#define DRQ 0x300 /* Handshake MDMA Request Type */ +#define RBC 0x1000 /* Force Reload of BCOUNT */ +#define PS 0x2000 /* Pin Status */ +#define OI 0x4000 /* Overflow Interrupt Generated */ +#define BDI 0x8000 /* Block Done Interrupt Generated */ + +/* ******************************************* */ +/* MULTI BIT MACRO ENUMERATIONS */ +/* ******************************************* */ + +/* ************************ */ +/* MXVR Address Offsets */ +/* ************************ */ + +/* Control Message Receive Buffer (CMRB) Address Offsets */ + +#define CMRB_STRIDE 0x00000016lu + +#define CMRB_DST_OFFSET 0x00000000lu +#define CMRB_SRC_OFFSET 0x00000002lu +#define CMRB_DATA_OFFSET 0x00000005lu + +/* Control Message Transmit Buffer (CMTB) Address Offsets */ + +#define CMTB_PRIO_OFFSET 0x00000000lu +#define CMTB_DST_OFFSET 0x00000002lu +#define CMTB_SRC_OFFSET 0x00000004lu +#define CMTB_TYPE_OFFSET 0x00000006lu +#define CMTB_DATA_OFFSET 0x00000007lu + +#define CMTB_ANSWER_OFFSET 0x0000000Alu + +#define CMTB_STAT_N_OFFSET 0x00000018lu +#define CMTB_STAT_A_OFFSET 0x00000016lu +#define CMTB_STAT_D_OFFSET 0x0000000Elu +#define CMTB_STAT_R_OFFSET 0x00000014lu +#define CMTB_STAT_W_OFFSET 0x00000014lu +#define CMTB_STAT_G_OFFSET 0x00000014lu + +/* Asynchronous Packet Receive Buffer (APRB) Address Offsets */ + +#define APRB_STRIDE 0x00000400lu + +#define APRB_DST_OFFSET 0x00000000lu +#define APRB_LEN_OFFSET 0x00000002lu +#define APRB_SRC_OFFSET 0x00000004lu +#define APRB_DATA_OFFSET 0x00000006lu + +/* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */ + +#define APTB_PRIO_OFFSET 0x00000000lu +#define APTB_DST_OFFSET 0x00000002lu +#define APTB_LEN_OFFSET 0x00000004lu +#define APTB_SRC_OFFSET 0x00000006lu +#define APTB_DATA_OFFSET 0x00000008lu + +/* Remote Read Buffer (RRDB) Address Offsets */ + +#define RRDB_WADDR_OFFSET 0x00000100lu +#define RRDB_WLEN_OFFSET 0x00000101lu + +/* **************** */ +/* MXVR Macros */ +/* **************** */ + +/* MXVR_CONFIG Macros */ + +#define SET_MSB(x) ( ( (x) & 0xF ) << 9) + +/* MXVR_INT_STAT_1 Macros */ + +#define DONEX(x) (0x00000002 << (4 * (x))) +#define HDONEX(x) (0x00000001 << (4 * (x))) + +/* MXVR_INT_EN_1 Macros */ + +#define DONEENX(x) (0x00000002 << (4 * (x))) +#define HDONEENX(x) (0x00000001 << (4 * (x))) + +/* MXVR_CDRPLL_CTL Macros */ + +#define SET_CDRSHPSEL(x) ( ( (x) & 0x3F ) << 16) + +/* MXVR_FMPLL_CTL Macros */ + +#define SET_CDRCPSEL(x) ( ( (x) & 0xFF ) << 24) +#define SET_FMCPSEL(x) ( ( (x) & 0xFF ) << 24) + +#endif /* _DEF_BF549_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h new file mode 100644 index 000000000000..e022e896cb18 --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h @@ -0,0 +1,3956 @@ +/* + * File: include/asm-blackfin/mach-bf548/defBF54x_base.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _DEF_BF54X_H +#define _DEF_BF54X_H + + +/* ************************************************************** */ +/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ +/* ************************************************************** */ + +/* PLL Registers */ + +#define PLL_CTL 0xffc00000 /* PLL Control Register */ +#define PLL_DIV 0xffc00004 /* PLL Divisor Register */ +#define VR_CTL 0xffc00008 /* Voltage Regulator Control Register */ +#define PLL_STAT 0xffc0000c /* PLL Status Register */ +#define PLL_LOCKCNT 0xffc00010 /* PLL Lock Count Register */ + +/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */ + +#define CHIPID 0xffc00014 +/* CHIPID Masks */ +#define CHIPID_VERSION 0xF0000000 +#define CHIPID_FAMILY 0x0FFFF000 +#define CHIPID_MANUFACTURE 0x00000FFE + +/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */ + +#define SWRST 0xffc00100 /* Software Reset Register */ +#define SYSCR 0xffc00104 /* System Configuration register */ + +/* SIC Registers */ + +#define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */ +#define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */ +#define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */ +#define SIC_ISR0 0xffc00118 /* System Interrupt Status Register 0 */ +#define SIC_ISR1 0xffc0011c /* System Interrupt Status Register 1 */ +#define SIC_ISR2 0xffc00120 /* System Interrupt Status Register 2 */ +#define SIC_IWR0 0xffc00124 /* System Interrupt Wakeup Register 0 */ +#define SIC_IWR1 0xffc00128 /* System Interrupt Wakeup Register 1 */ +#define SIC_IWR2 0xffc0012c /* System Interrupt Wakeup Register 2 */ +#define SIC_IAR0 0xffc00130 /* System Interrupt Assignment Register 0 */ +#define SIC_IAR1 0xffc00134 /* System Interrupt Assignment Register 1 */ +#define SIC_IAR2 0xffc00138 /* System Interrupt Assignment Register 2 */ +#define SIC_IAR3 0xffc0013c /* System Interrupt Assignment Register 3 */ +#define SIC_IAR4 0xffc00140 /* System Interrupt Assignment Register 4 */ +#define SIC_IAR5 0xffc00144 /* System Interrupt Assignment Register 5 */ +#define SIC_IAR6 0xffc00148 /* System Interrupt Assignment Register 6 */ +#define SIC_IAR7 0xffc0014c /* System Interrupt Assignment Register 7 */ +#define SIC_IAR8 0xffc00150 /* System Interrupt Assignment Register 8 */ +#define SIC_IAR9 0xffc00154 /* System Interrupt Assignment Register 9 */ +#define SIC_IAR10 0xffc00158 /* System Interrupt Assignment Register 10 */ +#define SIC_IAR11 0xffc0015c /* System Interrupt Assignment Register 11 */ + +/* Watchdog Timer Registers */ + +#define WDOG_CTL 0xffc00200 /* Watchdog Control Register */ +#define WDOG_CNT 0xffc00204 /* Watchdog Count Register */ +#define WDOG_STAT 0xffc00208 /* Watchdog Status Register */ + +/* RTC Registers */ + +#define RTC_STAT 0xffc00300 /* RTC Status Register */ +#define RTC_ICTL 0xffc00304 /* RTC Interrupt Control Register */ +#define RTC_ISTAT 0xffc00308 /* RTC Interrupt Status Register */ +#define RTC_SWCNT 0xffc0030c /* RTC Stopwatch Count Register */ +#define RTC_ALARM 0xffc00310 /* RTC Alarm Register */ +#define RTC_PREN 0xffc00314 /* RTC Prescaler Enable Register */ + +/* UART0 Registers */ + +#define UART0_DLL 0xffc00400 /* Divisor Latch Low Byte */ +#define UART0_DLH 0xffc00404 /* Divisor Latch High Byte */ +#define UART0_GCTL 0xffc00408 /* Global Control Register */ +#define UART0_LCR 0xffc0040c /* Line Control Register */ +#define UART0_MCR 0xffc00410 /* Modem Control Register */ +#define UART0_LSR 0xffc00414 /* Line Status Register */ +#define UART0_MSR 0xffc00418 /* Modem Status Register */ +#define UART0_SCR 0xffc0041c /* Scratch Register */ +#define UART0_IER_SET 0xffc00420 /* Interrupt Enable Register Set */ +#define UART0_IER_CLEAR 0xffc00424 /* Interrupt Enable Register Clear */ +#define UART0_THR 0xffc00428 /* Transmit Hold Register */ +#define UART0_RBR 0xffc0042c /* Receive Buffer Register */ + +/* SPI0 Registers */ + +#define SPI0_REGBASE 0xffc00500 +#define SPI0_CTL 0xffc00500 /* SPI0 Control Register */ +#define SPI0_FLG 0xffc00504 /* SPI0 Flag Register */ +#define SPI0_STAT 0xffc00508 /* SPI0 Status Register */ +#define SPI0_TDBR 0xffc0050c /* SPI0 Transmit Data Buffer Register */ +#define SPI0_RDBR 0xffc00510 /* SPI0 Receive Data Buffer Register */ +#define SPI0_BAUD 0xffc00514 /* SPI0 Baud Rate Register */ +#define SPI0_SHADOW 0xffc00518 /* SPI0 Receive Data Buffer Shadow Register */ + +/* Timer Group of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */ + +/* Two Wire Interface Registers (TWI0) */ + +#define TWI0_REGBASE 0xffc00700 +#define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */ +#define TWI0_CONTROL 0xffc00704 /* TWI Control Register */ +#define TWI0_SLAVE_CTRL 0xffc00708 /* TWI Slave Mode Control Register */ +#define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */ +#define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */ +#define TWI0_MASTER_CTRL 0xffc00714 /* TWI Master Mode Control Register */ +#define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */ +#define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */ +#define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */ +#define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */ +#define TWI0_FIFO_CTRL 0xffc00728 /* TWI FIFO Control Register */ +#define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */ +#define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */ +#define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */ +#define TWI0_RCV_DATA8 0xffc00788 /* TWI FIFO Receive Data Single Byte Register */ +#define TWI0_RCV_DATA16 0xffc0078c /* TWI FIFO Receive Data Double Byte Register */ + +/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */ + +/* SPORT1 Registers */ + +#define SPORT1_TCR1 0xffc00900 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_TCR2 0xffc00904 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_TCLKDIV 0xffc00908 /* SPORT1 Transmit Serial Clock Divider Register */ +#define SPORT1_TFSDIV 0xffc0090c /* SPORT1 Transmit Frame Sync Divider Register */ +#define SPORT1_TX 0xffc00910 /* SPORT1 Transmit Data Register */ +#define SPORT1_RX 0xffc00918 /* SPORT1 Receive Data Register */ +#define SPORT1_RCR1 0xffc00920 /* SPORT1 Receive Configuration 1 Register */ +#define SPORT1_RCR2 0xffc00924 /* SPORT1 Receive Configuration 2 Register */ +#define SPORT1_RCLKDIV 0xffc00928 /* SPORT1 Receive Serial Clock Divider Register */ +#define SPORT1_RFSDIV 0xffc0092c /* SPORT1 Receive Frame Sync Divider Register */ +#define SPORT1_STAT 0xffc00930 /* SPORT1 Status Register */ +#define SPORT1_CHNL 0xffc00934 /* SPORT1 Current Channel Register */ +#define SPORT1_MCMC1 0xffc00938 /* SPORT1 Multi channel Configuration Register 1 */ +#define SPORT1_MCMC2 0xffc0093c /* SPORT1 Multi channel Configuration Register 2 */ +#define SPORT1_MTCS0 0xffc00940 /* SPORT1 Multi channel Transmit Select Register 0 */ +#define SPORT1_MTCS1 0xffc00944 /* SPORT1 Multi channel Transmit Select Register 1 */ +#define SPORT1_MTCS2 0xffc00948 /* SPORT1 Multi channel Transmit Select Register 2 */ +#define SPORT1_MTCS3 0xffc0094c /* SPORT1 Multi channel Transmit Select Register 3 */ +#define SPORT1_MRCS0 0xffc00950 /* SPORT1 Multi channel Receive Select Register 0 */ +#define SPORT1_MRCS1 0xffc00954 /* SPORT1 Multi channel Receive Select Register 1 */ +#define SPORT1_MRCS2 0xffc00958 /* SPORT1 Multi channel Receive Select Register 2 */ +#define SPORT1_MRCS3 0xffc0095c /* SPORT1 Multi channel Receive Select Register 3 */ + +/* Asynchronous Memory Control Registers */ + +#define EBIU_AMGCTL 0xffc00a00 /* Asynchronous Memory Global Control Register */ +#define EBIU_AMBCTL0 0xffc00a04 /* Asynchronous Memory Bank Control Register */ +#define EBIU_AMBCTL1 0xffc00a08 /* Asynchronous Memory Bank Control Register */ +#define EBIU_MBSCTL 0xffc00a0c /* Asynchronous Memory Bank Select Control Register */ +#define EBIU_ARBSTAT 0xffc00a10 /* Asynchronous Memory Arbiter Status Register */ +#define EBIU_MODE 0xffc00a14 /* Asynchronous Mode Control Register */ +#define EBIU_FCTL 0xffc00a18 /* Asynchronous Memory Flash Control Register */ + +/* DDR Memory Control Registers */ + +#define EBIU_DDRCTL0 0xffc00a20 /* DDR Memory Control 0 Register */ +#define EBIU_DDRCTL1 0xffc00a24 /* DDR Memory Control 1 Register */ +#define EBIU_DDRCTL2 0xffc00a28 /* DDR Memory Control 2 Register */ +#define EBIU_DDRCTL3 0xffc00a2c /* DDR Memory Control 3 Register */ +#define EBIU_DDRQUE 0xffc00a30 /* DDR Queue Configuration Register */ +#define EBIU_ERRADD 0xffc00a34 /* DDR Error Address Register */ +#define EBIU_ERRMST 0xffc00a38 /* DDR Error Master Register */ +#define EBIU_RSTCTL 0xffc00a3c /* DDR Reset Control Register */ + +/* DDR BankRead and Write Count Registers */ + +#define EBIU_DDRBRC0 0xffc00a60 /* DDR Bank0 Read Count Register */ +#define EBIU_DDRBRC1 0xffc00a64 /* DDR Bank1 Read Count Register */ +#define EBIU_DDRBRC2 0xffc00a68 /* DDR Bank2 Read Count Register */ +#define EBIU_DDRBRC3 0xffc00a6c /* DDR Bank3 Read Count Register */ +#define EBIU_DDRBRC4 0xffc00a70 /* DDR Bank4 Read Count Register */ +#define EBIU_DDRBRC5 0xffc00a74 /* DDR Bank5 Read Count Register */ +#define EBIU_DDRBRC6 0xffc00a78 /* DDR Bank6 Read Count Register */ +#define EBIU_DDRBRC7 0xffc00a7c /* DDR Bank7 Read Count Register */ +#define EBIU_DDRBWC0 0xffc00a80 /* DDR Bank0 Write Count Register */ +#define EBIU_DDRBWC1 0xffc00a84 /* DDR Bank1 Write Count Register */ +#define EBIU_DDRBWC2 0xffc00a88 /* DDR Bank2 Write Count Register */ +#define EBIU_DDRBWC3 0xffc00a8c /* DDR Bank3 Write Count Register */ +#define EBIU_DDRBWC4 0xffc00a90 /* DDR Bank4 Write Count Register */ +#define EBIU_DDRBWC5 0xffc00a94 /* DDR Bank5 Write Count Register */ +#define EBIU_DDRBWC6 0xffc00a98 /* DDR Bank6 Write Count Register */ +#define EBIU_DDRBWC7 0xffc00a9c /* DDR Bank7 Write Count Register */ +#define EBIU_DDRACCT 0xffc00aa0 /* DDR Activation Count Register */ +#define EBIU_DDRTACT 0xffc00aa8 /* DDR Turn Around Count Register */ +#define EBIU_DDRARCT 0xffc00aac /* DDR Auto-refresh Count Register */ +#define EBIU_DDRGC0 0xffc00ab0 /* DDR Grant Count 0 Register */ +#define EBIU_DDRGC1 0xffc00ab4 /* DDR Grant Count 1 Register */ +#define EBIU_DDRGC2 0xffc00ab8 /* DDR Grant Count 2 Register */ +#define EBIU_DDRGC3 0xffc00abc /* DDR Grant Count 3 Register */ +#define EBIU_DDRMCEN 0xffc00ac0 /* DDR Metrics Counter Enable Register */ +#define EBIU_DDRMCCL 0xffc00ac4 /* DDR Metrics Counter Clear Register */ + +/* DMAC0 Registers */ + +#define DMAC0_TCPER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */ +#define DMAC0_TCCNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */ + +/* DMA Channel 0 Registers */ + +#define DMA0_NEXT_DESC_PTR 0xffc00c00 /* DMA Channel 0 Next Descriptor Pointer Register */ +#define DMA0_START_ADDR 0xffc00c04 /* DMA Channel 0 Start Address Register */ +#define DMA0_CONFIG 0xffc00c08 /* DMA Channel 0 Configuration Register */ +#define DMA0_X_COUNT 0xffc00c10 /* DMA Channel 0 X Count Register */ +#define DMA0_X_MODIFY 0xffc00c14 /* DMA Channel 0 X Modify Register */ +#define DMA0_Y_COUNT 0xffc00c18 /* DMA Channel 0 Y Count Register */ +#define DMA0_Y_MODIFY 0xffc00c1c /* DMA Channel 0 Y Modify Register */ +#define DMA0_CURR_DESC_PTR 0xffc00c20 /* DMA Channel 0 Current Descriptor Pointer Register */ +#define DMA0_CURR_ADDR 0xffc00c24 /* DMA Channel 0 Current Address Register */ +#define DMA0_IRQ_STATUS 0xffc00c28 /* DMA Channel 0 Interrupt/Status Register */ +#define DMA0_PERIPHERAL_MAP 0xffc00c2c /* DMA Channel 0 Peripheral Map Register */ +#define DMA0_CURR_X_COUNT 0xffc00c30 /* DMA Channel 0 Current X Count Register */ +#define DMA0_CURR_Y_COUNT 0xffc00c38 /* DMA Channel 0 Current Y Count Register */ + +/* DMA Channel 1 Registers */ + +#define DMA1_NEXT_DESC_PTR 0xffc00c40 /* DMA Channel 1 Next Descriptor Pointer Register */ +#define DMA1_START_ADDR 0xffc00c44 /* DMA Channel 1 Start Address Register */ +#define DMA1_CONFIG 0xffc00c48 /* DMA Channel 1 Configuration Register */ +#define DMA1_X_COUNT 0xffc00c50 /* DMA Channel 1 X Count Register */ +#define DMA1_X_MODIFY 0xffc00c54 /* DMA Channel 1 X Modify Register */ +#define DMA1_Y_COUNT 0xffc00c58 /* DMA Channel 1 Y Count Register */ +#define DMA1_Y_MODIFY 0xffc00c5c /* DMA Channel 1 Y Modify Register */ +#define DMA1_CURR_DESC_PTR 0xffc00c60 /* DMA Channel 1 Current Descriptor Pointer Register */ +#define DMA1_CURR_ADDR 0xffc00c64 /* DMA Channel 1 Current Address Register */ +#define DMA1_IRQ_STATUS 0xffc00c68 /* DMA Channel 1 Interrupt/Status Register */ +#define DMA1_PERIPHERAL_MAP 0xffc00c6c /* DMA Channel 1 Peripheral Map Register */ +#define DMA1_CURR_X_COUNT 0xffc00c70 /* DMA Channel 1 Current X Count Register */ +#define DMA1_CURR_Y_COUNT 0xffc00c78 /* DMA Channel 1 Current Y Count Register */ + +/* DMA Channel 2 Registers */ + +#define DMA2_NEXT_DESC_PTR 0xffc00c80 /* DMA Channel 2 Next Descriptor Pointer Register */ +#define DMA2_START_ADDR 0xffc00c84 /* DMA Channel 2 Start Address Register */ +#define DMA2_CONFIG 0xffc00c88 /* DMA Channel 2 Configuration Register */ +#define DMA2_X_COUNT 0xffc00c90 /* DMA Channel 2 X Count Register */ +#define DMA2_X_MODIFY 0xffc00c94 /* DMA Channel 2 X Modify Register */ +#define DMA2_Y_COUNT 0xffc00c98 /* DMA Channel 2 Y Count Register */ +#define DMA2_Y_MODIFY 0xffc00c9c /* DMA Channel 2 Y Modify Register */ +#define DMA2_CURR_DESC_PTR 0xffc00ca0 /* DMA Channel 2 Current Descriptor Pointer Register */ +#define DMA2_CURR_ADDR 0xffc00ca4 /* DMA Channel 2 Current Address Register */ +#define DMA2_IRQ_STATUS 0xffc00ca8 /* DMA Channel 2 Interrupt/Status Register */ +#define DMA2_PERIPHERAL_MAP 0xffc00cac /* DMA Channel 2 Peripheral Map Register */ +#define DMA2_CURR_X_COUNT 0xffc00cb0 /* DMA Channel 2 Current X Count Register */ +#define DMA2_CURR_Y_COUNT 0xffc00cb8 /* DMA Channel 2 Current Y Count Register */ + +/* DMA Channel 3 Registers */ + +#define DMA3_NEXT_DESC_PTR 0xffc00cc0 /* DMA Channel 3 Next Descriptor Pointer Register */ +#define DMA3_START_ADDR 0xffc00cc4 /* DMA Channel 3 Start Address Register */ +#define DMA3_CONFIG 0xffc00cc8 /* DMA Channel 3 Configuration Register */ +#define DMA3_X_COUNT 0xffc00cd0 /* DMA Channel 3 X Count Register */ +#define DMA3_X_MODIFY 0xffc00cd4 /* DMA Channel 3 X Modify Register */ +#define DMA3_Y_COUNT 0xffc00cd8 /* DMA Channel 3 Y Count Register */ +#define DMA3_Y_MODIFY 0xffc00cdc /* DMA Channel 3 Y Modify Register */ +#define DMA3_CURR_DESC_PTR 0xffc00ce0 /* DMA Channel 3 Current Descriptor Pointer Register */ +#define DMA3_CURR_ADDR 0xffc00ce4 /* DMA Channel 3 Current Address Register */ +#define DMA3_IRQ_STATUS 0xffc00ce8 /* DMA Channel 3 Interrupt/Status Register */ +#define DMA3_PERIPHERAL_MAP 0xffc00cec /* DMA Channel 3 Peripheral Map Register */ +#define DMA3_CURR_X_COUNT 0xffc00cf0 /* DMA Channel 3 Current X Count Register */ +#define DMA3_CURR_Y_COUNT 0xffc00cf8 /* DMA Channel 3 Current Y Count Register */ + +/* DMA Channel 4 Registers */ + +#define DMA4_NEXT_DESC_PTR 0xffc00d00 /* DMA Channel 4 Next Descriptor Pointer Register */ +#define DMA4_START_ADDR 0xffc00d04 /* DMA Channel 4 Start Address Register */ +#define DMA4_CONFIG 0xffc00d08 /* DMA Channel 4 Configuration Register */ +#define DMA4_X_COUNT 0xffc00d10 /* DMA Channel 4 X Count Register */ +#define DMA4_X_MODIFY 0xffc00d14 /* DMA Channel 4 X Modify Register */ +#define DMA4_Y_COUNT 0xffc00d18 /* DMA Channel 4 Y Count Register */ +#define DMA4_Y_MODIFY 0xffc00d1c /* DMA Channel 4 Y Modify Register */ +#define DMA4_CURR_DESC_PTR 0xffc00d20 /* DMA Channel 4 Current Descriptor Pointer Register */ +#define DMA4_CURR_ADDR 0xffc00d24 /* DMA Channel 4 Current Address Register */ +#define DMA4_IRQ_STATUS 0xffc00d28 /* DMA Channel 4 Interrupt/Status Register */ +#define DMA4_PERIPHERAL_MAP 0xffc00d2c /* DMA Channel 4 Peripheral Map Register */ +#define DMA4_CURR_X_COUNT 0xffc00d30 /* DMA Channel 4 Current X Count Register */ +#define DMA4_CURR_Y_COUNT 0xffc00d38 /* DMA Channel 4 Current Y Count Register */ + +/* DMA Channel 5 Registers */ + +#define DMA5_NEXT_DESC_PTR 0xffc00d40 /* DMA Channel 5 Next Descriptor Pointer Register */ +#define DMA5_START_ADDR 0xffc00d44 /* DMA Channel 5 Start Address Register */ +#define DMA5_CONFIG 0xffc00d48 /* DMA Channel 5 Configuration Register */ +#define DMA5_X_COUNT 0xffc00d50 /* DMA Channel 5 X Count Register */ +#define DMA5_X_MODIFY 0xffc00d54 /* DMA Channel 5 X Modify Register */ +#define DMA5_Y_COUNT 0xffc00d58 /* DMA Channel 5 Y Count Register */ +#define DMA5_Y_MODIFY 0xffc00d5c /* DMA Channel 5 Y Modify Register */ +#define DMA5_CURR_DESC_PTR 0xffc00d60 /* DMA Channel 5 Current Descriptor Pointer Register */ +#define DMA5_CURR_ADDR 0xffc00d64 /* DMA Channel 5 Current Address Register */ +#define DMA5_IRQ_STATUS 0xffc00d68 /* DMA Channel 5 Interrupt/Status Register */ +#define DMA5_PERIPHERAL_MAP 0xffc00d6c /* DMA Channel 5 Peripheral Map Register */ +#define DMA5_CURR_X_COUNT 0xffc00d70 /* DMA Channel 5 Current X Count Register */ +#define DMA5_CURR_Y_COUNT 0xffc00d78 /* DMA Channel 5 Current Y Count Register */ + +/* DMA Channel 6 Registers */ + +#define DMA6_NEXT_DESC_PTR 0xffc00d80 /* DMA Channel 6 Next Descriptor Pointer Register */ +#define DMA6_START_ADDR 0xffc00d84 /* DMA Channel 6 Start Address Register */ +#define DMA6_CONFIG 0xffc00d88 /* DMA Channel 6 Configuration Register */ +#define DMA6_X_COUNT 0xffc00d90 /* DMA Channel 6 X Count Register */ +#define DMA6_X_MODIFY 0xffc00d94 /* DMA Channel 6 X Modify Register */ +#define DMA6_Y_COUNT 0xffc00d98 /* DMA Channel 6 Y Count Register */ +#define DMA6_Y_MODIFY 0xffc00d9c /* DMA Channel 6 Y Modify Register */ +#define DMA6_CURR_DESC_PTR 0xffc00da0 /* DMA Channel 6 Current Descriptor Pointer Register */ +#define DMA6_CURR_ADDR 0xffc00da4 /* DMA Channel 6 Current Address Register */ +#define DMA6_IRQ_STATUS 0xffc00da8 /* DMA Channel 6 Interrupt/Status Register */ +#define DMA6_PERIPHERAL_MAP 0xffc00dac /* DMA Channel 6 Peripheral Map Register */ +#define DMA6_CURR_X_COUNT 0xffc00db0 /* DMA Channel 6 Current X Count Register */ +#define DMA6_CURR_Y_COUNT 0xffc00db8 /* DMA Channel 6 Current Y Count Register */ + +/* DMA Channel 7 Registers */ + +#define DMA7_NEXT_DESC_PTR 0xffc00dc0 /* DMA Channel 7 Next Descriptor Pointer Register */ +#define DMA7_START_ADDR 0xffc00dc4 /* DMA Channel 7 Start Address Register */ +#define DMA7_CONFIG 0xffc00dc8 /* DMA Channel 7 Configuration Register */ +#define DMA7_X_COUNT 0xffc00dd0 /* DMA Channel 7 X Count Register */ +#define DMA7_X_MODIFY 0xffc00dd4 /* DMA Channel 7 X Modify Register */ +#define DMA7_Y_COUNT 0xffc00dd8 /* DMA Channel 7 Y Count Register */ +#define DMA7_Y_MODIFY 0xffc00ddc /* DMA Channel 7 Y Modify Register */ +#define DMA7_CURR_DESC_PTR 0xffc00de0 /* DMA Channel 7 Current Descriptor Pointer Register */ +#define DMA7_CURR_ADDR 0xffc00de4 /* DMA Channel 7 Current Address Register */ +#define DMA7_IRQ_STATUS 0xffc00de8 /* DMA Channel 7 Interrupt/Status Register */ +#define DMA7_PERIPHERAL_MAP 0xffc00dec /* DMA Channel 7 Peripheral Map Register */ +#define DMA7_CURR_X_COUNT 0xffc00df0 /* DMA Channel 7 Current X Count Register */ +#define DMA7_CURR_Y_COUNT 0xffc00df8 /* DMA Channel 7 Current Y Count Register */ + +/* DMA Channel 8 Registers */ + +#define DMA8_NEXT_DESC_PTR 0xffc00e00 /* DMA Channel 8 Next Descriptor Pointer Register */ +#define DMA8_START_ADDR 0xffc00e04 /* DMA Channel 8 Start Address Register */ +#define DMA8_CONFIG 0xffc00e08 /* DMA Channel 8 Configuration Register */ +#define DMA8_X_COUNT 0xffc00e10 /* DMA Channel 8 X Count Register */ +#define DMA8_X_MODIFY 0xffc00e14 /* DMA Channel 8 X Modify Register */ +#define DMA8_Y_COUNT 0xffc00e18 /* DMA Channel 8 Y Count Register */ +#define DMA8_Y_MODIFY 0xffc00e1c /* DMA Channel 8 Y Modify Register */ +#define DMA8_CURR_DESC_PTR 0xffc00e20 /* DMA Channel 8 Current Descriptor Pointer Register */ +#define DMA8_CURR_ADDR 0xffc00e24 /* DMA Channel 8 Current Address Register */ +#define DMA8_IRQ_STATUS 0xffc00e28 /* DMA Channel 8 Interrupt/Status Register */ +#define DMA8_PERIPHERAL_MAP 0xffc00e2c /* DMA Channel 8 Peripheral Map Register */ +#define DMA8_CURR_X_COUNT 0xffc00e30 /* DMA Channel 8 Current X Count Register */ +#define DMA8_CURR_Y_COUNT 0xffc00e38 /* DMA Channel 8 Current Y Count Register */ + +/* DMA Channel 9 Registers */ + +#define DMA9_NEXT_DESC_PTR 0xffc00e40 /* DMA Channel 9 Next Descriptor Pointer Register */ +#define DMA9_START_ADDR 0xffc00e44 /* DMA Channel 9 Start Address Register */ +#define DMA9_CONFIG 0xffc00e48 /* DMA Channel 9 Configuration Register */ +#define DMA9_X_COUNT 0xffc00e50 /* DMA Channel 9 X Count Register */ +#define DMA9_X_MODIFY 0xffc00e54 /* DMA Channel 9 X Modify Register */ +#define DMA9_Y_COUNT 0xffc00e58 /* DMA Channel 9 Y Count Register */ +#define DMA9_Y_MODIFY 0xffc00e5c /* DMA Channel 9 Y Modify Register */ +#define DMA9_CURR_DESC_PTR 0xffc00e60 /* DMA Channel 9 Current Descriptor Pointer Register */ +#define DMA9_CURR_ADDR 0xffc00e64 /* DMA Channel 9 Current Address Register */ +#define DMA9_IRQ_STATUS 0xffc00e68 /* DMA Channel 9 Interrupt/Status Register */ +#define DMA9_PERIPHERAL_MAP 0xffc00e6c /* DMA Channel 9 Peripheral Map Register */ +#define DMA9_CURR_X_COUNT 0xffc00e70 /* DMA Channel 9 Current X Count Register */ +#define DMA9_CURR_Y_COUNT 0xffc00e78 /* DMA Channel 9 Current Y Count Register */ + +/* DMA Channel 10 Registers */ + +#define DMA10_NEXT_DESC_PTR 0xffc00e80 /* DMA Channel 10 Next Descriptor Pointer Register */ +#define DMA10_START_ADDR 0xffc00e84 /* DMA Channel 10 Start Address Register */ +#define DMA10_CONFIG 0xffc00e88 /* DMA Channel 10 Configuration Register */ +#define DMA10_X_COUNT 0xffc00e90 /* DMA Channel 10 X Count Register */ +#define DMA10_X_MODIFY 0xffc00e94 /* DMA Channel 10 X Modify Register */ +#define DMA10_Y_COUNT 0xffc00e98 /* DMA Channel 10 Y Count Register */ +#define DMA10_Y_MODIFY 0xffc00e9c /* DMA Channel 10 Y Modify Register */ +#define DMA10_CURR_DESC_PTR 0xffc00ea0 /* DMA Channel 10 Current Descriptor Pointer Register */ +#define DMA10_CURR_ADDR 0xffc00ea4 /* DMA Channel 10 Current Address Register */ +#define DMA10_IRQ_STATUS 0xffc00ea8 /* DMA Channel 10 Interrupt/Status Register */ +#define DMA10_PERIPHERAL_MAP 0xffc00eac /* DMA Channel 10 Peripheral Map Register */ +#define DMA10_CURR_X_COUNT 0xffc00eb0 /* DMA Channel 10 Current X Count Register */ +#define DMA10_CURR_Y_COUNT 0xffc00eb8 /* DMA Channel 10 Current Y Count Register */ + +/* DMA Channel 11 Registers */ + +#define DMA11_NEXT_DESC_PTR 0xffc00ec0 /* DMA Channel 11 Next Descriptor Pointer Register */ +#define DMA11_START_ADDR 0xffc00ec4 /* DMA Channel 11 Start Address Register */ +#define DMA11_CONFIG 0xffc00ec8 /* DMA Channel 11 Configuration Register */ +#define DMA11_X_COUNT 0xffc00ed0 /* DMA Channel 11 X Count Register */ +#define DMA11_X_MODIFY 0xffc00ed4 /* DMA Channel 11 X Modify Register */ +#define DMA11_Y_COUNT 0xffc00ed8 /* DMA Channel 11 Y Count Register */ +#define DMA11_Y_MODIFY 0xffc00edc /* DMA Channel 11 Y Modify Register */ +#define DMA11_CURR_DESC_PTR 0xffc00ee0 /* DMA Channel 11 Current Descriptor Pointer Register */ +#define DMA11_CURR_ADDR 0xffc00ee4 /* DMA Channel 11 Current Address Register */ +#define DMA11_IRQ_STATUS 0xffc00ee8 /* DMA Channel 11 Interrupt/Status Register */ +#define DMA11_PERIPHERAL_MAP 0xffc00eec /* DMA Channel 11 Peripheral Map Register */ +#define DMA11_CURR_X_COUNT 0xffc00ef0 /* DMA Channel 11 Current X Count Register */ +#define DMA11_CURR_Y_COUNT 0xffc00ef8 /* DMA Channel 11 Current Y Count Register */ + +/* MDMA Stream 0 Registers */ + +#define MDMA_D0_NEXT_DESC_PTR 0xffc00f00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */ +#define MDMA_D0_START_ADDR 0xffc00f04 /* Memory DMA Stream 0 Destination Start Address Register */ +#define MDMA_D0_CONFIG 0xffc00f08 /* Memory DMA Stream 0 Destination Configuration Register */ +#define MDMA_D0_X_COUNT 0xffc00f10 /* Memory DMA Stream 0 Destination X Count Register */ +#define MDMA_D0_X_MODIFY 0xffc00f14 /* Memory DMA Stream 0 Destination X Modify Register */ +#define MDMA_D0_Y_COUNT 0xffc00f18 /* Memory DMA Stream 0 Destination Y Count Register */ +#define MDMA_D0_Y_MODIFY 0xffc00f1c /* Memory DMA Stream 0 Destination Y Modify Register */ +#define MDMA_D0_CURR_DESC_PTR 0xffc00f20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */ +#define MDMA_D0_CURR_ADDR 0xffc00f24 /* Memory DMA Stream 0 Destination Current Address Register */ +#define MDMA_D0_IRQ_STATUS 0xffc00f28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */ +#define MDMA_D0_PERIPHERAL_MAP 0xffc00f2c /* Memory DMA Stream 0 Destination Peripheral Map Register */ +#define MDMA_D0_CURR_X_COUNT 0xffc00f30 /* Memory DMA Stream 0 Destination Current X Count Register */ +#define MDMA_D0_CURR_Y_COUNT 0xffc00f38 /* Memory DMA Stream 0 Destination Current Y Count Register */ +#define MDMA_S0_NEXT_DESC_PTR 0xffc00f40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */ +#define MDMA_S0_START_ADDR 0xffc00f44 /* Memory DMA Stream 0 Source Start Address Register */ +#define MDMA_S0_CONFIG 0xffc00f48 /* Memory DMA Stream 0 Source Configuration Register */ +#define MDMA_S0_X_COUNT 0xffc00f50 /* Memory DMA Stream 0 Source X Count Register */ +#define MDMA_S0_X_MODIFY 0xffc00f54 /* Memory DMA Stream 0 Source X Modify Register */ +#define MDMA_S0_Y_COUNT 0xffc00f58 /* Memory DMA Stream 0 Source Y Count Register */ +#define MDMA_S0_Y_MODIFY 0xffc00f5c /* Memory DMA Stream 0 Source Y Modify Register */ +#define MDMA_S0_CURR_DESC_PTR 0xffc00f60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */ +#define MDMA_S0_CURR_ADDR 0xffc00f64 /* Memory DMA Stream 0 Source Current Address Register */ +#define MDMA_S0_IRQ_STATUS 0xffc00f68 /* Memory DMA Stream 0 Source Interrupt/Status Register */ +#define MDMA_S0_PERIPHERAL_MAP 0xffc00f6c /* Memory DMA Stream 0 Source Peripheral Map Register */ +#define MDMA_S0_CURR_X_COUNT 0xffc00f70 /* Memory DMA Stream 0 Source Current X Count Register */ +#define MDMA_S0_CURR_Y_COUNT 0xffc00f78 /* Memory DMA Stream 0 Source Current Y Count Register */ + +/* MDMA Stream 1 Registers */ + +#define MDMA_D1_NEXT_DESC_PTR 0xffc00f80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */ +#define MDMA_D1_START_ADDR 0xffc00f84 /* Memory DMA Stream 1 Destination Start Address Register */ +#define MDMA_D1_CONFIG 0xffc00f88 /* Memory DMA Stream 1 Destination Configuration Register */ +#define MDMA_D1_X_COUNT 0xffc00f90 /* Memory DMA Stream 1 Destination X Count Register */ +#define MDMA_D1_X_MODIFY 0xffc00f94 /* Memory DMA Stream 1 Destination X Modify Register */ +#define MDMA_D1_Y_COUNT 0xffc00f98 /* Memory DMA Stream 1 Destination Y Count Register */ +#define MDMA_D1_Y_MODIFY 0xffc00f9c /* Memory DMA Stream 1 Destination Y Modify Register */ +#define MDMA_D1_CURR_DESC_PTR 0xffc00fa0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */ +#define MDMA_D1_CURR_ADDR 0xffc00fa4 /* Memory DMA Stream 1 Destination Current Address Register */ +#define MDMA_D1_IRQ_STATUS 0xffc00fa8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */ +#define MDMA_D1_PERIPHERAL_MAP 0xffc00fac /* Memory DMA Stream 1 Destination Peripheral Map Register */ +#define MDMA_D1_CURR_X_COUNT 0xffc00fb0 /* Memory DMA Stream 1 Destination Current X Count Register */ +#define MDMA_D1_CURR_Y_COUNT 0xffc00fb8 /* Memory DMA Stream 1 Destination Current Y Count Register */ +#define MDMA_S1_NEXT_DESC_PTR 0xffc00fc0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */ +#define MDMA_S1_START_ADDR 0xffc00fc4 /* Memory DMA Stream 1 Source Start Address Register */ +#define MDMA_S1_CONFIG 0xffc00fc8 /* Memory DMA Stream 1 Source Configuration Register */ +#define MDMA_S1_X_COUNT 0xffc00fd0 /* Memory DMA Stream 1 Source X Count Register */ +#define MDMA_S1_X_MODIFY 0xffc00fd4 /* Memory DMA Stream 1 Source X Modify Register */ +#define MDMA_S1_Y_COUNT 0xffc00fd8 /* Memory DMA Stream 1 Source Y Count Register */ +#define MDMA_S1_Y_MODIFY 0xffc00fdc /* Memory DMA Stream 1 Source Y Modify Register */ +#define MDMA_S1_CURR_DESC_PTR 0xffc00fe0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */ +#define MDMA_S1_CURR_ADDR 0xffc00fe4 /* Memory DMA Stream 1 Source Current Address Register */ +#define MDMA_S1_IRQ_STATUS 0xffc00fe8 /* Memory DMA Stream 1 Source Interrupt/Status Register */ +#define MDMA_S1_PERIPHERAL_MAP 0xffc00fec /* Memory DMA Stream 1 Source Peripheral Map Register */ +#define MDMA_S1_CURR_X_COUNT 0xffc00ff0 /* Memory DMA Stream 1 Source Current X Count Register */ +#define MDMA_S1_CURR_Y_COUNT 0xffc00ff8 /* Memory DMA Stream 1 Source Current Y Count Register */ + +/* UART3 Registers */ + +#define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */ +#define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */ +#define UART3_GCTL 0xffc03108 /* Global Control Register */ +#define UART3_LCR 0xffc0310c /* Line Control Register */ +#define UART3_MCR 0xffc03110 /* Modem Control Register */ +#define UART3_LSR 0xffc03114 /* Line Status Register */ +#define UART3_MSR 0xffc03118 /* Modem Status Register */ +#define UART3_SCR 0xffc0311c /* Scratch Register */ +#define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */ +#define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */ +#define UART3_THR 0xffc03128 /* Transmit Hold Register */ +#define UART3_RBR 0xffc0312c /* Receive Buffer Register */ + +/* EPPI1 Registers */ + +#define EPPI1_STATUS 0xffc01300 /* EPPI1 Status Register */ +#define EPPI1_HCOUNT 0xffc01304 /* EPPI1 Horizontal Transfer Count Register */ +#define EPPI1_HDELAY 0xffc01308 /* EPPI1 Horizontal Delay Count Register */ +#define EPPI1_VCOUNT 0xffc0130c /* EPPI1 Vertical Transfer Count Register */ +#define EPPI1_VDELAY 0xffc01310 /* EPPI1 Vertical Delay Count Register */ +#define EPPI1_FRAME 0xffc01314 /* EPPI1 Lines per Frame Register */ +#define EPPI1_LINE 0xffc01318 /* EPPI1 Samples per Line Register */ +#define EPPI1_CLKDIV 0xffc0131c /* EPPI1 Clock Divide Register */ +#define EPPI1_CONTROL 0xffc01320 /* EPPI1 Control Register */ +#define EPPI1_FS1W_HBL 0xffc01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */ +#define EPPI1_FS1P_AVPL 0xffc01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */ +#define EPPI1_FS2W_LVB 0xffc0132c /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */ +#define EPPI1_FS2P_LAVF 0xffc01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */ +#define EPPI1_CLIP 0xffc01334 /* EPPI1 Clipping Register */ + +/* Port Interrupt 0 Registers (32-bit) */ + +#define PINT0_MASK_SET 0xffc01400 /* Pin Interrupt 0 Mask Set Register */ +#define PINT0_MASK_CLEAR 0xffc01404 /* Pin Interrupt 0 Mask Clear Register */ +#define PINT0_REQUEST 0xffc01408 /* Pin Interrupt 0 Interrupt Request Register */ +#define PINT0_ASSIGN 0xffc0140c /* Pin Interrupt 0 Port Assign Register */ +#define PINT0_EDGE_SET 0xffc01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */ +#define PINT0_EDGE_CLEAR 0xffc01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */ +#define PINT0_INVERT_SET 0xffc01418 /* Pin Interrupt 0 Inversion Set Register */ +#define PINT0_INVERT_CLEAR 0xffc0141c /* Pin Interrupt 0 Inversion Clear Register */ +#define PINT0_PINSTATE 0xffc01420 /* Pin Interrupt 0 Pin Status Register */ +#define PINT0_LATCH 0xffc01424 /* Pin Interrupt 0 Latch Register */ + +/* Port Interrupt 1 Registers (32-bit) */ + +#define PINT1_MASK_SET 0xffc01430 /* Pin Interrupt 1 Mask Set Register */ +#define PINT1_MASK_CLEAR 0xffc01434 /* Pin Interrupt 1 Mask Clear Register */ +#define PINT1_REQUEST 0xffc01438 /* Pin Interrupt 1 Interrupt Request Register */ +#define PINT1_ASSIGN 0xffc0143c /* Pin Interrupt 1 Port Assign Register */ +#define PINT1_EDGE_SET 0xffc01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */ +#define PINT1_EDGE_CLEAR 0xffc01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */ +#define PINT1_INVERT_SET 0xffc01448 /* Pin Interrupt 1 Inversion Set Register */ +#define PINT1_INVERT_CLEAR 0xffc0144c /* Pin Interrupt 1 Inversion Clear Register */ +#define PINT1_PINSTATE 0xffc01450 /* Pin Interrupt 1 Pin Status Register */ +#define PINT1_LATCH 0xffc01454 /* Pin Interrupt 1 Latch Register */ + +/* Port Interrupt 2 Registers (32-bit) */ + +#define PINT2_MASK_SET 0xffc01460 /* Pin Interrupt 2 Mask Set Register */ +#define PINT2_MASK_CLEAR 0xffc01464 /* Pin Interrupt 2 Mask Clear Register */ +#define PINT2_REQUEST 0xffc01468 /* Pin Interrupt 2 Interrupt Request Register */ +#define PINT2_ASSIGN 0xffc0146c /* Pin Interrupt 2 Port Assign Register */ +#define PINT2_EDGE_SET 0xffc01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */ +#define PINT2_EDGE_CLEAR 0xffc01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */ +#define PINT2_INVERT_SET 0xffc01478 /* Pin Interrupt 2 Inversion Set Register */ +#define PINT2_INVERT_CLEAR 0xffc0147c /* Pin Interrupt 2 Inversion Clear Register */ +#define PINT2_PINSTATE 0xffc01480 /* Pin Interrupt 2 Pin Status Register */ +#define PINT2_LATCH 0xffc01484 /* Pin Interrupt 2 Latch Register */ + +/* Port Interrupt 3 Registers (32-bit) */ + +#define PINT3_MASK_SET 0xffc01490 /* Pin Interrupt 3 Mask Set Register */ +#define PINT3_MASK_CLEAR 0xffc01494 /* Pin Interrupt 3 Mask Clear Register */ +#define PINT3_REQUEST 0xffc01498 /* Pin Interrupt 3 Interrupt Request Register */ +#define PINT3_ASSIGN 0xffc0149c /* Pin Interrupt 3 Port Assign Register */ +#define PINT3_EDGE_SET 0xffc014a0 /* Pin Interrupt 3 Edge-sensitivity Set Register */ +#define PINT3_EDGE_CLEAR 0xffc014a4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */ +#define PINT3_INVERT_SET 0xffc014a8 /* Pin Interrupt 3 Inversion Set Register */ +#define PINT3_INVERT_CLEAR 0xffc014ac /* Pin Interrupt 3 Inversion Clear Register */ +#define PINT3_PINSTATE 0xffc014b0 /* Pin Interrupt 3 Pin Status Register */ +#define PINT3_LATCH 0xffc014b4 /* Pin Interrupt 3 Latch Register */ + +/* Port A Registers */ + +#define PORTA_FER 0xffc014c0 /* Function Enable Register */ +#define PORTA 0xffc014c4 /* GPIO Data Register */ +#define PORTA_SET 0xffc014c8 /* GPIO Data Set Register */ +#define PORTA_CLEAR 0xffc014cc /* GPIO Data Clear Register */ +#define PORTA_DIR_SET 0xffc014d0 /* GPIO Direction Set Register */ +#define PORTA_DIR_CLEAR 0xffc014d4 /* GPIO Direction Clear Register */ +#define PORTA_INEN 0xffc014d8 /* GPIO Input Enable Register */ +#define PORTA_MUX 0xffc014dc /* Multiplexer Control Register */ + +/* Port B Registers */ + +#define PORTB_FER 0xffc014e0 /* Function Enable Register */ +#define PORTB 0xffc014e4 /* GPIO Data Register */ +#define PORTB_SET 0xffc014e8 /* GPIO Data Set Register */ +#define PORTB_CLEAR 0xffc014ec /* GPIO Data Clear Register */ +#define PORTB_DIR_SET 0xffc014f0 /* GPIO Direction Set Register */ +#define PORTB_DIR_CLEAR 0xffc014f4 /* GPIO Direction Clear Register */ +#define PORTB_INEN 0xffc014f8 /* GPIO Input Enable Register */ +#define PORTB_MUX 0xffc014fc /* Multiplexer Control Register */ + +/* Port C Registers */ + +#define PORTC_FER 0xffc01500 /* Function Enable Register */ +#define PORTC 0xffc01504 /* GPIO Data Register */ +#define PORTC_SET 0xffc01508 /* GPIO Data Set Register */ +#define PORTC_CLEAR 0xffc0150c /* GPIO Data Clear Register */ +#define PORTC_DIR_SET 0xffc01510 /* GPIO Direction Set Register */ +#define PORTC_DIR_CLEAR 0xffc01514 /* GPIO Direction Clear Register */ +#define PORTC_INEN 0xffc01518 /* GPIO Input Enable Register */ +#define PORTC_MUX 0xffc0151c /* Multiplexer Control Register */ + +/* Port D Registers */ + +#define PORTD_FER 0xffc01520 /* Function Enable Register */ +#define PORTD 0xffc01524 /* GPIO Data Register */ +#define PORTD_SET 0xffc01528 /* GPIO Data Set Register */ +#define PORTD_CLEAR 0xffc0152c /* GPIO Data Clear Register */ +#define PORTD_DIR_SET 0xffc01530 /* GPIO Direction Set Register */ +#define PORTD_DIR_CLEAR 0xffc01534 /* GPIO Direction Clear Register */ +#define PORTD_INEN 0xffc01538 /* GPIO Input Enable Register */ +#define PORTD_MUX 0xffc0153c /* Multiplexer Control Register */ + +/* Port E Registers */ + +#define PORTE_FER 0xffc01540 /* Function Enable Register */ +#define PORTE 0xffc01544 /* GPIO Data Register */ +#define PORTE_SET 0xffc01548 /* GPIO Data Set Register */ +#define PORTE_CLEAR 0xffc0154c /* GPIO Data Clear Register */ +#define PORTE_DIR_SET 0xffc01550 /* GPIO Direction Set Register */ +#define PORTE_DIR_CLEAR 0xffc01554 /* GPIO Direction Clear Register */ +#define PORTE_INEN 0xffc01558 /* GPIO Input Enable Register */ +#define PORTE_MUX 0xffc0155c /* Multiplexer Control Register */ + +/* Port F Registers */ + +#define PORTF_FER 0xffc01560 /* Function Enable Register */ +#define PORTF 0xffc01564 /* GPIO Data Register */ +#define PORTF_SET 0xffc01568 /* GPIO Data Set Register */ +#define PORTF_CLEAR 0xffc0156c /* GPIO Data Clear Register */ +#define PORTF_DIR_SET 0xffc01570 /* GPIO Direction Set Register */ +#define PORTF_DIR_CLEAR 0xffc01574 /* GPIO Direction Clear Register */ +#define PORTF_INEN 0xffc01578 /* GPIO Input Enable Register */ +#define PORTF_MUX 0xffc0157c /* Multiplexer Control Register */ + +/* Port G Registers */ + +#define PORTG_FER 0xffc01580 /* Function Enable Register */ +#define PORTG 0xffc01584 /* GPIO Data Register */ +#define PORTG_SET 0xffc01588 /* GPIO Data Set Register */ +#define PORTG_CLEAR 0xffc0158c /* GPIO Data Clear Register */ +#define PORTG_DIR_SET 0xffc01590 /* GPIO Direction Set Register */ +#define PORTG_DIR_CLEAR 0xffc01594 /* GPIO Direction Clear Register */ +#define PORTG_INEN 0xffc01598 /* GPIO Input Enable Register */ +#define PORTG_MUX 0xffc0159c /* Multiplexer Control Register */ + +/* Port H Registers */ + +#define PORTH_FER 0xffc015a0 /* Function Enable Register */ +#define PORTH 0xffc015a4 /* GPIO Data Register */ +#define PORTH_SET 0xffc015a8 /* GPIO Data Set Register */ +#define PORTH_CLEAR 0xffc015ac /* GPIO Data Clear Register */ +#define PORTH_DIR_SET 0xffc015b0 /* GPIO Direction Set Register */ +#define PORTH_DIR_CLEAR 0xffc015b4 /* GPIO Direction Clear Register */ +#define PORTH_INEN 0xffc015b8 /* GPIO Input Enable Register */ +#define PORTH_MUX 0xffc015bc /* Multiplexer Control Register */ + +/* Port I Registers */ + +#define PORTI_FER 0xffc015c0 /* Function Enable Register */ +#define PORTI 0xffc015c4 /* GPIO Data Register */ +#define PORTI_SET 0xffc015c8 /* GPIO Data Set Register */ +#define PORTI_CLEAR 0xffc015cc /* GPIO Data Clear Register */ +#define PORTI_DIR_SET 0xffc015d0 /* GPIO Direction Set Register */ +#define PORTI_DIR_CLEAR 0xffc015d4 /* GPIO Direction Clear Register */ +#define PORTI_INEN 0xffc015d8 /* GPIO Input Enable Register */ +#define PORTI_MUX 0xffc015dc /* Multiplexer Control Register */ + +/* Port J Registers */ + +#define PORTJ_FER 0xffc015e0 /* Function Enable Register */ +#define PORTJ 0xffc015e4 /* GPIO Data Register */ +#define PORTJ_SET 0xffc015e8 /* GPIO Data Set Register */ +#define PORTJ_CLEAR 0xffc015ec /* GPIO Data Clear Register */ +#define PORTJ_DIR_SET 0xffc015f0 /* GPIO Direction Set Register */ +#define PORTJ_DIR_CLEAR 0xffc015f4 /* GPIO Direction Clear Register */ +#define PORTJ_INEN 0xffc015f8 /* GPIO Input Enable Register */ +#define PORTJ_MUX 0xffc015fc /* Multiplexer Control Register */ + +/* PWM Timer Registers */ + +#define TIMER0_CONFIG 0xffc01600 /* Timer 0 Configuration Register */ +#define TIMER0_COUNTER 0xffc01604 /* Timer 0 Counter Register */ +#define TIMER0_PERIOD 0xffc01608 /* Timer 0 Period Register */ +#define TIMER0_WIDTH 0xffc0160c /* Timer 0 Width Register */ +#define TIMER1_CONFIG 0xffc01610 /* Timer 1 Configuration Register */ +#define TIMER1_COUNTER 0xffc01614 /* Timer 1 Counter Register */ +#define TIMER1_PERIOD 0xffc01618 /* Timer 1 Period Register */ +#define TIMER1_WIDTH 0xffc0161c /* Timer 1 Width Register */ +#define TIMER2_CONFIG 0xffc01620 /* Timer 2 Configuration Register */ +#define TIMER2_COUNTER 0xffc01624 /* Timer 2 Counter Register */ +#define TIMER2_PERIOD 0xffc01628 /* Timer 2 Period Register */ +#define TIMER2_WIDTH 0xffc0162c /* Timer 2 Width Register */ +#define TIMER3_CONFIG 0xffc01630 /* Timer 3 Configuration Register */ +#define TIMER3_COUNTER 0xffc01634 /* Timer 3 Counter Register */ +#define TIMER3_PERIOD 0xffc01638 /* Timer 3 Period Register */ +#define TIMER3_WIDTH 0xffc0163c /* Timer 3 Width Register */ +#define TIMER4_CONFIG 0xffc01640 /* Timer 4 Configuration Register */ +#define TIMER4_COUNTER 0xffc01644 /* Timer 4 Counter Register */ +#define TIMER4_PERIOD 0xffc01648 /* Timer 4 Period Register */ +#define TIMER4_WIDTH 0xffc0164c /* Timer 4 Width Register */ +#define TIMER5_CONFIG 0xffc01650 /* Timer 5 Configuration Register */ +#define TIMER5_COUNTER 0xffc01654 /* Timer 5 Counter Register */ +#define TIMER5_PERIOD 0xffc01658 /* Timer 5 Period Register */ +#define TIMER5_WIDTH 0xffc0165c /* Timer 5 Width Register */ +#define TIMER6_CONFIG 0xffc01660 /* Timer 6 Configuration Register */ +#define TIMER6_COUNTER 0xffc01664 /* Timer 6 Counter Register */ +#define TIMER6_PERIOD 0xffc01668 /* Timer 6 Period Register */ +#define TIMER6_WIDTH 0xffc0166c /* Timer 6 Width Register */ +#define TIMER7_CONFIG 0xffc01670 /* Timer 7 Configuration Register */ +#define TIMER7_COUNTER 0xffc01674 /* Timer 7 Counter Register */ +#define TIMER7_PERIOD 0xffc01678 /* Timer 7 Period Register */ +#define TIMER7_WIDTH 0xffc0167c /* Timer 7 Width Register */ + +/* Timer Group of 8 */ + +#define TIMER_ENABLE0 0xffc01680 /* Timer Group of 8 Enable Register */ +#define TIMER_DISABLE0 0xffc01684 /* Timer Group of 8 Disable Register */ +#define TIMER_STATUS0 0xffc01688 /* Timer Group of 8 Status Register */ + +/* DMAC1 Registers */ + +#define DMAC1_TCPER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */ +#define DMAC1_TCCNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */ + +/* DMA Channel 12 Registers */ + +#define DMA12_NEXT_DESC_PTR 0xffc01c00 /* DMA Channel 12 Next Descriptor Pointer Register */ +#define DMA12_START_ADDR 0xffc01c04 /* DMA Channel 12 Start Address Register */ +#define DMA12_CONFIG 0xffc01c08 /* DMA Channel 12 Configuration Register */ +#define DMA12_X_COUNT 0xffc01c10 /* DMA Channel 12 X Count Register */ +#define DMA12_X_MODIFY 0xffc01c14 /* DMA Channel 12 X Modify Register */ +#define DMA12_Y_COUNT 0xffc01c18 /* DMA Channel 12 Y Count Register */ +#define DMA12_Y_MODIFY 0xffc01c1c /* DMA Channel 12 Y Modify Register */ +#define DMA12_CURR_DESC_PTR 0xffc01c20 /* DMA Channel 12 Current Descriptor Pointer Register */ +#define DMA12_CURR_ADDR 0xffc01c24 /* DMA Channel 12 Current Address Register */ +#define DMA12_IRQ_STATUS 0xffc01c28 /* DMA Channel 12 Interrupt/Status Register */ +#define DMA12_PERIPHERAL_MAP 0xffc01c2c /* DMA Channel 12 Peripheral Map Register */ +#define DMA12_CURR_X_COUNT 0xffc01c30 /* DMA Channel 12 Current X Count Register */ +#define DMA12_CURR_Y_COUNT 0xffc01c38 /* DMA Channel 12 Current Y Count Register */ + +/* DMA Channel 13 Registers */ + +#define DMA13_NEXT_DESC_PTR 0xffc01c40 /* DMA Channel 13 Next Descriptor Pointer Register */ +#define DMA13_START_ADDR 0xffc01c44 /* DMA Channel 13 Start Address Register */ +#define DMA13_CONFIG 0xffc01c48 /* DMA Channel 13 Configuration Register */ +#define DMA13_X_COUNT 0xffc01c50 /* DMA Channel 13 X Count Register */ +#define DMA13_X_MODIFY 0xffc01c54 /* DMA Channel 13 X Modify Register */ +#define DMA13_Y_COUNT 0xffc01c58 /* DMA Channel 13 Y Count Register */ +#define DMA13_Y_MODIFY 0xffc01c5c /* DMA Channel 13 Y Modify Register */ +#define DMA13_CURR_DESC_PTR 0xffc01c60 /* DMA Channel 13 Current Descriptor Pointer Register */ +#define DMA13_CURR_ADDR 0xffc01c64 /* DMA Channel 13 Current Address Register */ +#define DMA13_IRQ_STATUS 0xffc01c68 /* DMA Channel 13 Interrupt/Status Register */ +#define DMA13_PERIPHERAL_MAP 0xffc01c6c /* DMA Channel 13 Peripheral Map Register */ +#define DMA13_CURR_X_COUNT 0xffc01c70 /* DMA Channel 13 Current X Count Register */ +#define DMA13_CURR_Y_COUNT 0xffc01c78 /* DMA Channel 13 Current Y Count Register */ + +/* DMA Channel 14 Registers */ + +#define DMA14_NEXT_DESC_PTR 0xffc01c80 /* DMA Channel 14 Next Descriptor Pointer Register */ +#define DMA14_START_ADDR 0xffc01c84 /* DMA Channel 14 Start Address Register */ +#define DMA14_CONFIG 0xffc01c88 /* DMA Channel 14 Configuration Register */ +#define DMA14_X_COUNT 0xffc01c90 /* DMA Channel 14 X Count Register */ +#define DMA14_X_MODIFY 0xffc01c94 /* DMA Channel 14 X Modify Register */ +#define DMA14_Y_COUNT 0xffc01c98 /* DMA Channel 14 Y Count Register */ +#define DMA14_Y_MODIFY 0xffc01c9c /* DMA Channel 14 Y Modify Register */ +#define DMA14_CURR_DESC_PTR 0xffc01ca0 /* DMA Channel 14 Current Descriptor Pointer Register */ +#define DMA14_CURR_ADDR 0xffc01ca4 /* DMA Channel 14 Current Address Register */ +#define DMA14_IRQ_STATUS 0xffc01ca8 /* DMA Channel 14 Interrupt/Status Register */ +#define DMA14_PERIPHERAL_MAP 0xffc01cac /* DMA Channel 14 Peripheral Map Register */ +#define DMA14_CURR_X_COUNT 0xffc01cb0 /* DMA Channel 14 Current X Count Register */ +#define DMA14_CURR_Y_COUNT 0xffc01cb8 /* DMA Channel 14 Current Y Count Register */ + +/* DMA Channel 15 Registers */ + +#define DMA15_NEXT_DESC_PTR 0xffc01cc0 /* DMA Channel 15 Next Descriptor Pointer Register */ +#define DMA15_START_ADDR 0xffc01cc4 /* DMA Channel 15 Start Address Register */ +#define DMA15_CONFIG 0xffc01cc8 /* DMA Channel 15 Configuration Register */ +#define DMA15_X_COUNT 0xffc01cd0 /* DMA Channel 15 X Count Register */ +#define DMA15_X_MODIFY 0xffc01cd4 /* DMA Channel 15 X Modify Register */ +#define DMA15_Y_COUNT 0xffc01cd8 /* DMA Channel 15 Y Count Register */ +#define DMA15_Y_MODIFY 0xffc01cdc /* DMA Channel 15 Y Modify Register */ +#define DMA15_CURR_DESC_PTR 0xffc01ce0 /* DMA Channel 15 Current Descriptor Pointer Register */ +#define DMA15_CURR_ADDR 0xffc01ce4 /* DMA Channel 15 Current Address Register */ +#define DMA15_IRQ_STATUS 0xffc01ce8 /* DMA Channel 15 Interrupt/Status Register */ +#define DMA15_PERIPHERAL_MAP 0xffc01cec /* DMA Channel 15 Peripheral Map Register */ +#define DMA15_CURR_X_COUNT 0xffc01cf0 /* DMA Channel 15 Current X Count Register */ +#define DMA15_CURR_Y_COUNT 0xffc01cf8 /* DMA Channel 15 Current Y Count Register */ + +/* DMA Channel 16 Registers */ + +#define DMA16_NEXT_DESC_PTR 0xffc01d00 /* DMA Channel 16 Next Descriptor Pointer Register */ +#define DMA16_START_ADDR 0xffc01d04 /* DMA Channel 16 Start Address Register */ +#define DMA16_CONFIG 0xffc01d08 /* DMA Channel 16 Configuration Register */ +#define DMA16_X_COUNT 0xffc01d10 /* DMA Channel 16 X Count Register */ +#define DMA16_X_MODIFY 0xffc01d14 /* DMA Channel 16 X Modify Register */ +#define DMA16_Y_COUNT 0xffc01d18 /* DMA Channel 16 Y Count Register */ +#define DMA16_Y_MODIFY 0xffc01d1c /* DMA Channel 16 Y Modify Register */ +#define DMA16_CURR_DESC_PTR 0xffc01d20 /* DMA Channel 16 Current Descriptor Pointer Register */ +#define DMA16_CURR_ADDR 0xffc01d24 /* DMA Channel 16 Current Address Register */ +#define DMA16_IRQ_STATUS 0xffc01d28 /* DMA Channel 16 Interrupt/Status Register */ +#define DMA16_PERIPHERAL_MAP 0xffc01d2c /* DMA Channel 16 Peripheral Map Register */ +#define DMA16_CURR_X_COUNT 0xffc01d30 /* DMA Channel 16 Current X Count Register */ +#define DMA16_CURR_Y_COUNT 0xffc01d38 /* DMA Channel 16 Current Y Count Register */ + +/* DMA Channel 17 Registers */ + +#define DMA17_NEXT_DESC_PTR 0xffc01d40 /* DMA Channel 17 Next Descriptor Pointer Register */ +#define DMA17_START_ADDR 0xffc01d44 /* DMA Channel 17 Start Address Register */ +#define DMA17_CONFIG 0xffc01d48 /* DMA Channel 17 Configuration Register */ +#define DMA17_X_COUNT 0xffc01d50 /* DMA Channel 17 X Count Register */ +#define DMA17_X_MODIFY 0xffc01d54 /* DMA Channel 17 X Modify Register */ +#define DMA17_Y_COUNT 0xffc01d58 /* DMA Channel 17 Y Count Register */ +#define DMA17_Y_MODIFY 0xffc01d5c /* DMA Channel 17 Y Modify Register */ +#define DMA17_CURR_DESC_PTR 0xffc01d60 /* DMA Channel 17 Current Descriptor Pointer Register */ +#define DMA17_CURR_ADDR 0xffc01d64 /* DMA Channel 17 Current Address Register */ +#define DMA17_IRQ_STATUS 0xffc01d68 /* DMA Channel 17 Interrupt/Status Register */ +#define DMA17_PERIPHERAL_MAP 0xffc01d6c /* DMA Channel 17 Peripheral Map Register */ +#define DMA17_CURR_X_COUNT 0xffc01d70 /* DMA Channel 17 Current X Count Register */ +#define DMA17_CURR_Y_COUNT 0xffc01d78 /* DMA Channel 17 Current Y Count Register */ + +/* DMA Channel 18 Registers */ + +#define DMA18_NEXT_DESC_PTR 0xffc01d80 /* DMA Channel 18 Next Descriptor Pointer Register */ +#define DMA18_START_ADDR 0xffc01d84 /* DMA Channel 18 Start Address Register */ +#define DMA18_CONFIG 0xffc01d88 /* DMA Channel 18 Configuration Register */ +#define DMA18_X_COUNT 0xffc01d90 /* DMA Channel 18 X Count Register */ +#define DMA18_X_MODIFY 0xffc01d94 /* DMA Channel 18 X Modify Register */ +#define DMA18_Y_COUNT 0xffc01d98 /* DMA Channel 18 Y Count Register */ +#define DMA18_Y_MODIFY 0xffc01d9c /* DMA Channel 18 Y Modify Register */ +#define DMA18_CURR_DESC_PTR 0xffc01da0 /* DMA Channel 18 Current Descriptor Pointer Register */ +#define DMA18_CURR_ADDR 0xffc01da4 /* DMA Channel 18 Current Address Register */ +#define DMA18_IRQ_STATUS 0xffc01da8 /* DMA Channel 18 Interrupt/Status Register */ +#define DMA18_PERIPHERAL_MAP 0xffc01dac /* DMA Channel 18 Peripheral Map Register */ +#define DMA18_CURR_X_COUNT 0xffc01db0 /* DMA Channel 18 Current X Count Register */ +#define DMA18_CURR_Y_COUNT 0xffc01db8 /* DMA Channel 18 Current Y Count Register */ + +/* DMA Channel 19 Registers */ + +#define DMA19_NEXT_DESC_PTR 0xffc01dc0 /* DMA Channel 19 Next Descriptor Pointer Register */ +#define DMA19_START_ADDR 0xffc01dc4 /* DMA Channel 19 Start Address Register */ +#define DMA19_CONFIG 0xffc01dc8 /* DMA Channel 19 Configuration Register */ +#define DMA19_X_COUNT 0xffc01dd0 /* DMA Channel 19 X Count Register */ +#define DMA19_X_MODIFY 0xffc01dd4 /* DMA Channel 19 X Modify Register */ +#define DMA19_Y_COUNT 0xffc01dd8 /* DMA Channel 19 Y Count Register */ +#define DMA19_Y_MODIFY 0xffc01ddc /* DMA Channel 19 Y Modify Register */ +#define DMA19_CURR_DESC_PTR 0xffc01de0 /* DMA Channel 19 Current Descriptor Pointer Register */ +#define DMA19_CURR_ADDR 0xffc01de4 /* DMA Channel 19 Current Address Register */ +#define DMA19_IRQ_STATUS 0xffc01de8 /* DMA Channel 19 Interrupt/Status Register */ +#define DMA19_PERIPHERAL_MAP 0xffc01dec /* DMA Channel 19 Peripheral Map Register */ +#define DMA19_CURR_X_COUNT 0xffc01df0 /* DMA Channel 19 Current X Count Register */ +#define DMA19_CURR_Y_COUNT 0xffc01df8 /* DMA Channel 19 Current Y Count Register */ + +/* DMA Channel 20 Registers */ + +#define DMA20_NEXT_DESC_PTR 0xffc01e00 /* DMA Channel 20 Next Descriptor Pointer Register */ +#define DMA20_START_ADDR 0xffc01e04 /* DMA Channel 20 Start Address Register */ +#define DMA20_CONFIG 0xffc01e08 /* DMA Channel 20 Configuration Register */ +#define DMA20_X_COUNT 0xffc01e10 /* DMA Channel 20 X Count Register */ +#define DMA20_X_MODIFY 0xffc01e14 /* DMA Channel 20 X Modify Register */ +#define DMA20_Y_COUNT 0xffc01e18 /* DMA Channel 20 Y Count Register */ +#define DMA20_Y_MODIFY 0xffc01e1c /* DMA Channel 20 Y Modify Register */ +#define DMA20_CURR_DESC_PTR 0xffc01e20 /* DMA Channel 20 Current Descriptor Pointer Register */ +#define DMA20_CURR_ADDR 0xffc01e24 /* DMA Channel 20 Current Address Register */ +#define DMA20_IRQ_STATUS 0xffc01e28 /* DMA Channel 20 Interrupt/Status Register */ +#define DMA20_PERIPHERAL_MAP 0xffc01e2c /* DMA Channel 20 Peripheral Map Register */ +#define DMA20_CURR_X_COUNT 0xffc01e30 /* DMA Channel 20 Current X Count Register */ +#define DMA20_CURR_Y_COUNT 0xffc01e38 /* DMA Channel 20 Current Y Count Register */ + +/* DMA Channel 21 Registers */ + +#define DMA21_NEXT_DESC_PTR 0xffc01e40 /* DMA Channel 21 Next Descriptor Pointer Register */ +#define DMA21_START_ADDR 0xffc01e44 /* DMA Channel 21 Start Address Register */ +#define DMA21_CONFIG 0xffc01e48 /* DMA Channel 21 Configuration Register */ +#define DMA21_X_COUNT 0xffc01e50 /* DMA Channel 21 X Count Register */ +#define DMA21_X_MODIFY 0xffc01e54 /* DMA Channel 21 X Modify Register */ +#define DMA21_Y_COUNT 0xffc01e58 /* DMA Channel 21 Y Count Register */ +#define DMA21_Y_MODIFY 0xffc01e5c /* DMA Channel 21 Y Modify Register */ +#define DMA21_CURR_DESC_PTR 0xffc01e60 /* DMA Channel 21 Current Descriptor Pointer Register */ +#define DMA21_CURR_ADDR 0xffc01e64 /* DMA Channel 21 Current Address Register */ +#define DMA21_IRQ_STATUS 0xffc01e68 /* DMA Channel 21 Interrupt/Status Register */ +#define DMA21_PERIPHERAL_MAP 0xffc01e6c /* DMA Channel 21 Peripheral Map Register */ +#define DMA21_CURR_X_COUNT 0xffc01e70 /* DMA Channel 21 Current X Count Register */ +#define DMA21_CURR_Y_COUNT 0xffc01e78 /* DMA Channel 21 Current Y Count Register */ + +/* DMA Channel 22 Registers */ + +#define DMA22_NEXT_DESC_PTR 0xffc01e80 /* DMA Channel 22 Next Descriptor Pointer Register */ +#define DMA22_START_ADDR 0xffc01e84 /* DMA Channel 22 Start Address Register */ +#define DMA22_CONFIG 0xffc01e88 /* DMA Channel 22 Configuration Register */ +#define DMA22_X_COUNT 0xffc01e90 /* DMA Channel 22 X Count Register */ +#define DMA22_X_MODIFY 0xffc01e94 /* DMA Channel 22 X Modify Register */ +#define DMA22_Y_COUNT 0xffc01e98 /* DMA Channel 22 Y Count Register */ +#define DMA22_Y_MODIFY 0xffc01e9c /* DMA Channel 22 Y Modify Register */ +#define DMA22_CURR_DESC_PTR 0xffc01ea0 /* DMA Channel 22 Current Descriptor Pointer Register */ +#define DMA22_CURR_ADDR 0xffc01ea4 /* DMA Channel 22 Current Address Register */ +#define DMA22_IRQ_STATUS 0xffc01ea8 /* DMA Channel 22 Interrupt/Status Register */ +#define DMA22_PERIPHERAL_MAP 0xffc01eac /* DMA Channel 22 Peripheral Map Register */ +#define DMA22_CURR_X_COUNT 0xffc01eb0 /* DMA Channel 22 Current X Count Register */ +#define DMA22_CURR_Y_COUNT 0xffc01eb8 /* DMA Channel 22 Current Y Count Register */ + +/* DMA Channel 23 Registers */ + +#define DMA23_NEXT_DESC_PTR 0xffc01ec0 /* DMA Channel 23 Next Descriptor Pointer Register */ +#define DMA23_START_ADDR 0xffc01ec4 /* DMA Channel 23 Start Address Register */ +#define DMA23_CONFIG 0xffc01ec8 /* DMA Channel 23 Configuration Register */ +#define DMA23_X_COUNT 0xffc01ed0 /* DMA Channel 23 X Count Register */ +#define DMA23_X_MODIFY 0xffc01ed4 /* DMA Channel 23 X Modify Register */ +#define DMA23_Y_COUNT 0xffc01ed8 /* DMA Channel 23 Y Count Register */ +#define DMA23_Y_MODIFY 0xffc01edc /* DMA Channel 23 Y Modify Register */ +#define DMA23_CURR_DESC_PTR 0xffc01ee0 /* DMA Channel 23 Current Descriptor Pointer Register */ +#define DMA23_CURR_ADDR 0xffc01ee4 /* DMA Channel 23 Current Address Register */ +#define DMA23_IRQ_STATUS 0xffc01ee8 /* DMA Channel 23 Interrupt/Status Register */ +#define DMA23_PERIPHERAL_MAP 0xffc01eec /* DMA Channel 23 Peripheral Map Register */ +#define DMA23_CURR_X_COUNT 0xffc01ef0 /* DMA Channel 23 Current X Count Register */ +#define DMA23_CURR_Y_COUNT 0xffc01ef8 /* DMA Channel 23 Current Y Count Register */ + +/* MDMA Stream 2 Registers */ + +#define MDMA_D2_NEXT_DESC_PTR 0xffc01f00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */ +#define MDMA_D2_START_ADDR 0xffc01f04 /* Memory DMA Stream 2 Destination Start Address Register */ +#define MDMA_D2_CONFIG 0xffc01f08 /* Memory DMA Stream 2 Destination Configuration Register */ +#define MDMA_D2_X_COUNT 0xffc01f10 /* Memory DMA Stream 2 Destination X Count Register */ +#define MDMA_D2_X_MODIFY 0xffc01f14 /* Memory DMA Stream 2 Destination X Modify Register */ +#define MDMA_D2_Y_COUNT 0xffc01f18 /* Memory DMA Stream 2 Destination Y Count Register */ +#define MDMA_D2_Y_MODIFY 0xffc01f1c /* Memory DMA Stream 2 Destination Y Modify Register */ +#define MDMA_D2_CURR_DESC_PTR 0xffc01f20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */ +#define MDMA_D2_CURR_ADDR 0xffc01f24 /* Memory DMA Stream 2 Destination Current Address Register */ +#define MDMA_D2_IRQ_STATUS 0xffc01f28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */ +#define MDMA_D2_PERIPHERAL_MAP 0xffc01f2c /* Memory DMA Stream 2 Destination Peripheral Map Register */ +#define MDMA_D2_CURR_X_COUNT 0xffc01f30 /* Memory DMA Stream 2 Destination Current X Count Register */ +#define MDMA_D2_CURR_Y_COUNT 0xffc01f38 /* Memory DMA Stream 2 Destination Current Y Count Register */ +#define MDMA_S2_NEXT_DESC_PTR 0xffc01f40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */ +#define MDMA_S2_START_ADDR 0xffc01f44 /* Memory DMA Stream 2 Source Start Address Register */ +#define MDMA_S2_CONFIG 0xffc01f48 /* Memory DMA Stream 2 Source Configuration Register */ +#define MDMA_S2_X_COUNT 0xffc01f50 /* Memory DMA Stream 2 Source X Count Register */ +#define MDMA_S2_X_MODIFY 0xffc01f54 /* Memory DMA Stream 2 Source X Modify Register */ +#define MDMA_S2_Y_COUNT 0xffc01f58 /* Memory DMA Stream 2 Source Y Count Register */ +#define MDMA_S2_Y_MODIFY 0xffc01f5c /* Memory DMA Stream 2 Source Y Modify Register */ +#define MDMA_S2_CURR_DESC_PTR 0xffc01f60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */ +#define MDMA_S2_CURR_ADDR 0xffc01f64 /* Memory DMA Stream 2 Source Current Address Register */ +#define MDMA_S2_IRQ_STATUS 0xffc01f68 /* Memory DMA Stream 2 Source Interrupt/Status Register */ +#define MDMA_S2_PERIPHERAL_MAP 0xffc01f6c /* Memory DMA Stream 2 Source Peripheral Map Register */ +#define MDMA_S2_CURR_X_COUNT 0xffc01f70 /* Memory DMA Stream 2 Source Current X Count Register */ +#define MDMA_S2_CURR_Y_COUNT 0xffc01f78 /* Memory DMA Stream 2 Source Current Y Count Register */ + +/* MDMA Stream 3 Registers */ + +#define MDMA_D3_NEXT_DESC_PTR 0xffc01f80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */ +#define MDMA_D3_START_ADDR 0xffc01f84 /* Memory DMA Stream 3 Destination Start Address Register */ +#define MDMA_D3_CONFIG 0xffc01f88 /* Memory DMA Stream 3 Destination Configuration Register */ +#define MDMA_D3_X_COUNT 0xffc01f90 /* Memory DMA Stream 3 Destination X Count Register */ +#define MDMA_D3_X_MODIFY 0xffc01f94 /* Memory DMA Stream 3 Destination X Modify Register */ +#define MDMA_D3_Y_COUNT 0xffc01f98 /* Memory DMA Stream 3 Destination Y Count Register */ +#define MDMA_D3_Y_MODIFY 0xffc01f9c /* Memory DMA Stream 3 Destination Y Modify Register */ +#define MDMA_D3_CURR_DESC_PTR 0xffc01fa0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */ +#define MDMA_D3_CURR_ADDR 0xffc01fa4 /* Memory DMA Stream 3 Destination Current Address Register */ +#define MDMA_D3_IRQ_STATUS 0xffc01fa8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */ +#define MDMA_D3_PERIPHERAL_MAP 0xffc01fac /* Memory DMA Stream 3 Destination Peripheral Map Register */ +#define MDMA_D3_CURR_X_COUNT 0xffc01fb0 /* Memory DMA Stream 3 Destination Current X Count Register */ +#define MDMA_D3_CURR_Y_COUNT 0xffc01fb8 /* Memory DMA Stream 3 Destination Current Y Count Register */ +#define MDMA_S3_NEXT_DESC_PTR 0xffc01fc0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */ +#define MDMA_S3_START_ADDR 0xffc01fc4 /* Memory DMA Stream 3 Source Start Address Register */ +#define MDMA_S3_CONFIG 0xffc01fc8 /* Memory DMA Stream 3 Source Configuration Register */ +#define MDMA_S3_X_COUNT 0xffc01fd0 /* Memory DMA Stream 3 Source X Count Register */ +#define MDMA_S3_X_MODIFY 0xffc01fd4 /* Memory DMA Stream 3 Source X Modify Register */ +#define MDMA_S3_Y_COUNT 0xffc01fd8 /* Memory DMA Stream 3 Source Y Count Register */ +#define MDMA_S3_Y_MODIFY 0xffc01fdc /* Memory DMA Stream 3 Source Y Modify Register */ +#define MDMA_S3_CURR_DESC_PTR 0xffc01fe0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */ +#define MDMA_S3_CURR_ADDR 0xffc01fe4 /* Memory DMA Stream 3 Source Current Address Register */ +#define MDMA_S3_IRQ_STATUS 0xffc01fe8 /* Memory DMA Stream 3 Source Interrupt/Status Register */ +#define MDMA_S3_PERIPHERAL_MAP 0xffc01fec /* Memory DMA Stream 3 Source Peripheral Map Register */ +#define MDMA_S3_CURR_X_COUNT 0xffc01ff0 /* Memory DMA Stream 3 Source Current X Count Register */ +#define MDMA_S3_CURR_Y_COUNT 0xffc01ff8 /* Memory DMA Stream 3 Source Current Y Count Register */ + +/* UART1 Registers */ + +#define UART1_DLL 0xffc02000 /* Divisor Latch Low Byte */ +#define UART1_DLH 0xffc02004 /* Divisor Latch High Byte */ +#define UART1_GCTL 0xffc02008 /* Global Control Register */ +#define UART1_LCR 0xffc0200c /* Line Control Register */ +#define UART1_MCR 0xffc02010 /* Modem Control Register */ +#define UART1_LSR 0xffc02014 /* Line Status Register */ +#define UART1_MSR 0xffc02018 /* Modem Status Register */ +#define UART1_SCR 0xffc0201c /* Scratch Register */ +#define UART1_IER_SET 0xffc02020 /* Interrupt Enable Register Set */ +#define UART1_IER_CLEAR 0xffc02024 /* Interrupt Enable Register Clear */ +#define UART1_THR 0xffc02028 /* Transmit Hold Register */ +#define UART1_RBR 0xffc0202c /* Receive Buffer Register */ + +/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */ + +/* SPI1 Registers */ + +#define SPI1_REGBASE 0xffc02300 +#define SPI1_CTL 0xffc02300 /* SPI1 Control Register */ +#define SPI1_FLG 0xffc02304 /* SPI1 Flag Register */ +#define SPI1_STAT 0xffc02308 /* SPI1 Status Register */ +#define SPI1_TDBR 0xffc0230c /* SPI1 Transmit Data Buffer Register */ +#define SPI1_RDBR 0xffc02310 /* SPI1 Receive Data Buffer Register */ +#define SPI1_BAUD 0xffc02314 /* SPI1 Baud Rate Register */ +#define SPI1_SHADOW 0xffc02318 /* SPI1 Receive Data Buffer Shadow Register */ + +/* SPORT2 Registers */ + +#define SPORT2_TCR1 0xffc02500 /* SPORT2 Transmit Configuration 1 Register */ +#define SPORT2_TCR2 0xffc02504 /* SPORT2 Transmit Configuration 2 Register */ +#define SPORT2_TCLKDIV 0xffc02508 /* SPORT2 Transmit Serial Clock Divider Register */ +#define SPORT2_TFSDIV 0xffc0250c /* SPORT2 Transmit Frame Sync Divider Register */ +#define SPORT2_TX 0xffc02510 /* SPORT2 Transmit Data Register */ +#define SPORT2_RX 0xffc02518 /* SPORT2 Receive Data Register */ +#define SPORT2_RCR1 0xffc02520 /* SPORT2 Receive Configuration 1 Register */ +#define SPORT2_RCR2 0xffc02524 /* SPORT2 Receive Configuration 2 Register */ +#define SPORT2_RCLKDIV 0xffc02528 /* SPORT2 Receive Serial Clock Divider Register */ +#define SPORT2_RFSDIV 0xffc0252c /* SPORT2 Receive Frame Sync Divider Register */ +#define SPORT2_STAT 0xffc02530 /* SPORT2 Status Register */ +#define SPORT2_CHNL 0xffc02534 /* SPORT2 Current Channel Register */ +#define SPORT2_MCMC1 0xffc02538 /* SPORT2 Multi channel Configuration Register 1 */ +#define SPORT2_MCMC2 0xffc0253c /* SPORT2 Multi channel Configuration Register 2 */ +#define SPORT2_MTCS0 0xffc02540 /* SPORT2 Multi channel Transmit Select Register 0 */ +#define SPORT2_MTCS1 0xffc02544 /* SPORT2 Multi channel Transmit Select Register 1 */ +#define SPORT2_MTCS2 0xffc02548 /* SPORT2 Multi channel Transmit Select Register 2 */ +#define SPORT2_MTCS3 0xffc0254c /* SPORT2 Multi channel Transmit Select Register 3 */ +#define SPORT2_MRCS0 0xffc02550 /* SPORT2 Multi channel Receive Select Register 0 */ +#define SPORT2_MRCS1 0xffc02554 /* SPORT2 Multi channel Receive Select Register 1 */ +#define SPORT2_MRCS2 0xffc02558 /* SPORT2 Multi channel Receive Select Register 2 */ +#define SPORT2_MRCS3 0xffc0255c /* SPORT2 Multi channel Receive Select Register 3 */ + +/* SPORT3 Registers */ + +#define SPORT3_TCR1 0xffc02600 /* SPORT3 Transmit Configuration 1 Register */ +#define SPORT3_TCR2 0xffc02604 /* SPORT3 Transmit Configuration 2 Register */ +#define SPORT3_TCLKDIV 0xffc02608 /* SPORT3 Transmit Serial Clock Divider Register */ +#define SPORT3_TFSDIV 0xffc0260c /* SPORT3 Transmit Frame Sync Divider Register */ +#define SPORT3_TX 0xffc02610 /* SPORT3 Transmit Data Register */ +#define SPORT3_RX 0xffc02618 /* SPORT3 Receive Data Register */ +#define SPORT3_RCR1 0xffc02620 /* SPORT3 Receive Configuration 1 Register */ +#define SPORT3_RCR2 0xffc02624 /* SPORT3 Receive Configuration 2 Register */ +#define SPORT3_RCLKDIV 0xffc02628 /* SPORT3 Receive Serial Clock Divider Register */ +#define SPORT3_RFSDIV 0xffc0262c /* SPORT3 Receive Frame Sync Divider Register */ +#define SPORT3_STAT 0xffc02630 /* SPORT3 Status Register */ +#define SPORT3_CHNL 0xffc02634 /* SPORT3 Current Channel Register */ +#define SPORT3_MCMC1 0xffc02638 /* SPORT3 Multi channel Configuration Register 1 */ +#define SPORT3_MCMC2 0xffc0263c /* SPORT3 Multi channel Configuration Register 2 */ +#define SPORT3_MTCS0 0xffc02640 /* SPORT3 Multi channel Transmit Select Register 0 */ +#define SPORT3_MTCS1 0xffc02644 /* SPORT3 Multi channel Transmit Select Register 1 */ +#define SPORT3_MTCS2 0xffc02648 /* SPORT3 Multi channel Transmit Select Register 2 */ +#define SPORT3_MTCS3 0xffc0264c /* SPORT3 Multi channel Transmit Select Register 3 */ +#define SPORT3_MRCS0 0xffc02650 /* SPORT3 Multi channel Receive Select Register 0 */ +#define SPORT3_MRCS1 0xffc02654 /* SPORT3 Multi channel Receive Select Register 1 */ +#define SPORT3_MRCS2 0xffc02658 /* SPORT3 Multi channel Receive Select Register 2 */ +#define SPORT3_MRCS3 0xffc0265c /* SPORT3 Multi channel Receive Select Register 3 */ + +/* EPPI2 Registers */ + +#define EPPI2_STATUS 0xffc02900 /* EPPI2 Status Register */ +#define EPPI2_HCOUNT 0xffc02904 /* EPPI2 Horizontal Transfer Count Register */ +#define EPPI2_HDELAY 0xffc02908 /* EPPI2 Horizontal Delay Count Register */ +#define EPPI2_VCOUNT 0xffc0290c /* EPPI2 Vertical Transfer Count Register */ +#define EPPI2_VDELAY 0xffc02910 /* EPPI2 Vertical Delay Count Register */ +#define EPPI2_FRAME 0xffc02914 /* EPPI2 Lines per Frame Register */ +#define EPPI2_LINE 0xffc02918 /* EPPI2 Samples per Line Register */ +#define EPPI2_CLKDIV 0xffc0291c /* EPPI2 Clock Divide Register */ +#define EPPI2_CONTROL 0xffc02920 /* EPPI2 Control Register */ +#define EPPI2_FS1W_HBL 0xffc02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */ +#define EPPI2_FS1P_AVPL 0xffc02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */ +#define EPPI2_FS2W_LVB 0xffc0292c /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */ +#define EPPI2_FS2P_LAVF 0xffc02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */ +#define EPPI2_CLIP 0xffc02934 /* EPPI2 Clipping Register */ + +/* CAN Controller 0 Config 1 Registers */ + +#define CAN0_MC1 0xffc02a00 /* CAN Controller 0 Mailbox Configuration Register 1 */ +#define CAN0_MD1 0xffc02a04 /* CAN Controller 0 Mailbox Direction Register 1 */ +#define CAN0_TRS1 0xffc02a08 /* CAN Controller 0 Transmit Request Set Register 1 */ +#define CAN0_TRR1 0xffc02a0c /* CAN Controller 0 Transmit Request Reset Register 1 */ +#define CAN0_TA1 0xffc02a10 /* CAN Controller 0 Transmit Acknowledge Register 1 */ +#define CAN0_AA1 0xffc02a14 /* CAN Controller 0 Abort Acknowledge Register 1 */ +#define CAN0_RMP1 0xffc02a18 /* CAN Controller 0 Receive Message Pending Register 1 */ +#define CAN0_RML1 0xffc02a1c /* CAN Controller 0 Receive Message Lost Register 1 */ +#define CAN0_MBTIF1 0xffc02a20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */ +#define CAN0_MBRIF1 0xffc02a24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */ +#define CAN0_MBIM1 0xffc02a28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */ +#define CAN0_RFH1 0xffc02a2c /* CAN Controller 0 Remote Frame Handling Enable Register 1 */ +#define CAN0_OPSS1 0xffc02a30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */ + +/* CAN Controller 0 Config 2 Registers */ + +#define CAN0_MC2 0xffc02a40 /* CAN Controller 0 Mailbox Configuration Register 2 */ +#define CAN0_MD2 0xffc02a44 /* CAN Controller 0 Mailbox Direction Register 2 */ +#define CAN0_TRS2 0xffc02a48 /* CAN Controller 0 Transmit Request Set Register 2 */ +#define CAN0_TRR2 0xffc02a4c /* CAN Controller 0 Transmit Request Reset Register 2 */ +#define CAN0_TA2 0xffc02a50 /* CAN Controller 0 Transmit Acknowledge Register 2 */ +#define CAN0_AA2 0xffc02a54 /* CAN Controller 0 Abort Acknowledge Register 2 */ +#define CAN0_RMP2 0xffc02a58 /* CAN Controller 0 Receive Message Pending Register 2 */ +#define CAN0_RML2 0xffc02a5c /* CAN Controller 0 Receive Message Lost Register 2 */ +#define CAN0_MBTIF2 0xffc02a60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */ +#define CAN0_MBRIF2 0xffc02a64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */ +#define CAN0_MBIM2 0xffc02a68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */ +#define CAN0_RFH2 0xffc02a6c /* CAN Controller 0 Remote Frame Handling Enable Register 2 */ +#define CAN0_OPSS2 0xffc02a70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */ + +/* CAN Controller 0 Clock/Interrupt/Counter Registers */ + +#define CAN0_CLOCK 0xffc02a80 /* CAN Controller 0 Clock Register */ +#define CAN0_TIMING 0xffc02a84 /* CAN Controller 0 Timing Register */ +#define CAN0_DEBUG 0xffc02a88 /* CAN Controller 0 Debug Register */ +#define CAN0_STATUS 0xffc02a8c /* CAN Controller 0 Global Status Register */ +#define CAN0_CEC 0xffc02a90 /* CAN Controller 0 Error Counter Register */ +#define CAN0_GIS 0xffc02a94 /* CAN Controller 0 Global Interrupt Status Register */ +#define CAN0_GIM 0xffc02a98 /* CAN Controller 0 Global Interrupt Mask Register */ +#define CAN0_GIF 0xffc02a9c /* CAN Controller 0 Global Interrupt Flag Register */ +#define CAN0_CONTROL 0xffc02aa0 /* CAN Controller 0 Master Control Register */ +#define CAN0_INTR 0xffc02aa4 /* CAN Controller 0 Interrupt Pending Register */ +#define CAN0_MBTD 0xffc02aac /* CAN Controller 0 Mailbox Temporary Disable Register */ +#define CAN0_EWR 0xffc02ab0 /* CAN Controller 0 Programmable Warning Level Register */ +#define CAN0_ESR 0xffc02ab4 /* CAN Controller 0 Error Status Register */ +#define CAN0_UCCNT 0xffc02ac4 /* CAN Controller 0 Universal Counter Register */ +#define CAN0_UCRC 0xffc02ac8 /* CAN Controller 0 Universal Counter Force Reload Register */ +#define CAN0_UCCNF 0xffc02acc /* CAN Controller 0 Universal Counter Configuration Register */ + +/* CAN Controller 0 Acceptance Registers */ + +#define CAN0_AM00L 0xffc02b00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */ +#define CAN0_AM00H 0xffc02b04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */ +#define CAN0_AM01L 0xffc02b08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */ +#define CAN0_AM01H 0xffc02b0c /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */ +#define CAN0_AM02L 0xffc02b10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */ +#define CAN0_AM02H 0xffc02b14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */ +#define CAN0_AM03L 0xffc02b18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */ +#define CAN0_AM03H 0xffc02b1c /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */ +#define CAN0_AM04L 0xffc02b20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */ +#define CAN0_AM04H 0xffc02b24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */ +#define CAN0_AM05L 0xffc02b28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */ +#define CAN0_AM05H 0xffc02b2c /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */ +#define CAN0_AM06L 0xffc02b30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */ +#define CAN0_AM06H 0xffc02b34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */ +#define CAN0_AM07L 0xffc02b38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */ +#define CAN0_AM07H 0xffc02b3c /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */ +#define CAN0_AM08L 0xffc02b40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */ +#define CAN0_AM08H 0xffc02b44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */ +#define CAN0_AM09L 0xffc02b48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */ +#define CAN0_AM09H 0xffc02b4c /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */ +#define CAN0_AM10L 0xffc02b50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */ +#define CAN0_AM10H 0xffc02b54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */ +#define CAN0_AM11L 0xffc02b58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */ +#define CAN0_AM11H 0xffc02b5c /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */ +#define CAN0_AM12L 0xffc02b60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */ +#define CAN0_AM12H 0xffc02b64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */ +#define CAN0_AM13L 0xffc02b68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */ +#define CAN0_AM13H 0xffc02b6c /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */ +#define CAN0_AM14L 0xffc02b70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */ +#define CAN0_AM14H 0xffc02b74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */ +#define CAN0_AM15L 0xffc02b78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */ +#define CAN0_AM15H 0xffc02b7c /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */ + +/* CAN Controller 0 Acceptance Registers */ + +#define CAN0_AM16L 0xffc02b80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */ +#define CAN0_AM16H 0xffc02b84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */ +#define CAN0_AM17L 0xffc02b88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */ +#define CAN0_AM17H 0xffc02b8c /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */ +#define CAN0_AM18L 0xffc02b90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */ +#define CAN0_AM18H 0xffc02b94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */ +#define CAN0_AM19L 0xffc02b98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */ +#define CAN0_AM19H 0xffc02b9c /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */ +#define CAN0_AM20L 0xffc02ba0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */ +#define CAN0_AM20H 0xffc02ba4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */ +#define CAN0_AM21L 0xffc02ba8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */ +#define CAN0_AM21H 0xffc02bac /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */ +#define CAN0_AM22L 0xffc02bb0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */ +#define CAN0_AM22H 0xffc02bb4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */ +#define CAN0_AM23L 0xffc02bb8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */ +#define CAN0_AM23H 0xffc02bbc /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */ +#define CAN0_AM24L 0xffc02bc0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */ +#define CAN0_AM24H 0xffc02bc4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */ +#define CAN0_AM25L 0xffc02bc8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */ +#define CAN0_AM25H 0xffc02bcc /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */ +#define CAN0_AM26L 0xffc02bd0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */ +#define CAN0_AM26H 0xffc02bd4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */ +#define CAN0_AM27L 0xffc02bd8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */ +#define CAN0_AM27H 0xffc02bdc /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */ +#define CAN0_AM28L 0xffc02be0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */ +#define CAN0_AM28H 0xffc02be4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */ +#define CAN0_AM29L 0xffc02be8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */ +#define CAN0_AM29H 0xffc02bec /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */ +#define CAN0_AM30L 0xffc02bf0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */ +#define CAN0_AM30H 0xffc02bf4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */ +#define CAN0_AM31L 0xffc02bf8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */ +#define CAN0_AM31H 0xffc02bfc /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */ + +/* CAN Controller 0 Mailbox Data Registers */ + +#define CAN0_MB00_DATA0 0xffc02c00 /* CAN Controller 0 Mailbox 0 Data 0 Register */ +#define CAN0_MB00_DATA1 0xffc02c04 /* CAN Controller 0 Mailbox 0 Data 1 Register */ +#define CAN0_MB00_DATA2 0xffc02c08 /* CAN Controller 0 Mailbox 0 Data 2 Register */ +#define CAN0_MB00_DATA3 0xffc02c0c /* CAN Controller 0 Mailbox 0 Data 3 Register */ +#define CAN0_MB00_LENGTH 0xffc02c10 /* CAN Controller 0 Mailbox 0 Length Register */ +#define CAN0_MB00_TIMESTAMP 0xffc02c14 /* CAN Controller 0 Mailbox 0 Timestamp Register */ +#define CAN0_MB00_ID0 0xffc02c18 /* CAN Controller 0 Mailbox 0 ID0 Register */ +#define CAN0_MB00_ID1 0xffc02c1c /* CAN Controller 0 Mailbox 0 ID1 Register */ +#define CAN0_MB01_DATA0 0xffc02c20 /* CAN Controller 0 Mailbox 1 Data 0 Register */ +#define CAN0_MB01_DATA1 0xffc02c24 /* CAN Controller 0 Mailbox 1 Data 1 Register */ +#define CAN0_MB01_DATA2 0xffc02c28 /* CAN Controller 0 Mailbox 1 Data 2 Register */ +#define CAN0_MB01_DATA3 0xffc02c2c /* CAN Controller 0 Mailbox 1 Data 3 Register */ +#define CAN0_MB01_LENGTH 0xffc02c30 /* CAN Controller 0 Mailbox 1 Length Register */ +#define CAN0_MB01_TIMESTAMP 0xffc02c34 /* CAN Controller 0 Mailbox 1 Timestamp Register */ +#define CAN0_MB01_ID0 0xffc02c38 /* CAN Controller 0 Mailbox 1 ID0 Register */ +#define CAN0_MB01_ID1 0xffc02c3c /* CAN Controller 0 Mailbox 1 ID1 Register */ +#define CAN0_MB02_DATA0 0xffc02c40 /* CAN Controller 0 Mailbox 2 Data 0 Register */ +#define CAN0_MB02_DATA1 0xffc02c44 /* CAN Controller 0 Mailbox 2 Data 1 Register */ +#define CAN0_MB02_DATA2 0xffc02c48 /* CAN Controller 0 Mailbox 2 Data 2 Register */ +#define CAN0_MB02_DATA3 0xffc02c4c /* CAN Controller 0 Mailbox 2 Data 3 Register */ +#define CAN0_MB02_LENGTH 0xffc02c50 /* CAN Controller 0 Mailbox 2 Length Register */ +#define CAN0_MB02_TIMESTAMP 0xffc02c54 /* CAN Controller 0 Mailbox 2 Timestamp Register */ +#define CAN0_MB02_ID0 0xffc02c58 /* CAN Controller 0 Mailbox 2 ID0 Register */ +#define CAN0_MB02_ID1 0xffc02c5c /* CAN Controller 0 Mailbox 2 ID1 Register */ +#define CAN0_MB03_DATA0 0xffc02c60 /* CAN Controller 0 Mailbox 3 Data 0 Register */ +#define CAN0_MB03_DATA1 0xffc02c64 /* CAN Controller 0 Mailbox 3 Data 1 Register */ +#define CAN0_MB03_DATA2 0xffc02c68 /* CAN Controller 0 Mailbox 3 Data 2 Register */ +#define CAN0_MB03_DATA3 0xffc02c6c /* CAN Controller 0 Mailbox 3 Data 3 Register */ +#define CAN0_MB03_LENGTH 0xffc02c70 /* CAN Controller 0 Mailbox 3 Length Register */ +#define CAN0_MB03_TIMESTAMP 0xffc02c74 /* CAN Controller 0 Mailbox 3 Timestamp Register */ +#define CAN0_MB03_ID0 0xffc02c78 /* CAN Controller 0 Mailbox 3 ID0 Register */ +#define CAN0_MB03_ID1 0xffc02c7c /* CAN Controller 0 Mailbox 3 ID1 Register */ +#define CAN0_MB04_DATA0 0xffc02c80 /* CAN Controller 0 Mailbox 4 Data 0 Register */ +#define CAN0_MB04_DATA1 0xffc02c84 /* CAN Controller 0 Mailbox 4 Data 1 Register */ +#define CAN0_MB04_DATA2 0xffc02c88 /* CAN Controller 0 Mailbox 4 Data 2 Register */ +#define CAN0_MB04_DATA3 0xffc02c8c /* CAN Controller 0 Mailbox 4 Data 3 Register */ +#define CAN0_MB04_LENGTH 0xffc02c90 /* CAN Controller 0 Mailbox 4 Length Register */ +#define CAN0_MB04_TIMESTAMP 0xffc02c94 /* CAN Controller 0 Mailbox 4 Timestamp Register */ +#define CAN0_MB04_ID0 0xffc02c98 /* CAN Controller 0 Mailbox 4 ID0 Register */ +#define CAN0_MB04_ID1 0xffc02c9c /* CAN Controller 0 Mailbox 4 ID1 Register */ +#define CAN0_MB05_DATA0 0xffc02ca0 /* CAN Controller 0 Mailbox 5 Data 0 Register */ +#define CAN0_MB05_DATA1 0xffc02ca4 /* CAN Controller 0 Mailbox 5 Data 1 Register */ +#define CAN0_MB05_DATA2 0xffc02ca8 /* CAN Controller 0 Mailbox 5 Data 2 Register */ +#define CAN0_MB05_DATA3 0xffc02cac /* CAN Controller 0 Mailbox 5 Data 3 Register */ +#define CAN0_MB05_LENGTH 0xffc02cb0 /* CAN Controller 0 Mailbox 5 Length Register */ +#define CAN0_MB05_TIMESTAMP 0xffc02cb4 /* CAN Controller 0 Mailbox 5 Timestamp Register */ +#define CAN0_MB05_ID0 0xffc02cb8 /* CAN Controller 0 Mailbox 5 ID0 Register */ +#define CAN0_MB05_ID1 0xffc02cbc /* CAN Controller 0 Mailbox 5 ID1 Register */ +#define CAN0_MB06_DATA0 0xffc02cc0 /* CAN Controller 0 Mailbox 6 Data 0 Register */ +#define CAN0_MB06_DATA1 0xffc02cc4 /* CAN Controller 0 Mailbox 6 Data 1 Register */ +#define CAN0_MB06_DATA2 0xffc02cc8 /* CAN Controller 0 Mailbox 6 Data 2 Register */ +#define CAN0_MB06_DATA3 0xffc02ccc /* CAN Controller 0 Mailbox 6 Data 3 Register */ +#define CAN0_MB06_LENGTH 0xffc02cd0 /* CAN Controller 0 Mailbox 6 Length Register */ +#define CAN0_MB06_TIMESTAMP 0xffc02cd4 /* CAN Controller 0 Mailbox 6 Timestamp Register */ +#define CAN0_MB06_ID0 0xffc02cd8 /* CAN Controller 0 Mailbox 6 ID0 Register */ +#define CAN0_MB06_ID1 0xffc02cdc /* CAN Controller 0 Mailbox 6 ID1 Register */ +#define CAN0_MB07_DATA0 0xffc02ce0 /* CAN Controller 0 Mailbox 7 Data 0 Register */ +#define CAN0_MB07_DATA1 0xffc02ce4 /* CAN Controller 0 Mailbox 7 Data 1 Register */ +#define CAN0_MB07_DATA2 0xffc02ce8 /* CAN Controller 0 Mailbox 7 Data 2 Register */ +#define CAN0_MB07_DATA3 0xffc02cec /* CAN Controller 0 Mailbox 7 Data 3 Register */ +#define CAN0_MB07_LENGTH 0xffc02cf0 /* CAN Controller 0 Mailbox 7 Length Register */ +#define CAN0_MB07_TIMESTAMP 0xffc02cf4 /* CAN Controller 0 Mailbox 7 Timestamp Register */ +#define CAN0_MB07_ID0 0xffc02cf8 /* CAN Controller 0 Mailbox 7 ID0 Register */ +#define CAN0_MB07_ID1 0xffc02cfc /* CAN Controller 0 Mailbox 7 ID1 Register */ +#define CAN0_MB08_DATA0 0xffc02d00 /* CAN Controller 0 Mailbox 8 Data 0 Register */ +#define CAN0_MB08_DATA1 0xffc02d04 /* CAN Controller 0 Mailbox 8 Data 1 Register */ +#define CAN0_MB08_DATA2 0xffc02d08 /* CAN Controller 0 Mailbox 8 Data 2 Register */ +#define CAN0_MB08_DATA3 0xffc02d0c /* CAN Controller 0 Mailbox 8 Data 3 Register */ +#define CAN0_MB08_LENGTH 0xffc02d10 /* CAN Controller 0 Mailbox 8 Length Register */ +#define CAN0_MB08_TIMESTAMP 0xffc02d14 /* CAN Controller 0 Mailbox 8 Timestamp Register */ +#define CAN0_MB08_ID0 0xffc02d18 /* CAN Controller 0 Mailbox 8 ID0 Register */ +#define CAN0_MB08_ID1 0xffc02d1c /* CAN Controller 0 Mailbox 8 ID1 Register */ +#define CAN0_MB09_DATA0 0xffc02d20 /* CAN Controller 0 Mailbox 9 Data 0 Register */ +#define CAN0_MB09_DATA1 0xffc02d24 /* CAN Controller 0 Mailbox 9 Data 1 Register */ +#define CAN0_MB09_DATA2 0xffc02d28 /* CAN Controller 0 Mailbox 9 Data 2 Register */ +#define CAN0_MB09_DATA3 0xffc02d2c /* CAN Controller 0 Mailbox 9 Data 3 Register */ +#define CAN0_MB09_LENGTH 0xffc02d30 /* CAN Controller 0 Mailbox 9 Length Register */ +#define CAN0_MB09_TIMESTAMP 0xffc02d34 /* CAN Controller 0 Mailbox 9 Timestamp Register */ +#define CAN0_MB09_ID0 0xffc02d38 /* CAN Controller 0 Mailbox 9 ID0 Register */ +#define CAN0_MB09_ID1 0xffc02d3c /* CAN Controller 0 Mailbox 9 ID1 Register */ +#define CAN0_MB10_DATA0 0xffc02d40 /* CAN Controller 0 Mailbox 10 Data 0 Register */ +#define CAN0_MB10_DATA1 0xffc02d44 /* CAN Controller 0 Mailbox 10 Data 1 Register */ +#define CAN0_MB10_DATA2 0xffc02d48 /* CAN Controller 0 Mailbox 10 Data 2 Register */ +#define CAN0_MB10_DATA3 0xffc02d4c /* CAN Controller 0 Mailbox 10 Data 3 Register */ +#define CAN0_MB10_LENGTH 0xffc02d50 /* CAN Controller 0 Mailbox 10 Length Register */ +#define CAN0_MB10_TIMESTAMP 0xffc02d54 /* CAN Controller 0 Mailbox 10 Timestamp Register */ +#define CAN0_MB10_ID0 0xffc02d58 /* CAN Controller 0 Mailbox 10 ID0 Register */ +#define CAN0_MB10_ID1 0xffc02d5c /* CAN Controller 0 Mailbox 10 ID1 Register */ +#define CAN0_MB11_DATA0 0xffc02d60 /* CAN Controller 0 Mailbox 11 Data 0 Register */ +#define CAN0_MB11_DATA1 0xffc02d64 /* CAN Controller 0 Mailbox 11 Data 1 Register */ +#define CAN0_MB11_DATA2 0xffc02d68 /* CAN Controller 0 Mailbox 11 Data 2 Register */ +#define CAN0_MB11_DATA3 0xffc02d6c /* CAN Controller 0 Mailbox 11 Data 3 Register */ +#define CAN0_MB11_LENGTH 0xffc02d70 /* CAN Controller 0 Mailbox 11 Length Register */ +#define CAN0_MB11_TIMESTAMP 0xffc02d74 /* CAN Controller 0 Mailbox 11 Timestamp Register */ +#define CAN0_MB11_ID0 0xffc02d78 /* CAN Controller 0 Mailbox 11 ID0 Register */ +#define CAN0_MB11_ID1 0xffc02d7c /* CAN Controller 0 Mailbox 11 ID1 Register */ +#define CAN0_MB12_DATA0 0xffc02d80 /* CAN Controller 0 Mailbox 12 Data 0 Register */ +#define CAN0_MB12_DATA1 0xffc02d84 /* CAN Controller 0 Mailbox 12 Data 1 Register */ +#define CAN0_MB12_DATA2 0xffc02d88 /* CAN Controller 0 Mailbox 12 Data 2 Register */ +#define CAN0_MB12_DATA3 0xffc02d8c /* CAN Controller 0 Mailbox 12 Data 3 Register */ +#define CAN0_MB12_LENGTH 0xffc02d90 /* CAN Controller 0 Mailbox 12 Length Register */ +#define CAN0_MB12_TIMESTAMP 0xffc02d94 /* CAN Controller 0 Mailbox 12 Timestamp Register */ +#define CAN0_MB12_ID0 0xffc02d98 /* CAN Controller 0 Mailbox 12 ID0 Register */ +#define CAN0_MB12_ID1 0xffc02d9c /* CAN Controller 0 Mailbox 12 ID1 Register */ +#define CAN0_MB13_DATA0 0xffc02da0 /* CAN Controller 0 Mailbox 13 Data 0 Register */ +#define CAN0_MB13_DATA1 0xffc02da4 /* CAN Controller 0 Mailbox 13 Data 1 Register */ +#define CAN0_MB13_DATA2 0xffc02da8 /* CAN Controller 0 Mailbox 13 Data 2 Register */ +#define CAN0_MB13_DATA3 0xffc02dac /* CAN Controller 0 Mailbox 13 Data 3 Register */ +#define CAN0_MB13_LENGTH 0xffc02db0 /* CAN Controller 0 Mailbox 13 Length Register */ +#define CAN0_MB13_TIMESTAMP 0xffc02db4 /* CAN Controller 0 Mailbox 13 Timestamp Register */ +#define CAN0_MB13_ID0 0xffc02db8 /* CAN Controller 0 Mailbox 13 ID0 Register */ +#define CAN0_MB13_ID1 0xffc02dbc /* CAN Controller 0 Mailbox 13 ID1 Register */ +#define CAN0_MB14_DATA0 0xffc02dc0 /* CAN Controller 0 Mailbox 14 Data 0 Register */ +#define CAN0_MB14_DATA1 0xffc02dc4 /* CAN Controller 0 Mailbox 14 Data 1 Register */ +#define CAN0_MB14_DATA2 0xffc02dc8 /* CAN Controller 0 Mailbox 14 Data 2 Register */ +#define CAN0_MB14_DATA3 0xffc02dcc /* CAN Controller 0 Mailbox 14 Data 3 Register */ +#define CAN0_MB14_LENGTH 0xffc02dd0 /* CAN Controller 0 Mailbox 14 Length Register */ +#define CAN0_MB14_TIMESTAMP 0xffc02dd4 /* CAN Controller 0 Mailbox 14 Timestamp Register */ +#define CAN0_MB14_ID0 0xffc02dd8 /* CAN Controller 0 Mailbox 14 ID0 Register */ +#define CAN0_MB14_ID1 0xffc02ddc /* CAN Controller 0 Mailbox 14 ID1 Register */ +#define CAN0_MB15_DATA0 0xffc02de0 /* CAN Controller 0 Mailbox 15 Data 0 Register */ +#define CAN0_MB15_DATA1 0xffc02de4 /* CAN Controller 0 Mailbox 15 Data 1 Register */ +#define CAN0_MB15_DATA2 0xffc02de8 /* CAN Controller 0 Mailbox 15 Data 2 Register */ +#define CAN0_MB15_DATA3 0xffc02dec /* CAN Controller 0 Mailbox 15 Data 3 Register */ +#define CAN0_MB15_LENGTH 0xffc02df0 /* CAN Controller 0 Mailbox 15 Length Register */ +#define CAN0_MB15_TIMESTAMP 0xffc02df4 /* CAN Controller 0 Mailbox 15 Timestamp Register */ +#define CAN0_MB15_ID0 0xffc02df8 /* CAN Controller 0 Mailbox 15 ID0 Register */ +#define CAN0_MB15_ID1 0xffc02dfc /* CAN Controller 0 Mailbox 15 ID1 Register */ + +/* CAN Controller 0 Mailbox Data Registers */ + +#define CAN0_MB16_DATA0 0xffc02e00 /* CAN Controller 0 Mailbox 16 Data 0 Register */ +#define CAN0_MB16_DATA1 0xffc02e04 /* CAN Controller 0 Mailbox 16 Data 1 Register */ +#define CAN0_MB16_DATA2 0xffc02e08 /* CAN Controller 0 Mailbox 16 Data 2 Register */ +#define CAN0_MB16_DATA3 0xffc02e0c /* CAN Controller 0 Mailbox 16 Data 3 Register */ +#define CAN0_MB16_LENGTH 0xffc02e10 /* CAN Controller 0 Mailbox 16 Length Register */ +#define CAN0_MB16_TIMESTAMP 0xffc02e14 /* CAN Controller 0 Mailbox 16 Timestamp Register */ +#define CAN0_MB16_ID0 0xffc02e18 /* CAN Controller 0 Mailbox 16 ID0 Register */ +#define CAN0_MB16_ID1 0xffc02e1c /* CAN Controller 0 Mailbox 16 ID1 Register */ +#define CAN0_MB17_DATA0 0xffc02e20 /* CAN Controller 0 Mailbox 17 Data 0 Register */ +#define CAN0_MB17_DATA1 0xffc02e24 /* CAN Controller 0 Mailbox 17 Data 1 Register */ +#define CAN0_MB17_DATA2 0xffc02e28 /* CAN Controller 0 Mailbox 17 Data 2 Register */ +#define CAN0_MB17_DATA3 0xffc02e2c /* CAN Controller 0 Mailbox 17 Data 3 Register */ +#define CAN0_MB17_LENGTH 0xffc02e30 /* CAN Controller 0 Mailbox 17 Length Register */ +#define CAN0_MB17_TIMESTAMP 0xffc02e34 /* CAN Controller 0 Mailbox 17 Timestamp Register */ +#define CAN0_MB17_ID0 0xffc02e38 /* CAN Controller 0 Mailbox 17 ID0 Register */ +#define CAN0_MB17_ID1 0xffc02e3c /* CAN Controller 0 Mailbox 17 ID1 Register */ +#define CAN0_MB18_DATA0 0xffc02e40 /* CAN Controller 0 Mailbox 18 Data 0 Register */ +#define CAN0_MB18_DATA1 0xffc02e44 /* CAN Controller 0 Mailbox 18 Data 1 Register */ +#define CAN0_MB18_DATA2 0xffc02e48 /* CAN Controller 0 Mailbox 18 Data 2 Register */ +#define CAN0_MB18_DATA3 0xffc02e4c /* CAN Controller 0 Mailbox 18 Data 3 Register */ +#define CAN0_MB18_LENGTH 0xffc02e50 /* CAN Controller 0 Mailbox 18 Length Register */ +#define CAN0_MB18_TIMESTAMP 0xffc02e54 /* CAN Controller 0 Mailbox 18 Timestamp Register */ +#define CAN0_MB18_ID0 0xffc02e58 /* CAN Controller 0 Mailbox 18 ID0 Register */ +#define CAN0_MB18_ID1 0xffc02e5c /* CAN Controller 0 Mailbox 18 ID1 Register */ +#define CAN0_MB19_DATA0 0xffc02e60 /* CAN Controller 0 Mailbox 19 Data 0 Register */ +#define CAN0_MB19_DATA1 0xffc02e64 /* CAN Controller 0 Mailbox 19 Data 1 Register */ +#define CAN0_MB19_DATA2 0xffc02e68 /* CAN Controller 0 Mailbox 19 Data 2 Register */ +#define CAN0_MB19_DATA3 0xffc02e6c /* CAN Controller 0 Mailbox 19 Data 3 Register */ +#define CAN0_MB19_LENGTH 0xffc02e70 /* CAN Controller 0 Mailbox 19 Length Register */ +#define CAN0_MB19_TIMESTAMP 0xffc02e74 /* CAN Controller 0 Mailbox 19 Timestamp Register */ +#define CAN0_MB19_ID0 0xffc02e78 /* CAN Controller 0 Mailbox 19 ID0 Register */ +#define CAN0_MB19_ID1 0xffc02e7c /* CAN Controller 0 Mailbox 19 ID1 Register */ +#define CAN0_MB20_DATA0 0xffc02e80 /* CAN Controller 0 Mailbox 20 Data 0 Register */ +#define CAN0_MB20_DATA1 0xffc02e84 /* CAN Controller 0 Mailbox 20 Data 1 Register */ +#define CAN0_MB20_DATA2 0xffc02e88 /* CAN Controller 0 Mailbox 20 Data 2 Register */ +#define CAN0_MB20_DATA3 0xffc02e8c /* CAN Controller 0 Mailbox 20 Data 3 Register */ +#define CAN0_MB20_LENGTH 0xffc02e90 /* CAN Controller 0 Mailbox 20 Length Register */ +#define CAN0_MB20_TIMESTAMP 0xffc02e94 /* CAN Controller 0 Mailbox 20 Timestamp Register */ +#define CAN0_MB20_ID0 0xffc02e98 /* CAN Controller 0 Mailbox 20 ID0 Register */ +#define CAN0_MB20_ID1 0xffc02e9c /* CAN Controller 0 Mailbox 20 ID1 Register */ +#define CAN0_MB21_DATA0 0xffc02ea0 /* CAN Controller 0 Mailbox 21 Data 0 Register */ +#define CAN0_MB21_DATA1 0xffc02ea4 /* CAN Controller 0 Mailbox 21 Data 1 Register */ +#define CAN0_MB21_DATA2 0xffc02ea8 /* CAN Controller 0 Mailbox 21 Data 2 Register */ +#define CAN0_MB21_DATA3 0xffc02eac /* CAN Controller 0 Mailbox 21 Data 3 Register */ +#define CAN0_MB21_LENGTH 0xffc02eb0 /* CAN Controller 0 Mailbox 21 Length Register */ +#define CAN0_MB21_TIMESTAMP 0xffc02eb4 /* CAN Controller 0 Mailbox 21 Timestamp Register */ +#define CAN0_MB21_ID0 0xffc02eb8 /* CAN Controller 0 Mailbox 21 ID0 Register */ +#define CAN0_MB21_ID1 0xffc02ebc /* CAN Controller 0 Mailbox 21 ID1 Register */ +#define CAN0_MB22_DATA0 0xffc02ec0 /* CAN Controller 0 Mailbox 22 Data 0 Register */ +#define CAN0_MB22_DATA1 0xffc02ec4 /* CAN Controller 0 Mailbox 22 Data 1 Register */ +#define CAN0_MB22_DATA2 0xffc02ec8 /* CAN Controller 0 Mailbox 22 Data 2 Register */ +#define CAN0_MB22_DATA3 0xffc02ecc /* CAN Controller 0 Mailbox 22 Data 3 Register */ +#define CAN0_MB22_LENGTH 0xffc02ed0 /* CAN Controller 0 Mailbox 22 Length Register */ +#define CAN0_MB22_TIMESTAMP 0xffc02ed4 /* CAN Controller 0 Mailbox 22 Timestamp Register */ +#define CAN0_MB22_ID0 0xffc02ed8 /* CAN Controller 0 Mailbox 22 ID0 Register */ +#define CAN0_MB22_ID1 0xffc02edc /* CAN Controller 0 Mailbox 22 ID1 Register */ +#define CAN0_MB23_DATA0 0xffc02ee0 /* CAN Controller 0 Mailbox 23 Data 0 Register */ +#define CAN0_MB23_DATA1 0xffc02ee4 /* CAN Controller 0 Mailbox 23 Data 1 Register */ +#define CAN0_MB23_DATA2 0xffc02ee8 /* CAN Controller 0 Mailbox 23 Data 2 Register */ +#define CAN0_MB23_DATA3 0xffc02eec /* CAN Controller 0 Mailbox 23 Data 3 Register */ +#define CAN0_MB23_LENGTH 0xffc02ef0 /* CAN Controller 0 Mailbox 23 Length Register */ +#define CAN0_MB23_TIMESTAMP 0xffc02ef4 /* CAN Controller 0 Mailbox 23 Timestamp Register */ +#define CAN0_MB23_ID0 0xffc02ef8 /* CAN Controller 0 Mailbox 23 ID0 Register */ +#define CAN0_MB23_ID1 0xffc02efc /* CAN Controller 0 Mailbox 23 ID1 Register */ +#define CAN0_MB24_DATA0 0xffc02f00 /* CAN Controller 0 Mailbox 24 Data 0 Register */ +#define CAN0_MB24_DATA1 0xffc02f04 /* CAN Controller 0 Mailbox 24 Data 1 Register */ +#define CAN0_MB24_DATA2 0xffc02f08 /* CAN Controller 0 Mailbox 24 Data 2 Register */ +#define CAN0_MB24_DATA3 0xffc02f0c /* CAN Controller 0 Mailbox 24 Data 3 Register */ +#define CAN0_MB24_LENGTH 0xffc02f10 /* CAN Controller 0 Mailbox 24 Length Register */ +#define CAN0_MB24_TIMESTAMP 0xffc02f14 /* CAN Controller 0 Mailbox 24 Timestamp Register */ +#define CAN0_MB24_ID0 0xffc02f18 /* CAN Controller 0 Mailbox 24 ID0 Register */ +#define CAN0_MB24_ID1 0xffc02f1c /* CAN Controller 0 Mailbox 24 ID1 Register */ +#define CAN0_MB25_DATA0 0xffc02f20 /* CAN Controller 0 Mailbox 25 Data 0 Register */ +#define CAN0_MB25_DATA1 0xffc02f24 /* CAN Controller 0 Mailbox 25 Data 1 Register */ +#define CAN0_MB25_DATA2 0xffc02f28 /* CAN Controller 0 Mailbox 25 Data 2 Register */ +#define CAN0_MB25_DATA3 0xffc02f2c /* CAN Controller 0 Mailbox 25 Data 3 Register */ +#define CAN0_MB25_LENGTH 0xffc02f30 /* CAN Controller 0 Mailbox 25 Length Register */ +#define CAN0_MB25_TIMESTAMP 0xffc02f34 /* CAN Controller 0 Mailbox 25 Timestamp Register */ +#define CAN0_MB25_ID0 0xffc02f38 /* CAN Controller 0 Mailbox 25 ID0 Register */ +#define CAN0_MB25_ID1 0xffc02f3c /* CAN Controller 0 Mailbox 25 ID1 Register */ +#define CAN0_MB26_DATA0 0xffc02f40 /* CAN Controller 0 Mailbox 26 Data 0 Register */ +#define CAN0_MB26_DATA1 0xffc02f44 /* CAN Controller 0 Mailbox 26 Data 1 Register */ +#define CAN0_MB26_DATA2 0xffc02f48 /* CAN Controller 0 Mailbox 26 Data 2 Register */ +#define CAN0_MB26_DATA3 0xffc02f4c /* CAN Controller 0 Mailbox 26 Data 3 Register */ +#define CAN0_MB26_LENGTH 0xffc02f50 /* CAN Controller 0 Mailbox 26 Length Register */ +#define CAN0_MB26_TIMESTAMP 0xffc02f54 /* CAN Controller 0 Mailbox 26 Timestamp Register */ +#define CAN0_MB26_ID0 0xffc02f58 /* CAN Controller 0 Mailbox 26 ID0 Register */ +#define CAN0_MB26_ID1 0xffc02f5c /* CAN Controller 0 Mailbox 26 ID1 Register */ +#define CAN0_MB27_DATA0 0xffc02f60 /* CAN Controller 0 Mailbox 27 Data 0 Register */ +#define CAN0_MB27_DATA1 0xffc02f64 /* CAN Controller 0 Mailbox 27 Data 1 Register */ +#define CAN0_MB27_DATA2 0xffc02f68 /* CAN Controller 0 Mailbox 27 Data 2 Register */ +#define CAN0_MB27_DATA3 0xffc02f6c /* CAN Controller 0 Mailbox 27 Data 3 Register */ +#define CAN0_MB27_LENGTH 0xffc02f70 /* CAN Controller 0 Mailbox 27 Length Register */ +#define CAN0_MB27_TIMESTAMP 0xffc02f74 /* CAN Controller 0 Mailbox 27 Timestamp Register */ +#define CAN0_MB27_ID0 0xffc02f78 /* CAN Controller 0 Mailbox 27 ID0 Register */ +#define CAN0_MB27_ID1 0xffc02f7c /* CAN Controller 0 Mailbox 27 ID1 Register */ +#define CAN0_MB28_DATA0 0xffc02f80 /* CAN Controller 0 Mailbox 28 Data 0 Register */ +#define CAN0_MB28_DATA1 0xffc02f84 /* CAN Controller 0 Mailbox 28 Data 1 Register */ +#define CAN0_MB28_DATA2 0xffc02f88 /* CAN Controller 0 Mailbox 28 Data 2 Register */ +#define CAN0_MB28_DATA3 0xffc02f8c /* CAN Controller 0 Mailbox 28 Data 3 Register */ +#define CAN0_MB28_LENGTH 0xffc02f90 /* CAN Controller 0 Mailbox 28 Length Register */ +#define CAN0_MB28_TIMESTAMP 0xffc02f94 /* CAN Controller 0 Mailbox 28 Timestamp Register */ +#define CAN0_MB28_ID0 0xffc02f98 /* CAN Controller 0 Mailbox 28 ID0 Register */ +#define CAN0_MB28_ID1 0xffc02f9c /* CAN Controller 0 Mailbox 28 ID1 Register */ +#define CAN0_MB29_DATA0 0xffc02fa0 /* CAN Controller 0 Mailbox 29 Data 0 Register */ +#define CAN0_MB29_DATA1 0xffc02fa4 /* CAN Controller 0 Mailbox 29 Data 1 Register */ +#define CAN0_MB29_DATA2 0xffc02fa8 /* CAN Controller 0 Mailbox 29 Data 2 Register */ +#define CAN0_MB29_DATA3 0xffc02fac /* CAN Controller 0 Mailbox 29 Data 3 Register */ +#define CAN0_MB29_LENGTH 0xffc02fb0 /* CAN Controller 0 Mailbox 29 Length Register */ +#define CAN0_MB29_TIMESTAMP 0xffc02fb4 /* CAN Controller 0 Mailbox 29 Timestamp Register */ +#define CAN0_MB29_ID0 0xffc02fb8 /* CAN Controller 0 Mailbox 29 ID0 Register */ +#define CAN0_MB29_ID1 0xffc02fbc /* CAN Controller 0 Mailbox 29 ID1 Register */ +#define CAN0_MB30_DATA0 0xffc02fc0 /* CAN Controller 0 Mailbox 30 Data 0 Register */ +#define CAN0_MB30_DATA1 0xffc02fc4 /* CAN Controller 0 Mailbox 30 Data 1 Register */ +#define CAN0_MB30_DATA2 0xffc02fc8 /* CAN Controller 0 Mailbox 30 Data 2 Register */ +#define CAN0_MB30_DATA3 0xffc02fcc /* CAN Controller 0 Mailbox 30 Data 3 Register */ +#define CAN0_MB30_LENGTH 0xffc02fd0 /* CAN Controller 0 Mailbox 30 Length Register */ +#define CAN0_MB30_TIMESTAMP 0xffc02fd4 /* CAN Controller 0 Mailbox 30 Timestamp Register */ +#define CAN0_MB30_ID0 0xffc02fd8 /* CAN Controller 0 Mailbox 30 ID0 Register */ +#define CAN0_MB30_ID1 0xffc02fdc /* CAN Controller 0 Mailbox 30 ID1 Register */ +#define CAN0_MB31_DATA0 0xffc02fe0 /* CAN Controller 0 Mailbox 31 Data 0 Register */ +#define CAN0_MB31_DATA1 0xffc02fe4 /* CAN Controller 0 Mailbox 31 Data 1 Register */ +#define CAN0_MB31_DATA2 0xffc02fe8 /* CAN Controller 0 Mailbox 31 Data 2 Register */ +#define CAN0_MB31_DATA3 0xffc02fec /* CAN Controller 0 Mailbox 31 Data 3 Register */ +#define CAN0_MB31_LENGTH 0xffc02ff0 /* CAN Controller 0 Mailbox 31 Length Register */ +#define CAN0_MB31_TIMESTAMP 0xffc02ff4 /* CAN Controller 0 Mailbox 31 Timestamp Register */ +#define CAN0_MB31_ID0 0xffc02ff8 /* CAN Controller 0 Mailbox 31 ID0 Register */ +#define CAN0_MB31_ID1 0xffc02ffc /* CAN Controller 0 Mailbox 31 ID1 Register */ + +/* UART3 Registers */ + +#define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */ +#define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */ +#define UART3_GCTL 0xffc03108 /* Global Control Register */ +#define UART3_LCR 0xffc0310c /* Line Control Register */ +#define UART3_MCR 0xffc03110 /* Modem Control Register */ +#define UART3_LSR 0xffc03114 /* Line Status Register */ +#define UART3_MSR 0xffc03118 /* Modem Status Register */ +#define UART3_SCR 0xffc0311c /* Scratch Register */ +#define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */ +#define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */ +#define UART3_THR 0xffc03128 /* Transmit Hold Register */ +#define UART3_RBR 0xffc0312c /* Receive Buffer Register */ + +/* NFC Registers */ + +#define NFC_CTL 0xffc03b00 /* NAND Control Register */ +#define NFC_STAT 0xffc03b04 /* NAND Status Register */ +#define NFC_IRQSTAT 0xffc03b08 /* NAND Interrupt Status Register */ +#define NFC_IRQMASK 0xffc03b0c /* NAND Interrupt Mask Register */ +#define NFC_ECC0 0xffc03b10 /* NAND ECC Register 0 */ +#define NFC_ECC1 0xffc03b14 /* NAND ECC Register 1 */ +#define NFC_ECC2 0xffc03b18 /* NAND ECC Register 2 */ +#define NFC_ECC3 0xffc03b1c /* NAND ECC Register 3 */ +#define NFC_COUNT 0xffc03b20 /* NAND ECC Count Register */ +#define NFC_RST 0xffc03b24 /* NAND ECC Reset Register */ +#define NFC_PGCTL 0xffc03b28 /* NAND Page Control Register */ +#define NFC_READ 0xffc03b2c /* NAND Read Data Register */ +#define NFC_ADDR 0xffc03b40 /* NAND Address Register */ +#define NFC_CMD 0xffc03b44 /* NAND Command Register */ +#define NFC_DATA_WR 0xffc03b48 /* NAND Data Write Register */ +#define NFC_DATA_RD 0xffc03b4c /* NAND Data Read Register */ + +/* Counter Registers */ + +#define CNT_CONFIG 0xffc04200 /* Configuration Register */ +#define CNT_IMASK 0xffc04204 /* Interrupt Mask Register */ +#define CNT_STATUS 0xffc04208 /* Status Register */ +#define CNT_COMMAND 0xffc0420c /* Command Register */ +#define CNT_DEBOUNCE 0xffc04210 /* Debounce Register */ +#define CNT_COUNTER 0xffc04214 /* Counter Register */ +#define CNT_MAX 0xffc04218 /* Maximal Count Register */ +#define CNT_MIN 0xffc0421c /* Minimal Count Register */ + +/* OTP/FUSE Registers */ + +#define OTP_CONTROL 0xffc04300 /* OTP/Fuse Control Register */ +#define OTP_BEN 0xffc04304 /* OTP/Fuse Byte Enable */ +#define OTP_STATUS 0xffc04308 /* OTP/Fuse Status */ +#define OTP_TIMING 0xffc0430c /* OTP/Fuse Access Timing */ + +/* Security Registers */ + +#define SECURE_SYSSWT 0xffc04320 /* Secure System Switches */ +#define SECURE_CONTROL 0xffc04324 /* Secure Control */ +#define SECURE_STATUS 0xffc04328 /* Secure Status */ + +/* DMA Peripheral Mux Register */ + +#define DMAC1_PERIMUX 0xffc04340 /* DMA Controller 1 Peripheral Multiplexer Register */ + +/* OTP Read/Write Data Buffer Registers */ + +#define OTP_DATA0 0xffc04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ +#define OTP_DATA1 0xffc04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ +#define OTP_DATA2 0xffc04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ +#define OTP_DATA3 0xffc0438c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ + +/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 processor */ + +/* ********************************************************** */ +/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ +/* and MULTI BIT READ MACROS */ +/* ********************************************************** */ + +/* SIC_IMASK Masks */ +#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ +#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ +#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ +#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */ + +/* SIC_IWR Masks */ +#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ +#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ +#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ +#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ + +/* Bit masks for SIC_IAR0 */ + +#define PLL_WAKEUP 0x1 /* PLL Wakeup */ + +/* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */ + +#define DMA0_ERR 0x2 /* DMA Controller 0 Error */ +#define EPPI0_ERR 0x4 /* EPPI0 Error */ +#define SPORT0_ERR 0x8 /* SPORT0 Error */ +#define SPORT1_ERR 0x10 /* SPORT1 Error */ +#define SPI0_ERR 0x20 /* SPI0 Error */ +#define UART0_ERR 0x40 /* UART0 Error */ +#define RTC 0x80 /* Real-Time Clock */ +#define DMA12 0x100 /* DMA Channel 12 */ +#define DMA0 0x200 /* DMA Channel 0 */ +#define DMA1 0x400 /* DMA Channel 1 */ +#define DMA2 0x800 /* DMA Channel 2 */ +#define DMA3 0x1000 /* DMA Channel 3 */ +#define DMA4 0x2000 /* DMA Channel 4 */ +#define DMA6 0x4000 /* DMA Channel 6 */ +#define DMA7 0x8000 /* DMA Channel 7 */ +#define PINT0 0x80000 /* Pin Interrupt 0 */ +#define PINT1 0x100000 /* Pin Interrupt 1 */ +#define MDMA0 0x200000 /* Memory DMA Stream 0 */ +#define MDMA1 0x400000 /* Memory DMA Stream 1 */ +#define WDOG 0x800000 /* Watchdog Timer */ +#define DMA1_ERR 0x1000000 /* DMA Controller 1 Error */ +#define SPORT2_ERR 0x2000000 /* SPORT2 Error */ +#define SPORT3_ERR 0x4000000 /* SPORT3 Error */ +#define MXVR_SD 0x8000000 /* MXVR Synchronous Data */ +#define SPI1_ERR 0x10000000 /* SPI1 Error */ +#define SPI2_ERR 0x20000000 /* SPI2 Error */ +#define UART1_ERR 0x40000000 /* UART1 Error */ +#define UART2_ERR 0x80000000 /* UART2 Error */ + +/* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */ + +#define CAN0_ERR 0x1 /* CAN0 Error */ +#define DMA18 0x2 /* DMA Channel 18 */ +#define DMA19 0x4 /* DMA Channel 19 */ +#define DMA20 0x8 /* DMA Channel 20 */ +#define DMA21 0x10 /* DMA Channel 21 */ +#define DMA13 0x20 /* DMA Channel 13 */ +#define DMA14 0x40 /* DMA Channel 14 */ +#define DMA5 0x80 /* DMA Channel 5 */ +#define DMA23 0x100 /* DMA Channel 23 */ +#define DMA8 0x200 /* DMA Channel 8 */ +#define DMA9 0x400 /* DMA Channel 9 */ +#define DMA10 0x800 /* DMA Channel 10 */ +#define DMA11 0x1000 /* DMA Channel 11 */ +#define TWI0 0x2000 /* TWI0 */ +#define TWI1 0x4000 /* TWI1 */ +#define CAN0_RX 0x8000 /* CAN0 Receive */ +#define CAN0_TX 0x10000 /* CAN0 Transmit */ +#define MDMA2 0x20000 /* Memory DMA Stream 0 */ +#define MDMA3 0x40000 /* Memory DMA Stream 1 */ +#define MXVR_STAT 0x80000 /* MXVR Status */ +#define MXVR_CM 0x100000 /* MXVR Control Message */ +#define MXVR_AP 0x200000 /* MXVR Asynchronous Packet */ +#define EPPI1_ERR 0x400000 /* EPPI1 Error */ +#define EPPI2_ERR 0x800000 /* EPPI2 Error */ +#define UART3_ERR 0x1000000 /* UART3 Error */ +#define HOST_ERR 0x2000000 /* Host DMA Port Error */ +#define USB_ERR 0x4000000 /* USB Error */ +#define PIXC_ERR 0x8000000 /* Pixel Compositor Error */ +#define NFC_ERR 0x10000000 /* Nand Flash Controller Error */ +#define ATAPI_ERR 0x20000000 /* ATAPI Error */ +#define CAN1_ERR 0x40000000 /* CAN1 Error */ +#define DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */ +#define DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */ +#define DMAR0 0x80000000 /* DMAR0 Block */ +#define DMAR1 0x80000000 /* DMAR1 Block */ + +/* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */ + +#define DMA15 0x1 /* DMA Channel 15 */ +#define DMA16 0x2 /* DMA Channel 16 */ +#define DMA17 0x4 /* DMA Channel 17 */ +#define DMA22 0x8 /* DMA Channel 22 */ +#define CNT 0x10 /* Counter */ +#define KEY 0x20 /* Keypad */ +#define CAN1_RX 0x40 /* CAN1 Receive */ +#define CAN1_TX 0x80 /* CAN1 Transmit */ +#define SDH_INT_MASK0 0x100 /* SDH Mask 0 */ +#define SDH_INT_MASK1 0x200 /* SDH Mask 1 */ +#define USB_EINT 0x400 /* USB Exception */ +#define USB_INT0 0x800 /* USB Interrupt 0 */ +#define USB_INT1 0x1000 /* USB Interrupt 1 */ +#define USB_INT2 0x2000 /* USB Interrupt 2 */ +#define USB_DMAINT 0x4000 /* USB DMA */ +#define OTPSEC 0x8000 /* OTP Access Complete */ +#define TIMER0 0x400000 /* Timer 0 */ +#define TIMER1 0x800000 /* Timer 1 */ +#define TIMER2 0x1000000 /* Timer 2 */ +#define TIMER3 0x2000000 /* Timer 3 */ +#define TIMER4 0x4000000 /* Timer 4 */ +#define TIMER5 0x8000000 /* Timer 5 */ +#define TIMER6 0x10000000 /* Timer 6 */ +#define TIMER7 0x20000000 /* Timer 7 */ +#define PINT2 0x40000000 /* Pin Interrupt 2 */ +#define PINT3 0x80000000 /* Pin Interrupt 3 */ + +/* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */ + +#define DMAEN 0x1 /* DMA Channel Enable */ +#define WNR 0x2 /* DMA Direction */ +#define WDSIZE_8 0x0 /* Transfer Word Size = 8 */ +#define WDSIZE_16 0x4 /* Transfer Word Size = 16 */ +#define WDSIZE_32 0x8 /* Transfer Word Size = 32 */ +#define DMA2D 0x10 /* DMA Mode */ +#define RESTART 0x20 /* Work Unit Transitions */ +#define DI_SEL 0x40 /* Data Interrupt Timing Select */ +#define DI_EN 0x80 /* Data Interrupt Enable */ + +#define NDSIZE 0xf00 /* Flex Descriptor Size */ +#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ +#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ +#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ +#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ +#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ +#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ +#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ +#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ +#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ +#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ + +#define DMAFLOW 0xf000 /* Next Operation */ +#define DMAFLOW_STOP 0x0000 /* Stop Mode */ +#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ +#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ +#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ +#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ + +/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ + +#define DMA_DONE 0x1 /* DMA Completion Interrupt Status */ +#define DMA_ERR 0x2 /* DMA Error Interrupt Status */ +#define DFETCH 0x4 /* DMA Descriptor Fetch */ +#define DMA_RUN 0x8 /* DMA Channel Running */ + +/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ + +#define CTYPE 0x40 /* DMA Channel Type */ +#define PMAP 0xf000 /* Peripheral Mapped To This Channel */ + +/* Bit masks for DMACx_TCPER */ + +#define DCB_TRAFFIC_PERIOD 0xf /* DCB Traffic Control Period */ +#define DEB_TRAFFIC_PERIOD 0xf0 /* DEB Traffic Control Period */ +#define DAB_TRAFFIC_PERIOD 0x700 /* DAB Traffic Control Period */ +#define MDMA_ROUND_ROBIN_PERIOD 0xf800 /* MDMA Round Robin Period */ + +/* Bit masks for DMACx_TCCNT */ + +#define DCB_TRAFFIC_COUNT 0xf /* DCB Traffic Control Count */ +#define DEB_TRAFFIC_COUNT 0xf0 /* DEB Traffic Control Count */ +#define DAB_TRAFFIC_COUNT 0x700 /* DAB Traffic Control Count */ +#define MDMA_ROUND_ROBIN_COUNT 0xf800 /* MDMA Round Robin Count */ + +/* Bit masks for DMAC1_PERIMUX */ + +#define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */ + +/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ +/* EBIU_AMGCTL Masks */ +#define AMCKEN 0x0001 /* Enable CLKOUT */ +#define AMBEN_NONE 0x0000 /* All Banks Disabled */ +#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */ +#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */ +#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */ +#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */ + + +/* Bit masks for EBIU_AMBCTL0 */ + +#define B0RDYEN 0x1 /* Bank 0 ARDY Enable */ +#define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */ +#define B0TT 0xc /* Bank 0 transition time */ +#define B0ST 0x30 /* Bank 0 Setup time */ +#define B0HT 0xc0 /* Bank 0 Hold time */ +#define B0RAT 0xf00 /* Bank 0 Read access time */ +#define B0WAT 0xf000 /* Bank 0 write access time */ +#define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */ +#define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */ +#define B1TT 0xc0000 /* Bank 1 transition time */ +#define B1ST 0x300000 /* Bank 1 Setup time */ +#define B1HT 0xc00000 /* Bank 1 Hold time */ +#define B1RAT 0xf000000 /* Bank 1 Read access time */ +#define B1WAT 0xf0000000 /* Bank 1 write access time */ + +/* Bit masks for EBIU_AMBCTL1 */ + +#define B2RDYEN 0x1 /* Bank 2 ARDY Enable */ +#define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */ +#define B2TT 0xc /* Bank 2 transition time */ +#define B2ST 0x30 /* Bank 2 Setup time */ +#define B2HT 0xc0 /* Bank 2 Hold time */ +#define B2RAT 0xf00 /* Bank 2 Read access time */ +#define B2WAT 0xf000 /* Bank 2 write access time */ +#define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */ +#define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */ +#define B3TT 0xc0000 /* Bank 3 transition time */ +#define B3ST 0x300000 /* Bank 3 Setup time */ +#define B3HT 0xc00000 /* Bank 3 Hold time */ +#define B3RAT 0xf000000 /* Bank 3 Read access time */ +#define B3WAT 0xf0000000 /* Bank 3 write access time */ + +/* Bit masks for EBIU_MBSCTL */ + +#define AMSB0CTL 0x3 /* Async Memory Bank 0 select */ +#define AMSB1CTL 0xc /* Async Memory Bank 1 select */ +#define AMSB2CTL 0x30 /* Async Memory Bank 2 select */ +#define AMSB3CTL 0xc0 /* Async Memory Bank 3 select */ + +/* Bit masks for EBIU_MODE */ + +#define B0MODE 0x3 /* Async Memory Bank 0 Access Mode */ +#define B1MODE 0xc /* Async Memory Bank 1 Access Mode */ +#define B2MODE 0x30 /* Async Memory Bank 2 Access Mode */ +#define B3MODE 0xc0 /* Async Memory Bank 3 Access Mode */ + +/* Bit masks for EBIU_FCTL */ + +#define TESTSETLOCK 0x1 /* Test set lock */ +#define BCLK 0x6 /* Burst clock frequency */ +#define PGWS 0x38 /* Page wait states */ +#define PGSZ 0x40 /* Page size */ +#define RDDL 0x380 /* Read data delay */ + +/* Bit masks for EBIU_ARBSTAT */ + +#define ARBSTAT 0x1 /* Arbitration status */ +#define BGSTAT 0x2 /* Bus grant status */ + +/* Bit masks for EBIU_DDRCTL0 */ + +#define TREFI 0x3fff /* Refresh Interval */ +#define TRFC 0x3c000 /* Auto-refresh command period */ +#define TRP 0x3c0000 /* Pre charge-to-active command period */ +#define TRAS 0x3c00000 /* Min Active-to-pre charge time */ +#define TRC 0x3c000000 /* Active-to-active time */ +#define DDR_TRAS(x) ((x<<22)&TRAS) /* DDR tRAS = (1~15) cycles */ +#define DDR_TRP(x) ((x<<18)&TRP) /* DDR tRP = (1~15) cycles */ +#define DDR_TRC(x) ((x<<26)&TRC) /* DDR tRC = (1~15) cycles */ +#define DDR_TRFC(x) ((x<<14)&TRFC) /* DDR tRFC = (1~15) cycles */ +#define DDR_TREFI(x) (x&TREFI) /* DDR tRFC = (1~15) cycles */ + +/* Bit masks for EBIU_DDRCTL1 */ + +#define TRCD 0xf /* Active-to-Read/write delay */ +#define TMRD 0xf0 /* Mode register set to active */ +#define TWR 0x300 /* Write Recovery time */ +#define DDRDATWIDTH 0x3000 /* DDR data width */ +#define EXTBANKS 0xc000 /* External banks */ +#define DDRDEVWIDTH 0x30000 /* DDR device width */ +#define DDRDEVSIZE 0xc0000 /* DDR device size */ +#define TWTR 0xf0000000 /* Write-to-read delay */ +#define DDR_TWTR(x) ((x<<28)&TWTR) /* DDR tWTR = (1~15) cycles */ +#define DDR_TMRD(x) ((x<<4)&TMRD) /* DDR tMRD = (1~15) cycles */ +#define DDR_TWR(x) ((x<<8)&TWR) /* DDR tWR = (1~15) cycles */ +#define DDR_TRCD(x) (x&TRCD) /* DDR tRCD = (1~15) cycles */ +#define DDR_DATWIDTH 0x2000 /* DDR data width */ +#define EXTBANK_1 0 /* 1 external bank */ +#define EXTBANK_2 0x4000 /* 2 external banks */ +#define DEVSZ_64 0x40000 /* DDR External Bank Size = 64MB */ +#define DEVSZ_128 0x80000 /* DDR External Bank Size = 128MB */ +#define DEVSZ_256 0xc0000 /* DDR External Bank Size = 256MB */ +#define DEVSZ_512 0 /* DDR External Bank Size = 512MB */ +#define DEVWD_4 0 /* DDR Device Width = 4 Bits */ +#define DEVWD_8 0x10000 /* DDR Device Width = 8 Bits */ +#define DEVWD_16 0x20000 /* DDR Device Width = 16 Bits */ + +/* Bit masks for EBIU_DDRCTL2 */ + +#define BURSTLENGTH 0x7 /* Burst length */ +#define CASLATENCY 0x70 /* CAS latency */ +#define DLLRESET 0x100 /* DLL Reset */ +#define REGE 0x1000 /* Register mode enable */ +#define CL_1_5 0x50 /* DDR CAS Latency = 1.5 cycles */ +#define CL_2 0x20 /* DDR CAS Latency = 2 cycles */ +#define CL_2_5 0x60 /* DDR CAS Latency = 2.5 cycles */ +#define CL_3 0x30 /* DDR CAS Latency = 3 cycles */ + +/* Bit masks for EBIU_DDRCTL3 */ + +#define PASR 0x7 /* Partial array self-refresh */ + +/* Bit masks for EBIU_DDRQUE */ + +#define DEB1_PFLEN 0x3 /* Pre fetch length for DEB1 accesses */ +#define DEB2_PFLEN 0xc /* Pre fetch length for DEB2 accesses */ +#define DEB3_PFLEN 0x30 /* Pre fetch length for DEB3 accesses */ +#define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */ +#define DEB1_URGENT 0x1000 /* DEB1 Urgent */ +#define DEB2_URGENT 0x2000 /* DEB2 Urgent */ +#define DEB3_URGENT 0x4000 /* DEB3 Urgent */ + +/* Bit masks for EBIU_ERRMST */ + +#define DEB1_ERROR 0x1 /* DEB1 Error */ +#define DEB2_ERROR 0x2 /* DEB2 Error */ +#define DEB3_ERROR 0x4 /* DEB3 Error */ +#define CORE_ERROR 0x8 /* Core error */ +#define DEB_MERROR 0x10 /* DEB1 Error (2nd) */ +#define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */ +#define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */ +#define CORE_MERROR 0x80 /* Core Error (2nd) */ + +/* Bit masks for EBIU_ERRADD */ + +#define ERROR_ADDRESS 0xffffffff /* Error Address */ + +/* Bit masks for EBIU_RSTCTL */ + +#define DDRSRESET 0x1 /* DDR soft reset */ +#define PFTCHSRESET 0x4 /* DDR prefetch reset */ +#define SRREQ 0x8 /* Self-refresh request */ +#define SRACK 0x10 /* Self-refresh acknowledge */ +#define MDDRENABLE 0x20 /* Mobile DDR enable */ + +/* Bit masks for EBIU_DDRBRC0 */ + +#define BRC0 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBRC1 */ + +#define BRC1 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBRC2 */ + +#define BRC2 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBRC3 */ + +#define BRC3 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBRC4 */ + +#define BRC4 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBRC5 */ + +#define BRC5 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBRC6 */ + +#define BRC6 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBRC7 */ + +#define BRC7 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBWC0 */ + +#define BWC0 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBWC1 */ + +#define BWC1 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBWC2 */ + +#define BWC2 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBWC3 */ + +#define BWC3 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBWC4 */ + +#define BWC4 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBWC5 */ + +#define BWC5 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBWC6 */ + +#define BWC6 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBWC7 */ + +#define BWC7 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRACCT */ + +#define ACCT 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRTACT */ + +#define TECT 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRARCT */ + +#define ARCT 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRGC0 */ + +#define GC0 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRGC1 */ + +#define GC1 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRGC2 */ + +#define GC2 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRGC3 */ + +#define GC3 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRMCEN */ + +#define B0WCENABLE 0x1 /* Bank 0 write count enable */ +#define B1WCENABLE 0x2 /* Bank 1 write count enable */ +#define B2WCENABLE 0x4 /* Bank 2 write count enable */ +#define B3WCENABLE 0x8 /* Bank 3 write count enable */ +#define B4WCENABLE 0x10 /* Bank 4 write count enable */ +#define B5WCENABLE 0x20 /* Bank 5 write count enable */ +#define B6WCENABLE 0x40 /* Bank 6 write count enable */ +#define B7WCENABLE 0x80 /* Bank 7 write count enable */ +#define B0RCENABLE 0x100 /* Bank 0 read count enable */ +#define B1RCENABLE 0x200 /* Bank 1 read count enable */ +#define B2RCENABLE 0x400 /* Bank 2 read count enable */ +#define B3RCENABLE 0x800 /* Bank 3 read count enable */ +#define B4RCENABLE 0x1000 /* Bank 4 read count enable */ +#define B5RCENABLE 0x2000 /* Bank 5 read count enable */ +#define B6RCENABLE 0x4000 /* Bank 6 read count enable */ +#define B7RCENABLE 0x8000 /* Bank 7 read count enable */ +#define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */ +#define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */ +#define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */ +#define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */ +#define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */ +#define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */ +#define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */ +#define GCCONTROL 0x3000000 /* DDR Grant Count Control */ + +/* Bit masks for EBIU_DDRMCCL */ + +#define CB0WCOUNT 0x1 /* Clear write count 0 */ +#define CB1WCOUNT 0x2 /* Clear write count 1 */ +#define CB2WCOUNT 0x4 /* Clear write count 2 */ +#define CB3WCOUNT 0x8 /* Clear write count 3 */ +#define CB4WCOUNT 0x10 /* Clear write count 4 */ +#define CB5WCOUNT 0x20 /* Clear write count 5 */ +#define CB6WCOUNT 0x40 /* Clear write count 6 */ +#define CB7WCOUNT 0x80 /* Clear write count 7 */ +#define CBRCOUNT 0x100 /* Clear read count 0 */ +#define CB1RCOUNT 0x200 /* Clear read count 1 */ +#define CB2RCOUNT 0x400 /* Clear read count 2 */ +#define CB3RCOUNT 0x800 /* Clear read count 3 */ +#define CB4RCOUNT 0x1000 /* Clear read count 4 */ +#define CB5RCOUNT 0x2000 /* Clear read count 5 */ +#define CB6RCOUNT 0x4000 /* Clear read count 6 */ +#define CB7RCOUNT 0x8000 /* Clear read count 7 */ +#define CRACOUNT 0x10000 /* Clear row activation count */ +#define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */ +#define CARCOUNT 0x40000 /* Clear auto-refresh count */ +#define CG0COUNT 0x100000 /* Clear grant count 0 */ +#define CG1COUNT 0x200000 /* Clear grant count 1 */ +#define CG2COUNT 0x400000 /* Clear grant count 2 */ +#define CG3COUNT 0x800000 /* Clear grant count 3 */ + +/* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */ + +#define Px0 0x1 /* GPIO 0 */ +#define Px1 0x2 /* GPIO 1 */ +#define Px2 0x4 /* GPIO 2 */ +#define Px3 0x8 /* GPIO 3 */ +#define Px4 0x10 /* GPIO 4 */ +#define Px5 0x20 /* GPIO 5 */ +#define Px6 0x40 /* GPIO 6 */ +#define Px7 0x80 /* GPIO 7 */ +#define Px8 0x100 /* GPIO 8 */ +#define Px9 0x200 /* GPIO 9 */ +#define Px10 0x400 /* GPIO 10 */ +#define Px11 0x800 /* GPIO 11 */ +#define Px12 0x1000 /* GPIO 12 */ +#define Px13 0x2000 /* GPIO 13 */ +#define Px14 0x4000 /* GPIO 14 */ +#define Px15 0x8000 /* GPIO 15 */ + +/* Bit masks for PORTA_MUX - PORTJ_MUX */ + +#define PxM0 0x3 /* GPIO Mux 0 */ +#define PxM1 0xc /* GPIO Mux 1 */ +#define PxM2 0x30 /* GPIO Mux 2 */ +#define PxM3 0xc0 /* GPIO Mux 3 */ +#define PxM4 0x300 /* GPIO Mux 4 */ +#define PxM5 0xc00 /* GPIO Mux 5 */ +#define PxM6 0x3000 /* GPIO Mux 6 */ +#define PxM7 0xc000 /* GPIO Mux 7 */ +#define PxM8 0x30000 /* GPIO Mux 8 */ +#define PxM9 0xc0000 /* GPIO Mux 9 */ +#define PxM10 0x300000 /* GPIO Mux 10 */ +#define PxM11 0xc00000 /* GPIO Mux 11 */ +#define PxM12 0x3000000 /* GPIO Mux 12 */ +#define PxM13 0xc000000 /* GPIO Mux 13 */ +#define PxM14 0x30000000 /* GPIO Mux 14 */ +#define PxM15 0xc0000000 /* GPIO Mux 15 */ + + +/* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */ + +#define IB0 0x1 /* Interrupt Bit 0 */ +#define IB1 0x2 /* Interrupt Bit 1 */ +#define IB2 0x4 /* Interrupt Bit 2 */ +#define IB3 0x8 /* Interrupt Bit 3 */ +#define IB4 0x10 /* Interrupt Bit 4 */ +#define IB5 0x20 /* Interrupt Bit 5 */ +#define IB6 0x40 /* Interrupt Bit 6 */ +#define IB7 0x80 /* Interrupt Bit 7 */ +#define IB8 0x100 /* Interrupt Bit 8 */ +#define IB9 0x200 /* Interrupt Bit 9 */ +#define IB10 0x400 /* Interrupt Bit 10 */ +#define IB11 0x800 /* Interrupt Bit 11 */ +#define IB12 0x1000 /* Interrupt Bit 12 */ +#define IB13 0x2000 /* Interrupt Bit 13 */ +#define IB14 0x4000 /* Interrupt Bit 14 */ +#define IB15 0x8000 /* Interrupt Bit 15 */ + +/* Bit masks for TIMERx_CONFIG */ + +#define TMODE 0x3 /* Timer Mode */ +#define PULSE_HI 0x4 /* Pulse Polarity */ +#define PERIOD_CNT 0x8 /* Period Count */ +#define IRQ_ENA 0x10 /* Interrupt Request Enable */ +#define TIN_SEL 0x20 /* Timer Input Select */ +#define OUT_DIS 0x40 /* Output Pad Disable */ +#define CLK_SEL 0x80 /* Timer Clock Select */ +#define TOGGLE_HI 0x100 /* Toggle Mode */ +#define EMU_RUN 0x200 /* Emulation Behavior Select */ +#define ERR_TYP 0xc000 /* Error Type */ + +/* Bit masks for TIMER_ENABLE0 */ + +#define TIMEN0 0x1 /* Timer 0 Enable */ +#define TIMEN1 0x2 /* Timer 1 Enable */ +#define TIMEN2 0x4 /* Timer 2 Enable */ +#define TIMEN3 0x8 /* Timer 3 Enable */ +#define TIMEN4 0x10 /* Timer 4 Enable */ +#define TIMEN5 0x20 /* Timer 5 Enable */ +#define TIMEN6 0x40 /* Timer 6 Enable */ +#define TIMEN7 0x80 /* Timer 7 Enable */ + +/* Bit masks for TIMER_DISABLE0 */ + +#define TIMDIS0 0x1 /* Timer 0 Disable */ +#define TIMDIS1 0x2 /* Timer 1 Disable */ +#define TIMDIS2 0x4 /* Timer 2 Disable */ +#define TIMDIS3 0x8 /* Timer 3 Disable */ +#define TIMDIS4 0x10 /* Timer 4 Disable */ +#define TIMDIS5 0x20 /* Timer 5 Disable */ +#define TIMDIS6 0x40 /* Timer 6 Disable */ +#define TIMDIS7 0x80 /* Timer 7 Disable */ + +/* Bit masks for TIMER_STATUS0 */ + +#define TIMIL0 0x1 /* Timer 0 Interrupt */ +#define TIMIL1 0x2 /* Timer 1 Interrupt */ +#define TIMIL2 0x4 /* Timer 2 Interrupt */ +#define TIMIL3 0x8 /* Timer 3 Interrupt */ +#define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */ +#define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */ +#define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */ +#define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */ +#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */ +#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */ +#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */ +#define TRUN3 0x8000 /* Timer 3 Slave Enable Status */ +#define TIMIL4 0x10000 /* Timer 4 Interrupt */ +#define TIMIL5 0x20000 /* Timer 5 Interrupt */ +#define TIMIL6 0x40000 /* Timer 6 Interrupt */ +#define TIMIL7 0x80000 /* Timer 7 Interrupt */ +#define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */ +#define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */ +#define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */ +#define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */ +#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ +#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ +#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ +#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ + +/* Bit masks for WDOG_CTL */ + +#define WDEV 0x6 /* Watchdog Event */ +#define WDEN 0xff0 /* Watchdog Enable */ +#define WDRO 0x8000 /* Watchdog Rolled Over */ + +/* Bit masks for CNT_CONFIG */ + +#define CNTE 0x1 /* Counter Enable */ +#define DEBE 0x2 /* Debounce Enable */ +#define CDGINV 0x10 /* CDG Pin Polarity Invert */ +#define CUDINV 0x20 /* CUD Pin Polarity Invert */ +#define CZMINV 0x40 /* CZM Pin Polarity Invert */ +#define CNTMODE 0x700 /* Counter Operating Mode */ +#define ZMZC 0x800 /* CZM Zeroes Counter Enable */ +#define BNDMODE 0x3000 /* Boundary register Mode */ +#define INPDIS 0x8000 /* CUG and CDG Input Disable */ + +/* Bit masks for CNT_IMASK */ + +#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */ +#define UCIE 0x2 /* Up count Interrupt Enable */ +#define DCIE 0x4 /* Down count Interrupt Enable */ +#define MINCIE 0x8 /* Min Count Interrupt Enable */ +#define MAXCIE 0x10 /* Max Count Interrupt Enable */ +#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */ +#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */ +#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */ +#define CZMIE 0x100 /* CZM Pin Interrupt Enable */ +#define CZMEIE 0x200 /* CZM Error Interrupt Enable */ +#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */ + +/* Bit masks for CNT_STATUS */ + +#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */ +#define UCII 0x2 /* Up count Interrupt Identifier */ +#define DCII 0x4 /* Down count Interrupt Identifier */ +#define MINCII 0x8 /* Min Count Interrupt Identifier */ +#define MAXCII 0x10 /* Max Count Interrupt Identifier */ +#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */ +#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */ +#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */ +#define CZMII 0x100 /* CZM Pin Interrupt Identifier */ +#define CZMEII 0x200 /* CZM Error Interrupt Identifier */ +#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */ + +/* Bit masks for CNT_COMMAND */ + +#define W1LCNT 0xf /* Load Counter Register */ +#define W1LMIN 0xf0 /* Load Min Register */ +#define W1LMAX 0xf00 /* Load Max Register */ +#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */ + +/* Bit masks for CNT_DEBOUNCE */ + +#define DPRESCALE 0xf /* Load Counter Register */ + +/* Bit masks for RTC_STAT */ + +#define SECONDS 0x3f /* Seconds */ +#define MINUTES 0xfc0 /* Minutes */ +#define HOURS 0x1f000 /* Hours */ +#define DAY_COUNTER 0xfffe0000 /* Day Counter */ + +/* Bit masks for RTC_ICTL */ + +#define STOPWATCH_INTERRUPT_ENABLE 0x1 /* Stopwatch Interrupt Enable */ +#define ALARM_INTERRUPT_ENABLE 0x2 /* Alarm Interrupt Enable */ +#define SECONDS_INTERRUPT_ENABLE 0x4 /* Seconds Interrupt Enable */ +#define MINUTES_INTERRUPT_ENABLE 0x8 /* Minutes Interrupt Enable */ +#define HOURS_INTERRUPT_ENABLE 0x10 /* Hours Interrupt Enable */ +#define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x20 /* 24 Hours Interrupt Enable */ +#define DAY_ALARM_INTERRUPT_ENABLE 0x40 /* Day Alarm Interrupt Enable */ +#define WRITE_COMPLETE_INTERRUPT_ENABLE 0x8000 /* Write Complete Interrupt Enable */ + +/* Bit masks for RTC_ISTAT */ + +#define STOPWATCH_EVENT_FLAG 0x1 /* Stopwatch Event Flag */ +#define ALARM_EVENT_FLAG 0x2 /* Alarm Event Flag */ +#define SECONDS_EVENT_FLAG 0x4 /* Seconds Event Flag */ +#define MINUTES_EVENT_FLAG 0x8 /* Minutes Event Flag */ +#define HOURS_EVENT_FLAG 0x10 /* Hours Event Flag */ +#define TWENTY_FOUR_HOURS_EVENT_FLAG 0x20 /* 24 Hours Event Flag */ +#define DAY_ALARM_EVENT_FLAG 0x40 /* Day Alarm Event Flag */ +#define WRITE_PENDING__STATUS 0x4000 /* Write Pending Status */ +#define WRITE_COMPLETE 0x8000 /* Write Complete */ + +/* Bit masks for RTC_SWCNT */ + +#define STOPWATCH_COUNT 0xffff /* Stopwatch Count */ + +/* Bit masks for RTC_ALARM */ + +#define SECONDS 0x3f /* Seconds */ +#define MINUTES 0xfc0 /* Minutes */ +#define HOURS 0x1f000 /* Hours */ +#define DAY 0xfffe0000 /* Day */ + +/* Bit masks for RTC_PREN */ + +#define PREN 0x1 /* Prescaler Enable */ + +/* Bit masks for OTP_CONTROL */ + +#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ +#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */ +#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */ +#define FWRTEST 0x2000 /* OTP/Fuse Write Test */ +#define FRDEN 0x4000 /* OTP/Fuse Read Enable */ +#define FWREN 0x8000 /* OTP/Fuse Write Enable */ + +/* Bit masks for OTP_BEN */ + +#define FBEN 0xffff /* OTP/Fuse Byte Enable */ + +/* Bit masks for OTP_STATUS */ + +#define FCOMP 0x1 /* OTP/Fuse Access Complete */ +#define FERROR 0x2 /* OTP/Fuse Access Error */ +#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */ +#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */ +#define FPGMEN 0x40 /* OTP/Fuse Program Enable */ + +/* Bit masks for OTP_TIMING */ + +#define USECDIV 0xff /* Micro Second Divider */ +#define READACC 0x7f00 /* Read Access Time */ +#define CPUMPRL 0x38000 /* Charge Pump Release Time */ +#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */ +#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */ +#define PGMTIME 0xff000000 /* Program Time */ + +/* Bit masks for SECURE_SYSSWT */ + +#define EMUDABL 0x1 /* Emulation Disable. */ +#define RSTDABL 0x2 /* Reset Disable */ +#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ +#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ +#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ +#define DMA0OVR 0x800 /* DMA0 Memory Access Override */ +#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ +#define EMUOVR 0x4000 /* Emulation Override */ +#define OTPSEN 0x8000 /* OTP Secrets Enable. */ +#define L2DABL 0x70000 /* L2 Memory Disable. */ + +/* Bit masks for SECURE_CONTROL */ + +#define SECURE0 0x1 /* SECURE 0 */ +#define SECURE1 0x2 /* SECURE 1 */ +#define SECURE2 0x4 /* SECURE 2 */ +#define SECURE3 0x8 /* SECURE 3 */ + +/* Bit masks for SECURE_STATUS */ + +#define SECMODE 0x3 /* Secured Mode Control State */ +#define NMI 0x4 /* Non Maskable Interrupt */ +#define AFVALID 0x8 /* Authentication Firmware Valid */ +#define AFEXIT 0x10 /* Authentication Firmware Exit */ +#define SECSTAT 0xe0 /* Secure Status */ + +/* Bit masks for PLL_DIV */ + +#define CSEL 0x30 /* Core Select */ +#define SSEL 0xf /* System Select */ +#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ +#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ +#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ +#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ + +/* Bit masks for PLL_CTL */ + +#define MSEL 0x7e00 /* Multiplier Select */ +#define BYPASS 0x100 /* PLL Bypass Enable */ +#define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */ +#define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */ +#define PDWN 0x20 /* Power Down */ +#define STOPCK 0x8 /* Stop Clock */ +#define PLL_OFF 0x2 /* Disable PLL */ +#define DF 0x1 /* Divide Frequency */ + +/* SWRST Masks */ +#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ +#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ +#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ +#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ +#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ + +/* Bit masks for PLL_STAT */ + +#define PLL_LOCKED 0x20 /* PLL Locked Status */ +#define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */ +#define FULL_ON 0x2 /* Full-On Mode */ +#define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */ +#define RTCWS 0x400 /* RTC/Reset Wake-Up Status */ +#define CANWS 0x800 /* CAN Wake-Up Status */ +#define USBWS 0x2000 /* USB Wake-Up Status */ +#define KPADWS 0x4000 /* Keypad Wake-Up Status */ +#define ROTWS 0x8000 /* Rotary Wake-Up Status */ +#define GPWS 0x1000 /* General-Purpose Wake-Up Status */ + +/* Bit masks for VR_CTL */ + +#define FREQ 0x3 /* Regulator Switching Frequency */ +#define GAIN 0xc /* Voltage Output Level Gain */ +#define VLEV 0xf0 /* Internal Voltage Level */ +#define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */ +#define WAKE 0x100 /* RTC/Reset Wake-Up Enable */ +#define CANWE 0x200 /* CAN0/1 Wake-Up Enable */ +#define GPWE 0x400 /* General-Purpose Wake-Up Enable */ +#define USBWE 0x800 /* USB Wake-Up Enable */ +#define KPADWE 0x1000 /* Keypad Wake-Up Enable */ +#define ROTWE 0x2000 /* Rotary Wake-Up Enable */ + +#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ +#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ +#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ + +#define GAIN_5 0x0000 /* GAIN = 5*/ +#define GAIN_10 0x0004 /* GAIN = 1*/ +#define GAIN_20 0x0008 /* GAIN = 2*/ +#define GAIN_50 0x000C /* GAIN = 5*/ + +#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ +#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ +#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ +#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ +#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ +#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ +#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ +#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ +#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ +#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ + +/* Bit masks for NFC_CTL */ + +#define WR_DLY 0xf /* Write Strobe Delay */ +#define RD_DLY 0xf0 /* Read Strobe Delay */ +#define NWIDTH 0x100 /* NAND Data Width */ +#define PG_SIZE 0x200 /* Page Size */ + +/* Bit masks for NFC_STAT */ + +#define NBUSY 0x1 /* Not Busy */ +#define WB_FULL 0x2 /* Write Buffer Full */ +#define PG_WR_STAT 0x4 /* Page Write Pending */ +#define PG_RD_STAT 0x8 /* Page Read Pending */ +#define WB_EMPTY 0x10 /* Write Buffer Empty */ + +/* Bit masks for NFC_IRQSTAT */ + +#define NBUSYIRQ 0x1 /* Not Busy IRQ */ +#define WB_OVF 0x2 /* Write Buffer Overflow */ +#define WB_EDGE 0x4 /* Write Buffer Edge Detect */ +#define RD_RDY 0x8 /* Read Data Ready */ +#define WR_DONE 0x10 /* Page Write Done */ + +/* Bit masks for NFC_IRQMASK */ + +#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */ +#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */ +#define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */ +#define MASK_RDRDY 0x8 /* Mask Read Data Ready */ +#define MASK_WRDONE 0x10 /* Mask Write Done */ + +/* Bit masks for NFC_RST */ + +#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */ + +/* Bit masks for NFC_PGCTL */ + +#define PG_RD_START 0x1 /* Page Read Start */ +#define PG_WR_START 0x2 /* Page Write Start */ + +/* Bit masks for NFC_ECC0 */ + +#define ECC0 0x7ff /* Parity Calculation Result0 */ + +/* Bit masks for NFC_ECC1 */ + +#define ECC1 0x7ff /* Parity Calculation Result1 */ + +/* Bit masks for NFC_ECC2 */ + +#define ECC2 0x7ff /* Parity Calculation Result2 */ + +/* Bit masks for NFC_ECC3 */ + +#define ECC3 0x7ff /* Parity Calculation Result3 */ + +/* Bit masks for NFC_COUNT */ + +#define ECCCNT 0x3ff /* Transfer Count */ + +/* Bit masks for CAN0_CONTROL */ + +#define SRS 0x1 /* Software Reset */ +#define DNM 0x2 /* DeviceNet Mode */ +#define ABO 0x4 /* Auto Bus On */ +#define WBA 0x10 /* Wakeup On CAN Bus Activity */ +#define SMR 0x20 /* Sleep Mode Request */ +#define CSR 0x40 /* CAN Suspend Mode Request */ +#define CCR 0x80 /* CAN Configuration Mode Request */ + +/* Bit masks for CAN0_STATUS */ + +#define WT 0x1 /* CAN Transmit Warning Flag */ +#define WR 0x2 /* CAN Receive Warning Flag */ +#define EP 0x4 /* CAN Error Passive Mode */ +#define EBO 0x8 /* CAN Error Bus Off Mode */ +#define CSA 0x40 /* CAN Suspend Mode Acknowledge */ +#define CCA 0x80 /* CAN Configuration Mode Acknowledge */ +#define MBPTR 0x1f00 /* Mailbox Pointer */ +#define TRM 0x4000 /* Transmit Mode Status */ +#define REC 0x8000 /* Receive Mode Status */ + +/* Bit masks for CAN0_DEBUG */ + +#define DEC 0x1 /* Disable Transmit/Receive Error Counters */ +#define DRI 0x2 /* Disable CANRX Input Pin */ +#define DTO 0x4 /* Disable CANTX Output Pin */ +#define DIL 0x8 /* Disable Internal Loop */ +#define MAA 0x10 /* Mode Auto-Acknowledge */ +#define MRB 0x20 /* Mode Read Back */ +#define CDE 0x8000 /* CAN Debug Mode Enable */ + +/* Bit masks for CAN0_CLOCK */ + +#define BRP 0x3ff /* CAN Bit Rate Prescaler */ + +/* Bit masks for CAN0_TIMING */ + +#define SJW 0x300 /* Synchronization Jump Width */ +#define SAM 0x80 /* Sampling */ +#define TSEG2 0x70 /* Time Segment 2 */ +#define TSEG1 0xf /* Time Segment 1 */ + +/* Bit masks for CAN0_INTR */ + +#define CANRX 0x80 /* Serial Input From Transceiver */ +#define CANTX 0x40 /* Serial Output To Transceiver */ +#define SMACK 0x8 /* Sleep Mode Acknowledge */ +#define GIRQ 0x4 /* Global Interrupt Request Status */ +#define MBTIRQ 0x2 /* Mailbox Transmit Interrupt Request */ +#define MBRIRQ 0x1 /* Mailbox Receive Interrupt Request */ + +/* Bit masks for CAN0_GIM */ + +#define EWTIM 0x1 /* Error Warning Transmit Interrupt Mask */ +#define EWRIM 0x2 /* Error Warning Receive Interrupt Mask */ +#define EPIM 0x4 /* Error Passive Interrupt Mask */ +#define BOIM 0x8 /* Bus Off Interrupt Mask */ +#define WUIM 0x10 /* Wakeup Interrupt Mask */ +#define UIAIM 0x20 /* Unimplemented Address Interrupt Mask */ +#define AAIM 0x40 /* Abort Acknowledge Interrupt Mask */ +#define RMLIM 0x80 /* Receive Message Lost Interrupt Mask */ +#define UCEIM 0x100 /* Universal Counter Exceeded Interrupt Mask */ +#define ADIM 0x400 /* Access Denied Interrupt Mask */ + +/* Bit masks for CAN0_GIS */ + +#define EWTIS 0x1 /* Error Warning Transmit Interrupt Status */ +#define EWRIS 0x2 /* Error Warning Receive Interrupt Status */ +#define EPIS 0x4 /* Error Passive Interrupt Status */ +#define BOIS 0x8 /* Bus Off Interrupt Status */ +#define WUIS 0x10 /* Wakeup Interrupt Status */ +#define UIAIS 0x20 /* Unimplemented Address Interrupt Status */ +#define AAIS 0x40 /* Abort Acknowledge Interrupt Status */ +#define RMLIS 0x80 /* Receive Message Lost Interrupt Status */ +#define UCEIS 0x100 /* Universal Counter Exceeded Interrupt Status */ +#define ADIS 0x400 /* Access Denied Interrupt Status */ + +/* Bit masks for CAN0_GIF */ + +#define EWTIF 0x1 /* Error Warning Transmit Interrupt Flag */ +#define EWRIF 0x2 /* Error Warning Receive Interrupt Flag */ +#define EPIF 0x4 /* Error Passive Interrupt Flag */ +#define BOIF 0x8 /* Bus Off Interrupt Flag */ +#define WUIF 0x10 /* Wakeup Interrupt Flag */ +#define UIAIF 0x20 /* Unimplemented Address Interrupt Flag */ +#define AAIF 0x40 /* Abort Acknowledge Interrupt Flag */ +#define RMLIF 0x80 /* Receive Message Lost Interrupt Flag */ +#define UCEIF 0x100 /* Universal Counter Exceeded Interrupt Flag */ +#define ADIF 0x400 /* Access Denied Interrupt Flag */ + +/* Bit masks for CAN0_MBTD */ + +#define TDR 0x80 /* Temporary Disable Request */ +#define TDA 0x40 /* Temporary Disable Acknowledge */ +#define TDPTR 0x1f /* Temporary Disable Pointer */ + +/* Bit masks for CAN0_UCCNF */ + +#define UCCNF 0xf /* Universal Counter Configuration */ +#define UCRC 0x20 /* Universal Counter Reload/Clear */ +#define UCCT 0x40 /* Universal Counter CAN Trigger */ +#define UCE 0x80 /* Universal Counter Enable */ + +/* Bit masks for CAN0_UCCNT */ + +#define UCCNT 0xffff /* Universal Counter Count Value */ + +/* Bit masks for CAN0_UCRC */ + +#define UCVAL 0xffff /* Universal Counter Reload/Capture Value */ + +/* Bit masks for CAN0_CEC */ + +#define RXECNT 0xff /* Receive Error Counter */ +#define TXECNT 0xff00 /* Transmit Error Counter */ + +/* Bit masks for CAN0_ESR */ + +#define FER 0x80 /* Form Error */ +#define BEF 0x40 /* Bit Error Flag */ +#define SA0 0x20 /* Stuck At Dominant */ +#define CRCE 0x10 /* CRC Error */ +#define SER 0x8 /* Stuff Bit Error */ +#define ACKE 0x4 /* Acknowledge Error */ + +/* Bit masks for CAN0_EWR */ + +#define EWLTEC 0xff00 /* Transmit Error Warning Limit */ +#define EWLREC 0xff /* Receive Error Warning Limit */ + +/* Bit masks for CAN0_AMxx_H */ + +#define FDF 0x8000 /* Filter On Data Field */ +#define FMD 0x4000 /* Full Mask Data */ +#define AMIDE 0x2000 /* Acceptance Mask Identifier Extension */ +#define BASEID 0x1ffc /* Base Identifier */ +#define EXTID_HI 0x3 /* Extended Identifier High Bits */ + +/* Bit masks for CAN0_AMxx_L */ + +#define EXTID_LO 0xffff /* Extended Identifier Low Bits */ +#define DFM 0xffff /* Data Field Mask */ + +/* Bit masks for CAN0_MBxx_ID1 */ + +#define AME 0x8000 /* Acceptance Mask Enable */ +#define RTR 0x4000 /* Remote Transmission Request */ +#define IDE 0x2000 /* Identifier Extension */ +#define BASEID 0x1ffc /* Base Identifier */ +#define EXTID_HI 0x3 /* Extended Identifier High Bits */ + +/* Bit masks for CAN0_MBxx_ID0 */ + +#define EXTID_LO 0xffff /* Extended Identifier Low Bits */ +#define DFM 0xffff /* Data Field Mask */ + +/* Bit masks for CAN0_MBxx_TIMESTAMP */ + +#define TSV 0xffff /* Time Stamp Value */ + +/* Bit masks for CAN0_MBxx_LENGTH */ + +#define DLC 0xf /* Data Length Code */ + +/* Bit masks for CAN0_MBxx_DATA3 */ + +#define CAN_BYTE0 0xff00 /* Data Field Byte 0 */ +#define CAN_BYTE1 0xff /* Data Field Byte 1 */ + +/* Bit masks for CAN0_MBxx_DATA2 */ + +#define CAN_BYTE2 0xff00 /* Data Field Byte 2 */ +#define CAN_BYTE3 0xff /* Data Field Byte 3 */ + +/* Bit masks for CAN0_MBxx_DATA1 */ + +#define CAN_BYTE4 0xff00 /* Data Field Byte 4 */ +#define CAN_BYTE5 0xff /* Data Field Byte 5 */ + +/* Bit masks for CAN0_MBxx_DATA0 */ + +#define CAN_BYTE6 0xff00 /* Data Field Byte 6 */ +#define CAN_BYTE7 0xff /* Data Field Byte 7 */ + +/* Bit masks for CAN0_MC1 */ + +#define MC0 0x1 /* Mailbox 0 Enable */ +#define MC1 0x2 /* Mailbox 1 Enable */ +#define MC2 0x4 /* Mailbox 2 Enable */ +#define MC3 0x8 /* Mailbox 3 Enable */ +#define MC4 0x10 /* Mailbox 4 Enable */ +#define MC5 0x20 /* Mailbox 5 Enable */ +#define MC6 0x40 /* Mailbox 6 Enable */ +#define MC7 0x80 /* Mailbox 7 Enable */ +#define MC8 0x100 /* Mailbox 8 Enable */ +#define MC9 0x200 /* Mailbox 9 Enable */ +#define MC10 0x400 /* Mailbox 10 Enable */ +#define MC11 0x800 /* Mailbox 11 Enable */ +#define MC12 0x1000 /* Mailbox 12 Enable */ +#define MC13 0x2000 /* Mailbox 13 Enable */ +#define MC14 0x4000 /* Mailbox 14 Enable */ +#define MC15 0x8000 /* Mailbox 15 Enable */ + +/* Bit masks for CAN0_MC2 */ + +#define MC16 0x1 /* Mailbox 16 Enable */ +#define MC17 0x2 /* Mailbox 17 Enable */ +#define MC18 0x4 /* Mailbox 18 Enable */ +#define MC19 0x8 /* Mailbox 19 Enable */ +#define MC20 0x10 /* Mailbox 20 Enable */ +#define MC21 0x20 /* Mailbox 21 Enable */ +#define MC22 0x40 /* Mailbox 22 Enable */ +#define MC23 0x80 /* Mailbox 23 Enable */ +#define MC24 0x100 /* Mailbox 24 Enable */ +#define MC25 0x200 /* Mailbox 25 Enable */ +#define MC26 0x400 /* Mailbox 26 Enable */ +#define MC27 0x800 /* Mailbox 27 Enable */ +#define MC28 0x1000 /* Mailbox 28 Enable */ +#define MC29 0x2000 /* Mailbox 29 Enable */ +#define MC30 0x4000 /* Mailbox 30 Enable */ +#define MC31 0x8000 /* Mailbox 31 Enable */ + +/* Bit masks for CAN0_MD1 */ + +#define MD0 0x1 /* Mailbox 0 Receive Enable */ +#define MD1 0x2 /* Mailbox 1 Receive Enable */ +#define MD2 0x4 /* Mailbox 2 Receive Enable */ +#define MD3 0x8 /* Mailbox 3 Receive Enable */ +#define MD4 0x10 /* Mailbox 4 Receive Enable */ +#define MD5 0x20 /* Mailbox 5 Receive Enable */ +#define MD6 0x40 /* Mailbox 6 Receive Enable */ +#define MD7 0x80 /* Mailbox 7 Receive Enable */ +#define MD8 0x100 /* Mailbox 8 Receive Enable */ +#define MD9 0x200 /* Mailbox 9 Receive Enable */ +#define MD10 0x400 /* Mailbox 10 Receive Enable */ +#define MD11 0x800 /* Mailbox 11 Receive Enable */ +#define MD12 0x1000 /* Mailbox 12 Receive Enable */ +#define MD13 0x2000 /* Mailbox 13 Receive Enable */ +#define MD14 0x4000 /* Mailbox 14 Receive Enable */ +#define MD15 0x8000 /* Mailbox 15 Receive Enable */ + +/* Bit masks for CAN0_MD2 */ + +#define MD16 0x1 /* Mailbox 16 Receive Enable */ +#define MD17 0x2 /* Mailbox 17 Receive Enable */ +#define MD18 0x4 /* Mailbox 18 Receive Enable */ +#define MD19 0x8 /* Mailbox 19 Receive Enable */ +#define MD20 0x10 /* Mailbox 20 Receive Enable */ +#define MD21 0x20 /* Mailbox 21 Receive Enable */ +#define MD22 0x40 /* Mailbox 22 Receive Enable */ +#define MD23 0x80 /* Mailbox 23 Receive Enable */ +#define MD24 0x100 /* Mailbox 24 Receive Enable */ +#define MD25 0x200 /* Mailbox 25 Receive Enable */ +#define MD26 0x400 /* Mailbox 26 Receive Enable */ +#define MD27 0x800 /* Mailbox 27 Receive Enable */ +#define MD28 0x1000 /* Mailbox 28 Receive Enable */ +#define MD29 0x2000 /* Mailbox 29 Receive Enable */ +#define MD30 0x4000 /* Mailbox 30 Receive Enable */ +#define MD31 0x8000 /* Mailbox 31 Receive Enable */ + +/* Bit masks for CAN0_RMP1 */ + +#define RMP0 0x1 /* Mailbox 0 Receive Message Pending */ +#define RMP1 0x2 /* Mailbox 1 Receive Message Pending */ +#define RMP2 0x4 /* Mailbox 2 Receive Message Pending */ +#define RMP3 0x8 /* Mailbox 3 Receive Message Pending */ +#define RMP4 0x10 /* Mailbox 4 Receive Message Pending */ +#define RMP5 0x20 /* Mailbox 5 Receive Message Pending */ +#define RMP6 0x40 /* Mailbox 6 Receive Message Pending */ +#define RMP7 0x80 /* Mailbox 7 Receive Message Pending */ +#define RMP8 0x100 /* Mailbox 8 Receive Message Pending */ +#define RMP9 0x200 /* Mailbox 9 Receive Message Pending */ +#define RMP10 0x400 /* Mailbox 10 Receive Message Pending */ +#define RMP11 0x800 /* Mailbox 11 Receive Message Pending */ +#define RMP12 0x1000 /* Mailbox 12 Receive Message Pending */ +#define RMP13 0x2000 /* Mailbox 13 Receive Message Pending */ +#define RMP14 0x4000 /* Mailbox 14 Receive Message Pending */ +#define RMP15 0x8000 /* Mailbox 15 Receive Message Pending */ + +/* Bit masks for CAN0_RMP2 */ + +#define RMP16 0x1 /* Mailbox 16 Receive Message Pending */ +#define RMP17 0x2 /* Mailbox 17 Receive Message Pending */ +#define RMP18 0x4 /* Mailbox 18 Receive Message Pending */ +#define RMP19 0x8 /* Mailbox 19 Receive Message Pending */ +#define RMP20 0x10 /* Mailbox 20 Receive Message Pending */ +#define RMP21 0x20 /* Mailbox 21 Receive Message Pending */ +#define RMP22 0x40 /* Mailbox 22 Receive Message Pending */ +#define RMP23 0x80 /* Mailbox 23 Receive Message Pending */ +#define RMP24 0x100 /* Mailbox 24 Receive Message Pending */ +#define RMP25 0x200 /* Mailbox 25 Receive Message Pending */ +#define RMP26 0x400 /* Mailbox 26 Receive Message Pending */ +#define RMP27 0x800 /* Mailbox 27 Receive Message Pending */ +#define RMP28 0x1000 /* Mailbox 28 Receive Message Pending */ +#define RMP29 0x2000 /* Mailbox 29 Receive Message Pending */ +#define RMP30 0x4000 /* Mailbox 30 Receive Message Pending */ +#define RMP31 0x8000 /* Mailbox 31 Receive Message Pending */ + +/* Bit masks for CAN0_RML1 */ + +#define RML0 0x1 /* Mailbox 0 Receive Message Lost */ +#define RML1 0x2 /* Mailbox 1 Receive Message Lost */ +#define RML2 0x4 /* Mailbox 2 Receive Message Lost */ +#define RML3 0x8 /* Mailbox 3 Receive Message Lost */ +#define RML4 0x10 /* Mailbox 4 Receive Message Lost */ +#define RML5 0x20 /* Mailbox 5 Receive Message Lost */ +#define RML6 0x40 /* Mailbox 6 Receive Message Lost */ +#define RML7 0x80 /* Mailbox 7 Receive Message Lost */ +#define RML8 0x100 /* Mailbox 8 Receive Message Lost */ +#define RML9 0x200 /* Mailbox 9 Receive Message Lost */ +#define RML10 0x400 /* Mailbox 10 Receive Message Lost */ +#define RML11 0x800 /* Mailbox 11 Receive Message Lost */ +#define RML12 0x1000 /* Mailbox 12 Receive Message Lost */ +#define RML13 0x2000 /* Mailbox 13 Receive Message Lost */ +#define RML14 0x4000 /* Mailbox 14 Receive Message Lost */ +#define RML15 0x8000 /* Mailbox 15 Receive Message Lost */ + +/* Bit masks for CAN0_RML2 */ + +#define RML16 0x1 /* Mailbox 16 Receive Message Lost */ +#define RML17 0x2 /* Mailbox 17 Receive Message Lost */ +#define RML18 0x4 /* Mailbox 18 Receive Message Lost */ +#define RML19 0x8 /* Mailbox 19 Receive Message Lost */ +#define RML20 0x10 /* Mailbox 20 Receive Message Lost */ +#define RML21 0x20 /* Mailbox 21 Receive Message Lost */ +#define RML22 0x40 /* Mailbox 22 Receive Message Lost */ +#define RML23 0x80 /* Mailbox 23 Receive Message Lost */ +#define RML24 0x100 /* Mailbox 24 Receive Message Lost */ +#define RML25 0x200 /* Mailbox 25 Receive Message Lost */ +#define RML26 0x400 /* Mailbox 26 Receive Message Lost */ +#define RML27 0x800 /* Mailbox 27 Receive Message Lost */ +#define RML28 0x1000 /* Mailbox 28 Receive Message Lost */ +#define RML29 0x2000 /* Mailbox 29 Receive Message Lost */ +#define RML30 0x4000 /* Mailbox 30 Receive Message Lost */ +#define RML31 0x8000 /* Mailbox 31 Receive Message Lost */ + +/* Bit masks for CAN0_OPSS1 */ + +#define OPSS0 0x1 /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS1 0x2 /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS2 0x4 /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS3 0x8 /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS4 0x10 /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS5 0x20 /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS6 0x40 /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS7 0x80 /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS8 0x100 /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS9 0x200 /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS10 0x400 /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS11 0x800 /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS12 0x1000 /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS13 0x2000 /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS14 0x4000 /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS15 0x8000 /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */ + +/* Bit masks for CAN0_OPSS2 */ + +#define OPSS16 0x1 /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS17 0x2 /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS18 0x4 /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS19 0x8 /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS20 0x10 /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS21 0x20 /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS22 0x40 /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS23 0x80 /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS24 0x100 /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS25 0x200 /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS26 0x400 /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS27 0x800 /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS28 0x1000 /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS29 0x2000 /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS30 0x4000 /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */ +#define OPSS31 0x8000 /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */ + +/* Bit masks for CAN0_TRS1 */ + +#define TRS0 0x1 /* Mailbox 0 Transmit Request Set */ +#define TRS1 0x2 /* Mailbox 1 Transmit Request Set */ +#define TRS2 0x4 /* Mailbox 2 Transmit Request Set */ +#define TRS3 0x8 /* Mailbox 3 Transmit Request Set */ +#define TRS4 0x10 /* Mailbox 4 Transmit Request Set */ +#define TRS5 0x20 /* Mailbox 5 Transmit Request Set */ +#define TRS6 0x40 /* Mailbox 6 Transmit Request Set */ +#define TRS7 0x80 /* Mailbox 7 Transmit Request Set */ +#define TRS8 0x100 /* Mailbox 8 Transmit Request Set */ +#define TRS9 0x200 /* Mailbox 9 Transmit Request Set */ +#define TRS10 0x400 /* Mailbox 10 Transmit Request Set */ +#define TRS11 0x800 /* Mailbox 11 Transmit Request Set */ +#define TRS12 0x1000 /* Mailbox 12 Transmit Request Set */ +#define TRS13 0x2000 /* Mailbox 13 Transmit Request Set */ +#define TRS14 0x4000 /* Mailbox 14 Transmit Request Set */ +#define TRS15 0x8000 /* Mailbox 15 Transmit Request Set */ + +/* Bit masks for CAN0_TRS2 */ + +#define TRS16 0x1 /* Mailbox 16 Transmit Request Set */ +#define TRS17 0x2 /* Mailbox 17 Transmit Request Set */ +#define TRS18 0x4 /* Mailbox 18 Transmit Request Set */ +#define TRS19 0x8 /* Mailbox 19 Transmit Request Set */ +#define TRS20 0x10 /* Mailbox 20 Transmit Request Set */ +#define TRS21 0x20 /* Mailbox 21 Transmit Request Set */ +#define TRS22 0x40 /* Mailbox 22 Transmit Request Set */ +#define TRS23 0x80 /* Mailbox 23 Transmit Request Set */ +#define TRS24 0x100 /* Mailbox 24 Transmit Request Set */ +#define TRS25 0x200 /* Mailbox 25 Transmit Request Set */ +#define TRS26 0x400 /* Mailbox 26 Transmit Request Set */ +#define TRS27 0x800 /* Mailbox 27 Transmit Request Set */ +#define TRS28 0x1000 /* Mailbox 28 Transmit Request Set */ +#define TRS29 0x2000 /* Mailbox 29 Transmit Request Set */ +#define TRS30 0x4000 /* Mailbox 30 Transmit Request Set */ +#define TRS31 0x8000 /* Mailbox 31 Transmit Request Set */ + +/* Bit masks for CAN0_TRR1 */ + +#define TRR0 0x1 /* Mailbox 0 Transmit Request Reset */ +#define TRR1 0x2 /* Mailbox 1 Transmit Request Reset */ +#define TRR2 0x4 /* Mailbox 2 Transmit Request Reset */ +#define TRR3 0x8 /* Mailbox 3 Transmit Request Reset */ +#define TRR4 0x10 /* Mailbox 4 Transmit Request Reset */ +#define TRR5 0x20 /* Mailbox 5 Transmit Request Reset */ +#define TRR6 0x40 /* Mailbox 6 Transmit Request Reset */ +#define TRR7 0x80 /* Mailbox 7 Transmit Request Reset */ +#define TRR8 0x100 /* Mailbox 8 Transmit Request Reset */ +#define TRR9 0x200 /* Mailbox 9 Transmit Request Reset */ +#define TRR10 0x400 /* Mailbox 10 Transmit Request Reset */ +#define TRR11 0x800 /* Mailbox 11 Transmit Request Reset */ +#define TRR12 0x1000 /* Mailbox 12 Transmit Request Reset */ +#define TRR13 0x2000 /* Mailbox 13 Transmit Request Reset */ +#define TRR14 0x4000 /* Mailbox 14 Transmit Request Reset */ +#define TRR15 0x8000 /* Mailbox 15 Transmit Request Reset */ + +/* Bit masks for CAN0_TRR2 */ + +#define TRR16 0x1 /* Mailbox 16 Transmit Request Reset */ +#define TRR17 0x2 /* Mailbox 17 Transmit Request Reset */ +#define TRR18 0x4 /* Mailbox 18 Transmit Request Reset */ +#define TRR19 0x8 /* Mailbox 19 Transmit Request Reset */ +#define TRR20 0x10 /* Mailbox 20 Transmit Request Reset */ +#define TRR21 0x20 /* Mailbox 21 Transmit Request Reset */ +#define TRR22 0x40 /* Mailbox 22 Transmit Request Reset */ +#define TRR23 0x80 /* Mailbox 23 Transmit Request Reset */ +#define TRR24 0x100 /* Mailbox 24 Transmit Request Reset */ +#define TRR25 0x200 /* Mailbox 25 Transmit Request Reset */ +#define TRR26 0x400 /* Mailbox 26 Transmit Request Reset */ +#define TRR27 0x800 /* Mailbox 27 Transmit Request Reset */ +#define TRR28 0x1000 /* Mailbox 28 Transmit Request Reset */ +#define TRR29 0x2000 /* Mailbox 29 Transmit Request Reset */ +#define TRR30 0x4000 /* Mailbox 30 Transmit Request Reset */ +#define TRR31 0x8000 /* Mailbox 31 Transmit Request Reset */ + +/* Bit masks for CAN0_AA1 */ + +#define AA0 0x1 /* Mailbox 0 Abort Acknowledge */ +#define AA1 0x2 /* Mailbox 1 Abort Acknowledge */ +#define AA2 0x4 /* Mailbox 2 Abort Acknowledge */ +#define AA3 0x8 /* Mailbox 3 Abort Acknowledge */ +#define AA4 0x10 /* Mailbox 4 Abort Acknowledge */ +#define AA5 0x20 /* Mailbox 5 Abort Acknowledge */ +#define AA6 0x40 /* Mailbox 6 Abort Acknowledge */ +#define AA7 0x80 /* Mailbox 7 Abort Acknowledge */ +#define AA8 0x100 /* Mailbox 8 Abort Acknowledge */ +#define AA9 0x200 /* Mailbox 9 Abort Acknowledge */ +#define AA10 0x400 /* Mailbox 10 Abort Acknowledge */ +#define AA11 0x800 /* Mailbox 11 Abort Acknowledge */ +#define AA12 0x1000 /* Mailbox 12 Abort Acknowledge */ +#define AA13 0x2000 /* Mailbox 13 Abort Acknowledge */ +#define AA14 0x4000 /* Mailbox 14 Abort Acknowledge */ +#define AA15 0x8000 /* Mailbox 15 Abort Acknowledge */ + +/* Bit masks for CAN0_AA2 */ + +#define AA16 0x1 /* Mailbox 16 Abort Acknowledge */ +#define AA17 0x2 /* Mailbox 17 Abort Acknowledge */ +#define AA18 0x4 /* Mailbox 18 Abort Acknowledge */ +#define AA19 0x8 /* Mailbox 19 Abort Acknowledge */ +#define AA20 0x10 /* Mailbox 20 Abort Acknowledge */ +#define AA21 0x20 /* Mailbox 21 Abort Acknowledge */ +#define AA22 0x40 /* Mailbox 22 Abort Acknowledge */ +#define AA23 0x80 /* Mailbox 23 Abort Acknowledge */ +#define AA24 0x100 /* Mailbox 24 Abort Acknowledge */ +#define AA25 0x200 /* Mailbox 25 Abort Acknowledge */ +#define AA26 0x400 /* Mailbox 26 Abort Acknowledge */ +#define AA27 0x800 /* Mailbox 27 Abort Acknowledge */ +#define AA28 0x1000 /* Mailbox 28 Abort Acknowledge */ +#define AA29 0x2000 /* Mailbox 29 Abort Acknowledge */ +#define AA30 0x4000 /* Mailbox 30 Abort Acknowledge */ +#define AA31 0x8000 /* Mailbox 31 Abort Acknowledge */ + +/* Bit masks for CAN0_TA1 */ + +#define TA0 0x1 /* Mailbox 0 Transmit Acknowledge */ +#define TA1 0x2 /* Mailbox 1 Transmit Acknowledge */ +#define TA2 0x4 /* Mailbox 2 Transmit Acknowledge */ +#define TA3 0x8 /* Mailbox 3 Transmit Acknowledge */ +#define TA4 0x10 /* Mailbox 4 Transmit Acknowledge */ +#define TA5 0x20 /* Mailbox 5 Transmit Acknowledge */ +#define TA6 0x40 /* Mailbox 6 Transmit Acknowledge */ +#define TA7 0x80 /* Mailbox 7 Transmit Acknowledge */ +#define TA8 0x100 /* Mailbox 8 Transmit Acknowledge */ +#define TA9 0x200 /* Mailbox 9 Transmit Acknowledge */ +#define TA10 0x400 /* Mailbox 10 Transmit Acknowledge */ +#define TA11 0x800 /* Mailbox 11 Transmit Acknowledge */ +#define TA12 0x1000 /* Mailbox 12 Transmit Acknowledge */ +#define TA13 0x2000 /* Mailbox 13 Transmit Acknowledge */ +#define TA14 0x4000 /* Mailbox 14 Transmit Acknowledge */ +#define TA15 0x8000 /* Mailbox 15 Transmit Acknowledge */ + +/* Bit masks for CAN0_TA2 */ + +#define TA16 0x1 /* Mailbox 16 Transmit Acknowledge */ +#define TA17 0x2 /* Mailbox 17 Transmit Acknowledge */ +#define TA18 0x4 /* Mailbox 18 Transmit Acknowledge */ +#define TA19 0x8 /* Mailbox 19 Transmit Acknowledge */ +#define TA20 0x10 /* Mailbox 20 Transmit Acknowledge */ +#define TA21 0x20 /* Mailbox 21 Transmit Acknowledge */ +#define TA22 0x40 /* Mailbox 22 Transmit Acknowledge */ +#define TA23 0x80 /* Mailbox 23 Transmit Acknowledge */ +#define TA24 0x100 /* Mailbox 24 Transmit Acknowledge */ +#define TA25 0x200 /* Mailbox 25 Transmit Acknowledge */ +#define TA26 0x400 /* Mailbox 26 Transmit Acknowledge */ +#define TA27 0x800 /* Mailbox 27 Transmit Acknowledge */ +#define TA28 0x1000 /* Mailbox 28 Transmit Acknowledge */ +#define TA29 0x2000 /* Mailbox 29 Transmit Acknowledge */ +#define TA30 0x4000 /* Mailbox 30 Transmit Acknowledge */ +#define TA31 0x8000 /* Mailbox 31 Transmit Acknowledge */ + +/* Bit masks for CAN0_RFH1 */ + +#define RFH0 0x1 /* Mailbox 0 Remote Frame Handling Enable */ +#define RFH1 0x2 /* Mailbox 1 Remote Frame Handling Enable */ +#define RFH2 0x4 /* Mailbox 2 Remote Frame Handling Enable */ +#define RFH3 0x8 /* Mailbox 3 Remote Frame Handling Enable */ +#define RFH4 0x10 /* Mailbox 4 Remote Frame Handling Enable */ +#define RFH5 0x20 /* Mailbox 5 Remote Frame Handling Enable */ +#define RFH6 0x40 /* Mailbox 6 Remote Frame Handling Enable */ +#define RFH7 0x80 /* Mailbox 7 Remote Frame Handling Enable */ +#define RFH8 0x100 /* Mailbox 8 Remote Frame Handling Enable */ +#define RFH9 0x200 /* Mailbox 9 Remote Frame Handling Enable */ +#define RFH10 0x400 /* Mailbox 10 Remote Frame Handling Enable */ +#define RFH11 0x800 /* Mailbox 11 Remote Frame Handling Enable */ +#define RFH12 0x1000 /* Mailbox 12 Remote Frame Handling Enable */ +#define RFH13 0x2000 /* Mailbox 13 Remote Frame Handling Enable */ +#define RFH14 0x4000 /* Mailbox 14 Remote Frame Handling Enable */ +#define RFH15 0x8000 /* Mailbox 15 Remote Frame Handling Enable */ + +/* Bit masks for CAN0_RFH2 */ + +#define RFH16 0x1 /* Mailbox 16 Remote Frame Handling Enable */ +#define RFH17 0x2 /* Mailbox 17 Remote Frame Handling Enable */ +#define RFH18 0x4 /* Mailbox 18 Remote Frame Handling Enable */ +#define RFH19 0x8 /* Mailbox 19 Remote Frame Handling Enable */ +#define RFH20 0x10 /* Mailbox 20 Remote Frame Handling Enable */ +#define RFH21 0x20 /* Mailbox 21 Remote Frame Handling Enable */ +#define RFH22 0x40 /* Mailbox 22 Remote Frame Handling Enable */ +#define RFH23 0x80 /* Mailbox 23 Remote Frame Handling Enable */ +#define RFH24 0x100 /* Mailbox 24 Remote Frame Handling Enable */ +#define RFH25 0x200 /* Mailbox 25 Remote Frame Handling Enable */ +#define RFH26 0x400 /* Mailbox 26 Remote Frame Handling Enable */ +#define RFH27 0x800 /* Mailbox 27 Remote Frame Handling Enable */ +#define RFH28 0x1000 /* Mailbox 28 Remote Frame Handling Enable */ +#define RFH29 0x2000 /* Mailbox 29 Remote Frame Handling Enable */ +#define RFH30 0x4000 /* Mailbox 30 Remote Frame Handling Enable */ +#define RFH31 0x8000 /* Mailbox 31 Remote Frame Handling Enable */ + +/* Bit masks for CAN0_MBIM1 */ + +#define MBIM0 0x1 /* Mailbox 0 Mailbox Interrupt Mask */ +#define MBIM1 0x2 /* Mailbox 1 Mailbox Interrupt Mask */ +#define MBIM2 0x4 /* Mailbox 2 Mailbox Interrupt Mask */ +#define MBIM3 0x8 /* Mailbox 3 Mailbox Interrupt Mask */ +#define MBIM4 0x10 /* Mailbox 4 Mailbox Interrupt Mask */ +#define MBIM5 0x20 /* Mailbox 5 Mailbox Interrupt Mask */ +#define MBIM6 0x40 /* Mailbox 6 Mailbox Interrupt Mask */ +#define MBIM7 0x80 /* Mailbox 7 Mailbox Interrupt Mask */ +#define MBIM8 0x100 /* Mailbox 8 Mailbox Interrupt Mask */ +#define MBIM9 0x200 /* Mailbox 9 Mailbox Interrupt Mask */ +#define MBIM10 0x400 /* Mailbox 10 Mailbox Interrupt Mask */ +#define MBIM11 0x800 /* Mailbox 11 Mailbox Interrupt Mask */ +#define MBIM12 0x1000 /* Mailbox 12 Mailbox Interrupt Mask */ +#define MBIM13 0x2000 /* Mailbox 13 Mailbox Interrupt Mask */ +#define MBIM14 0x4000 /* Mailbox 14 Mailbox Interrupt Mask */ +#define MBIM15 0x8000 /* Mailbox 15 Mailbox Interrupt Mask */ + +/* Bit masks for CAN0_MBIM2 */ + +#define MBIM16 0x1 /* Mailbox 16 Mailbox Interrupt Mask */ +#define MBIM17 0x2 /* Mailbox 17 Mailbox Interrupt Mask */ +#define MBIM18 0x4 /* Mailbox 18 Mailbox Interrupt Mask */ +#define MBIM19 0x8 /* Mailbox 19 Mailbox Interrupt Mask */ +#define MBIM20 0x10 /* Mailbox 20 Mailbox Interrupt Mask */ +#define MBIM21 0x20 /* Mailbox 21 Mailbox Interrupt Mask */ +#define MBIM22 0x40 /* Mailbox 22 Mailbox Interrupt Mask */ +#define MBIM23 0x80 /* Mailbox 23 Mailbox Interrupt Mask */ +#define MBIM24 0x100 /* Mailbox 24 Mailbox Interrupt Mask */ +#define MBIM25 0x200 /* Mailbox 25 Mailbox Interrupt Mask */ +#define MBIM26 0x400 /* Mailbox 26 Mailbox Interrupt Mask */ +#define MBIM27 0x800 /* Mailbox 27 Mailbox Interrupt Mask */ +#define MBIM28 0x1000 /* Mailbox 28 Mailbox Interrupt Mask */ +#define MBIM29 0x2000 /* Mailbox 29 Mailbox Interrupt Mask */ +#define MBIM30 0x4000 /* Mailbox 30 Mailbox Interrupt Mask */ +#define MBIM31 0x8000 /* Mailbox 31 Mailbox Interrupt Mask */ + +/* Bit masks for CAN0_MBTIF1 */ + +#define MBTIF0 0x1 /* Mailbox 0 Mailbox Transmit Interrupt Flag */ +#define MBTIF1 0x2 /* Mailbox 1 Mailbox Transmit Interrupt Flag */ +#define MBTIF2 0x4 /* Mailbox 2 Mailbox Transmit Interrupt Flag */ +#define MBTIF3 0x8 /* Mailbox 3 Mailbox Transmit Interrupt Flag */ +#define MBTIF4 0x10 /* Mailbox 4 Mailbox Transmit Interrupt Flag */ +#define MBTIF5 0x20 /* Mailbox 5 Mailbox Transmit Interrupt Flag */ +#define MBTIF6 0x40 /* Mailbox 6 Mailbox Transmit Interrupt Flag */ +#define MBTIF7 0x80 /* Mailbox 7 Mailbox Transmit Interrupt Flag */ +#define MBTIF8 0x100 /* Mailbox 8 Mailbox Transmit Interrupt Flag */ +#define MBTIF9 0x200 /* Mailbox 9 Mailbox Transmit Interrupt Flag */ +#define MBTIF10 0x400 /* Mailbox 10 Mailbox Transmit Interrupt Flag */ +#define MBTIF11 0x800 /* Mailbox 11 Mailbox Transmit Interrupt Flag */ +#define MBTIF12 0x1000 /* Mailbox 12 Mailbox Transmit Interrupt Flag */ +#define MBTIF13 0x2000 /* Mailbox 13 Mailbox Transmit Interrupt Flag */ +#define MBTIF14 0x4000 /* Mailbox 14 Mailbox Transmit Interrupt Flag */ +#define MBTIF15 0x8000 /* Mailbox 15 Mailbox Transmit Interrupt Flag */ + +/* Bit masks for CAN0_MBTIF2 */ + +#define MBTIF16 0x1 /* Mailbox 16 Mailbox Transmit Interrupt Flag */ +#define MBTIF17 0x2 /* Mailbox 17 Mailbox Transmit Interrupt Flag */ +#define MBTIF18 0x4 /* Mailbox 18 Mailbox Transmit Interrupt Flag */ +#define MBTIF19 0x8 /* Mailbox 19 Mailbox Transmit Interrupt Flag */ +#define MBTIF20 0x10 /* Mailbox 20 Mailbox Transmit Interrupt Flag */ +#define MBTIF21 0x20 /* Mailbox 21 Mailbox Transmit Interrupt Flag */ +#define MBTIF22 0x40 /* Mailbox 22 Mailbox Transmit Interrupt Flag */ +#define MBTIF23 0x80 /* Mailbox 23 Mailbox Transmit Interrupt Flag */ +#define MBTIF24 0x100 /* Mailbox 24 Mailbox Transmit Interrupt Flag */ +#define MBTIF25 0x200 /* Mailbox 25 Mailbox Transmit Interrupt Flag */ +#define MBTIF26 0x400 /* Mailbox 26 Mailbox Transmit Interrupt Flag */ +#define MBTIF27 0x800 /* Mailbox 27 Mailbox Transmit Interrupt Flag */ +#define MBTIF28 0x1000 /* Mailbox 28 Mailbox Transmit Interrupt Flag */ +#define MBTIF29 0x2000 /* Mailbox 29 Mailbox Transmit Interrupt Flag */ +#define MBTIF30 0x4000 /* Mailbox 30 Mailbox Transmit Interrupt Flag */ +#define MBTIF31 0x8000 /* Mailbox 31 Mailbox Transmit Interrupt Flag */ + +/* Bit masks for CAN0_MBRIF1 */ + +#define MBRIF0 0x1 /* Mailbox 0 Mailbox Receive Interrupt Flag */ +#define MBRIF1 0x2 /* Mailbox 1 Mailbox Receive Interrupt Flag */ +#define MBRIF2 0x4 /* Mailbox 2 Mailbox Receive Interrupt Flag */ +#define MBRIF3 0x8 /* Mailbox 3 Mailbox Receive Interrupt Flag */ +#define MBRIF4 0x10 /* Mailbox 4 Mailbox Receive Interrupt Flag */ +#define MBRIF5 0x20 /* Mailbox 5 Mailbox Receive Interrupt Flag */ +#define MBRIF6 0x40 /* Mailbox 6 Mailbox Receive Interrupt Flag */ +#define MBRIF7 0x80 /* Mailbox 7 Mailbox Receive Interrupt Flag */ +#define MBRIF8 0x100 /* Mailbox 8 Mailbox Receive Interrupt Flag */ +#define MBRIF9 0x200 /* Mailbox 9 Mailbox Receive Interrupt Flag */ +#define MBRIF10 0x400 /* Mailbox 10 Mailbox Receive Interrupt Flag */ +#define MBRIF11 0x800 /* Mailbox 11 Mailbox Receive Interrupt Flag */ +#define MBRIF12 0x1000 /* Mailbox 12 Mailbox Receive Interrupt Flag */ +#define MBRIF13 0x2000 /* Mailbox 13 Mailbox Receive Interrupt Flag */ +#define MBRIF14 0x4000 /* Mailbox 14 Mailbox Receive Interrupt Flag */ +#define MBRIF15 0x8000 /* Mailbox 15 Mailbox Receive Interrupt Flag */ + +/* Bit masks for CAN0_MBRIF2 */ + +#define MBRIF16 0x1 /* Mailbox 16 Mailbox Receive Interrupt Flag */ +#define MBRIF17 0x2 /* Mailbox 17 Mailbox Receive Interrupt Flag */ +#define MBRIF18 0x4 /* Mailbox 18 Mailbox Receive Interrupt Flag */ +#define MBRIF19 0x8 /* Mailbox 19 Mailbox Receive Interrupt Flag */ +#define MBRIF20 0x10 /* Mailbox 20 Mailbox Receive Interrupt Flag */ +#define MBRIF21 0x20 /* Mailbox 21 Mailbox Receive Interrupt Flag */ +#define MBRIF22 0x40 /* Mailbox 22 Mailbox Receive Interrupt Flag */ +#define MBRIF23 0x80 /* Mailbox 23 Mailbox Receive Interrupt Flag */ +#define MBRIF24 0x100 /* Mailbox 24 Mailbox Receive Interrupt Flag */ +#define MBRIF25 0x200 /* Mailbox 25 Mailbox Receive Interrupt Flag */ +#define MBRIF26 0x400 /* Mailbox 26 Mailbox Receive Interrupt Flag */ +#define MBRIF27 0x800 /* Mailbox 27 Mailbox Receive Interrupt Flag */ +#define MBRIF28 0x1000 /* Mailbox 28 Mailbox Receive Interrupt Flag */ +#define MBRIF29 0x2000 /* Mailbox 29 Mailbox Receive Interrupt Flag */ +#define MBRIF30 0x4000 /* Mailbox 30 Mailbox Receive Interrupt Flag */ +#define MBRIF31 0x8000 /* Mailbox 31 Mailbox Receive Interrupt Flag */ + +/* Bit masks for EPPIx_STATUS */ + +#define CFIFO_ERR 0x1 /* Chroma FIFO Error */ +#define YFIFO_ERR 0x2 /* Luma FIFO Error */ +#define LTERR_OVR 0x4 /* Line Track Overflow */ +#define LTERR_UNDR 0x8 /* Line Track Underflow */ +#define FTERR_OVR 0x10 /* Frame Track Overflow */ +#define FTERR_UNDR 0x20 /* Frame Track Underflow */ +#define ERR_NCOR 0x40 /* Preamble Error Not Corrected */ +#define DMA1URQ 0x80 /* DMA1 Urgent Request */ +#define DMA0URQ 0x100 /* DMA0 Urgent Request */ +#define ERR_DET 0x4000 /* Preamble Error Detected */ +#define FLD 0x8000 /* Field */ + +/* Bit masks for EPPIx_CONTROL */ + +#define EPPI_EN 0x1 /* Enable */ +#define EPPI_DIR 0x2 /* Direction */ +#define XFR_TYPE 0xc /* Operating Mode */ +#define FS_CFG 0x30 /* Frame Sync Configuration */ +#define FLD_SEL 0x40 /* Field Select/Trigger */ +#define ITU_TYPE 0x80 /* ITU Interlaced or Progressive */ +#define BLANKGEN 0x100 /* ITU Output Mode with Internal Blanking Generation */ +#define ICLKGEN 0x200 /* Internal Clock Generation */ +#define IFSGEN 0x400 /* Internal Frame Sync Generation */ +#define POLC 0x1800 /* Frame Sync and Data Driving/Sampling Edges */ +#define POLS 0x6000 /* Frame Sync Polarity */ +#define DLENGTH 0x38000 /* Data Length */ +#define SKIP_EN 0x40000 /* Skip Enable */ +#define SKIP_EO 0x80000 /* Skip Even or Odd */ +#define PACKEN 0x100000 /* Packing/Unpacking Enable */ +#define SWAPEN 0x200000 /* Swap Enable */ +#define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format */ +#define SPLT_EVEN_ODD 0x800000 /* Split Even and Odd Data Samples */ +#define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */ +#define DMACFG 0x2000000 /* One or Two DMA Channels Mode */ +#define RGB_FMT_EN 0x4000000 /* RGB Formatting Enable */ +#define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */ +#define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */ + +#define DLEN_8 (0 << 15) /* 000 - 8 bits */ +#define DLEN_10 (1 << 15) /* 001 - 10 bits */ +#define DLEN_12 (2 << 15) /* 010 - 12 bits */ +#define DLEN_14 (3 << 15) /* 011 - 14 bits */ +#define DLEN_16 (4 << 15) /* 100 - 16 bits */ +#define DLEN_18 (5 << 15) /* 101 - 18 bits */ +#define DLEN_24 (6 << 15) /* 110 - 24 bits */ + + +/* Bit masks for EPPIx_FS2W_LVB */ + +#define F1VB_BD 0xff /* Vertical Blanking before Field 1 Active Data */ +#define F1VB_AD 0xff00 /* Vertical Blanking after Field 1 Active Data */ +#define F2VB_BD 0xff0000 /* Vertical Blanking before Field 2 Active Data */ +#define F2VB_AD 0xff000000 /* Vertical Blanking after Field 2 Active Data */ + +/* Bit masks for EPPIx_FS2W_LAVF */ + +#define F1_ACT 0xffff /* Number of Lines of Active Data in Field 1 */ +#define F2_ACT 0xffff0000 /* Number of Lines of Active Data in Field 2 */ + +/* Bit masks for EPPIx_CLIP */ + +#define LOW_ODD 0xff /* Lower Limit for Odd Bytes (Chroma) */ +#define HIGH_ODD 0xff00 /* Upper Limit for Odd Bytes (Chroma) */ +#define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */ +#define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */ + +/* Bit masks for SPIx_BAUD */ + +#define SPI_BAUD 0xffff /* Baud Rate */ + +/* Bit masks for SPIx_CTL */ + +#define SPE 0x4000 /* SPI Enable */ +#define WOM 0x2000 /* Write Open Drain Master */ +#define MSTR 0x1000 /* Master Mode */ +#define CPOL 0x800 /* Clock Polarity */ +#define CPHA 0x400 /* Clock Phase */ +#define LSBF 0x200 /* LSB First */ +#define SIZE 0x100 /* Size of Words */ +#define EMISO 0x20 /* Enable MISO Output */ +#define PSSE 0x10 /* Slave-Select Enable */ +#define GM 0x8 /* Get More Data */ +#define SZ 0x4 /* Send Zero */ +#define TIMOD 0x3 /* Transfer Initiation Mode */ + +/* Bit masks for SPIx_FLG */ + +#define FLS1 0x2 /* Slave Select Enable 1 */ +#define FLS2 0x4 /* Slave Select Enable 2 */ +#define FLS3 0x8 /* Slave Select Enable 3 */ +#define FLG1 0x200 /* Slave Select Value 1 */ +#define FLG2 0x400 /* Slave Select Value 2 */ +#define FLG3 0x800 /* Slave Select Value 3 */ + +/* Bit masks for SPIx_STAT */ + +#define TXCOL 0x40 /* Transmit Collision Error */ +#define RXS 0x20 /* RDBR Data Buffer Status */ +#define RBSY 0x10 /* Receive Error */ +#define TXS 0x8 /* TDBR Data Buffer Status */ +#define TXE 0x4 /* Transmission Error */ +#define MODF 0x2 /* Mode Fault Error */ +#define SPIF 0x1 /* SPI Finished */ + +/* Bit masks for SPIx_TDBR */ + +#define TDBR 0xffff /* Transmit Data Buffer */ + +/* Bit masks for SPIx_RDBR */ + +#define RDBR 0xffff /* Receive Data Buffer */ + +/* Bit masks for SPIx_SHADOW */ + +#define SHADOW 0xffff /* RDBR Shadow */ + +/* ************************************************ */ +/* The TWI bit masks fields are from the ADSP-BF538 */ +/* and they have not been verified as the final */ +/* ones for the Moab processors ... bz 1/19/2007 */ +/* ************************************************ */ + +/* Bit masks for TWIx_CONTROL */ + +#define PRESCALE 0x7f /* Prescale Value */ +#define TWI_ENA 0x80 /* TWI Enable */ +#define SCCB 0x200 /* Serial Camera Control Bus */ + +/* Bit maskes for TWIx_CLKDIV */ + +#define CLKLOW 0xff /* Clock Low */ +#define CLKHI 0xff00 /* Clock High */ + +/* Bit maskes for TWIx_SLAVE_CTL */ + +#define SEN 0x1 /* Slave Enable */ +#define STDVAL 0x4 /* Slave Transmit Data Valid */ +#define NAK 0x8 /* Not Acknowledge */ +#define GEN 0x10 /* General Call Enable */ + +/* Bit maskes for TWIx_SLAVE_ADDR */ + +#define SADDR 0x7f /* Slave Mode Address */ + +/* Bit maskes for TWIx_SLAVE_STAT */ + +#define SDIR 0x1 /* Slave Transfer Direction */ +#define GCALL 0x2 /* General Call */ + +/* Bit maskes for TWIx_MASTER_CTL */ + +#define MEN 0x1 /* Master Mode Enable */ +#define MDIR 0x4 /* Master Transfer Direction */ +#define FAST 0x8 /* Fast Mode */ +#define STOP 0x10 /* Issue Stop Condition */ +#define RSTART 0x20 /* Repeat Start */ +#define DCNT 0x3fc0 /* Data Transfer Count */ +#define SDAOVR 0x4000 /* Serial Data Override */ +#define SCLOVR 0x8000 /* Serial Clock Override */ + +/* Bit maskes for TWIx_MASTER_ADDR */ + +#define MADDR 0x7f /* Master Mode Address */ + +/* Bit maskes for TWIx_MASTER_STAT */ + +#define MPROG 0x1 /* Master Transfer in Progress */ +#define LOSTARB 0x2 /* Lost Arbitration */ +#define ANAK 0x4 /* Address Not Acknowledged */ +#define DNAK 0x8 /* Data Not Acknowledged */ +#define BUFRDERR 0x10 /* Buffer Read Error */ +#define BUFWRERR 0x20 /* Buffer Write Error */ +#define SDASEN 0x40 /* Serial Data Sense */ +#define SCLSEN 0x80 /* Serial Clock Sense */ +#define BUSBUSY 0x100 /* Bus Busy */ + +/* Bit maskes for TWIx_FIFO_CTL */ + +#define XMTFLUSH 0x1 /* Transmit Buffer Flush */ +#define RCVFLUSH 0x2 /* Receive Buffer Flush */ +#define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */ +#define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */ + +/* Bit maskes for TWIx_FIFO_STAT */ + +#define XMTSTAT 0x3 /* Transmit FIFO Status */ +#define RCVSTAT 0xc /* Receive FIFO Status */ + +/* Bit maskes for TWIx_INT_MASK */ + +#define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */ +#define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */ +#define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */ +#define SOVFM 0x8 /* Slave Overflow Interrupt Mask */ +#define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */ +#define MERRM 0x20 /* Master Transfer Error Interrupt Mask */ +#define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */ +#define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */ + +/* Bit maskes for TWIx_INT_STAT */ + +#define SINIT 0x1 /* Slave Transfer Initiated */ +#define SCOMP 0x2 /* Slave Transfer Complete */ +#define SERR 0x4 /* Slave Transfer Error */ +#define SOVF 0x8 /* Slave Overflow */ +#define MCOMP 0x10 /* Master Transfer Complete */ +#define MERR 0x20 /* Master Transfer Error */ +#define XMTSERV 0x40 /* Transmit FIFO Service */ +#define RCVSERV 0x80 /* Receive FIFO Service */ + +/* Bit maskes for TWIx_XMT_DATA8 */ + +#define XMTDATA8 0xff /* Transmit FIFO 8-Bit Data */ + +/* Bit maskes for TWIx_XMT_DATA16 */ + +#define XMTDATA16 0xffff /* Transmit FIFO 16-Bit Data */ + +/* Bit maskes for TWIx_RCV_DATA8 */ + +#define RCVDATA8 0xff /* Receive FIFO 8-Bit Data */ + +/* Bit maskes for TWIx_RCV_DATA16 */ + +#define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */ + +/* Bit masks for SPORTx_TCR1 */ + +#define TCKFE 0x4000 /* Clock Falling Edge Select */ +#define LATFS 0x2000 /* Late Transmit Frame Sync */ +#define LTFS 0x1000 /* Low Transmit Frame Sync Select */ +#define DITFS 0x800 /* Data-Independent Transmit Frame Sync Select */ +#define TFSR 0x400 /* Transmit Frame Sync Required Select */ +#define ITFS 0x200 /* Internal Transmit Frame Sync Select */ +#define TLSBIT 0x10 /* Transmit Bit Order */ +#define TDTYPE 0xc /* Data Formatting Type Select */ +#define ITCLK 0x2 /* Internal Transmit Clock Select */ +#define TSPEN 0x1 /* Transmit Enable */ + +/* Bit masks for SPORTx_TCR2 */ + +#define TRFST 0x400 /* Left/Right Order */ +#define TSFSE 0x200 /* Transmit Stereo Frame Sync Enable */ +#define TXSE 0x100 /* TxSEC Enable */ +#define SLEN_T 0x1f /* SPORT Word Length */ + +/* Bit masks for SPORTx_RCR1 */ + +#define RCKFE 0x4000 /* Clock Falling Edge Select */ +#define LARFS 0x2000 /* Late Receive Frame Sync */ +#define LRFS 0x1000 /* Low Receive Frame Sync Select */ +#define RFSR 0x400 /* Receive Frame Sync Required Select */ +#define IRFS 0x200 /* Internal Receive Frame Sync Select */ +#define RLSBIT 0x10 /* Receive Bit Order */ +#define RDTYPE 0xc /* Data Formatting Type Select */ +#define IRCLK 0x2 /* Internal Receive Clock Select */ +#define RSPEN 0x1 /* Receive Enable */ + +/* Bit masks for SPORTx_RCR2 */ + +#define RRFST 0x400 /* Left/Right Order */ +#define RSFSE 0x200 /* Receive Stereo Frame Sync Enable */ +#define RXSE 0x100 /* RxSEC Enable */ +#define SLEN_R 0x1f /* SPORT Word Length */ + +/* Bit masks for SPORTx_STAT */ + +#define TXHRE 0x40 /* Transmit Hold Register Empty */ +#define TOVF 0x20 /* Sticky Transmit Overflow Status */ +#define TUVF 0x10 /* Sticky Transmit Underflow Status */ +#define TXF 0x8 /* Transmit FIFO Full Status */ +#define ROVF 0x4 /* Sticky Receive Overflow Status */ +#define RUVF 0x2 /* Sticky Receive Underflow Status */ +#define RXNE 0x1 /* Receive FIFO Not Empty Status */ + +/* Bit masks for SPORTx_MCMC1 */ + +#define SP_WSIZE 0xf000 /* Window Size */ +#define SP_WOFF 0x3ff /* Windows Offset */ + +/* Bit masks for SPORTx_MCMC2 */ + +#define MFD 0xf000 /* Multi channel Frame Delay */ +#define FSDR 0x80 /* Frame Sync to Data Relationship */ +#define MCMEN 0x10 /* Multi channel Frame Mode Enable */ +#define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */ +#define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */ +#define MCCRM 0x3 /* 2X Clock Recovery Mode */ + +/* Bit masks for SPORTx_CHNL */ + +#define CUR_CHNL 0x3ff /* Current Channel Indicator */ + +/* Bit masks for UARTx_LCR */ + +#if 0 +/* conflicts with legacy one in last section */ +#define WLS 0x3 /* Word Length Select */ +#endif +#define STB 0x4 /* Stop Bits */ +#define PEN 0x8 /* Parity Enable */ +#define EPS 0x10 /* Even Parity Select */ +#define STP 0x20 /* Sticky Parity */ +#define SB 0x40 /* Set Break */ + +/* Bit masks for UARTx_MCR */ + +#define XOFF 0x1 /* Transmitter Off */ +#define MRTS 0x2 /* Manual Request To Send */ +#define RFIT 0x4 /* Receive FIFO IRQ Threshold */ +#define RFRT 0x8 /* Receive FIFO RTS Threshold */ +#define LOOP_ENA 0x10 /* Loopback Mode Enable */ +#define FCPOL 0x20 /* Flow Control Pin Polarity */ +#define ARTS 0x40 /* Automatic Request To Send */ +#define ACTS 0x80 /* Automatic Clear To Send */ + +/* Bit masks for UARTx_LSR */ + +#define DR 0x1 /* Data Ready */ +#define OE 0x2 /* Overrun Error */ +#define PE 0x4 /* Parity Error */ +#define FE 0x8 /* Framing Error */ +#define BI 0x10 /* Break Interrupt */ +#define THRE 0x20 /* THR Empty */ +#define TEMT 0x40 /* Transmitter Empty */ +#define TFI 0x80 /* Transmission Finished Indicator */ + +/* Bit masks for UARTx_MSR */ + +#define SCTS 0x1 /* Sticky CTS */ +#define CTS 0x10 /* Clear To Send */ +#define RFCS 0x20 /* Receive FIFO Count Status */ + +/* Bit masks for UARTx_IER_SET & UARTx_IER_CLEAR */ + +#define ERBFI 0x1 /* Enable Receive Buffer Full Interrupt */ +#define ETBEI 0x2 /* Enable Transmit Buffer Empty Interrupt */ +#define ELSI 0x4 /* Enable Receive Status Interrupt */ +#define EDSSI 0x8 /* Enable Modem Status Interrupt */ +#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */ +#define ETFI 0x20 /* Enable Transmission Finished Interrupt */ +#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */ + +/* Bit masks for UARTx_GCTL */ + +#define UCEN 0x1 /* UART Enable */ +#define IREN 0x2 /* IrDA Mode Enable */ +#define TPOLC 0x4 /* IrDA TX Polarity Change */ +#define RPOLC 0x8 /* IrDA RX Polarity Change */ +#define FPE 0x10 /* Force Parity Error */ +#define FFE 0x20 /* Force Framing Error */ +#define EDBO 0x40 /* Enable Divide-by-One */ +#define EGLSI 0x80 /* Enable Global LS Interrupt */ + + +/* ******************************************* */ +/* MULTI BIT MACRO ENUMERATIONS */ +/* ******************************************* */ + +/* BCODE bit field options (SYSCFG register) */ + +#define BCODE_WAKEUP 0x0000 /* boot according to wake-up condition */ +#define BCODE_FULLBOOT 0x0010 /* always perform full boot */ +#define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */ +#define BCODE_NOBOOT 0x0030 /* always perform full boot */ + +/* CNT_COMMAND bit field options */ + +#define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */ +#define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */ +#define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */ + +#define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */ +#define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */ +#define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */ + +#define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */ +#define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */ +#define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */ + +/* CNT_CONFIG bit field options */ + +#define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */ +#define CNTMODE_BINENC 0x0100 /* binary encoder mode */ +#define CNTMODE_UDCNT 0x0200 /* up/down counter mode */ +#define CNTMODE_DIRCNT 0x0400 /* direction counter mode */ +#define CNTMODE_DIRTMR 0x0500 /* direction timer mode */ + +#define BNDMODE_COMP 0x0000 /* boundary compare mode */ +#define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */ +#define BNDMODE_CAPT 0x2000 /* boundary capture mode */ +#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */ + +/* TMODE in TIMERx_CONFIG bit field options */ + +#define PWM_OUT 0x0001 +#define WDTH_CAP 0x0002 +#define EXT_CLK 0x0003 + +/* UARTx_LCR bit field options */ + +#define WLS_5 0x0000 /* 5 data bits */ +#define WLS_6 0x0001 /* 6 data bits */ +#define WLS_7 0x0002 /* 7 data bits */ +#define WLS_8 0x0003 /* 8 data bits */ + +/* PINTx Register Bit Definitions */ + +#define PIQ0 0x00000001 +#define PIQ1 0x00000002 +#define PIQ2 0x00000004 +#define PIQ3 0x00000008 + +#define PIQ4 0x00000010 +#define PIQ5 0x00000020 +#define PIQ6 0x00000040 +#define PIQ7 0x00000080 + +#define PIQ8 0x00000100 +#define PIQ9 0x00000200 +#define PIQ10 0x00000400 +#define PIQ11 0x00000800 + +#define PIQ12 0x00001000 +#define PIQ13 0x00002000 +#define PIQ14 0x00004000 +#define PIQ15 0x00008000 + +#define PIQ16 0x00010000 +#define PIQ17 0x00020000 +#define PIQ18 0x00040000 +#define PIQ19 0x00080000 + +#define PIQ20 0x00100000 +#define PIQ21 0x00200000 +#define PIQ22 0x00400000 +#define PIQ23 0x00800000 + +#define PIQ24 0x01000000 +#define PIQ25 0x02000000 +#define PIQ26 0x04000000 +#define PIQ27 0x08000000 + +#define PIQ28 0x10000000 +#define PIQ29 0x20000000 +#define PIQ30 0x40000000 +#define PIQ31 0x80000000 + +/* PORT A Bit Definitions for the registers +PORTA, PORTA_SET, PORTA_CLEAR, +PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN, +PORTA_FER registers +*/ + +#define PA0 0x0001 +#define PA1 0x0002 +#define PA2 0x0004 +#define PA3 0x0008 +#define PA4 0x0010 +#define PA5 0x0020 +#define PA6 0x0040 +#define PA7 0x0080 +#define PA8 0x0100 +#define PA9 0x0200 +#define PA10 0x0400 +#define PA11 0x0800 +#define PA12 0x1000 +#define PA13 0x2000 +#define PA14 0x4000 +#define PA15 0x8000 + +/* PORT B Bit Definitions for the registers +PORTB, PORTB_SET, PORTB_CLEAR, +PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN, +PORTB_FER registers +*/ + +#define PB0 0x0001 +#define PB1 0x0002 +#define PB2 0x0004 +#define PB3 0x0008 +#define PB4 0x0010 +#define PB5 0x0020 +#define PB6 0x0040 +#define PB7 0x0080 +#define PB8 0x0100 +#define PB9 0x0200 +#define PB10 0x0400 +#define PB11 0x0800 +#define PB12 0x1000 +#define PB13 0x2000 +#define PB14 0x4000 + + +/* PORT C Bit Definitions for the registers +PORTC, PORTC_SET, PORTC_CLEAR, +PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN, +PORTC_FER registers +*/ + + +#define PC0 0x0001 +#define PC1 0x0002 +#define PC2 0x0004 +#define PC3 0x0008 +#define PC4 0x0010 +#define PC5 0x0020 +#define PC6 0x0040 +#define PC7 0x0080 +#define PC8 0x0100 +#define PC9 0x0200 +#define PC10 0x0400 +#define PC11 0x0800 +#define PC12 0x1000 +#define PC13 0x2000 + + +/* PORT D Bit Definitions for the registers +PORTD, PORTD_SET, PORTD_CLEAR, +PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN, +PORTD_FER registers +*/ + +#define PD0 0x0001 +#define PD1 0x0002 +#define PD2 0x0004 +#define PD3 0x0008 +#define PD4 0x0010 +#define PD5 0x0020 +#define PD6 0x0040 +#define PD7 0x0080 +#define PD8 0x0100 +#define PD9 0x0200 +#define PD10 0x0400 +#define PD11 0x0800 +#define PD12 0x1000 +#define PD13 0x2000 +#define PD14 0x4000 +#define PD15 0x8000 + +/* PORT E Bit Definitions for the registers +PORTE, PORTE_SET, PORTE_CLEAR, +PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN, +PORTE_FER registers +*/ + + +#define PE0 0x0001 +#define PE1 0x0002 +#define PE2 0x0004 +#define PE3 0x0008 +#define PE4 0x0010 +#define PE5 0x0020 +#define PE6 0x0040 +#define PE7 0x0080 +#define PE8 0x0100 +#define PE9 0x0200 +#define PE10 0x0400 +#define PE11 0x0800 +#define PE12 0x1000 +#define PE13 0x2000 +#define PE14 0x4000 +#define PE15 0x8000 + +/* PORT F Bit Definitions for the registers +PORTF, PORTF_SET, PORTF_CLEAR, +PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN, +PORTF_FER registers +*/ + + +#define PF0 0x0001 +#define PF1 0x0002 +#define PF2 0x0004 +#define PF3 0x0008 +#define PF4 0x0010 +#define PF5 0x0020 +#define PF6 0x0040 +#define PF7 0x0080 +#define PF8 0x0100 +#define PF9 0x0200 +#define PF10 0x0400 +#define PF11 0x0800 +#define PF12 0x1000 +#define PF13 0x2000 +#define PF14 0x4000 +#define PF15 0x8000 + +/* PORT G Bit Definitions for the registers +PORTG, PORTG_SET, PORTG_CLEAR, +PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN, +PORTG_FER registers +*/ + + +#define PG0 0x0001 +#define PG1 0x0002 +#define PG2 0x0004 +#define PG3 0x0008 +#define PG4 0x0010 +#define PG5 0x0020 +#define PG6 0x0040 +#define PG7 0x0080 +#define PG8 0x0100 +#define PG9 0x0200 +#define PG10 0x0400 +#define PG11 0x0800 +#define PG12 0x1000 +#define PG13 0x2000 +#define PG14 0x4000 +#define PG15 0x8000 + +/* PORT H Bit Definitions for the registers +PORTH, PORTH_SET, PORTH_CLEAR, +PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN, +PORTH_FER registers +*/ + + +#define PH0 0x0001 +#define PH1 0x0002 +#define PH2 0x0004 +#define PH3 0x0008 +#define PH4 0x0010 +#define PH5 0x0020 +#define PH6 0x0040 +#define PH7 0x0080 +#define PH8 0x0100 +#define PH9 0x0200 +#define PH10 0x0400 +#define PH11 0x0800 +#define PH12 0x1000 +#define PH13 0x2000 + + +/* PORT I Bit Definitions for the registers +PORTI, PORTI_SET, PORTI_CLEAR, +PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN, +PORTI_FER registers +*/ + + +#define PI0 0x0001 +#define PI1 0x0002 +#define PI2 0x0004 +#define PI3 0x0008 +#define PI4 0x0010 +#define PI5 0x0020 +#define PI6 0x0040 +#define PI7 0x0080 +#define PI8 0x0100 +#define PI9 0x0200 +#define PI10 0x0400 +#define PI11 0x0800 +#define PI12 0x1000 +#define PI13 0x2000 +#define PI14 0x4000 +#define PI15 0x8000 + +/* PORT J Bit Definitions for the registers +PORTJ, PORTJ_SET, PORTJ_CLEAR, +PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN, +PORTJ_FER registers +*/ + + +#define PJ0 0x0001 +#define PJ1 0x0002 +#define PJ2 0x0004 +#define PJ3 0x0008 +#define PJ4 0x0010 +#define PJ5 0x0020 +#define PJ6 0x0040 +#define PJ7 0x0080 +#define PJ8 0x0100 +#define PJ9 0x0200 +#define PJ10 0x0400 +#define PJ11 0x0800 +#define PJ12 0x1000 +#define PJ13 0x2000 + + +/* Port Muxing Bit Fields for PORTx_MUX Registers */ + +#define MUX0 0x00000003 +#define MUX0_0 0x00000000 +#define MUX0_1 0x00000001 +#define MUX0_2 0x00000002 +#define MUX0_3 0x00000003 + +#define MUX1 0x0000000C +#define MUX1_0 0x00000000 +#define MUX1_1 0x00000004 +#define MUX1_2 0x00000008 +#define MUX1_3 0x0000000C + +#define MUX2 0x00000030 +#define MUX2_0 0x00000000 +#define MUX2_1 0x00000010 +#define MUX2_2 0x00000020 +#define MUX2_3 0x00000030 + +#define MUX3 0x000000C0 +#define MUX3_0 0x00000000 +#define MUX3_1 0x00000040 +#define MUX3_2 0x00000080 +#define MUX3_3 0x000000C0 + +#define MUX4 0x00000300 +#define MUX4_0 0x00000000 +#define MUX4_1 0x00000100 +#define MUX4_2 0x00000200 +#define MUX4_3 0x00000300 + +#define MUX5 0x00000C00 +#define MUX5_0 0x00000000 +#define MUX5_1 0x00000400 +#define MUX5_2 0x00000800 +#define MUX5_3 0x00000C00 + +#define MUX6 0x00003000 +#define MUX6_0 0x00000000 +#define MUX6_1 0x00001000 +#define MUX6_2 0x00002000 +#define MUX6_3 0x00003000 + +#define MUX7 0x0000C000 +#define MUX7_0 0x00000000 +#define MUX7_1 0x00004000 +#define MUX7_2 0x00008000 +#define MUX7_3 0x0000C000 + +#define MUX8 0x00030000 +#define MUX8_0 0x00000000 +#define MUX8_1 0x00010000 +#define MUX8_2 0x00020000 +#define MUX8_3 0x00030000 + +#define MUX9 0x000C0000 +#define MUX9_0 0x00000000 +#define MUX9_1 0x00040000 +#define MUX9_2 0x00080000 +#define MUX9_3 0x000C0000 + +#define MUX10 0x00300000 +#define MUX10_0 0x00000000 +#define MUX10_1 0x00100000 +#define MUX10_2 0x00200000 +#define MUX10_3 0x00300000 + +#define MUX11 0x00C00000 +#define MUX11_0 0x00000000 +#define MUX11_1 0x00400000 +#define MUX11_2 0x00800000 +#define MUX11_3 0x00C00000 + +#define MUX12 0x03000000 +#define MUX12_0 0x00000000 +#define MUX12_1 0x01000000 +#define MUX12_2 0x02000000 +#define MUX12_3 0x03000000 + +#define MUX13 0x0C000000 +#define MUX13_0 0x00000000 +#define MUX13_1 0x04000000 +#define MUX13_2 0x08000000 +#define MUX13_3 0x0C000000 + +#define MUX14 0x30000000 +#define MUX14_0 0x00000000 +#define MUX14_1 0x10000000 +#define MUX14_2 0x20000000 +#define MUX14_3 0x30000000 + +#define MUX15 0xC0000000 +#define MUX15_0 0x00000000 +#define MUX15_1 0x40000000 +#define MUX15_2 0x80000000 +#define MUX15_3 0xC0000000 + +#define MUX(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \ + ((((b15)&3) << 30) | \ + (((b14)&3) << 28) | \ + (((b13)&3) << 26) | \ + (((b12)&3) << 24) | \ + (((b11)&3) << 22) | \ + (((b10)&3) << 20) | \ + (((b9) &3) << 18) | \ + (((b8) &3) << 16) | \ + (((b7) &3) << 14) | \ + (((b6) &3) << 12) | \ + (((b5) &3) << 10) | \ + (((b4) &3) << 8) | \ + (((b3) &3) << 6) | \ + (((b2) &3) << 4) | \ + (((b1) &3) << 2) | \ + (((b0) &3))) + +/* Bit fields for PINT0_ASSIGN and PINT1_ASSIGN registers */ + +#define B0MAP 0x000000FF /* Byte 0 Lower Half Port Mapping */ +#define B0MAP_PAL 0x00000000 /* Map Port A Low to Byte 0 */ +#define B0MAP_PBL 0x00000001 /* Map Port B Low to Byte 0 */ +#define B1MAP 0x0000FF00 /* Byte 1 Upper Half Port Mapping */ +#define B1MAP_PAH 0x00000000 /* Map Port A High to Byte 1 */ +#define B1MAP_PBH 0x00000100 /* Map Port B High to Byte 1 */ +#define B2MAP 0x00FF0000 /* Byte 2 Lower Half Port Mapping */ +#define B2MAP_PAL 0x00000000 /* Map Port A Low to Byte 2 */ +#define B2MAP_PBL 0x00010000 /* Map Port B Low to Byte 2 */ +#define B3MAP 0xFF000000 /* Byte 3 Upper Half Port Mapping */ +#define B3MAP_PAH 0x00000000 /* Map Port A High to Byte 3 */ +#define B3MAP_PBH 0x01000000 /* Map Port B High to Byte 3 */ + +/* Bit fields for PINT2_ASSIGN and PINT3_ASSIGN registers */ + +#define B0MAP_PCL 0x00000000 /* Map Port C Low to Byte 0 */ +#define B0MAP_PDL 0x00000001 /* Map Port D Low to Byte 0 */ +#define B0MAP_PEL 0x00000002 /* Map Port E Low to Byte 0 */ +#define B0MAP_PFL 0x00000003 /* Map Port F Low to Byte 0 */ +#define B0MAP_PGL 0x00000004 /* Map Port G Low to Byte 0 */ +#define B0MAP_PHL 0x00000005 /* Map Port H Low to Byte 0 */ +#define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */ +#define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */ + +#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */ +#define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */ +#define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */ +#define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */ +#define B1MAP_PGH 0x00000400 /* Map Port G High to Byte 1 */ +#define B1MAP_PHH 0x00000500 /* Map Port H High to Byte 1 */ +#define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */ +#define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */ + +#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */ +#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */ +#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */ +#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */ +#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */ +#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */ +#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */ +#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */ + +#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */ +#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */ +#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */ +#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */ +#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */ +#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */ +#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */ +#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */ + + +/* for legacy compatibility */ + +#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ +#define W1LMAX_MAX W1LMAX_MIN +#define EBIU_AMCBCTL0 EBIU_AMBCTL0 +#define EBIU_AMCBCTL1 EBIU_AMBCTL1 +#define PINT0_IRQ PINT0_REQUEST +#define PINT1_IRQ PINT1_REQUEST +#define PINT2_IRQ PINT2_REQUEST +#define PINT3_IRQ PINT3_REQUEST + +#endif /* _DEF_BF54X_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/dma.h b/arch/blackfin/mach-bf548/include/mach/dma.h new file mode 100644 index 000000000000..36a2ef7e7849 --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/dma.h @@ -0,0 +1,76 @@ +/* + * file: include/asm-blackfin/mach-bf548/dma.h + * based on: + * author: + * + * created: + * description: + * system mmr register map + * rev: + * + * modified: + * + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + +#ifndef _MACH_DMA_H_ +#define _MACH_DMA_H_ + +#define CH_SPORT0_RX 0 +#define CH_SPORT0_TX 1 +#define CH_SPORT1_RX 2 +#define CH_SPORT1_TX 3 +#define CH_SPI0 4 +#define CH_SPI1 5 +#define CH_UART0_RX 6 +#define CH_UART0_TX 7 +#define CH_UART1_RX 8 +#define CH_UART1_TX 9 +#define CH_ATAPI_RX 10 +#define CH_ATAPI_TX 11 +#define CH_EPPI0 12 +#define CH_EPPI1 13 +#define CH_EPPI2 14 +#define CH_PIXC_IMAGE 15 +#define CH_PIXC_OVERLAY 16 +#define CH_PIXC_OUTPUT 17 +#define CH_SPORT2_RX 18 +#define CH_UART2_RX 18 +#define CH_SPORT2_TX 19 +#define CH_UART2_TX 19 +#define CH_SPORT3_RX 20 +#define CH_UART3_RX 20 +#define CH_SPORT3_TX 21 +#define CH_UART3_TX 21 +#define CH_SDH 22 +#define CH_NFC 22 +#define CH_SPI2 23 + +#define CH_MEM_STREAM0_DEST 24 +#define CH_MEM_STREAM0_SRC 25 +#define CH_MEM_STREAM1_DEST 26 +#define CH_MEM_STREAM1_SRC 27 +#define CH_MEM_STREAM2_DEST 28 +#define CH_MEM_STREAM2_SRC 29 +#define CH_MEM_STREAM3_DEST 30 +#define CH_MEM_STREAM3_SRC 31 + +#define MAX_BLACKFIN_DMA_CHANNEL 32 + +#endif diff --git a/arch/blackfin/mach-bf548/include/mach/gpio.h b/arch/blackfin/mach-bf548/include/mach/gpio.h new file mode 100644 index 000000000000..bba82dc75f16 --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/gpio.h @@ -0,0 +1,219 @@ +/* + * File: include/asm-blackfin/mach-bf548/gpio.h + * Based on: + * Author: Michael Hennerich (hennerich@blackfin.uclinux.org) + * + * Created: + * Description: + * + * Modified: + * Copyright 2004-2007 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + + +#define GPIO_PA0 0 +#define GPIO_PA1 1 +#define GPIO_PA2 2 +#define GPIO_PA3 3 +#define GPIO_PA4 4 +#define GPIO_PA5 5 +#define GPIO_PA6 6 +#define GPIO_PA7 7 +#define GPIO_PA8 8 +#define GPIO_PA9 9 +#define GPIO_PA10 10 +#define GPIO_PA11 11 +#define GPIO_PA12 12 +#define GPIO_PA13 13 +#define GPIO_PA14 14 +#define GPIO_PA15 15 +#define GPIO_PB0 16 +#define GPIO_PB1 17 +#define GPIO_PB2 18 +#define GPIO_PB3 19 +#define GPIO_PB4 20 +#define GPIO_PB5 21 +#define GPIO_PB6 22 +#define GPIO_PB7 23 +#define GPIO_PB8 24 +#define GPIO_PB9 25 +#define GPIO_PB10 26 +#define GPIO_PB11 27 +#define GPIO_PB12 28 +#define GPIO_PB13 29 +#define GPIO_PB14 30 +#define GPIO_PB15 31 /* N/A */ +#define GPIO_PC0 32 +#define GPIO_PC1 33 +#define GPIO_PC2 34 +#define GPIO_PC3 35 +#define GPIO_PC4 36 +#define GPIO_PC5 37 +#define GPIO_PC6 38 +#define GPIO_PC7 39 +#define GPIO_PC8 40 +#define GPIO_PC9 41 +#define GPIO_PC10 42 +#define GPIO_PC11 43 +#define GPIO_PC12 44 +#define GPIO_PC13 45 +#define GPIO_PC14 46 /* N/A */ +#define GPIO_PC15 47 /* N/A */ +#define GPIO_PD0 48 +#define GPIO_PD1 49 +#define GPIO_PD2 50 +#define GPIO_PD3 51 +#define GPIO_PD4 52 +#define GPIO_PD5 53 +#define GPIO_PD6 54 +#define GPIO_PD7 55 +#define GPIO_PD8 56 +#define GPIO_PD9 57 +#define GPIO_PD10 58 +#define GPIO_PD11 59 +#define GPIO_PD12 60 +#define GPIO_PD13 61 +#define GPIO_PD14 62 +#define GPIO_PD15 63 +#define GPIO_PE0 64 +#define GPIO_PE1 65 +#define GPIO_PE2 66 +#define GPIO_PE3 67 +#define GPIO_PE4 68 +#define GPIO_PE5 69 +#define GPIO_PE6 70 +#define GPIO_PE7 71 +#define GPIO_PE8 72 +#define GPIO_PE9 73 +#define GPIO_PE10 74 +#define GPIO_PE11 75 +#define GPIO_PE12 76 +#define GPIO_PE13 77 +#define GPIO_PE14 78 +#define GPIO_PE15 79 +#define GPIO_PF0 80 +#define GPIO_PF1 81 +#define GPIO_PF2 82 +#define GPIO_PF3 83 +#define GPIO_PF4 84 +#define GPIO_PF5 85 +#define GPIO_PF6 86 +#define GPIO_PF7 87 +#define GPIO_PF8 88 +#define GPIO_PF9 89 +#define GPIO_PF10 90 +#define GPIO_PF11 91 +#define GPIO_PF12 92 +#define GPIO_PF13 93 +#define GPIO_PF14 94 +#define GPIO_PF15 95 +#define GPIO_PG0 96 +#define GPIO_PG1 97 +#define GPIO_PG2 98 +#define GPIO_PG3 99 +#define GPIO_PG4 100 +#define GPIO_PG5 101 +#define GPIO_PG6 102 +#define GPIO_PG7 103 +#define GPIO_PG8 104 +#define GPIO_PG9 105 +#define GPIO_PG10 106 +#define GPIO_PG11 107 +#define GPIO_PG12 108 +#define GPIO_PG13 109 +#define GPIO_PG14 110 +#define GPIO_PG15 111 +#define GPIO_PH0 112 +#define GPIO_PH1 113 +#define GPIO_PH2 114 +#define GPIO_PH3 115 +#define GPIO_PH4 116 +#define GPIO_PH5 117 +#define GPIO_PH6 118 +#define GPIO_PH7 119 +#define GPIO_PH8 120 +#define GPIO_PH9 121 +#define GPIO_PH10 122 +#define GPIO_PH11 123 +#define GPIO_PH12 124 +#define GPIO_PH13 125 +#define GPIO_PH14 126 /* N/A */ +#define GPIO_PH15 127 /* N/A */ +#define GPIO_PI0 128 +#define GPIO_PI1 129 +#define GPIO_PI2 130 +#define GPIO_PI3 131 +#define GPIO_PI4 132 +#define GPIO_PI5 133 +#define GPIO_PI6 134 +#define GPIO_PI7 135 +#define GPIO_PI8 136 +#define GPIO_PI9 137 +#define GPIO_PI10 138 +#define GPIO_PI11 139 +#define GPIO_PI12 140 +#define GPIO_PI13 141 +#define GPIO_PI14 142 +#define GPIO_PI15 143 +#define GPIO_PJ0 144 +#define GPIO_PJ1 145 +#define GPIO_PJ2 146 +#define GPIO_PJ3 147 +#define GPIO_PJ4 148 +#define GPIO_PJ5 149 +#define GPIO_PJ6 150 +#define GPIO_PJ7 151 +#define GPIO_PJ8 152 +#define GPIO_PJ9 153 +#define GPIO_PJ10 154 +#define GPIO_PJ11 155 +#define GPIO_PJ12 156 +#define GPIO_PJ13 157 +#define GPIO_PJ14 158 /* N/A */ +#define GPIO_PJ15 159 /* N/A */ + +#define MAX_BLACKFIN_GPIOS 160 + +struct gpio_port_t { + unsigned short port_fer; + unsigned short dummy1; + unsigned short port_data; + unsigned short dummy2; + unsigned short port_set; + unsigned short dummy3; + unsigned short port_clear; + unsigned short dummy4; + unsigned short port_dir_set; + unsigned short dummy5; + unsigned short port_dir_clear; + unsigned short dummy6; + unsigned short port_inen; + unsigned short dummy7; + unsigned int port_mux; +}; + +struct gpio_port_s { + unsigned short fer; + unsigned short data; + unsigned short dir; + unsigned short inen; + unsigned int mux; +}; diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h new file mode 100644 index 000000000000..ad380d1f5872 --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/irq.h @@ -0,0 +1,501 @@ +/* + * file: include/asm-blackfin/mach-bf548/irq.h + * based on: include/asm-blackfin/mach-bf537/irq.h + * author: Roy Huang (roy.huang@analog.com) + * + * created: + * description: + * system mmr register map + * rev: + * + * modified: + * + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + +#ifndef _BF548_IRQ_H_ +#define _BF548_IRQ_H_ + +/* + * Interrupt source definitions + Event Source Core Event Name +Core Emulation ** +Events (highest priority) EMU 0 + Reset RST 1 + NMI NMI 2 + Exception EVX 3 + Reserved -- 4 + Hardware Error IVHW 5 + Core Timer IVTMR 6 * + +..... + + Software Interrupt 1 IVG14 31 + Software Interrupt 2 -- + (lowest priority) IVG15 32 * + */ + +#define NR_PERI_INTS (32 * 3) + +/* The ABSTRACT IRQ definitions */ +/** the first seven of the following are fixed, the rest you change if you need to **/ +#define IRQ_EMU 0 /* Emulation */ +#define IRQ_RST 1 /* reset */ +#define IRQ_NMI 2 /* Non Maskable */ +#define IRQ_EVX 3 /* Exception */ +#define IRQ_UNUSED 4 /* - unused interrupt*/ +#define IRQ_HWERR 5 /* Hardware Error */ +#define IRQ_CORETMR 6 /* Core timer */ + +#define BFIN_IRQ(x) ((x) + 7) + +#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ +#define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */ +#define IRQ_EPPI0_ERROR BFIN_IRQ(2) /* EPPI0 Error Interrupt */ +#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */ +#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */ +#define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */ +#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */ +#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */ +#define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */ +#define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */ +#define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */ +#define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */ +#define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */ +#define IRQ_SPI0 BFIN_IRQ(13) /* SPI0 Interrupt (DMA4) */ +#define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */ +#define IRQ_UART0_TX BFIN_IRQ(15) /* UART0 TX Interrupt (DMA7) */ +#define IRQ_TIMER8 BFIN_IRQ(16) /* TIMER 8 Interrupt */ +#define IRQ_TIMER9 BFIN_IRQ(17) /* TIMER 9 Interrupt */ +#define IRQ_TIMER10 BFIN_IRQ(18) /* TIMER 10 Interrupt */ +#define IRQ_PINT0 BFIN_IRQ(19) /* PINT0 Interrupt */ +#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */ +#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */ +#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */ +#define IRQ_WATCH BFIN_IRQ(23) /* Watchdog Interrupt */ +#define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ +#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ +#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ +#define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */ +#define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */ +#define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */ +#define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */ +#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */ +#define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */ +#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */ +#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */ +#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ +#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */ +#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ +#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */ +#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ +#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */ +#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ +#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ +#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ +#define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */ +#define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */ +#define IRQ_UART1_TX BFIN_IRQ(42) /* UART1 TX (DMA9) Interrupt */ +#define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */ +#define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */ +#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */ +#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */ +#define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */ +#define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */ +#define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */ +#define IRQ_MDMAS3 BFIN_IRQ(50) /* MDMA Stream 3 Interrupt */ +#define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */ +#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */ +#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */ +#define IRQ_EPP1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */ +#define IRQ_EPP2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */ +#define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */ +#define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */ +#define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */ +#define IRQ_NFC_ERROR BFIN_IRQ(60) /* NFC Error Interrupt */ +#define IRQ_ATAPI_ERROR BFIN_IRQ(61) /* ATAPI Error Interrupt */ +#define IRQ_CAN1_ERROR BFIN_IRQ(62) /* CAN1 Status (Error) Interrupt */ +#define IRQ_HS_DMA_ERROR BFIN_IRQ(63) /* Handshake DMA Status Interrupt */ +#define IRQ_PIXC_IN0 BFIN_IRQ(64) /* PIXC IN0 (DMA15) Interrupt */ +#define IRQ_PIXC_IN1 BFIN_IRQ(65) /* PIXC IN1 (DMA16) Interrupt */ +#define IRQ_PIXC_OUT BFIN_IRQ(66) /* PIXC OUT (DMA17) Interrupt */ +#define IRQ_SDH BFIN_IRQ(67) /* SDH/NFC (DMA22) Interrupt */ +#define IRQ_CNT BFIN_IRQ(68) /* CNT Interrupt */ +#define IRQ_KEY BFIN_IRQ(69) /* KEY Interrupt */ +#define IRQ_CAN1_RX BFIN_IRQ(70) /* CAN1 RX Interrupt */ +#define IRQ_CAN1_TX BFIN_IRQ(71) /* CAN1 TX Interrupt */ +#define IRQ_SDH_MASK0 BFIN_IRQ(72) /* SDH Mask 0 Interrupt */ +#define IRQ_SDH_MASK1 BFIN_IRQ(73) /* SDH Mask 1 Interrupt */ +#define IRQ_USB_INT0 BFIN_IRQ(75) /* USB INT0 Interrupt */ +#define IRQ_USB_INT1 BFIN_IRQ(76) /* USB INT1 Interrupt */ +#define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */ +#define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */ +#define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */ +#define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */ +#define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */ +#define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */ +#define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */ +#define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */ +#define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */ +#define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */ +#define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */ +#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ +#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ + +#define SYS_IRQS IRQ_PINT3 + +#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1) +#define IRQ_PA0 BFIN_PA_IRQ(0) +#define IRQ_PA1 BFIN_PA_IRQ(1) +#define IRQ_PA2 BFIN_PA_IRQ(2) +#define IRQ_PA3 BFIN_PA_IRQ(3) +#define IRQ_PA4 BFIN_PA_IRQ(4) +#define IRQ_PA5 BFIN_PA_IRQ(5) +#define IRQ_PA6 BFIN_PA_IRQ(6) +#define IRQ_PA7 BFIN_PA_IRQ(7) +#define IRQ_PA8 BFIN_PA_IRQ(8) +#define IRQ_PA9 BFIN_PA_IRQ(9) +#define IRQ_PA10 BFIN_PA_IRQ(10) +#define IRQ_PA11 BFIN_PA_IRQ(11) +#define IRQ_PA12 BFIN_PA_IRQ(12) +#define IRQ_PA13 BFIN_PA_IRQ(13) +#define IRQ_PA14 BFIN_PA_IRQ(14) +#define IRQ_PA15 BFIN_PA_IRQ(15) + +#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1) +#define IRQ_PB0 BFIN_PB_IRQ(0) +#define IRQ_PB1 BFIN_PB_IRQ(1) +#define IRQ_PB2 BFIN_PB_IRQ(2) +#define IRQ_PB3 BFIN_PB_IRQ(3) +#define IRQ_PB4 BFIN_PB_IRQ(4) +#define IRQ_PB5 BFIN_PB_IRQ(5) +#define IRQ_PB6 BFIN_PB_IRQ(6) +#define IRQ_PB7 BFIN_PB_IRQ(7) +#define IRQ_PB8 BFIN_PB_IRQ(8) +#define IRQ_PB9 BFIN_PB_IRQ(9) +#define IRQ_PB10 BFIN_PB_IRQ(10) +#define IRQ_PB11 BFIN_PB_IRQ(11) +#define IRQ_PB12 BFIN_PB_IRQ(12) +#define IRQ_PB13 BFIN_PB_IRQ(13) +#define IRQ_PB14 BFIN_PB_IRQ(14) +#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */ + +#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1) +#define IRQ_PC0 BFIN_PC_IRQ(0) +#define IRQ_PC1 BFIN_PC_IRQ(1) +#define IRQ_PC2 BFIN_PC_IRQ(2) +#define IRQ_PC3 BFIN_PC_IRQ(3) +#define IRQ_PC4 BFIN_PC_IRQ(4) +#define IRQ_PC5 BFIN_PC_IRQ(5) +#define IRQ_PC6 BFIN_PC_IRQ(6) +#define IRQ_PC7 BFIN_PC_IRQ(7) +#define IRQ_PC8 BFIN_PC_IRQ(8) +#define IRQ_PC9 BFIN_PC_IRQ(9) +#define IRQ_PC10 BFIN_PC_IRQ(10) +#define IRQ_PC11 BFIN_PC_IRQ(11) +#define IRQ_PC12 BFIN_PC_IRQ(12) +#define IRQ_PC13 BFIN_PC_IRQ(13) +#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */ +#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */ + +#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1) +#define IRQ_PD0 BFIN_PD_IRQ(0) +#define IRQ_PD1 BFIN_PD_IRQ(1) +#define IRQ_PD2 BFIN_PD_IRQ(2) +#define IRQ_PD3 BFIN_PD_IRQ(3) +#define IRQ_PD4 BFIN_PD_IRQ(4) +#define IRQ_PD5 BFIN_PD_IRQ(5) +#define IRQ_PD6 BFIN_PD_IRQ(6) +#define IRQ_PD7 BFIN_PD_IRQ(7) +#define IRQ_PD8 BFIN_PD_IRQ(8) +#define IRQ_PD9 BFIN_PD_IRQ(9) +#define IRQ_PD10 BFIN_PD_IRQ(10) +#define IRQ_PD11 BFIN_PD_IRQ(11) +#define IRQ_PD12 BFIN_PD_IRQ(12) +#define IRQ_PD13 BFIN_PD_IRQ(13) +#define IRQ_PD14 BFIN_PD_IRQ(14) +#define IRQ_PD15 BFIN_PD_IRQ(15) + +#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1) +#define IRQ_PE0 BFIN_PE_IRQ(0) +#define IRQ_PE1 BFIN_PE_IRQ(1) +#define IRQ_PE2 BFIN_PE_IRQ(2) +#define IRQ_PE3 BFIN_PE_IRQ(3) +#define IRQ_PE4 BFIN_PE_IRQ(4) +#define IRQ_PE5 BFIN_PE_IRQ(5) +#define IRQ_PE6 BFIN_PE_IRQ(6) +#define IRQ_PE7 BFIN_PE_IRQ(7) +#define IRQ_PE8 BFIN_PE_IRQ(8) +#define IRQ_PE9 BFIN_PE_IRQ(9) +#define IRQ_PE10 BFIN_PE_IRQ(10) +#define IRQ_PE11 BFIN_PE_IRQ(11) +#define IRQ_PE12 BFIN_PE_IRQ(12) +#define IRQ_PE13 BFIN_PE_IRQ(13) +#define IRQ_PE14 BFIN_PE_IRQ(14) +#define IRQ_PE15 BFIN_PE_IRQ(15) + +#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1) +#define IRQ_PF0 BFIN_PF_IRQ(0) +#define IRQ_PF1 BFIN_PF_IRQ(1) +#define IRQ_PF2 BFIN_PF_IRQ(2) +#define IRQ_PF3 BFIN_PF_IRQ(3) +#define IRQ_PF4 BFIN_PF_IRQ(4) +#define IRQ_PF5 BFIN_PF_IRQ(5) +#define IRQ_PF6 BFIN_PF_IRQ(6) +#define IRQ_PF7 BFIN_PF_IRQ(7) +#define IRQ_PF8 BFIN_PF_IRQ(8) +#define IRQ_PF9 BFIN_PF_IRQ(9) +#define IRQ_PF10 BFIN_PF_IRQ(10) +#define IRQ_PF11 BFIN_PF_IRQ(11) +#define IRQ_PF12 BFIN_PF_IRQ(12) +#define IRQ_PF13 BFIN_PF_IRQ(13) +#define IRQ_PF14 BFIN_PF_IRQ(14) +#define IRQ_PF15 BFIN_PF_IRQ(15) + +#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1) +#define IRQ_PG0 BFIN_PG_IRQ(0) +#define IRQ_PG1 BFIN_PG_IRQ(1) +#define IRQ_PG2 BFIN_PG_IRQ(2) +#define IRQ_PG3 BFIN_PG_IRQ(3) +#define IRQ_PG4 BFIN_PG_IRQ(4) +#define IRQ_PG5 BFIN_PG_IRQ(5) +#define IRQ_PG6 BFIN_PG_IRQ(6) +#define IRQ_PG7 BFIN_PG_IRQ(7) +#define IRQ_PG8 BFIN_PG_IRQ(8) +#define IRQ_PG9 BFIN_PG_IRQ(9) +#define IRQ_PG10 BFIN_PG_IRQ(10) +#define IRQ_PG11 BFIN_PG_IRQ(11) +#define IRQ_PG12 BFIN_PG_IRQ(12) +#define IRQ_PG13 BFIN_PG_IRQ(13) +#define IRQ_PG14 BFIN_PG_IRQ(14) +#define IRQ_PG15 BFIN_PG_IRQ(15) + +#define BFIN_PH_IRQ(x) ((x) + IRQ_PG15 + 1) +#define IRQ_PH0 BFIN_PH_IRQ(0) +#define IRQ_PH1 BFIN_PH_IRQ(1) +#define IRQ_PH2 BFIN_PH_IRQ(2) +#define IRQ_PH3 BFIN_PH_IRQ(3) +#define IRQ_PH4 BFIN_PH_IRQ(4) +#define IRQ_PH5 BFIN_PH_IRQ(5) +#define IRQ_PH6 BFIN_PH_IRQ(6) +#define IRQ_PH7 BFIN_PH_IRQ(7) +#define IRQ_PH8 BFIN_PH_IRQ(8) +#define IRQ_PH9 BFIN_PH_IRQ(9) +#define IRQ_PH10 BFIN_PH_IRQ(10) +#define IRQ_PH11 BFIN_PH_IRQ(11) +#define IRQ_PH12 BFIN_PH_IRQ(12) +#define IRQ_PH13 BFIN_PH_IRQ(13) +#define IRQ_PH14 BFIN_PH_IRQ(14) /* N/A */ +#define IRQ_PH15 BFIN_PH_IRQ(15) /* N/A */ + +#define BFIN_PI_IRQ(x) ((x) + IRQ_PH15 + 1) +#define IRQ_PI0 BFIN_PI_IRQ(0) +#define IRQ_PI1 BFIN_PI_IRQ(1) +#define IRQ_PI2 BFIN_PI_IRQ(2) +#define IRQ_PI3 BFIN_PI_IRQ(3) +#define IRQ_PI4 BFIN_PI_IRQ(4) +#define IRQ_PI5 BFIN_PI_IRQ(5) +#define IRQ_PI6 BFIN_PI_IRQ(6) +#define IRQ_PI7 BFIN_PI_IRQ(7) +#define IRQ_PI8 BFIN_PI_IRQ(8) +#define IRQ_PI9 BFIN_PI_IRQ(9) +#define IRQ_PI10 BFIN_PI_IRQ(10) +#define IRQ_PI11 BFIN_PI_IRQ(11) +#define IRQ_PI12 BFIN_PI_IRQ(12) +#define IRQ_PI13 BFIN_PI_IRQ(13) +#define IRQ_PI14 BFIN_PI_IRQ(14) +#define IRQ_PI15 BFIN_PI_IRQ(15) + +#define BFIN_PJ_IRQ(x) ((x) + IRQ_PI15 + 1) +#define IRQ_PJ0 BFIN_PJ_IRQ(0) +#define IRQ_PJ1 BFIN_PJ_IRQ(1) +#define IRQ_PJ2 BFIN_PJ_IRQ(2) +#define IRQ_PJ3 BFIN_PJ_IRQ(3) +#define IRQ_PJ4 BFIN_PJ_IRQ(4) +#define IRQ_PJ5 BFIN_PJ_IRQ(5) +#define IRQ_PJ6 BFIN_PJ_IRQ(6) +#define IRQ_PJ7 BFIN_PJ_IRQ(7) +#define IRQ_PJ8 BFIN_PJ_IRQ(8) +#define IRQ_PJ9 BFIN_PJ_IRQ(9) +#define IRQ_PJ10 BFIN_PJ_IRQ(10) +#define IRQ_PJ11 BFIN_PJ_IRQ(11) +#define IRQ_PJ12 BFIN_PJ_IRQ(12) +#define IRQ_PJ13 BFIN_PJ_IRQ(13) +#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */ +#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */ + +#define GPIO_IRQ_BASE IRQ_PA0 + +#define NR_IRQS (IRQ_PJ15+1) + +/* For compatibility reasons with existing code */ + +#define IRQ_DMAC0_ERR IRQ_DMAC0_ERROR +#define IRQ_EPPI0_ERR IRQ_EPPI0_ERROR +#define IRQ_SPORT0_ERR IRQ_SPORT0_ERROR +#define IRQ_SPORT1_ERR IRQ_SPORT1_ERROR +#define IRQ_SPI0_ERR IRQ_SPI0_ERROR +#define IRQ_UART0_ERR IRQ_UART0_ERROR +#define IRQ_DMAC1_ERR IRQ_DMAC1_ERROR +#define IRQ_SPORT2_ERR IRQ_SPORT2_ERROR +#define IRQ_SPORT3_ERR IRQ_SPORT3_ERROR +#define IRQ_SPI1_ERR IRQ_SPI1_ERROR +#define IRQ_SPI2_ERR IRQ_SPI2_ERROR +#define IRQ_UART1_ERR IRQ_UART1_ERROR +#define IRQ_UART2_ERR IRQ_UART2_ERROR +#define IRQ_CAN0_ERR IRQ_CAN0_ERROR +#define IRQ_MXVR_ERR IRQ_MXVR_ERROR +#define IRQ_EPP1_ERR IRQ_EPP1_ERROR +#define IRQ_EPP2_ERR IRQ_EPP2_ERROR +#define IRQ_UART3_ERR IRQ_UART3_ERROR +#define IRQ_HOST_ERR IRQ_HOST_ERROR +#define IRQ_PIXC_ERR IRQ_PIXC_ERROR +#define IRQ_NFC_ERR IRQ_NFC_ERROR +#define IRQ_ATAPI_ERR IRQ_ATAPI_ERROR +#define IRQ_CAN1_ERR IRQ_CAN1_ERROR +#define IRQ_HS_DMA_ERR IRQ_HS_DMA_ERROR + + +#define IVG7 7 +#define IVG8 8 +#define IVG9 9 +#define IVG10 10 +#define IVG11 11 +#define IVG12 12 +#define IVG13 13 +#define IVG14 14 +#define IVG15 15 + +/* IAR0 BIT FIELDS */ +#define IRQ_PLL_WAKEUP_POS 0 +#define IRQ_DMAC0_ERR_POS 4 +#define IRQ_EPPI0_ERR_POS 8 +#define IRQ_SPORT0_ERR_POS 12 +#define IRQ_SPORT1_ERR_POS 16 +#define IRQ_SPI0_ERR_POS 20 +#define IRQ_UART0_ERR_POS 24 +#define IRQ_RTC_POS 28 + +/* IAR1 BIT FIELDS */ +#define IRQ_EPPI0_POS 0 +#define IRQ_SPORT0_RX_POS 4 +#define IRQ_SPORT0_TX_POS 8 +#define IRQ_SPORT1_RX_POS 12 +#define IRQ_SPORT1_TX_POS 16 +#define IRQ_SPI0_POS 20 +#define IRQ_UART0_RX_POS 24 +#define IRQ_UART0_TX_POS 28 + +/* IAR2 BIT FIELDS */ +#define IRQ_TIMER8_POS 0 +#define IRQ_TIMER9_POS 4 +#define IRQ_TIMER10_POS 8 +#define IRQ_PINT0_POS 12 +#define IRQ_PINT1_POS 16 +#define IRQ_MDMAS0_POS 20 +#define IRQ_MDMAS1_POS 24 +#define IRQ_WATCH_POS 28 + +/* IAR3 BIT FIELDS */ +#define IRQ_DMAC1_ERR_POS 0 +#define IRQ_SPORT2_ERR_POS 4 +#define IRQ_SPORT3_ERR_POS 8 +#define IRQ_MXVR_DATA_POS 12 +#define IRQ_SPI1_ERR_POS 16 +#define IRQ_SPI2_ERR_POS 20 +#define IRQ_UART1_ERR_POS 24 +#define IRQ_UART2_ERR_POS 28 + +/* IAR4 BIT FILEDS */ +#define IRQ_CAN0_ERR_POS 0 +#define IRQ_SPORT2_RX_POS 4 +#define IRQ_UART2_RX_POS 4 +#define IRQ_SPORT2_TX_POS 8 +#define IRQ_UART2_TX_POS 8 +#define IRQ_SPORT3_RX_POS 12 +#define IRQ_UART3_RX_POS 12 +#define IRQ_SPORT3_TX_POS 16 +#define IRQ_UART3_TX_POS 16 +#define IRQ_EPPI1_POS 20 +#define IRQ_EPPI2_POS 24 +#define IRQ_SPI1_POS 28 + +/* IAR5 BIT FIELDS */ +#define IRQ_SPI2_POS 0 +#define IRQ_UART1_RX_POS 4 +#define IRQ_UART1_TX_POS 8 +#define IRQ_ATAPI_RX_POS 12 +#define IRQ_ATAPI_TX_POS 16 +#define IRQ_TWI0_POS 20 +#define IRQ_TWI1_POS 24 +#define IRQ_CAN0_RX_POS 28 + +/* IAR6 BIT FIELDS */ +#define IRQ_CAN0_TX_POS 0 +#define IRQ_MDMAS2_POS 4 +#define IRQ_MDMAS3_POS 8 +#define IRQ_MXVR_ERR_POS 12 +#define IRQ_MXVR_MSG_POS 16 +#define IRQ_MXVR_PKT_POS 20 +#define IRQ_EPPI1_ERR_POS 24 +#define IRQ_EPPI2_ERR_POS 28 + +/* IAR7 BIT FIELDS */ +#define IRQ_UART3_ERR_POS 0 +#define IRQ_HOST_ERR_POS 4 +#define IRQ_PIXC_ERR_POS 12 +#define IRQ_NFC_ERR_POS 16 +#define IRQ_ATAPI_ERR_POS 20 +#define IRQ_CAN1_ERR_POS 24 +#define IRQ_HS_DMA_ERR_POS 28 + +/* IAR8 BIT FIELDS */ +#define IRQ_PIXC_IN0_POS 0 +#define IRQ_PIXC_IN1_POS 4 +#define IRQ_PIXC_OUT_POS 8 +#define IRQ_SDH_POS 12 +#define IRQ_CNT_POS 16 +#define IRQ_KEY_POS 20 +#define IRQ_CAN1_RX_POS 24 +#define IRQ_CAN1_TX_POS 28 + +/* IAR9 BIT FIELDS */ +#define IRQ_SDH_MASK0_POS 0 +#define IRQ_SDH_MASK1_POS 4 +#define IRQ_USB_INT0_POS 12 +#define IRQ_USB_INT1_POS 16 +#define IRQ_USB_INT2_POS 20 +#define IRQ_USB_DMA_POS 24 +#define IRQ_OTPSEC_POS 28 + +/* IAR10 BIT FIELDS */ +#define IRQ_TIMER0_POS 24 +#define IRQ_TIMER1_POS 28 + +/* IAR11 BIT FIELDS */ +#define IRQ_TIMER2_POS 0 +#define IRQ_TIMER3_POS 4 +#define IRQ_TIMER4_POS 8 +#define IRQ_TIMER5_POS 12 +#define IRQ_TIMER6_POS 16 +#define IRQ_TIMER7_POS 20 +#define IRQ_PINT2_POS 24 +#define IRQ_PINT3_POS 28 + +#endif /* _BF548_IRQ_H_ */ diff --git a/arch/blackfin/mach-bf548/include/mach/mem_init.h b/arch/blackfin/mach-bf548/include/mach/mem_init.h new file mode 100644 index 000000000000..ab0b863eee66 --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/mem_init.h @@ -0,0 +1,255 @@ +/* + * File: include/asm-blackfin/mach-bf548/mem_init.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * Copyright 2004-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1) +#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000) +#define DDR_CLK_HZ(x) (1000*1000*1000/x) + +#if (CONFIG_MEM_MT46V32M16_6T) +#define DDR_SIZE DEVSZ_512 +#define DDR_WIDTH DEVWD_16 +#define DDR_MAX_tCK 13 + +#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60)) +#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42)) +#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) +#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72)) +#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800)) + +#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) +#define DDR_tWTR DDR_TWTR(1) +#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12)) +#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15)) +#endif + +#if (CONFIG_MEM_MT46V32M16_5B) +#define DDR_SIZE DEVSZ_512 +#define DDR_WIDTH DEVWD_16 +#define DDR_MAX_tCK 13 + +#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55)) +#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40)) +#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) +#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70)) +#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800)) + +#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) +#define DDR_tWTR DDR_TWTR(2) +#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10)) +#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15)) +#endif + +#if (CONFIG_MEM_GENERIC_BOARD) +#define DDR_SIZE DEVSZ_512 +#define DDR_WIDTH DEVWD_16 +#define DDR_MAX_tCK 13 + +#define DDR_tRCD DDR_TRCD(3) +#define DDR_tWTR DDR_TWTR(2) +#define DDR_tWR DDR_TWR(2) +#define DDR_tMRD DDR_TMRD(2) +#define DDR_tRP DDR_TRP(3) +#define DDR_tRAS DDR_TRAS(7) +#define DDR_tRC DDR_TRC(10) +#define DDR_tRFC DDR_TRFC(12) +#define DDR_tREFI DDR_TREFI(1288) +#endif + +#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK)) +# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)." +#elif(CONFIG_SCLK_HZ <= 133333333) +# define DDR_CL CL_2 +#else +# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)." +#endif + + +#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI) +#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \ + | DDR_tMRD | DDR_tWR | DDR_tRCD) +#define mem_DDRCTL2 DDR_CL + + +#if defined CONFIG_CLKIN_HALF +#define CLKIN_HALF 1 +#else +#define CLKIN_HALF 0 +#endif + +#if defined CONFIG_PLL_BYPASS +#define PLL_BYPASS 1 +#else +#define PLL_BYPASS 0 +#endif + +/***************************************Currently Not Being Used *********************************/ +#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 +#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 +#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ)) +#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 +#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 + +#if (flash_EBIU_AMBCTL_TT > 3) +#define flash_EBIU_AMBCTL0_TT B0TT_4 +#endif +#if (flash_EBIU_AMBCTL_TT == 3) +#define flash_EBIU_AMBCTL0_TT B0TT_3 +#endif +#if (flash_EBIU_AMBCTL_TT == 2) +#define flash_EBIU_AMBCTL0_TT B0TT_2 +#endif +#if (flash_EBIU_AMBCTL_TT < 2) +#define flash_EBIU_AMBCTL0_TT B0TT_1 +#endif + +#if (flash_EBIU_AMBCTL_ST > 3) +#define flash_EBIU_AMBCTL0_ST B0ST_4 +#endif +#if (flash_EBIU_AMBCTL_ST == 3) +#define flash_EBIU_AMBCTL0_ST B0ST_3 +#endif +#if (flash_EBIU_AMBCTL_ST == 2) +#define flash_EBIU_AMBCTL0_ST B0ST_2 +#endif +#if (flash_EBIU_AMBCTL_ST < 2) +#define flash_EBIU_AMBCTL0_ST B0ST_1 +#endif + +#if (flash_EBIU_AMBCTL_HT > 2) +#define flash_EBIU_AMBCTL0_HT B0HT_3 +#endif +#if (flash_EBIU_AMBCTL_HT == 2) +#define flash_EBIU_AMBCTL0_HT B0HT_2 +#endif +#if (flash_EBIU_AMBCTL_HT == 1) +#define flash_EBIU_AMBCTL0_HT B0HT_1 +#endif +#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0) +#define flash_EBIU_AMBCTL0_HT B0HT_0 +#endif +#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0) +#define flash_EBIU_AMBCTL0_HT B0HT_1 +#endif + +#if (flash_EBIU_AMBCTL_WAT > 14) +#define flash_EBIU_AMBCTL0_WAT B0WAT_15 +#endif +#if (flash_EBIU_AMBCTL_WAT == 14) +#define flash_EBIU_AMBCTL0_WAT B0WAT_14 +#endif +#if (flash_EBIU_AMBCTL_WAT == 13) +#define flash_EBIU_AMBCTL0_WAT B0WAT_13 +#endif +#if (flash_EBIU_AMBCTL_WAT == 12) +#define flash_EBIU_AMBCTL0_WAT B0WAT_12 +#endif +#if (flash_EBIU_AMBCTL_WAT == 11) +#define flash_EBIU_AMBCTL0_WAT B0WAT_11 +#endif +#if (flash_EBIU_AMBCTL_WAT == 10) +#define flash_EBIU_AMBCTL0_WAT B0WAT_10 +#endif +#if (flash_EBIU_AMBCTL_WAT == 9) +#define flash_EBIU_AMBCTL0_WAT B0WAT_9 +#endif +#if (flash_EBIU_AMBCTL_WAT == 8) +#define flash_EBIU_AMBCTL0_WAT B0WAT_8 +#endif +#if (flash_EBIU_AMBCTL_WAT == 7) +#define flash_EBIU_AMBCTL0_WAT B0WAT_7 +#endif +#if (flash_EBIU_AMBCTL_WAT == 6) +#define flash_EBIU_AMBCTL0_WAT B0WAT_6 +#endif +#if (flash_EBIU_AMBCTL_WAT == 5) +#define flash_EBIU_AMBCTL0_WAT B0WAT_5 +#endif +#if (flash_EBIU_AMBCTL_WAT == 4) +#define flash_EBIU_AMBCTL0_WAT B0WAT_4 +#endif +#if (flash_EBIU_AMBCTL_WAT == 3) +#define flash_EBIU_AMBCTL0_WAT B0WAT_3 +#endif +#if (flash_EBIU_AMBCTL_WAT == 2) +#define flash_EBIU_AMBCTL0_WAT B0WAT_2 +#endif +#if (flash_EBIU_AMBCTL_WAT == 1) +#define flash_EBIU_AMBCTL0_WAT B0WAT_1 +#endif + +#if (flash_EBIU_AMBCTL_RAT > 14) +#define flash_EBIU_AMBCTL0_RAT B0RAT_15 +#endif +#if (flash_EBIU_AMBCTL_RAT == 14) +#define flash_EBIU_AMBCTL0_RAT B0RAT_14 +#endif +#if (flash_EBIU_AMBCTL_RAT == 13) +#define flash_EBIU_AMBCTL0_RAT B0RAT_13 +#endif +#if (flash_EBIU_AMBCTL_RAT == 12) +#define flash_EBIU_AMBCTL0_RAT B0RAT_12 +#endif +#if (flash_EBIU_AMBCTL_RAT == 11) +#define flash_EBIU_AMBCTL0_RAT B0RAT_11 +#endif +#if (flash_EBIU_AMBCTL_RAT == 10) +#define flash_EBIU_AMBCTL0_RAT B0RAT_10 +#endif +#if (flash_EBIU_AMBCTL_RAT == 9) +#define flash_EBIU_AMBCTL0_RAT B0RAT_9 +#endif +#if (flash_EBIU_AMBCTL_RAT == 8) +#define flash_EBIU_AMBCTL0_RAT B0RAT_8 +#endif +#if (flash_EBIU_AMBCTL_RAT == 7) +#define flash_EBIU_AMBCTL0_RAT B0RAT_7 +#endif +#if (flash_EBIU_AMBCTL_RAT == 6) +#define flash_EBIU_AMBCTL0_RAT B0RAT_6 +#endif +#if (flash_EBIU_AMBCTL_RAT == 5) +#define flash_EBIU_AMBCTL0_RAT B0RAT_5 +#endif +#if (flash_EBIU_AMBCTL_RAT == 4) +#define flash_EBIU_AMBCTL0_RAT B0RAT_4 +#endif +#if (flash_EBIU_AMBCTL_RAT == 3) +#define flash_EBIU_AMBCTL0_RAT B0RAT_3 +#endif +#if (flash_EBIU_AMBCTL_RAT == 2) +#define flash_EBIU_AMBCTL0_RAT B0RAT_2 +#endif +#if (flash_EBIU_AMBCTL_RAT == 1) +#define flash_EBIU_AMBCTL0_RAT B0RAT_1 +#endif + +#define flash_EBIU_AMBCTL0 \ + (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \ + flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN) diff --git a/arch/blackfin/mach-bf548/include/mach/mem_map.h b/arch/blackfin/mach-bf548/include/mach/mem_map.h new file mode 100644 index 000000000000..f99f47bc3a07 --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/mem_map.h @@ -0,0 +1,111 @@ +/* + * file: include/asm-blackfin/mach-bf548/mem_map.h + * based on: + * author: + * + * created: + * description: + * Memory MAP Common header file for blackfin BF537/6/4 of processors. + * rev: + * + * modified: + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + +#ifndef _MEM_MAP_548_H_ +#define _MEM_MAP_548_H_ + +#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ +#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ + +/* Async Memory Banks */ +#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ +#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */ +#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */ +#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */ +#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */ +#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */ +#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ +#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */ + +/* Boot ROM Memory */ + +#define BOOT_ROM_START 0xEF000000 +#define BOOT_ROM_LENGTH 0x1000 + +/* L1 Instruction ROM */ + +#define L1_ROM_START 0xFFA14000 +#define L1_ROM_LENGTH 0x10000 + +/* Level 1 Memory */ + +/* Memory Map for ADSP-BF548 processors */ +#ifdef CONFIG_BFIN_ICACHE +#define BFIN_ICACHESIZE (16*1024) +#else +#define BFIN_ICACHESIZE (0*1024) +#endif + +#define L1_CODE_START 0xFFA00000 +#define L1_DATA_A_START 0xFF800000 +#define L1_DATA_B_START 0xFF900000 + +#define L1_CODE_LENGTH 0xC000 + +#ifdef CONFIG_BFIN_DCACHE + +#ifdef CONFIG_BFIN_DCACHE_BANKA +#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) +#define L1_DATA_A_LENGTH (0x8000 - 0x4000) +#define L1_DATA_B_LENGTH 0x8000 +#define BFIN_DCACHESIZE (16*1024) +#define BFIN_DSUPBANKS 1 +#else +#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) +#define L1_DATA_A_LENGTH (0x8000 - 0x4000) +#define L1_DATA_B_LENGTH (0x8000 - 0x4000) +#define BFIN_DCACHESIZE (32*1024) +#define BFIN_DSUPBANKS 2 +#endif + +#else +#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) +#define L1_DATA_A_LENGTH 0x8000 +#define L1_DATA_B_LENGTH 0x8000 +#define BFIN_DCACHESIZE (0*1024) +#define BFIN_DSUPBANKS 0 +#endif /*CONFIG_BFIN_DCACHE*/ + +/* Level 2 Memory */ +#if !defined(CONFIG_BF542) +# define L2_START 0xFEB00000 +# if defined(CONFIG_BF544) +# define L2_LENGTH 0x10000 +# else +# define L2_LENGTH 0x20000 +# endif +#endif + +/* Scratch Pad Memory */ + +#define L1_SCRATCH_START 0xFFB00000 +#define L1_SCRATCH_LENGTH 0x1000 + +#endif/* _MEM_MAP_548_H_ */ diff --git a/arch/blackfin/mach-bf548/include/mach/portmux.h b/arch/blackfin/mach-bf548/include/mach/portmux.h new file mode 100644 index 000000000000..8177a567dcdb --- /dev/null +++ b/arch/blackfin/mach-bf548/include/mach/portmux.h @@ -0,0 +1,286 @@ +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS + +#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0)) +#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0)) +#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0)) +#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0)) +#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0)) +#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0)) +#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0)) +#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0)) +#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0)) +#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0)) +#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0)) +#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0)) +#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0)) +#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0)) +#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0)) +#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0)) +#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1)) +#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1)) +#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1)) +#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1)) + +#define P_TWI1_SCL (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0)) +#define P_TWI1_SDA (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0)) +#define P_UART3_RTS (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0)) +#define P_UART3_CTS (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0)) +#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0)) +#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0)) +#define P_UART3_TX (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0)) +#define P_UART3_RX (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0)) +#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0)) +#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(0)) +#define P_SPI2_SSEL2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0)) +#define P_SPI2_SSEL3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0)) +#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(0)) +#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0)) +#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0)) +#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1)) +#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(1)) +#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(1)) +#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(1)) + +#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0)) +#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0)) +#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0)) +#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0)) +#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0)) +#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0)) +#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0)) +#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0)) +#define P_SD_D0 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(0)) +#define P_SD_D1 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0)) +#define P_SD_D2 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(0)) +#define P_SD_D3 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(0)) +#define P_SD_CLK (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0)) +#define P_SD_CMD (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0)) +#define P_MMCLK (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1)) +#define P_MBCLK (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1)) + +#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0)) +#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0)) +#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0)) +#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0)) +#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0)) +#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0)) +#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0)) +#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(0)) +#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(0)) +#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0)) +#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0)) +#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0)) +#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0)) +#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0)) +#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0)) +#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(0)) + +#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1)) +#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1)) +#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(1)) +#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(1)) +#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(1)) +#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(1)) +#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1)) +#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1)) +#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1)) +#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1)) +#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1)) +#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(1)) +#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1)) +#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(1)) +#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(1)) +#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1)) +#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2)) +#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2)) +#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(2)) +#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(2)) +#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(2)) +#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(2)) +#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(2)) +#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(2)) +#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(2)) +#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2)) +#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2)) +#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(2)) +#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2)) +#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(2)) +#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(2)) +#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2)) +#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(3)) +#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(3)) +#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(3)) +#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(3)) +#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(3)) +#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(3)) +#define P_KEY_ROW0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(3)) +#define P_KEY_ROW1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(3)) +#define P_KEY_ROW2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(3)) +#define P_KEY_ROW3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3)) +#define P_KEY_COL0 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3)) +#define P_KEY_COL1 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(3)) +#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3)) +#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3)) + +#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0)) +#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0)) +#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0)) +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(0)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(0)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(0)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0)) +#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0)) +#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(0)) +#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(0)) +#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0)) +#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0)) +#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0)) +#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0)) +#define P_TWI0_SCL (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0)) +#define P_TWI0_SDA (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0)) +#define P_KEY_COL7 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1)) +#define P_KEY_ROW6 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1)) +#define P_KEY_COL6 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1)) +#define P_KEY_ROW5 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1)) +#define P_KEY_COL5 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1)) +#define P_KEY_ROW4 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1)) +#define P_KEY_COL4 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1)) +#define P_KEY_ROW7 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1)) + +#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) +#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) +#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) +#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0)) +#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0)) +#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0)) +#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0)) +#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0)) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0)) +#define P_ATAPI_D0A (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) +#define P_ATAPI_D1A (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) +#define P_ATAPI_D2A (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) +#define P_ATAPI_D3A (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) +#define P_ATAPI_D4A (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) +#define P_ATAPI_D5A (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) +#define P_ATAPI_D6A (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) +#define P_ATAPI_D7A (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) +#define P_ATAPI_D8A (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) +#define P_ATAPI_D9A (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) +#define P_ATAPI_D10A (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1)) +#define P_ATAPI_D11A (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1)) +#define P_ATAPI_D12A (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1)) +#define P_ATAPI_D13A (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1)) +#define P_ATAPI_D14A (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) +#define P_ATAPI_D15A (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) + +#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) +#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) +#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0)) +#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0)) +#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0)) +#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) +#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) +#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0)) +#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0)) +#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0)) +#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0)) +#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) +#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0)) +#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) +#define P_CAN1_TX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) +#define P_CAN1_RX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) +#define P_ATAPI_A0A (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1)) +#define P_ATAPI_A1A (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1)) +#define P_ATAPI_A2A (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1)) +#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1)) +#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1)) +#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1)) +#define P_MTXONB (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) +#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2)) +#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2)) +#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2)) +#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(3)) + +#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0)) +#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0)) +#define P_ATAPI_RESET (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0)) +#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0)) +#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0)) +#define P_MTX (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0)) +#define P_MRX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0)) +#define P_MRXONB (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0)) +#define P_A4 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0)) +#define P_A5 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0)) +#define P_A6 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0)) +#define P_A7 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0)) +#define P_A8 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0)) +#define P_A9 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0)) +#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1)) +#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1)) +#define P_TMR8 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1)) +#define P_TMR9 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1)) +#define P_TMR10 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1)) +#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1)) +#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1)) +#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2)) +#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2)) +#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2)) + +#define P_A10 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI0) | P_FUNCT(0)) +#define P_A11 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI1) | P_FUNCT(0)) +#define P_A12 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI2) | P_FUNCT(0)) +#define P_A13 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI3) | P_FUNCT(0)) +#define P_A14 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI4) | P_FUNCT(0)) +#define P_A15 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI5) | P_FUNCT(0)) +#define P_A16 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI6) | P_FUNCT(0)) +#define P_A17 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI7) | P_FUNCT(0)) +#define P_A18 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI8) | P_FUNCT(0)) +#define P_A19 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI9) | P_FUNCT(0)) +#define P_A20 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI10) | P_FUNCT(0)) +#define P_A21 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI11) | P_FUNCT(0)) +#define P_A22 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI12) | P_FUNCT(0)) +#define P_A23 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI13) | P_FUNCT(0)) +#define P_A24 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI14) | P_FUNCT(0)) +#define P_A25 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(0)) +#define P_NOR_CLK (P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(1)) + +#define P_AMC_ARDY_NOR_WAIT (P_DEFINED | P_IDENT(GPIO_PJ0) | P_FUNCT(0)) +#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PJ1) | P_FUNCT(0)) +#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PJ2) | P_FUNCT(0)) +#define P_ATAPI_DIOR (P_DEFINED | P_IDENT(GPIO_PJ3) | P_FUNCT(0)) +#define P_ATAPI_DIOW (P_DEFINED | P_IDENT(GPIO_PJ4) | P_FUNCT(0)) +#define P_ATAPI_CS0 (P_DEFINED | P_IDENT(GPIO_PJ5) | P_FUNCT(0)) +#define P_ATAPI_CS1 (P_DEFINED | P_IDENT(GPIO_PJ6) | P_FUNCT(0)) +#define P_ATAPI_DMACK (P_DEFINED | P_IDENT(GPIO_PJ7) | P_FUNCT(0)) +#define P_ATAPI_DMARQ (P_DEFINED | P_IDENT(GPIO_PJ8) | P_FUNCT(0)) +#define P_ATAPI_INTRQ (P_DEFINED | P_IDENT(GPIO_PJ9) | P_FUNCT(0)) +#define P_ATAPI_IORDY (P_DEFINED | P_IDENT(GPIO_PJ10) | P_FUNCT(0)) +#define P_AMC_BR (P_DEFINED | P_IDENT(GPIO_PJ11) | P_FUNCT(0)) +#define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0)) +#define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0)) + + +#define P_NAND_D0 (P_DONTCARE) +#define P_NAND_D1 (P_DONTCARE) +#define P_NAND_D2 (P_DONTCARE) +#define P_NAND_D3 (P_DONTCARE) +#define P_NAND_D4 (P_DONTCARE) +#define P_NAND_D5 (P_DONTCARE) +#define P_NAND_D6 (P_DONTCARE) +#define P_NAND_D7 (P_DONTCARE) +#define P_NAND_WE (P_DONTCARE) +#define P_NAND_RE (P_DONTCARE) +#define P_NAND_CLE (P_DONTCARE) +#define P_NAND_ALE (P_DONTCARE) + +#endif /* _MACH_PORTMUX_H_ */ |