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Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3399.dtsi')
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399.dtsi116
1 files changed, 104 insertions, 12 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 3871c7fd83b0..d3cdf6f42a30 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -124,6 +124,12 @@
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <436>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+
+ thermal-idle {
+ #cooling-cells = <2>;
+ duration-us = <10000>;
+ exit-latency-us = <500>;
+ };
};
cpu_b1: cpu@101 {
@@ -136,6 +142,12 @@
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <436>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+
+ thermal-idle {
+ #cooling-cells = <2>;
+ duration-us = <10000>;
+ exit-latency-us = <500>;
+ };
};
idle-states {
@@ -361,6 +373,54 @@
status = "disabled";
};
+ debug@fe430000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfe430000 0 0x1000>;
+ clocks = <&cru PCLK_COREDBG_L>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu_l0>;
+ };
+
+ debug@fe432000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfe432000 0 0x1000>;
+ clocks = <&cru PCLK_COREDBG_L>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu_l1>;
+ };
+
+ debug@fe434000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfe434000 0 0x1000>;
+ clocks = <&cru PCLK_COREDBG_L>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu_l2>;
+ };
+
+ debug@fe436000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfe436000 0 0x1000>;
+ clocks = <&cru PCLK_COREDBG_L>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu_l3>;
+ };
+
+ debug@fe610000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfe610000 0 0x1000>;
+ clocks = <&cru PCLK_COREDBG_B>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu_b0>;
+ };
+
+ debug@fe710000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfe710000 0 0x1000>;
+ clocks = <&cru PCLK_COREDBG_B>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu_b1>;
+ };
+
usbdrd3_0: usb@fe800000 {
compatible = "rockchip,rk3399-dwc3";
#address-cells = <2>;
@@ -1251,7 +1311,6 @@
compatible = "rockchip,iommu";
reg = <0x0 0xff650800 0x0 0x40>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vpu_mmu";
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
@@ -1273,7 +1332,6 @@
compatible = "rockchip,iommu";
reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vdec_mmu";
clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
clock-names = "aclk", "iface";
power-domains = <&power RK3399_PD_VDU>;
@@ -1284,7 +1342,6 @@
compatible = "rockchip,iommu";
reg = <0x0 0xff670800 0x0 0x40>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "iep_mmu";
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
@@ -1666,7 +1723,6 @@
compatible = "rockchip,iommu";
reg = <0x0 0xff8f3f00 0x0 0x100>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vopl_mmu";
clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
clock-names = "aclk", "iface";
power-domains = <&power RK3399_PD_VOPL>;
@@ -1723,7 +1779,6 @@
compatible = "rockchip,iommu";
reg = <0x0 0xff903f00 0x0 0x100>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vopb_mmu";
clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
clock-names = "aclk", "iface";
power-domains = <&power RK3399_PD_VOPB>;
@@ -1761,7 +1816,6 @@
compatible = "rockchip,iommu";
reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "isp0_mmu";
clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
@@ -1769,11 +1823,36 @@
rockchip,disable-mmu-reset;
};
+ isp1: isp1@ff920000 {
+ compatible = "rockchip,rk3399-cif-isp";
+ reg = <0x0 0xff920000 0x0 0x4000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_ISP1>,
+ <&cru ACLK_ISP1_WRAPPER>,
+ <&cru HCLK_ISP1_WRAPPER>;
+ clock-names = "isp", "aclk", "hclk";
+ iommus = <&isp1_mmu>;
+ phys = <&mipi_dsi1>;
+ phy-names = "dphy";
+ power-domains = <&power RK3399_PD_ISP1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+
isp1_mmu: iommu@ff924000 {
compatible = "rockchip,iommu";
reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "isp1_mmu";
clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
@@ -1878,6 +1957,7 @@
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
+ #phy-cells = <0>;
status = "disabled";
ports {
@@ -1958,7 +2038,7 @@
#size-cells = <2>;
ranges;
- gpio0: gpio0@ff720000 {
+ gpio0: gpio@ff720000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff720000 0x0 0x100>;
clocks = <&pmucru PCLK_GPIO0_PMU>;
@@ -1971,7 +2051,7 @@
#interrupt-cells = <0x2>;
};
- gpio1: gpio1@ff730000 {
+ gpio1: gpio@ff730000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff730000 0x0 0x100>;
clocks = <&pmucru PCLK_GPIO1_PMU>;
@@ -1984,7 +2064,7 @@
#interrupt-cells = <0x2>;
};
- gpio2: gpio2@ff780000 {
+ gpio2: gpio@ff780000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff780000 0x0 0x100>;
clocks = <&cru PCLK_GPIO2>;
@@ -1997,7 +2077,7 @@
#interrupt-cells = <0x2>;
};
- gpio3: gpio3@ff788000 {
+ gpio3: gpio@ff788000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff788000 0x0 0x100>;
clocks = <&cru PCLK_GPIO3>;
@@ -2010,7 +2090,7 @@
#interrupt-cells = <0x2>;
};
- gpio4: gpio4@ff790000 {
+ gpio4: gpio@ff790000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff790000 0x0 0x100>;
clocks = <&cru PCLK_GPIO4>;
@@ -2114,6 +2194,18 @@
};
};
+ cif {
+ cif_clkin: cif-clkin {
+ rockchip,pins =
+ <2 RK_PB2 3 &pcfg_pull_none>;
+ };
+
+ cif_clkouta: cif-clkouta {
+ rockchip,pins =
+ <2 RK_PB3 3 &pcfg_pull_none>;
+ };
+ };
+
edp {
edp_hpd: edp-hpd {
rockchip,pins =
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-21 11:23:57 +0000