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-rw-r--r--arch/arm64/boot/dts/qcom/msm8996.dtsi391
1 files changed, 217 insertions, 174 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index c0a2baffa49d..d31464204f69 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -144,82 +145,92 @@
/* Nominal fmax for now */
opp-307200000 {
opp-hz = /bits/ 64 <307200000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-422400000 {
opp-hz = /bits/ 64 <422400000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-480000000 {
opp-hz = /bits/ 64 <480000000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-556800000 {
opp-hz = /bits/ 64 <556800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-652800000 {
opp-hz = /bits/ 64 <652800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-844800000 {
opp-hz = /bits/ 64 <844800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-960000000 {
opp-hz = /bits/ 64 <960000000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1228800000 {
opp-hz = /bits/ 64 <1228800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1324800000 {
opp-hz = /bits/ 64 <1324800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xd>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1363200000 {
+ opp-hz = /bits/ 64 <1363200000>;
+ opp-supported-hw = <0x2>;
clock-latency-ns = <200000>;
};
opp-1401600000 {
opp-hz = /bits/ 64 <1401600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xd>;
clock-latency-ns = <200000>;
};
opp-1478400000 {
opp-hz = /bits/ 64 <1478400000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0x9>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ opp-supported-hw = <0x04>;
clock-latency-ns = <200000>;
};
opp-1593600000 {
opp-hz = /bits/ 64 <1593600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0x9>;
clock-latency-ns = <200000>;
};
};
@@ -232,127 +243,137 @@
/* Nominal fmax for now */
opp-307200000 {
opp-hz = /bits/ 64 <307200000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-403200000 {
opp-hz = /bits/ 64 <403200000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-480000000 {
opp-hz = /bits/ 64 <480000000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-556800000 {
opp-hz = /bits/ 64 <556800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-652800000 {
opp-hz = /bits/ 64 <652800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-806400000 {
opp-hz = /bits/ 64 <806400000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-883200000 {
opp-hz = /bits/ 64 <883200000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-940800000 {
opp-hz = /bits/ 64 <940800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1248000000 {
opp-hz = /bits/ 64 <1248000000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1324800000 {
opp-hz = /bits/ 64 <1324800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1401600000 {
opp-hz = /bits/ 64 <1401600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1478400000 {
opp-hz = /bits/ 64 <1478400000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1555200000 {
opp-hz = /bits/ 64 <1555200000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1632000000 {
opp-hz = /bits/ 64 <1632000000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1708800000 {
opp-hz = /bits/ 64 <1708800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1785600000 {
opp-hz = /bits/ 64 <1785600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1804800000 {
+ opp-hz = /bits/ 64 <1804800000>;
+ opp-supported-hw = <0xe>;
clock-latency-ns = <200000>;
};
opp-1824000000 {
opp-hz = /bits/ 64 <1824000000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1900800000 {
+ opp-hz = /bits/ 64 <1900800000>;
+ opp-supported-hw = <0x4>;
clock-latency-ns = <200000>;
};
opp-1920000000 {
opp-hz = /bits/ 64 <1920000000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
};
opp-1996800000 {
opp-hz = /bits/ 64 <1996800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
};
opp-2073600000 {
opp-hz = /bits/ 64 <2073600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
};
opp-2150400000 {
opp-hz = /bits/ 64 <2150400000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
};
};
@@ -860,9 +881,9 @@
<&gcc GPLL0>,
<&dsi0_phy 1>,
<&dsi0_phy 0>,
- <0>,
- <0>,
- <0>;
+ <&dsi1_phy 1>,
+ <&dsi1_phy 0>,
+ <&hdmi_phy>;
clock-names = "xo",
"gcc_mmss_noc_cfg_ahb_clk",
"gpll0",
@@ -993,7 +1014,6 @@
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
phys = <&dsi0_phy>;
- phy-names = "dsi";
status = "disabled";
#address-cells = <1>;
@@ -1018,7 +1038,7 @@
};
};
- dsi0_phy: dsi-phy@994400 {
+ dsi0_phy: phy@994400 {
compatible = "qcom,dsi-phy-14nm";
reg = <0x00994400 0x100>,
<0x00994500 0x300>,
@@ -1061,7 +1081,6 @@
assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
phys = <&dsi1_phy>;
- phy-names = "dsi";
status = "disabled";
#address-cells = <1>;
@@ -1086,7 +1105,7 @@
};
};
- dsi1_phy: dsi-phy@996400 {
+ dsi1_phy: phy@996400 {
compatible = "qcom,dsi-phy-14nm";
reg = <0x00996400 0x100>,
<0x00996500 0x300>,
@@ -1145,7 +1164,7 @@
};
};
- hdmi_phy: hdmi-phy@9a0600 {
+ hdmi_phy: phy@9a0600 {
#phy-cells = <0>;
compatible = "qcom,hdmi-phy-8996";
reg = <0x009a0600 0x1c4>,
@@ -1213,17 +1232,17 @@
compatible = "operating-points-v2";
/*
- * 624Mhz and 560Mhz are only available on speed
- * bin (1 << 0). All the rest are available on
- * all bins of the hardware
+ * 624Mhz is only available on speed bins 0 and 3.
+ * 560Mhz is only available on speed bins 0, 2 and 3.
+ * All the rest are available on all bins of the hardware.
*/
opp-624000000 {
opp-hz = /bits/ 64 <624000000>;
- opp-supported-hw = <0x01>;
+ opp-supported-hw = <0x09>;
};
opp-560000000 {
opp-hz = /bits/ 64 <560000000>;
- opp-supported-hw = <0x01>;
+ opp-supported-hw = <0x0d>;
};
opp-510000000 {
opp-hz = /bits/ 64 <510000000>;
@@ -1262,15 +1281,15 @@
interrupt-controller;
#interrupt-cells = <2>;
- blsp1_spi1_default: blsp1-spi1-default {
- spi {
+ blsp1_spi1_default: blsp1-spi1-default-state {
+ spi-pins {
pins = "gpio0", "gpio1", "gpio3";
function = "blsp_spi1";
drive-strength = <12>;
bias-disable;
};
- cs {
+ cs-pins {
pins = "gpio2";
function = "gpio";
drive-strength = <16>;
@@ -1279,42 +1298,56 @@
};
};
- blsp1_spi1_sleep: blsp1-spi1-sleep {
+ blsp1_spi1_sleep: blsp1-spi1-sleep-state {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- blsp2_uart2_2pins_default: blsp2-uart1-2pins {
+ blsp2_uart2_2pins_default: blsp2-uart2-2pins-state {
pins = "gpio4", "gpio5";
function = "blsp_uart8";
drive-strength = <16>;
bias-disable;
};
- blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
+ blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state {
pins = "gpio4", "gpio5";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- blsp2_i2c2_default: blsp2-i2c2 {
+ blsp2_i2c2_default: blsp2-i2c2-state {
pins = "gpio6", "gpio7";
function = "blsp_i2c8";
drive-strength = <16>;
bias-disable;
};
- blsp2_i2c2_sleep: blsp2-i2c2-sleep {
+ blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
pins = "gpio6", "gpio7";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- cci0_default: cci0-default {
+ blsp1_i2c6_default: blsp1-i2c6-state {
+ pins = "gpio27", "gpio28";
+ function = "blsp_i2c6";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
+ pins = "gpio27", "gpio28";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci0_default: cci0-default-state {
pins = "gpio17", "gpio18";
function = "cci_i2c";
drive-strength = <16>;
@@ -1322,22 +1355,22 @@
};
camera0_state_on:
- camera_rear_default: camera-rear-default {
- camera0_mclk: mclk0 {
+ camera_rear_default: camera-rear-default-state {
+ camera0_mclk: mclk0-pins {
pins = "gpio13";
function = "cam_mclk";
drive-strength = <16>;
bias-disable;
};
- camera0_rst: rst {
+ camera0_rst: rst-pins {
pins = "gpio25";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
- camera0_pwdn: pwdn {
+ camera0_pwdn: pwdn-pins {
pins = "gpio26";
function = "gpio";
drive-strength = <16>;
@@ -1345,7 +1378,7 @@
};
};
- cci1_default: cci1-default {
+ cci1_default: cci1-default-state {
pins = "gpio19", "gpio20";
function = "cci_i2c";
drive-strength = <16>;
@@ -1353,22 +1386,22 @@
};
camera1_state_on:
- camera_board_default: camera-board-default {
- mclk1 {
+ camera_board_default: camera-board-default-state {
+ mclk1-pins {
pins = "gpio14";
function = "cam_mclk";
drive-strength = <16>;
bias-disable;
};
- pwdn {
+ pwdn-pins {
pins = "gpio98";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
- rst {
+ rst-pins {
pins = "gpio104";
function = "gpio";
drive-strength = <16>;
@@ -1377,22 +1410,22 @@
};
camera2_state_on:
- camera_front_default: camera-front-default {
- camera2_mclk: mclk2 {
+ camera_front_default: camera-front-default-state {
+ camera2_mclk: mclk2-pins {
pins = "gpio15";
function = "cam_mclk";
drive-strength = <16>;
bias-disable;
};
- camera2_rst: rst {
+ camera2_rst: rst-pins {
pins = "gpio23";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
- pwdn {
+ pwdn-pins {
pins = "gpio133";
function = "gpio";
drive-strength = <16>;
@@ -1400,22 +1433,22 @@
};
};
- pcie0_state_on: pcie0-state-on {
- perst {
+ pcie0_state_on: pcie0-state-on-state {
+ perst-pins {
pins = "gpio35";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- clkreq {
+ clkreq-pins {
pins = "gpio36";
function = "pci_e0";
drive-strength = <2>;
bias-pull-up;
};
- wake {
+ wake-pins {
pins = "gpio37";
function = "gpio";
drive-strength = <2>;
@@ -1423,22 +1456,22 @@
};
};
- pcie0_state_off: pcie0-state-off {
- perst {
+ pcie0_state_off: pcie0-state-off-state {
+ perst-pins {
pins = "gpio35";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- clkreq {
+ clkreq-pins {
pins = "gpio36";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- wake {
+ wake-pins {
pins = "gpio37";
function = "gpio";
drive-strength = <2>;
@@ -1446,63 +1479,63 @@
};
};
- blsp1_uart2_default: blsp1-uart2-default {
+ blsp1_uart2_default: blsp1-uart2-default-state {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "blsp_uart2";
drive-strength = <16>;
bias-disable;
};
- blsp1_uart2_sleep: blsp1-uart2-sleep {
+ blsp1_uart2_sleep: blsp1-uart2-sleep-state {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- blsp1_i2c3_default: blsp1-i2c2-default {
+ blsp1_i2c3_default: blsp1-i2c3-default-state {
pins = "gpio47", "gpio48";
function = "blsp_i2c3";
drive-strength = <16>;
bias-disable;
};
- blsp1_i2c3_sleep: blsp1-i2c2-sleep {
+ blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
pins = "gpio47", "gpio48";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- blsp2_uart3_4pins_default: blsp2-uart2-4pins {
+ blsp2_uart3_4pins_default: blsp2-uart3-4pins-state {
pins = "gpio49", "gpio50", "gpio51", "gpio52";
function = "blsp_uart9";
drive-strength = <16>;
bias-disable;
};
- blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
+ blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state {
pins = "gpio49", "gpio50", "gpio51", "gpio52";
function = "blsp_uart9";
drive-strength = <2>;
bias-disable;
};
- blsp2_i2c3_default: blsp2-i2c3 {
+ blsp2_i2c3_default: blsp2-i2c3-state-state {
pins = "gpio51", "gpio52";
function = "blsp_i2c9";
drive-strength = <16>;
bias-disable;
};
- blsp2_i2c3_sleep: blsp2-i2c3-sleep {
+ blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
pins = "gpio51", "gpio52";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- wcd_intr_default: wcd-intr-default{
+ wcd_intr_default: wcd-intr-default-state {
pins = "gpio54";
function = "gpio";
drive-strength = <2>;
@@ -1510,21 +1543,21 @@
input-enable;
};
- blsp2_i2c1_default: blsp2-i2c1 {
+ blsp2_i2c1_default: blsp2-i2c1-state {
pins = "gpio55", "gpio56";
function = "blsp_i2c7";
drive-strength = <16>;
bias-disable;
};
- blsp2_i2c1_sleep: blsp2-i2c0-sleep {
+ blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
pins = "gpio55", "gpio56";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- blsp2_i2c5_default: blsp2-i2c5 {
+ blsp2_i2c5_default: blsp2-i2c5-state {
pins = "gpio60", "gpio61";
function = "blsp_i2c11";
drive-strength = <2>;
@@ -1533,7 +1566,7 @@
/* Sleep state for BLSP2_I2C5 is missing.. */
- cdc_reset_active: cdc-reset-active {
+ cdc_reset_active: cdc-reset-active-state {
pins = "gpio64";
function = "gpio";
drive-strength = <16>;
@@ -1541,7 +1574,7 @@
output-high;
};
- cdc_reset_sleep: cdc-reset-sleep {
+ cdc_reset_sleep: cdc-reset-sleep-state {
pins = "gpio64";
function = "gpio";
drive-strength = <16>;
@@ -1549,15 +1582,15 @@
output-low;
};
- blsp2_spi6_default: blsp2-spi5-default {
- spi {
+ blsp2_spi6_default: blsp2-spi6-default-state {
+ spi-pins {
pins = "gpio85", "gpio86", "gpio88";
function = "blsp_spi12";
drive-strength = <12>;
bias-disable;
};
- cs {
+ cs-pins {
pins = "gpio87";
function = "gpio";
drive-strength = <16>;
@@ -1566,43 +1599,43 @@
};
};
- blsp2_spi6_sleep: blsp2-spi5-sleep {
+ blsp2_spi6_sleep: blsp2-spi6-sleep-state {
pins = "gpio85", "gpio86", "gpio87", "gpio88";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- blsp2_i2c6_default: blsp2-i2c6 {
+ blsp2_i2c6_default: blsp2-i2c6-state {
pins = "gpio87", "gpio88";
function = "blsp_i2c12";
drive-strength = <16>;
bias-disable;
};
- blsp2_i2c6_sleep: blsp2-i2c6-sleep {
+ blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
pins = "gpio87", "gpio88";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- pcie1_state_on: pcie1-state-on {
- perst {
+ pcie1_state_on: pcie1-on-state {
+ perst-pins {
pins = "gpio130";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- clkreq {
+ clkreq-pins {
pins = "gpio131";
function = "pci_e1";
drive-strength = <2>;
bias-pull-up;
};
- wake {
+ wake-pins {
pins = "gpio132";
function = "gpio";
drive-strength = <2>;
@@ -1610,16 +1643,16 @@
};
};
- pcie1_state_off: pcie1-state-off {
+ pcie1_state_off: pcie1-off-state {
/* Perst is missing? */
- clkreq {
+ clkreq-pins {
pins = "gpio131";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- wake {
+ wake-pins {
pins = "gpio132";
function = "gpio";
drive-strength = <2>;
@@ -1627,22 +1660,22 @@
};
};
- pcie2_state_on: pcie2-state-on {
- perst {
+ pcie2_state_on: pcie2-on-state {
+ perst-pins {
pins = "gpio114";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- clkreq {
+ clkreq-pins {
pins = "gpio115";
function = "pci_e2";
drive-strength = <2>;
bias-pull-up;
};
- wake {
+ wake-pins {
pins = "gpio116";
function = "gpio";
drive-strength = <2>;
@@ -1650,16 +1683,16 @@
};
};
- pcie2_state_off: pcie2-state-off {
+ pcie2_state_off: pcie2-off-state {
/* Perst is missing? */
- clkreq {
+ clkreq-pins {
pins = "gpio115";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- wake {
+ wake-pins {
pins = "gpio116";
function = "gpio";
drive-strength = <2>;
@@ -1667,90 +1700,90 @@
};
};
- sdc1_state_on: sdc1-state-on {
- clk {
+ sdc1_state_on: sdc1-on-state {
+ clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
- cmd {
+ cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
- data {
+ data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};
- rclk {
+ rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
- sdc1_state_off: sdc1-state-off {
- clk {
+ sdc1_state_off: sdc1-off-state {
+ clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
- cmd {
+ cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
- data {
+ data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
- rclk {
+ rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
- sdc2_state_on: sdc2-clk-on {
- clk {
+ sdc2_state_on: sdc2-on-state {
+ clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
- cmd {
+ cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
- data {
+ data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
};
- sdc2_state_off: sdc2-clk-off {
- clk {
+ sdc2_state_off: sdc2-off-state {
+ clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <2>;
};
- cmd {
+ cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <2>;
};
- data {
+ data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <2>;
@@ -1995,10 +2028,6 @@
lanes-per-direction = <1>;
#reset-cells = <1>;
status = "disabled";
-
- ufs_variant {
- compatible = "qcom,ufs_variant";
- };
};
ufsphy: phy@627000 {
@@ -2205,9 +2234,9 @@
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
- clocks = <&mmcc GPU_AHB_CLK>,
- <&gcc GCC_MMSS_BIMC_GFX_CLK>;
- clock-names = "iface", "bus";
+ clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>,
+ <&mmcc GPU_AHB_CLK>;
+ clock-names = "bus", "iface";
power-domains = <&mmcc GPU_GDSC>;
};
@@ -2272,9 +2301,9 @@
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
- clocks = <&mmcc SMMU_MDP_AHB_CLK>,
- <&mmcc SMMU_MDP_AXI_CLK>;
- clock-names = "iface", "bus";
+ clocks = <&mmcc SMMU_MDP_AXI_CLK>,
+ <&mmcc SMMU_MDP_AHB_CLK>;
+ clock-names = "bus", "iface";
power-domains = <&mmcc MDSS_GDSC>;
};
@@ -2292,9 +2321,9 @@
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
- clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
- <&mmcc SMMU_VIDEO_AXI_CLK>;
- clock-names = "iface", "bus";
+ clocks = <&mmcc SMMU_VIDEO_AXI_CLK>,
+ <&mmcc SMMU_VIDEO_AHB_CLK>;
+ clock-names = "bus", "iface";
#iommu-cells = <1>;
status = "okay";
};
@@ -2308,10 +2337,9 @@
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
- clocks = <&mmcc SMMU_VFE_AHB_CLK>,
- <&mmcc SMMU_VFE_AXI_CLK>;
- clock-names = "iface",
- "bus";
+ clocks = <&mmcc SMMU_VFE_AXI_CLK>,
+ <&mmcc SMMU_VFE_AHB_CLK>;
+ clock-names = "bus", "iface";
#iommu-cells = <1>;
};
@@ -2336,9 +2364,9 @@
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
- <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
- clock-names = "iface", "bus";
+ clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>,
+ <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>;
+ clock-names = "bus", "iface";
};
slpi_pil: remoteproc@1c00000 {
@@ -3127,6 +3155,23 @@
status = "disabled";
};
+ blsp1_i2c6: i2c@757a000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x757a000 0x1000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_i2c6_default>;
+ pinctrl-1 = <&blsp1_i2c6_sleep>;
+ dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
blsp2_dma: dma-controller@7584000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07584000 0x2b000>;
@@ -3309,27 +3354,25 @@
qcom,num-ees = <2>;
};
- slim_msm: slim@91c0000 {
+ slim_msm: slim-ngd@91c0000 {
compatible = "qcom,slim-ngd-v1.5.0";
reg = <0x091c0000 0x2C000>;
- reg-names = "ctrl";
interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&slimbam 3>, <&slimbam 4>,
- <&slimbam 5>, <&slimbam 6>;
- dma-names = "rx", "tx", "tx2", "rx2";
+ dmas = <&slimbam 3>, <&slimbam 4>;
+ dma-names = "rx", "tx";
#address-cells = <1>;
#size-cells = <0>;
- ngd@1 {
+ slim@1 {
reg = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <0>;
- tasha_ifd: tas-ifd {
+ tasha_ifd: tas-ifd@0,0 {
compatible = "slim217,1a0";
reg = <0 0>;
};
- wcd9335: codec@1{
+ wcd9335: codec@1,0 {
pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
pinctrl-names = "default";
@@ -3342,7 +3385,7 @@
interrupt-names = "intr1", "intr2";
interrupt-controller;
#interrupt-cells = <1>;
- reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
slim-ifc-dev = <&tasha_ifd>;
@@ -3393,12 +3436,12 @@
#address-cells = <1>;
#size-cells = <0>;
- q6core {
+ service@3 {
reg = <APR_SVC_ADSP_CORE>;
compatible = "qcom,q6core";
};
- q6afe: q6afe {
+ q6afe: service@4 {
compatible = "qcom,q6afe";
reg = <APR_SVC_AFE>;
q6afedai: dais {
@@ -3406,13 +3449,13 @@
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
- hdmi@1 {
+ dai@1 {
reg = <1>;
};
};
};
- q6asm: q6asm {
+ q6asm: service@7 {
compatible = "qcom,q6asm";
reg = <APR_SVC_ASM>;
q6asmdai: dais {
@@ -3424,7 +3467,7 @@
};
};
- q6adm: q6adm {
+ q6adm: service@8 {
compatible = "qcom,q6adm";
reg = <APR_SVC_ADM>;
q6routing: routing {
@@ -3504,7 +3547,7 @@
};
saw3: syscon@9a10000 {
- compatible = "qcom,tcsr-msm8996", "syscon";
+ compatible = "syscon";
reg = <0x09a10000 0x1000>;
};
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-21 07:39:54 +0000