diff options
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/mx53.h')
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/mx53.h | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h index 9577cdbf7fad..d7a8e52181ea 100644 --- a/arch/arm/plat-mxc/include/mach/mx53.h +++ b/arch/arm/plat-mxc/include/mach/mx53.h @@ -53,13 +53,13 @@ #define MX53_SPBA0_BASE_ADDR 0x50000000 #define MX53_SPBA0_SIZE SZ_1M -#define MX53_MMC_SDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000) -#define MX53_MMC_SDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000) +#define MX53_ESDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000) +#define MX53_ESDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000) #define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000) -#define MX53_CSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000) +#define MX53_ECSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000) #define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000) -#define MX53_MMC_SDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000) -#define MX53_MMC_SDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000) +#define MX53_ESDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000) +#define MX53_ESDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000) #define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000) #define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000) #define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000) @@ -117,12 +117,12 @@ #define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000) #define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000) #define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000) -#define MX53_CSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000) +#define MX53_ECSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000) #define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000) #define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000) #define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000) #define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000) -#define MX53_CSPI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000) +#define MX53_CSPI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000) #define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000) #define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000) #define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000) @@ -136,7 +136,7 @@ #define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000) #define MX53_MLB_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E4000) #define MX53_SSI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E8000) -#define MX53_MXC_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000) +#define MX53_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000) #define MX53_TVE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F0000) #define MX53_VPU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F4000) #define MX53_SAHARA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F8000) @@ -229,10 +229,10 @@ * Interrupt numbers */ #define MX53_INT_RESV0 0 -#define MX53_INT_MMC_SDHC1 1 -#define MX53_INT_MMC_SDHC2 2 -#define MX53_INT_MMC_SDHC3 3 -#define MX53_INT_MMC_SDHC4 4 +#define MX53_INT_ESDHC1 1 +#define MX53_INT_ESDHC2 2 +#define MX53_INT_ESDHC3 3 +#define MX53_INT_ESDHC4 4 #define MX53_INT_RESV5 5 #define MX53_INT_SDMA 6 #define MX53_INT_IOMUX 7 @@ -264,8 +264,8 @@ #define MX53_INT_UART3 33 #define MX53_INT_RESV34 34 #define MX53_INT_RESV35 35 -#define MX53_INT_CSPI1 36 -#define MX53_INT_CSPI2 37 +#define MX53_INT_ECSPI1 36 +#define MX53_INT_ECSPI2 37 #define MX53_INT_CSPI 38 #define MX53_INT_GPT 39 #define MX53_INT_EPIT1 40 |