diff options
Diffstat (limited to 'arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h')
| -rw-r--r-- | arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h | 211 |
1 files changed, 70 insertions, 141 deletions
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h index b114ecd9a5eb..d5efce2388c7 100644 --- a/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h +++ b/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h @@ -1,7 +1,8 @@ /* - * STMP pinmux register definitions + * stmp37xx: PINCTRL register definitions * * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,143 +18,71 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef _INCLUDE_ASM_ARCH_REGS_PINCTRL_H -#define _INCLUDE_ASM_ARCH_REGS_PINCTRL_H - -#include <mach/stmp3xxx_regs.h> - -#ifndef REGS_PINCTRL_BASE -#define REGS_PINCTRL_BASE (REGS_BASE + 0x00018000) -#endif /* REGS_PINCTRL_BASE */ - -HW_REGISTER(HW_PINCTRL_CTRL, REGS_PINCTRL_BASE, 0) - -#define HW_PINCTRL_MUXSEL0_ADDR (REGS_PINCTRL_BASE + 0x100) -HW_REGISTER(HW_PINCTRL_MUXSEL0, REGS_PINCTRL_BASE, 0x100) -#define HW_PINCTRL_MUXSEL1_ADDR (REGS_PINCTRL_BASE + 0x110) -HW_REGISTER(HW_PINCTRL_MUXSEL1, REGS_PINCTRL_BASE, 0x110) -#define HW_PINCTRL_MUXSEL2_ADDR (REGS_PINCTRL_BASE + 0x120) -HW_REGISTER(HW_PINCTRL_MUXSEL2, REGS_PINCTRL_BASE, 0x120) -#define HW_PINCTRL_MUXSEL3_ADDR (REGS_PINCTRL_BASE + 0x130) -HW_REGISTER(HW_PINCTRL_MUXSEL3, REGS_PINCTRL_BASE, 0x130) -#define BM_PINCTRL_MUXSEL3_BANK1_PIN28 0x03000000 -#define HW_PINCTRL_MUXSEL4_ADDR (REGS_PINCTRL_BASE + 0x140) -HW_REGISTER(HW_PINCTRL_MUXSEL4, REGS_PINCTRL_BASE, 0x140) -#define BM_PINCTRL_MUXSEL4_BANK2_PIN03 0x000000C0 -#define BM_PINCTRL_MUXSEL4_BANK2_PIN04 0x00000300 -#define HW_PINCTRL_MUXSEL5_ADDR (REGS_PINCTRL_BASE + 0x150) -HW_REGISTER(HW_PINCTRL_MUXSEL5, REGS_PINCTRL_BASE, 0x150) -#define HW_PINCTRL_MUXSEL6_ADDR (REGS_PINCTRL_BASE + 0x160) -HW_REGISTER(HW_PINCTRL_MUXSEL6, REGS_PINCTRL_BASE, 0x160) -#define HW_PINCTRL_MUXSEL7_ADDR (REGS_PINCTRL_BASE + 0x170) -HW_REGISTER(HW_PINCTRL_MUXSEL7, REGS_PINCTRL_BASE, 0x170) - -HW_REGISTER(HW_PINCTRL_DRIVE0, REGS_PINCTRL_BASE, 0x200) -#define HW_PINCTRL_DRIVE0_ADDR (REGS_PINCTRL_BASE + 0x200) -HW_REGISTER(HW_PINCTRL_DRIVE1, REGS_PINCTRL_BASE, 0x210) -#define HW_PINCTRL_DRIVE1_ADDR (REGS_PINCTRL_BASE + 0x210) -HW_REGISTER(HW_PINCTRL_DRIVE2, REGS_PINCTRL_BASE, 0x220) -#define HW_PINCTRL_DRIVE2_ADDR (REGS_PINCTRL_BASE + 0x220) -HW_REGISTER(HW_PINCTRL_DRIVE3, REGS_PINCTRL_BASE, 0x230) -#define HW_PINCTRL_DRIVE3_ADDR (REGS_PINCTRL_BASE + 0x230) -HW_REGISTER(HW_PINCTRL_DRIVE4, REGS_PINCTRL_BASE, 0x240) -#define HW_PINCTRL_DRIVE4_ADDR (REGS_PINCTRL_BASE + 0x240) -HW_REGISTER(HW_PINCTRL_DRIVE5, REGS_PINCTRL_BASE, 0x250) -#define HW_PINCTRL_DRIVE5_ADDR (REGS_PINCTRL_BASE + 0x250) -HW_REGISTER(HW_PINCTRL_DRIVE6, REGS_PINCTRL_BASE, 0x260) -#define HW_PINCTRL_DRIVE6_ADDR (REGS_PINCTRL_BASE + 0x260) -HW_REGISTER(HW_PINCTRL_DRIVE7, REGS_PINCTRL_BASE, 0x270) -#define HW_PINCTRL_DRIVE7_ADDR (REGS_PINCTRL_BASE + 0x270) -HW_REGISTER(HW_PINCTRL_DRIVE8, REGS_PINCTRL_BASE, 0x280) -#define HW_PINCTRL_DRIVE8_ADDR (REGS_PINCTRL_BASE + 0x280) -HW_REGISTER(HW_PINCTRL_DRIVE9, REGS_PINCTRL_BASE, 0x290) -#define HW_PINCTRL_DRIVE9_ADDR (REGS_PINCTRL_BASE + 0x290) -HW_REGISTER(HW_PINCTRL_DRIVE10, REGS_PINCTRL_BASE, 0x2a0) -#define HW_PINCTRL_DRIVE10_ADDR (REGS_PINCTRL_BASE + 0x2a0) -HW_REGISTER(HW_PINCTRL_DRIVE11, REGS_PINCTRL_BASE, 0x2b0) -#define HW_PINCTRL_DRIVE11_ADDR (REGS_PINCTRL_BASE + 0x2b0) -HW_REGISTER(HW_PINCTRL_DRIVE12, REGS_PINCTRL_BASE, 0x2c0) -#define HW_PINCTRL_DRIVE12_ADDR (REGS_PINCTRL_BASE + 0x2c0) -HW_REGISTER(HW_PINCTRL_DRIVE13, REGS_PINCTRL_BASE, 0x2d0) -#define HW_PINCTRL_DRIVE13_ADDR (REGS_PINCTRL_BASE + 0x2d0) -HW_REGISTER(HW_PINCTRL_DRIVE14, REGS_PINCTRL_BASE, 0x2e0) -#define HW_PINCTRL_DRIVE14_ADDR (REGS_PINCTRL_BASE + 0x2e0) - - -HW_REGISTER(HW_PINCTRL_PULL0, REGS_PINCTRL_BASE, 0x300) -#define HW_PINCTRL_PULL0_ADDR (REGS_PINCTRL_BASE + 0x300) -#define BM_PINCTRL_PULL0_BANK0_PIN01 0x00000002 -#define BM_PINCTRL_PULL0_BANK0_PIN02 0x00000004 -#define BM_PINCTRL_PULL0_BANK0_PIN03 0x00000008 -#define BM_PINCTRL_PULL0_BANK0_PIN04 0x00000010 -#define BM_PINCTRL_PULL0_BANK0_PIN20 0x00100000 -HW_REGISTER(HW_PINCTRL_PULL1, REGS_PINCTRL_BASE, 0x310) -#define HW_PINCTRL_PULL1_ADDR (REGS_PINCTRL_BASE + 0x310) -#define BM_PINCTRL_PULL1_BANK1_PIN22 0x00400000 -#define BM_PINCTRL_PULL1_BANK1_PIN24 0x01000000 -#define BM_PINCTRL_PULL1_BANK1_PIN25 0x02000000 -#define BM_PINCTRL_PULL1_BANK1_PIN26 0x04000000 -#define BM_PINCTRL_PULL1_BANK1_PIN27 0x08000000 -HW_REGISTER(HW_PINCTRL_PULL2, REGS_PINCTRL_BASE, 0x320) -#define HW_PINCTRL_PULL2_ADDR (REGS_PINCTRL_BASE + 0x320) -HW_REGISTER(HW_PINCTRL_PULL3, REGS_PINCTRL_BASE, 0x330) -#define HW_PINCTRL_PULL3_ADDR (REGS_PINCTRL_BASE + 0x330) - -#define HW_PINCTRL_DOUT0_ADDR (REGS_PINCTRL_BASE + 0x400) -HW_REGISTER(HW_PINCTRL_DOUT0, REGS_PINCTRL_BASE, 0x400) -#define HW_PINCTRL_DOUT1_ADDR (REGS_PINCTRL_BASE + 0x410) -HW_REGISTER(HW_PINCTRL_DOUT1, REGS_PINCTRL_BASE, 0x410) -#define HW_PINCTRL_DOUT2_ADDR (REGS_PINCTRL_BASE + 0x420) -HW_REGISTER(HW_PINCTRL_DOUT2, REGS_PINCTRL_BASE, 0x420) - -#define HW_PINCTRL_DIN0_ADDR (REGS_PINCTRL_BASE + 0x500) -HW_REGISTER_RO(HW_PINCTRL_DIN0, REGS_PINCTRL_BASE, 0x500) -#define HW_PINCTRL_DIN1_ADDR (REGS_PINCTRL_BASE + 0x510) -HW_REGISTER_RO(HW_PINCTRL_DIN1, REGS_PINCTRL_BASE, 0x510) -#define HW_PINCTRL_DIN2_ADDR (REGS_PINCTRL_BASE + 0x520) -HW_REGISTER_RO(HW_PINCTRL_DIN2, REGS_PINCTRL_BASE, 0x520) - -#define HW_PINCTRL_DOE0_ADDR (REGS_PINCTRL_BASE + 0x600) -HW_REGISTER(HW_PINCTRL_DOE0, REGS_PINCTRL_BASE, 0x600) -#define HW_PINCTRL_DOE1_ADDR (REGS_PINCTRL_BASE + 0x610) -HW_REGISTER(HW_PINCTRL_DOE1, REGS_PINCTRL_BASE, 0x610) -#define HW_PINCTRL_DOE2_ADDR (REGS_PINCTRL_BASE + 0x620) -HW_REGISTER(HW_PINCTRL_DOE2, REGS_PINCTRL_BASE, 0x620) - -HW_REGISTER(HW_PINCTRL_PIN2IRQ0, REGS_PINCTRL_BASE, 0x700) -#define HW_PINCTRL_PIN2IRQ0_ADDR (REGS_PINCTRL_BASE + 0x700) -HW_REGISTER(HW_PINCTRL_PIN2IRQ1, REGS_PINCTRL_BASE, 0x710) -#define HW_PINCTRL_PIN2IRQ1_ADDR (REGS_PINCTRL_BASE + 0x710) -HW_REGISTER(HW_PINCTRL_PIN2IRQ2, REGS_PINCTRL_BASE, 0x720) -#define HW_PINCTRL_PIN2IRQ2_ADDR (REGS_PINCTRL_BASE + 0x720) - -HW_REGISTER(HW_PINCTRL_IRQEN0, REGS_PINCTRL_BASE, 0x800) -#define HW_PINCTRL_IRQEN0_ADDR (REGS_PINCTRL_BASE + 0x800) -HW_REGISTER(HW_PINCTRL_IRQEN1, REGS_PINCTRL_BASE, 0x810) -#define HW_PINCTRL_IRQEN1_ADDR (REGS_PINCTRL_BASE + 0x810) -HW_REGISTER(HW_PINCTRL_IRQEN2, REGS_PINCTRL_BASE, 0x820) -#define HW_PINCTRL_IRQEN2_ADDR (REGS_PINCTRL_BASE + 0x820) - -HW_REGISTER(HW_PINCTRL_IRQLEVEL0, REGS_PINCTRL_BASE, 0x900) -#define HW_PINCTRL_IRQLEVEL0_ADDR (REGS_PINCTRL_BASE + 0x900) -HW_REGISTER(HW_PINCTRL_IRQLEVEL1, REGS_PINCTRL_BASE, 0x910) -#define HW_PINCTRL_IRQLEVEL1_ADDR (REGS_PINCTRL_BASE + 0x910) -HW_REGISTER(HW_PINCTRL_IRQLEVEL2, REGS_PINCTRL_BASE, 0x920) -#define HW_PINCTRL_IRQLEVEL2_ADDR (REGS_PINCTRL_BASE + 0x920) - -HW_REGISTER(HW_PINCTRL_IRQPOL0, REGS_PINCTRL_BASE, 0xA00) -#define HW_PINCTRL_IRQPOL0_ADDR (REGS_PINCTRL_BASE + 0xa00) -HW_REGISTER(HW_PINCTRL_IRQPOL1, REGS_PINCTRL_BASE, 0xA10) -#define HW_PINCTRL_IRQPOL1_ADDR (REGS_PINCTRL_BASE + 0xa10) -HW_REGISTER(HW_PINCTRL_IRQPOL2, REGS_PINCTRL_BASE, 0xA20) -#define HW_PINCTRL_IRQPOL2_ADDR (REGS_PINCTRL_BASE + 0xa20) - -HW_REGISTER(HW_PINCTRL_IRQSTAT0, REGS_PINCTRL_BASE, 0xB00) -#define HW_PINCTRL_IRQSTAT0_ADDR (REGS_PINCTRL_BASE + 0xb00) -HW_REGISTER(HW_PINCTRL_IRQSTAT1, REGS_PINCTRL_BASE, 0xB10) -#define HW_PINCTRL_IRQSTAT1_ADDR (REGS_PINCTRL_BASE + 0xb10) -HW_REGISTER(HW_PINCTRL_IRQSTAT2, REGS_PINCTRL_BASE, 0xB20) -#define HW_PINCTRL_IRQSTAT2_ADDR (REGS_PINCTRL_BASE + 0xb20) - -#endif /* _INCLUDE_ASM_ARCH_REGS_PINCTRL_H */ - +#ifndef _MACH_REGS_PINCTRL +#define _MACH_REGS_PINCTRL + +#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000) + +#define HW_PINCTRL_MUXSEL0 0x100 +#define HW_PINCTRL_MUXSEL1 0x110 +#define HW_PINCTRL_MUXSEL2 0x120 +#define HW_PINCTRL_MUXSEL3 0x130 +#define HW_PINCTRL_MUXSEL4 0x140 +#define HW_PINCTRL_MUXSEL5 0x150 +#define HW_PINCTRL_MUXSEL6 0x160 +#define HW_PINCTRL_MUXSEL7 0x170 + +#define HW_PINCTRL_DRIVE0 0x200 +#define HW_PINCTRL_DRIVE1 0x210 +#define HW_PINCTRL_DRIVE2 0x220 +#define HW_PINCTRL_DRIVE3 0x230 +#define HW_PINCTRL_DRIVE4 0x240 +#define HW_PINCTRL_DRIVE5 0x250 +#define HW_PINCTRL_DRIVE6 0x260 +#define HW_PINCTRL_DRIVE7 0x270 +#define HW_PINCTRL_DRIVE8 0x280 +#define HW_PINCTRL_DRIVE9 0x290 +#define HW_PINCTRL_DRIVE10 0x2A0 +#define HW_PINCTRL_DRIVE11 0x2B0 +#define HW_PINCTRL_DRIVE12 0x2C0 +#define HW_PINCTRL_DRIVE13 0x2D0 +#define HW_PINCTRL_DRIVE14 0x2E0 + +#define HW_PINCTRL_PULL0 0x300 +#define HW_PINCTRL_PULL1 0x310 +#define HW_PINCTRL_PULL2 0x320 +#define HW_PINCTRL_PULL3 0x330 + +#define HW_PINCTRL_DOUT0 0x400 +#define HW_PINCTRL_DOUT1 0x410 +#define HW_PINCTRL_DOUT2 0x420 + +#define HW_PINCTRL_DIN0 0x500 +#define HW_PINCTRL_DIN1 0x510 +#define HW_PINCTRL_DIN2 0x520 + +#define HW_PINCTRL_DOE0 0x600 +#define HW_PINCTRL_DOE1 0x610 +#define HW_PINCTRL_DOE2 0x620 + +#define HW_PINCTRL_PIN2IRQ0 0x700 +#define HW_PINCTRL_PIN2IRQ1 0x710 +#define HW_PINCTRL_PIN2IRQ2 0x720 + +#define HW_PINCTRL_IRQEN0 0x800 +#define HW_PINCTRL_IRQEN1 0x810 +#define HW_PINCTRL_IRQEN2 0x820 + +#define HW_PINCTRL_IRQLEVEL0 0x900 +#define HW_PINCTRL_IRQLEVEL1 0x910 +#define HW_PINCTRL_IRQLEVEL2 0x920 + +#define HW_PINCTRL_IRQPOL0 0xA00 +#define HW_PINCTRL_IRQPOL1 0xA10 +#define HW_PINCTRL_IRQPOL2 0xA20 + +#define HW_PINCTRL_IRQSTAT0 0xB00 +#define HW_PINCTRL_IRQSTAT1 0xB10 +#define HW_PINCTRL_IRQSTAT2 0xB20 + +#endif |