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Diffstat (limited to 'arch/arm/mach-at91/clock.c')
-rw-r--r--arch/arm/mach-at91/clock.c30
1 files changed, 23 insertions, 7 deletions
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index da841885d01c..6b2630a92f71 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -75,7 +75,7 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
|| cpu_is_at91sam9g45() \
|| cpu_is_at91sam9x5() \
- || cpu_is_at91sam9n12()))
+ || cpu_is_sama5d3()))
#define cpu_has_upll() (cpu_is_at91sam9g45() \
|| cpu_is_at91sam9x5() \
@@ -489,7 +489,7 @@ static int at91_clk_show(struct seq_file *s, void *unused)
seq_printf(s, "UCKR = %8x\n", uckr);
}
seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
- if (cpu_has_upll())
+ if (cpu_has_upll() || cpu_is_at91sam9n12())
seq_printf(s, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB));
seq_printf(s, "SR = %8x\n", sr);
@@ -614,6 +614,8 @@ static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
{
if (pll == &pllb && (reg & AT91_PMC_USB96M))
return freq / 2;
+ else if (pll == &utmi_clk || cpu_is_at91sam9n12())
+ return freq / (1 + ((reg & AT91_PMC_OHCIUSBDIV) >> 8));
else
return freq;
}
@@ -683,6 +685,8 @@ static struct clk *const standard_pmc_clocks[] __initconst = {
/* PLLB generated USB full speed clock init */
static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
{
+ unsigned int reg;
+
/*
* USB clock init: choose 48 MHz PLLB value,
* disable 48MHz clock during usb peripheral suspend.
@@ -691,22 +695,35 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
*/
uhpck.parent = &pllb;
- at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
+ reg = at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2);
pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
if (cpu_is_at91rm9200()) {
+ reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
uhpck.pmc_mask = AT91RM9200_PMC_UHP;
udpck.pmc_mask = AT91RM9200_PMC_UDP;
at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
} else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
cpu_is_at91sam9g10()) {
+ reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
+ uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
+ udpck.pmc_mask = AT91SAM926x_PMC_UDP;
+ } else if (cpu_is_at91sam9n12()) {
+ /* Divider for USB clock is in USB clock register for 9n12 */
+ reg = AT91_PMC_USBS_PLLB;
+
+ /* For PLLB output 96M, set usb divider 2 (USBDIV + 1) */
+ reg |= AT91_PMC_OHCIUSBDIV_2;
+ at91_pmc_write(AT91_PMC_USB, reg);
+
+ /* Still setup masks */
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
udpck.pmc_mask = AT91SAM926x_PMC_UDP;
}
at91_pmc_write(AT91_CKGR_PLLBR, 0);
- udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
- uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
+ udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
+ uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
}
/* UPLL generated USB full speed clock init */
@@ -725,8 +742,7 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
/* Now set uhpck values */
uhpck.parent = &utmi_clk;
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
- uhpck.rate_hz = utmi_clk.rate_hz;
- uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
+ uhpck.rate_hz = at91_usb_rate(&utmi_clk, utmi_clk.rate_hz, usbr);
}
static int __init at91_pmc_init(unsigned long main_clock)