diff options
Diffstat (limited to 'arch/arm/boot/dts/stihxxx-b2120.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/stihxxx-b2120.dtsi | 46 |
1 files changed, 44 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi index ad21a4293a33..133375bc8aa5 100644 --- a/arch/arm/boot/dts/stihxxx-b2120.dtsi +++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi @@ -6,6 +6,9 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#include <dt-bindings/clock/stih407-clks.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/media/c8sectpfe.h> / { soc { sbc_serial0: serial@9530000 { @@ -35,12 +38,18 @@ status = "okay"; }; - i2c@9842000 { + ssc2: i2c@9842000 { status = "okay"; + clock-frequency = <100000>; + st,i2c-min-scl-pulse-width-us = <0>; + st,i2c-min-sda-pulse-width-us = <5>; }; - i2c@9843000 { + ssc3: i2c@9843000 { status = "okay"; + clock-frequency = <100000>; + st,i2c-min-scl-pulse-width-us = <0>; + st,i2c-min-sda-pulse-width-us = <5>; }; i2c@9844000 { @@ -93,5 +102,38 @@ phy-mode = "rgmii"; fixed-link = <0 1 1000 0 0>; }; + + demux@08a20000 { + compatible = "st,stih407-c8sectpfe"; + status = "okay"; + reg = <0x08a20000 0x10000>, + <0x08a00000 0x4000>; + reg-names = "c8sectpfe", "c8sectpfe-ram"; + interrupts = <GIC_SPI 34 IRQ_TYPE_NONE>, + <GIC_SPI 35 IRQ_TYPE_NONE>; + interrupt-names = "c8sectpfe-error-irq", + "c8sectpfe-idle-irq"; + pinctrl-0 = <&pinctrl_tsin0_serial>; + pinctrl-1 = <&pinctrl_tsin0_parallel>; + pinctrl-2 = <&pinctrl_tsin3_serial>; + pinctrl-3 = <&pinctrl_tsin4_serial_alt3>; + pinctrl-4 = <&pinctrl_tsin5_serial_alt1>; + pinctrl-names = "tsin0-serial", + "tsin0-parallel", + "tsin3-serial", + "tsin4-serial", + "tsin5-serial"; + clocks = <&clk_s_c0_flexgen CLK_PROC_STFE>; + clock-names = "c8sectpfe"; + + /* tsin0 is TSA on NIMA */ + tsin0: port@0 { + tsin-num = <0>; + serial-not-parallel; + i2c-bus = <&ssc2>; + reset-gpios = <&pio15 4 GPIO_ACTIVE_HIGH>; + dvb-card = <STV0367_TDA18212_NIMA_1>; + }; + }; }; }; |