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-* Allwinner A1X Pin Controller
-
-The pins controlled by sunXi pin controller are organized in banks,
-each bank has 32 pins. Each pin has 7 multiplexing functions, with
-the first two functions being GPIO in and out. The configuration on
-the pins includes drive strength and pull-up.
-
-Required properties:
-- compatible: Should be one of the following (depending on your SoC):
- "allwinner,sun4i-a10-pinctrl"
- "allwinner,sun5i-a10s-pinctrl"
- "allwinner,sun5i-a13-pinctrl"
- "allwinner,sun6i-a31-pinctrl"
- "allwinner,sun6i-a31s-pinctrl"
- "allwinner,sun6i-a31-r-pinctrl"
- "allwinner,sun7i-a20-pinctrl"
- "allwinner,sun8i-a23-pinctrl"
- "allwinner,sun8i-a23-r-pinctrl"
- "allwinner,sun8i-a33-pinctrl"
- "allwinner,sun9i-a80-pinctrl"
- "allwinner,sun9i-a80-r-pinctrl"
- "allwinner,sun8i-a83t-pinctrl"
- "allwinner,sun8i-a83t-r-pinctrl"
- "allwinner,sun8i-h3-pinctrl"
- "allwinner,sun8i-h3-r-pinctrl"
- "allwinner,sun8i-r40-pinctrl"
- "allwinner,sun8i-v3-pinctrl"
- "allwinner,sun8i-v3s-pinctrl"
- "allwinner,sun50i-a64-pinctrl"
- "allwinner,sun50i-a64-r-pinctrl"
- "allwinner,sun50i-h5-pinctrl"
- "allwinner,sun50i-h6-pinctrl"
- "allwinner,sun50i-h6-r-pinctrl"
- "allwinner,suniv-f1c100s-pinctrl"
- "nextthing,gr8-pinctrl"
-
-- reg: Should contain the register physical address and length for the
- pin controller.
-
-- clocks: phandle to the clocks feeding the pin controller:
- - "apb": the gated APB parent clock
- - "hosc": the high frequency oscillator in the system
- - "losc": the low frequency oscillator in the system
-
-Note: For backward compatibility reasons, the hosc and losc clocks are only
-required if you need to use the optional input-debounce property. Any new
-device tree should set them.
-
-Each pin bank, depending on the SoC, can have an associated regulator:
-
-- vcc-pa-supply: for the A10, A20, A31, A31s, A80 and R40 SoCs
-- vcc-pb-supply: for the A31, A31s, A80 and V3s SoCs
-- vcc-pc-supply: for the A10, A20, A31, A31s, A64, A80, H5, R40 and V3s SoCs
-- vcc-pd-supply: for the A23, A31, A31s, A64, A80, A83t, H3, H5 and R40 SoCs
-- vcc-pe-supply: for the A10, A20, A31, A31s, A64, A80, R40 and V3s SoCs
-- vcc-pf-supply: for the A10, A20, A31, A31s, A80, R40 and V3s SoCs
-- vcc-pg-supply: for the A10, A20, A31, A31s, A64, A80, H3, H5, R40 and V3s SoCs
-- vcc-ph-supply: for the A31, A31s and A80 SoCs
-- vcc-pl-supply: for the r-pinctrl of the A64, A80 and A83t SoCs
-- vcc-pm-supply: for the r-pinctrl of the A31, A31s and A80 SoCs
-
-Optional properties:
- - input-debounce: Array of debouncing periods in microseconds. One period per
- irq bank found in the controller. 0 if no setup required.
-
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices.
-
-A pinctrl node should contain at least one subnodes representing the
-pinctrl groups available on the machine. Each subnode will list the
-pins it needs, and how they should be configured, with regard to muxer
-configuration, drive strength and pullups. If one of these options is
-not set, its actual value will be unspecified.
-
-Allwinner A1X Pin Controller supports the generic pin multiplexing and
-configuration bindings. For details on each properties, you can refer to
- ./pinctrl-bindings.txt.
-
-Required sub-node properties:
- - pins
- - function
-
-Optional sub-node properties:
- - bias-disable
- - bias-pull-up
- - bias-pull-down
- - drive-strength
-
-*** Deprecated pin configuration and multiplexing binding
-
-Required subnode-properties:
-
-- allwinner,pins: List of strings containing the pin name.
-- allwinner,function: Function to mux the pins listed above to.
-
-Optional subnode-properties:
-- allwinner,drive: Integer. Represents the current sent to the pin
- 0: 10 mA
- 1: 20 mA
- 2: 30 mA
- 3: 40 mA
-- allwinner,pull: Integer.
- 0: No resistor
- 1: Pull-up resistor
- 2: Pull-down resistor
-
-Examples:
-
-pio: pinctrl@1c20800 {
- compatible = "allwinner,sun5i-a13-pinctrl";
- reg = <0x01c20800 0x400>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- uart1_pins_a: uart1@0 {
- allwinner,pins = "PE10", "PE11";
- allwinner,function = "uart1";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
- };
-
- uart1_pins_b: uart1@1 {
- allwinner,pins = "PG3", "PG4";
- allwinner,function = "uart1";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
- };
-};
-
-
-GPIO and interrupt controller
------------------------------
-
-This hardware also acts as a GPIO controller and an interrupt
-controller.
-
-Consumers that would want to refer to one or the other (or both)
-should provide through the usual *-gpios and interrupts properties a
-cell with 3 arguments, first the number of the bank, then the pin
-inside that bank, and finally the flags for the GPIO/interrupts.
-
-Example:
-
-xio: gpio@38 {
- compatible = "nxp,pcf8574a";
- reg = <0x38>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-parent = <&pio>;
- interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <2>;
-};
-
-reg_usb1_vbus: usb1-vbus {
- compatible = "regulator-fixed";
- regulator-name = "usb1-vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>;
-};