diff options
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5433.c | 10 | ||||
| -rw-r--r-- | include/dt-bindings/clock/exynos5433.h | 6 |
2 files changed, 8 insertions, 8 deletions
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 1a005c1f7c4b..387e3e39e635 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -661,6 +661,11 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = { GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b", ENABLE_SCLK_TOP_CAM1, 0, 0, 0), + /* ENABLE_SCLK_TOP_DISP */ + GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp", + "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0, + CLK_IGNORE_UNUSED, 0), + /* ENABLE_SCLK_TOP_FSYS */ GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100", ENABLE_SCLK_TOP_FSYS, 7, 0, 0), @@ -1521,11 +1526,6 @@ static struct samsung_gate_clock mif_gate_clks[] __initdata = { ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0), GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll", ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), - - /* ENABLE_SCLK_TOP_DISP */ - GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp", - "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0, - CLK_IGNORE_UNUSED, 0), }; static struct samsung_cmu_info mif_cmu_info __initdata = { diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h index 4853bc598b57..5bd80d5ecd0f 100644 --- a/include/dt-bindings/clock/exynos5433.h +++ b/include/dt-bindings/clock/exynos5433.h @@ -189,8 +189,9 @@ #define CLK_SCLK_ISP_UART_CAM1 250 #define CLK_SCLK_ISP_SPI1_CAM1 251 #define CLK_SCLK_ISP_SPI0_CAM1 252 +#define CLK_SCLK_HDMI_SPDIF_DISP 253 -#define TOP_NR_CLK 253 +#define TOP_NR_CLK 254 /* CMU_CPIF */ #define CLK_FOUT_MPHY_PLL 1 @@ -397,9 +398,8 @@ #define CLK_SCLK_BUS_PLL 198 #define CLK_SCLK_BUS_PLL_APOLLO 199 #define CLK_SCLK_BUS_PLL_ATLAS 200 -#define CLK_SCLK_HDMI_SPDIF_DISP 201 -#define MIF_NR_CLK 202 +#define MIF_NR_CLK 201 /* CMU_PERIC */ #define CLK_PCLK_SPI2 1 |