diff options
| -rw-r--r-- | arch/arm/mach-shmobile/smp-emev2.c | 22 | ||||
| -rw-r--r-- | arch/arm/mach-shmobile/smp-r8a7779.c | 25 | ||||
| -rw-r--r-- | arch/arm/mach-shmobile/smp-sh73a0.c | 23 | ||||
| -rw-r--r-- | drivers/sh/clk/cpg.c | 1 |
4 files changed, 63 insertions, 8 deletions
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index 535426c306bd..f67456286280 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c @@ -32,8 +32,24 @@ #define EMEV2_SCU_BASE 0x1e000000 +static DEFINE_SPINLOCK(scu_lock); static void __iomem *scu_base; +static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) +{ + unsigned long tmp; + + /* we assume this code is running on a different cpu + * than the one that is changing coherency setting */ + spin_lock(&scu_lock); + tmp = readl(scu_base + 8); + tmp &= ~clr; + tmp |= set; + writel(tmp, scu_base + 8); + spin_unlock(&scu_lock); + +} + static unsigned int __init emev2_get_core_count(void) { if (!scu_base) { @@ -79,7 +95,7 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct * cpu = cpu_logical_map(cpu); /* enable cache coherency */ - scu_power_mode(scu_base, 0); + modify_scu_cpu_psr(0, 3 << (cpu * 8)); /* Tell ROM loader about our vector (in headsmp.S) */ emev2_set_boot_vector(__pa(shmobile_secondary_vector)); @@ -90,10 +106,12 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct * static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) { + int cpu = cpu_logical_map(0); + scu_enable(scu_base); /* enable cache coherency on CPU0 */ - scu_power_mode(scu_base, 0); + modify_scu_cpu_psr(0, 3 << (cpu * 8)); } static void __init emev2_smp_init_cpus(void) diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index 9def0f22bf22..2ce6af9a6a37 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -61,6 +61,9 @@ static void __iomem *scu_base_addr(void) return (void __iomem *)0xf0000000; } +static DEFINE_SPINLOCK(scu_lock); +static unsigned long tmp; + #ifdef CONFIG_HAVE_ARM_TWD static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); @@ -70,6 +73,20 @@ void __init r8a7779_register_twd(void) } #endif +static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) +{ + void __iomem *scu_base = scu_base_addr(); + + spin_lock(&scu_lock); + tmp = __raw_readl(scu_base + 8); + tmp &= ~clr; + tmp |= set; + spin_unlock(&scu_lock); + + /* disable cache coherency after releasing the lock */ + __raw_writel(tmp, scu_base + 8); +} + static unsigned int __init r8a7779_get_core_count(void) { void __iomem *scu_base = scu_base_addr(); @@ -85,7 +102,7 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu) cpu = cpu_logical_map(cpu); /* disable cache coherency */ - scu_power_mode(scu_base_addr(), 3); + modify_scu_cpu_psr(3 << (cpu * 8), 0); if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) ch = r8a7779_ch_cpu[cpu]; @@ -128,7 +145,7 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct cpu = cpu_logical_map(cpu); /* enable cache coherency */ - scu_power_mode(scu_base_addr(), 0); + modify_scu_cpu_psr(0, 3 << (cpu * 8)); if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) ch = r8a7779_ch_cpu[cpu]; @@ -141,13 +158,15 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) { + int cpu = cpu_logical_map(0); + scu_enable(scu_base_addr()); /* Map the reset vector (in headsmp.S) */ __raw_writel(__pa(shmobile_secondary_vector), AVECR); /* enable cache coherency on CPU0 */ - scu_power_mode(scu_base_addr(), 0); + modify_scu_cpu_psr(0, 3 << (cpu * 8)); r8a7779_pm_init(); diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 96ddb97babbe..624f00f70abf 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -41,6 +41,9 @@ static void __iomem *scu_base_addr(void) return (void __iomem *)0xf0000000; } +static DEFINE_SPINLOCK(scu_lock); +static unsigned long tmp; + #ifdef CONFIG_HAVE_ARM_TWD static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); void __init sh73a0_register_twd(void) @@ -49,6 +52,20 @@ void __init sh73a0_register_twd(void) } #endif +static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) +{ + void __iomem *scu_base = scu_base_addr(); + + spin_lock(&scu_lock); + tmp = __raw_readl(scu_base + 8); + tmp &= ~clr; + tmp |= set; + spin_unlock(&scu_lock); + + /* disable cache coherency after releasing the lock */ + __raw_writel(tmp, scu_base + 8); +} + static unsigned int __init sh73a0_get_core_count(void) { void __iomem *scu_base = scu_base_addr(); @@ -66,7 +83,7 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct cpu = cpu_logical_map(cpu); /* enable cache coherency */ - scu_power_mode(scu_base_addr(), 0); + modify_scu_cpu_psr(0, 3 << (cpu * 8)); if (((__raw_readl(PSTR) >> (4 * cpu)) & 3) == 3) __raw_writel(1 << cpu, WUPCR); /* wake up */ @@ -78,6 +95,8 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) { + int cpu = cpu_logical_map(0); + scu_enable(scu_base_addr()); /* Map the reset vector (in headsmp.S) */ @@ -85,7 +104,7 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) __raw_writel(__pa(shmobile_secondary_vector), SBAR); /* enable cache coherency on CPU0 */ - scu_power_mode(scu_base_addr(), 0); + modify_scu_cpu_psr(0, 3 << (cpu * 8)); } static void __init sh73a0_smp_init_cpus(void) diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c index b3dc44146ca0..5aedcdf4ac5c 100644 --- a/drivers/sh/clk/cpg.c +++ b/drivers/sh/clk/cpg.c @@ -401,7 +401,6 @@ static int fsidiv_enable(struct clk *clk) static int fsidiv_set_rate(struct clk *clk, unsigned long rate) { - u32 val; int idx; idx = (clk->parent->rate / rate) & 0xffff; |