diff options
| -rw-r--r-- | arch/arm/boot/dts/gemini-dlink-dir-685.dts | 35 | ||||
| -rw-r--r-- | arch/arm/boot/dts/gemini-sq201.dts | 31 |
2 files changed, 41 insertions, 25 deletions
diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts index 502a361d1fe9..318e9b2ba7dc 100644 --- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts +++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts @@ -64,7 +64,6 @@ gpio-sck = <&gpio1 5 GPIO_ACTIVE_HIGH>; gpio-miso = <&gpio1 8 GPIO_ACTIVE_HIGH>; gpio-mosi = <&gpio1 7 GPIO_ACTIVE_HIGH>; - /* Collides with pflash CE1, not so cool */ cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; num-chipselects = <1>; @@ -253,15 +252,18 @@ soc { flash@30000000 { /* - * Flash access is by default disabled, because it - * collides with the Chip Enable signal for the display - * panel, that reuse the parallel flash Chip Select 1 - * (CS1). Enabling flash makes graphics stop working. - * - * We might be able to hack around this by letting - * GPIO poke around in the flash controller registers. + * Flash access collides with the Chip Enable signal for + * the display panel, that reuse the parallel flash Chip + * Select 1 (CS1). We switch the pin control state so we + * enable these pins for flash access only when we need + * then, and when disabled they can be used for GPIO which + * is what the display panel needs. */ - /* status = "okay"; */ + status = "okay"; + pinctrl-names = "enabled", "disabled"; + pinctrl-0 = <&pflash_default_pins>; + pinctrl-1 = <&pflash_disabled_pins>; + /* 32MB of flash */ reg = <0x30000000 0x02000000>; @@ -327,7 +329,6 @@ "gpio0cgrp", "gpio0egrp", "gpio0fgrp", - "gpio0ggrp", "gpio0hgrp"; }; }; @@ -342,6 +343,18 @@ groups = "gpio1bgrp"; }; }; + /* + * These GPIO groups will be mapped in over some + * of the flash pins when the flash is not in + * active use. + */ + pflash_disabled_pins: pinctrl-pflash-disabled { + mux { + function = "gpio0"; + groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp", + "gpio0kgrp"; + }; + }; pinctrl-gmii { mux { function = "gmii"; @@ -430,7 +443,7 @@ }; display-controller@6a000000 { - status = "okay"; + status = "disabled"; port@0 { reg = <0>; diff --git a/arch/arm/boot/dts/gemini-sq201.dts b/arch/arm/boot/dts/gemini-sq201.dts index 3787cf3763c4..af4be6ecb02c 100644 --- a/arch/arm/boot/dts/gemini-sq201.dts +++ b/arch/arm/boot/dts/gemini-sq201.dts @@ -41,14 +41,12 @@ compatible = "gpio-leds"; led-green-info { label = "sq201:green:info"; - /* Conflict with parallel flash */ gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; default-state = "on"; linux,default-trigger = "heartbeat"; }; led-green-usb { label = "sq201:green:usb"; - /* Conflict with parallel and NAND flash */ gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "usb-host"; @@ -126,15 +124,10 @@ soc { flash@30000000 { - /* - * Flash access can be enabled, with the side effect - * of disabling access to GPIO LED on GPIO0[20] which - * reuse one of the parallel flash chip select lines. - * Also the default firmware on the machine has the - * problem that since it uses the flash, the two LEDS - * on the right become numb. - */ - /* status = "okay"; */ + status = "okay"; + pinctrl-names = "enabled", "disabled"; + pinctrl-0 = <&pflash_default_pins>; + pinctrl-1 = <&pflash_disabled_pins>; /* 16MB of flash */ reg = <0x30000000 0x01000000>; @@ -184,9 +177,7 @@ mux { function = "gpio0"; groups = "gpio0fgrp", - "gpio0ggrp", - "gpio0hgrp", - "gpio0kgrp"; + "gpio0hgrp"; }; }; /* @@ -199,6 +190,18 @@ groups = "gpio1dgrp"; }; }; + /* + * These GPIO groups will be mapped in over some + * of the flash pins when the flash is not in + * active use. + */ + pflash_disabled_pins: pinctrl-pflash-disabled { + mux { + function = "gpio0"; + groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp", + "gpio0kgrp"; + }; + }; pinctrl-gmii { mux { function = "gmii"; |