diff options
| -rw-r--r-- | Documentation/ABI/testing/sysfs-driver-intel-m10-bmc | 15 | ||||
| -rw-r--r-- | drivers/mfd/Kconfig | 13 | ||||
| -rw-r--r-- | drivers/mfd/Makefile | 1 | ||||
| -rw-r--r-- | drivers/mfd/intel-m10-bmc.c | 164 | ||||
| -rw-r--r-- | include/linux/mfd/intel-m10-bmc.h | 65 |
5 files changed, 258 insertions, 0 deletions
diff --git a/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc b/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc new file mode 100644 index 000000000000..979a2d62513f --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc @@ -0,0 +1,15 @@ +What: /sys/bus/spi/devices/.../bmc_version +Date: June 2020 +KernelVersion: 5.10 +Contact: Xu Yilun <yilun.xu@intel.com> +Description: Read only. Returns the hardware build version of Intel + MAX10 BMC chip. + Format: "0x%x". + +What: /sys/bus/spi/devices/.../bmcfw_version +Date: June 2020 +KernelVersion: 5.10 +Contact: Xu Yilun <yilun.xu@intel.com> +Description: Read only. Returns the firmware version of Intel MAX10 + BMC chip. + Format: "0x%x". diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index e1d3bf77b245..2ba269429e25 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -2151,5 +2151,18 @@ config SGI_MFD_IOC3 If you have an SGI Origin, Octane, or a PCI IOC3 card, then say Y. Otherwise say N. +config MFD_INTEL_M10_BMC + tristate "Intel MAX 10 Board Management Controller" + depends on SPI_MASTER + select REGMAP_SPI_AVMM + select MFD_CORE + help + Support for the Intel MAX 10 board management controller using the + SPI interface. + + This driver provides common support for accessing the device, + additional drivers must be enabled in order to use the functionality + of the device. + endmenu endif diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index e6c7520ed129..1780019d2474 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -266,3 +266,4 @@ obj-$(CONFIG_MFD_KHADAS_MCU) += khadas-mcu.o obj-$(CONFIG_SGI_MFD_IOC3) += ioc3.o obj-$(CONFIG_MFD_SIMPLE_MFD_I2C) += simple-mfd-i2c.o +obj-$(CONFIG_MFD_INTEL_M10_BMC) += intel-m10-bmc.o diff --git a/drivers/mfd/intel-m10-bmc.c b/drivers/mfd/intel-m10-bmc.c new file mode 100644 index 000000000000..b84579b7b4f0 --- /dev/null +++ b/drivers/mfd/intel-m10-bmc.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Intel MAX 10 Board Management Controller chip + * + * Copyright (C) 2018-2020 Intel Corporation. All rights reserved. + */ +#include <linux/bitfield.h> +#include <linux/init.h> +#include <linux/mfd/core.h> +#include <linux/mfd/intel-m10-bmc.h> +#include <linux/module.h> +#include <linux/mutex.h> +#include <linux/regmap.h> +#include <linux/spi/spi.h> + +enum m10bmc_type { + M10_N3000, +}; + +static struct mfd_cell m10bmc_pacn3000_subdevs[] = { + { .name = "n3000bmc-hwmon" }, + { .name = "n3000bmc-retimer" }, + { .name = "n3000bmc-secure" }, +}; + +static struct regmap_config intel_m10bmc_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = M10BMC_MEM_END, +}; + +static ssize_t bmc_version_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct intel_m10bmc *ddata = dev_get_drvdata(dev); + unsigned int val; + int ret; + + ret = m10bmc_sys_read(ddata, M10BMC_BUILD_VER, &val); + if (ret) + return ret; + + return sprintf(buf, "0x%x\n", val); +} +static DEVICE_ATTR_RO(bmc_version); + +static ssize_t bmcfw_version_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct intel_m10bmc *ddata = dev_get_drvdata(dev); + unsigned int val; + int ret; + + ret = m10bmc_sys_read(ddata, NIOS2_FW_VERSION, &val); + if (ret) + return ret; + + return sprintf(buf, "0x%x\n", val); +} +static DEVICE_ATTR_RO(bmcfw_version); + +static struct attribute *m10bmc_attrs[] = { + &dev_attr_bmc_version.attr, + &dev_attr_bmcfw_version.attr, + NULL, +}; +ATTRIBUTE_GROUPS(m10bmc); + +static int check_m10bmc_version(struct intel_m10bmc *ddata) +{ + unsigned int v; + int ret; + + /* + * This check is to filter out the very old legacy BMC versions, + * M10BMC_LEGACY_SYS_BASE is the offset to this old block of mmio + * registers. In the old BMC chips, the BMC version info is stored + * in this old version register (M10BMC_LEGACY_SYS_BASE + + * M10BMC_BUILD_VER), so its read out value would have not been + * LEGACY_INVALID (0xffffffff). But in new BMC chips that the + * driver supports, the value of this register should be + * LEGACY_INVALID. + */ + ret = m10bmc_raw_read(ddata, + M10BMC_LEGACY_SYS_BASE + M10BMC_BUILD_VER, &v); + if (ret) + return -ENODEV; + + if (v != M10BMC_VER_LEGACY_INVALID) { + dev_err(ddata->dev, "bad version M10BMC detected\n"); + return -ENODEV; + } + + return 0; +} + +static int intel_m10_bmc_spi_probe(struct spi_device *spi) +{ + const struct spi_device_id *id = spi_get_device_id(spi); + struct device *dev = &spi->dev; + struct mfd_cell *cells; + struct intel_m10bmc *ddata; + int ret, n_cell; + + ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); + if (!ddata) + return -ENOMEM; + + ddata->dev = dev; + + ddata->regmap = + devm_regmap_init_spi_avmm(spi, &intel_m10bmc_regmap_config); + if (IS_ERR(ddata->regmap)) { + ret = PTR_ERR(ddata->regmap); + dev_err(dev, "Failed to allocate regmap: %d\n", ret); + return ret; + } + + spi_set_drvdata(spi, ddata); + + ret = check_m10bmc_version(ddata); + if (ret) { + dev_err(dev, "Failed to identify m10bmc hardware\n"); + return ret; + } + + switch (id->driver_data) { + case M10_N3000: + cells = m10bmc_pacn3000_subdevs; + n_cell = ARRAY_SIZE(m10bmc_pacn3000_subdevs); + break; + default: + return -ENODEV; + } + + ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, cells, n_cell, + NULL, 0, NULL); + if (ret) + dev_err(dev, "Failed to register sub-devices: %d\n", ret); + + return ret; +} + +static const struct spi_device_id m10bmc_spi_id[] = { + { "m10-n3000", M10_N3000 }, + { } +}; +MODULE_DEVICE_TABLE(spi, m10bmc_spi_id); + +static struct spi_driver intel_m10bmc_spi_driver = { + .driver = { + .name = "intel-m10-bmc", + .dev_groups = m10bmc_groups, + }, + .probe = intel_m10_bmc_spi_probe, + .id_table = m10bmc_spi_id, +}; +module_spi_driver(intel_m10bmc_spi_driver); + +MODULE_DESCRIPTION("Intel MAX 10 BMC Device Driver"); +MODULE_AUTHOR("Intel Corporation"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("spi:intel-m10-bmc"); diff --git a/include/linux/mfd/intel-m10-bmc.h b/include/linux/mfd/intel-m10-bmc.h new file mode 100644 index 000000000000..c8ef2f1654a4 --- /dev/null +++ b/include/linux/mfd/intel-m10-bmc.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Intel MAX 10 Board Management Controller chip. + * + * Copyright (C) 2018-2020 Intel Corporation, Inc. + */ +#ifndef __MFD_INTEL_M10_BMC_H +#define __MFD_INTEL_M10_BMC_H + +#include <linux/regmap.h> + +#define M10BMC_LEGACY_SYS_BASE 0x300400 +#define M10BMC_SYS_BASE 0x300800 +#define M10BMC_MEM_END 0x200000fc + +/* Register offset of system registers */ +#define NIOS2_FW_VERSION 0x0 +#define M10BMC_TEST_REG 0x3c +#define M10BMC_BUILD_VER 0x68 +#define M10BMC_VER_MAJOR_MSK GENMASK(23, 16) +#define M10BMC_VER_PCB_INFO_MSK GENMASK(31, 24) +#define M10BMC_VER_LEGACY_INVALID 0xffffffff + +/** + * struct intel_m10bmc - Intel MAX 10 BMC parent driver data structure + * @dev: this device + * @regmap: the regmap used to access registers by m10bmc itself + */ +struct intel_m10bmc { + struct device *dev; + struct regmap *regmap; +}; + +/* + * register access helper functions. + * + * m10bmc_raw_read - read m10bmc register per addr + * m10bmc_sys_read - read m10bmc system register per offset + */ +static inline int +m10bmc_raw_read(struct intel_m10bmc *m10bmc, unsigned int addr, + unsigned int *val) +{ + int ret; + + ret = regmap_read(m10bmc->regmap, addr, val); + if (ret) + dev_err(m10bmc->dev, "fail to read raw reg %x: %d\n", + addr, ret); + + return ret; +} + +/* + * The base of the system registers could be configured by HW developers, and + * in HW SPEC, the base is not added to the addresses of the system registers. + * + * This macro helps to simplify the accessing of the system registers. And if + * the base is reconfigured in HW, SW developers could simply change the + * M10BMC_SYS_BASE accordingly. + */ +#define m10bmc_sys_read(m10bmc, offset, val) \ + m10bmc_raw_read(m10bmc, M10BMC_SYS_BASE + (offset), val) + +#endif /* __MFD_INTEL_M10_BMC_H */ |