diff options
| -rw-r--r-- | drivers/media/dvb/ngene/ngene-core.c | 4062 | ||||
| -rw-r--r-- | drivers/media/dvb/ngene/ngene-ioctls.h | 216 | ||||
| -rw-r--r-- | drivers/media/dvb/ngene/ngene-snd.c | 421 | ||||
| -rw-r--r-- | drivers/media/dvb/ngene/ngene-v4l2.c | 1937 | ||||
| -rw-r--r-- | drivers/media/dvb/ngene/ngene.h | 948 |
5 files changed, 7584 insertions, 0 deletions
diff --git a/drivers/media/dvb/ngene/ngene-core.c b/drivers/media/dvb/ngene/ngene-core.c new file mode 100644 index 000000000000..744a232bd100 --- /dev/null +++ b/drivers/media/dvb/ngene/ngene-core.c @@ -0,0 +1,4062 @@ +/* + * ngene.c: nGene PCIe bridge driver + * + * Copyright (C) 2005-2007 Micronas + * + * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de> + * Modifications for new nGene firmware, + * support for EEPROM-copying, + * support for new dual DVB-S2 card prototype + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/slab.h> +#include <linux/poll.h> +#include <asm/io.h> +#include <asm/div64.h> +#include <linux/pci.h> +#include <linux/pci_ids.h> +#include <linux/smp_lock.h> +#include <linux/timer.h> +#include <linux/version.h> +#include <linux/byteorder/generic.h> +#include <linux/firmware.h> + +#include "ngene.h" + +#ifdef NGENE_COMMAND_API +#include "ngene-ioctls.h" +#endif + +#define FW_INC 1 +#ifdef FW_INC +#include "ngene_fw_15.h" +#include "ngene_fw_16.h" +#include "ngene_fw_17.h" + +DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); + +static int load_firmware; +module_param(load_firmware, int, 0444); +MODULE_PARM_DESC(load_firmware, "Try to load firmware from file."); +#endif + +static int copy_eeprom; +module_param(copy_eeprom, int, 0444); +MODULE_PARM_DESC(copy_eeprom, "Copy eeprom."); + +static int ngene_fw_debug; +module_param(ngene_fw_debug, int, 0444); +MODULE_PARM_DESC(ngene_fw_debug, "Debug firmware."); + +static int debug; +module_param(debug, int, 0444); +MODULE_PARM_DESC(debug, "Print debugging information."); + +#define dprintk if (debug) printk + +#define DEVICE_NAME "ngene" + +#define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr))) +#define ngwritel(dat, adr) writel((dat), (char *)(dev->iomem + (adr))) +#define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr))) +#define ngreadl(adr) readl(dev->iomem + (adr)) +#define ngreadb(adr) readb(dev->iomem + (adr)) +#define ngcpyto(adr, src, count) memcpy_toio((char *) \ + (dev->iomem + (adr)), (src), (count)) +#define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), (char *) \ + (dev->iomem + (adr)), (count)) + +/****************************************************************************/ +/* Functions with missing kernel exports ************************************/ +/****************************************************************************/ + +/* yeah, let's throw out all exports which are not used in kernel ... */ + +void my_dvb_ringbuffer_flush(struct dvb_ringbuffer *rbuf) +{ + rbuf->pread = rbuf->pwrite; + rbuf->error = 0; +} + +/****************************************************************************/ +/* nGene interrupt handler **************************************************/ +/****************************************************************************/ + +static void event_tasklet(unsigned long data) +{ + struct ngene *dev = (struct ngene *)data; + + while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) { + struct EVENT_BUFFER Event = + dev->EventQueue[dev->EventQueueReadIndex]; + dev->EventQueueReadIndex = + (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1); + + if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify)) + dev->TxEventNotify(dev, Event.TimeStamp); + if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify)) + dev->RxEventNotify(dev, Event.TimeStamp, + Event.RXCharacter); + } +} + +static void demux_tasklet(unsigned long data) +{ + struct ngene_channel *chan = (struct ngene_channel *)data; + struct SBufferHeader *Cur = chan->nextBuffer; + + spin_lock_irq(&chan->state_lock); + + while (Cur->ngeneBuffer.SR.Flags & 0x80) { + if (chan->mode & NGENE_IO_TSOUT) { + u32 Flags = chan->DataFormatFlags; + if (Cur->ngeneBuffer.SR.Flags & 0x20) + Flags |= BEF_OVERFLOW; + if (chan->pBufferExchange) { + if (!chan->pBufferExchange(chan, + Cur->Buffer1, + chan->Capture1Length, + Cur->ngeneBuffer.SR. + Clock, Flags)) { + /* + We didn't get data + Clear in service flag to make sure we + get called on next interrupt again. + leave fill/empty (0x80) flag alone + to avoid hardware running out of + buffers during startup, we hold only + in run state ( the source may be late + delivering data ) + */ + + if (chan->HWState == HWSTATE_RUN) { + Cur->ngeneBuffer.SR.Flags &= + ~0x40; + break; + /* Stop proccessing stream */ + } + } else { + /* We got a valid buffer, + so switch to run state */ + chan->HWState = HWSTATE_RUN; + } + } else { + printk(KERN_ERR DEVICE_NAME ": OOPS\n"); + if (chan->HWState == HWSTATE_RUN) { + Cur->ngeneBuffer.SR.Flags &= ~0x40; + break; /* Stop proccessing stream */ + } + } + if (chan->AudioDTOUpdated) { + printk(KERN_INFO DEVICE_NAME + ": Update AudioDTO = %d\n", + chan->AudioDTOValue); + Cur->ngeneBuffer.SR.DTOUpdate = + chan->AudioDTOValue; + chan->AudioDTOUpdated = 0; + } + } else { + if (chan->HWState == HWSTATE_RUN) { + u32 Flags = 0; + if (Cur->ngeneBuffer.SR.Flags & 0x01) + Flags |= BEF_EVEN_FIELD; + if (Cur->ngeneBuffer.SR.Flags & 0x20) + Flags |= BEF_OVERFLOW; + if (chan->pBufferExchange) + chan->pBufferExchange(chan, + Cur->Buffer1, + chan-> + Capture1Length, + Cur->ngeneBuffer. + SR.Clock, Flags); + if (chan->pBufferExchange2) + chan->pBufferExchange2(chan, + Cur->Buffer2, + chan-> + Capture2Length, + Cur->ngeneBuffer. + SR.Clock, Flags); + } else if (chan->HWState != HWSTATE_STOP) + chan->HWState = HWSTATE_RUN; + } + Cur->ngeneBuffer.SR.Flags = 0x00; + Cur = Cur->Next; + } + chan->nextBuffer = Cur; + + spin_unlock_irq(&chan->state_lock); +} + +static irqreturn_t irq_handler(int irq, void *dev_id) +{ + struct ngene *dev = (struct ngene *)dev_id; + u32 icounts = 0; + irqreturn_t rc = IRQ_NONE; + u32 i = MAX_STREAM; + u8 *tmpCmdDoneByte; + + if (dev->BootFirmware) { + icounts = ngreadl(NGENE_INT_COUNTS); + if (icounts != dev->icounts) { + ngwritel(0, FORCE_NMI); + dev->cmd_done = 1; + wake_up(&dev->cmd_wq); + dev->icounts = icounts; + rc = IRQ_HANDLED; + } + return rc; + } + + ngwritel(0, FORCE_NMI); + + spin_lock(&dev->cmd_lock); + tmpCmdDoneByte = dev->CmdDoneByte; + if (tmpCmdDoneByte && + (*tmpCmdDoneByte || + (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) { + dev->CmdDoneByte = NULL; + dev->cmd_done = 1; + wake_up(&dev->cmd_wq); + rc = IRQ_HANDLED; + } + spin_unlock(&dev->cmd_lock); + + if (dev->EventBuffer->EventStatus & 0x80) { + u8 nextWriteIndex = + (dev->EventQueueWriteIndex + 1) & + (EVENT_QUEUE_SIZE - 1); + if (nextWriteIndex != dev->EventQueueReadIndex) { + dev->EventQueue[dev->EventQueueWriteIndex] = + *(dev->EventBuffer); + dev->EventQueueWriteIndex = nextWriteIndex; + } else { + printk(KERN_ERR DEVICE_NAME ": event overflow\n"); + dev->EventQueueOverflowCount += 1; + dev->EventQueueOverflowFlag = 1; + } + dev->EventBuffer->EventStatus &= ~0x80; + tasklet_schedule(&dev->event_tasklet); + rc = IRQ_HANDLED; + } + + while (i > 0) { + i--; + spin_lock(&dev->channel[i].state_lock); + /* if (dev->channel[i].State>=KSSTATE_RUN) { */ + if (dev->channel[i].nextBuffer) { + if ((dev->channel[i].nextBuffer-> + ngeneBuffer.SR.Flags & 0xC0) == 0x80) { + dev->channel[i].nextBuffer-> + ngeneBuffer.SR.Flags |= 0x40; + tasklet_schedule( + &dev->channel[i].demux_tasklet); + rc = IRQ_HANDLED; + } + } + spin_unlock(&dev->channel[i].state_lock); + } + + return rc; +} + +/****************************************************************************/ +/* nGene command interface **************************************************/ +/****************************************************************************/ + +static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com) +{ + int ret; + u8 *tmpCmdDoneByte; + + dev->cmd_done = 0; + + if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) { + dev->BootFirmware = 1; + dev->icounts = ngreadl(NGENE_INT_COUNTS); + ngwritel(0, NGENE_COMMAND); + ngwritel(0, NGENE_COMMAND_HI); + ngwritel(0, NGENE_STATUS); + ngwritel(0, NGENE_STATUS_HI); + ngwritel(0, NGENE_EVENT); + ngwritel(0, NGENE_EVENT_HI); + } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) { + u64 fwio = dev->PAFWInterfaceBuffer; + + ngwritel(fwio & 0xffffffff, NGENE_COMMAND); + ngwritel(fwio >> 32, NGENE_COMMAND_HI); + ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS); + ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI); + ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT); + ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI); + } + + memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2); + + if (dev->BootFirmware) + ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2); + + spin_lock_irq(&dev->cmd_lock); + tmpCmdDoneByte = dev->ngenetohost + com->out_len; + if (!com->out_len) + tmpCmdDoneByte++; + *tmpCmdDoneByte = 0; + dev->ngenetohost[0] = 0; + dev->ngenetohost[1] = 0; + dev->CmdDoneByte = tmpCmdDoneByte; + spin_unlock_irq(&dev->cmd_lock); + + /* Notify 8051. */ + ngwritel(1, FORCE_INT); + + ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ); + if (!ret) { + /*ngwritel(0, FORCE_NMI);*/ + + printk(KERN_ERR DEVICE_NAME + ": Command timeout cmd=%02x prev=%02x\n", + com->cmd.hdr.Opcode, dev->prev_cmd); + return -1; + } + if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) + dev->BootFirmware = 0; + + dev->prev_cmd = com->cmd.hdr.Opcode; + msleep(10); + + if (!com->out_len) + return 0; + + memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len); + + return 0; +} + +static int ngene_command(struct ngene *dev, struct ngene_command *com) +{ + int result; + + down(&dev->cmd_mutex); + result = ngene_command_mutex(dev, com); + up(&dev->cmd_mutex); + return result; +} + +int ngene_command_nop(struct ngene *dev) +{ + struct ngene_command com; + + com.cmd.hdr.Opcode = CMD_NOP; + com.cmd.hdr.Length = 0; + com.in_len = 0; + com.out_len = 0; + + return ngene_command(dev, &com); +} + +int ngene_command_i2c_read(struct ngene *dev, u8 adr, + u8 *out, u8 outlen, u8 *in, u8 inlen, int flag) +{ + struct ngene_command com; + + com.cmd.hdr.Opcode = CMD_I2C_READ; + com.cmd.hdr.Length = outlen + 3; + com.cmd.I2CRead.Device = adr << 1; + memcpy(com.cmd.I2CRead.Data, out, outlen); + com.cmd.I2CRead.Data[outlen] = inlen; + com.cmd.I2CRead.Data[outlen + 1] = 0; + com.in_len = outlen + 3; + com.out_len = inlen + 1; + + if (ngene_command(dev, &com) < 0) + return -EIO; + + if ((com.cmd.raw8[0] >> 1) != adr) + return -EIO; + + if (flag) + memcpy(in, com.cmd.raw8, inlen + 1); + else + memcpy(in, com.cmd.raw8 + 1, inlen); + return 0; +} + +int ngene_command_i2c_write(struct ngene *dev, u8 adr, u8 *out, u8 outlen) +{ + struct ngene_command com; + + + com.cmd.hdr.Opcode = CMD_I2C_WRITE; + com.cmd.hdr.Length = outlen + 1; + com.cmd.I2CRead.Device = adr << 1; + memcpy(com.cmd.I2CRead.Data, out, outlen); + com.in_len = outlen + 1; + com.out_len = 1; + + if (ngene_command(dev, &com) < 0) + return -EIO; + + if (com.cmd.raw8[0] == 1) + return -EIO; + + return 0; +} + +static int ngene_command_load_firmware(struct ngene *dev, + u8 *ngene_fw, u32 size) +{ +#define FIRSTCHUNK (1024) + u32 cleft; + struct ngene_command com; + + com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE; + com.cmd.hdr.Length = 0; + com.in_len = 0; + com.out_len = 0; + + ngene_command(dev, &com); + + cleft = (size + 3) & ~3; + if (cleft > FIRSTCHUNK) { + ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK, + cleft - FIRSTCHUNK); + cleft = FIRSTCHUNK; + } + ngene_fw[FW_DEBUG_DEFAULT - PROGRAM_SRAM] = ngene_fw_debug; + ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft); + + memset(&com, 0, sizeof(struct ngene_command)); + com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH; + com.cmd.hdr.Length = 4; + com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA; + com.cmd.FWLoadFinish.Length = (unsigned short)cleft; + com.in_len = 4; + com.out_len = 0; + + return ngene_command(dev, &com); +} + +int ngene_command_imem_read(struct ngene *dev, u8 adr, u8 *data, int type) +{ + struct ngene_command com; + + com.cmd.hdr.Opcode = type ? CMD_SFR_READ : CMD_IRAM_READ; + com.cmd.hdr.Length = 1; + com.cmd.SfrIramRead.address = adr; + com.in_len = 1; + com.out_len = 2; + + if (ngene_command(dev, &com) < 0) + return -EIO; + + *data = com.cmd.raw8[1]; + return 0; +} + +int ngene_command_imem_write(struct ngene *dev, u8 adr, u8 data, int type) +{ + struct ngene_command com; + + com.cmd.hdr.Opcode = type ? CMD_SFR_WRITE : CMD_IRAM_WRITE; + com.cmd.hdr.Length = 2; + com.cmd.SfrIramWrite.address = adr; + com.cmd.SfrIramWrite.data = data; + com.in_len = 2; + com.out_len = 1; + + if (ngene_command(dev, &com) < 0) + return -EIO; + + return 0; +} + +static int ngene_command_config_uart(struct ngene *dev, u8 config, + tx_cb_t *tx_cb, rx_cb_t *rx_cb) +{ + struct ngene_command com; + + com.cmd.hdr.Opcode = CMD_CONFIGURE_UART; + com.cmd.hdr.Length = sizeof(struct FW_CONFIGURE_UART) - 2; + com.cmd.ConfigureUart.UartControl = config; + com.in_len = sizeof(struct FW_CONFIGURE_UART); + com.out_len = 0; + + if (ngene_command(dev, &com) < 0) + return -EIO; + + dev->TxEventNotify = tx_cb; + dev->RxEventNotify = rx_cb; + + dprintk(KERN_DEBUG DEVICE_NAME ": Set UART config %02x.\n", config); + + return 0; +} + +static void tx_cb(struct ngene *dev, u32 ts) +{ + dev->tx_busy = 0; + wake_up_interruptible(&dev->tx_wq); +} + +static void rx_cb(struct ngene *dev, u32 ts, u8 c) +{ + int rp = dev->uart_rp; + int nwp, wp = dev->uart_wp; + + /* dprintk(KERN_DEBUG DEVICE_NAME ": %c\n", c); */ + nwp = (wp + 1) % (UART_RBUF_LEN); + if (nwp == rp) + return; + dev->uart_rbuf[wp] = c; + dev->uart_wp = nwp; + wake_up_interruptible(&dev->rx_wq); +} + +static int ngene_command_config_buf(struct ngene *dev, u8 config) +{ + struct ngene_command com; + + com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER; + com.cmd.hdr.Length = 1; + com.cmd.ConfigureBuffers.config = config; + com.in_len = 1; + com.out_len = 0; + + if (ngene_command(dev, &com) < 0) + return -EIO; + return 0; +} + +static int ngene_command_config_free_buf(struct ngene *dev, u8 *config) +{ + struct ngene_command com; + + com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER; + com.cmd.hdr.Length = 6; + memcpy(&com.cmd.ConfigureBuffers.config, config, 6); + com.in_len = 6; + com.out_len = 0; + + if (ngene_command(dev, &com) < 0) + return -EIO; + + return 0; +} + +static int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level) +{ + struct ngene_command com; + + com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN; + com.cmd.hdr.Length = 1; + com.cmd.SetGpioPin.select = select | (level << 7); + com.in_len = 1; + com.out_len = 0; + + return ngene_command(dev, &com); +} + +/* The reset is only wired to GPIO4 on MicRacer Revision 1.10 ! + Also better set bootdelay to 1 in nvram or less. */ +static void ngene_reset_decypher(struct ngene *dev) +{ + printk(KERN_INFO DEVICE_NAME ": Resetting Decypher.\n"); + ngene_command_gpio_set(dev, 4, 0); + msleep(1); + ngene_command_gpio_set(dev, 4, 1); + msleep(2000); +} + +/* + 02000640 is sample on rising edge. + 02000740 is sample on falling edge. + 02000040 is ignore "valid" signal + + 0: FD_CTL1 Bit 7,6 must be 0,1 + 7 disable(fw controlled) + 6 0-AUX,1-TS + 5 0-par,1-ser + 4 0-lsb/1-msb + 3,2 reserved + 1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both + 1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge + 2: FD_STA is read-only. 0-sync + 3: FD_INSYNC is number of 47s to trigger "in sync". + 4: FD_OUTSYNC is number of 47s to trigger "out of sync". + 5: FD_MAXBYTE1 is low-order of bytes per packet. + 6: FD_MAXBYTE2 is high-order of bytes per packet. + 7: Top byte is unused. +*/ + +/****************************************************************************/ + +static u8 TSFeatureDecoderSetup[8 * 4] = { + 0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, + 0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */ + 0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */ + 0x72, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */ +}; + +/* Set NGENE I2S Config to 16 bit packed */ +static u8 I2SConfiguration[] = { + 0x00, 0x10, 0x00, 0x00, + 0x80, 0x10, 0x00, 0x00, +}; + +static u8 SPDIFConfiguration[10] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +/* Set NGENE I2S Config to transport stream compatible mode */ + +static u8 TS_I2SConfiguration[4] = { 0x3E, 0x1A, 0x00, 0x00 }; /*3e 18 00 00 ?*/ + +static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x20, 0x00, 0x00 }; + +static u8 ITUDecoderSetup[4][16] = { + {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20, /* SDTV */ + 0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00}, + {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00, + 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00}, + {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00, /* HDTV 1080i50 */ + 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00}, + {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00, /* HDTV 1080i60 */ + 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00}, +}; + +/* + * 50 48 60 gleich + * 27p50 9f 00 22 80 42 69 18 ... + * 27p60 93 00 22 80 82 69 1c ... + */ + +/* Maxbyte to 1144 (for raw data) */ +static u8 ITUFeatureDecoderSetup[8] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00 +}; + +static void FillTSBuffer(void *Buffer, int Length, u32 Flags) +{ + u32 *ptr = Buffer; + + memset(Buffer, Length, 0xff); + while (Length > 0) { + if (Flags & DF_SWAP32) + *ptr = 0x471FFF10; + else + *ptr = 0x10FF1F47; + ptr += (188 / 4); + Length -= 188; + } +} + +static void clear_tsin(struct ngene_channel *chan) +{ + struct SBufferHeader *Cur = chan->nextBuffer; + + do { + memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR)); + Cur = Cur->Next; + } while (Cur != chan->nextBuffer); +} + +static void flush_buffers(struct ngene_channel *chan) +{ + u8 val; + + do { + msleep(1); + spin_lock_irq(&chan->state_lock); + val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80; + spin_unlock_irq(&chan->state_lock); + } while (val); +} + +static void clear_buffers(struct ngene_channel *chan) +{ + struct SBufferHeader *Cur = chan->nextBuffer; + + do { + memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR)); + if (chan->mode & NGENE_IO_TSOUT) + FillTSBuffer(Cur->Buffer1, + chan->Capture1Length, + chan->DataFormatFlags); + Cur = Cur->Next; + } while (Cur != chan->nextBuffer); + + if (chan->mode & NGENE_IO_TSOUT) { + chan->nextBuffer->ngeneBuffer.SR.DTOUpdate = + chan->AudioDTOValue; + chan->AudioDTOUpdated = 0; + + Cur = chan->TSIdleBuffer.Head; + + do { + memset(&Cur->ngeneBuffer.SR, 0, + sizeof(Cur->ngeneBuffer.SR)); + FillTSBuffer(Cur->Buffer1, + chan->Capture1Length, + chan->DataFormatFlags); + Cur = Cur->Next; + } while (Cur != chan->TSIdleBuffer.Head); + } +} + +int ngene_command_stream_control(struct ngene *dev, u8 stream, u8 control, + u8 mode, u8 flags) +{ + struct ngene_channel *chan = &dev->channel[stream]; + struct ngene_command com; + u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300); + u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500); + u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700); + u16 BsSDO = 0x9B00; + + /* down(&dev->stream_mutex); */ + while (down_trylock(&dev->stream_mutex)) { + printk(KERN_INFO DEVICE_NAME ": SC locked\n"); + msleep(1); + } + memset(&com, 0, sizeof(com)); + com.cmd.hdr.Opcode = CMD_CONTROL; + com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2; + com.cmd.StreamControl.Stream = stream | (control ? 8 : 0); + if (chan->mode & NGENE_IO_TSOUT) + com.cmd.StreamControl.Stream |= 0x07; + com.cmd.StreamControl.Control = control | + (flags & SFLAG_ORDER_LUMA_CHROMA); + com.cmd.StreamControl.Mode = mode; + com.in_len = sizeof(struct FW_STREAM_CONTROL); + com.out_len = 0; + + printk(KERN_INFO DEVICE_NAME ": Stream=%02x, Control=%02x, Mode=%02x\n", + com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control, + com.cmd.StreamControl.Mode); + chan->Mode = mode; + + if (!(control & 0x80)) { + spin_lock_irq(&chan->state_lock); + if (chan->State == KSSTATE_RUN) { + chan->State = KSSTATE_ACQUIRE; + chan->HWState = HWSTATE_STOP; + spin_unlock_irq(&chan->state_lock); + if (ngene_command(dev, &com) < 0) { + up(&dev->stream_mutex); + return -1; + } + /* clear_buffers(chan); */ + flush_buffers(chan); + up(&dev->stream_mutex); + return 0; + } + spin_unlock_irq(&chan->state_lock); + up(&dev->stream_mutex); + return 0; + } + + if (mode & SMODE_AUDIO_CAPTURE) { + com.cmd.StreamControl.CaptureBlockCount = + chan->Capture1Length / AUDIO_BLOCK_SIZE; + com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead; + } else if (mode & SMODE_TRANSPORT_STREAM) { + com.cmd.StreamControl.CaptureBlockCount = + chan->Capture1Length / TS_BLOCK_SIZE; + com.cmd.StreamControl.MaxLinesPerField = + chan->Capture1Length / TS_BLOCK_SIZE; + com.cmd.StreamControl.Buffer_Address = + chan->TSRingBuffer.PAHead; + if (chan->mode & NGENE_IO_TSOUT) { + com.cmd.StreamControl.BytesPerVBILine = + chan->Capture1Length / TS_BLOCK_SIZE; + com.cmd.StreamControl.Stream |= 0x07; + } + } else { + com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine; + com.cmd.StreamControl.MaxLinesPerField = chan->nLines; + com.cmd.StreamControl.MinLinesPerField = 100; + com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead; + + if (mode & SMODE_VBI_CAPTURE) { + com.cmd.StreamControl.MaxVBILinesPerField = + chan->nVBILines; + com.cmd.StreamControl.MinVBILinesPerField = 0; + com.cmd.StreamControl.BytesPerVBILine = + chan->nBytesPerVBILine; + } + if (flags & SFLAG_COLORBAR) + com.cmd.StreamControl.Stream |= 0x04; + } + + spin_lock_irq(&chan->state_lock); + if (mode & SMODE_AUDIO_CAPTURE) { + chan->nextBuffer = chan->RingBuffer.Head; + if (mode & SMODE_AUDIO_SPDIF) { + com.cmd.StreamControl.SetupDataLen = + sizeof(SPDIFConfiguration); + com.cmd.StreamControl.SetupDataAddr = BsSPI; + memcpy(com.cmd.StreamControl.SetupData, + SPDIFConfiguration, sizeof(SPDIFConfiguration)); + } else { + com.cmd.StreamControl.SetupDataLen = 4; + com.cmd.StreamControl.SetupDataAddr = BsSDI; + memcpy(com.cmd.StreamControl.SetupData, + I2SConfiguration + + 4 * dev->card_info->i2s[stream], 4); + } + } else if (mode & SMODE_TRANSPORT_STREAM) { + chan->nextBuffer = chan->TSRingBuffer.Head; + if (stream >= STREAM_AUDIOIN1) { + if (chan->mode & NGENE_IO_TSOUT) { + com.cmd.StreamControl.SetupDataLen = + sizeof(TS_I2SOutConfiguration); + com.cmd.StreamControl.SetupDataAddr = BsSDO; + memcpy(com.cmd.StreamControl.SetupData, + TS_I2SOutConfiguration, + sizeof(TS_I2SOutConfiguration)); + } else { + com.cmd.StreamControl.SetupDataLen = + sizeof(TS_I2SConfiguration); + com.cmd.StreamControl.SetupDataAddr = BsSDI; + memcpy(com.cmd.StreamControl.SetupData, + TS_I2SConfiguration, + sizeof(TS_I2SConfiguration)); + } + } else { + com.cmd.StreamControl.SetupDataLen = 8; + com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10; + memcpy(com.cmd.StreamControl.SetupData, + TSFeatureDecoderSetup + + 8 * dev->card_info->tsf[stream], 8); + } + } else { + chan->nextBuffer = chan->RingBuffer.Head; + com.cmd.StreamControl.SetupDataLen = + 16 + sizeof(ITUFeatureDecoderSetup); + com.cmd.StreamControl.SetupDataAddr = BsUVI; + memcpy(com.cmd.StreamControl.SetupData, + ITUDecoderSetup[chan->itumode], 16); + memcpy(com.cmd.StreamControl.SetupData + 16, + ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup)); + } + clear_buffers(chan); + chan->State = KSSTATE_RUN; + if (mode & SMODE_TRANSPORT_STREAM) + chan->HWState = HWSTATE_RUN; + else + chan->HWState = HWSTATE_STARTUP; + spin_unlock_irq(&chan->state_lock); + + if (ngene_command(dev, &com) < 0) { + up(&dev->stream_mutex); + return -1; + } + up(&dev->stream_mutex); + return 0; +} + +int ngene_stream_control(struct ngene *dev, u8 stream, u8 control, u8 mode, + u16 lines, u16 bpl, u16 vblines, u16 vbibpl) +{ + if (!(mode & SMODE_TRANSPORT_STREAM)) + return -EINVAL; + + if (lines * bpl > MAX_VIDEO_BUFFER_SIZE) + return -EINVAL; + + if ((mode & SMODE_TRANSPORT_STREAM) && (((bpl * lines) & 0xff) != 0)) + return -EINVAL; + + if ((mode & SMODE_VIDEO_CAPTURE) && (bpl & 7) != 0) + return -EINVAL; + + return ngene_command_stream_control(dev, stream, control, mode, 0); +} + +/****************************************************************************/ +/* I2C **********************************************************************/ +/****************************************************************************/ + +static void ngene_i2c_set_bus(struct ngene *dev, int bus) +{ + if (!(dev->card_info->i2c_access & 2)) + return; + if (dev->i2c_current_bus == bus) + return; + + switch (bus) { + case 0: + ngene_command_gpio_set(dev, 3, 0); + ngene_command_gpio_set(dev, 2, 1); + break; + + case 1: + ngene_command_gpio_set(dev, 2, 0); + ngene_command_gpio_set(dev, 3, 1); + break; + } + dev->i2c_current_bus = bus; +} + +static int ngene_i2c_master_xfer(struct i2c_adapter *adapter, + struct i2c_msg msg[], int num) +{ + struct ngene_channel *chan = + (struct ngene_channel *)i2c_get_adapdata(adapter); + struct ngene *dev = chan->dev; + + down(&dev->i2c_switch_mutex); + ngene_i2c_set_bus(dev, chan->number); + + if (num == 2 && msg[1].flags & I2C_M_RD && !(msg[0].flags & I2C_M_RD)) + if (!ngene_command_i2c_read(dev, msg[0].addr, + msg[0].buf, msg[0].len, + msg[1].buf, msg[1].len, 0)) + goto done; + + if (num == 1 && !(msg[0].flags & I2C_M_RD)) + if (!ngene_command_i2c_write(dev, msg[0].addr, + msg[0].buf, msg[0].len)) + goto done; + if (num == 1 && (msg[0].flags & I2C_M_RD)) + if (!ngene_command_i2c_read(dev, msg[0].addr, 0, 0, + msg[0].buf, msg[0].len, 0)) + goto done; + + up(&dev->i2c_switch_mutex); + return -EIO; + +done: + up(&dev->i2c_switch_mutex); + return num; +} + + +static int ngene_i2c_algo_control(struct i2c_adapter *adap, + unsigned int cmd, unsigned long arg) +{ + struct ngene_channel *chan = + (struct ngene_channel *)i2c_get_adapdata(adap); + + switch (cmd) { + case IOCTL_MIC_TUN_RDY: + chan->tun_rdy = 1; + if (chan->dec_rdy == 1) + chan->tun_dec_rdy = 1; + break; + + case IOCTL_MIC_DEC_RDY: + chan->dec_rdy = 1; + if (chan->tun_rdy == 1) + chan->tun_dec_rdy = 1; + break; + + case IOCTL_MIC_TUN_DETECT: + { + int *palorbtsc = (int *)arg; + *palorbtsc = chan->dev->card_info->ntsc; + break; + } + + default: + break; + } + return 0; +} + +static u32 ngene_i2c_functionality(struct i2c_adapter *adap) +{ + return I2C_FUNC_SMBUS_EMUL; +} + +struct i2c_algorithm ngene_i2c_algo = { + .master_xfer = ngene_i2c_master_xfer, + .functionality = ngene_i2c_functionality, +}; + +static int ngene_i2c_attach(struct i2c_client *client) +{ + return 0; +} + +static int ngene_i2c_detach(struct i2c_client *client) +{ + return 0; +} + +static int ngene_i2c_init(struct ngene *dev, int dev_nr) +{ + struct i2c_adapter *adap = &(dev->channel[dev_nr].i2c_adapter); + + i2c_set_adapdata(adap, &(dev->channel[dev_nr])); +#ifdef I2C_ADAP_CLASS_TV_DIGITAL + adap->class = I2C_ADAP_CLASS_TV_DIGITAL | I2C_CLASS_TV_ANALOG; +#else + adap->class = I2C_CLASS_TV_ANALOG; +#endif + + strcpy(adap->name, "nGene"); + + adap->id = I2C_HW_SAA7146; + adap->client_register = ngene_i2c_attach; + adap->client_unregister = ngene_i2c_detach; + adap->algo = &ngene_i2c_algo; + adap->algo_data = (void *)&(dev->channel[dev_nr]); + + mutex_init(&adap->bus_lock); + return i2c_add_adapter(adap); +} + +int i2c_write(struct i2c_adapter *adapter, u8 adr, u8 data) +{ + u8 m[1] = {data}; + struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 1}; + + if (i2c_transfer(adapter, &msg, 1) != 1) { + printk(KERN_ERR DEVICE_NAME + ": Failed to write to I2C adr %02x!\n", adr); + return -1; + } + return 0; +} + +static int i2c_write_register(struct i2c_adapter *adapter, + u8 adr, u8 reg, u8 data) +{ + u8 m[2] = {reg, data}; + struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 2}; + + if (i2c_transfer(adapter, &msg, 1) != 1) { + printk(KERN_ERR DEVICE_NAME + ": Failed to write to I2C register %02x@%02x!\n", + reg, adr); + return -1; + } + return 0; +} + +static int i2c_write_read(struct i2c_adapter *adapter, + u8 adr, u8 *w, u8 wlen, u8 *r, u8 rlen) +{ + struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, + .buf = w, .len = wlen}, + {.addr = adr, .flags = I2C_M_RD, + .buf = r, .len = rlen} }; + + if (i2c_transfer(adapter, msgs, 2) != 2) { + printk(KERN_ERR DEVICE_NAME ": error in i2c_write_read\n"); + return -1; + } + return 0; +} + +static int test_dec_i2c(struct i2c_adapter *adapter, int reg) +{ + u8 data[256] = { reg, 0x00, 0x93, 0x78, 0x43, 0x45 }; + u8 data2[256]; + int i; + + memset(data2, 0, 256); + i2c_write_read(adapter, 0x66, data, 2, data2, 4); + for (i = 0; i < 4; i++) + printk("%02x ", data2[i]); + printk("\n"); + + return 0; +} + + +/****************************************************************************/ +/* EEPROM TAGS **************************************************************/ +/****************************************************************************/ + +#define MICNG_EE_START 0x0100 +#define MICNG_EE_END 0x0FF0 + +#define MICNG_EETAG_END0 0x0000 +#define MICNG_EETAG_END1 0xFFFF + +/* 0x0001 - 0x000F reserved for housekeeping */ +/* 0xFFFF - 0xFFFE reserved for housekeeping */ + +/* Micronas assigned tags + EEProm tags for hardware support */ + +#define MICNG_EETAG_DRXD1_OSCDEVIATION 0x1000 /* 2 Bytes data */ +#define MICNG_EETAG_DRXD2_OSCDEVIATION 0x1001 /* 2 Bytes data */ + +#define MICNG_EETAG_MT2060_1_1STIF 0x1100 /* 2 Bytes data */ +#define MICNG_EETAG_MT2060_2_1STIF 0x1101 /* 2 Bytes data */ + +/* Tag range for OEMs */ + +#define MICNG_EETAG_OEM_FIRST 0xC000 +#define MICNG_EETAG_OEM_LAST 0xFFEF + +static int i2c_write_eeprom(struct i2c_adapter *adapter, + u8 adr, u16 reg, u8 data) +{ + u8 m[3] = {(reg >> 8), (reg & 0xff), data}; + struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, + .len = sizeof(m)}; + + if (i2c_transfer(adapter, &msg, 1) != 1) { + dprintk(KERN_DEBUG DEVICE_NAME ": Error writing EEPROM!\n"); + return -EIO; + } + return 0; +} + +static int i2c_read_eeprom(struct i2c_adapter *adapter, + u8 adr, u16 reg, u8 *data, int len) +{ + u8 msg[2] = {(reg >> 8), (reg & 0xff)}; + struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, + .buf = msg, .len = 2 }, + {.addr = adr, .flags = I2C_M_RD, + .buf = data, .len = len} }; + + if (i2c_transfer(adapter, msgs, 2) != 2) { + dprintk(KERN_DEBUG DEVICE_NAME ": Error reading EEPROM\n"); + return -EIO; + } + return 0; +} + +static int ReadEEProm(struct i2c_adapter *adapter, + u16 Tag, u32 MaxLen, u8 *data, u32 *pLength) +{ + int status = 0; + u16 Addr = MICNG_EE_START, Length, tag = 0; + u8 EETag[3]; + + while (Addr + sizeof(u16) + 1 < MICNG_EE_END) { + if (i2c_read_eeprom(adapter, 0x50, Addr, EETag, sizeof(EETag))) + return -1; + tag = (EETag[0] << 8) | EETag[1]; + if (tag == MICNG_EETAG_END0 || tag == MICNG_EETAG_END1) + return -1; + if (tag == Tag) + break; + Addr += sizeof(u16) + 1 + EETag[2]; + } + if (Addr + sizeof(u16) + 1 + EETag[2] > MICNG_EE_END) { + printk(KERN_ERR DEVICE_NAME + ": Reached EOEE @ Tag = %04x Length = %3d\n", + tag, EETag[2]); + return -1; + } + Length = EETag[2]; + if (Length > MaxLen) + Length = (u16) MaxLen; + if (Length > 0) { + Addr += sizeof(u16) + 1; + status = i2c_read_eeprom(adapter, 0x50, Addr, data, Length); + if (!status) { + *pLength = EETag[2]; + if (Length < EETag[2]) + ; /*status=STATUS_BUFFER_OVERFLOW; */ + } + } + return status; +} + +static int WriteEEProm(struct i2c_adapter *adapter, + u16 Tag, u32 Length, u8 *data) +{ + int status = 0; + u16 Addr = MICNG_EE_START; + u8 EETag[3]; + u16 tag = 0; + int retry, i; + + while (Addr + sizeof(u16) + 1 < MICNG_EE_END) { + if (i2c_read_eeprom(adapter, 0x50, Addr, EETag, sizeof(EETag))) + return -1; + tag = (EETag[0] << 8) | EETag[1]; + if (tag == MICNG_EETAG_END0 || tag == MICNG_EETAG_END1) + return -1; + if (tag == Tag) + break; + Addr += sizeof(u16) + 1 + EETag[2]; + } + if (Addr + sizeof(u16) + 1 + EETag[2] > MICNG_EE_END) { + printk(KERN_ERR DEVICE_NAME + ": Reached EOEE @ Tag = %04x Length = %3d\n", + tag, EETag[2]); + return -1; + } + + if (Length > EETag[2]) + return -EINVAL; + /* Note: We write the data one byte at a time to avoid + issues with page sizes. (which are different for + each manufacture and eeprom size) + */ + Addr += sizeof(u16) + 1; + for (i = 0; i < Length; i++, Addr++) { + status = i2c_write_eeprom(adapter, 0x50, Addr, data[i]); + + if (status) + break; + + /* Poll for finishing write cycle */ + retry = 10; + while (retry) { + u8 Tmp; + + msleep(50); + status = i2c_read_eeprom(adapter, 0x50, Addr, &Tmp, 1); + if (status) + break; + if (Tmp != data[i]) + printk(KERN_ERR DEVICE_NAME + "eeprom write error\n"); + retry -= 1; + } + if (status) { + printk(KERN_ERR DEVICE_NAME + ": Timeout polling eeprom\n"); + break; + } + } + return status; +} + +static void i2c_init_eeprom(struct i2c_adapter *adapter) +{ + u8 tags[] = {0x10, 0x00, 0x02, 0x00, 0x00, + 0x10, 0x01, 0x02, 0x00, 0x00, + 0x00, 0x00, 0x00}; + + int i; + + for (i = 0; i < sizeof(tags); i++) + i2c_write_eeprom(adapter, 0x50, 0x0100 + i, tags[i]); +} + +static int eeprom_read_ushort(struct i2c_adapter *adapter, u16 tag, u16 *data) +{ + int stat; + u8 buf[2]; + u32 len = 0; + + stat = ReadEEProm(adapter, tag, 2, buf, &len); + if (stat) + return stat; + if (len != 2) + return -EINVAL; + + *data = (buf[0] << 8) | buf[1]; + return 0; +} + +static int eeprom_write_ushort(struct i2c_adapter *adapter, u16 tag, u16 data) +{ + int stat; + u8 buf[2]; + + buf[0] = data >> 8; + buf[1] = data & 0xff; + stat = WriteEEProm(adapter, tag, 2, buf); + if (stat) + return stat; + return 0; +} + +static int i2c_dump_eeprom(struct i2c_adapter *adapter, u8 adr) +{ + u8 buf[64]; + int i; + + if (i2c_read_eeprom(adapter, adr, 0x0000, buf, sizeof(buf))) { + printk(KERN_ERR DEVICE_NAME ": No EEPROM?\n"); + return -1; + } + for (i = 0; i < sizeof(buf); i++) { + if (!(i & 15)) + printk("\n"); + printk("%02x ", buf[i]); + } + printk("\n"); + + return 0; +} + +static int i2c_copy_eeprom(struct i2c_adapter *adapter, u8 adr, u8 adr2) +{ + u8 buf[64]; + int i; + + if (i2c_read_eeprom(adapter, adr, 0x0000, buf, sizeof(buf))) { + printk(KERN_ERR DEVICE_NAME ": No EEPROM?\n"); + return -1; + } + buf[36] = 0xc3; + buf[39] = 0xab; + for (i = 0; i < sizeof(buf); i++) { + i2c_write_eeprom(adapter, adr2, i, buf[i]); + msleep(10); + } + return 0; +} + + +/****************************************************************************/ +/* COMMAND API interface ****************************************************/ +/****************************************************************************/ + +#ifdef NGENE_COMMAND_API + +static int command_do_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, void *parg) +{ + struct dvb_device *dvbdev = file->private_data; + struct ngene_channel *chan = dvbdev->priv; + struct ngene *dev = chan->dev; + int err = 0; + + switch (cmd) { + case IOCTL_MIC_NO_OP: + err = ngene_command_nop(dev); + break; + + case IOCTL_MIC_DOWNLOAD_FIRMWARE: + break; + + case IOCTL_MIC_I2C_READ: + { + MIC_I2C_READ *msg = parg; + + err = ngene_command_i2c_read(dev, msg->I2CAddress >> 1, + msg->OutData, msg->OutLength, + msg->OutData, msg->InLength, 1); + break; + } + + case IOCTL_MIC_I2C_WRITE: + { + MIC_I2C_WRITE *msg = parg; + + err = ngene_command_i2c_write(dev, msg->I2CAddress >> 1, + msg->Data, msg->Length); + break; + } + + case IOCTL_MIC_TEST_GETMEM: + { + MIC_MEM *m = parg; + + if (m->Length > 64 * 1024 || m->Start + m->Length > 64 * 1024) + return -EINVAL; + + /* WARNING, only use this on x86, + other archs may not swallow this */ + err = copy_to_user(m->Data, dev->iomem + m->Start, m->Length); + break; + } + + case IOCTL_MIC_TEST_SETMEM: + { + MIC_MEM *m = parg; + + if (m->Length > 64 * 1024 || m->Start + m->Length > 64 * 1024) + return -EINVAL; + + err = copy_from_user(dev->iomem + m->Start, m->Data, m->Length); + break; + } + + case IOCTL_MIC_SFR_READ: + { + MIC_IMEM *m = parg; + + err = ngene_command_imem_read(dev, m->Address, &m->Data, 1); + break; + } + + case IOCTL_MIC_SFR_WRITE: + { + MIC_IMEM *m = parg; + + err = ngene_command_imem_write(dev, m->Address, m->Data, 1); + break; + } + + case IOCTL_MIC_IRAM_READ: + { + MIC_IMEM *m = parg; + + err = ngene_command_imem_read(dev, m->Address, &m->Data, 0); + break; + } + + case IOCTL_MIC_IRAM_WRITE: + { + MIC_IMEM *m = parg; + + err = ngene_command_imem_write(dev, m->Address, m->Data, 0); + break; + } + + case IOCTL_MIC_STREAM_CONTROL: + { + MIC_STREAM_CONTROL *m = parg; + + err = ngene_stream_control(dev, m->Stream, m->Control, m->Mode, + m->nLines, m->nBytesPerLine, + m->nVBILines, m->nBytesPerVBILine); + break; + } + + default: + err = -EINVAL; + break; + } + return err; +} + +static int command_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + void *parg = (void *)arg, *pbuf = NULL; + char buf[64]; + int res = -EFAULT; + + if (_IOC_DIR(cmd) & _IOC_WRITE) { + parg = buf; + if (_IOC_SIZE(cmd) > sizeof(buf)) { + pbuf = kmalloc(_IOC_SIZE(cmd), GFP_KERNEL); + if (!pbuf) + return -ENOMEM; + parg = pbuf; + } + if (copy_from_user(parg, (void __user *)arg, _IOC_SIZE(cmd))) + goto error; + } + res = command_do_ioctl(inode, file, cmd, parg); + if (res < 0) + goto error; + if (_IOC_DIR(cmd) & _IOC_READ) + if (copy_to_user((void __user *)arg, parg, _IOC_SIZE(cmd))) + res = -EFAULT; +error: + kfree(pbuf); + return res; +} + +struct page *ngene_nopage(struct vm_area_struct *vma, + unsigned long address, int *type) +{ + return 0; +} + +static int ngene_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct dvb_device *dvbdev = file->private_data; + struct ngene_channel *chan = dvbdev->priv; + struct ngene *dev = chan->dev; + + unsigned long size = vma->vm_end - vma->vm_start; + unsigned long off = vma->vm_pgoff << PAGE_SHIFT; + unsigned long padr = pci_resource_start(dev->pci_dev, 0) + off; + unsigned long psize = pci_resource_len(dev->pci_dev, 0) - off; + + if (size > psize) + return -EINVAL; + + if (io_remap_pfn_range(vma, vma->vm_start, padr >> PAGE_SHIFT, size, + vma->vm_page_prot)) + return -EAGAIN; + return 0; +} + +static int write_uart(struct ngene *dev, u8 *data, int len) +{ + struct ngene_command com; + + com.cmd.hdr.Opcode = CMD_WRITE_UART; + com.cmd.hdr.Length = len; + memcpy(com.cmd.WriteUart.Data, data, len); + com.cmd.WriteUart.Data[len] = 0; + com.cmd.WriteUart.Data[len + 1] = 0; + com.in_len = len; + com.out_len = 0; + + if (ngene_command(dev, &com) < 0) + return -EIO; + + return 0; +} + +static int send_cli(struct ngene *dev, char *cmd) +{ + /* printk(KERN_INFO DEVICE_NAME ": %s", cmd); */ + return write_uart(dev, cmd, strlen(cmd)); +} + +static int send_cli_val(struct ngene *dev, char *cmd, u32 val) +{ + char s[32]; + + snprintf(s, 32, "%s %d\n", cmd, val); + /* printk(KERN_INFO DEVICE_NAME ": %s", s); */ + return write_uart(dev, s, strlen(s)); +} + +static int ngene_command_write_uart_user(struct ngene *dev, + const u8 *data, int len) +{ + struct ngene_command com; + + dev->tx_busy = 1; + com.cmd.hdr.Opcode = CMD_WRITE_UART; + com.cmd.hdr.Length = len; + + if (copy_from_user(com.cmd.WriteUart.Data, data, len)) + return -EFAULT; + com.in_len = len; + com.out_len = 0; + + if (ngene_command(dev, &com) < 0) + return -EIO; + + return 0; +} + +static ssize_t uart_write(struct file *file, const char *buf, + size_t count, loff_t *ppos) +{ + struct dvb_device *dvbdev = file->private_data; + struct ngene_channel *chan = dvbdev->priv; + struct ngene *dev = chan->dev; + int len, ret = 0; + size_t left = count; + + while (left) { + len = left; + if (len > 250) + len = 250; + ret = wait_event_interruptible(dev->tx_wq, dev->tx_busy == 0); + if (ret < 0) + return ret; + ngene_command_write_uart_user(dev, buf, len); + left -= len; + buf += len; + } + return count; +} + +static ssize_t ts_write(struct file *file, const char *buf, + size_t count, loff_t *ppos) +{ + struct dvb_device *dvbdev = file->private_data; + struct ngene_channel *chan = dvbdev->priv; + struct ngene *dev = chan->dev; + + if (wait_event_interruptible(dev->tsout_rbuf.queue, + dvb_ringbuffer_free + (&dev->tsout_rbuf) >= count) < 0) + return 0; + + dvb_ringbuffer_write(&dev->tsout_rbuf, buf, count); + + return count; +} + +static ssize_t uart_read(struct file *file, char *buf, + size_t count, loff_t *ppos) +{ + struct dvb_device *dvbdev = file->private_data; + struct ngene_channel *chan = dvbdev->priv; + struct ngene *dev = chan->dev; + int left; + int wp, rp, avail, len; + + if (!dev->uart_rbuf) + return -EINVAL; + if (count > 128) + count = 128; + left = count; + while (left) { + if (wait_event_interruptible(dev->rx_wq, + dev->uart_wp != dev->uart_rp) < 0) + return -EAGAIN; + wp = dev->uart_wp; + rp = dev->uart_rp; + avail = (wp - rp); + + if (avail < 0) + avail += UART_RBUF_LEN; + if (avail > left) + avail = left; + if (wp < rp) { + len = UART_RBUF_LEN - rp; + if (len > avail) + len = avail; + if (copy_to_user(buf, dev->uart_rbuf + rp, len)) + return -EFAULT; + if (len < avail) + if (copy_to_user(buf + len, dev->uart_rbuf, + avail - len)) + return -EFAULT; + } else { + if (copy_to_user(buf, dev->uart_rbuf + rp, avail)) + return -EFAULT; + } + dev->uart_rp = (rp + avail) % UART_RBUF_LEN; + left -= avail; + buf += avail; + } + return count; +} + +static const struct file_operations command_fops = { + .owner = THIS_MODULE, + .read = uart_read, + .write = ts_write, + .ioctl = command_ioctl, + .open = dvb_generic_open, + .release = dvb_generic_release, + .poll = 0, + .mmap = ngene_mmap, +}; + +static struct dvb_device dvbdev_command = { + .priv = 0, + .readers = -1, + .writers = -1, + .users = -1, + .fops = &command_fops, +}; + +#endif + +/****************************************************************************/ +/* DVB functions and API interface ******************************************/ +/****************************************************************************/ + +static void swap_buffer(u32 *p, u32 len) +{ + while (len) { + *p = swab32(*p); + p++; + len -= 4; + } +} + +static void *ain_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags) +{ + struct ngene_channel *chan = priv; + struct ngene *dev = chan->dev; + + if (dvb_ringbuffer_free(&dev->ain_rbuf) >= len) { + dvb_ringbuffer_write(&dev->ain_rbuf, buf, len); + wake_up_interruptible(&dev->ain_rbuf.queue); + } else + printk(KERN_INFO DEVICE_NAME ": Dropped ain packet.\n"); + + return 0; +} + +static void *vcap_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags) +{ + + struct ngene_channel *chan = priv; + struct ngene *dev = chan->dev; + + if (len >= 1920 * 1080) + len = 1920 * 1080; + if (dvb_ringbuffer_free(&dev->vin_rbuf) >= len) { + dvb_ringbuffer_write(&dev->vin_rbuf, buf, len); + wake_up_interruptible(&dev->vin_rbuf.queue); + } else { + ;/*printk(KERN_INFO DEVICE_NAME ": Dropped vcap packet.\n"); */ + } + return 0; +} + +static void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags) +{ + struct ngene_channel *chan = priv; + + + dvb_dmx_swfilter(&chan->demux, buf, len); + return 0; +} + +u8 fill_ts[188] = { 0x47, 0x1f, 0xff, 0x10 }; + +static void *tsout_exchange(void *priv, void *buf, u32 len, + u32 clock, u32 flags) +{ + struct ngene_channel *chan = priv; + struct ngene *dev = chan->dev; + u32 alen; + + alen = dvb_ringbuffer_avail(&dev->tsout_rbuf); + alen -= alen % 188; + + if (alen < len) + FillTSBuffer(buf + alen, len - alen, flags); + else + alen = len; + dvb_ringbuffer_read(&dev->tsout_rbuf, buf, alen); + if (flags & DF_SWAP32) + swap_buffer((u32 *)buf, alen); + wake_up_interruptible(&dev->tsout_rbuf.queue); + return buf; +} + +static void set_dto(struct ngene_channel *chan, u32 rate) +{ + u64 val = rate * 0x89705f41ULL; /* times val for 2^26 Hz */ + + val = ((val >> 25) + 1) >> 1; + chan->AudioDTOValue = (u32) val; + /* chan->AudioDTOUpdated=1; */ + /* printk(KERN_INFO DEVICE_NAME ": Setting DTO to %08x\n", val); */ +} + +static void set_transfer(struct ngene_channel *chan, int state) +{ + u8 control = 0, mode = 0, flags = 0; + struct ngene *dev = chan->dev; + int ret; + + /* + if (chan->running) + return; + */ + + /* + printk(KERN_INFO DEVICE_NAME ": st %d\n", state); + msleep(100); + */ + + if (state) { + if (chan->running) { + printk(KERN_INFO DEVICE_NAME ": already running\n"); + return; + } + } else { + if (!chan->running) { + printk(KERN_INFO DEVICE_NAME ": already stopped\n"); + return; + } + } + + if (dev->card_info->switch_ctrl) + dev->card_info->switch_ctrl(chan, 1, state ^ 1); + + if (state) { + spin_lock_irq(&chan->state_lock); + + /* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n", + ngreadl(0x9310)); */ + my_dvb_ringbuffer_flush(&dev->tsout_rbuf); + control = 0x80; + if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) { + chan->Capture1Length = 512 * 188; + mode = SMODE_TRANSPORT_STREAM; + } + if (chan->mode & NGENE_IO_TSOUT) { + chan->pBufferExchange = tsout_exchange; + /* 0x66666666 = 50MHz *2^33 /250MHz */ + chan->AudioDTOValue = 0x66666666; + /* set_dto(chan, 38810700+1000); */ + /* set_dto(chan, 19392658); */ + } + if (chan->mode & NGENE_IO_TSIN) + chan->pBufferExchange = tsin_exchange; + /* ngwritel(0, 0x9310); */ + spin_unlock_irq(&chan->state_lock); + } else + ;/* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n", + ngreadl(0x9310)); */ + + ret = ngene_command_stream_control(dev, chan->number, + control, mode, flags); + if (!ret) + chan->running = state; + else + printk(KERN_ERR DEVICE_NAME ": set_transfer %d failed\n", + state); + if (!state) { + spin_lock_irq(&chan->state_lock); + chan->pBufferExchange = 0; + my_dvb_ringbuffer_flush(&dev->tsout_rbuf); + spin_unlock_irq(&chan->state_lock); + } +} + +static int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed) +{ + struct dvb_demux *dvbdmx = dvbdmxfeed->demux; + struct ngene_channel *chan = dvbdmx->priv; + struct ngene *dev = chan->dev; + + if (dev->card_info->io_type[chan->number] & NGENE_IO_TSOUT) { + switch (dvbdmxfeed->pes_type) { + case DMX_TS_PES_VIDEO: + send_cli_val(dev, "vpid", dvbdmxfeed->pid); + send_cli(dev, "res 1080i50\n"); + /* send_cli(dev, "vdec mpeg2\n"); */ + break; + + case DMX_TS_PES_AUDIO: + send_cli_val(dev, "apid", dvbdmxfeed->pid); + send_cli(dev, "start\n"); + break; + + case DMX_TS_PES_PCR: + send_cli_val(dev, "pcrpid", dvbdmxfeed->pid); + break; + + default: + break; + } + + } + + if (chan->users == 0) { + set_transfer(chan, 1); + /* msleep(10); */ + } + + return ++chan->users; +} + +static int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed) +{ + struct dvb_demux *dvbdmx = dvbdmxfeed->demux; + struct ngene_channel *chan = dvbdmx->priv; + struct ngene *dev = chan->dev; + + if (dev->card_info->io_type[chan->number] & NGENE_IO_TSOUT) { + switch (dvbdmxfeed->pes_type) { + case DMX_TS_PES_VIDEO: + send_cli(dev, "stop\n"); + break; + + case DMX_TS_PES_AUDIO: + break; + + case DMX_TS_PES_PCR: + break; + + default: + break; + } + + } + + if (--chan->users) + return chan->users; + + set_transfer(chan, 0); + + return 0; +} + +static int write_demod(struct i2c_adapter *adapter, u8 adr, u16 reg, u16 data) +{ + u8 mm[5] = { 0x10, (reg >> 8) & 0xff, reg & 0xff, + (data >> 8) & 0xff, data & 0xff}; + struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = mm, .len = 5 }; + + if (i2c_transfer(adapter, &msg, 1) != 1) { + printk(KERN_ERR DEVICE_NAME ": error in write_demod\n"); + return -1; + } + return 0; +} + + +static int ngene_drxd_pll_set(struct ngene_channel *chan, + u8 *pll, u8 *aux, u8 plladr) +{ + struct i2c_adapter *adap = &chan->i2c_adapter; + struct i2c_msg msg_pll = {.addr = plladr, .flags = 0, .buf = pll, + .len = 4}; + struct i2c_msg msg_aux = {.addr = plladr, .flags = 0, .buf = aux, + .len = 2}; + int err = 0; + + if (chan->dev->card_info->i2c_access & 1) + down(&chan->dev->pll_mutex); + + chan->fe->ops.i2c_gate_ctrl(chan->fe, 1); + err = i2c_transfer(adap, &msg_pll, 1); + if (err != 1) + goto error; + if (aux) + err = i2c_transfer(adap, &msg_aux, 1); +error: + chan->fe->ops.i2c_gate_ctrl(chan->fe, 0); + if (chan->dev->card_info->i2c_access & 1) + up(&chan->dev->pll_mutex); + return err; +} + +static int ngene_pll_set_th_dtt7520x(void *priv, void *priv_params, + u8 plladr, u8 dadr, s32 *off) +{ + struct dvb_frontend_parameters *params = priv_params; + struct ngene_channel *chan = priv; + + u32 freq = params->frequency; + u8 pll[4], aux[2]; + u8 c1, c2; + u32 div; + + if (freq < 185000000 || freq > 900000000) + return -EINVAL; + + if (freq < 465000000) + c2 = 0x12; + else + c2 = 0x18; + + if (freq < 305000000) + c1 = 0xb4; + else if (freq < 405000000) + c1 = 0xbc; + else if (freq < 445000000) + c1 = 0xf4; + else if (freq < 465000000) + c1 = 0xfc; + else if (freq < 735000000) + c1 = 0xbc; + else if (freq < 835000000) + c1 = 0xf4; + else + c1 = 0xfc; + + if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) + c2 ^= 0x10; + + div = (freq + 36000000 + 166667 / 2) / 166667; + *off = ((s32) div) * 166667 - (s32) freq - 36000000; + + pll[0] = (div >> 8) & 0x7f; + pll[1] = div & 0xff; + pll[2] = c1; + pll[3] = c2; + + aux[0] = (c1 & 0xc7) | 0x98; + aux[1] = 0x30; + + return ngene_drxd_pll_set(chan, pll, aux, plladr); +} + +static int ngene_pll_set_mt_3x0823(void *priv, + void *priv_params, + u8 plladr, u8 dadr, s32 *off) +{ + struct dvb_frontend_parameters *params = priv_params; + struct ngene_channel *chan = priv; + struct i2c_adapter *adap = &chan->i2c_adapter; + u32 freq = params->frequency; + u8 pll[4]; + u8 aux[2]; + u8 c1, c2; + u32 div; + + if (freq < 47125000 || freq > 855250000) + return -EINVAL; + else if (freq < 120000000) { + c1 = 0xcc; + c2 = 0x01; + } else if (freq < 155500000) { + c1 = 0xfc; + c2 = 0x01; + } else if (freq < 300000000) { + c1 = 0xbc; + c2 = 0x02; + } else if (freq < 467000000) { + c1 = 0xcc; + c2 = 0x02; + } else { + c1 = 0xcc; + c2 = 0x04; + } + + if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) + c2 |= 0x08; + +#define INTERFREQ (36000000) + + div = (freq + INTERFREQ + 166667 / 2) / 166667; + + *off = ((s32) div) * 166667 - (s32) freq - INTERFREQ; + + pll[0] = (div >> 8) & 0x7f; + pll[1] = div & 0xff; + pll[2] = c1; + pll[3] = c2; + + aux[0] = (c1 & 0xc7) | 0x98; + aux[1] = 0x20; + + write_demod(adap, dadr, 0x1007, 0xc27); + + switch (params->u.ofdm.bandwidth) { + case BANDWIDTH_7_MHZ: + write_demod(adap, dadr, 0x0020, 0x103); + break; + case BANDWIDTH_AUTO: + case BANDWIDTH_8_MHZ: + write_demod(adap, dadr, 0x0020, 0x003); + break; + case BANDWIDTH_6_MHZ: + write_demod(adap, dadr, 0x0020, 0x002); + /*write_demod(adap, dadr, 0x1022, 397);*/ + break; + } + + return ngene_drxd_pll_set(chan, pll, aux, plladr); + +} + +static s16 osc_deviation(void *priv, s16 deviation, int flag) +{ + struct ngene_channel *chan = priv; + struct i2c_adapter *adap = &chan->i2c_adapter; + u16 data = 0; + + if (flag) { + data = (u16) deviation; + printk(KERN_INFO DEVICE_NAME ": write deviation %d\n", + deviation); + eeprom_write_ushort(adap, 0x1000 + chan->number, data); + } else { + if (eeprom_read_ushort(adap, 0x1000 + chan->number, &data)) + data = 0; + printk(KERN_INFO DEVICE_NAME ": read deviation %d\n", + (s16) data); + } + + return (s16) data; +} + +static int write_to_decoder(struct dvb_demux_feed *feed, + const u8 *buf, size_t len) +{ + struct dvb_demux *dvbdmx = feed->demux; + struct ngene_channel *chan = dvbdmx->priv; + struct ngene *dev = chan->dev; + + if (wait_event_interruptible(dev->tsout_rbuf.queue, + dvb_ringbuffer_free + (&dev->tsout_rbuf) >= len) < 0) + return 0; + + dvb_ringbuffer_write(&dev->tsout_rbuf, buf, len); + + return len; +} + +static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id, + int (*start_feed)(struct dvb_demux_feed *), + int (*stop_feed)(struct dvb_demux_feed *), + void *priv) +{ + dvbdemux->priv = priv; + + dvbdemux->filternum = 256; + dvbdemux->feednum = 256; + dvbdemux->start_feed = start_feed; + dvbdemux->stop_feed = stop_feed; + dvbdemux->write_to_decoder = 0; + dvbdemux->dmx.capabilities = (DMX_TS_FILTERING | + DMX_SECTION_FILTERING | + DMX_MEMORY_BASED_FILTERING); + return dvb_dmx_init(dvbdemux); +} + +static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev, + struct dvb_demux *dvbdemux, + struct dmx_frontend *hw_frontend, + struct dmx_frontend *mem_frontend, + struct dvb_adapter *dvb_adapter) +{ + int ret; + + dmxdev->filternum = 256; + dmxdev->demux = &dvbdemux->dmx; + dmxdev->capabilities = 0; + ret = dvb_dmxdev_init(dmxdev, dvb_adapter); + if (ret < 0) + return ret; + + hw_frontend->source = DMX_FRONTEND_0; + dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend); + mem_frontend->source = DMX_MEMORY_FE; + dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend); + return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend); +} + +/****************************************************************************/ +/* Decypher firmware loading ************************************************/ +/****************************************************************************/ + +#define DECYPHER_FW "decypher.fw" + +static int dec_ts_send(struct ngene *dev, u8 *buf, u32 len) +{ + while (dvb_ringbuffer_free(&dev->tsout_rbuf) < len) + msleep(1); + + + dvb_ringbuffer_write(&dev->tsout_rbuf, buf, len); + + return len; +} + +u8 dec_fw_fill_ts[188] = { 0x47, 0x09, 0x0e, 0x10, 0xff, 0xff, 0x00, 0x00 }; + +int dec_fw_send(struct ngene *dev, u8 *fw, u32 size) +{ + struct ngene_channel *chan = &dev->channel[4]; + u32 len = 180, cc = 0; + u8 buf[8] = { 0x47, 0x09, 0x0e, 0x10, 0x00, 0x00, 0x00, 0x00 }; + + set_transfer(chan, 1); + msleep(100); + while (size) { + len = 180; + if (len > size) + len = size; + buf[3] = 0x10 | (cc & 0x0f); + buf[4] = (cc >> 8); + buf[5] = cc & 0xff; + buf[6] = len; + + dec_ts_send(dev, buf, 8); + dec_ts_send(dev, fw, len); + if (len < 180) + dec_ts_send(dev, dec_fw_fill_ts + len + 8, 180 - len); + cc++; + size -= len; + fw += len; + } + for (len = 0; len < 512; len++) + dec_ts_send(dev, dec_fw_fill_ts, 188); + while (dvb_ringbuffer_avail(&dev->tsout_rbuf)) + msleep(10); + msleep(100); + set_transfer(chan, 0); + return 0; +} + +int dec_fw_boot(struct ngene *dev) +{ + u32 size; + const struct firmware *fw = NULL; + u8 *dec_fw; + char *fw_name; + int err, version; + + if (request_firmware(&fw, DECYPHER_FW, &dev->pci_dev->dev) < 0) { + printk(KERN_ERR DEVICE_NAME + ": %s not found. Check hotplug directory.\n", + DECYPHER_FW); + return -1; + } + printk(KERN_INFO DEVICE_NAME ": Booting decypher firmware file %s\n", + DECYPHER_FW); + + size = fw->size; + dec_fw = fw->data; + dec_fw_send(dev, dec_fw, size); + release_firmware(fw); + return 0; +} + +/****************************************************************************/ +/* nGene hardware init and release functions ********************************/ +/****************************************************************************/ + +void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb) +{ + struct SBufferHeader *Cur = rb->Head; + u32 j; + + if (!Cur) + return; + + for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) { + if (Cur->Buffer1) + pci_free_consistent(dev->pci_dev, + rb->Buffer1Length, + Cur->Buffer1, + Cur->scList1->Address); + + if (Cur->Buffer2) + pci_free_consistent(dev->pci_dev, + rb->Buffer2Length, + Cur->Buffer2, + Cur->scList2->Address); + } + + if (rb->SCListMem) + pci_free_consistent(dev->pci_dev, rb->SCListMemSize, + rb->SCListMem, rb->PASCListMem); + + pci_free_consistent(dev->pci_dev, rb->MemSize, rb->Head, rb->PAHead); +} + +void free_idlebuffer(struct ngene *dev, + struct SRingBufferDescriptor *rb, + struct SRingBufferDescriptor *tb) +{ + int j; + struct SBufferHeader *Cur = tb->Head; + + if (!rb->Head) + return; + free_ringbuffer(dev, rb); + for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) { + Cur->Buffer2 = 0; + Cur->scList2 = 0; + Cur->ngeneBuffer.Address_of_first_entry_2 = 0; + Cur->ngeneBuffer.Number_of_entries_2 = 0; + } +} + +void free_common_buffers(struct ngene *dev) +{ + u32 i; + struct ngene_channel *chan; + + for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) { + chan = &dev->channel[i]; + free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer); + free_ringbuffer(dev, &chan->RingBuffer); + free_ringbuffer(dev, &chan->TSRingBuffer); + } + + if (dev->OverflowBuffer) + pci_free_consistent(dev->pci_dev, + OVERFLOW_BUFFER_SIZE, + dev->OverflowBuffer, dev->PAOverflowBuffer); + + if (dev->FWInterfaceBuffer) + pci_free_consistent(dev->pci_dev, + 4096, + dev->FWInterfaceBuffer, + dev->PAFWInterfaceBuffer); +} + +/****************************************************************************/ +/* Ring buffer handling *****************************************************/ +/****************************************************************************/ + +int create_ring_buffer(struct pci_dev *pci_dev, + struct SRingBufferDescriptor *descr, u32 NumBuffers) +{ + dma_addr_t tmp; + struct SBufferHeader *Head; + u32 i; + u32 MemSize = SIZEOF_SBufferHeader * NumBuffers; + u64 PARingBufferHead; + u64 PARingBufferCur; + u64 PARingBufferNext; + struct SBufferHeader *Cur, *Next; + + descr->Head = 0; + descr->MemSize = 0; + descr->PAHead = 0; + descr->NumBuffers = 0; + + if (MemSize < 4096) + MemSize = 4096; + + Head = pci_alloc_consistent(pci_dev, MemSize, &tmp); + PARingBufferHead = tmp; + + if (!Head) + return -ENOMEM; + + memset(Head, 0, MemSize); + + PARingBufferCur = PARingBufferHead; + Cur = Head; + + for (i = 0; i < NumBuffers - 1; i++) { + Next = (struct SBufferHeader *) + (((u8 *) Cur) + SIZEOF_SBufferHeader); + PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader; + Cur->Next = Next; + Cur->ngeneBuffer.Next = PARingBufferNext; + Cur = Next; + PARingBufferCur = PARingBufferNext; + } + /* Last Buffer points back to first one */ + Cur->Next = Head; + Cur->ngeneBuffer.Next = PARingBufferHead; + + descr->Head = Head; + descr->MemSize = MemSize; + descr->PAHead = PARingBufferHead; + descr->NumBuffers = NumBuffers; + + return 0; +} + +static int AllocateRingBuffers(struct pci_dev *pci_dev, + dma_addr_t of, + struct SRingBufferDescriptor *pRingBuffer, + u32 Buffer1Length, u32 Buffer2Length) +{ + dma_addr_t tmp; + u32 i, j; + int status = 0; + u32 SCListMemSize = pRingBuffer->NumBuffers + * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) : + NUM_SCATTER_GATHER_ENTRIES) + * sizeof(struct HW_SCATTER_GATHER_ELEMENT); + + u64 PASCListMem; + PHW_SCATTER_GATHER_ELEMENT SCListEntry; + u64 PASCListEntry; + struct SBufferHeader *Cur; + void *SCListMem; + + if (SCListMemSize < 4096) + SCListMemSize = 4096; + + SCListMem = pci_alloc_consistent(pci_dev, SCListMemSize, &tmp); + + PASCListMem = tmp; + if (SCListMem == NULL) + return -ENOMEM; + + memset(SCListMem, 0, SCListMemSize); + + pRingBuffer->SCListMem = SCListMem; + pRingBuffer->PASCListMem = PASCListMem; + pRingBuffer->SCListMemSize = SCListMemSize; + pRingBuffer->Buffer1Length = Buffer1Length; + pRingBuffer->Buffer2Length = Buffer2Length; + + SCListEntry = (PHW_SCATTER_GATHER_ELEMENT) SCListMem; + PASCListEntry = PASCListMem; + Cur = pRingBuffer->Head; + + for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) { + u64 PABuffer; + + void *Buffer = pci_alloc_consistent(pci_dev, Buffer1Length, + &tmp); + PABuffer = tmp; + + if (Buffer == NULL) + return -ENOMEM; + + Cur->Buffer1 = Buffer; + + SCListEntry->Address = PABuffer; + SCListEntry->Length = Buffer1Length; + + Cur->scList1 = SCListEntry; + Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry; + Cur->ngeneBuffer.Number_of_entries_1 = + NUM_SCATTER_GATHER_ENTRIES; + + SCListEntry += 1; + PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT); + +#if NUM_SCATTER_GATHER_ENTRIES > 1 + for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) { + SCListEntry->Address = of; + SCListEntry->Length = OVERFLOW_BUFFER_SIZE; + SCListEntry += 1; + PASCListEntry += + sizeof(struct HW_SCATTER_GATHER_ELEMENT); + } +#endif + + if (!Buffer2Length) + continue; + + Buffer = pci_alloc_consistent(pci_dev, Buffer2Length, &tmp); + PABuffer = tmp; + + if (Buffer == NULL) + return -ENOMEM; + + Cur->Buffer2 = Buffer; + + SCListEntry->Address = PABuffer; + SCListEntry->Length = Buffer2Length; + + Cur->scList2 = SCListEntry; + Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry; + Cur->ngeneBuffer.Number_of_entries_2 = + NUM_SCATTER_GATHER_ENTRIES; + + SCListEntry += 1; + PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT); + +#if NUM_SCATTER_GATHER_ENTRIES > 1 + for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) { + SCListEntry->Address = of; + SCListEntry->Length = OVERFLOW_BUFFER_SIZE; + SCListEntry += 1; + PASCListEntry += + sizeof(struct HW_SCATTER_GATHER_ELEMENT); + } +#endif + + } + + return status; +} + +static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer, + struct SRingBufferDescriptor *pRingBuffer) +{ + int status = 0; + + /* Copy pointer to scatter gather list in TSRingbuffer + structure for buffer 2 + Load number of buffer + */ + u32 n = pRingBuffer->NumBuffers; + + /* Point to first buffer entry */ + struct SBufferHeader *Cur = pRingBuffer->Head; + int i; + /* Loop thru all buffer and set Buffer 2 pointers to TSIdlebuffer */ + for (i = 0; i < n; i++) { + Cur->Buffer2 = pIdleBuffer->Head->Buffer1; + Cur->scList2 = pIdleBuffer->Head->scList1; + Cur->ngeneBuffer.Address_of_first_entry_2 = + pIdleBuffer->Head->ngeneBuffer. + Address_of_first_entry_1; + Cur->ngeneBuffer.Number_of_entries_2 = + pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1; + Cur = Cur->Next; + } + return status; +} + +static u32 RingBufferSizes[MAX_STREAM] = { + RING_SIZE_VIDEO, + RING_SIZE_VIDEO, + RING_SIZE_AUDIO, + RING_SIZE_AUDIO, + RING_SIZE_AUDIO, +}; + +static u32 Buffer1Sizes[MAX_STREAM] = { + MAX_VIDEO_BUFFER_SIZE, + MAX_VIDEO_BUFFER_SIZE, + MAX_AUDIO_BUFFER_SIZE, + MAX_AUDIO_BUFFER_SIZE, + MAX_AUDIO_BUFFER_SIZE +}; + +static u32 Buffer2Sizes[MAX_STREAM] = { + MAX_VBI_BUFFER_SIZE, + MAX_VBI_BUFFER_SIZE, + 0, + 0, + 0 +}; + +static int allocate_buffer(struct pci_dev *pci_dev, dma_addr_t of, + struct SRingBufferDescriptor *rbuf, + u32 entries, u32 size1, u32 size2) +{ + if (create_ring_buffer(pci_dev, rbuf, entries) < 0) + return -ENOMEM; + + if (AllocateRingBuffers(pci_dev, of, rbuf, size1, size2) < 0) + return -ENOMEM; + + return 0; +} + +static int channel_allocate_buffers(struct ngene_channel *chan) +{ + struct ngene *dev = chan->dev; + int type = dev->card_info->io_type[chan->number]; + int status; + + chan->State = KSSTATE_STOP; + + if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) { + status = create_ring_buffer(dev->pci_dev, + &chan->RingBuffer, + RingBufferSizes[chan->number]); + if (status < 0) + return -ENOMEM; + + if (type & (NGENE_IO_TV | NGENE_IO_AIN)) { + status = AllocateRingBuffers(dev->pci_dev, + dev->PAOverflowBuffer, + &chan->RingBuffer, + Buffer1Sizes[chan->number], + Buffer2Sizes[chan-> + number]); + if (status < 0) + return -ENOMEM; + } else if (type & NGENE_IO_HDTV) { + status = AllocateRingBuffers(dev->pci_dev, + dev->PAOverflowBuffer, + &chan->RingBuffer, + MAX_HDTV_BUFFER_SIZE, 0); + if (status < 0) + return -ENOMEM; + } + } + + if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) { + + status = create_ring_buffer(dev->pci_dev, + &chan->TSRingBuffer, RING_SIZE_TS); + if (status < 0) + return -ENOMEM; + + status = AllocateRingBuffers(dev->pci_dev, + dev->PAOverflowBuffer, + &chan->TSRingBuffer, + MAX_TS_BUFFER_SIZE, 0); + if (status) + return -ENOMEM; + } + + if (type & NGENE_IO_TSOUT) { + status = create_ring_buffer(dev->pci_dev, + &chan->TSIdleBuffer, 1); + if (status < 0) + return -ENOMEM; + status = AllocateRingBuffers(dev->pci_dev, + dev->PAOverflowBuffer, + &chan->TSIdleBuffer, + MAX_TS_BUFFER_SIZE, 0); + if (status) + return -ENOMEM; + FillTSIdleBuffer(&chan->TSIdleBuffer, &chan->TSRingBuffer); + } + return 0; +} + +static int AllocCommonBuffers(struct ngene *dev) +{ + int status = 0, i; + + dev->FWInterfaceBuffer = pci_alloc_consistent(dev->pci_dev, 4096, + &dev->PAFWInterfaceBuffer); + if (!dev->FWInterfaceBuffer) + return -ENOMEM; + dev->hosttongene = dev->FWInterfaceBuffer; + dev->ngenetohost = dev->FWInterfaceBuffer + 256; + dev->EventBuffer = dev->FWInterfaceBuffer + 512; + + dev->OverflowBuffer = pci_alloc_consistent(dev->pci_dev, + OVERFLOW_BUFFER_SIZE, + &dev->PAOverflowBuffer); + if (!dev->OverflowBuffer) + return -ENOMEM; + memset(dev->OverflowBuffer, 0, OVERFLOW_BUFFER_SIZE); + + for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) { + int type = dev->card_info->io_type[i]; + + dev->channel[i].State = KSSTATE_STOP; + + if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) { + status = create_ring_buffer(dev->pci_dev, + &dev->channel[i].RingBuffer, + RingBufferSizes[i]); + if (status < 0) + break; + + if (type & (NGENE_IO_TV | NGENE_IO_AIN)) { + status = AllocateRingBuffers(dev->pci_dev, + dev-> + PAOverflowBuffer, + &dev->channel[i]. + RingBuffer, + Buffer1Sizes[i], + Buffer2Sizes[i]); + if (status < 0) + break; + } else if (type & NGENE_IO_HDTV) { + status = AllocateRingBuffers(dev->pci_dev, + dev-> + PAOverflowBuffer, + &dev->channel[i]. + RingBuffer, + MAX_HDTV_BUFFER_SIZE, + 0); + if (status < 0) + break; + } + } + + if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) { + + status = create_ring_buffer(dev->pci_dev, + &dev->channel[i]. + TSRingBuffer, RING_SIZE_TS); + if (status < 0) + break; + + status = AllocateRingBuffers(dev->pci_dev, + dev->PAOverflowBuffer, + &dev->channel[i]. + TSRingBuffer, + MAX_TS_BUFFER_SIZE, 0); + if (status) + break; + } + + if (type & NGENE_IO_TSOUT) { + status = create_ring_buffer(dev->pci_dev, + &dev->channel[i]. + TSIdleBuffer, 1); + if (status < 0) + break; + status = AllocateRingBuffers(dev->pci_dev, + dev->PAOverflowBuffer, + &dev->channel[i]. + TSIdleBuffer, + MAX_TS_BUFFER_SIZE, 0); + if (status) + break; + FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer, + &dev->channel[i].TSRingBuffer); + } + } + return status; +} + +static void ngene_release_buffers(struct ngene *dev) +{ + if (dev->iomem) + iounmap(dev->iomem); + free_common_buffers(dev); + vfree(dev->tsout_buf); + vfree(dev->ain_buf); + vfree(dev->vin_buf); + vfree(dev); +} + +static int ngene_get_buffers(struct ngene *dev) +{ + if (AllocCommonBuffers(dev)) + return -ENOMEM; + if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) { + dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE); + if (!dev->tsout_buf) + return -ENOMEM; + dvb_ringbuffer_init(&dev->tsout_rbuf, + dev->tsout_buf, TSOUT_BUF_SIZE); + } + if (dev->card_info->io_type[2] & NGENE_IO_AIN) { + dev->ain_buf = vmalloc(AIN_BUF_SIZE); + if (!dev->ain_buf) + return -ENOMEM; + dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE); + } + if (dev->card_info->io_type[0] & NGENE_IO_HDTV) { + dev->vin_buf = vmalloc(VIN_BUF_SIZE); + if (!dev->vin_buf) + return -ENOMEM; + dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE); + } + dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0), + pci_resource_len(dev->pci_dev, 0)); + if (!dev->iomem) + return -ENOMEM; + + return 0; +} + +static void ngene_init(struct ngene *dev) +{ + int i; + + tasklet_init(&dev->event_tasklet, event_tasklet, (unsigned long)dev); + + memset_io(dev->iomem + 0xc000, 0x00, 0x220); + memset_io(dev->iomem + 0xc400, 0x00, 0x100); + + for (i = 0; i < MAX_STREAM; i++) { + dev->channel[i].dev = dev; + dev->channel[i].number = i; + } + + dev->fw_interface_version = 0; + + ngwritel(0, NGENE_INT_ENABLE); + + dev->icounts = ngreadl(NGENE_INT_COUNTS); + + dev->device_version = ngreadl(DEV_VER) & 0x0f; + printk(KERN_INFO DEVICE_NAME ": Device version %d\n", + dev->device_version); +} + +static int ngene_load_firm(struct ngene *dev) +{ + u32 size; + const struct firmware *fw = NULL; + u8 *ngene_fw; + char *fw_name; + int err, version; + + version = dev->card_info->fw_version; + + switch (version) { + default: + case 15: + version = 15; + ngene_fw = FW15; + size = sizeof(FW15); + fw_name = "ngene_15.fw"; + break; + case 16: + ngene_fw = FW16; + size = sizeof(FW16); + fw_name = "ngene_16.fw"; + break; + case 17: + ngene_fw = FW17; + size = sizeof(FW17); + fw_name = "ngene_17.fw"; + break; + } +#ifdef FW_INC + if (load_firmware && + request_firmware(&fw, fw_name, &dev->pci_dev->dev) >= 0) { + printk(KERN_INFO DEVICE_NAME + ": Loading firmware file %s.\n", fw_name); + size = fw->size; + ngene_fw = fw->data; + } else + printk(KERN_INFO DEVICE_NAME + ": Loading built-in firmware version %d.\n", version); + err = ngene_command_load_firmware(dev, ngene_fw, size); + + if (fw) + release_firmware(fw); +#else + if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) { + printk(KERN_ERR DEVICE_NAME + ": Could not load firmware file %s. \n", fw_name); + printk(KERN_INFO DEVICE_NAME + ": Copy %s to your hotplug directory!\n", fw_name); + return -1; + } + printk(KERN_INFO DEVICE_NAME ": Loading firmware file %s.\n", fw_name); + size = fw->size; + ngene_fw = fw->data; + err = ngene_command_load_firmware(dev, ngene_fw, size); + release_firmware(fw); +#endif + return err; +} + +static void ngene_stop(struct ngene *dev) +{ + down(&dev->cmd_mutex); + i2c_del_adapter(&(dev->channel[0].i2c_adapter)); + i2c_del_adapter(&(dev->channel[1].i2c_adapter)); + ngwritel(0, NGENE_INT_ENABLE); + ngwritel(0, NGENE_COMMAND); + ngwritel(0, NGENE_COMMAND_HI); + ngwritel(0, NGENE_STATUS); + ngwritel(0, NGENE_STATUS_HI); + ngwritel(0, NGENE_EVENT); + ngwritel(0, NGENE_EVENT_HI); + free_irq(dev->pci_dev->irq, dev); +} + +static int ngene_start(struct ngene *dev) +{ + int stat; + int i; + + pci_set_master(dev->pci_dev); + ngene_init(dev); + + stat = request_irq(dev->pci_dev->irq, irq_handler, + IRQF_SHARED, "nGene", + (void *)dev); + if (stat < 0) + return stat; + + init_waitqueue_head(&dev->cmd_wq); + init_waitqueue_head(&dev->tx_wq); + init_waitqueue_head(&dev->rx_wq); + sema_init(&dev->cmd_mutex, 1); + sema_init(&dev->stream_mutex, 1); + sema_init(&dev->pll_mutex, 1); + sema_init(&dev->i2c_switch_mutex, 1); + spin_lock_init(&dev->cmd_lock); + for (i = 0; i < MAX_STREAM; i++) + spin_lock_init(&dev->channel[i].state_lock); + ngwritel(1, TIMESTAMPS); + + ngwritel(1, NGENE_INT_ENABLE); + + stat = ngene_load_firm(dev); + if (stat < 0) + goto fail; + + stat = ngene_i2c_init(dev, 0); + if (stat < 0) + goto fail; + + stat = ngene_i2c_init(dev, 1); + if (stat < 0) + goto fail; + + if (dev->card_info->fw_version == 17) { + u8 hdtv_config[6] = + {6144 / 64, 0, 0, 2048 / 64, 2048 / 64, 2048 / 64}; + u8 tsin4_config[6] = + {3072 / 64, 3072 / 64, 0, 3072 / 64, 3072 / 64, 0}; + u8 ts5_config[6] = + {2048 / 64, 2048 / 64, 0, 2048 / 64, 2048 / 64, + 2048 / 64}; + u8 default_config[6] = + {4096 / 64, 4096 / 64, 0, 2048 / 64, 2048 / 64, 0}; + u8 *bconf = default_config; + + if (dev->card_info->io_type[3] == NGENE_IO_TSIN) + bconf = tsin4_config; + if (dev->card_info->io_type[0] == NGENE_IO_HDTV) { + bconf = hdtv_config; + ngene_reset_decypher(dev); + } + printk(KERN_INFO DEVICE_NAME ": FW 17 buffer config\n"); + stat = ngene_command_config_free_buf(dev, bconf); + } else { + int bconf = BUFFER_CONFIG_4422; + + if (dev->card_info->io_type[0] == NGENE_IO_HDTV) { + bconf = BUFFER_CONFIG_8022; + ngene_reset_decypher(dev); + } + if (dev->card_info->io_type[3] == NGENE_IO_TSIN) + bconf = BUFFER_CONFIG_3333; + stat = ngene_command_config_buf(dev, bconf); + } + + if (dev->card_info->io_type[0] == NGENE_IO_HDTV) { + ngene_command_config_uart(dev, 0xc1, tx_cb, rx_cb); + test_dec_i2c(&dev->channel[0].i2c_adapter, 0); + test_dec_i2c(&dev->channel[0].i2c_adapter, 1); + } + + return stat; +fail: + ngwritel(0, NGENE_INT_ENABLE); + free_irq(dev->pci_dev->irq, dev); + return stat; +} + +/****************************************************************************/ +/* DVB audio/video device functions *****************************************/ +/****************************************************************************/ + +static ssize_t audio_write(struct file *file, + const char *buf, size_t count, loff_t *ppos) +{ + return -EINVAL; +} + +ssize_t audio_read(struct file *file, char *buf, size_t count, loff_t *ppos) +{ + struct dvb_device *dvbdev = file->private_data; + struct ngene_channel *chan = dvbdev->priv; + struct ngene *dev = chan->dev; + int left; + int avail; + + left = count; + while (left) { + if (wait_event_interruptible( + dev->ain_rbuf.queue, + dvb_ringbuffer_avail(&dev->ain_rbuf) > 0) < 0) + return -EAGAIN; + avail = dvb_ringbuffer_avail(&dev->ain_rbuf); + if (avail > left) + avail = left; + dvb_ringbuffer_read_user(&dev->ain_rbuf, buf, avail); + left -= avail; + buf += avail; + } + return count; +} + +static int audio_open(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + struct ngene_channel *chan = dvbdev->priv; + struct ngene *dev = chan->dev; + struct ngene_channel *chan2 = &chan->dev->channel[2]; + int ret; + + ret = dvb_generic_open(inode, file); + if (ret < 0) + return ret; + my_dvb_ringbuffer_flush(&dev->ain_rbuf); + + chan2->Capture1Length = MAX_AUDIO_BUFFER_SIZE; + chan2->pBufferExchange = ain_exchange; + ngene_command_stream_control(chan2->dev, chan2->number, 0x80, + SMODE_AUDIO_CAPTURE, 0); + return ret; +} + +static int audio_release(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + struct ngene_channel *chan = dvbdev->priv; + struct ngene *dev = chan->dev; + struct ngene_channel *chan2 = &chan->dev->channel[2]; + + ngene_command_stream_control(dev, 2, 0, 0, 0); + chan2->pBufferExchange = 0; + + return dvb_generic_release(inode, file); +} + +static const struct file_operations audio_fops = { + .owner = THIS_MODULE, + .read = audio_read, + .write = audio_write, + .open = audio_open, + .release = audio_release, +}; + +static struct dvb_device dvbdev_audio = { + .priv = 0, + .readers = -1, + .writers = 1, + .users = 1, + .fops = &audio_fops, +}; + +static int video_open(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + struct ngene_channel *chan = dvbdev->priv; + struct ngene *dev = chan->dev; + struct ngene_channel *chan0 = &chan->dev->channel[0]; + int ret; + + ret = dvb_generic_open(inode, file); + if (ret < 0) + return ret; + if ((file->f_flags & O_ACCMODE) != O_RDONLY) + return ret; + my_dvb_ringbuffer_flush(&dev->vin_rbuf); + + chan0->nBytesPerLine = 1920 * 2; + chan0->nLines = 540; + chan0->Capture1Length = 1920 * 2 * 540; + chan0->pBufferExchange = vcap_exchange; + chan0->itumode = 2; + ngene_command_stream_control(chan0->dev, chan0->number, + 0x80, SMODE_VIDEO_CAPTURE, 0); + return ret; +} + +static int video_release(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + struct ngene_channel *chan = dvbdev->priv; + struct ngene *dev = chan->dev; + struct ngene_channel *chan0 = &chan->dev->channel[0]; + + ngene_command_stream_control(dev, 0, 0, 0, 0); + chan0->pBufferExchange = 0; + + return dvb_generic_release(inode, file); +} + +static ssize_t video_write(struct file *file, + const char *buf, size_t count, loff_t *ppos) +{ + return -EINVAL; +} + +ssize_t video_read(struct file *file, char *buf, size_t count, loff_t *ppos) +{ + struct dvb_device *dvbdev = file->private_data; + struct ngene_channel *chan = dvbdev->priv; + struct ngene *dev = chan->dev; + int left, avail; + + left = count; + while (left) { + if (wait_event_interruptible( + dev->vin_rbuf.queue, + dvb_ringbuffer_avail(&dev->vin_rbuf) > 0) < 0) + return -EAGAIN; + avail = dvb_ringbuffer_avail(&dev->vin_rbuf); + if (avail > left) + avail = left; + dvb_ringbuffer_read_user(&dev->vin_rbuf, buf, avail); + left -= avail; + buf += avail; + } + return count; +} + +/* Why is this not exported from dvb_core ?!?! */ + +static int dvb_usercopy2(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg, + int (*func)(struct inode *inode, struct file *file, + unsigned int cmd, void *arg)) +{ + char sbuf[128]; + void *mbuf = NULL; + void *parg = NULL; + int err = -EINVAL; + + /* Copy arguments into temp kernel buffer */ + switch (_IOC_DIR(cmd)) { + case _IOC_NONE: + /* + * For this command, the pointer is actually an integer + * argument. + */ + parg = (void *)arg; + break; + case _IOC_READ: /* some v4l ioctls are marked wrong ... */ + case _IOC_WRITE: + case (_IOC_WRITE | _IOC_READ): + if (_IOC_SIZE(cmd) <= sizeof(sbuf)) { + parg = sbuf; + } else { + /* too big to allocate from stack */ + mbuf = kmalloc(_IOC_SIZE(cmd), GFP_KERNEL); + if (NULL == mbuf) + return -ENOMEM; + parg = mbuf; + } + + err = -EFAULT; + if (copy_from_user(parg, (void __user *)arg, _IOC_SIZE(cmd))) + goto out; + break; + } + + /* call driver */ + err = func(inode, file, cmd, parg); + if (err == -ENOIOCTLCMD) + err = -EINVAL; + + if (err < 0) + goto out; + + /* Copy results into user buffer */ + switch (_IOC_DIR(cmd)) { + case _IOC_READ: + case (_IOC_WRITE | _IOC_READ): + if (copy_to_user((void __user *)arg, parg, _IOC_SIZE(cmd))) + err = -EFAULT; + break; + } + +out: + kfree(mbuf); + return err; +} + +static int video_do_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, void *parg) +{ + struct dvb_device *dvbdev = file->private_data; + struct ngene_channel *chan = dvbdev->priv; + struct ngene *dev = chan->dev; + int ret = 0; + unsigned long arg = (unsigned long)parg; + + switch (cmd) { + case VIDEO_SET_STREAMTYPE: + switch (arg) { + case VIDEO_CAP_MPEG2: + /* printk(KERN_INFO DEVICE_NAME ": setting MPEG2\n"); */ + send_cli(dev, "vdec mpeg2\n"); + break; + case VIDEO_CAP_AVC: + /* printk(KERN_INFO DEVICE_NAME ": setting H264\n"); */ + send_cli(dev, "vdec h264\n"); + break; + case VIDEO_CAP_VC1: + /* printk(KERN_INFO DEVICE_NAME ": setting VC1\n"); */ + send_cli(dev, "vdec vc1\n"); + break; + default: + ret = -EINVAL; + break; + } + break; + default: + ret = -ENOIOCTLCMD; + return -EINVAL; + } + return ret; +} + +static int video_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + return dvb_usercopy2(inode, file, cmd, arg, video_do_ioctl); +} + +static const struct file_operations video_fops = { + .owner = THIS_MODULE, + .read = video_read, + .write = video_write, + .open = video_open, + .release = video_release, + .ioctl = video_ioctl, +}; + +static struct dvb_device dvbdev_video = { + .priv = 0, + .readers = -1, + .writers = 1, + .users = -1, + .fops = &video_fops, +}; + +/****************************************************************************/ +/* LNBH21 *******************************************************************/ +/****************************************************************************/ + +static int lnbh21_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) +{ + struct ngene_channel *chan = + *(struct ngene_channel **) fe->demodulator_priv; + + switch (voltage) { + case SEC_VOLTAGE_OFF: + chan->lnbh &= 0xf3; + break; + case SEC_VOLTAGE_13: + chan->lnbh |= 0x04; + chan->lnbh &= ~0x08; + break; + case SEC_VOLTAGE_18: + chan->lnbh |= 0x0c; + break; + default: + return -EINVAL; + }; + chan->lnbh |= 0x10; + return i2c_write(&chan->i2c_adapter, + chan->dev->card_info->lnb[chan->number], chan->lnbh); +} + +static int lnbh21_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone) +{ + struct ngene_channel *chan = + *(struct ngene_channel **)fe->demodulator_priv; + + switch (tone) { + case SEC_TONE_ON: + chan->lnbh |= 0x20; + break; + case SEC_TONE_OFF: + chan->lnbh &= 0xdf; + break; + default: + return -EINVAL; + } + return i2c_write(&chan->i2c_adapter, + chan->dev->card_info->lnb[chan->number], chan->lnbh); +} + +/****************************************************************************/ +/* Switch control (I2C gates, etc.) *****************************************/ +/****************************************************************************/ + +static int avf_output(struct ngene_channel *chan, int state) +{ + if (chan->dev->card_info->avf[chan->number]) + i2c_write_register(&chan->i2c_adapter, + chan->dev->card_info->avf[chan->number], + 0xf2, state ? 0x89 : 0x80); + return 0; +} + +/* Viper expander: sw11,sw12,sw21,sw22,i2csw1,i2csw2,tsen1,tsen2 */ + +static int exp_set(struct ngene *dev) +{ + return i2c_write(&dev->channel[0].i2c_adapter, + dev->card_info->exp, dev->exp_val); +} + +static int exp_init(struct ngene *dev) +{ + if (!dev->card_info->exp) + return 0; + dev->exp_val = dev->card_info->exp_init; + return exp_set(dev); +} + +static int exp_set_bit(struct ngene *dev, int bit, int val) +{ + if (val) + set_bit(bit, &dev->exp_val); + else + clear_bit(bit, &dev->exp_val); + return exp_set(dev); +} + +static int viper_switch_ctrl(struct ngene_channel *chan, int type, int val) +{ + switch (type) { + case 0: /* I2C tuner gate on/off */ + return exp_set_bit(chan->dev, 4 + chan->number, val); + case 1: /* Stream: 0=TS 1=ITU */ + avf_output(chan, val); + return exp_set_bit(chan->dev, 6 + chan->number, val); + case 2: /* Input: 0=digital 1=analog antenna input */ + exp_set_bit(chan->dev, 0 + chan->number * 2, val ? 0 : 1); + exp_set_bit(chan->dev, 1 + chan->number * 2, val ? 1 : 0); + break; + } + return 0; +} + +static int viper_switch_ctrl2(struct ngene_channel *chan, int type, int val) +{ + switch (type) { + case 0: /* I2C tuner gate on/off */ + return exp_set_bit(chan->dev, 4 + chan->number, val); + case 1: /* Stream: 0=TS 1=ITU */ + avf_output(chan, val); + return exp_set_bit(chan->dev, 6 + chan->number, val); + case 2: /* Input: 0=digital 1=analog antenna input */ + exp_set_bit(chan->dev, 0 + chan->number * 2, val ? 0 : 1); + exp_set_bit(chan->dev, 1 + chan->number * 2, 0); + break; + } + return 0; +} + +static int viper_gate_ctrl(struct dvb_frontend *fe, int enable) +{ + /* Well, just abuse sec :-) */ + struct ngene_channel *chan = fe->sec_priv; + struct ngene *dev = chan->dev; + + return dev->card_info->switch_ctrl(chan, 0, enable); +} + +static int python_switch_ctrl(struct ngene_channel *chan, int type, int val) +{ + switch (type) { + case 0: /* I2C tuner gate on/off */ + if (chan->number > 1) + return -EINVAL; + return ngene_command_gpio_set(chan->dev, 3 + chan->number, val); + case 1: /* Stream: 0=TS 1=ITU */ + avf_output(chan, val); + return 0; + } + return 0; +} + +static int viper_reset_xc(struct dvb_frontend *fe) +{ + struct ngene_channel *chan = fe->sec_priv; + struct ngene *dev = chan->dev; + + printk(KERN_INFO DEVICE_NAME ": Reset XC3028\n"); + + if (chan->number > 1) + return -EINVAL; + + ngene_command_gpio_set(dev, 3 + chan->number, 0); + msleep(150); + ngene_command_gpio_set(dev, 3 + chan->number, 1); + return 0; +} + +static int python_gate_ctrl(struct dvb_frontend *fe, int enable) +{ + struct ngene_channel *chan = fe->sec_priv; + struct ngene *dev = chan->dev; + + if (chan->number == 0) + return ngene_command_gpio_set(dev, 3, enable); + if (chan->number == 1) + return ngene_command_gpio_set(dev, 4, enable); + return -EINVAL; +} + +/****************************************************************************/ +/* Demod/tuner attachment ***************************************************/ +/****************************************************************************/ + +static int tuner_attach_mt2060(struct ngene_channel *chan) +{ + struct ngene *dev = chan->dev; + void *tconf = dev->card_info->tuner_config[chan->number]; + u8 drxa = dev->card_info->demoda[chan->number]; + struct dvb_frontend *fe = chan->fe, *fe2; + + fe->sec_priv = chan; + fe->ops.i2c_gate_ctrl = dev->card_info->gate_ctrl; + + dev->card_info->gate_ctrl(fe, 1); + fe2 = mt2060_attach(fe, &chan->i2c_adapter, tconf, 1220); + dev->card_info->gate_ctrl(fe, 0); + + i2c_write_register(&chan->i2c_adapter, drxa, 3, 4); + write_demod(&chan->i2c_adapter, drxa, 0x1012, 15); + write_demod(&chan->i2c_adapter, drxa, 0x1007, 0xc27); + write_demod(&chan->i2c_adapter, drxa, 0x0020, 0x003); + + return fe2 ? 0 : -ENODEV; +} + +static int tuner_attach_xc3028(struct ngene_channel *chan) +{ + struct ngene *dev = chan->dev; + void *tconf = dev->card_info->tuner_config[chan->number]; + struct dvb_frontend *fe = chan->fe, *fe2; + + fe->sec_priv = chan; + fe->ops.i2c_gate_ctrl = dev->card_info->gate_ctrl; + + dev->card_info->gate_ctrl(fe, 1); + fe2 = xc3028_attach(fe, &chan->i2c_adapter, tconf); + dev->card_info->gate_ctrl(fe, 0); + + /*chan->fe->ops.tuner_ops.set_frequency(chan->fe,231250000);*/ + + return fe2 ? 0 : -ENODEV; +} + +static int demod_attach_drxd(struct ngene_channel *chan) +{ + void *feconf = chan->dev->card_info->fe_config[chan->number]; + + chan->fe = drxd_attach(feconf, + chan, &chan->i2c_adapter, + &chan->dev->pci_dev->dev); + return (chan->fe) ? 0 : -ENODEV; +} + +static int demod_attach_drxh(struct ngene_channel *chan) +{ + void *feconf = chan->dev->card_info->fe_config[chan->number]; + + chan->fe = drxh_attach(feconf, chan, + &chan->i2c_adapter, &chan->dev->pci_dev->dev); + return (chan->fe) ? 0 : -ENODEV; +} + +static int demod_attach_stb0899(struct ngene_channel *chan) +{ + void *feconf = chan->dev->card_info->fe_config[chan->number]; + + chan->fe = stb0899_attach(feconf, + chan, &chan->i2c_adapter, + &chan->dev->pci_dev->dev); + if (chan->fe) { + chan->set_tone = chan->fe->ops.set_tone; + chan->fe->ops.set_tone = lnbh21_set_tone; + chan->fe->ops.set_voltage = lnbh21_set_voltage; + } + + return (chan->fe) ? 0 : -ENODEV; +} + +static int demod_attach_stv0900(struct ngene_channel *chan) +{ + void *feconf = chan->dev->card_info->fe_config[chan->number]; + + chan->fe = stv0900_attach(feconf, + chan, &chan->i2c_adapter, + &chan->dev->pci_dev->dev); + + if (chan->fe) { + chan->set_tone = chan->fe->ops.set_tone; + chan->fe->ops.set_tone = lnbh21_set_tone; + chan->fe->ops.set_voltage = lnbh21_set_voltage; + } + + return (chan->fe) ? 0 : -ENODEV; +} + +/****************************************************************************/ +/****************************************************************************/ +/****************************************************************************/ + +static void release_channel(struct ngene_channel *chan) +{ + struct dvb_demux *dvbdemux = &chan->demux; + struct ngene *dev = chan->dev; + struct ngene_info *ni = dev->card_info; + int io = ni->io_type[chan->number]; + + tasklet_kill(&chan->demux_tasklet); + + if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) { +#ifdef NGENE_COMMAND_API + if (chan->command_dev) + dvb_unregister_device(chan->command_dev); +#endif + if (chan->audio_dev) + dvb_unregister_device(chan->audio_dev); + if (chan->video_dev) + dvb_unregister_device(chan->video_dev); + if (chan->fe) { + dvb_unregister_frontend(chan->fe); + /*dvb_frontend_detach(chan->fe); */ + chan->fe = 0; + } + dvbdemux->dmx.close(&dvbdemux->dmx); + dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, + &chan->hw_frontend); + dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, + &chan->mem_frontend); + dvb_dmxdev_release(&chan->dmxdev); + dvb_dmx_release(&chan->demux); +#ifndef ONE_ADAPTER + dvb_unregister_adapter(&chan->dvb_adapter); +#endif + } + + if (io & (NGENE_IO_AIN)) { + ngene_snd_exit(chan); + kfree(chan->soundbuffer); + } +} + +static int init_channel(struct ngene_channel *chan) +{ + int ret = 0, nr = chan->number; + struct dvb_adapter *adapter = 0; + struct dvb_demux *dvbdemux = &chan->demux; + struct ngene *dev = chan->dev; + struct ngene_info *ni = dev->card_info; + int io = ni->io_type[nr]; + + tasklet_init(&chan->demux_tasklet, demux_tasklet, (unsigned long)chan); + chan->users = 0; + chan->type = io; + chan->mode = chan->type; /* for now only one mode */ + + if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) { + if (nr >= STREAM_AUDIOIN1) + chan->DataFormatFlags = DF_SWAP32; + + if (io & NGENE_IO_TSOUT) + dec_fw_boot(dev); + +#ifdef ONE_ADAPTER + adapter = &chan->dev->dvb_adapter; +#else + ret = dvb_register_adapter(&chan->dvb_adapter, "nGene", + THIS_MODULE, + &chan->dev->pci_dev->dev); + if (ret < 0) + return ret; + adapter = &chan->dvb_adapter; +#endif + ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux", + ngene_start_feed, + ngene_stop_feed, chan); + ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux, + &chan->hw_frontend, + &chan->mem_frontend, adapter); + if (io & NGENE_IO_TSOUT) { + dvbdemux->write_to_decoder = write_to_decoder; + dvb_register_device(adapter, &chan->audio_dev, + &dvbdev_audio, (void *)chan, + DVB_DEVICE_AUDIO); + dvb_register_device(adapter, &chan->video_dev, + &dvbdev_video, (void *)chan, + DVB_DEVICE_VIDEO); + + } +#ifdef NGENE_COMMAND_API + dvb_register_device(adapter, &chan->command_dev, + &dvbdev_command, (void *)chan, + DVB_DEVICE_SEC); +#endif + } + + if (io & NGENE_IO_TSIN) { + chan->fe = NULL; + if (ni->demod_attach[nr]) + ni->demod_attach[nr](chan); + if (chan->fe) { + if (dvb_register_frontend(adapter, chan->fe) < 0) { + if (chan->fe->ops.release) + chan->fe->ops.release(chan->fe); + chan->fe = NULL; + } + } + if (chan->fe && ni->tuner_attach[nr]) + if (ni->tuner_attach[nr] (chan) < 0) { + printk(KERN_ERR DEVICE_NAME + ": Tuner attach failed on channel %d!\n", + nr); + } + } + + if (io & (NGENE_IO_AIN)) { + ngene_snd_init(chan); +#ifdef NGENE_V4L + spin_lock_init(&chan->s_lock); + init_MUTEX(&chan->reslock); + INIT_LIST_HEAD(&chan->capture); +#endif + + chan->soundbuffer = kmalloc(MAX_AUDIO_BUFFER_SIZE, GFP_KERNEL); + if (!chan->soundbuffer) + return -ENOMEM; + memset(chan->soundbuffer, 0, MAX_AUDIO_BUFFER_SIZE); + } + return ret; +} + +static int init_channels(struct ngene *dev) +{ + int i, j; + + for (i = 0; i < MAX_STREAM; i++) { + if (init_channel(&dev->channel[i]) < 0) { + for (j = 0; j < i; j++) + release_channel(&dev->channel[j]); + return -1; + } + } + return 0; +} + +/****************************************************************************/ +/* device probe/remove calls ************************************************/ +/****************************************************************************/ + +static void __devexit ngene_remove(struct pci_dev *pdev) +{ + struct ngene *dev = (struct ngene *)pci_get_drvdata(pdev); + int i; + + tasklet_kill(&dev->event_tasklet); + for (i = 0; i < MAX_STREAM; i++) + release_channel(&dev->channel[i]); +#ifdef ONE_ADAPTER + dvb_unregister_adapter(&dev->dvb_adapter); +#endif + ngene_stop(dev); + ngene_release_buffers(dev); + pci_set_drvdata(pdev, 0); + pci_disable_device(pdev); +} + +static int __devinit ngene_probe(struct pci_dev *pci_dev, + const struct pci_device_id *id) +{ + struct ngene *dev; + int stat = 0; + + if (pci_enable_device(pci_dev) < 0) + return -ENODEV; + + dev = vmalloc(sizeof(struct ngene)); + if (dev == NULL) + return -ENOMEM; + memset(dev, 0, sizeof(struct ngene)); + + dev->pci_dev = pci_dev; + dev->card_info = (struct ngene_info *)id->driver_data; + printk(KERN_INFO DEVICE_NAME ": Found %s\n", dev->card_info->name); + + pci_set_drvdata(pci_dev, dev); + + /* Alloc buffers and start nGene */ + stat = ngene_get_buffers(dev); + if (stat < 0) + goto fail1; + stat = ngene_start(dev); + if (stat < 0) + goto fail1; + + dev->i2c_current_bus = -1; + exp_init(dev); + + /* Disable analog TV decoder chips if present */ + if (copy_eeprom) { + i2c_copy_eeprom(&dev->channel[0].i2c_adapter, 0x50, 0x52); + i2c_dump_eeprom(&dev->channel[0].i2c_adapter, 0x52); + } + /*i2c_check_eeprom(&dev->i2c_adapter);*/ + + /* Register DVB adapters and devices for both channels */ +#ifdef ONE_ADAPTER + if (dvb_register_adapter(&dev->dvb_adapter, "nGene", THIS_MODULE, + &dev->pci_dev->dev, adapter_nr) < 0) + goto fail2; +#endif + if (init_channels(dev) < 0) + goto fail2; + + return 0; + +fail2: + ngene_stop(dev); +fail1: + ngene_release_buffers(dev); + pci_set_drvdata(pci_dev, 0); + return stat; +} + +/****************************************************************************/ +/* Card configs *************************************************************/ +/****************************************************************************/ + +static struct drxd_config fe_terratec_dvbt_0 = { + .index = 0, + .demod_address = 0x70, + .demod_revision = 0xa2, + .demoda_address = 0x00, + .pll_address = 0x60, + .pll_type = DRXD_PLL_DTT7520X, + .clock = 20000, + .pll_set = ngene_pll_set_th_dtt7520x, + .osc_deviation = osc_deviation, +}; + +static struct drxd_config fe_terratec_dvbt_1 = { + .index = 1, + .demod_address = 0x71, + .demod_revision = 0xa2, + .demoda_address = 0x00, + .pll_address = 0x60, + .pll_type = DRXD_PLL_DTT7520X, + .clock = 20000, + .pll_set = ngene_pll_set_th_dtt7520x, + .osc_deviation = osc_deviation, +}; + +static struct ngene_info ngene_info_terratec = { + .type = NGENE_TERRATEC, + .name = "Terratec Integra/Cinergy2400i Dual DVB-T", + .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN}, + .demod_attach = {demod_attach_drxd, demod_attach_drxd}, + .fe_config = {&fe_terratec_dvbt_0, &fe_terratec_dvbt_1}, + .i2c_access = 1, +}; + +/****************************************************************************/ + +static struct mt2060_config tuner_python_0 = { + .i2c_address = 0x60, + .clock_out = 3, + .input = 0 +}; + +static struct mt2060_config tuner_python_1 = { + .i2c_address = 0x61, + .clock_out = 3, + .input = 1 +}; + +static struct drxd_config fe_python_0 = { + .index = 0, + .demod_address = 0x71, + .demod_revision = 0xb1, + .demoda_address = 0x41, + .clock = 16000, + .osc_deviation = osc_deviation, +}; + +static struct drxd_config fe_python_1 = { + .index = 1, + .demod_address = 0x70, + .demod_revision = 0xb1, + .demoda_address = 0x45, + .clock = 16000, + .osc_deviation = osc_deviation, +}; + +static struct ngene_info ngene_info_python = { + .type = NGENE_PYTHON, + .name = "Micronas MicPython/Hedgehog Dual DVB-T", + .io_type = {NGENE_IO_TSIN | NGENE_IO_TV, + NGENE_IO_TSIN | NGENE_IO_TV, + NGENE_IO_AIN, NGENE_IO_AIN}, + .demod_attach = {demod_attach_drxd, demod_attach_drxd}, + .tuner_attach = {tuner_attach_mt2060, tuner_attach_mt2060}, + .fe_config = {&fe_python_0, &fe_python_1}, + .tuner_config = {&tuner_python_0, &tuner_python_1}, + .avf = {0x43, 0x47}, + .msp = {0x40, 0x42}, + .demoda = {0x41, 0x45}, + .gate_ctrl = python_gate_ctrl, + .switch_ctrl = python_switch_ctrl, +}; + +/****************************************************************************/ + +static struct drxd_config fe_appb_dvbt_0 = { + .index = 0, + .demod_address = 0x71, + .demod_revision = 0xa2, + .demoda_address = 0x41, + .pll_address = 0x63, + .pll_type = DRXD_PLL_MT3X0823, + .clock = 20000, + .pll_set = ngene_pll_set_mt_3x0823, + .osc_deviation = osc_deviation, +}; + +static struct drxd_config fe_appb_dvbt_1 = { + .index = 1, + .demod_address = 0x70, + .demod_revision = 0xa2, + .demoda_address = 0x45, + .pll_address = 0x60, + .pll_type = DRXD_PLL_MT3X0823, + .clock = 20000, + .pll_set = ngene_pll_set_mt_3x0823, + .osc_deviation = osc_deviation, +}; + +static struct ngene_info ngene_info_appboard = { + .type = NGENE_APP, + .name = "Micronas Application Board Dual DVB-T", + .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN}, + .demod_attach = {demod_attach_drxd, demod_attach_drxd}, + .fe_config = {&fe_appb_dvbt_0, &fe_appb_dvbt_1}, + .avf = {0x43, 0x47}, +}; + +static struct ngene_info ngene_info_appboard_ntsc = { + .type = NGENE_APP, + .name = "Micronas Application Board Dual DVB-T", + .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN}, + .demod_attach = {demod_attach_drxd, demod_attach_drxd}, + .fe_config = {&fe_appb_dvbt_0, &fe_appb_dvbt_1}, + .avf = {0x43, 0x47}, + .ntsc = 1, +}; + +/****************************************************************************/ + +static struct stb0899_config fe_sidewinder_0 = { + .demod_address = 0x68, + .pll_address = 0x63, +}; + +static struct stb0899_config fe_sidewinder_1 = { + .demod_address = 0x6b, + .pll_address = 0x60, +}; + +static struct ngene_info ngene_info_sidewinder = { + .type = NGENE_SIDEWINDER, + .name = "Micronas MicSquirrel/Sidewinder Dual DVB-S2", + .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN}, + .demod_attach = {demod_attach_stb0899, demod_attach_stb0899}, + .fe_config = {&fe_sidewinder_0, &fe_sidewinder_1}, + .lnb = {0x0b, 0x08}, +}; + +/****************************************************************************/ +/* Yet unnamed S2 card with dual DVB-S2 demod */ +/****************************************************************************/ + +static struct stv0900_config fe_s2_0 = { + .addr = 0x68, + .pll = 0x63, + .pll_type = 0, + .nr = 0, +}; + +static struct stv0900_config fe_s2_1 = { + .addr = 0x68, + .pll = 0x60, + .pll_type = 0, + .nr = 1, +}; + +static struct ngene_info ngene_info_s2 = { + .type = NGENE_SIDEWINDER, + .name = "S2", + .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN, + NGENE_IO_TSIN, NGENE_IO_TSIN}, + .demod_attach = {demod_attach_stv0900, demod_attach_stv0900}, + .fe_config = {&fe_s2_0, &fe_s2_1}, + .lnb = {0x0b, 0x08}, + .tsf = {3, 3}, + .fw_version = 15, +}; + +static struct stv0900_config fe_s2b_0 = { + .addr = 0x68, + .pll = 0x60, + .pll_type = 0x10, + .nr = 0, +}; + +static struct stv0900_config fe_s2b_1 = { + .addr = 0x68, + .pll = 0x63, + .pll_type = 0x10, + .nr = 1, +}; + +static struct ngene_info ngene_info_s2_b = { + .type = NGENE_SIDEWINDER, + .name = "S2 V2", + .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN, + NGENE_IO_TSIN, NGENE_IO_TSIN}, + .demod_attach = {demod_attach_stv0900, demod_attach_stv0900}, + .fe_config = {&fe_s2b_0, &fe_s2b_1}, + .lnb = {0x0b, 0x08}, + .tsf = {3, 3}, + .fw_version = 17, +}; + +/****************************************************************************/ + +static struct xc3028_config tuner_viper_0 = { + .adr = 0x61, + .reset = viper_reset_xc +}; + +static struct xc3028_config tuner_viper_1 = { + .adr = 0x64, + .reset = viper_reset_xc +}; + +static struct drxh_config fe_viper_h_0 = {.adr = 0x2b}; + +static struct drxh_config fe_viper_h_1 = {.adr = 0x29}; + +static struct drxh_config fe_viper_l_0 = {.adr = 0x2b, .type = 3931}; + +static struct drxh_config fe_viper_l_1 = {.adr = 0x29, .type = 3931}; + +static struct ngene_info ngene_info_viper_v1 = { + .type = NGENE_VIPER, + .name = "Micronas MicViper Dual ATSC DRXH", + .io_type = {NGENE_IO_TSIN | NGENE_IO_TV, + NGENE_IO_TSIN | NGENE_IO_TV, + NGENE_IO_AIN, NGENE_IO_AIN}, + .demod_attach = {demod_attach_drxh, demod_attach_drxh}, + .fe_config = {&fe_viper_h_0, &fe_viper_h_1}, + .tuner_config = {&tuner_viper_0, &tuner_viper_1}, + .tuner_attach = {tuner_attach_xc3028, tuner_attach_xc3028}, + .avf = {0x43, 0x47}, + .msp = {0x40, 0x42}, + .exp = 0x20, + .exp_init = 0xf5, + .gate_ctrl = viper_gate_ctrl, + .switch_ctrl = viper_switch_ctrl, + .tsf = {2, 2}, +}; + +static struct ngene_info ngene_info_viper_v2 = { + .type = NGENE_VIPER, + .name = "Micronas MicViper Dual ATSC DRXL", + .io_type = {NGENE_IO_TSIN | NGENE_IO_TV, + NGENE_IO_TSIN | NGENE_IO_TV, + NGENE_IO_AIN, NGENE_IO_AIN}, + .demod_attach = {demod_attach_drxh, demod_attach_drxh}, + .fe_config = {&fe_viper_l_0, &fe_viper_l_1}, + .tuner_config = {&tuner_viper_0, &tuner_viper_1}, + .tuner_attach = {tuner_attach_xc3028, tuner_attach_xc3028}, + .avf = {0x43, 0x47}, + .msp = {0x40, 0x42}, + .exp = 0x38, + .exp_init = 0xf5, + .gate_ctrl = viper_gate_ctrl, + .switch_ctrl = viper_switch_ctrl, + .tsf = {2, 2}, +}; + +/****************************************************************************/ + +static struct ngene_info ngene_info_vbox_v1 = { + .type = NGENE_VBOX_V1, + .name = "VBox Cat's Eye 164E", + .io_type = {NGENE_IO_TSIN | NGENE_IO_TV, + NGENE_IO_TSIN | NGENE_IO_TV, + NGENE_IO_AIN, NGENE_IO_AIN}, + .demod_attach = {demod_attach_drxh, demod_attach_drxh}, + .fe_config = {&fe_viper_h_0, &fe_viper_h_1}, + .tuner_config = {&tuner_viper_0, &tuner_viper_1}, + .tuner_attach = {tuner_attach_xc3028, tuner_attach_xc3028}, + .avf = {0x43, 0x47}, + .msp = {0x40, 0x42}, + .exp = 0x20, + .exp_init = 0xf5, + .gate_ctrl = viper_gate_ctrl, + .switch_ctrl = viper_switch_ctrl, + .tsf = {2, 2}, +}; + +/****************************************************************************/ + +static struct ngene_info ngene_info_vbox_v2 = { + .type = NGENE_VBOX_V2, + .name = "VBox Cat's Eye 164E", + .io_type = {NGENE_IO_TSIN | NGENE_IO_TV, + NGENE_IO_TSIN | NGENE_IO_TV, + NGENE_IO_AIN, NGENE_IO_AIN}, + .demod_attach = {demod_attach_drxh, demod_attach_drxh}, + .fe_config = {&fe_viper_h_0, &fe_viper_h_1}, + .tuner_config = {&tuner_viper_0, &tuner_viper_1}, + .tuner_attach = {tuner_attach_xc3028, tuner_attach_xc3028}, + .avf = {0x43, 0x47}, + .msp = {0x40, 0x42}, + .exp = 0x20, + .exp_init = 0xf5, + .gate_ctrl = viper_gate_ctrl, + .switch_ctrl = viper_switch_ctrl2, + .tsf = {2, 2}, +}; + +/****************************************************************************/ + +static struct ngene_info ngene_info_racer = { + .type = NGENE_RACER, + .name = "Micronas MicRacer HDTV Decoder Card", + .io_type = {NGENE_IO_HDTV, NGENE_IO_NONE, + NGENE_IO_AIN, NGENE_IO_NONE, + NGENE_IO_TSOUT}, + .i2s = {0, 0, 1, 0}, + .fw_version = 17, +}; + + +/****************************************************************************/ +/****************************************************************************/ +/****************************************************************************/ + +#define NGENE_ID(_subvend, _subdev, _driverdata) { \ + .vendor = NGENE_VID, .device = NGENE_PID, \ + .subvendor = _subvend, .subdevice = _subdev, \ + .driver_data = (unsigned long) &_driverdata } + +/****************************************************************************/ + +static const struct pci_device_id ngene_id_tbl[] __devinitdata = { + NGENE_ID(0x18c3, 0x0000, ngene_info_appboard), + NGENE_ID(0x18c3, 0x0004, ngene_info_appboard), + NGENE_ID(0x18c3, 0x8011, ngene_info_appboard), + NGENE_ID(0x18c3, 0x8015, ngene_info_appboard_ntsc), + NGENE_ID(0x153b, 0x1167, ngene_info_terratec), + NGENE_ID(0x18c3, 0x0030, ngene_info_python), + NGENE_ID(0x18c3, 0x0052, ngene_info_sidewinder), + NGENE_ID(0x18c3, 0x8f00, ngene_info_racer), + NGENE_ID(0x18c3, 0x0041, ngene_info_viper_v1), + NGENE_ID(0x18c3, 0x0042, ngene_info_viper_v2), + NGENE_ID(0x14f3, 0x0041, ngene_info_vbox_v1), + NGENE_ID(0x14f3, 0x0043, ngene_info_vbox_v2), + NGENE_ID(0x18c3, 0xabcd, ngene_info_s2), + NGENE_ID(0x18c3, 0xabc2, ngene_info_s2_b), + NGENE_ID(0x18c3, 0xabc3, ngene_info_s2_b), + {0} +}; + +/****************************************************************************/ +/* Init/Exit ****************************************************************/ +/****************************************************************************/ + +static pci_ers_result_t ngene_error_detected(struct pci_dev *dev, + enum pci_channel_state state) +{ + printk(KERN_ERR DEVICE_NAME ": PCI error\n"); + if (state == pci_channel_io_perm_failure) + return PCI_ERS_RESULT_DISCONNECT; + if (state == pci_channel_io_frozen) + return PCI_ERS_RESULT_NEED_RESET; + return PCI_ERS_RESULT_CAN_RECOVER; +} + +static pci_ers_result_t ngene_link_reset(struct pci_dev *dev) +{ + printk(KERN_INFO DEVICE_NAME ": link reset\n"); + return 0; +} + +static pci_ers_result_t ngene_slot_reset(struct pci_dev *dev) +{ + printk(KERN_INFO DEVICE_NAME ": slot reset\n"); + return 0; +} + +static void ngene_resume(struct pci_dev *dev) +{ + printk(KERN_INFO DEVICE_NAME ": resume\n"); +} + +static struct pci_error_handlers ngene_errors = { + .error_detected = ngene_error_detected, + .link_reset = ngene_link_reset, + .slot_reset = ngene_slot_reset, + .resume = ngene_resume, +}; + +static struct pci_driver ngene_pci_driver = { + .name = "ngene", + .id_table = ngene_id_tbl, + .probe = ngene_probe, + .remove = ngene_remove, + .err_handler = &ngene_errors, +}; + +static __init int module_init_ngene(void) +{ + printk(KERN_INFO + "nGene PCIE bridge driver, Copyright (C) 2005-2007 Micronas\n"); + return pci_register_driver(&ngene_pci_driver); +} + +static __exit void module_exit_ngene(void) +{ + pci_unregister_driver(&ngene_pci_driver); +} + +module_init(module_init_ngene); +module_exit(module_exit_ngene); + +MODULE_DESCRIPTION("nGene"); +MODULE_AUTHOR("Micronas, Ralph Metzler, Manfred Voelkel"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/dvb/ngene/ngene-ioctls.h b/drivers/media/dvb/ngene/ngene-ioctls.h new file mode 100644 index 000000000000..4aa2f64a5314 --- /dev/null +++ b/drivers/media/dvb/ngene/ngene-ioctls.h @@ -0,0 +1,216 @@ +/* + * Copyright (C) 2006-2007 Micronas + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _NGENE_IOCTLS_H_ +#define _NGENE_IOCTLS_H_ + +#include <linux/ioctl.h> +#include <linux/types.h> + +#define NGENE_MAGIC 'n' + +typedef struct { + unsigned char I2CAddress; + unsigned char OutLength; /* bytes to write first */ + unsigned char InLength; /* bytes to read */ + unsigned char OutData[256]; /* output data */ + unsigned char InData[256]; /* input data */ +} MIC_I2C_READ, *PMIC_I2C_READ; + +#define IOCTL_MIC_I2C_READ _IOWR(NGENE_MAGIC, 0x00, MIC_I2C_READ) + + +typedef struct { + unsigned char I2CAddress; + unsigned char Length; + unsigned char Data[250]; +} MIC_I2C_WRITE, *PMIC_I2C_WRITE; + +typedef struct { + unsigned char Length; + unsigned char Data[250]; +} MIC_I2C_CONTINUE_WRITE, *PMIC_I2C_CONTINUE_WRITE; + +#define IOCTL_MIC_I2C_WRITE _IOW(NGENE_MAGIC, 0x01, \ + MIC_I2C_WRITE) +#define IOCTL_MIC_I2C_WRITE_NOSTOP _IOW(NGENE_MAGIC, 0x0c, \ + MIC_I2C_WRITE) +#define IOCTL_MIC_I2C_CONTINUE_WRITE_NOSTOP _IOW(NGENE_MAGIC, 0x0d, \ + MIC_I2C_CONTINUE_WRITE) +#define IOCTL_MIC_I2C_CONTINUE_WRITE _IOW(NGENE_MAGIC, 0x0e, \ + MIC_I2C_CONTINUE_WRITE) + +typedef struct { + unsigned char ModeSelect; /* see bellow */ + unsigned char OutLength; /* bytes to write first */ + unsigned char InLength; /* bytes to read */ + unsigned char OutData[250]; /* output data */ +} MIC_SPI_READ, *PMIC_SPI_READ; + +#define IOCTL_MIC_SPI_READ _IOWR(NGENE_MAGIC, 0x02, MIC_SPI_READ) + +typedef struct { + unsigned char ModeSelect; /* see below */ + unsigned char Length; + unsigned char Data[250]; +} MIC_SPI_WRITE, *PMIC_SPI_WRITE; + +#define IOCTL_MIC_SPI_WRITE _IOW(NGENE_MAGIC, 0x03, MIC_SPI_READ) + +#define IOCTL_MIC_DOWNLOAD_FIRMWARE _IOW(NGENE_MAGIC, 0x06, unsigned char) + +#define IOCTL_MIC_NO_OP _IO(NGENE_MAGIC, 0x18) + +#define IOCTL_MIC_TUN_RDY _IO(NGENE_MAGIC, 0x07) +#define IOCTL_MIC_DEC_SRATE _IOW(NGENE_MAGIC, 0x0a, int) +#define IOCTL_MIC_DEC_RDY _IO(NGENE_MAGIC, 0x09) +#define IOCTL_MIC_DEC_FREESYNC _IOW(NGENE_MAGIC, 0x08, int) +#define IOCTL_MIC_TUN_DETECT _IOWR(NGENE_MAGIC, 0x0b, int) + +typedef struct { + unsigned char Stream; /* < UVI1, UVI2, or TVOUT */ + unsigned char Control; + unsigned char Mode; + unsigned short nLines; + unsigned short nBytesPerLine; + unsigned short nVBILines; + unsigned short nBytesPerVBILine; +} MIC_STREAM_CONTROL, *PMIC_STREAM_CONTROL; + +enum MIC_STREAM_CONTROL_MODE_BITS { + MSC_MODE_LOOPBACK = 0x80, + MSC_MODE_AVLOOP = 0x40, + MSC_MODE_AUDIO_SPDIF = 0x20, + MSC_MODE_AVSYNC = 0x10, + MSC_MODE_TRANSPORT_STREAM = 0x08, + MSC_MODE_AUDIO_CAPTURE = 0x04, + MSC_MODE_VBI_CAPTURE = 0x02, + MSC_MODE_VIDEO_CAPTURE = 0x01 +}; + +#define IOCTL_MIC_STREAM_CONTROL _IOW(NGENE_MAGIC, 0x22, MIC_STREAM_CONTROL) + +typedef struct { + unsigned char Stream; /* < UVI1, UVI2 */ + unsigned int Rate; /* < Rate in 100nsec to release the buffers + to the stream filters */ +} MIC_SIMULATE_CONTROL, *PMIC_SIMULATE_CONTROL; + +#define IOCTL_MIC_SIMULATE_CONTROL _IOW(NGENE_MAGIC, 0x23, \ + MIC_SIMULATE_CONTROL) + +/* + * IOCTL definitions for the test driver + * + * NOTE: the test driver also supports following IOCTL defined above: + * IOCTL_MIC_NO_OP: + * IOCTL_MIC_RECEIVE_BUFFER: + * IOCTL_MIC_STREAM_CONTROL: + * IOCTL_MIC_I2C_READ: + * IOCTL_MIC_I2C_WRITE: + * + * + * VI2C access to NGene memory (read) + * + * GETMEM in : ULONG start offset + * out : read data (length defined by size of output buffer) + * SETMEM in : ULONG start offset followed by data to be written + * (length defined by size of input buffer) + */ + +typedef struct { + __u32 Start; + __u32 Length; + __u8 *Data; +} MIC_MEM; + +#define IOCTL_MIC_TEST_GETMEM _IOWR(NGENE_MAGIC, 0x90, MIC_MEM) +#define IOCTL_MIC_TEST_SETMEM _IOW(NGENE_MAGIC, 0x91, MIC_MEM) + +typedef struct { + __u8 Address; + __u8 Data; +} MIC_IMEM; + +#define IOCTL_MIC_SFR_READ _IOWR(NGENE_MAGIC, 0xa2, MIC_IMEM) +#define IOCTL_MIC_SFR_WRITE _IOWR(NGENE_MAGIC, 0xa3, MIC_IMEM) + +#define IOCTL_MIC_IRAM_READ _IOWR(NGENE_MAGIC, 0xa4, MIC_IMEM) +#define IOCTL_MIC_IRAM_WRITE _IOWR(NGENE_MAGIC, 0xa5, MIC_IMEM) + +/* + * Set Ngene gpio bit + */ +typedef struct { + unsigned char Select; + unsigned char Level; +} MIC_SET_GPIO_PIN, *PMIC_SET_GPIO_PIN; + +#define IOCTL_MIC_SET_GPIO_PIN _IOWR(NGENE_MAGIC, 0xa6, MIC_SET_GPIO_PIN) + +/* + * Uart ioctls: + * These are implemented in the test driver. + * + * Enable UART + * + * In: 1 byte containing baud rate: 0 = 19200, 1 = 9600, 2 = 4800, 3 = 2400 + * Out: nothing + */ +#define IOCTL_MIC_UART_ENABLE _IOW(NGENE_MAGIC, 0xa9, unsigned char) + +/* + * Enable UART + * + * In: nothing + * Out: nothing + */ +#define IOCTL_MIC_UART_DISABLE _IO(NGENE_MAGIC, 0xAA) + +/* + * Write UART + * + * In: data to write + * Out: nothing + * Note: Call returns immediatly, data are send out asynchrounsly + */ +#define IOCTL_MIC_UART_WRITE _IOW(NGENE_MAGIC, 0xAB, unsigned char) + +/* + * Read UART + * + * In: nothing + * Out: Data read (since last call) + * Note: Call returns immediatly + */ +#define IOCTL_MIC_UART_READ _IOR(NGENE_MAGIC, 0xAC, unsigned char) + +/* + * UART Status + * + * In: nothing + * Out: Byte 0 : Transmitter busy, + * Byte 1 : Nbr of characters available for read. + * Note: Call returns immediatly + */ +#define IOCTL_MIC_UART_STATUS _IOR(NGENE_MAGIC, 0xAD, unsigned char) + +#endif diff --git a/drivers/media/dvb/ngene/ngene-snd.c b/drivers/media/dvb/ngene/ngene-snd.c new file mode 100644 index 000000000000..1ca343236ffb --- /dev/null +++ b/drivers/media/dvb/ngene/ngene-snd.c @@ -0,0 +1,421 @@ +/* + * ngene_snd.c: nGene PCIe bridge driver ALSA support + * + * Copyright (C) 2005-2007 Micronas + * + * Based on the initial ALSA support port by Thomas Eschbach. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/version.h> +#include <linux/module.h> + +#include "ngene.h" +#include "ngene-ioctls.h" + +static int sound_dev; + +/* sound module parameters (see "Module Parameters") */ +static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; +static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; +static int enable[SNDRV_CARDS] = {1, [1 ... (SNDRV_CARDS - 1)] = 1}; + +/****************************************************************************/ +/* PCM Sound Funktions ******************************************************/ +/****************************************************************************/ + +static struct snd_pcm_hardware snd_mychip_capture_hw = { + .info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER), + .formats = SNDRV_PCM_FMTBIT_S16_LE, + .rates = (SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 + | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 + | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000), + .rate_min = 11025, + .rate_max = 48000, + .channels_min = 2, + .channels_max = 2, + .buffer_bytes_max = 16384, + .period_bytes_min = 8192, + .period_bytes_max = 8192, + .periods_min = 1, + .periods_max = 2, +}; + +/* open callback */ +static int snd_mychip_capture_open(struct snd_pcm_substream *substream) +{ + + struct mychip *chip = snd_pcm_substream_chip(substream); + struct snd_pcm_runtime *runtime = substream->runtime; + + runtime->hw = snd_mychip_capture_hw; + chip->substream = substream; + return 0; +} + +/* close callback */ +static int snd_mychip_capture_close(struct snd_pcm_substream *substream) +{ + struct mychip *chip = snd_pcm_substream_chip(substream); + chip->substream = NULL; + return 0; + +} + +/* hw_params callback */ +static int snd_mychip_pcm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *hw_params) +{ + struct mychip *chip = snd_pcm_substream_chip(substream); + struct ngene_channel *chan = chip->chan; + if (chan->soundbuffisallocated == 0) { + chan->soundbuffisallocated = 1; + return snd_pcm_lib_malloc_pages(substream, + params_buffer_bytes(hw_params)); + } + return 0; +} + +/* hw_free callback */ +static int snd_mychip_pcm_hw_free(struct snd_pcm_substream *substream) +{ + struct mychip *chip = snd_pcm_substream_chip(substream); + struct ngene_channel *chan = chip->chan; + int retval = 0; + if (chan->soundbuffisallocated == 1) { + chan->soundbuffisallocated = 0; + retval = snd_pcm_lib_free_pages(substream); + } + return retval; +} + +/* prepare callback */ +static int snd_mychip_pcm_prepare(struct snd_pcm_substream *substream) +{ + + struct mychip *chip = snd_pcm_substream_chip(substream); + struct snd_pcm_runtime *runtime = substream->runtime; + struct ngene_channel *chan = chip->chan; + struct ngene_channel *ch = &chan->dev->channel[chan->number - 2]; + struct i2c_adapter *adap = &ch->i2c_adapter; + + if (ch->soundstreamon == 1) + ;/*ngene_command_stream_control_sound(chan->dev, chan->number, + 0x00, 0x00);*/ + i2c_clients_command(adap, IOCTL_MIC_DEC_SRATE, &(runtime->rate)); + mdelay(80); + if (ch->soundstreamon == 1) + ;/*ngene_command_stream_control_sound(chan->dev, chan->number, + 0x80, 0x04);*/ + + return 0; +} + +/* trigger callback */ +static int snd_mychip_pcm_trigger(struct snd_pcm_substream *substream, int cmd) +{ + struct mychip *chip = snd_pcm_substream_chip(substream); + struct ngene_channel *chan = chip->chan; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + /* do something to start the PCM engine */ + chan->sndbuffflag = 0; + break; + case SNDRV_PCM_TRIGGER_STOP: + /* do something to stop the PCM engine */ + chip->substream = NULL; + chan->sndbuffflag = 0; + break; + default: + return -EINVAL; + } + return 0; +} + +/* pointer callback */ +static snd_pcm_uframes_t +snd_mychip_pcm_pointer(struct snd_pcm_substream *substream) +{ + struct mychip *chip = snd_pcm_substream_chip(substream); + struct ngene_channel *chan = chip->chan; + unsigned int current_ptr; + + if (chan->sndbuffflag == 0) { + current_ptr = (unsigned int) + bytes_to_frames(substream->runtime, 0); + } else { + current_ptr = (unsigned int) + bytes_to_frames(substream->runtime, 8192); + } + return current_ptr; +} + +/*copy sound buffer to pcm middel layer*/ +static int snd_capture_copy(struct snd_pcm_substream *substream, int channel, + snd_pcm_uframes_t pos, void *dst, + snd_pcm_uframes_t count) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct mychip *chip = snd_pcm_substream_chip(substream); + struct ngene_channel *chan = chip->chan; + + memcpy(dst, chan->soundbuffer, frames_to_bytes(runtime, count)); + return 0; +} + +static int snd_pcm_capture_silence(struct snd_pcm_substream *substream, + int channel, + snd_pcm_uframes_t pos, + snd_pcm_uframes_t count) +{ + /* + struct snd_pcm_runtime *runtime = substream->runtime; + struct mychip *chip = snd_pcm_substream_chip(substream); + struct ngene_channel *chan = chip->chan; + */ + return 0; +} + +/* operators */ +static struct snd_pcm_ops snd_mychip_capture_ops = { + .open = snd_mychip_capture_open, + .close = snd_mychip_capture_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = snd_mychip_pcm_hw_params, + .hw_free = snd_mychip_pcm_hw_free, + .prepare = snd_mychip_pcm_prepare, + .trigger = snd_mychip_pcm_trigger, + .pointer = snd_mychip_pcm_pointer, + .copy = snd_capture_copy, + .silence = snd_pcm_capture_silence, +}; + +static void mychip_pcm_free(struct snd_pcm *pcm) +{ + pcm->private_data = NULL; +} + +/* create a pcm device */ +static int snd_mychip_new_pcm(struct mychip *chip, struct ngene_channel *chan) +{ + struct snd_pcm *pcm; + int err; + char gro[10]; + sprintf(gro, "PCM%d", chan->number); + + err = snd_pcm_new(chip->card, gro, 0, 0, 1, &pcm); + if (err < 0) + return err; + + pcm->private_data = chip; + pcm->private_free = mychip_pcm_free; + + sprintf(pcm->name, "MyPCM_%d", chan->number); + + chip->pcm = pcm; + /* set operators */ + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_mychip_capture_ops); + /* pre-allocation of buffers */ + + err = snd_pcm_lib_preallocate_pages_for_all(pcm, + SNDRV_DMA_TYPE_CONTINUOUS, + snd_dma_continuous_data( + GFP_KERNEL), + 0, 16 * 1024); + + return 0; +} + +#define ngene_VOLUME(xname, xindex, addr) \ + { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ + .info = snd_volume_info, \ + .get = snd_volume_get, .put = snd_volume_put, \ + .private_value = addr } + +static int snd_volume_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 2; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = 20; + return 0; +} + +static int snd_volume_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct mychip *chip = snd_kcontrol_chip(kcontrol); + int addr = kcontrol->private_value; + + ucontrol->value.integer.value[0] = chip->mixer_volume[addr][0]; + ucontrol->value.integer.value[1] = chip->mixer_volume[addr][1]; + return 0; +} + +static int snd_volume_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct mychip *chip = snd_kcontrol_chip(kcontrol); + int change, addr = kcontrol->private_value; + int left, right; + + left = ucontrol->value.integer.value[0]; + if (left < 0) + left = 0; + if (left > 20) + left = 20; + right = ucontrol->value.integer.value[1]; + if (right < 0) + right = 0; + if (right > 20) + right = 20; + spin_lock_irq(&chip->mixer_lock); + change = chip->mixer_volume[addr][0] != left || + chip->mixer_volume[addr][1] != right; + chip->mixer_volume[addr][0] = left; + chip->mixer_volume[addr][1] = right; + spin_unlock_irq(&chip->mixer_lock); + return change; +} + +#define ngene_CAPSRC(xname, xindex, addr) \ + { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ + .info = snd_capsrc_info, \ + .get = snd_capsrc_get, .put = snd_capsrc_put, \ + .private_value = addr } + +static int snd_capsrc_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; + uinfo->count = 2; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = 1; + return 0; +} + +static int snd_capsrc_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct mychip *chip = snd_kcontrol_chip(kcontrol); + int addr = kcontrol->private_value; + + spin_lock_irq(&chip->mixer_lock); + ucontrol->value.integer.value[0] = chip->capture_source[addr][0]; + ucontrol->value.integer.value[1] = chip->capture_source[addr][1]; + spin_unlock_irq(&chip->mixer_lock); + + return 0; +} + +static int snd_capsrc_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct mychip *chip = snd_kcontrol_chip(kcontrol); + int change, addr = kcontrol->private_value; + int left, right; + + left = ucontrol->value.integer.value[0] & 1; + right = ucontrol->value.integer.value[1] & 1; + spin_lock_irq(&chip->mixer_lock); + + change = chip->capture_source[addr][0] != left || + chip->capture_source[addr][1] != right; + chip->capture_source[addr][0] = left; + chip->capture_source[addr][1] = right; + + spin_unlock_irq(&chip->mixer_lock); + + if (change) + printk(KERN_INFO "snd_capsrc_put change\n"); + return 0; +} + +static struct snd_kcontrol_new snd_controls[] = { + ngene_VOLUME("Video Volume", 0, MIXER_ADDR_TVTUNER), + ngene_CAPSRC("Video Capture Switch", 0, MIXER_ADDR_TVTUNER), +}; + +static int snd_card_new_mixer(struct mychip *chip) +{ + struct snd_card *card = chip->card; + unsigned int idx; + int err; + + strcpy(card->mixername, "NgeneMixer"); + + for (idx = 0; idx < ARRAY_SIZE(snd_controls); idx++) { + err = snd_ctl_add(card, snd_ctl_new1(&snd_controls[idx], chip)); + if (err < 0) + return err; + } + return 0; +} + +int ngene_snd_init(struct ngene_channel *chan) +{ + struct snd_card *card; + struct mychip *chip; + int err; + + if (sound_dev >= SNDRV_CARDS) + return -ENODEV; + if (!enable[sound_dev]) { + sound_dev++; + return -ENOENT; + } + card = snd_card_new(index[sound_dev], id[sound_dev], + THIS_MODULE, sizeof(struct mychip)); + if (card == NULL) + return -ENOMEM; + + chip = card->private_data; + chip->card = card; + chip->irq = -1; + + sprintf(card->shortname, "MyChip%d%d", chan->dev->nr, chan->number); + sprintf(card->shortname, "Myown%d%d", chan->dev->nr, chan->number); + sprintf(card->longname, "My first Own Chip on Card Nr.%d is %d", + chan->dev->nr, chan->number); + + spin_lock_init(&chip->lock); + spin_lock_init(&chip->mixer_lock); + + snd_card_new_mixer(chip); + + snd_mychip_new_pcm(chip, chan); + err = snd_card_register(card); + if (err < 0) { + snd_card_free(card); + return err; + } + chan->soundcard = card; + chan->mychip = chip; + chip->chan = chan; + sound_dev++; + return 0; +} + +int ngene_snd_exit(struct ngene_channel *chan) +{ + snd_card_free(chan->soundcard); + return 0; +} diff --git a/drivers/media/dvb/ngene/ngene-v4l2.c b/drivers/media/dvb/ngene/ngene-v4l2.c new file mode 100644 index 000000000000..c0a9147c44a5 --- /dev/null +++ b/drivers/media/dvb/ngene/ngene-v4l2.c @@ -0,0 +1,1937 @@ +/* + * ngene_v4l2.c: nGene PCIe bridge driver V4L2 support + * + * Copyright (C) 2005-2007 Micronas + * + * Based on the initial V4L2 support port by Thomas Eschbach. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/sched.h> +#include <linux/spinlock.h> +#include <linux/fs.h> +#include <linux/unistd.h> +#include <linux/time.h> +#include <linux/pci.h> +#include <linux/vmalloc.h> +#include <linux/pagemap.h> +#include <linux/videodev2.h> +#include <linux/videodev.h> +#include <linux/version.h> +#include <asm/uaccess.h> +#include <asm/semaphore.h> +#include <asm/system.h> +#include <asm/io.h> +#include <asm/kmap_types.h> +#include <linux/videodev.h> + +#include <media/v4l2-dev.h> + +#include "ngene.h" +#include "ngene-ioctls.h" + +/****************************************************************************/ + +static unsigned int gbuffers = 8; +static unsigned int gbufsize = 0x208000; + +enum km_type ngene_km_types[] = { + KM_USER0, + KM_USER1, + KM_SOFTIRQ0, + KM_SOFTIRQ1, +}; + +#define V4L2_STD_NTSC_M_KOREA ((v4l2_std_id)0x00004000) +#define V4L2_STD_SECAM_L1 ((v4l2_std_id)0x00008000) + +static inline void *my_video_get_drvdata(struct video_device *vd) +{ + return dev_get_drvdata(vd->dev); +} + +static inline void my_video_set_drvdata(struct video_device *vd, void *d) +{ + dev_set_drvdata(vd->dev, d); +} + +static struct ngene_tvnorm ngene_tvnorms_hd[] = { + { + .v4l2_id = V4L2_STD_PAL_BG, + .name = "1080i50", + .swidth = 1920, + .sheight = 1080, + .tuner_norm = 1, + .soundstd = 1, + } +}; + +static struct ngene_tvnorm ngene_tvnorms_sd[] = { + /* PAL-BDGHI */ + /* max. active video is actually 922, but 924 is divisible by 4 & 3!*/ + /* actually, max active PAL with HSCALE=0 is 948, NTSC is 768 - nil */ + { + .v4l2_id = V4L2_STD_PAL_BG, + .name = "PAL-BG", + .swidth = 720, + .sheight = 576, + .tuner_norm = 1, + .soundstd = 1, + }, { + .v4l2_id = V4L2_STD_PAL_DK, + .name = "PAL-DK", + .swidth = 720, + .sheight = 576, + .tuner_norm = 2, + .soundstd = 2, + }, { + .v4l2_id = V4L2_STD_PAL_H, + .name = "PAL-H", + .swidth = 720, + .sheight = 576, + .tuner_norm = 0, + .soundstd = 1, + }, { + .v4l2_id = V4L2_STD_PAL_I, + .name = "PAL-I", + .swidth = 720, + .sheight = 576, + .tuner_norm = 4, + .soundstd = 4, + }, { + .v4l2_id = V4L2_STD_PAL_M, + .name = "PAL_M", + .swidth = 720, + .sheight = 5760, + .tuner_norm = 7, + .soundstd = 5, + }, { + .v4l2_id = V4L2_STD_NTSC_M, + .name = "NTSC_M", + .swidth = 720, + .sheight = 480, + .tuner_norm = 7, + .soundstd = 5, + }, { + .v4l2_id = V4L2_STD_NTSC_M_JP, + .name = "NTSC_M_JP", + .swidth = 720, + .sheight = 480, + .tuner_norm = 7, + .soundstd = 6, + }, { + .v4l2_id = V4L2_STD_PAL_N, + .name = "PAL-N", + .swidth = 720, + .sheight = 576, + .tuner_norm = 7, + .soundstd = 5, + }, { + .v4l2_id = V4L2_STD_SECAM_B, + .name = "SECAM_B", + .swidth = 720, + .sheight = 576, + .tuner_norm = 1, + .soundstd = 1, + }, { + .v4l2_id = V4L2_STD_SECAM_D, + .name = "SECAM_D", + .swidth = 720, + .sheight = 576, + .tuner_norm = 2, + .soundstd = 2, + }, { + .v4l2_id = V4L2_STD_SECAM_G, + .name = "SECAM_G", + .swidth = 720, + .sheight = 576, + .tuner_norm = 3, + .soundstd = 1, + }, { + .v4l2_id = V4L2_STD_SECAM_H, + .name = "SECAM_H", + .swidth = 720, + .sheight = 576, + .tuner_norm = 3, + .soundstd = 1, + }, { + .v4l2_id = V4L2_STD_SECAM_K, + .name = "SECAM_K", + .swidth = 720, + .sheight = 576, + .tuner_norm = 2, + .soundstd = 2, + }, { + .v4l2_id = V4L2_STD_SECAM_K1, + .name = "SECAM_K1", + .swidth = 720, + .sheight = 576, + .tuner_norm = 2, + .soundstd = 2, + }, { + .v4l2_id = V4L2_STD_SECAM_L, + .name = "SECAM_L", + .swidth = 720, + .sheight = 576, + .tuner_norm = 5, + .soundstd = 3, + }, { + .v4l2_id = V4L2_STD_NTSC_M_KOREA, + .name = "NTSC_M_KOREA", + .swidth = 720, + .sheight = 480, + .tuner_norm = 7, + .soundstd = 7, + }, { + .v4l2_id = V4L2_STD_SECAM_L1, + .name = "SECAM_L1", + .swidth = 720, + .sheight = 576, + .tuner_norm = 6, + .soundstd = 3, + } + +}; + +static const int NGENE_TVNORMS = ARRAY_SIZE(ngene_tvnorms_sd); + +static u8 BlackLine[1440] = { + /* 0x80, */ 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, + 0x80, +}; + +#define V4L2_CID_PRIVATE_SHARPNESS (V4L2_CID_PRIVATE_BASE + 0) +#define V4L2_CID_PRIVATE_LASTP1 (V4L2_CID_PRIVATE_BASE + 1) + +static const struct v4l2_queryctrl no_ctl = { + .name = "no_ctl", + .flags = V4L2_CTRL_FLAG_DISABLED, +}; + +static const struct v4l2_queryctrl ngene_ctls[] = { + /* --- video --- */ + { + .id = V4L2_CID_BRIGHTNESS, + .name = "Brightness", + .minimum = -127, + .maximum = 127, + .step = 1, + .default_value = 0, + .type = V4L2_CTRL_TYPE_INTEGER, + }, { + .id = V4L2_CID_CONTRAST, + .name = "Contrast", + .minimum = 0, + .maximum = 63, + .step = 1, + .default_value = 30, + .type = V4L2_CTRL_TYPE_INTEGER, + }, { + .id = V4L2_CID_SATURATION, + .name = "Saturation", + .minimum = 0, + .maximum = 4094, + .step = 1, + .default_value = 2000, + .type = V4L2_CTRL_TYPE_INTEGER, + }, { + .id = V4L2_CID_HUE, + .name = "Hue", + .minimum = -2047, + .maximum = 2047, + .step = 1, + .default_value = 0, + .type = V4L2_CTRL_TYPE_INTEGER, + }, + /* --- audio --- */ + { + .id = V4L2_CID_AUDIO_MUTE, + .name = "Mute", + .minimum = 0, + .maximum = 1, + .type = V4L2_CTRL_TYPE_BOOLEAN, + }, { + .id = V4L2_CID_PRIVATE_SHARPNESS, + .name = "sharpness", + .minimum = 0, + .maximum = 100, + .step = 1, + .default_value = 50, + .type = V4L2_CTRL_TYPE_INTEGER, + }, + +}; + +static const int NGENE_CTLS = ARRAY_SIZE(ngene_ctls); + +static const struct ngene_format ngene_formats[] = { + { + .name = "4:2:2, packed, YUYV", + .palette = -1, + .fourcc = V4L2_PIX_FMT_YUYV, + .format = V4L2_PIX_FMT_YUYV, + .palette = VIDEO_PALETTE_YUYV, + .depth = 16, + .flags = 0x02,/* FORMAT_FLAGS_PACKED, */ + } +}; + +static const unsigned int NGENE_FORMATS = ARRAY_SIZE(ngene_formats); + +/****************************************************************************/ + +static struct videobuf_queue *ngene_queue(struct ngene_vopen *vopen) +{ + struct videobuf_queue *q = NULL; + + switch (vopen->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + q = &vopen->vbuf_q; + break; + case V4L2_BUF_TYPE_VBI_CAPTURE: + q = &vopen->vbi; + break; + default: + break; + } + return q; +} + +static int ngene_resource(struct ngene_vopen *vopen) +{ + int res = 0; + + switch (vopen->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + res = RESOURCE_VIDEO; + break; + case V4L2_BUF_TYPE_VBI_CAPTURE: + res = RESOURCE_VBI; + break; + default: + break; + } + return res; +} + +static int ngene_try_fmt(struct ngene_vopen *vopen, struct ngene_channel *chan, + struct v4l2_format *f) +{ + switch (f->type) { + + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + { + const struct ngene_format *fmt; + enum v4l2_field field; + unsigned int maxw, maxh; + int maxLinesPerField; + + fmt = ngene_formats; + if (NULL == fmt) + return -EINVAL; + + /* fixup format */ + maxw = chan->tvnorms[chan->tvnorm].swidth; + maxLinesPerField = chan->tvnorms[chan->tvnorm].sheight; + maxh = maxLinesPerField; + field = f->fmt.pix.field; + + if (V4L2_FIELD_ANY == field) + field = (f->fmt.pix.height > maxh / 2) + ? V4L2_FIELD_INTERLACED : V4L2_FIELD_BOTTOM; + + if (V4L2_FIELD_SEQ_BT == field) + field = V4L2_FIELD_SEQ_TB; + + /* update data for the application */ + f->fmt.pix.field = field; + if (f->fmt.pix.width < 48) + f->fmt.pix.width = 48; + if (f->fmt.pix.height < 32) + f->fmt.pix.height = 32; + if (f->fmt.pix.width > maxw) + f->fmt.pix.width = maxw; + if (f->fmt.pix.height > maxh) + f->fmt.pix.height = maxh; + f->fmt.pix.width &= ~0x03; + f->fmt.pix.bytesperline = + (f->fmt.pix.width * fmt->depth) >> 3; + f->fmt.pix.sizeimage = + f->fmt.pix.height * f->fmt.pix.bytesperline; + + return 0; + } + + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + return -EINVAL; + + case V4L2_BUF_TYPE_VBI_CAPTURE: + return 0; + + default: + return -EINVAL; + } +} + +/****************************************************************************/ +/* Analog driver stuff ******************************************************/ +/****************************************************************************/ + +static int check_alloc_res(struct ngene_channel *channel, + struct ngene_vopen *vopen, int bit) +{ + if (vopen->resources & bit) + /* have it already allocated */ + return 1; + + /* is it free? */ + down(&channel->reslock); + if (channel->resources & bit) { + /* no, someone else uses it */ + up(&channel->reslock); + return 0; + } + /* it's free, grab it */ + vopen->resources |= bit; + channel->resources |= bit; + up(&channel->reslock); + return 1; +} + +static int check_res(struct ngene_vopen *vopen, int bit) +{ + return vopen->resources & bit; +} + +static int locked_res(struct ngene_channel *chan, int bit) +{ + return chan->resources & bit; +} + +static void free_res(struct ngene_channel *channel, + struct ngene_vopen *vopen, int bits) +{ + down(&channel->reslock); + vopen->resources &= ~bits; + channel->resources &= ~bits; + up(&channel->reslock); +} + +/****************************************************************************/ +/* MISC HELPERS *************************************************************/ +/****************************************************************************/ + +static int ngene_g_fmt(struct ngene_vopen *vopen, struct v4l2_format *f) +{ + if (!vopen->fmt) + vopen->fmt = ngene_formats; + + switch (f->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + memset(&f->fmt.pix, 0, sizeof(struct v4l2_pix_format)); + f->fmt.pix.width = vopen->width; + f->fmt.pix.height = vopen->height; + f->fmt.pix.field = vopen->vbuf_q.field; + f->fmt.pix.pixelformat = vopen->fmt->fourcc; + f->fmt.pix.bytesperline = (f->fmt.pix.width * 16) >> 3; + f->fmt.pix.sizeimage = + f->fmt.pix.height * f->fmt.pix.bytesperline; + return 0; + + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + memset(&f->fmt.win, 0, sizeof(struct v4l2_window)); + return 0; + f->fmt.win.w = vopen->ov.w; + f->fmt.win.field = vopen->ov.field; + return 0; + + case V4L2_BUF_TYPE_VBI_CAPTURE: + return -EINVAL; + + default: + return -EINVAL; + } +} + +static int ngene_switch_type(struct ngene_vopen *vopen, enum v4l2_buf_type type) +{ + struct videobuf_queue *q = ngene_queue(vopen); + int res = ngene_resource(vopen); + + if (check_res(vopen, res)) + return -EBUSY; + if (videobuf_queue_is_busy(q)) + return -EBUSY; + vopen->type = type; + return 0; +} + +static int ngene_s_fmt(struct ngene_vopen *vopen, struct ngene_channel *chan, + struct v4l2_format *f) +{ + int retval; + + switch (f->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + { + const struct ngene_format *fmt; + retval = ngene_try_fmt(vopen, chan, f); + if (0 != retval) + return retval; + + retval = ngene_switch_type(vopen, f->type); + if (0 != retval) + return retval; + fmt = ngene_formats; + + if (f->fmt.pix.pixelformat != V4L2_PIX_FMT_YUYV) + return -EINVAL; + /* update our state informations */ + mutex_lock(&vopen->vbuf_q.lock); + vopen->fmt = fmt; + vopen->vbuf_q.field = f->fmt.pix.field; + vopen->vbuf_q.last = V4L2_FIELD_INTERLACED; + vopen->width = f->fmt.pix.width; + vopen->height = f->fmt.pix.height; + chan->init.fmt = fmt; + chan->init.width = f->fmt.pix.width; + chan->init.height = f->fmt.pix.height; + mutex_unlock(&vopen->vbuf_q.lock); + + return 0; + } + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + return -EINVAL; + case V4L2_BUF_TYPE_VBI_CAPTURE: + return -EINVAL; + default: + return -EINVAL; + } +} + +/****************************************************************************/ +/* SG support ***************************************************************/ +/****************************************************************************/ + +static inline enum km_type ngene_kmap_type(int out) +{ + return ngene_km_types[(in_softirq() ? 2 : 0) + out]; +} + +static inline void *ngene_kmap(struct page *page, int out) +{ + return kmap_atomic(page, ngene_kmap_type(out)); +} + +static inline void ngene_kunmap(void *vaddr, int out) +{ + kunmap_atomic(vaddr, ngene_kmap_type(out)); +} + +struct scatter_walk { + struct scatterlist *sg; + struct page *page; + void *data; + unsigned int len_this_page; + unsigned int len_this_segment; + unsigned int offset; +}; + +static inline struct scatterlist *sg_next(struct scatterlist *sg) +{ + return sg + 1; +} + +void *scatterwalk_whichbuf(struct scatter_walk *walk, unsigned int nbytes) +{ + if (nbytes <= walk->len_this_page && + (((unsigned long)walk->data) & + (PAGE_CACHE_SIZE - 1)) + nbytes <= PAGE_CACHE_SIZE) + return walk->data; + else + return walk->data; +} + +void scatterwalk_start(struct scatter_walk *walk, struct scatterlist *sg) +{ + unsigned int rest_of_page; + + walk->sg = sg; + walk->page = sg->page; + walk->len_this_segment = sg->length; + rest_of_page = PAGE_CACHE_SIZE - (sg->offset & (PAGE_CACHE_SIZE - 1)); + walk->len_this_page = min(sg->length, rest_of_page); + walk->offset = sg->offset; +} + +void scatterwalk_map(struct scatter_walk *walk, int out) +{ + walk->data = ngene_kmap(walk->page, out) + walk->offset; +} + +static void scatterwalk_pagedone(struct scatter_walk *walk, int out, + unsigned int more) +{ + /* walk->data may be pointing the first byte of the next page; + however, we know we transfered at least one byte. So, + walk->data - 1 will be a virtual address in the mapped page. */ + + if (out) + flush_dcache_page(walk->page); + + if (more) { + walk->len_this_segment -= walk->len_this_page; + + if (walk->len_this_segment) { + walk->page++; + walk->len_this_page = min(walk->len_this_segment, + (unsigned)PAGE_CACHE_SIZE); + walk->offset = 0; + } else { + scatterwalk_start(walk, sg_next(walk->sg)); + } + } +} + +void scatterwalk_done(struct scatter_walk *walk, int out, int more) +{ + ngene_kunmap(walk->data, out); + if (walk->len_this_page == 0 || !more) + scatterwalk_pagedone(walk, out, more); +} + +/* + * Do not call this unless the total length of all of the fragments + * has been verified as multiple of the block size. + */ +int scatterwalk_copychunks(struct scatter_walk *walk, size_t nbytes, int out) +{ + walk->offset += nbytes; + walk->len_this_page -= nbytes; + walk->len_this_segment -= nbytes; + return 0; +} + +static void *vid_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags) +{ + struct ngene_channel *chan = priv; + struct ngene_buffer *item; + int wstrich, hstrich; + u8 *odd, *even; + u32 bpl = chan->tvnorms[chan->tvnorm].swidth * 2; + + struct scatter_walk walk_out; + const unsigned int bsize = PAGE_SIZE; + unsigned int nbytes; + int rest_of_buffer, ah, rwstrich; + + spin_lock(&chan->s_lock); + + if (list_empty(&chan->capture)) { + chan->evenbuffer = NULL; + goto out; + } + item = list_entry(chan->capture.next, struct ngene_buffer, vb.queue); + + if (chan->tvnorms[chan->tvnorm].sheight == 1080) + buf += 3840; + + odd = buf; + + hstrich = item->vb.height; + if (hstrich > chan->tvnorms[chan->tvnorm].sheight) + hstrich = chan->tvnorms[chan->tvnorm].sheight; + + wstrich = item->vb.width; + if (wstrich > chan->tvnorms[chan->tvnorm].swidth) + wstrich = chan->tvnorms[chan->tvnorm].swidth; + wstrich <<= 1; + + if (flags & BEF_EVEN_FIELD) { + chan->evenbuffer = buf; + if (chan->lastbufferflag) { + chan->lastbufferflag = 0; + if (chan->tvnorms[chan->tvnorm].sheight == 576) { + memcpy(buf + 413280, BlackLine, 1440); + memcpy(buf + 411840, BlackLine, 1440); + } + goto out; + } + } + chan->lastbufferflag = 1; + if (chan->evenbuffer) + even = chan->evenbuffer; + else + even = odd; + if (chan->tvnorms[chan->tvnorm].sheight == 576) { + memcpy(odd + 413280, BlackLine, 1440); + memcpy(odd + 411840, BlackLine, 1440); + } + nbytes = item->vb.dma.sglen * PAGE_SIZE; + scatterwalk_start(&walk_out, item->vb.dma.sglist); + ah = 0; + rwstrich = wstrich; + do { + u8 *dst_p; + + rest_of_buffer = bsize; + scatterwalk_map(&walk_out, 1); + dst_p = scatterwalk_whichbuf(&walk_out, bsize); + nbytes -= bsize; + scatterwalk_copychunks(&walk_out, bsize, 1); + + while (rest_of_buffer > 0 && ah < hstrich) { + if (rest_of_buffer >= rwstrich) { + if (ah % 2 == 0) { + memcpy(walk_out.data + + (bsize - rest_of_buffer), + odd, rwstrich); + odd += bpl - (wstrich - rwstrich); + } else { + memcpy(walk_out.data + + (bsize - rest_of_buffer), + even, rwstrich); + even += bpl - (wstrich - rwstrich); + } + rest_of_buffer -= rwstrich; + ah++; + rwstrich = wstrich; + } else { + if (ah % 2 == 0) { + memcpy(walk_out.data + + (bsize - rest_of_buffer), + odd, rest_of_buffer); + odd += rest_of_buffer; + } else { + memcpy(walk_out.data + + (bsize - rest_of_buffer), + even, rest_of_buffer); + even += rest_of_buffer; + } + rwstrich -= rest_of_buffer; + rest_of_buffer = 0; + } + } + scatterwalk_done(&walk_out, 1, nbytes); + } while (nbytes && ah < hstrich); + + { + struct timeval ts; + do_gettimeofday(&ts); + list_del(&item->vb.queue); + item->vb.state = STATE_DONE; + item->vb.ts = ts; + wake_up(&item->vb.done); + chan->evenbuffer = NULL; + } + +out: + spin_unlock(&chan->s_lock); + return 0; +} + +static void *snd_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags) +{ + struct ngene_channel *chan = priv; + struct mychip *mychip = chan->mychip; + + if (chan->audiomute == 0) + memcpy(chan->soundbuffer, (u8 *) buf, MAX_AUDIO_BUFFER_SIZE); + else + memset(chan->soundbuffer, 0, MAX_AUDIO_BUFFER_SIZE); + + if (mychip->substream != NULL) { + if (chan->sndbuffflag == 0) + chan->sndbuffflag = 1; + else + chan->sndbuffflag = 0; + spin_unlock(&mychip->lock); + snd_pcm_period_elapsed(mychip->substream); + spin_lock(&mychip->lock); + } + return 0; +} + +static void set_analog_transfer(struct ngene_channel *chan, int state) +{ + struct ngene_channel *ch; + u8 flags = 0; + + ch = &chan->dev->channel[chan->number + 2]; + /* printk(KERN_INFO "set_analog_transfer %d\n", state); */ + + if (1) { /* chan->tun_dec_rdy == 1){ */ + if (state) { + + chan->Capture1Length = + chan->tvnorms[chan->tvnorm].swidth * + chan->tvnorms[chan->tvnorm].sheight; + if (chan->tvnorms[chan->tvnorm].sheight == 576) + chan->nLines = 287; + else if (chan->tvnorms[chan->tvnorm].sheight == 1080) + chan->nLines = 541; + else + chan->nLines = + chan->tvnorms[chan->tvnorm].sheight / 2; + chan->nBytesPerLine = + chan->tvnorms[chan->tvnorm].swidth * 2; + if (chan->dev->card_info->io_type[chan->number] == + NGENE_IO_HDTV) { + chan->itumode = 2; + flags = SFLAG_ORDER_LUMA_CHROMA; + } else { + chan->itumode = 0; + flags = SFLAG_ORDER_LUMA_CHROMA; + } + chan->pBufferExchange = vid_exchange; + ngene_command_stream_control(chan->dev, chan->number, + 0x80, + SMODE_VIDEO_CAPTURE, + flags); + + ch->Capture1Length = MAX_AUDIO_BUFFER_SIZE; + ch->pBufferExchange = snd_exchange; + ngene_command_stream_control(ch->dev, ch->number, + 0x80, + SMODE_AUDIO_CAPTURE, 0); + ch->soundstreamon = 1; + } else { + ngene_command_stream_control(chan->dev, chan->number, + 0, 0, 0); + ngene_command_stream_control(ch->dev, ch->number, + 0, 0, 0); + ch->soundstreamon = 0; + } + } +} + +static int ngene_analog_start_feed(struct ngene_channel *chan) +{ + int freerunmode = 1; + struct i2c_adapter *adapter = &chan->i2c_adapter; + + if (chan->users == 0 && chan->number < 2) { + chan->evenbuffer = NULL; + chan->users = 1; + i2c_clients_command(adapter, IOCTL_MIC_DEC_FREESYNC, + &freerunmode); + msleep(25); + set_analog_transfer(chan, 1); + msleep(25); + freerunmode = 0; + i2c_clients_command(adapter, IOCTL_MIC_DEC_FREESYNC, + &freerunmode); + } + return chan->users; +} + +static int ngene_analog_stop_feed(struct ngene_channel *chan) +{ + int freerunmode = 1; + struct i2c_adapter *adapter = &chan->i2c_adapter; + if (chan->users == 1 && chan->number < 2) { + chan->users = 0; + i2c_clients_command(adapter, + IOCTL_MIC_DEC_FREESYNC, &freerunmode); + msleep(20); + set_analog_transfer(chan, 0); + } + return 0; +} + +/****************************************************************************/ +/* V4L2 API interface *******************************************************/ +/****************************************************************************/ + +void ngene_dma_free(struct videobuf_queue *q, + struct ngene_channel *chan, struct ngene_buffer *buf) +{ + videobuf_waiton(&buf->vb, 0, 0); + videobuf_dma_unmap(q, &buf->vb.dma); + videobuf_dma_free(&buf->vb.dma); + buf->vb.state = STATE_NEEDS_INIT; +} + +static int ngene_prepare_buffer(struct videobuf_queue *q, + struct ngene_channel *chan, + struct ngene_buffer *buf, + const struct ngene_format *fmt, + unsigned int width, unsigned int height, + enum v4l2_field field) +{ + int rc = 0; + /* check settings */ + if (NULL == fmt) + return -EINVAL; + + if (width < 48 || height < 32) + return -EINVAL; + + buf->vb.size = (width * height * 16 /* fmt->depth */) >> 3; + if (0 != buf->vb.baddr && buf->vb.bsize < buf->vb.size) + return -EINVAL; + + /* alloc + fill struct ngene_buffer (if changed) */ + if (buf->vb.width != width || buf->vb.height != height || + buf->vb.field != field || buf->fmt != fmt || + buf->tvnorm != chan->tvnorm) { + + buf->vb.width = width; + buf->vb.height = height; + buf->vb.field = field; + buf->tvnorm = chan->tvnorm; + buf->fmt = fmt; + + ngene_dma_free(q, chan, buf); + } + + if (0 != buf->vb.baddr && buf->vb.bsize < buf->vb.size) + return -EINVAL; + + if (buf->vb.field == 0) + buf->vb.field = V4L2_FIELD_INTERLACED; + + if (STATE_NEEDS_INIT == buf->vb.state) { + buf->vb.width = width; + buf->vb.height = height; + buf->vb.field = field; + buf->tvnorm = chan->tvnorm; + buf->fmt = fmt; + + rc = videobuf_iolock(q, &buf->vb, &chan->fbuf); + if (0 != rc) + goto fail; + } + if (!buf->vb.dma.bus_addr) + videobuf_dma_sync(q, &buf->vb.dma); + buf->vb.state = STATE_PREPARED; + return 0; + +fail: + ngene_dma_free(q, chan, buf); + return rc; + +} + +static int buffer_setup(struct videobuf_queue *q, + unsigned int *count, unsigned int *size) +{ + struct ngene_vopen *vopen = q->priv_data; + *size = 2 * vopen->width * vopen->height; + if (0 == *count) + *count = gbuffers; + while (*size * *count > gbuffers * gbufsize) + (*count)--; + q->field = V4L2_FIELD_INTERLACED; + q->last = V4L2_FIELD_INTERLACED; + return 0; +} + +static int buffer_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb, + enum v4l2_field field) +{ + struct ngene_buffer *buf = container_of(vb, struct ngene_buffer, vb); + struct ngene_vopen *vopen = q->priv_data; + return ngene_prepare_buffer(q, vopen->ch, buf, vopen->fmt, + vopen->width, vopen->height, field); +} + +static void buffer_release(struct videobuf_queue *q, struct videobuf_buffer *vb) +{ + struct ngene_buffer *buf = container_of(vb, struct ngene_buffer, vb); + struct ngene_vopen *vopen = q->priv_data; + ngene_dma_free(q, vopen->ch, buf); +} + +static void buffer_queue(struct videobuf_queue *q, struct videobuf_buffer *vb) +{ + struct ngene_buffer *buf = container_of(vb, struct ngene_buffer, vb); + struct ngene_vopen *vopen = q->priv_data; + struct ngene_channel *chan = vopen->ch; + + buf->vb.state = STATE_QUEUED; + list_add_tail(&buf->vb.queue, &chan->capture); +} + +static struct videobuf_queue_ops ngene_video_qops = { + .buf_setup = buffer_setup, + .buf_prepare = buffer_prepare, + .buf_queue = buffer_queue, + .buf_release = buffer_release, +}; + +int video_open(struct inode *inode, struct file *flip) +{ + struct ngene_vopen *vopen = NULL; + enum v4l2_buf_type type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + struct video_device *vd = video_devdata(flip); + struct ngene_channel *chan = my_video_get_drvdata(vd); + + vopen = kmalloc(sizeof(*vopen), GFP_KERNEL); + if (!vopen) + return -ENOMEM; + memset(vopen, 0, sizeof(*vopen)); + flip->private_data = vopen; + v4l2_prio_open(&chan->prio, &vopen->prio); + vopen->ch = chan; + vopen->picxcount = 0; + vopen->type = type; + videobuf_queue_init(&vopen->vbuf_q, &ngene_video_qops, + chan->dev->pci_dev, &chan->s_lock, + V4L2_BUF_TYPE_VIDEO_CAPTURE, + V4L2_FIELD_INTERLACED, + sizeof(struct ngene_buffer), vopen); + + vopen->ovfmt = ngene_formats; + chan->videousers++; + if (chan->dev->card_info->switch_ctrl) + chan->dev->card_info->switch_ctrl(chan, 2, 1); + return 0; +} + +int video_close(struct inode *inode, struct file *filp) +{ + struct ngene_vopen *vopen = filp->private_data; + struct ngene_channel *chan = vopen->ch; + + chan->videousers--; + if (!chan->videousers) { + if (chan->dev->card_info->switch_ctrl) + chan->dev->card_info->switch_ctrl(chan, 2, 0); + ngene_analog_stop_feed(chan); + } + videobuf_mmap_free(&vopen->vbuf_q); + v4l2_prio_close(&chan->prio, &vopen->prio); + filp->private_data = NULL; + kfree(vopen); + return 0; +} + +/****************************************************************************/ + +static int vid_do_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, void *parg) +{ + struct ngene_vopen *vopen = file->private_data; + struct ngene_channel *chan = vopen->ch; + struct ngene *dev = chan->dev; + struct i2c_adapter *adap = &chan->i2c_adapter; + int retval = 0; + int err = 0; + + switch (cmd) { + + case VIDIOC_S_CTRL: + { + struct v4l2_control *c = parg; + + err = v4l2_prio_check(&chan->prio, &vopen->prio); + if (err) + return err; + + if (c->id == V4L2_CID_AUDIO_MUTE) { + if (c->value) + (dev->channel[chan->number + 2]).audiomute = 1; + else + (dev->channel[chan->number + 2]).audiomute = 0; + return 0; + } + if (c->value != V4L2_CID_AUDIO_MUTE) + ngene_analog_stop_feed(chan); + i2c_clients_command(adap, cmd, parg); + return 0; + } + + case VIDIOC_S_TUNER: + { + err = v4l2_prio_check(&chan->prio, &vopen->prio); + if (err != 0) + return err; + i2c_clients_command(adap, cmd, parg); + return 0; + } + + case VIDIOC_S_FREQUENCY: + { + struct v4l2_frequency *f = parg; + u8 drxa = dev->card_info->demoda[chan->number]; + + if (chan->fe && chan->fe->ops.tuner_ops.set_frequency) + chan->fe->ops.tuner_ops. + set_frequency(chan->fe, f->frequency * 62500); + if (drxa) + ; + } + + case VIDIOC_S_INPUT: + { + err = v4l2_prio_check(&chan->prio, &vopen->prio); + if (err != 0) + return err; + i2c_clients_command(adap, cmd, parg); + return 0; + } + + case VIDIOC_G_STD: + { + v4l2_std_id *id = parg; + *id = chan->tvnorms[chan->tvnorm].v4l2_id; + return 0; + } + + case VIDIOC_S_STD: + { + v4l2_std_id *id = parg; + unsigned int i; + + err = v4l2_prio_check(&chan->prio, &vopen->prio); + if (err != 0) + return err; + ngene_analog_stop_feed(chan); + i2c_clients_command(adap, cmd, parg); + for (i = 0; i < chan->tvnorm_num; i++) + if (*id & chan->tvnorms[i].v4l2_id) + break; + if (i == chan->tvnorm_num) + return -EINVAL; + + chan->tvnorm = i; + mdelay(50); + ngene_analog_start_feed(chan); + return 0; + } + + case VIDIOC_G_FREQUENCY: + case VIDIOC_G_INPUT: + case VIDIOC_S_AUDIO: + case VIDIOC_G_AUDIO: + case VIDIOC_ENUMAUDIO: + case VIDIOC_S_MODULATOR: + case VIDIOC_G_MODULATOR: + case VIDIOC_G_CTRL: + { + i2c_clients_command(adap, cmd, parg); + return 0; + } + + case VIDIOC_G_TUNER: + { + struct v4l2_tuner *tuner = parg; + if (tuner->index != 0) + return -EINVAL; + i2c_clients_command(adap, cmd, parg); + + if (chan->fe && chan->fe->ops.tuner_ops.get_status) { + u32 status; + + chan->fe->ops.tuner_ops.get_status(chan->fe, &status); + tuner->signal = status; + } + return 0; + } + + case VIDIOC_QUERYCTRL: + { + struct v4l2_queryctrl *c = parg; + int i; + + if ((c->id < V4L2_CID_BASE || + c->id >= V4L2_CID_LASTP1) && + (c->id < V4L2_CID_PRIVATE_BASE || + c->id >= V4L2_CID_PRIVATE_LASTP1)) + return -EINVAL; + for (i = 0; i < NGENE_CTLS; i++) + if (ngene_ctls[i].id == c->id) + break; + if (i == NGENE_CTLS) { + *c = no_ctl; + return 0; + } + *c = ngene_ctls[i]; + return 0; + } + + case VIDIOC_G_FMT: + { + struct v4l2_format *f = parg; + ngene_g_fmt(vopen, f); + } + + case VIDIOC_S_FMT: + { + struct v4l2_format *f = parg; + + ngene_analog_stop_feed(chan); + return ngene_s_fmt(vopen, chan, f); + } + + case VIDIOC_ENUM_FMT: + { + struct v4l2_fmtdesc *f = parg; + enum v4l2_buf_type type; + unsigned int i; + int index; + + type = f->type; + if (V4L2_BUF_TYPE_VBI_CAPTURE == type) { + /* vbi + index = f->index; + if (0 != index) + return -EINVAL; + memset(f, 0, sizeof(*f)); + f->index = index; + f->type = type; + f->pixelformat = V4L2_PIX_FMT_GREY; + strcpy(f->description, "vbi data"); */ + return EINVAL; + } + + /* video capture + overlay */ + index = -1; + for (i = 0; i < NGENE_FORMATS; i++) { + if (ngene_formats[i].fourcc != -1) + index++; + if ((unsigned int)index == f->index) + break; + } + if (NGENE_FORMATS == i) + return -EINVAL; + + switch (f->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + break; + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + /* dprintk(KERN_DEBUG + "Video Overlay not supported yet.\n"); */ + return -EINVAL; + break; + default: + return -EINVAL; + } + memset(f, 0, sizeof(*f)); + f->index = index; + f->type = type; + f->pixelformat = ngene_formats[i].fourcc; + strlcpy(f->description, ngene_formats[i].name, + sizeof(f->description)); + return 0; + + } + + case VIDIOC_QUERYSTD: + { + v4l2_std_id *id = parg; + *id = V4L2_STD_625_50 | V4L2_STD_525_60; + return 0; + } + + case VIDIOC_ENUMSTD: + { + struct v4l2_standard *e = parg; + unsigned int index = e->index; + + if (index >= chan->tvnorm_num) + return -EINVAL; + v4l2_video_std_construct(e, chan->tvnorms[e->index].v4l2_id, + chan->tvnorms[e->index].name); + e->index = index; + return 0; + } + + case VIDIOC_QUERYCAP: + { + static char driver[] = {'n', 'G', 'e', 'n', 'e', '\0'}; + static char card[] = {'M', 'k', '4', 'x', 'x', '\0'}; + struct v4l2_capability *cap = parg; + + memset(cap, 0, sizeof(*cap)); + if (dev->nr == 0) + card[3] = '0'; + else + card[3] = '1'; + if (chan->number) + card[4] = 'a'; + else + card[4] = 'b'; + strlcpy(cap->driver, driver, sizeof(cap->driver)); + strlcpy(cap->card, card, sizeof(cap->card)); + cap->bus_info[0] = 0; + cap->version = KERNEL_VERSION(0, 8, 1); + cap->capabilities = V4L2_CAP_VIDEO_CAPTURE| + V4L2_CAP_TUNER|V4L2_CAP_AUDIO| + V4L2_CAP_READWRITE|V4L2_CAP_STREAMING; + return 0; + } + + case VIDIOC_ENUMINPUT: + { + static char *inputname[2] = { + "AnalogTuner", + "S-Video" + }; + + struct v4l2_input *i = parg; + unsigned int index; + index = i->index; + + if (index > 1) + return -EINVAL; + + memset(i, 0, sizeof(*i)); + i->index = index; + strlcpy(i->name, inputname[index], sizeof(i->name)); + + i->type = index ? V4L2_INPUT_TYPE_CAMERA : + V4L2_INPUT_TYPE_TUNER; + i->audioset = 0; + i->tuner = 0; + i->std = V4L2_STD_PAL_BG | V4L2_STD_NTSC_M; + i->status = 0;/* V4L2_IN_ST_NO_H_LOCK; */ + return 0; + } + + case VIDIOC_G_PARM: + return -EINVAL; + + case VIDIOC_S_PARM: + return -EINVAL; + + case VIDIOC_G_PRIORITY: + { + enum v4l2_priority *prio = parg; + *prio = v4l2_prio_max(&chan->prio); + return 0; + } + + case VIDIOC_S_PRIORITY: + { + enum v4l2_priority *prio = parg; + return v4l2_prio_change(&chan->prio, &vopen->prio, *prio); + return 0; + } + + case VIDIOC_CROPCAP: + return -EINVAL; + + case VIDIOC_G_CROP: + return -EINVAL; + + case VIDIOC_S_CROP: + return -EINVAL; + + case VIDIOC_G_FBUF: + { + struct v4l2_framebuffer *fb = parg; + + *fb = chan->fbuf; + fb->capability = 0; + if (vopen->ovfmt) + fb->fmt.pixelformat = vopen->ovfmt->fourcc; + return 0; + } + + case VIDIOC_REQBUFS: + return videobuf_reqbufs(ngene_queue(vopen), parg); + + case VIDIOC_QUERYBUF: + return videobuf_querybuf(ngene_queue(vopen), parg); + + case VIDIOC_QBUF: + return videobuf_qbuf(ngene_queue(vopen), parg); + + case VIDIOC_DQBUF: + return videobuf_dqbuf(ngene_queue(vopen), parg, + file->f_flags & O_NONBLOCK); + + case VIDIOC_S_FBUF: + { + /* ngene_analog_stop_feed(chan); */ + struct v4l2_framebuffer *fb = parg; + const struct ngene_format *fmt; + + if (!capable(CAP_SYS_ADMIN) && !capable(CAP_SYS_RAWIO)) + return -EPERM; + + /* check args */ + fmt = ngene_formats; /*format_by_fourcc(fb->fmt.pixelformat);*/ + if (NULL == fmt) + return -EINVAL; + + if (0 == (fmt->flags & 0x02 /*FORMAT_FLAGS_PACKED*/)) + return -EINVAL; + + mutex_lock(&vopen->vbuf_q.lock); + retval = -EINVAL; + + if (fb->flags & V4L2_FBUF_FLAG_OVERLAY) { + int maxLinesPerField; + + if (fb->fmt.width > + chan->tvnorms[chan->tvnorm].swidth) + goto vopen_unlock_and_return; + maxLinesPerField = chan->tvnorms[chan->tvnorm].sheight; + if (fb->fmt.height > maxLinesPerField) + goto vopen_unlock_and_return; + } + + /* ok, accept it */ + chan->fbuf.base = fb->base; + chan->fbuf.fmt.width = fb->fmt.width; + chan->fbuf.fmt.height = fb->fmt.height; + if (0 != fb->fmt.bytesperline) + chan->fbuf.fmt.bytesperline = fb->fmt.bytesperline; + else + chan->fbuf.fmt.bytesperline = + chan->fbuf.fmt.width * fmt->depth / 8; + + retval = 0; + vopen->ovfmt = fmt; + chan->init.ovfmt = fmt; + +vopen_unlock_and_return: + mutex_unlock(&vopen->vbuf_q.lock); + return retval; + + } + + case VIDIOC_ENUMOUTPUT: + return -EINVAL; + + case VIDIOC_TRY_FMT: + { + struct v4l2_format *f = parg; + return ngene_try_fmt(vopen, chan, f); + + } + + case VIDIOC_STREAMON: + { + int res = ngene_resource(vopen); + if (!check_alloc_res(chan, vopen, res)) + return -EBUSY; + ngene_analog_start_feed(chan); + return videobuf_streamon(ngene_queue(vopen)); + } + + case VIDIOC_STREAMOFF: + { + int res = ngene_resource(vopen); + int retval = videobuf_streamoff(ngene_queue(vopen)); + ngene_analog_stop_feed(chan); + if (retval < 0) + return retval; + + free_res(chan, vopen, res); + return 0; + } + + case VIDIOC_OVERLAY: + return -EINVAL; + + case VIDIOCGFBUF: + { + struct video_buffer *vb = parg; + + memset(vb, 0, sizeof(*vb)); + return 0; + } + + default: + err = -EINVAL; + break; + } + return err; +} + +/* +static int vid_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + return video_usercopy(inode, file, cmd, arg, vid_do_ioctl); +} +*/ +static unsigned int video_fix_command(unsigned int cmd) +{ + switch (cmd) { + } + return cmd; +} + +static int vid_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + void *parg = (void *)arg, *pbuf = NULL; + char buf[64]; + int res = -EFAULT; + cmd = video_fix_command(cmd); + + if (_IOC_DIR(cmd) & _IOC_WRITE) { + parg = buf; + if (_IOC_SIZE(cmd) > sizeof(buf)) { + pbuf = kmalloc(_IOC_SIZE(cmd), GFP_KERNEL); + if (!pbuf) + return -ENOMEM; + parg = pbuf; + } + if (copy_from_user(parg, (void __user *)arg, _IOC_SIZE(cmd))) + goto error; + } + res = vid_do_ioctl(inode, file, cmd, parg); + if (res < 0) + goto error; + if (_IOC_DIR(cmd) & _IOC_READ) + if (copy_to_user((void __user *)arg, parg, _IOC_SIZE(cmd))) + res = -EFAULT; +error: + kfree(pbuf); + return res; +} + +static int ngene_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct ngene_vopen *vopen = file->private_data; + return videobuf_mmap_mapper(ngene_queue(vopen), vma); +} + +#define MAGIC_BUFFER 0x20040302 +void *my_videobuf_alloc(unsigned int size) +{ + struct videobuf_buffer *vb; + + vb = kmalloc(size, GFP_KERNEL); + if (NULL != vb) { + memset(vb, 0, size); + videobuf_dma_init(&vb->dma); + init_waitqueue_head(&vb->done); + vb->magic = MAGIC_BUFFER; + } + return vb; +} + +static ssize_t driver_read(struct file *file, char *user, + size_t count, loff_t *offset) +{ + char __user *data = user; + struct ngene_channel *chan; + int retval = 0; + struct videobuf_queue *q; + struct ngene_vopen *vopen = file->private_data; + int nonblocking = file->f_flags & O_NONBLOCK; + enum v4l2_field field; + unsigned long flags; + unsigned size, nbufs, bytes; + + if (!vopen) + return 0; + + chan = vopen->ch; + q = &vopen->vbuf_q; + + mutex_lock(&q->lock); + nbufs = 1; + size = 0; + q->ops->buf_setup(q, &nbufs, &size); + + if (NULL == q->read_buf) { + /* need to capture a new frame */ + retval = -ENOMEM; + q->read_buf = my_videobuf_alloc(q->msize); + if (NULL == q->read_buf) + goto done; + + q->read_buf->memory = V4L2_MEMORY_USERPTR; + field = V4L2_FIELD_INTERLACED; + retval = q->ops->buf_prepare(q, q->read_buf, field); + if (0 != retval) { + kfree(q->read_buf); + q->read_buf = NULL; + goto done; + } + + spin_lock_irqsave(q->irqlock, flags); + q->ops->buf_queue(q, q->read_buf); + spin_unlock_irqrestore(q->irqlock, flags); + q->read_off = 0; + } + + ngene_analog_start_feed(chan); + /* wait until capture is done */ + retval = videobuf_waiton(q->read_buf, nonblocking, 1); + if (0 != retval) + goto done; + videobuf_dma_sync(q, &q->read_buf->dma); + + if (STATE_ERROR == q->read_buf->state) { + /* catch I/O errors */ + q->ops->buf_release(q, q->read_buf); + kfree(q->read_buf); + q->read_buf = NULL; + retval = -EIO; + goto done; + } + + /* copy to userspace */ + bytes = count; + if (bytes > q->read_buf->size - q->read_off) + bytes = q->read_buf->size - q->read_off; + retval = -EFAULT; + + if (copy_to_user(data, q->read_buf->dma.vmalloc + q->read_off, bytes)) + goto done; + + retval = bytes; + + q->read_off += bytes; + if (q->read_off == q->read_buf->size) { + /* all data copied, cleanup */ + q->ops->buf_release(q, q->read_buf); + kfree(q->read_buf); + q->read_buf = NULL; + } + +done: + mutex_unlock(&q->lock); + + ngene_analog_stop_feed(chan); + + return retval; +} + +static unsigned int ngene_poll(struct file *file, poll_table *wait) +{ + struct ngene_vopen *vopen = file->private_data; + struct ngene_buffer *buf; + enum v4l2_field field; + + if (check_res(vopen, RESOURCE_VIDEO)) { + /* streaming capture */ + if (list_empty(&vopen->vbuf_q.stream)) + return POLLERR; + buf = list_entry(vopen->vbuf_q.stream.next, + struct ngene_buffer, vb.stream); + } else { + /* read() capture */ + mutex_lock(&vopen->vbuf_q.lock); + if (NULL == vopen->vbuf_q.read_buf) { + /* need to capture a new frame */ + if (locked_res(vopen->ch, RESOURCE_VIDEO)) { + mutex_unlock(&vopen->vbuf_q.lock); + return POLLERR; + } + vopen->vbuf_q.read_buf = + videobuf_alloc(vopen->vbuf_q.msize); + if (NULL == vopen->vbuf_q.read_buf) { + mutex_unlock(&vopen->vbuf_q.lock); + return POLLERR; + } + vopen->vbuf_q.read_buf->memory = V4L2_MEMORY_USERPTR; + field = videobuf_next_field(&vopen->vbuf_q); + if (0 != + vopen->vbuf_q.ops-> + buf_prepare(&vopen->vbuf_q, + vopen->vbuf_q.read_buf, field)) { + mutex_unlock(&vopen->vbuf_q.lock); + return POLLERR; + } + vopen->vbuf_q.ops->buf_queue(&vopen->vbuf_q, + vopen->vbuf_q.read_buf); + vopen->vbuf_q.read_off = 0; + } + mutex_unlock(&vopen->vbuf_q.lock); + buf = (struct ngene_buffer *)vopen->vbuf_q.read_buf; + } + + poll_wait(file, &buf->vb.done, wait); + if (buf->vb.state == STATE_DONE || buf->vb.state == STATE_ERROR) + return POLLIN | POLLRDNORM; + return 0; +} + +static const struct file_operations ngene_fops = { + .owner = THIS_MODULE, + .read = driver_read, + .write = 0, + .open = video_open, + .release = video_close, + .ioctl = vid_ioctl, + .poll = ngene_poll, + .mmap = ngene_mmap, +}; + +static struct video_device ngene_cinfo = { + .name = "analog_Ngene", + .type = VID_TYPE_CAPTURE | VID_TYPE_TUNER | VID_TYPE_SCALES, + .fops = &ngene_fops, + .minor = -1, +}; + +void ngene_v4l2_remove(struct ngene_channel *chan) +{ + video_unregister_device(chan->v4l_dev); +} + +int ngene_v4l2_init(struct ngene_channel *chan) +{ + int ret = 0; + struct video_device *v_dev; + + chan->evenbuffer = NULL; + chan->dma_on = 0; + + v_dev = video_device_alloc(); + *v_dev = ngene_cinfo; + /* v_dev->dev = &(chan->dev->pci_dev->dev); */ + v_dev->release = video_device_release; + v_dev->minor = -1; + video_register_device(v_dev, VFL_TYPE_GRABBER, -1); + snprintf(v_dev->name, sizeof(v_dev->name), "AnalognGene%d", + v_dev->minor); + chan->v4l_dev = v_dev; + chan->minor = v_dev->minor; + printk(KERN_INFO "nGene V4L2 device video%d registered.\n", + v_dev->minor); + + v_dev->dev = &chan->device; + my_video_set_drvdata(chan->v4l_dev, chan); + + v4l2_prio_init(&chan->prio); + + if (chan->dev->card_info->io_type[chan->number] == NGENE_IO_HDTV) { + chan->tvnorms = ngene_tvnorms_hd; + chan->tvnorm_num = 1; + } else { + chan->tvnorms = ngene_tvnorms_sd; + chan->tvnorm_num = NGENE_TVNORMS; + } + chan->tvnorm = 0; + + spin_lock_init(&chan->s_lock); + init_MUTEX(&chan->reslock); + INIT_LIST_HEAD(&chan->capture); + chan->users = 0; + chan->videousers = 0; + chan->init.ov.w.width = 384; + chan->init.ov.w.height = 288; + chan->init.fmt = ngene_formats; + chan->init.width = 384; + chan->init.height = 288; + chan->tun_rdy = 0; + chan->dec_rdy = 0; + chan->tun_dec_rdy = 0; + chan->lastbufferflag = -1; + + if (chan->dev->card_info->avf[chan->number]) + avf4910a_attach(&chan->i2c_adapter, + chan->dev->card_info->avf[chan->number]); + + return ret; +} diff --git a/drivers/media/dvb/ngene/ngene.h b/drivers/media/dvb/ngene/ngene.h new file mode 100644 index 000000000000..9b48250fdbf8 --- /dev/null +++ b/drivers/media/dvb/ngene/ngene.h @@ -0,0 +1,948 @@ +/* + * ngene.h: nGene PCIe bridge driver + * + * Copyright (C) 2005-2007 Micronas + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _NGENE_H_ +#define _NGENE_H_ + +#define ONE_ADAPTER +#define NGENE_COMMAND_API +/*#define NGENE_V4L*/ + +#include <linux/types.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/i2c.h> +#include <asm/dma.h> +#include <asm/scatterlist.h> +#include <sound/driver.h> +#include <sound/core.h> +#include <sound/initval.h> +#include <sound/control.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> + +#include <linux/dvb/frontend.h> +#include <linux/dvb/ca.h> +#include <linux/dvb/video.h> +#include <linux/dvb/audio.h> + +#include "dmxdev.h" +#include "dvbdev.h" +#include "dvb_demux.h" +#include "dvb_frontend.h" +#include "dvb_ringbuffer.h" +#include "drxd.h" +#include "drxh.h" +#include "xc3028.h" +#include "stb0899.h" +#include "stv0900.h" +#include "mt2060.h" + +#ifdef NGENE_V4L +#include <media/v4l2-dev.h> +#include <media/videobuf-core.h> +#include <linux/videodev.h> +#endif + +#define NGENE_VID 0x18c3 +#define NGENE_PID 0x0720 + +#ifndef VIDEO_CAP_VC1 +#define VIDEO_CAP_AVC 128 +#define VIDEO_CAP_H264 128 +#define VIDEO_CAP_VC1 256 +#define VIDEO_CAP_WMV9 256 +#define VIDEO_CAP_MPEG4 512 +#endif + +enum STREAM { + STREAM_VIDEOIN1 = 0, /* ITU656 or TS Input */ + STREAM_VIDEOIN2, + STREAM_AUDIOIN1, /* I2S or SPI Input */ + STREAM_AUDIOIN2, + STREAM_AUDIOOUT, + MAX_STREAM +}; + +enum SMODE_BITS { + SMODE_AUDIO_SPDIF = 0x20, + SMODE_AVSYNC = 0x10, + SMODE_TRANSPORT_STREAM = 0x08, + SMODE_AUDIO_CAPTURE = 0x04, + SMODE_VBI_CAPTURE = 0x02, + SMODE_VIDEO_CAPTURE = 0x01 +}; + +enum STREAM_FLAG_BITS { + SFLAG_CHROMA_FORMAT_2COMP = 0x01, /* Chroma Format : 2's complement */ + SFLAG_CHROMA_FORMAT_OFFSET = 0x00, /* Chroma Format : Binary offset */ + SFLAG_ORDER_LUMA_CHROMA = 0x02, /* Byte order: Y,Cb,Y,Cr */ + SFLAG_ORDER_CHROMA_LUMA = 0x00, /* Byte order: Cb,Y,Cr,Y */ + SFLAG_COLORBAR = 0x04, /* Select colorbar */ +}; + +#define PROGRAM_ROM 0x0000 +#define PROGRAM_SRAM 0x1000 +#define PERIPHERALS0 0x8000 +#define PERIPHERALS1 0x9000 +#define SHARED_BUFFER 0xC000 + +#define HOST_TO_NGENE (SHARED_BUFFER+0x0000) +#define NGENE_TO_HOST (SHARED_BUFFER+0x0100) +#define NGENE_COMMAND (SHARED_BUFFER+0x0200) +#define NGENE_COMMAND_HI (SHARED_BUFFER+0x0204) +#define NGENE_STATUS (SHARED_BUFFER+0x0208) +#define NGENE_STATUS_HI (SHARED_BUFFER+0x020C) +#define NGENE_EVENT (SHARED_BUFFER+0x0210) +#define NGENE_EVENT_HI (SHARED_BUFFER+0x0214) +#define VARIABLES (SHARED_BUFFER+0x0210) + +#define NGENE_INT_COUNTS (SHARED_BUFFER+0x0260) +#define NGENE_INT_ENABLE (SHARED_BUFFER+0x0264) +#define NGENE_VBI_LINE_COUNT (SHARED_BUFFER+0x0268) + +#define BUFFER_GP_XMIT (SHARED_BUFFER+0x0800) +#define BUFFER_GP_RECV (SHARED_BUFFER+0x0900) +#define EEPROM_AREA (SHARED_BUFFER+0x0A00) + +#define SG_V_IN_1 (SHARED_BUFFER+0x0A80) +#define SG_VBI_1 (SHARED_BUFFER+0x0B00) +#define SG_A_IN_1 (SHARED_BUFFER+0x0B80) +#define SG_V_IN_2 (SHARED_BUFFER+0x0C00) +#define SG_VBI_2 (SHARED_BUFFER+0x0C80) +#define SG_A_IN_2 (SHARED_BUFFER+0x0D00) +#define SG_V_OUT (SHARED_BUFFER+0x0D80) +#define SG_A_OUT2 (SHARED_BUFFER+0x0E00) + +#define DATA_A_IN_1 (SHARED_BUFFER+0x0E80) +#define DATA_A_IN_2 (SHARED_BUFFER+0x0F00) +#define DATA_A_OUT (SHARED_BUFFER+0x0F80) +#define DATA_V_IN_1 (SHARED_BUFFER+0x1000) +#define DATA_V_IN_2 (SHARED_BUFFER+0x2000) +#define DATA_V_OUT (SHARED_BUFFER+0x3000) + +#define DATA_FIFO_AREA (SHARED_BUFFER+0x1000) + +#define TIMESTAMPS 0xA000 +#define SCRATCHPAD 0xA080 +#define FORCE_INT 0xA088 +#define FORCE_NMI 0xA090 +#define INT_STATUS 0xA0A0 + +#define DEV_VER 0x9004 + +#define FW_DEBUG_DEFAULT (PROGRAM_SRAM+0x00FF) + +struct SG_ADDR { + u64 start; + u64 curr; + u16 curr_ptr; + u16 elements; + u32 pad[3]; +} __attribute__ ((__packed__)); + +struct SHARED_MEMORY { + /* C000 */ + u32 HostToNgene[64]; + + /* C100 */ + u32 NgeneToHost[64]; + + /* C200 */ + u64 NgeneCommand; + u64 NgeneStatus; + u64 NgeneEvent; + + /* C210 */ + u8 pad1[0xc260 - 0xc218]; + + /* C260 */ + u32 IntCounts; + u32 IntEnable; + + /* C268 */ + u8 pad2[0xd000 - 0xc268]; + +} __attribute__ ((__packed__)); + +struct BUFFER_STREAM_RESULTS { + u32 Clock; /* Stream time in 100ns units */ + u16 RemainingLines; /* Remaining lines in this field. + 0 for complete field */ + u8 FieldCount; /* Video field number */ + u8 Flags; /* Bit 7 = Done, Bit 6 = seen, Bit 5 = overflow, + Bit 0 = FieldID */ + u16 BlockCount; /* Audio block count (unused) */ + u8 Reserved[2]; + u32 DTOUpdate; +} __attribute__ ((__packed__)); + +struct HW_SCATTER_GATHER_ELEMENT { + u64 Address; + u32 Length; + u32 Reserved; +} __attribute__ ((__packed__)); + +struct BUFFER_HEADER { + u64 Next; + struct BUFFER_STREAM_RESULTS SR; + + u32 Number_of_entries_1; + u32 Reserved5; + u64 Address_of_first_entry_1; + + u32 Number_of_entries_2; + u32 Reserved7; + u64 Address_of_first_entry_2; +} __attribute__ ((__packed__)); + +struct EVENT_BUFFER { + u32 TimeStamp; + u8 GPIOStatus; + u8 UARTStatus; + u8 RXCharacter; + u8 EventStatus; + u32 Reserved[2]; +} __attribute__ ((__packed__)); + +typedef struct EVENT_BUFFER *PEVENT_BUFFER; + +/* Firmware commands. */ + +enum OPCODES { + CMD_NOP = 0, + CMD_FWLOAD_PREPARE = 0x01, + CMD_FWLOAD_FINISH = 0x02, + CMD_I2C_READ = 0x03, + CMD_I2C_WRITE = 0x04, + + CMD_I2C_WRITE_NOSTOP = 0x05, + CMD_I2C_CONTINUE_WRITE = 0x06, + CMD_I2C_CONTINUE_WRITE_NOSTOP = 0x07, + + CMD_DEBUG_OUTPUT = 0x09, + + CMD_CONTROL = 0x10, + CMD_CONFIGURE_BUFFER = 0x11, + CMD_CONFIGURE_FREE_BUFFER = 0x12, + + CMD_SPI_READ = 0x13, + CMD_SPI_WRITE = 0x14, + + CMD_MEM_READ = 0x20, + CMD_MEM_WRITE = 0x21, + CMD_SFR_READ = 0x22, + CMD_SFR_WRITE = 0x23, + CMD_IRAM_READ = 0x24, + CMD_IRAM_WRITE = 0x25, + CMD_SET_GPIO_PIN = 0x26, + CMD_SET_GPIO_INT = 0x27, + CMD_CONFIGURE_UART = 0x28, + CMD_WRITE_UART = 0x29, + MAX_CMD +}; + +enum RESPONSES { + OK = 0, + ERROR = 1 +}; + +struct FW_HEADER { + u8 Opcode; + u8 Length; +} __attribute__ ((__packed__)); + +struct FW_I2C_WRITE { + struct FW_HEADER hdr; + u8 Device; + u8 Data[250]; +} __attribute__ ((__packed__)); + +struct FW_I2C_CONTINUE_WRITE { + struct FW_HEADER hdr; + u8 Data[250]; +} __attribute__ ((__packed__)); + +struct FW_I2C_READ { + struct FW_HEADER hdr; + u8 Device; + u8 Data[252]; /* followed by two bytes of read data count */ +} __attribute__ ((__packed__)); + +struct FW_SPI_WRITE { + struct FW_HEADER hdr; + u8 ModeSelect; + u8 Data[250]; +} __attribute__ ((__packed__)); + +struct FW_SPI_READ { + struct FW_HEADER hdr; + u8 ModeSelect; + u8 Data[252]; /* followed by two bytes of read data count */ +} __attribute__ ((__packed__)); + +struct FW_FWLOAD_PREPARE { + struct FW_HEADER hdr; +} __attribute__ ((__packed__)); + +struct FW_FWLOAD_FINISH { + struct FW_HEADER hdr; + u16 Address; /* address of final block */ + u16 Length; +} __attribute__ ((__packed__)); + +/* + * Meaning of FW_STREAM_CONTROL::Mode bits: + * Bit 7: Loopback PEXin to PEXout using TVOut channel + * Bit 6: AVLOOP + * Bit 5: Audio select; 0=I2S, 1=SPDIF + * Bit 4: AVSYNC + * Bit 3: Enable transport stream + * Bit 2: Enable audio capture + * Bit 1: Enable ITU-Video VBI capture + * Bit 0: Enable ITU-Video capture + * + * Meaning of FW_STREAM_CONTROL::Control bits (see UVI1_CTL) + * Bit 7: continuous capture + * Bit 6: capture one field + * Bit 5: capture one frame + * Bit 4: unused + * Bit 3: starting field; 0=odd, 1=even + * Bit 2: sample size; 0=8-bit, 1=10-bit + * Bit 1: data format; 0=UYVY, 1=YUY2 + * Bit 0: resets buffer pointers +*/ + +enum FSC_MODE_BITS { + SMODE_LOOPBACK = 0x80, + SMODE_AVLOOP = 0x40, + _SMODE_AUDIO_SPDIF = 0x20, + _SMODE_AVSYNC = 0x10, + _SMODE_TRANSPORT_STREAM = 0x08, + _SMODE_AUDIO_CAPTURE = 0x04, + _SMODE_VBI_CAPTURE = 0x02, + _SMODE_VIDEO_CAPTURE = 0x01 +}; + + +/* Meaning of FW_STREAM_CONTROL::Stream bits: + * Bit 3: Audio sample count: 0 = relative, 1 = absolute + * Bit 2: color bar select; 1=color bars, 0=CV3 decoder + * Bits 1-0: stream select, UVI1, UVI2, TVOUT + */ + +struct FW_STREAM_CONTROL { + struct FW_HEADER hdr; + u8 Stream; /* Stream number (UVI1, UVI2, TVOUT) */ + u8 Control; /* Value written to UVI1_CTL */ + u8 Mode; /* Controls clock source */ + u8 SetupDataLen; /* Length of setup data, MSB=1 write + backwards */ + u16 CaptureBlockCount; /* Blocks (a 256 Bytes) to capture per buffer + for TS and Audio */ + u64 Buffer_Address; /* Address of first buffer header */ + u16 BytesPerVideoLine; + u16 MaxLinesPerField; + u16 MinLinesPerField; + u16 Reserved_1; + u16 BytesPerVBILine; + u16 MaxVBILinesPerField; + u16 MinVBILinesPerField; + u16 SetupDataAddr; /* ngene relative address of setup data */ + u8 SetupData[32]; /* setup data */ +} __attribute__((__packed__)); + +#define AUDIO_BLOCK_SIZE 256 +#define TS_BLOCK_SIZE 256 + +struct FW_MEM_READ { + struct FW_HEADER hdr; + u16 address; +} __attribute__ ((__packed__)); + +struct FW_MEM_WRITE { + struct FW_HEADER hdr; + u16 address; + u8 data; +} __attribute__ ((__packed__)); + +struct FW_SFR_IRAM_READ { + struct FW_HEADER hdr; + u8 address; +} __attribute__ ((__packed__)); + +struct FW_SFR_IRAM_WRITE { + struct FW_HEADER hdr; + u8 address; + u8 data; +} __attribute__ ((__packed__)); + +struct FW_SET_GPIO_PIN { + struct FW_HEADER hdr; + u8 select; +} __attribute__ ((__packed__)); + +struct FW_SET_GPIO_INT { + struct FW_HEADER hdr; + u8 select; +} __attribute__ ((__packed__)); + +struct FW_SET_DEBUGMODE { + struct FW_HEADER hdr; + u8 debug_flags; +} __attribute__ ((__packed__)); + +struct FW_CONFIGURE_BUFFERS { + struct FW_HEADER hdr; + u8 config; +} __attribute__ ((__packed__)); + +enum _BUFFER_CONFIGS { + /* 4k UVI1, 4k UVI2, 2k AUD1, 2k AUD2 (standard usage) */ + BUFFER_CONFIG_4422 = 0, + /* 3k UVI1, 3k UVI2, 3k AUD1, 3k AUD2 (4x TS input usage) */ + BUFFER_CONFIG_3333 = 1, + /* 8k UVI1, 0k UVI2, 2k AUD1, 2k I2SOut (HDTV decoder usage) */ + BUFFER_CONFIG_8022 = 2, + BUFFER_CONFIG_FW17 = 255, /* Use new FW 17 command */ +}; + +struct FW_CONFIGURE_FREE_BUFFERS { + struct FW_HEADER hdr; + u8 UVI1_BufferLength; + u8 UVI2_BufferLength; + u8 TVO_BufferLength; + u8 AUD1_BufferLength; + u8 AUD2_BufferLength; + u8 TVA_BufferLength; +} __attribute__ ((__packed__)); + +struct FW_CONFIGURE_UART { + struct FW_HEADER hdr; + u8 UartControl; +} __attribute__ ((__packed__)); + +enum _UART_CONFIG { + _UART_BAUDRATE_19200 = 0, + _UART_BAUDRATE_9600 = 1, + _UART_BAUDRATE_4800 = 2, + _UART_BAUDRATE_2400 = 3, + _UART_RX_ENABLE = 0x40, + _UART_TX_ENABLE = 0x80, +}; + +struct FW_WRITE_UART { + struct FW_HEADER hdr; + u8 Data[252]; +} __attribute__ ((__packed__)); + + +struct ngene_command { + u32 in_len; + u32 out_len; + union { + u32 raw[64]; + u8 raw8[256]; + struct FW_HEADER hdr; + struct FW_I2C_WRITE I2CWrite; + struct FW_I2C_CONTINUE_WRITE I2CContinueWrite; + struct FW_I2C_READ I2CRead; + struct FW_STREAM_CONTROL StreamControl; + struct FW_FWLOAD_PREPARE FWLoadPrepare; + struct FW_FWLOAD_FINISH FWLoadFinish; + struct FW_MEM_READ MemoryRead; + struct FW_MEM_WRITE MemoryWrite; + struct FW_SFR_IRAM_READ SfrIramRead; + struct FW_SFR_IRAM_WRITE SfrIramWrite; + struct FW_SPI_WRITE SPIWrite; + struct FW_SPI_READ SPIRead; + struct FW_SET_GPIO_PIN SetGpioPin; + struct FW_SET_GPIO_INT SetGpioInt; + struct FW_SET_DEBUGMODE SetDebugMode; + struct FW_CONFIGURE_BUFFERS ConfigureBuffers; + struct FW_CONFIGURE_FREE_BUFFERS ConfigureFreeBuffers; + struct FW_CONFIGURE_UART ConfigureUart; + struct FW_WRITE_UART WriteUart; + } cmd; +} __attribute__ ((__packed__)); + +#define NGENE_INTERFACE_VERSION 0x103 +#define MAX_VIDEO_BUFFER_SIZE (417792) /* 288*1440 rounded up to next page */ +#define MAX_AUDIO_BUFFER_SIZE (8192) /* Gives room for about 23msec@48KHz */ +#define MAX_VBI_BUFFER_SIZE (28672) /* 1144*18 rounded up to next page */ +#define MAX_TS_BUFFER_SIZE (98304) /* 512*188 rounded up to next page */ +#define MAX_HDTV_BUFFER_SIZE (2080768) /* 541*1920*2 rounded up to next page + Max: (1920x1080i60) */ + +#define OVERFLOW_BUFFER_SIZE (8192) + +#define RING_SIZE_VIDEO 4 +#define RING_SIZE_AUDIO 8 +#define RING_SIZE_TS 8 + +#define NUM_SCATTER_GATHER_ENTRIES 8 + +#define MAX_DMA_LENGTH (((MAX_VIDEO_BUFFER_SIZE + MAX_VBI_BUFFER_SIZE) * \ + RING_SIZE_VIDEO * 2) + \ + (MAX_AUDIO_BUFFER_SIZE * RING_SIZE_AUDIO * 2) + \ + (MAX_TS_BUFFER_SIZE * RING_SIZE_TS * 4) + \ + (RING_SIZE_VIDEO * PAGE_SIZE * 2) + \ + (RING_SIZE_AUDIO * PAGE_SIZE * 2) + \ + (RING_SIZE_TS * PAGE_SIZE * 4) + \ + 8 * PAGE_SIZE + OVERFLOW_BUFFER_SIZE + PAGE_SIZE) + +#define EVENT_QUEUE_SIZE 16 + +typedef struct HW_SCATTER_GATHER_ELEMENT *PHW_SCATTER_GATHER_ELEMENT; +typedef struct FWRB *PFWRB; + +/* Gathers the current state of a single channel. */ + +struct SBufferHeader { + struct BUFFER_HEADER ngeneBuffer; /* Physical descriptor */ + struct SBufferHeader *Next; + void *Buffer1; + PHW_SCATTER_GATHER_ELEMENT scList1; + void *Buffer2; + PHW_SCATTER_GATHER_ELEMENT scList2; +}; + +/* Sizeof SBufferHeader aligned to next 64 Bit boundary (hw restriction) */ +#define SIZEOF_SBufferHeader ((sizeof(struct SBufferHeader) + 63) & ~63) + +enum HWSTATE { + HWSTATE_STOP, + HWSTATE_STARTUP, + HWSTATE_RUN, + HWSTATE_PAUSE, +}; + +enum KSSTATE { + KSSTATE_STOP, + KSSTATE_ACQUIRE, + KSSTATE_PAUSE, + KSSTATE_RUN, +}; + +struct SRingBufferDescriptor { + struct SBufferHeader *Head; /* Points to first buffer in ring buffer + structure*/ + u64 PAHead; /* Physical address of first buffer */ + u32 MemSize; /* Memory size of allocated ring buffers + (needed for freeing) */ + u32 NumBuffers; /* Number of buffers in the ring */ + u32 Buffer1Length; /* Allocated length of Buffer 1 */ + u32 Buffer2Length; /* Allocated length of Buffer 2 */ + void *SCListMem; /* Memory to hold scatter gather lists for this + ring */ + u64 PASCListMem; /* Physical address .. */ + u32 SCListMemSize; /* Size of this memory */ +}; + +enum STREAMMODEFLAGS { + StreamMode_NONE = 0, /* Stream not used */ + StreamMode_ANALOG = 1, /* Analog: Stream 0,1 = Video, 2,3 = Audio */ + StreamMode_TSIN = 2, /* Transport stream input (all) */ + StreamMode_HDTV = 4, /* HDTV: Maximum 1920x1080p30,1920x1080i60 + (only stream 0) */ + StreamMode_TSOUT = 8, /* Transport stream output (only stream 3) */ +}; + + +enum BufferExchangeFlags { + BEF_EVEN_FIELD = 0x00000001, + BEF_CONTINUATION = 0x00000002, + BEF_MORE_DATA = 0x00000004, + BEF_OVERFLOW = 0x00000008, + DF_SWAP32 = 0x00010000, +}; + +typedef void *(IBufferExchange)(void *, void *, u32, u32, u32); + +typedef struct { + IBufferExchange *pExchange; + IBufferExchange *pExchangeVBI; /* Secondary (VBI, ancillary) */ + u8 Stream; + u8 Flags; + u8 Mode; + u8 Reserved; + u16 nLinesVideo; + u16 nBytesPerLineVideo; + u16 nLinesVBI; + u16 nBytesPerLineVBI; + u32 CaptureLength; /* Used for audio and transport stream */ +} MICI_STREAMINFO, *PMICI_STREAMINFO; + +/****************************************************************************/ +/* STRUCTS ******************************************************************/ +/****************************************************************************/ + +/* sound hardware definition */ +#define MIXER_ADDR_TVTUNER 0 +#define MIXER_ADDR_LAST 0 + +struct ngene_channel; + +/*struct sound chip*/ + +struct mychip { + struct ngene_channel *chan; + struct snd_card *card; + struct pci_dev *pci; + struct snd_pcm_substream *substream; + struct snd_pcm *pcm; + unsigned long port; + int irq; + spinlock_t mixer_lock; + spinlock_t lock; + int mixer_volume[MIXER_ADDR_LAST + 1][2]; + int capture_source[MIXER_ADDR_LAST + 1][2]; +}; + +#ifdef NGENE_V4L +struct ngene_overlay { + int tvnorm; + struct v4l2_rect w; + enum v4l2_field field; + struct v4l2_clip *clips; + int nclips; + int setup_ok; +}; + +struct ngene_tvnorm { + int v4l2_id; + char *name; + u16 swidth, sheight; /* scaled standard width, height */ + int tuner_norm; + int soundstd; +}; + +struct ngene_vopen { + struct ngene_channel *ch; + enum v4l2_priority prio; + int width; + int height; + int depth; + struct videobuf_queue vbuf_q; + struct videobuf_queue vbi; + int fourcc; + int picxcount; + int resources; + enum v4l2_buf_type type; + const struct ngene_format *fmt; + + const struct ngene_format *ovfmt; + struct ngene_overlay ov; +}; +#endif + +struct ngene_channel { + struct device device; + struct i2c_adapter i2c_adapter; + + struct ngene *dev; + int number; + int type; + int mode; + + struct dvb_frontend *fe; + struct dmxdev dmxdev; + struct dvb_demux demux; + struct dmx_frontend hw_frontend; + struct dmx_frontend mem_frontend; + int users; + struct video_device *v4l_dev; +#ifndef ONE_ADAPTER + struct dvb_adapter dvb_adapter; +#endif + struct dvb_device *command_dev; + struct dvb_device *audio_dev; + struct dvb_device *video_dev; + struct tasklet_struct demux_tasklet; + + struct SBufferHeader *nextBuffer; + enum KSSTATE State; + enum HWSTATE HWState; + u8 Stream; + u8 Flags; + u8 Mode; + IBufferExchange *pBufferExchange; + IBufferExchange *pBufferExchange2; + + spinlock_t state_lock; + u16 nLines; + u16 nBytesPerLine; + u16 nVBILines; + u16 nBytesPerVBILine; + u16 itumode; + u32 Capture1Length; + u32 Capture2Length; + struct SRingBufferDescriptor RingBuffer; + struct SRingBufferDescriptor TSRingBuffer; + struct SRingBufferDescriptor TSIdleBuffer; + + u32 DataFormatFlags; + + int AudioDTOUpdated; + u32 AudioDTOValue; + + int (*set_tone)(struct dvb_frontend *, fe_sec_tone_mode_t); + u8 lnbh; + + /* stuff from analog driver */ + + int minor; + struct mychip *mychip; + struct snd_card *soundcard; + u8 *evenbuffer; + u8 *soundbuffer; + u8 dma_on; + int soundstreamon; + int audiomute; + int soundbuffisallocated; + int sndbuffflag; + int tun_rdy; + int dec_rdy; + int tun_dec_rdy; + int lastbufferflag; + + struct ngene_tvnorm *tvnorms; + int tvnorm_num; + int tvnorm; + +#ifdef NGENE_V4L + int videousers; + struct v4l2_prio_state prio; + struct ngene_vopen init; + int resources; + struct v4l2_framebuffer fbuf; + struct ngene_buffer *screen; /* overlay */ + struct list_head capture; /* video capture queue */ + spinlock_t s_lock; + struct semaphore reslock; +#endif + + int running; +}; + +struct ngene; + +typedef void (rx_cb_t)(struct ngene *, u32, u8); +typedef void (tx_cb_t)(struct ngene *, u32); + +struct ngene { + int nr; + struct pci_dev *pci_dev; + unsigned char *iomem; + +#ifdef ONE_ADAPTER + struct dvb_adapter dvb_adapter; +#endif + /*struct i2c_adapter i2c_adapter;*/ + + u32 device_version; + u32 fw_interface_version; + u32 icounts; + + u8 *CmdDoneByte; + int BootFirmware; + void *OverflowBuffer; + dma_addr_t PAOverflowBuffer; + void *FWInterfaceBuffer; + dma_addr_t PAFWInterfaceBuffer; + u8 *ngenetohost; + u8 *hosttongene; + + struct EVENT_BUFFER EventQueue[EVENT_QUEUE_SIZE]; + int EventQueueOverflowCount; + int EventQueueOverflowFlag; + struct tasklet_struct event_tasklet; + struct EVENT_BUFFER *EventBuffer; + int EventQueueWriteIndex; + int EventQueueReadIndex; + + wait_queue_head_t cmd_wq; + int cmd_done; + struct semaphore cmd_mutex; + struct semaphore stream_mutex; + struct semaphore pll_mutex; + struct semaphore i2c_switch_mutex; + int i2c_current_channel; + int i2c_current_bus; + spinlock_t cmd_lock; + + struct ngene_channel channel[MAX_STREAM]; + + struct ngene_info *card_info; + + tx_cb_t *TxEventNotify; + rx_cb_t *RxEventNotify; + int tx_busy; + wait_queue_head_t tx_wq; + wait_queue_head_t rx_wq; +#define UART_RBUF_LEN 4096 + u8 uart_rbuf[UART_RBUF_LEN]; + int uart_rp, uart_wp; + + u8 *tsout_buf; +#define TSOUT_BUF_SIZE (512*188*8) + struct dvb_ringbuffer tsout_rbuf; + + u8 *ain_buf; +#define AIN_BUF_SIZE (128*1024) + struct dvb_ringbuffer ain_rbuf; + + + u8 *vin_buf; +#define VIN_BUF_SIZE (4*1920*1080) + struct dvb_ringbuffer vin_rbuf; + + unsigned long exp_val; + int prev_cmd; +}; + +struct channel_info { + int io_type; +#define NGENE_IO_NONE 0 +#define NGENE_IO_TV 1 +#define NGENE_IO_HDTV 2 +#define NGENE_IO_TSIN 4 +#define NGENE_IO_TSOUT 8 +#define NGENE_IO_AIN 16 + + void *fe_config; + void *tuner_config; + + int (*demod_attach)(struct ngene_channel *); + int demod_type; +#define NGENE_DEMOD_NONE 0 +#define NGENE_DEMOD_DRXD 1 +#define NGENE_DEMOD_STB0899 2 +#define NGENE_DEMOD_DRXH 3 + + int (*tuner_attach)(struct ngene_channel *); + int tuner_type; +#define NGENE_TUNER_NONE 0 +#define NGENE_TUNER_MT2060 1 + + u8 demod; + u8 tuner; + u8 lnb; + u8 demoda; + u8 avf; + u8 msp; +}; + +struct ngene_info { + int type; +#define NGENE_APP 0 +#define NGENE_TERRATEC 1 +#define NGENE_SIDEWINDER 2 +#define NGENE_RACER 3 +#define NGENE_VIPER 4 +#define NGENE_PYTHON 5 +#define NGENE_VBOX_V1 6 +#define NGENE_VBOX_V2 7 + + int fw_version; + char *name; + + int io_type[MAX_STREAM]; +#define NGENE_IO_NONE 0 +#define NGENE_IO_TV 1 +#define NGENE_IO_HDTV 2 +#define NGENE_IO_TSIN 4 +#define NGENE_IO_TSOUT 8 +#define NGENE_IO_AIN 16 + + void *fe_config[4]; + void *tuner_config[4]; + + int (*demod_attach[4])(struct ngene_channel *); + int (*tuner_attach[4])(struct ngene_channel *); + + u8 avf[4]; + u8 msp[4]; + u8 demoda[4]; + u8 lnb[4]; + int i2c_access; + u8 ntsc; + u8 exp; + u8 exp_init; + u8 tsf[4]; + u8 i2s[4]; + + int (*gate_ctrl)(struct dvb_frontend *, int); + int (*switch_ctrl)(struct ngene_channel *, int, int); +}; + +#ifdef NGENE_V4L +struct ngene_format{ + char *name; + int fourcc; /* video4linux 2 */ + int btformat; /* BT848_COLOR_FMT_* */ + int format; + int btswap; /* BT848_COLOR_CTL_* */ + int depth; /* bit/pixel */ + int flags; + int hshift, vshift; /* for planar modes */ + int palette; +}; + +#define RESOURCE_OVERLAY 1 +#define RESOURCE_VIDEO 2 +#define RESOURCE_VBI 4 + +struct ngene_buffer { + /* common v4l buffer stuff -- must be first */ + struct videobuf_buffer vb; + + /* ngene specific */ + const struct ngene_format *fmt; + int tvnorm; + int btformat; + int btswap; +}; +#endif + +int ngene_command_stream_control(struct ngene *dev, + u8 stream, u8 control, u8 mode, u8 flags); +int ngene_command_nop(struct ngene *dev); +int ngene_command_i2c_read(struct ngene *dev, u8 adr, + u8 *out, u8 outlen, u8 *in, u8 inlen, int flag); +int ngene_command_i2c_write(struct ngene *dev, u8 adr, u8 *out, u8 outlen); +int ngene_command_imem_read(struct ngene *dev, u8 adr, u8 *data, int type); +int ngene_command_imem_write(struct ngene *dev, u8 adr, u8 data, int type); +int ngene_stream_control(struct ngene *dev, u8 stream, u8 control, u8 mode, + u16 lines, u16 bpl, u16 vblines, u16 vbibpl); +int ngene_v4l2_init(struct ngene_channel *chan); +void ngene_v4l2_remove(struct ngene_channel *chan); +int ngene_snd_exit(struct ngene_channel *chan); +int ngene_snd_init(struct ngene_channel *chan); + +struct i2c_client *avf4910a_attach(struct i2c_adapter *adap, int addr); + +#endif + +/* LocalWords: Endif + */ |