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| author | Alexander Sverdlin <alexander.sverdlin@nokia.com> | 2015-06-11 11:35:26 +0200 |
|---|---|---|
| committer | Wolfram Sang <wsa@the-dreams.de> | 2015-06-17 14:40:58 +0200 |
| commit | 955fc950795d1c9f11f220f449ecb29b92985ee2 (patch) | |
| tree | 3481aae74b60bf152ca42066166c8e79ae31b38d /virt/kvm/coalesced_mmio.c | |
| parent | 0a8237ae319ab5988d40a7a9b33d68846aae34b4 (diff) | |
| download | linux-955fc950795d1c9f11f220f449ecb29b92985ee2.tar.bz2 | |
i2c: davinci: Optimize SCL generation
There are several cases where current clock configuration algorithm produces
not optimal results:
- truncation in "clk" calculation leads to the fact that actual BUS frequency
will be always higher than spec except two exact module frequences 8MHz and
12MHz in the whole 7-12MHz range of permitted frequences
- driver configures SCL HIGH to LOW ratio always 1 to 1 and this doesn't work
well in 400kHz case, namely minimum time of LOW state (according to I2C Spec
2.1) 1.3us will not be fulfilled. HIGH to LOW ratio 1 to 2 would be more
approriate here.
Signed-off-by: Michael Lawnick <michael.lawnick@nokia.com>
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'virt/kvm/coalesced_mmio.c')
0 files changed, 0 insertions, 0 deletions