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authorKevin Cernekee <cernekee@gmail.com>2010-10-20 20:05:42 -0700
committerRalf Baechle <ralf@linux-mips.org>2010-10-29 19:08:52 +0100
commitea31a6b203710c03d1fc025377a19572e620588a (patch)
treeb9a39c79e7080b9790936618a704439d057cb78a /usr
parentaf231172634b5c0923fa7484a043fadcc07e899e (diff)
downloadlinux-ea31a6b203710c03d1fc025377a19572e620588a.tar.bz2
MIPS: Honor L2 bypass bit
On many of the newer MIPS32 cores, CP0 CONFIG2 bit 12 (L2B) indicates that the L2 cache is disabled and therefore Linux should not attempt to use it. [Ralf: Moved the code added by Kevin's original patch into a separate function that can easily be replaced for platforms that need more a different probe.] Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org> Cc: <linux-kernel@vger.kernel.org> Patchwork: https://patchwork.linux-mips.org/patch/1723/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'usr')
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