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| author | Zhuang Jin Can <jin.can.zhuang@intel.com> | 2014-05-16 05:57:57 +0800 |
|---|---|---|
| committer | Felipe Balbi <balbi@ti.com> | 2014-06-19 08:51:07 -0500 |
| commit | 5cd8c48d95c10f729090c89757727e090719fd83 (patch) | |
| tree | b413d6182b8ac1892bd9f8f4a4f941b7c2964175 /tools/usb | |
| parent | 7171511eaec5bf23fb06078f59784a3a0626b38f (diff) | |
| download | linux-5cd8c48d95c10f729090c89757727e090719fd83.tar.bz2 | |
usb: dwc3: gadget: check link trb after free_slot is increased
In ISOC transfers, when free_slot points to the last TRB (i.e. Link
TRB), and all queued requests meet Missed Interval Isoc error, busy_slot
points to trb0.
busy_slot->trb0
trb1
...
free_slot->trb31(Link TRB)
After end transfer and receiving the XferNotReady event, trb_left is
caculated as 1 which is wrong, and no TRB will be primed to the
endpoint.
The root cause is free_slot is not increased the same way as busy_slot.
When busy_slot is increased by one, it checks if points to a link TRB
after increasement, but free_slot checks it before increasement.
free_slot should behave the same as busy_slot to make the trb_left
caculation correct.
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Zhuang Jin Can <jin.can.zhuang@intel.com>
Signed-off-by: Jiebing Li <jiebing.li@intel.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'tools/usb')
0 files changed, 0 insertions, 0 deletions