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authorLinus Torvalds <torvalds@linux-foundation.org>2020-12-20 11:21:06 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2020-12-20 11:21:06 -0800
commit48342fc07272eec454fc5b400ed3ce3739c7e950 (patch)
tree29a2f05d5122091b35c131c082d6a43e87ad5f0a /tools/perf/tests/pmu-events.c
parent6a447b0e3151893f6d4a889956553c06d2e775c6 (diff)
parent2e7f545096f954a9726c9415763dd0bfbcac47e0 (diff)
downloadlinux-48342fc07272eec454fc5b400ed3ce3739c7e950.tar.bz2
Merge tag 'perf-tools-2020-12-19' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux
Pull perf tools updates from Arnaldo Carvalho de Melo: "perf record: - Fix memory leak when using '--user-regs=?' to list registers aarch64 support: - Add aarch64 registers to 'perf record's' --user-regs command line option aarch64 hw tracing support: - Decode memory tagging properties - Improve ARM's auxtrace support - Add support for ARMv8.3-SPE perf kvm: - Add kvm-stat for arm64 perf stat: - Add --quiet option Cleanups: - Fixup function names wrt what is in libperf and what is in tools/perf Build: - Allow building without libbpf in older systems New kernel features: - Initial support for data/code page size sample type, more to come perf annotate: - Support MIPS instruction extended support perf stack unwinding: - Fix separate debug info files when using elfutils' libdw's unwinder perf vendor events: - Update Intel's Skylake client events to v50 - Add JSON metrics for ARM's imx8mm DDR Perf - Support printing metric groups for system PMUs perf build id: - Prep work for supporting having the build id provided by the kernel in PERF_RECORD_MMAP2 metadata events perf stat: - Support regex pattern in --for-each-cgroup pipe mode: - Allow to use stdio functions for pipe mode - Support 'perf report's' --header-only for pipe mode - Support pipe mode display in 'perf evlist' Documentation: - Update information about CAP_PERFMON" * tag 'perf-tools-2020-12-19' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux: (134 commits) perf mem: Factor out a function to generate sort order perf sort: Add sort option for data page size perf script: Support data page size tools headers UAPI: Update asm-generic/unistd.h tools headers cpufeatures: Sync with the kernel sources tools headers UAPI: Sync linux/prctl.h with the kernel sources tools headers UAPI: Sync linux/fscrypt.h with the kernel sources tools headers UAPI: Sync linux/const.h with the kernel headers tools arch x86: Sync the msr-index.h copy with the kernel sources perf trace beauty: Update copy of linux/socket.h with the kernel sources tools headers: Update linux/ctype.h with the kernel sources tools headers: Add conditional __has_builtin() tools headers: Get tools's linux/compiler.h closer to the kernel's tools headers UAPI: Sync linux/stat.h with the kernel sources tools headers: Syncronize linux/build_bug.h with the kernel sources perf tools: Reformat record's control fd man text perf config: Fix example command in manpage to conform to syntax specified in the SYNOPSIS section. perf test: Make sample-parsing test aware of PERF_SAMPLE_{CODE,DATA}_PAGE_SIZE perf tools: Add support to read build id from compressed elf perf debug: Add debug_set_file function ...
Diffstat (limited to 'tools/perf/tests/pmu-events.c')
-rw-r--r--tools/perf/tests/pmu-events.c16
1 files changed, 15 insertions, 1 deletions
diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c
index d3517a74d95e..0ca6a5a53523 100644
--- a/tools/perf/tests/pmu-events.c
+++ b/tools/perf/tests/pmu-events.c
@@ -14,8 +14,10 @@
#include "util/parse-events.h"
struct perf_pmu_test_event {
+ /* used for matching against events from generated pmu-events.c */
struct pmu_event event;
+ /* used for matching against event aliases */
/* extra events for aliases */
const char *alias_str;
@@ -78,6 +80,17 @@ static struct perf_pmu_test_event test_cpu_events[] = {
.alias_str = "umask=0,(null)=0x30d40,event=0x3a",
.alias_long_desc = "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
},
+ {
+ .event = {
+ .name = "l3_cache_rd",
+ .event = "event=0x40",
+ .desc = "L3 cache access, read",
+ .long_desc = "Attributable Level 3 cache access, read",
+ .topic = "cache",
+ },
+ .alias_str = "event=0x40",
+ .alias_long_desc = "Attributable Level 3 cache access, read",
+ },
{ /* sentinel */
.event = {
.name = NULL,
@@ -357,6 +370,7 @@ static int __test__pmu_event_aliases(char *pmu_name, int *count)
}
+/* Test that aliases generated are as expected */
static int test_aliases(void)
{
struct perf_pmu *pmu = NULL;
@@ -561,7 +575,7 @@ static int metric_parse_fake(const char *str)
}
}
- if (expr__parse(&result, &ctx, str, 1))
+ if (expr__parse(&result, &ctx, str, 0))
pr_err("expr__parse failed\n");
else
ret = 0;