diff options
| author | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2019-03-12 18:40:06 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2019-03-13 15:04:47 +0000 |
| commit | 2b13bee3884926cba22061efa75bd315e871de24 (patch) | |
| tree | c2d974a907e1e4b4add746f3590c47af5b6ec437 /sound | |
| parent | 54d1cf78b0f4ba348a7c7fb8b7d0708d71b6cc8a (diff) | |
| download | linux-2b13bee3884926cba22061efa75bd315e871de24.tar.bz2 | |
ASoC: samsung: odroid: Fix clock configuration for 44100 sample rate
After commit fbeec965b8d1c ("ASoC: samsung: odroid: Fix 32000 sample rate
handling") the audio root clock frequency is configured improperly for
44100 sample rate. Due to clock rate rounding it's 20070401 Hz instead
of 22579000 Hz. This results in a too low value of the PSR clock divider
in the CPU DAI driver and too fast actual sample rate for fs=44100. E.g.
1 kHz tone has actual 1780 Hz frequency (1 kHz * 20070401/22579000 * 2).
Fix this by increasing the correction passed to clk_set_rate() to take
into account inaccuracy of the EPLL frequency properly.
Fixes: fbeec965b8d1c ("ASoC: samsung: odroid: Fix 32000 sample rate handling")
Reported-by: JaeChul Lee <jcsing.lee@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound')
| -rw-r--r-- | sound/soc/samsung/odroid.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sound/soc/samsung/odroid.c b/sound/soc/samsung/odroid.c index 694512f980fd..1dc54c4206f0 100644 --- a/sound/soc/samsung/odroid.c +++ b/sound/soc/samsung/odroid.c @@ -91,11 +91,11 @@ static int odroid_card_be_hw_params(struct snd_pcm_substream *substream, return ret; /* - * We add 1 to the rclk_freq value in order to avoid too low clock + * We add 2 to the rclk_freq value in order to avoid too low clock * frequency values due to the EPLL output frequency not being exact * multiple of the audio sampling rate. */ - rclk_freq = params_rate(params) * rfs + 1; + rclk_freq = params_rate(params) * rfs + 2; ret = clk_set_rate(priv->sclk_i2s, rclk_freq); if (ret < 0) |