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authorDaniel Mack <daniel@zonque.org>2019-03-20 22:41:56 +0100
committerMark Brown <broonie@kernel.org>2019-03-21 14:46:20 +0000
commitf0f2338a9cfaf71db895fa989ea7234e8a9b471d (patch)
tree462e82a3b2833369f255ff0cd52aaec309526cfe /sound
parentc47255b61129857b74b0d86eaf59335348be05e0 (diff)
downloadlinux-f0f2338a9cfaf71db895fa989ea7234e8a9b471d.tar.bz2
ASoC: cs4270: Set auto-increment bit for register writes
The CS4270 does not by default increment the register address on consecutive writes. During normal operation it doesn't matter as all register accesses are done individually. At resume time after suspend, however, the regcache code gathers the biggest possible block of registers to sync and sends them one on one go. To fix this, set the INCR bit in all cases. Signed-off-by: Daniel Mack <daniel@zonque.org> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound')
-rw-r--r--sound/soc/codecs/cs4270.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/sound/soc/codecs/cs4270.c b/sound/soc/codecs/cs4270.c
index 33d74f163bd7..793a14d58667 100644
--- a/sound/soc/codecs/cs4270.c
+++ b/sound/soc/codecs/cs4270.c
@@ -642,6 +642,7 @@ static const struct regmap_config cs4270_regmap = {
.reg_defaults = cs4270_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(cs4270_reg_defaults),
.cache_type = REGCACHE_RBTREE,
+ .write_flag_mask = CS4270_I2C_INCR,
.readable_reg = cs4270_reg_is_readable,
.volatile_reg = cs4270_reg_is_volatile,