diff options
| author | Oder Chiou <oder_chiou@realtek.com> | 2014-03-28 20:28:27 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2014-04-14 17:27:41 +0100 |
| commit | acf04e639bba2270fd07e161fa984234591ef43b (patch) | |
| tree | ab72a7aa33e0f9608558cd3e9530c2a9a595bd65 /sound/soc | |
| parent | 218a3f963822aca1d38b0175b6454fe53d15c2dd (diff) | |
| download | linux-acf04e639bba2270fd07e161fa984234591ef43b.tar.bz2 | |
ASoC: rt5640: Remove the unused or incorrect setting of clock source
The patch removes the unused or incorrect setting of clock source.
Signed-off-by: Oder Chiou <oder_chiou@realtek.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'sound/soc')
| -rw-r--r-- | sound/soc/codecs/rt5640.c | 8 | ||||
| -rw-r--r-- | sound/soc/codecs/rt5640.h | 2 |
2 files changed, 1 insertions, 9 deletions
diff --git a/sound/soc/codecs/rt5640.c b/sound/soc/codecs/rt5640.c index 19634d0992bc..4c866135e40f 100644 --- a/sound/soc/codecs/rt5640.c +++ b/sound/soc/codecs/rt5640.c @@ -487,7 +487,7 @@ static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, val = snd_soc_read(source->codec, RT5640_GLB_CLK); val &= RT5640_SCLK_SRC_MASK; - if (val == RT5640_SCLK_SRC_PLL1 || val == RT5640_SCLK_SRC_PLL1T) + if (val == RT5640_SCLK_SRC_PLL1) return 1; else return 0; @@ -1694,12 +1694,6 @@ static int rt5640_set_dai_sysclk(struct snd_soc_dai *dai, case RT5640_SCLK_S_PLL1: reg_val |= RT5640_SCLK_SRC_PLL1; break; - case RT5640_SCLK_S_PLL1_TK: - reg_val |= RT5640_SCLK_SRC_PLL1T; - break; - case RT5640_SCLK_S_RCCLK: - reg_val |= RT5640_SCLK_SRC_RCCLK; - break; default: dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id); return -EINVAL; diff --git a/sound/soc/codecs/rt5640.h b/sound/soc/codecs/rt5640.h index 5e8df25a13f3..cbd07b5f8060 100644 --- a/sound/soc/codecs/rt5640.h +++ b/sound/soc/codecs/rt5640.h @@ -976,8 +976,6 @@ #define RT5640_SCLK_SRC_SFT 14 #define RT5640_SCLK_SRC_MCLK (0x0 << 14) #define RT5640_SCLK_SRC_PLL1 (0x1 << 14) -#define RT5640_SCLK_SRC_PLL1T (0x2 << 14) -#define RT5640_SCLK_SRC_RCCLK (0x3 << 14) /* 15MHz */ #define RT5640_PLL1_SRC_MASK (0x3 << 12) #define RT5640_PLL1_SRC_SFT 12 #define RT5640_PLL1_SRC_MCLK (0x0 << 12) |