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authorMarek Szyprowski <m.szyprowski@samsung.com>2016-12-29 12:34:07 +0100
committerMark Brown <broonie@kernel.org>2016-12-31 18:36:31 +0000
commit9b41da80e09128574f09bed8dc5a5fc6f72a8239 (patch)
tree0f6ea99410c1626082c51f03e8b43adf87c53f09 /sound/soc/samsung/i2s.c
parentafa99da863e8e00efd8ce2f8840ed31d50abb889 (diff)
downloadlinux-9b41da80e09128574f09bed8dc5a5fc6f72a8239.tar.bz2
ASoC: samsung: i2s: Provide I2S device for registered clocks
This patch adds pointer to I2S device to clk_register_* functions. This in the future allow clock framework to ensure proper runtime state of the I2S device during all operations on the clocks provided by I2S module. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/samsung/i2s.c')
-rw-r--r--sound/soc/samsung/i2s.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index b2b9ee4a177a..2a5b92c672fb 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -1191,13 +1191,13 @@ static int i2s_register_clock_provider(struct platform_device *pdev)
u32 val = readl(i2s->addr + I2SPSR);
writel(val | PSR_PSREN, i2s->addr + I2SPSR);
- i2s->clk_table[CLK_I2S_RCLK_SRC] = clk_register_mux(NULL,
+ i2s->clk_table[CLK_I2S_RCLK_SRC] = clk_register_mux(dev,
"i2s_rclksrc", p_names, ARRAY_SIZE(p_names),
CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
i2s->addr + I2SMOD, reg_info->rclksrc_off,
1, 0, i2s->lock);
- i2s->clk_table[CLK_I2S_RCLK_PSR] = clk_register_divider(NULL,
+ i2s->clk_table[CLK_I2S_RCLK_PSR] = clk_register_divider(dev,
"i2s_presc", "i2s_rclksrc",
CLK_SET_RATE_PARENT,
i2s->addr + I2SPSR, 8, 6, 0, i2s->lock);
@@ -1208,7 +1208,7 @@ static int i2s_register_clock_provider(struct platform_device *pdev)
of_property_read_string_index(dev->of_node,
"clock-output-names", 0, &clk_name[0]);
- i2s->clk_table[CLK_I2S_CDCLK] = clk_register_gate(NULL, clk_name[0],
+ i2s->clk_table[CLK_I2S_CDCLK] = clk_register_gate(dev, clk_name[0],
p_names[0], CLK_SET_RATE_PARENT,
i2s->addr + I2SMOD, reg_info->cdclkcon_off,
CLK_GATE_SET_TO_DISABLE, i2s->lock);