diff options
| author | Chris Zhong <zyw@rock-chips.com> | 2016-07-18 22:34:34 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2016-07-18 15:38:28 +0100 |
| commit | 46dd2e28a90e48fbf1b7e253933fa3b7242e9b1b (patch) | |
| tree | 4bf92522aeb261947955bd1b6ab2330132f9e1c5 /sound/soc/rockchip | |
| parent | 359d9abdc208c662d8c9ff2966a7c6014124f715 (diff) | |
| download | linux-46dd2e28a90e48fbf1b7e253933fa3b7242e9b1b.tar.bz2 | |
ASoC: rockchip: correct the spdif clk
The spdif mclk should be 128 times of sample rate, and there is a
internal divider, the real rate of spdif mclk is mclk / (div + 1).
Hence, the original driver always get the good frequency for
48000/96000/44100/192000. But for 32000, the mclk is incorrect,
it should be 32000*128, but get 48000*128. Do not use the internal
divider here, just set all mclk to 128 * sample rate directly.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/rockchip')
| -rw-r--r-- | sound/soc/rockchip/rockchip_spdif.c | 17 |
1 files changed, 1 insertions, 16 deletions
diff --git a/sound/soc/rockchip/rockchip_spdif.c b/sound/soc/rockchip/rockchip_spdif.c index 100781e37848..4ca265737eda 100644 --- a/sound/soc/rockchip/rockchip_spdif.c +++ b/sound/soc/rockchip/rockchip_spdif.c @@ -101,21 +101,7 @@ static int rk_spdif_hw_params(struct snd_pcm_substream *substream, int ret; srate = params_rate(params); - switch (srate) { - case 32000: - case 48000: - case 96000: - mclk = 96000 * 128; /* 12288000 hz */ - break; - case 44100: - mclk = 44100 * 256; /* 11289600 hz */ - break; - case 192000: - mclk = 192000 * 128; /* 24576000 hz */ - break; - default: - return -EINVAL; - } + mclk = srate * 128; switch (params_format(params)) { case SNDRV_PCM_FORMAT_S16_LE: @@ -139,7 +125,6 @@ static int rk_spdif_hw_params(struct snd_pcm_substream *substream, return ret; } - val |= SPDIF_CFGR_CLK_DIV(mclk/(srate * 256)); ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR, SPDIF_CFGR_CLK_DIV_MASK | SPDIF_CFGR_HALFWORD_ENABLE | SDPIF_CFGR_VDW_MASK, |