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| author | Govindraj Raja <Govindraj.Raja@imgtec.com> | 2016-03-04 15:28:22 +0000 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2016-03-30 10:57:51 +0200 |
| commit | e9adb336d0bf391be23e820975ca5cd12c31d781 (patch) | |
| tree | a89dff4b5af60c4a915e6f619ea9075239d7d0b9 /security | |
| parent | 0129801be4b87226bf502f18f5a9eabd356d1058 (diff) | |
| download | linux-e9adb336d0bf391be23e820975ca5cd12c31d781.tar.bz2 | |
pinctrl: pistachio: fix mfio84-89 function description and pinmux.
mfio 84 to 89 are described wrongly, fix it to describe
the right pin and add them to right pin-mux group.
The correct order is:
pll1_lock => mips_pll -- MFIO_83
pll2_lock => audio_pll -- MFIO_84
pll3_lock => rpu_v_pll -- MFIO_85
pll4_lock => rpu_l_pll -- MFIO_86
pll5_lock => sys_pll -- MFIO_87
pll6_lock => wifi_pll -- MFIO_88
pll7_lock => bt_pll -- MFIO_89
Cc: linux-gpio@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: James Hartley <James.Hartley@imgtec.com>
Cc: <stable@vger.kernel.org> # v4.2+
Fixes: cefc03e5995e("pinctrl: Add Pistachio SoC pin control driver")
Signed-off-by: Govindraj Raja <Govindraj.Raja@imgtec.com>
Acked-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'security')
0 files changed, 0 insertions, 0 deletions