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authorMarc Zyngier <maz@kernel.org>2019-10-02 10:06:12 +0100
committerCatalin Marinas <catalin.marinas@arm.com>2019-10-15 12:26:09 +0100
commitf226650494c6aa87526d12135b7de8b8c074f3de (patch)
tree1c00f90dac02fdb1240153bab7a9faa8565aa52a /security/yama/yama_lsm.c
parent4f5cafb5cb8471e54afdc9054d973535614f7675 (diff)
downloadlinux-f226650494c6aa87526d12135b7de8b8c074f3de.tar.bz2
arm64: Relax ICC_PMR_EL1 accesses when ICC_CTLR_EL1.PMHE is clear
The GICv3 architecture specification is incredibly misleading when it comes to PMR and the requirement for a DSB. It turns out that this DSB is only required if the CPU interface sends an Upstream Control message to the redistributor in order to update the RD's view of PMR. This message is only sent when ICC_CTLR_EL1.PMHE is set, which isn't the case in Linux. It can still be set from EL3, so some special care is required. But the upshot is that in the (hopefuly large) majority of the cases, we can drop the DSB altogether. This relies on a new static key being set if the boot CPU has PMHE set. The drawback is that this static key has to be exported to modules. Cc: Will Deacon <will@kernel.org> Cc: James Morse <james.morse@arm.com> Cc: Julien Thierry <julien.thierry.kdev@gmail.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'security/yama/yama_lsm.c')
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