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| author | Serge Semin <Sergey.Semin@baikalelectronics.ru> | 2020-07-23 03:58:46 +0300 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2020-07-27 14:30:55 +0530 |
| commit | 585d35451e94b2e1b0bf59ef55d3b4a1c8ab3d77 (patch) | |
| tree | 930cedb9ff20c5a2edc286c0dab36197aa05a9c4 /scripts | |
| parent | e6fe5767961dbdcabbdfcc570993a91eebca4586 (diff) | |
| download | linux-585d35451e94b2e1b0bf59ef55d3b4a1c8ab3d77.tar.bz2 | |
dmaengine: dw: Initialize min and max burst DMA device capability
According to the DW APB DMAC data book the minimum burst transaction
length is 1 and it's true for any version of the controller since
isn't parametrised in the coreAssembler so can't be changed at the
IP-core synthesis stage. The maximum burst transaction can vary from
channel to channel and from controller to controller depending on a
IP-core parameter the system engineer activated during the IP-core
synthesis. Let's initialise both min_burst and max_burst members of the
DMA controller descriptor with extreme values so the DMA clients could
use them to properly optimize the DMA requests. The channels and
controller-specific max_burst length initialization will be introduced
by the follow-up patches.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200723005848.31907-9-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'scripts')
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