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| author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2019-01-04 11:06:47 +0800 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-02-06 14:28:25 +0100 |
| commit | b0dcfb78dc6aec8698ab5900dfdf6aeae0830815 (patch) | |
| tree | 7c5fa38f885fc0ae83c1d8f944a0745f90f45bb1 /scripts/extract_xc3028.pl | |
| parent | bfeffd155283772bbe78c6a05dec7c0128ee500c (diff) | |
| download | linux-b0dcfb78dc6aec8698ab5900dfdf6aeae0830815.tar.bz2 | |
clk: tegra: dfll: registration for multiple SoCs
In a future patch, support for the DFLL in Tegra210 will be introduced.
This requires support for more than 1 set of CVB and CPU max frequency
tables.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'scripts/extract_xc3028.pl')
0 files changed, 0 insertions, 0 deletions