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authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>2017-10-31 21:01:43 +0100
committerJonathan Cameron <Jonathan.Cameron@huawei.com>2017-12-02 11:15:13 +0000
commit7a6b0420d2fe4ce59437bd318826fe468f0d71ae (patch)
treeec9c76dd91f151646a32b5b4252e9f1cb2a06de4 /net/switchdev
parente53111ad5deaef98d8c18a9933ef1f5624c5979d (diff)
downloadlinux-7a6b0420d2fe4ce59437bd318826fe468f0d71ae.tar.bz2
iio: adc: meson-saradc: fix the bit_idx of the adc_en clock
Meson8 and Meson8b SoCs use the the SAR ADC gate clock provided by the MESON_SAR_ADC_REG3 register within the SAR ADC register area. According to the datasheet (and the existing MESON_SAR_ADC_REG3_CLK_EN definition) the gate is on bit 30. The fls() function returns the last set bit, which is "bit index + 1" (fls(MESON_SAR_ADC_REG3_CLK_EN) returns 31). Fix this by switching to __ffs() which returns the first set bit, which is bit 30 in our case. This off by one error results in the ADC not being usable on devices where the bootloader did not enable the clock. Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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